Merge ../linus

[cascardo/linux.git] / include / asm-powerpc / mpic.h

diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index a9f9604..b71e7b3 100644 (file)
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -3,6 +3,7 @@
 #ifdef __KERNEL__
 
 #include <linux/irq.h>
+#include <asm/dcr.h>
 
 /*
  * Global registers
@@ -225,6 +226,23 @@ struct mpic_irq_fixup
 #endif /* CONFIG_MPIC_BROKEN_U3 */
 
 
+enum mpic_reg_type {
+       mpic_access_mmio_le,
+       mpic_access_mmio_be,
+#ifdef CONFIG_PPC_DCR
+       mpic_access_dcr
+#endif
+};
+
+struct mpic_reg_bank {
+       u32 __iomem     *base;
+#ifdef CONFIG_PPC_DCR
+       dcr_host_t      dhost;
+       unsigned int    dbase;
+       unsigned int    doff;
+#endif /* CONFIG_PPC_DCR */
+};
+
 /* The instance data of a given MPIC */
 struct mpic
 {
@@ -264,11 +282,18 @@ struct mpic
        spinlock_t              fixup_lock;
 #endif
 
+       /* Register access method */
+       enum mpic_reg_type      reg_type;
+
        /* The various ioremap'ed bases */
-       volatile u32 __iomem    *gregs;
-       volatile u32 __iomem    *tmregs;
-       volatile u32 __iomem    *cpuregs[MPIC_MAX_CPUS];
-       volatile u32 __iomem    *isus[MPIC_MAX_ISU];
+       struct mpic_reg_bank    gregs;
+       struct mpic_reg_bank    tmregs;
+       struct mpic_reg_bank    cpuregs[MPIC_MAX_CPUS];
+       struct mpic_reg_bank    isus[MPIC_MAX_ISU];
+
+#ifdef CONFIG_PPC_DCR
+       unsigned int            dcr_base;
+#endif
 
 #ifdef CONFIG_MPIC_WEIRD
        /* Pointer to HW info array */
@@ -305,6 +330,8 @@ struct mpic
 #define MPIC_SPV_EOI                   0x00000020
 /* No passthrough disable */
 #define MPIC_NO_PTHROU_DIS             0x00000040
+/* DCR based MPIC */
+#define MPIC_USES_DCR                  0x00000080
 
 /* MPIC HW modification ID */
 #define MPIC_REGSET_MASK               0xf0000000
@@ -337,7 +364,7 @@ struct mpic
  * that is senses[0] correspond to linux irq "irq_offset".
  */
 extern struct mpic *mpic_alloc(struct device_node *node,
-                              unsigned long phys_addr,
+                              phys_addr_t phys_addr,
                               unsigned int flags,
                               unsigned int isu_size,
                               unsigned int irq_count,
@@ -350,7 +377,7 @@ extern struct mpic *mpic_alloc(struct device_node *node,
  * @phys_addr: physical address of the ISU
  */
 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
-                           unsigned long phys_addr);
+                           phys_addr_t phys_addr);
 
 /* Set default sense codes
  *
@@ -409,9 +436,9 @@ extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
 void smp_mpic_message_pass(int target, int msg);
 
 /* Fetch interrupt from a given mpic */
-extern unsigned int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
+extern unsigned int mpic_get_one_irq(struct mpic *mpic);
 /* This one gets to the primary mpic */
-extern unsigned int mpic_get_irq(struct pt_regs *regs);
+extern unsigned int mpic_get_irq(void);
 
 /* Set the EPIC clock ratio */
 void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);