X-Git-Url: http://git.cascardo.info/?a=blobdiff_plain;f=arch%2Ftile%2Finclude%2Fasm%2Fcache.h;h=6160761d5f611319ecd9f838d3f407c934e61ae6;hb=ce61cdc270a5e0dd18057bbf29bd3471abccbda8;hp=a9a529964e07d379b5c5ef1c9019e34498f71bae;hpb=c50e86ce7c2961a41f2f7aa6e4fd6c99229ba205;p=cascardo%2Flinux.git

diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h
index a9a529964e07..6160761d5f61 100644
--- a/arch/tile/include/asm/cache.h
+++ b/arch/tile/include/asm/cache.h
@@ -49,9 +49,16 @@
 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
 
 /*
- * Attribute for data that is kept read/write coherent until the end of
- * initialization, then bumped to read/only incoherent for performance.
+ * Originally we used small TLB pages for kernel data and grouped some
+ * things together as "write once", enforcing the property at the end
+ * of initialization by making those pages read-only and non-coherent.
+ * This allowed better cache utilization since cache inclusion did not
+ * need to be maintained.  However, to do this requires an extra TLB
+ * entry, which on balance is more of a performance hit than the
+ * non-coherence is a performance gain, so we now just make "read
+ * mostly" and "write once" be synonyms.  We keep the attribute
+ * separate in case we change our minds at a future date.
  */
-#define __write_once __attribute__((__section__(".w1data")))
+#define __write_once __read_mostly
 
 #endif /* _ASM_TILE_CACHE_H */