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sparc64: T5 PMU
authorbob picco <bpicco@meloft.net>
Tue, 16 Sep 2014 14:09:06 +0000 (10:09 -0400)
committerDavid S. Miller <davem@davemloft.net>
Wed, 17 Sep 2014 01:26:40 +0000 (18:26 -0700)
commit05aa1651e8b9ca078b1808a2fe7b50703353ec02
tree9a3cb98b69a4f1960c627586975043bcb364c82etree | snapshot
parent7c21d533ab2ffa1e681bdaf4a53ce3046f6e0e17commit | diff
sparc64: T5 PMU

The T5 (niagara5) has different PCR related HV fast trap values and a new
HV API Group. This patch utilizes these and shares when possible with niagara4.

We use the same sparc_pmu niagara4_pmu. Should there be new effort to
obtain the MCU perf statistics then this would have to be changed.

Cc: sparclinux@vger.kernel.org
Signed-off-by: Bob Picco <bob.picco@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
arch/sparc/include/asm/hypervisor.h diff | blob | history
arch/sparc/kernel/hvapi.c diff | blob | history
arch/sparc/kernel/hvcalls.S diff | blob | history
arch/sparc/kernel/pcr.c diff | blob | history
arch/sparc/kernel/perf_event.c diff | blob | history
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