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(parent: 245c027) | patch
serial: tegra: Add delay after enabling FIFO mode
authorJon Hunter <jonathanh@nvidia.com>
Tue, 5 May 2015 14:17:53 +0000 (15:17 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sun, 10 May 2015 17:12:18 +0000 (19:12 +0200)
commit11e71007a5652dce2528a5d2451fe2697c6a370a
tree523bc8985b6aeb782d6787c16c35db250be9a506tree | snapshot
parent245c0278ab2a2e3d0360296710b4c285291469b5commit | diff
serial: tegra: Add delay after enabling FIFO mode

For all tegra devices (up to t210), there is a hardware issue that
requires software to wait for 3 UART clock periods after enabling
the TX fifo, otherwise data could be lost.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/tty/serial/serial-tegra.c diff | blob | history
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