clk: exynos4: Add PPMU IP block source clocks.
authorJonghwa Lee <jonghwa3.lee@samsung.com>
Tue, 27 May 2014 11:27:08 +0000 (20:27 +0900)
committerTomasz Figa <t.figa@samsung.com>
Mon, 30 Jun 2014 13:07:56 +0000 (15:07 +0200)
commit17d3f1d27ce2fd377ddb03531b87dd9e96e01b34
tree5e337db7eaa68d4a17eca7c5ba3aee0b939e9e8f
parentd5e136a21b2028fb1f45143ea7112d5869bfc6c7
clk: exynos4: Add PPMU IP block source clocks.

Exynos4 has saveral PPMUs and each of them has operation clock which
can be gated through CMU's SFR control.

New clocks are listed below. All clocks are added as a gate-typed clock.

CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L,
CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1,
CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU,
CLK_PPMUACP,

Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
drivers/clk/samsung/clk-exynos4.c
include/dt-bindings/clock/exynos4.h