clk: rockchip: switch PLLs to slow mode before reboot for rk3288
authorChris Zhong <zyw@rock-chips.com>
Fri, 27 Nov 2015 02:09:30 +0000 (10:09 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 1 Dec 2015 17:33:43 +0000 (18:33 +0100)
commit1d33929e2a2b69ae6d40e09ccfc8c7d705a543ba
tree294bb65112326a7f83be4236ba35ecda2cfd70fa
parenta2f4c560f18edd2ffe0f15d52ce2be55cff605d2
clk: rockchip: switch PLLs to slow mode before reboot for rk3288

We've been seeing some crashes at reboot test on rk3288-based systems,
which boards have not reset pin connected to NPOR, they reboot by
setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in
a high frequency mode, some IPs might hang during soft reset.
It appears that we can fix the problem by switching to slow mode before
reboot, just like what we did before suspend.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3288.c