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(parent: a18037b) | patch
iommu/arm-smmu: fix programming of SMMU_CBn_TCR for stage 1
authorOlav Haugan <ohaugan@codeaurora.org>
Mon, 4 Aug 2014 18:01:02 +0000 (19:01 +0100)
committerWill Deacon <will.deacon@arm.com>
Mon, 1 Sep 2014 15:48:56 +0000 (16:48 +0100)
commit1fc870c7efa364862c3bc792cfbdb38afea26742
tree1c5719e57b7fccba898486eb622027036ee770a2tree | snapshot
parenta18037b27ebd23edf5edad8bc6ceb72e4bb5716dcommit | diff
iommu/arm-smmu: fix programming of SMMU_CBn_TCR for stage 1

Stage-1 context banks do not have the SMMU_CBn_TCR[SL0] field since it
is only applicable to stage-2 context banks.

This patch ensures that we don't set the reserved TCR bits for stage-1
translations.

Cc: <stable@vger.kernel.org>
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
drivers/iommu/arm-smmu.c diff | blob | history
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