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(parent: 410ade4) | patch
RDMA/cxgb4: Fastreg NSMR fixes
authorSteve Wise <swise@opengridcomputing.com>
Fri, 17 Sep 2010 20:40:15 +0000 (15:40 -0500)
committerRoland Dreier <rolandd@cisco.com>
Tue, 28 Sep 2010 17:53:50 +0000 (10:53 -0700)
commit40dbf6ee381008e471d3c4a332971247b7799744
tree6249fb3fd9cca9e2e42c01a798ef21b4f5a1e328tree | snapshot
parent410ade4c26bdf256fea3246e968a12409eb08763commit | diff
RDMA/cxgb4: Fastreg NSMR fixes

- Remove dsgl support - doesn't work in T4.
- Wrap the immediate PBL as needed when building it in the wr.
- Adjust max pbl depth allowed based on ulptx alignment requirements.
- Bump the slots per SQ to 5 to allow up to 128MB fast registers.
- Advertise fastreg support by default.

Signed-off-by: Steve Wise <swise@opengridcomputing.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
drivers/infiniband/hw/cxgb4/provider.c diff | blob | history
drivers/infiniband/hw/cxgb4/qp.c diff | blob | history
drivers/infiniband/hw/cxgb4/t4.h diff | blob | history
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