powerpc/pseries: Add Gen3 definitions for PCIE link speed
authorKleber Sacilotto de Souza <klebers@linux.vnet.ibm.com>
Fri, 17 Jan 2014 13:56:52 +0000 (11:56 -0200)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Mon, 17 Feb 2014 00:19:35 +0000 (11:19 +1100)
commit49d9684a54d21930372b7fb0d3d7b5617f621706
tree6062f657d789a425af844b02cc315b9715bb5d91
parentb020cc6c03a37c3526fcb1dff274f649257949e0
powerpc/pseries: Add Gen3 definitions for PCIE link speed

Rev3 of the PCI Express Base Specification defines a Supported Link
Speeds Vector where the bit definitions within this field are:

Bit 0 - 2.5 GT/s
Bit 1 - 5.0 GT/s
Bit 2 - 8.0 GT/s

This vector definition is used by the platform firmware to export the
maximum and current link speeds of the PCI bus via the
"ibm,pcie-link-speed-stats" device-tree property.

This patch updates pseries_root_bridge_prepare() to detect Gen3
speed buses (defined by 0x04).

Signed-off-by: Kleber Sacilotto de Souza <klebers@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/platforms/pseries/pci.c