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(parent: c8b62ab) | patch
ARM: tegra: reparent sclk to pll_c_out1
authorStephen Warren <swarren@nvidia.com>
Thu, 12 Apr 2012 20:09:39 +0000 (14:09 -0600)
committerStephen Warren <swarren@nvidia.com>
Wed, 25 Apr 2012 21:22:09 +0000 (15:22 -0600)
commit60f975b98cf41476ba0e156f7523b197b046cf2b
tree1af645f32f8aa377307e18876b4296586c18df95tree | snapshot
parentc8b62ab41f76218efca5e4baa5c22ef52a9fe3a5commit | diff
ARM: tegra: reparent sclk to pll_c_out1

pll_p_out4 needs to be used for other purposes. Reparent sclk so that
it runs from pll_c. Change sclk's rate to 120MHz from 108MHz since this
is the lowest precise rate that can be achieved by dividing the pll_c
rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909...,
600/6=100).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
arch/arm/mach-tegra/common.c diff | blob | history
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