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arm64: dts: r8a7795: Add CA53 L2 cache-controller node
authorGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 30 Sep 2015 13:22:15 +0000 (15:22 +0200)
committerSimon Horman <horms+renesas@verge.net.au>
Wed, 17 Feb 2016 05:53:14 +0000 (14:53 +0900)
commit8e1c3aa30c2c3a5f982da9365a1ef03a3ac7a815
tree55f4980518428c6efe25f24bedb2d2cd9f88b1c5tree | snapshot
parenta528b4bf1a2ecb756aa65548fd5518fe82fb4648commit | diff
arm64: dts: r8a7795: Add CA53 L2 cache-controller node

Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm64/boot/dts/renesas/r8a7795.dtsi diff | blob | history
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