drm/i915: Report enabled slices on Haswell GT3
authorRodrigo Vivi <rodrigo.vivi@gmail.com>
Wed, 28 Aug 2013 19:45:46 +0000 (16:45 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 4 Sep 2013 15:34:51 +0000 (17:34 +0200)
commit9435373ef8870e0a84b6fec0ad89b952bf3097fa
treeb3dc336376cce918843d011068107b2bd73a63c9
parent3e33a8408117088c873ebc4b3ca0e1e440c0b697
drm/i915: Report enabled slices on Haswell GT3

Batchbuffers constructed by userspace can conditionalise their URB
allocations through the use of the MI_SET_PREDICATE command. This
command can read the MI_PREDICATE_RESULT_2 register to see how many
slices are enabled on GT3, and by virtue of the result, scale their
memory allocations to fit enabled memory.

Of course, this only works if the kernel sets the appropriate bit in the
register first.

v2: Better commit subject and message by Chris Wilson.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Credits-to: Yejun Guo <yejun.guo@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_reg.h