ARM: mvebu: fix HW I/O coherency related deadlocks
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Thu, 16 Jun 2016 13:42:25 +0000 (15:42 +0200)
committerGregory CLEMENT <gregory.clement@free-electrons.com>
Thu, 16 Jun 2016 14:43:10 +0000 (16:43 +0200)
commitc5379ba8fccd99d5f99632c789f0393d84a57805
tree03e2cf4a0b3fbf9e716c555b5ae3840d80a0d4f9
parent1a695a905c18548062509178b98bc91e67510864
ARM: mvebu: fix HW I/O coherency related deadlocks

Until now, our understanding for HW I/O coherency to work on the
Cortex-A9 based Marvell SoC was that only the PCIe regions should be
mapped strongly-ordered. However, we were still encountering some
deadlocks, especially when testing the CESA crypto engine. After
checking with the HW designers, it was concluded that all the MMIO
registers should be mapped as strongly ordered for the HW I/O coherency
mechanism to work properly.

This fixes some easy to reproduce deadlocks with the CESA crypto engine
driver (dmcrypt on a sufficiently large disk partition).

Tested-by: Terry Stockert <stockert@inkblotadmirer.me>
Tested-by: Romain Perier <romain.perier@free-electrons.com>
Cc: Terry Stockert <stockert@inkblotadmirer.me>
Cc: Romain Perier <romain.perier@free-electrons.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
arch/arm/mach-mvebu/coherency.c