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(parent: eb662f8) | patch
clk: sunxi: codec clock support
authorEmilio López <emilio@elopez.com.ar>
Fri, 18 Jul 2014 18:49:37 +0000 (15:49 -0300)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Wed, 21 Oct 2015 19:51:28 +0000 (21:51 +0200)
commite2771545f49fbfec874642533058a3423fa29e16
tree13d88512ab374afa387804554ca87de90ff6c1betree | snapshot
parenteb662f854710e6a438789a4b0d1d0cce8c12379dcommit | diff
clk: sunxi: codec clock support

The codec clock on sun4i, sun5i and sun7i is a simple gate with PLL2 as
parent. Add a driver for such a clock.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
drivers/clk/sunxi/Makefile diff | blob | history
drivers/clk/sunxi/clk-a10-codec.c [new file with mode: 0644] blob
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