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ARM: dts: dra7: fix DSS PLL clock mux registers
authorTomi Valkeinen <tomi.valkeinen@ti.com>
Mon, 13 Oct 2014 08:50:41 +0000 (11:50 +0300)
committerTony Lindgren <tony@atomide.com>
Fri, 14 Nov 2014 18:28:33 +0000 (10:28 -0800)
commite671538d5110e913a0a3cd6122d7f70b71fc0728
tree1a21476719ee5c8d2af162574dc0862a8f317890tree | snapshot
parentbe6688350a4470e417aaeca54d162652aab40ac5commit | diff
ARM: dts: dra7: fix DSS PLL clock mux registers

The clock nodes for DSS VIDEO1/2 and HDMI have wrong register addresses.
This patch fixes the addresses so that they point to
CM_CLKSEL_VIDEO1_PLL_SYS, CM_CLKSEL_VIDEO2_PLL_SYS and
CM_CLKSEL_HDMI_PLL_SYS.

Reported-by: Somnath Mukherjee <somnath@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/dra7xx-clocks.dtsi diff | blob | history
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