drm/i915/skl: Fix WaDisableChickenBitTSGBarrierAckForFFSliceCS
authorDamien Lespiau <damien.lespiau@intel.com>
Wed, 6 May 2015 13:36:27 +0000 (14:36 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 8 May 2015 11:03:44 +0000 (13:03 +0200)
commitf1d3d34d1740e13f01411d85f53945596488d4c1
treed87cf731b9e48fe4e094b9281d5d58f7a3d47a3e
parent22e02c0b4bc87c94895b1f4cb25ee705d5687cb1
drm/i915/skl: Fix WaDisableChickenBitTSGBarrierAckForFFSliceCS

Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.

Ville noticed that the write was wrong since FF_SLICE_CS_CHICKEN2 is a
masked register. Re-oops.

A wonder if went through 2 people while having roughly a bug per line...

The problem was introduced in the original patch:

  commit 2caa3b260aa6a3d015352c07d1bce1461825fa6c
  Author: Damien Lespiau <damien.lespiau@intel.com>
  Date:   Mon Feb 9 19:33:20 2015 +0000

      drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS

v2: Also fix the register write (Ville)

Reported-by: Robert Beckett <robert.beckett@intel.com>
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Robert Beckett <robert.beckett@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c