PCI: tegra: Program PADS_REFCLK_CFG* registers with per-SoC values
authorStephen Warren <swarren@nvidia.com>
Mon, 25 Jul 2016 21:02:27 +0000 (16:02 -0500)
committerBjorn Helgaas <bhelgaas@google.com>
Tue, 26 Jul 2016 19:57:15 +0000 (14:57 -0500)
commitf814430c3ec89177f5d530484c4df95c268aedfb
tree570938ba932d4f02d4aa255c51560c9b51e89855
parentcf5d31801278be39bd2cc28a8cf582398e58402a
PCI: tegra: Program PADS_REFCLK_CFG* registers with per-SoC values

The value that should be programmed into the PADS_REFCLK register varies
per SoC.  Fix the Tegra PCIe driver to program the correct values.  Future
SoCs will require different values in cfg0/1, so the two values are stored
separately in the per-SoC data structures.

For reference, the values are all documented in NV bug 1771116 comment 20.
The ASIC team has validated all these values, except for the Tegra20 value
which is simply left unchanged in this patch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Thierry Reding <treding@nvidia.com>
drivers/pci/host/pci-tegra.c