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(parent: 18abd16) | patch
clk: tegra124: Add init data for dsi lp clocks
authorSean Paul <seanpaul@chromium.org>
Wed, 1 Oct 2014 16:40:41 +0000 (12:40 -0400)
committerPeter De Schrijver <pdeschrijver@nvidia.com>
Mon, 2 Feb 2015 13:46:34 +0000 (15:46 +0200)
commitf892f24b37345181b9bc7748ed4a8e927cdb6e06
tree75c2f3ba5b9dde77bc4487dad5ad24f8bc2e941btree | snapshot
parent18abd16376ad88ed3995c63ddae47be78bd56abecommit | diff
clk: tegra124: Add init data for dsi lp clocks

Set the parent of the dsi lp clocks to pll_p and the rate
to 68MHz. The default parent is clk_m and rate is 12MHz, this
is too slow to receive data from the peripheral.

Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz
will suffice.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
drivers/clk/tegra/clk-tegra124.c diff | blob | history
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