- MT2063_REG_LO1CQ_1, /* 0x01: LO1C Queued Byte 1 */
- MT2063_REG_LO1CQ_2, /* 0x02: LO1C Queued Byte 2 */
- MT2063_REG_LO2CQ_1, /* 0x03: LO2C Queued Byte 1 */
- MT2063_REG_LO2CQ_2, /* 0x04: LO2C Queued Byte 2 */
- MT2063_REG_LO2CQ_3, /* 0x05: LO2C Queued Byte 3 */
- MT2063_REG_RSVD_06, /* 0x06: Reserved */
- MT2063_REG_LO_STATUS, /* 0x07: LO Status */
- MT2063_REG_FIFFC, /* 0x08: FIFF Center */
- MT2063_REG_CLEARTUNE, /* 0x09: ClearTune Filter */
- MT2063_REG_ADC_OUT, /* 0x0A: ADC_OUT */
- MT2063_REG_LO1C_1, /* 0x0B: LO1C Byte 1 */
- MT2063_REG_LO1C_2, /* 0x0C: LO1C Byte 2 */
- MT2063_REG_LO2C_1, /* 0x0D: LO2C Byte 1 */
- MT2063_REG_LO2C_2, /* 0x0E: LO2C Byte 2 */
- MT2063_REG_LO2C_3, /* 0x0F: LO2C Byte 3 */
- MT2063_REG_RSVD_10, /* 0x10: Reserved */
- MT2063_REG_PWR_1, /* 0x11: PWR Byte 1 */
- MT2063_REG_PWR_2, /* 0x12: PWR Byte 2 */
- MT2063_REG_TEMP_STATUS, /* 0x13: Temp Status */
- MT2063_REG_XO_STATUS, /* 0x14: Crystal Status */
- MT2063_REG_RF_STATUS, /* 0x15: RF Attn Status */
- MT2063_REG_FIF_STATUS, /* 0x16: FIF Attn Status */
- MT2063_REG_LNA_OV, /* 0x17: LNA Attn Override */
- MT2063_REG_RF_OV, /* 0x18: RF Attn Override */
- MT2063_REG_FIF_OV, /* 0x19: FIF Attn Override */
- MT2063_REG_LNA_TGT, /* 0x1A: Reserved */
- MT2063_REG_PD1_TGT, /* 0x1B: Pwr Det 1 Target */
- MT2063_REG_PD2_TGT, /* 0x1C: Pwr Det 2 Target */
- MT2063_REG_RSVD_1D, /* 0x1D: Reserved */
- MT2063_REG_RSVD_1E, /* 0x1E: Reserved */
- MT2063_REG_RSVD_1F, /* 0x1F: Reserved */
- MT2063_REG_RSVD_20, /* 0x20: Reserved */
- MT2063_REG_BYP_CTRL, /* 0x21: Bypass Control */
- MT2063_REG_RSVD_22, /* 0x22: Reserved */
- MT2063_REG_RSVD_23, /* 0x23: Reserved */
- MT2063_REG_RSVD_24, /* 0x24: Reserved */
- MT2063_REG_RSVD_25, /* 0x25: Reserved */
- MT2063_REG_RSVD_26, /* 0x26: Reserved */
- MT2063_REG_RSVD_27, /* 0x27: Reserved */
- MT2063_REG_FIFF_CTRL, /* 0x28: FIFF Control */
- MT2063_REG_FIFF_OFFSET, /* 0x29: FIFF Offset */
- MT2063_REG_CTUNE_CTRL, /* 0x2A: Reserved */
- MT2063_REG_CTUNE_OV, /* 0x2B: Reserved */
- MT2063_REG_CTRL_2C, /* 0x2C: Reserved */
- MT2063_REG_FIFF_CTRL2, /* 0x2D: Fiff Control */
- MT2063_REG_RSVD_2E, /* 0x2E: Reserved */
- MT2063_REG_DNC_GAIN, /* 0x2F: DNC Control */
- MT2063_REG_VGA_GAIN, /* 0x30: VGA Gain Ctrl */
- MT2063_REG_RSVD_31, /* 0x31: Reserved */
- MT2063_REG_TEMP_SEL, /* 0x32: Temperature Selection */
- MT2063_REG_RSVD_33, /* 0x33: Reserved */
- MT2063_REG_RSVD_34, /* 0x34: Reserved */
- MT2063_REG_RSVD_35, /* 0x35: Reserved */
- MT2063_REG_RSVD_36, /* 0x36: Reserved */
- MT2063_REG_RSVD_37, /* 0x37: Reserved */
- MT2063_REG_RSVD_38, /* 0x38: Reserved */
- MT2063_REG_RSVD_39, /* 0x39: Reserved */
- MT2063_REG_RSVD_3A, /* 0x3A: Reserved */
- MT2063_REG_RSVD_3B, /* 0x3B: Reserved */
- MT2063_REG_RSVD_3C, /* 0x3C: Reserved */
+ MT2063_REG_LO1CQ_1, /* 0x01: LO1C Queued Byte 1 */
+ MT2063_REG_LO1CQ_2, /* 0x02: LO1C Queued Byte 2 */
+ MT2063_REG_LO2CQ_1, /* 0x03: LO2C Queued Byte 1 */
+ MT2063_REG_LO2CQ_2, /* 0x04: LO2C Queued Byte 2 */
+ MT2063_REG_LO2CQ_3, /* 0x05: LO2C Queued Byte 3 */
+ MT2063_REG_RSVD_06, /* 0x06: Reserved */
+ MT2063_REG_LO_STATUS, /* 0x07: LO Status */
+ MT2063_REG_FIFFC, /* 0x08: FIFF Center */
+ MT2063_REG_CLEARTUNE, /* 0x09: ClearTune Filter */
+ MT2063_REG_ADC_OUT, /* 0x0A: ADC_OUT */
+ MT2063_REG_LO1C_1, /* 0x0B: LO1C Byte 1 */
+ MT2063_REG_LO1C_2, /* 0x0C: LO1C Byte 2 */
+ MT2063_REG_LO2C_1, /* 0x0D: LO2C Byte 1 */
+ MT2063_REG_LO2C_2, /* 0x0E: LO2C Byte 2 */
+ MT2063_REG_LO2C_3, /* 0x0F: LO2C Byte 3 */
+ MT2063_REG_RSVD_10, /* 0x10: Reserved */
+ MT2063_REG_PWR_1, /* 0x11: PWR Byte 1 */
+ MT2063_REG_PWR_2, /* 0x12: PWR Byte 2 */
+ MT2063_REG_TEMP_STATUS, /* 0x13: Temp Status */
+ MT2063_REG_XO_STATUS, /* 0x14: Crystal Status */
+ MT2063_REG_RF_STATUS, /* 0x15: RF Attn Status */
+ MT2063_REG_FIF_STATUS, /* 0x16: FIF Attn Status */
+ MT2063_REG_LNA_OV, /* 0x17: LNA Attn Override */
+ MT2063_REG_RF_OV, /* 0x18: RF Attn Override */
+ MT2063_REG_FIF_OV, /* 0x19: FIF Attn Override */
+ MT2063_REG_LNA_TGT, /* 0x1A: Reserved */
+ MT2063_REG_PD1_TGT, /* 0x1B: Pwr Det 1 Target */
+ MT2063_REG_PD2_TGT, /* 0x1C: Pwr Det 2 Target */
+ MT2063_REG_RSVD_1D, /* 0x1D: Reserved */
+ MT2063_REG_RSVD_1E, /* 0x1E: Reserved */
+ MT2063_REG_RSVD_1F, /* 0x1F: Reserved */
+ MT2063_REG_RSVD_20, /* 0x20: Reserved */
+ MT2063_REG_BYP_CTRL, /* 0x21: Bypass Control */
+ MT2063_REG_RSVD_22, /* 0x22: Reserved */
+ MT2063_REG_RSVD_23, /* 0x23: Reserved */
+ MT2063_REG_RSVD_24, /* 0x24: Reserved */
+ MT2063_REG_RSVD_25, /* 0x25: Reserved */
+ MT2063_REG_RSVD_26, /* 0x26: Reserved */
+ MT2063_REG_RSVD_27, /* 0x27: Reserved */
+ MT2063_REG_FIFF_CTRL, /* 0x28: FIFF Control */
+ MT2063_REG_FIFF_OFFSET, /* 0x29: FIFF Offset */
+ MT2063_REG_CTUNE_CTRL, /* 0x2A: Reserved */
+ MT2063_REG_CTUNE_OV, /* 0x2B: Reserved */
+ MT2063_REG_CTRL_2C, /* 0x2C: Reserved */
+ MT2063_REG_FIFF_CTRL2, /* 0x2D: Fiff Control */
+ MT2063_REG_RSVD_2E, /* 0x2E: Reserved */
+ MT2063_REG_DNC_GAIN, /* 0x2F: DNC Control */
+ MT2063_REG_VGA_GAIN, /* 0x30: VGA Gain Ctrl */
+ MT2063_REG_RSVD_31, /* 0x31: Reserved */
+ MT2063_REG_TEMP_SEL, /* 0x32: Temperature Selection */
+ MT2063_REG_RSVD_33, /* 0x33: Reserved */
+ MT2063_REG_RSVD_34, /* 0x34: Reserved */
+ MT2063_REG_RSVD_35, /* 0x35: Reserved */
+ MT2063_REG_RSVD_36, /* 0x36: Reserved */
+ MT2063_REG_RSVD_37, /* 0x37: Reserved */
+ MT2063_REG_RSVD_38, /* 0x38: Reserved */
+ MT2063_REG_RSVD_39, /* 0x39: Reserved */
+ MT2063_REG_RSVD_3A, /* 0x3A: Reserved */
+ MT2063_REG_RSVD_3B, /* 0x3B: Reserved */
+ MT2063_REG_RSVD_3C, /* 0x3C: Reserved */