drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config()

Shared plls won't get assigned until the .compute_clocks() hook gets
called, which happens from the crtc .atomic_check hook. That's too late
as the cdclk computation has already happened. So let's move the DPLL0
VCO computation into intel_dp_compute_config() so that it's done when
the cdclk computation happens. Also only do it for eDP since we only
pick DPLL0 for eDP.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-4-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cccf9bc..8b67e0f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1578,6 +1578,27 @@ found:
                                &pipe_config->dp_m2_n2);
        }
 
+       /*
+        * DPLL0 VCO may need to be adjusted to get the correct
+        * clock for eDP. This will affect cdclk as well.
+        */
+       if (is_edp(intel_dp) &&
+           (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
+               int vco;
+
+               switch (pipe_config->port_clock / 2) {
+               case 108000:
+               case 216000:
+                       vco = 8640;
+                       break;
+               default:
+                       vco = 8100;
+                       break;
+               }
+
+               to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
+       }
+
        if (!HAS_DDI(dev))
                intel_dp_set_clock(encoder, pipe_config);
 

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e99e306..43ba60b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1194,7 +1194,6 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
        struct intel_shared_dpll *pll;
        uint32_t ctrl1, cfgcr1, cfgcr2;
        int clock = crtc_state->port_clock;
-       uint32_t vco = 8100;
 
        /*
         * See comment in intel_dpll_hw_state to understand why we always use 0
@@ -1239,15 +1238,12 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
                        break;
                case 108000:
                        ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
-                       vco = 8640;
                        break;
                case 216000:
                        ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
-                       vco = 8640;
                        break;
                }
 
-               to_intel_atomic_state(crtc_state->base.state)->cdclk_pll_vco = vco;
                cfgcr1 = cfgcr2 = 0;
        } else {
                return NULL;