references.
+16) Sending "git pull" requests (from Linus emails)
+Please write the git repo address and branch name alone on the same line
+so that I can't even by mistake pull from the wrong branch, and so
+that a triple-click just selects the whole thing.
+
+So the proper format is something along the lines of:
+
+ "Please pull from
+
+ git://jdelvare.pck.nerim.net/jdelvare-2.6 i2c-for-linus
+
+ to get these changes:"
+
+so that I don't have to hunt-and-peck for the address and inevitably
+get it wrong (actually, I've only gotten it wrong a few times, and
+checking against the diffstat tells me when I get it wrong, but I'm
+just a lot more comfortable when I don't have to "look for" the right
+thing to pull, and double-check that I have the right branch-name).
+
+
+Please use "git diff -M --stat --summary" to generate the diffstat:
+the -M enables rename detection, and the summary enables a summary of
+new/deleted or renamed files.
+
+With rename detection, the statistics are rather different [...]
+because git will notice that a fair number of the changes are renames.
-----------------------------------
SECTION 2 - HINTS, TIPS, AND TRICKS
Set active the IRQ edge(s)/level. This replaces the
SA1111 INTPOL manipulation, and the set_GPIO_IRQ_edge()
- function. Type should be one of the following:
-
- #define IRQT_NOEDGE (0)
- #define IRQT_RISING (__IRQT_RISEDGE)
- #define IRQT_FALLING (__IRQT_FALEDGE)
- #define IRQT_BOTHEDGE (__IRQT_RISEDGE|__IRQT_FALEDGE)
- #define IRQT_LOW (__IRQT_LOWLVL)
- #define IRQT_HIGH (__IRQT_HIGHLVL)
+ function. Type should be one of IRQ_TYPE_xxx defined in
+ <linux/irq.h>
3. set_GPIO_IRQ_edge() is obsolete, and should be replaced by set_irq_type.
---------------------------
+What: old tuner-3036 i2c driver
+When: 2.6.28
+Why: This driver is for VERY old i2c-over-parallel port teletext receiver
+ boxes. Rather then spending effort on converting this driver to V4L2,
+ and since it is extremely unlikely that anyone still uses one of these
+ devices, it was decided to drop it.
+Who: Hans Verkuil <hverkuil@xs4all.nl>
+ Mauro Carvalho Chehab <mchehab@infradead.org>
+
+ ---------------------------
+
+What: V4L2 dpc7146 driver
+When: 2.6.28
+Why: Old driver for the dpc7146 demonstration board that is no longer
+ relevant. The last time this was tested on actual hardware was
+ probably around 2002. Since this is a driver for a demonstration
+ board the decision was made to remove it rather than spending a
+ lot of effort continually updating this driver to stay in sync
+ with the latest internal V4L2 or I2C API.
+Who: Hans Verkuil <hverkuil@xs4all.nl>
+ Mauro Carvalho Chehab <mchehab@infradead.org>
+
+---------------------------
+
What: PCMCIA control ioctl (needed for pcmcia-cs [cardmgr, cardctl])
When: November 2005
Files: drivers/pcmcia/: pcmcia_ioctl.c
--- /dev/null
+Upgrading I2C Drivers to the new 2.6 Driver Model
+=================================================
+
+Ben Dooks <ben-linux@fluff.org>
+
+Introduction
+------------
+
+This guide outlines how to alter existing Linux 2.6 client drivers from
+the old to the new new binding methods.
+
+
+Example old-style driver
+------------------------
+
+
+struct example_state {
+ struct i2c_client client;
+ ....
+};
+
+static struct i2c_driver example_driver;
+
+static unsigned short ignore[] = { I2C_CLIENT_END };
+static unsigned short normal_addr[] = { OUR_ADDR, I2C_CLIENT_END };
+
+I2C_CLIENT_INSMOD;
+
+static int example_attach(struct i2c_adapter *adap, int addr, int kind)
+{
+ struct example_state *state;
+ struct device *dev = &adap->dev; /* to use for dev_ reports */
+ int ret;
+
+ state = kzalloc(sizeof(struct example_state), GFP_KERNEL);
+ if (state == NULL) {
+ dev_err(dev, "failed to create our state\n");
+ return -ENOMEM;
+ }
+
+ example->client.addr = addr;
+ example->client.flags = 0;
+ example->client.adapter = adap;
+
+ i2c_set_clientdata(&state->i2c_client, state);
+ strlcpy(client->i2c_client.name, "example", I2C_NAME_SIZE);
+
+ ret = i2c_attach_client(&state->i2c_client);
+ if (ret < 0) {
+ dev_err(dev, "failed to attach client\n");
+ kfree(state);
+ return ret;
+ }
+
+ dev = &state->i2c_client.dev;
+
+ /* rest of the initialisation goes here. */
+
+ dev_info(dev, "example client created\n");
+
+ return 0;
+}
+
+static int __devexit example_detach(struct i2c_client *client)
+{
+ struct example_state *state = i2c_get_clientdata(client);
+
+ i2c_detach_client(client);
+ kfree(state);
+ return 0;
+}
+
+static int example_attach_adapter(struct i2c_adapter *adap)
+{
+ return i2c_probe(adap, &addr_data, example_attach);
+}
+
+static struct i2c_driver example_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "example",
+ },
+ .attach_adapter = example_attach_adapter,
+ .detach_client = __devexit_p(example_detach),
+ .suspend = example_suspend,
+ .resume = example_resume,
+};
+
+
+Updating the client
+-------------------
+
+The new style binding model will check against a list of supported
+devices and their associated address supplied by the code registering
+the busses. This means that the driver .attach_adapter and
+.detach_adapter methods can be removed, along with the addr_data,
+as follows:
+
+- static struct i2c_driver example_driver;
+
+- static unsigned short ignore[] = { I2C_CLIENT_END };
+- static unsigned short normal_addr[] = { OUR_ADDR, I2C_CLIENT_END };
+
+- I2C_CLIENT_INSMOD;
+
+- static int example_attach_adapter(struct i2c_adapter *adap)
+- {
+- return i2c_probe(adap, &addr_data, example_attach);
+- }
+
+ static struct i2c_driver example_driver = {
+- .attach_adapter = example_attach_adapter,
+- .detach_client = __devexit_p(example_detach),
+ }
+
+Add the probe and remove methods to the i2c_driver, as so:
+
+ static struct i2c_driver example_driver = {
++ .probe = example_probe,
++ .remove = __devexit_p(example_remove),
+ }
+
+Change the example_attach method to accept the new parameters
+which include the i2c_client that it will be working with:
+
+- static int example_attach(struct i2c_adapter *adap, int addr, int kind)
++ static int example_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
+
+Change the name of example_attach to example_probe to align it with the
+i2c_driver entry names. The rest of the probe routine will now need to be
+changed as the i2c_client has already been setup for use.
+
+The necessary client fields have already been setup before
+the probe function is called, so the following client setup
+can be removed:
+
+- example->client.addr = addr;
+- example->client.flags = 0;
+- example->client.adapter = adap;
+-
+- strlcpy(client->i2c_client.name, "example", I2C_NAME_SIZE);
+
+The i2c_set_clientdata is now:
+
+- i2c_set_clientdata(&state->client, state);
++ i2c_set_clientdata(client, state);
+
+The call to i2c_attach_client is no longer needed, if the probe
+routine exits successfully, then the driver will be automatically
+attached by the core. Change the probe routine as so:
+
+- ret = i2c_attach_client(&state->i2c_client);
+- if (ret < 0) {
+- dev_err(dev, "failed to attach client\n");
+- kfree(state);
+- return ret;
+- }
+
+
+Remove the storage of 'struct i2c_client' from the 'struct example_state'
+as we are provided with the i2c_client in our example_probe. Instead we
+store a pointer to it for when it is needed.
+
+struct example_state {
+- struct i2c_client client;
++ struct i2c_client *client;
+
+the new i2c client as so:
+
+- struct device *dev = &adap->dev; /* to use for dev_ reports */
++ struct device *dev = &i2c_client->dev; /* to use for dev_ reports */
+
+And remove the change after our client is attached, as the driver no
+longer needs to register a new client structure with the core:
+
+- dev = &state->i2c_client.dev;
+
+In the probe routine, ensure that the new state has the client stored
+in it:
+
+static int example_probe(struct i2c_client *i2c_client,
+ const struct i2c_device_id *id)
+{
+ struct example_state *state;
+ struct device *dev = &i2c_client->dev;
+ int ret;
+
+ state = kzalloc(sizeof(struct example_state), GFP_KERNEL);
+ if (state == NULL) {
+ dev_err(dev, "failed to create our state\n");
+ return -ENOMEM;
+ }
+
++ state->client = i2c_client;
+
+Update the detach method, by changing the name to _remove and
+to delete the i2c_detach_client call. It is possible that you
+can also remove the ret variable as it is not not needed for
+any of the core functions.
+
+- static int __devexit example_detach(struct i2c_client *client)
++ static int __devexit example_remove(struct i2c_client *client)
+{
+ struct example_state *state = i2c_get_clientdata(client);
+
+- i2c_detach_client(client);
+
+And finally ensure that we have the correct ID table for the i2c-core
+and other utilities:
+
++ struct i2c_device_id example_idtable[] = {
++ { "example", 0 },
++ { }
++};
++
++MODULE_DEVICE_TABLE(i2c, example_idtable);
+
+static struct i2c_driver example_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "example",
+ },
++ .id_table = example_ids,
+
+
+Our driver should now look like this:
+
+struct example_state {
+ struct i2c_client *client;
+ ....
+};
+
+static int example_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct example_state *state;
+ struct device *dev = &client->dev;
+
+ state = kzalloc(sizeof(struct example_state), GFP_KERNEL);
+ if (state == NULL) {
+ dev_err(dev, "failed to create our state\n");
+ return -ENOMEM;
+ }
+
+ state->client = client;
+ i2c_set_clientdata(client, state);
+
+ /* rest of the initialisation goes here. */
+
+ dev_info(dev, "example client created\n");
+
+ return 0;
+}
+
+static int __devexit example_remove(struct i2c_client *client)
+{
+ struct example_state *state = i2c_get_clientdata(client);
+
+ kfree(state);
+ return 0;
+}
+
+static struct i2c_device_id example_idtable[] = {
+ { "example", 0 },
+ { }
+};
+
+MODULE_DEVICE_TABLE(i2c, example_idtable);
+
+static struct i2c_driver example_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "example",
+ },
+ .id_table = example_idtable,
+ .probe = example_probe,
+ .remove = __devexit_p(example_remove),
+ .suspend = example_suspend,
+ .resume = example_resume,
+};
1 -> Hauppauge HVR950Q (au0828) [2040:7200,2040:7210,2040:7217,2040:721b,2040:721f,2040:7280,0fd9:0008]
2 -> Hauppauge HVR850 (au0828) [2040:7240]
3 -> DViCO FusionHDTV USB (au0828) [0fe9:d620]
+ 4 -> Hauppauge HVR950Q rev xxF8 (au0828) [2040:7201,2040:7211,2040:7281]
0 -> Unknown EM2800 video grabber (em2800) [eb1a:2800]
- 1 -> Unknown EM2750/28xx video grabber (em2820/em2840) [eb1a:2750,eb1a:2820,eb1a:2821,eb1a:2860,eb1a:2861,eb1a:2870,eb1a:2881,eb1a:2883]
+ 1 -> Unknown EM2750/28xx video grabber (em2820/em2840) [eb1a:2820,eb1a:2821,eb1a:2860,eb1a:2861,eb1a:2870,eb1a:2881,eb1a:2883]
2 -> Terratec Cinergy 250 USB (em2820/em2840) [0ccd:0036]
3 -> Pinnacle PCTV USB 2 (em2820/em2840) [2304:0208]
4 -> Hauppauge WinTV USB 2 (em2820/em2840) [2040:4200,2040:4201]
5 -> MSI VOX USB 2.0 (em2820/em2840)
6 -> Terratec Cinergy 200 USB (em2800)
- 7 -> Leadtek Winfast USB II (em2800)
+ 7 -> Leadtek Winfast USB II (em2800) [0413:6023]
8 -> Kworld USB2800 (em2800)
9 -> Pinnacle Dazzle DVC 90/DVC 100 (em2820/em2840) [2304:0207,2304:021a]
10 -> Hauppauge WinTV HVR 900 (em2880) [2040:6500]
13 -> Terratec Prodigy XS (em2880) [0ccd:0047]
14 -> Pixelview Prolink PlayTV USB 2.0 (em2820/em2840)
15 -> V-Gear PocketTV (em2800)
- 16 -> Hauppauge WinTV HVR 950 (em2880) [2040:6513,2040:6517,2040:651b,2040:651f]
+ 16 -> Hauppauge WinTV HVR 950 (em2883) [2040:6513,2040:6517,2040:651b,2040:651f]
17 -> Pinnacle PCTV HD Pro Stick (em2880) [2304:0227]
18 -> Hauppauge WinTV HVR 900 (R2) (em2880) [2040:6502]
19 -> PointNix Intra-Oral Camera (em2860)
+ 20 -> AMD ATI TV Wonder HD 600 (em2880) [0438:b002]
+ 21 -> eMPIA Technology, Inc. GrabBeeX+ Video Encoder (em2800) [eb1a:2801]
+ 22 -> Unknown EM2750/EM2751 webcam grabber (em2750) [eb1a:2750,eb1a:2751]
+ 23 -> Huaqi DLCW-130 (em2750)
+ 24 -> D-Link DUB-T210 TV Tuner (em2820/em2840) [2001:f112]
+ 25 -> Gadmei UTV310 (em2820/em2840)
+ 26 -> Hercules Smart TV USB 2.0 (em2820/em2840)
+ 27 -> Pinnacle PCTV USB 2 (Philips FM1216ME) (em2820/em2840)
+ 28 -> Leadtek Winfast USB II Deluxe (em2820/em2840)
+ 29 -> Pinnacle Dazzle DVC 100 (em2820/em2840)
+ 30 -> Videology 20K14XUSB USB2.0 (em2820/em2840)
+ 31 -> Usbgear VD204v9 (em2821)
+ 32 -> Supercomp USB 2.0 TV (em2821)
+ 33 -> SIIG AVTuner-PVR/Prolink PlayTV USB 2.0 (em2821)
+ 34 -> Terratec Cinergy A Hybrid XS (em2860) [0ccd:004f]
+ 35 -> Typhoon DVD Maker (em2860)
+ 36 -> NetGMBH Cam (em2860)
+ 37 -> Gadmei UTV330 (em2860)
+ 38 -> Yakumo MovieMixer (em2861)
+ 39 -> KWorld PVRTV 300U (em2861) [eb1a:e300]
+ 40 -> Plextor ConvertX PX-TV100U (em2861) [093b:a005]
+ 41 -> Kworld 350 U DVB-T (em2870) [eb1a:e350]
+ 42 -> Kworld 355 U DVB-T (em2870) [eb1a:e355,eb1a:e357]
+ 43 -> Terratec Cinergy T XS (em2870) [0ccd:0043]
+ 44 -> Terratec Cinergy T XS (MT2060) (em2870)
+ 45 -> Pinnacle PCTV DVB-T (em2870)
+ 46 -> Compro, VideoMate U3 (em2870) [185b:2870]
+ 47 -> KWorld DVB-T 305U (em2880) [eb1a:e305]
+ 48 -> KWorld DVB-T 310U (em2880)
+ 49 -> MSI DigiVox A/D (em2880) [eb1a:e310]
+ 50 -> MSI DigiVox A/D II (em2880) [eb1a:e320]
+ 51 -> Terratec Hybrid XS Secam (em2880) [0ccd:004c]
+ 52 -> DNT DA2 Hybrid (em2881)
+ 53 -> Pinnacle Hybrid Pro (em2881)
+ 54 -> Kworld VS-DVB-T 323UR (em2882) [eb1a:e323]
+ 55 -> Terratec Hybrid XS (em2882) (em2882) [0ccd:005e]
+ 56 -> Pinnacle Hybrid Pro (2) (em2882) [2304:0226]
+ 57 -> Kworld PlusTV HD Hybrid 330 (em2883) [eb1a:a316]
+ 58 -> Compro VideoMate ForYou/Stereo (em2820/em2840) [185b:2041]
-List of the webcams know by gspca.
+List of the webcams known by gspca.
The modules are:
gspca_main main driver
M: bn@niasdigital.com
S: Maintained
+SOC-CAMERA V4L2 SUBSYSTEM
+P: Guennadi Liakhovetski
+M: g.liakhovetski@gmx.de
+L: video4linux-list@redhat.com
+S: Maintained
+
SOFTWARE RAID (Multiple Disks) SUPPORT
P: Ingo Molnar
M: mingo@redhat.com
endif
# Where to locate arch specific headers
-hdr-arch := $(SRCARCH)
+ifeq ($(ARCH),sparc64)
+ hdr-arch := sparc
+else
+ hdr-arch := $(SRCARCH)
+endif
KCONFIG_CONFIG ?= .config
select PLAT_IOP
select PCI
select GENERIC_GPIO
- select HAVE_GPIO_LIB
+ select ARCH_REQUIRE_GPIOLIB
help
Support for Intel's 80219 and IOP32X (XScale) family of
processors.
select PLAT_IOP
select PCI
select GENERIC_GPIO
- select HAVE_GPIO_LIB
+ select ARCH_REQUIRE_GPIOLIB
help
Support for Intel's IOP33X (XScale) family of processors.
select GENERIC_CLOCKEVENTS
select ARCH_MTD_XIP
select GENERIC_GPIO
- select HAVE_GPIO_LIB
+ select ARCH_REQUIRE_GPIOLIB
help
Support for Freescale MXC/iMX-based family of processors
tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi
tune-$(CONFIG_CPU_ARM9TDMI) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM940T) :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM946T) :=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
+tune-$(CONFIG_CPU_ARM946E) :=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi
mask = 1 << (irq - LOCOMO_IRQ_GPIO_START);
- if (type == IRQT_PROBE) {
+ if (type == IRQ_TYPE_PROBE) {
if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
return 0;
- type = __IRQT_RISEDGE | __IRQT_FALEDGE;
+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
- if (type & __IRQT_RISEDGE)
+ if (type & IRQ_TYPE_EDGE_RISING)
GPIO_IRQ_rising_edge |= mask;
else
GPIO_IRQ_rising_edge &= ~mask;
- if (type & __IRQT_FALEDGE)
+ if (type & IRQ_TYPE_EDGE_FALLING)
GPIO_IRQ_falling_edge |= mask;
else
GPIO_IRQ_falling_edge &= ~mask;
/*
* Install handler for IRQ_LOCOMO_HW.
*/
- set_irq_type(lchip->irq, IRQT_FALLING);
+ set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
set_irq_chip_data(lchip->irq, irqbase);
set_irq_chained_handler(lchip->irq, locomo_handler);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long ip0;
- if (flags == IRQT_PROBE)
+ if (flags == IRQ_TYPE_PROBE)
return 0;
- if ((!(flags & __IRQT_RISEDGE) ^ !(flags & __IRQT_FALEDGE)) == 0)
+ if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0)
return -EINVAL;
ip0 = sa1111_readl(mapbase + SA1111_INTPOL0);
- if (flags & __IRQT_RISEDGE)
+ if (flags & IRQ_TYPE_EDGE_RISING)
ip0 &= ~mask;
else
ip0 |= mask;
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long ip1;
- if (flags == IRQT_PROBE)
+ if (flags == IRQ_TYPE_PROBE)
return 0;
- if ((!(flags & __IRQT_RISEDGE) ^ !(flags & __IRQT_FALEDGE)) == 0)
+ if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0)
return -EINVAL;
ip1 = sa1111_readl(mapbase + SA1111_INTPOL1);
- if (flags & __IRQT_RISEDGE)
+ if (flags & IRQ_TYPE_EDGE_RISING)
ip1 &= ~mask;
else
ip1 |= mask;
/*
* Register SA1111 interrupt
*/
- set_irq_type(sachip->irq, IRQT_RISING);
+ set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
set_irq_data(sachip->irq, irqbase);
set_irq_chained_handler(sachip->irq, sa1111_irq_handler);
}
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21-hh17
-# Fri Nov 9 20:23:03 2007
+# Linux kernel version: 2.6.26
+# Sat Jul 26 22:28:46 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_MMU=y
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
CONFIG_ZONE_DMA=y
CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
-# Code maturity level options
+# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_KALLSYMS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
CONFIG_SHMEM=y
-CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
-
-#
-# Block layer
-#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
#
# IO Schedulers
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
#
# System Type
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_PNX4008 is not set
CONFIG_ARCH_PXA=y
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
-# CONFIG_BOARD_IRQ_MAP_SMALL is not set
-CONFIG_BOARD_IRQ_MAP_BIG=y
-CONFIG_DMABOUNCE=y
+# CONFIG_ARCH_MSM7X00A is not set
#
-# Intel PXA2xx Implementations
+# Intel PXA2xx/PXA3xx Implementations
#
+# CONFIG_ARCH_GUMSTIX is not set
# CONFIG_ARCH_LUBBOCK is not set
# CONFIG_MACH_LOGICPD_PXA270 is not set
# CONFIG_MACH_MAINSTONE is not set
# CONFIG_ARCH_PXA_IDP is not set
-CONFIG_TOSHIBA_TMIO_OHCI=y
-CONFIG_ARCH_ESERIES=y
+# CONFIG_PXA_SHARPSL is not set
+CONFIG_ARCH_PXA_ESERIES=y
CONFIG_MACH_E330=y
+CONFIG_MACH_E350=y
CONFIG_MACH_E740=y
CONFIG_MACH_E750=y
CONFIG_MACH_E400=y
CONFIG_MACH_E800=y
-CONFIG_E330_LCD=y
-CONFIG_E740_LCD=y
-CONFIG_E750_LCD=y
-CONFIG_E400_LCD=y
-CONFIG_E800_LCD=y
-CONFIG_ESERIES_UDC=y
-CONFIG_E330_TC6387XB=y
-CONFIG_E740_T7L66XB=y
-CONFIG_E400_T7L66XB=y
-CONFIG_E750_E800_TC6393XB=y
-CONFIG_E740_PCMCIA=m
-CONFIG_E750_PCMCIA=m
-CONFIG_E800_PCMCIA=m
-# CONFIG_MACH_A620 is not set
-# CONFIG_MACH_A716 is not set
-# CONFIG_MACH_A730 is not set
-# CONFIG_ARCH_H1900 is not set
-# CONFIG_ARCH_H2200 is not set
-# CONFIG_MACH_H3900 is not set
-# CONFIG_MACH_H4000 is not set
-# CONFIG_MACH_H4700 is not set
-# CONFIG_MACH_HX2750 is not set
-# CONFIG_ARCH_H5400 is not set
-# CONFIG_MACH_HIMALAYA is not set
-# CONFIG_MACH_HTCUNIVERSAL is not set
-# CONFIG_MACH_HTCALPINE is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_HTCAPACHE is not set
-# CONFIG_MACH_BLUEANGEL is not set
-
-#
-# HTC_HW6X00
-#
-# CONFIG_MACH_HTCBEETLES is not set
-# CONFIG_MACH_HW6900 is not set
-# CONFIG_MACH_HTCATHENA is not set
-# CONFIG_ARCH_AXIMX3 is not set
-# CONFIG_ARCH_AXIMX5 is not set
-# CONFIG_MACH_X50 is not set
-# CONFIG_ARCH_ROVERP1 is not set
-# CONFIG_ARCH_ROVERP5P is not set
-# CONFIG_MACH_XSCALE_PALMLD is not set
-# CONFIG_MACH_T3XSCALE is not set
-# CONFIG_MACH_RECON is not set
-# CONFIG_MACH_GHI270HG is not set
-# CONFIG_MACH_GHI270 is not set
-# CONFIG_MACH_LOOXC550 is not set
-# CONFIG_PXA_SHARPSL is not set
# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
+# CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_PCM027 is not set
+# CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_PXA_EZX is not set
CONFIG_PXA25x=y
+# CONFIG_PXA_PWM is not set
+
+#
+# Boot options
+#
#
-# Linux As Bootloader
+# Power management
#
-# CONFIG_LAB is not set
#
# Processor Type
CONFIG_CPU_XSCALE=y
CONFIG_CPU_32v5=y
CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_TLB_V4WBI=y
CONFIG_CPU_CP15=y
#
# Bus support
#
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-CONFIG_PCCARD=m
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCCARD=y
# CONFIG_PCMCIA_DEBUG is not set
CONFIG_PCMCIA=m
CONFIG_PCMCIA_LOAD_CIS=y
#
# PC-card bridges
#
-CONFIG_PCMCIA_PXA2XX=m
#
# Kernel Features
#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
# CONFIG_PREEMPT is not set
CONFIG_HZ=100
CONFIG_AEABI=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
CONFIG_ALIGNMENT_TRAP=y
#
CONFIG_CMDLINE=""
# CONFIG_XIP_KERNEL is not set
CONFIG_KEXEC=y
-# CONFIG_TXTOFFSET_DELTA is not set
+CONFIG_ATAGS_PROC=y
#
# CPU Frequency scaling
# Power management options
#
CONFIG_PM=y
-CONFIG_PM_LEGACY=y
# CONFIG_PM_DEBUG is not set
-# CONFIG_DPM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
#
# Networking
#
# Networking options
#
-# CONFIG_NETDEBUG is not set
# CONFIG_PACKET is not set
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_TUNNEL=y
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
# CONFIG_NET_SCHED is not set
#
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
+# CONFIG_CAN is not set
+CONFIG_IRDA=y
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=m
+CONFIG_IRCOMM=m
+CONFIG_IRDA_ULTRA=y
+
+#
+# IrDA options
+#
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+CONFIG_IRDA_FAST_RR=y
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+# CONFIG_KINGSUN_DONGLE is not set
+# CONFIG_KSDAZZLE_DONGLE is not set
+# CONFIG_KS959_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+CONFIG_PXA_FICP=y
+# CONFIG_MCS_FIR is not set
# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+CONFIG_NL80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_MAC80211=m
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_IEEE80211=m
# CONFIG_IEEE80211_DEBUG is not set
CONFIG_IEEE80211_CRYPT_WEP=m
-# CONFIG_IEEE80211_CRYPT_CCMP is not set
-# CONFIG_IEEE80211_CRYPT_TKIP is not set
-# CONFIG_IEEE80211_SOFTMAC is not set
-CONFIG_WIRELESS_EXT=y
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
#
# Device Drivers
#
# Generic Driver Options
#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_STANDALONE is not set
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
CONFIG_MTD=m
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_PARTITIONS is not set
#
# User Modules And Translation Layers
#
-CONFIG_MTD_CHAR=m
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
+# CONFIG_MTD_CHAR is not set
+# CONFIG_MTD_BLKDEVS is not set
+# CONFIG_MTD_BLOCK is not set
# CONFIG_MTD_BLOCK_RO is not set
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
#
# Mapping drivers for chip access
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
CONFIG_MTD_NAND=m
-CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
-# CONFIG_MTD_NAND_H1900 is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
CONFIG_MTD_NAND_IDS=m
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_NAND_SHARPSL is not set
-# CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
# CONFIG_MTD_ONENAND is not set
#
-# Parallel port support
+# UBI - Unsorted block images
#
+# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=m
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=6144
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=m
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=m
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=m
-# CONFIG_IDEDISK_MULTI_MODE is not set
-# CONFIG_BLK_DEV_IDECS is not set
-# CONFIG_BLK_DEV_IDECD is not set
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_BLK_DEV_IDESCSI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_IDE_ARM is not set
-# CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_SCSI_PROC_FS is not set
#
# SCSI support type (disk, tape, CD-ROM)
#
-# CONFIG_BLK_DEV_SD is not set
+CONFIG_BLK_DEV_SD=m
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# PCMCIA SCSI adapter support
-#
-# CONFIG_PCMCIA_AHA152X is not set
-# CONFIG_PCMCIA_FDOMAIN is not set
-# CONFIG_PCMCIA_NINJA_SCSI is not set
-# CONFIG_PCMCIA_QLOGIC is not set
-# CONFIG_PCMCIA_SYM53C500 is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_SATA_PMP is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_MV is not set
+CONFIG_PATA_PCMCIA=m
+# CONFIG_PATA_PLATFORM is not set
# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
-
-#
-# PHY device support
-#
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_VETH is not set
# CONFIG_NET_ETHERNET is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-CONFIG_NET_RADIO=y
-# CONFIG_NET_WIRELESS_RTNETLINK is not set
-
-#
-# Obsolete Wireless cards support (pre-802.11)
-#
-# CONFIG_STRIP is not set
-# CONFIG_PCMCIA_WAVELAN is not set
-# CONFIG_PCMCIA_NETWAVE is not set
-
-#
-# Wireless 802.11 Frequency Hopping cards support
+# Wireless LAN
#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
# CONFIG_PCMCIA_RAYCS is not set
-
-#
-# Wireless 802.11b ISA/PCI cards support
-#
-# CONFIG_HERMES is not set
+# CONFIG_LIBERTAS is not set
+CONFIG_HERMES=m
+CONFIG_PCMCIA_HERMES=m
+# CONFIG_PCMCIA_SPECTRUM is not set
# CONFIG_ATMEL is not set
-
-#
-# Wireless 802.11b Pcmcia/Cardbus cards support
-#
# CONFIG_AIRO_CS is not set
# CONFIG_PCMCIA_WL3501 is not set
# CONFIG_USB_ZD1201 is not set
-CONFIG_HOSTAP=m
-# CONFIG_HOSTAP_FIRMWARE is not set
-# CONFIG_HOSTAP_CS is not set
-# CONFIG_ACX is not set
-CONFIG_NET_WIRELESS=y
-
-#
-# PCMCIA network device support
-#
-# CONFIG_NET_PCMCIA is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
#
-# Wan interfaces
+# USB Network Adapters
#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+CONFIG_NET_PCMCIA=y
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+CONFIG_PCMCIA_PCNET=m
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_PCMCIA_AXNET is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
# CONFIG_ISDN is not set
#
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_TSDEV=m
-CONFIG_INPUT_TSDEV_SCREEN_X=240
-CONFIG_INPUT_TSDEV_SCREEN_Y=320
CONFIG_INPUT_EVDEV=m
# CONFIG_INPUT_EVBUG is not set
-# CONFIG_INPUT_LED_TRIGGER is not set
#
# Input Device Drivers
#
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=m
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
-CONFIG_TOUCHSCREEN_WM97XX=m
-CONFIG_TOUCHSCREEN_WM9705=y
-CONFIG_TOUCHSCREEN_WM9712=y
-CONFIG_TOUCHSCREEN_WM9713=y
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_UCB1400 is not set
+CONFIG_TOUCHSCREEN_WM97XX=m
+CONFIG_TOUCHSCREEN_WM9705=y
+CONFIG_TOUCHSCREEN_WM9712=y
+CONFIG_TOUCHSCREEN_WM9713=y
+# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_PXA is not set
-# CONFIG_RS232_SERIAL is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
-
-#
-# IPMI
-#
# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
CONFIG_HW_RANDOM=m
# CONFIG_NVRAM is not set
-# CONFIG_SA1100_RTC is not set
-# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
-# CONFIG_TIHTC is not set
#
# PCMCIA character devices
# CONFIG_SYNCLINK_CS is not set
# CONFIG_CARDMAN_4000 is not set
# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
# CONFIG_I2C is not set
-
-#
-# SPI support
-#
# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_SYSFS is not set
#
-# Hardware Monitoring support
-#
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
-# CONFIG_POWER_SUPPLY is not set
-
-#
-# L3 serial bus support
-#
-# CONFIG_L3 is not set
-
-#
-# Misc devices
+# I2C GPIO expanders:
#
#
-# Multimedia Capabilities Port drivers
+# PCI GPIO expanders:
#
-# CONFIG_ADC is not set
#
-# Compaq/iPAQ Drivers
+# SPI GPIO expanders:
#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
#
-# Compaq/HP iPAQ Drivers
+# Sonics Silicon Backplane
#
-# CONFIG_IPAQ_SLEEVE is not set
-# CONFIG_SLEEVE_DEBUG is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
#
# Multifunction device drivers
#
+CONFIG_MFD_CORE=y
# CONFIG_MFD_SM501 is not set
-# CONFIG_HTC_ASIC2 is not set
-# CONFIG_HTC_ASIC3 is not set
-# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_BBKEYS is not set
-# CONFIG_HTC_ASIC3_DS1WM is not set
-# CONFIG_SOC_SAMCOP is not set
-# CONFIG_SOC_HAMCOP is not set
-# CONFIG_SOC_MQ11XX is not set
-CONFIG_SOC_T7L66XB=y
-# CONFIG_SOC_TC6387XB is not set
-CONFIG_SOC_TC6393XB=y
-# CONFIG_SOC_TSC2101 is not set
-# CONFIG_SOC_TSC2200 is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
+# CONFIG_HTC_PASIC3 is not set
+CONFIG_MFD_TC6393XB=y
#
-# LED Triggers
+# Multimedia devices
#
-# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
#
-# Multimedia devices
+# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
#
-# Digital Video Broadcasting Devices
+# Multimedia drivers
#
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
+# CONFIG_DAB is not set
#
# Graphics support
#
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CORGI=y
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
#
# Frame buffer hardware drivers
#
-# CONFIG_FB_IMAGEON is not set
# CONFIG_FB_S1D13XXX is not set
CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_SMARTPANEL is not set
# CONFIG_FB_PXA_PARAMETERS is not set
# CONFIG_FB_MBX is not set
CONFIG_FB_W100=y
+# CONFIG_FB_AM200EPD is not set
# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_VSFB is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CORGI=y
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FONTS=y
# CONFIG_FONT_8x8 is not set
# CONFIG_FONT_6x11 is not set
# CONFIG_FONT_7x14 is not set
# CONFIG_FONT_PEARL_8x8 is not set
-CONFIG_FONT_ACORN_8x8=y
-# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+CONFIG_FONT_MINI_4x6=y
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_10x18 is not set
-
-#
-# Logo configuration
-#
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LINUX_CLUT224=y
-
-#
-# Sound
-#
+# CONFIG_LOGO is not set
CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
CONFIG_SND=m
CONFIG_SND_TIMER=m
CONFIG_SND_PCM=m
CONFIG_SND_VERBOSE_PROCFS=y
CONFIG_SND_VERBOSE_PRINTK=y
# CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_DRIVERS=y
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
-
-#
-# ALSA ARM devices
-#
+CONFIG_SND_ARM=y
# CONFIG_SND_PXA2XX_AC97 is not set
-# CONFIG_SND_RECON is not set
-
-#
-# USB devices
-#
-# CONFIG_SND_USB_AUDIO is not set
-
-#
-# PCMCIA devices
-#
-# CONFIG_SND_VXPOCKET is not set
-# CONFIG_SND_PDAUDIOCF is not set
-
-#
-# SoC audio support
-#
-CONFIG_SND_SOC_AC97_BUS=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
CONFIG_SND_SOC=m
-
-#
-# SoC Platforms
-#
-
-#
-# SoC Audio for the Atmel AT91
-#
-
-#
-# SoC Audio for the Intel PXA2xx
-#
+CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_PXA2XX_SOC=m
CONFIG_SND_PXA2XX_SOC_AC97=m
-CONFIG_SND_PXA2XX_SOC_E740_WM9705=m
-CONFIG_SND_PXA2XX_SOC_E750_WM9705=m
-CONFIG_SND_PXA2XX_SOC_E800_WM9712=m
-# CONFIG_SND_PXA2XX_SOC_MAGICIAN is not set
-# CONFIG_SND_PXA2XX_SOC_BLUEANGEL is not set
-# CONFIG_SND_PXA2XX_SOC_H5000 is not set
-
-#
-# SoC Audio for the Freescale i.MX
-#
-
-#
-# SoC Audio for the Samsung S3C24XX
-#
-# CONFIG_SND_SOC_AC97_CODEC is not set
-# CONFIG_SND_SOC_WM8711 is not set
-# CONFIG_SND_SOC_WM8510 is not set
-# CONFIG_SND_SOC_WM8731 is not set
-# CONFIG_SND_SOC_WM8750 is not set
-# CONFIG_SND_SOC_WM8753 is not set
-# CONFIG_SND_SOC_WM8772 is not set
-# CONFIG_SND_SOC_WM8971 is not set
-# CONFIG_SND_SOC_WM8956 is not set
-# CONFIG_SND_SOC_WM8960 is not set
-# CONFIG_SND_SOC_WM8976 is not set
-# CONFIG_SND_SOC_WM8974 is not set
-# CONFIG_SND_SOC_WM8980 is not set
-CONFIG_SND_SOC_WM9705=m
-# CONFIG_SND_SOC_WM9713 is not set
+CONFIG_SND_PXA2XX_SOC_E800=m
CONFIG_SND_SOC_WM9712=m
-# CONFIG_SND_SOC_UDA1380 is not set
-# CONFIG_SND_SOC_AK4535 is not set
-
-#
-# Open Sound System
-#
# CONFIG_SOUND_PRIME is not set
CONFIG_AC97_BUS=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
#
-# HID Devices
+# USB Input Devices
#
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
+CONFIG_USB_HID=m
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
#
-# USB support
+# USB HID Boot Protocol drivers
#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
CONFIG_USB=m
-CONFIG_USB_DEBUG=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
#
# Miscellaneous USB options
#
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_SUSPEND is not set
# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
#
# USB Host Controller Drivers
#
+# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
# may also be needed; see USB_STORAGE Help for more information
#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE is not set
# CONFIG_USB_LIBUSUAL is not set
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-# CONFIG_USB_GTCO is not set
-
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_USB_MON is not set
+CONFIG_USB_MON=y
#
# USB port drivers
#
-
-#
-# USB Serial Converter support
-#
# CONFIG_USB_SERIAL is not set
#
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
+# CONFIG_USB_ISIGHTFW is not set
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_NET2280 is not set
-CONFIG_USB_GADGET_PXA2XX=y
-CONFIG_USB_PXA2XX=y
-# CONFIG_USB_PXA2XX_SMALL is not set
+CONFIG_USB_GADGET_PXA25X=y
+CONFIG_USB_PXA25X=y
+CONFIG_USB_PXA25X_SMALL=y
+# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_PXA27X is not set
# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_MQ11XX is not set
# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
# CONFIG_USB_GADGET_AT91 is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_GADGET_DUALSPEED is not set
# CONFIG_USB_ZERO is not set
-CONFIG_USB_ETH=y
+CONFIG_USB_ETH=m
# CONFIG_USB_ETH_RNDIS is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_CHAR is not set
-# CONFIG_USB_PXA2XX_GPIO is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
#
-# MMC/SD Card support
+# MMC/SD Card Drivers
#
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_BLOCK=y
-# CONFIG_MMC_PXA is not set
-CONFIG_MMC_TMIO=y
-# CONFIG_MMC_SAMCOP is not set
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
#
-# Real Time Clock
+# MMC/SD Host Controller Drivers
#
+# CONFIG_MMC_PXA is not set
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
#
# File systems
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
#
# Partition Types
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-
-#
-# Native Language Support
-#
+# CONFIG_SYSV68_PARTITION is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
# CONFIG_DLM is not set
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
CONFIG_FRAME_POINTER=y
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+# CONFIG_FTRACE is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_DEBUG_USER is not set
#
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
#
-# Cryptographic options
+# Crypto core or helper
#
-CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=m
CONFIG_CRYPTO_BLKCIPHER=m
CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
#
-# Hardware crypto devices
+# Compression
#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
#
# Library routines
#
CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=y
# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=m
-CONFIG_ZLIB_DEFLATE=m
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
/* Serial */
at91_add_device_serial();
/* USB Host */
- set_irq_type(AT91CAP9_ID_UHP, IRQT_HIGH);
+ set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
at91_add_device_usbh(&cap9adk_usbh_data);
/* USB HS */
- set_irq_type(AT91CAP9_ID_UDPHS, IRQT_HIGH);
+ set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
at91_add_device_usba(&cap9adk_usba_udc_data);
/* SPI */
at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
/* I2C */
at91_add_device_i2c(NULL, 0);
/* LCD Controller */
- set_irq_type(AT91CAP9_ID_LCDC, IRQT_HIGH);
+ set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
at91_add_device_lcdc(&cap9adk_lcdc_data);
/* AC97 */
at91_add_device_ac97(&cap9adk_ac97_data);
unsigned int smr, srctype;
switch (type) {
- case IRQT_HIGH:
+ case IRQ_TYPE_LEVEL_HIGH:
srctype = AT91_AIC_SRCTYPE_HIGH;
break;
- case IRQT_RISING:
+ case IRQ_TYPE_EDGE_RISING:
srctype = AT91_AIC_SRCTYPE_RISING;
break;
- case IRQT_LOW:
+ case IRQ_TYPE_LEVEL_LOW:
if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
srctype = AT91_AIC_SRCTYPE_LOW;
else
return -EINVAL;
break;
- case IRQT_FALLING:
+ case IRQ_TYPE_EDGE_FALLING:
if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
srctype = AT91_AIC_SRCTYPE_FALLING;
else
int port = line >> 3;
int port_mask = 1 << (line & 7);
- if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
+ if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
ep93xx_gpio_update_int_params(port);
}
int port = line >> 3;
int port_mask = 1 << (line & 7);
- if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE)
+ if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
gpio_int_unmasked[port] &= ~port_mask;
gpio_direction_input(gpio);
switch (type) {
- case IRQT_RISING:
+ case IRQ_TYPE_EDGE_RISING:
gpio_int_type1[port] |= port_mask;
gpio_int_type2[port] |= port_mask;
desc->handle_irq = handle_edge_irq;
break;
- case IRQT_FALLING:
+ case IRQ_TYPE_EDGE_FALLING:
gpio_int_type1[port] |= port_mask;
gpio_int_type2[port] &= ~port_mask;
desc->handle_irq = handle_edge_irq;
break;
- case IRQT_HIGH:
+ case IRQ_TYPE_LEVEL_HIGH:
gpio_int_type1[port] &= ~port_mask;
gpio_int_type2[port] |= port_mask;
desc->handle_irq = handle_level_irq;
break;
- case IRQT_LOW:
+ case IRQ_TYPE_LEVEL_LOW:
gpio_int_type1[port] &= ~port_mask;
gpio_int_type2[port] &= ~port_mask;
desc->handle_irq = handle_level_irq;
break;
- case IRQT_BOTHEDGE:
+ case IRQ_TYPE_EDGE_BOTH:
gpio_int_type1[port] |= port_mask;
/* set initial polarity based on current input level */
if (gpio_get_value(gpio))
reg = irq >> 5;
bit = 1 << (irq % 32);
- if (type == IRQT_PROBE) {
+ if (type == IRQ_TYPE_PROBE) {
/* Don't mess with enabled GPIOs using preconfigured edges or
GPIOs set to alternate function during probe */
/* TODO: support probe */
// return 0;
// if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
// return 0;
-// type = __IRQT_RISEDGE | __IRQT_FALEDGE;
+// type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
GIUS(reg) |= bit;
DEBUG_IRQ("setting type of irq %d to ", _irq);
- if (type & __IRQT_RISEDGE) {
+ if (type & IRQ_TYPE_EDGE_RISING) {
DEBUG_IRQ("rising edges\n");
irq_type = 0x0;
}
- if (type & __IRQT_FALEDGE) {
+ if (type & IRQ_TYPE_EDGE_FALLING) {
DEBUG_IRQ("falling edges\n");
irq_type = 0x1;
}
- if (type & __IRQT_LOWLVL) {
+ if (type & IRQ_TYPE_LEVEL_LOW) {
DEBUG_IRQ("low level\n");
irq_type = 0x3;
}
- if (type & __IRQT_HIGHLVL) {
+ if (type & IRQ_TYPE_LEVEL_HIGH) {
DEBUG_IRQ("high level\n");
irq_type = 0x2;
}
/*
* Then, set the proper trigger type.
*/
- if (type & IRQT_FALLING)
+ if (type & IRQ_TYPE_EDGE_FALLING)
GPIO_IRQ_falling_edge |= 1 << line;
else
GPIO_IRQ_falling_edge &= ~(1 << line);
- if (type & IRQT_RISING)
+ if (type & IRQ_TYPE_EDGE_RISING)
GPIO_IRQ_rising_edge |= 1 << line;
else
GPIO_IRQ_rising_edge &= ~(1 << line);
- if (type & IRQT_LOW)
+ if (type & IRQ_TYPE_LEVEL_LOW)
GPIO_IRQ_level_low |= 1 << line;
else
GPIO_IRQ_level_low &= ~(1 << line);
- if (type & IRQT_HIGH)
+ if (type & IRQ_TYPE_LEVEL_HIGH)
GPIO_IRQ_level_high |= 1 << line;
else
GPIO_IRQ_level_high &= ~(1 << line);
return -EINVAL;
switch (type) {
- case IRQT_BOTHEDGE:
+ case IRQ_TYPE_EDGE_BOTH:
int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
irq_type = IXP23XX_IRQ_EDGE;
break;
- case IRQT_RISING:
+ case IRQ_TYPE_EDGE_RISING:
int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
irq_type = IXP23XX_IRQ_EDGE;
break;
- case IRQT_FALLING:
+ case IRQ_TYPE_EDGE_FALLING:
int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
irq_type = IXP23XX_IRQ_EDGE;
break;
- case IRQT_HIGH:
+ case IRQ_TYPE_LEVEL_HIGH:
int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
irq_type = IXP23XX_IRQ_LEVEL;
break;
- case IRQT_LOW:
+ case IRQ_TYPE_LEVEL_LOW:
int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
irq_type = IXP23XX_IRQ_LEVEL;
break;
static void __init roadrunner_pci_preinit(void)
{
- set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQT_LOW);
- set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQT_LOW);
+ set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
ixp23xx_pci_preinit();
}
void __init avila_pci_preinit(void)
{
- set_irq_type(IRQ_AVILA_PCI_INTA, IRQT_LOW);
- set_irq_type(IRQ_AVILA_PCI_INTB, IRQT_LOW);
- set_irq_type(IRQ_AVILA_PCI_INTC, IRQT_LOW);
- set_irq_type(IRQ_AVILA_PCI_INTD, IRQT_LOW);
+ set_irq_type(IRQ_AVILA_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_AVILA_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_AVILA_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_AVILA_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
return -EINVAL;
switch (type){
- case IRQT_BOTHEDGE:
+ case IRQ_TYPE_EDGE_BOTH:
int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
irq_type = IXP4XX_IRQ_EDGE;
break;
- case IRQT_RISING:
+ case IRQ_TYPE_EDGE_RISING:
int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
irq_type = IXP4XX_IRQ_EDGE;
break;
- case IRQT_FALLING:
+ case IRQ_TYPE_EDGE_FALLING:
int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
irq_type = IXP4XX_IRQ_EDGE;
break;
- case IRQT_HIGH:
+ case IRQ_TYPE_LEVEL_HIGH:
int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
irq_type = IXP4XX_IRQ_LEVEL;
break;
- case IRQT_LOW:
+ case IRQ_TYPE_LEVEL_LOW:
int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
irq_type = IXP4XX_IRQ_LEVEL;
break;
void __init coyote_pci_preinit(void)
{
- set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQT_LOW);
- set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQT_LOW);
+ set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
void __init dsmg600_pci_preinit(void)
{
- set_irq_type(IRQ_DSMG600_PCI_INTA, IRQT_LOW);
- set_irq_type(IRQ_DSMG600_PCI_INTB, IRQT_LOW);
- set_irq_type(IRQ_DSMG600_PCI_INTC, IRQT_LOW);
- set_irq_type(IRQ_DSMG600_PCI_INTD, IRQT_LOW);
- set_irq_type(IRQ_DSMG600_PCI_INTE, IRQT_LOW);
- set_irq_type(IRQ_DSMG600_PCI_INTF, IRQT_LOW);
+ set_irq_type(IRQ_DSMG600_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_DSMG600_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_DSMG600_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_DSMG600_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_DSMG600_PCI_INTE, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_DSMG600_PCI_INTF, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
void __init fsg_pci_preinit(void)
{
- set_irq_type(IRQ_FSG_PCI_INTA, IRQT_LOW);
- set_irq_type(IRQ_FSG_PCI_INTB, IRQT_LOW);
- set_irq_type(IRQ_FSG_PCI_INTC, IRQT_LOW);
+ set_irq_type(IRQ_FSG_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_FSG_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_FSG_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
void __init gateway7001_pci_preinit(void)
{
- set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
- set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
*/
void __init gtwx5715_pci_preinit(void)
{
- set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQT_LOW);
- set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQT_LOW);
- set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQT_LOW);
- set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQT_LOW);
+ set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
void __init ixdp425_pci_preinit(void)
{
- set_irq_type(IRQ_IXDP425_PCI_INTA, IRQT_LOW);
- set_irq_type(IRQ_IXDP425_PCI_INTB, IRQT_LOW);
- set_irq_type(IRQ_IXDP425_PCI_INTC, IRQT_LOW);
- set_irq_type(IRQ_IXDP425_PCI_INTD, IRQT_LOW);
+ set_irq_type(IRQ_IXDP425_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXDP425_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXDP425_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXDP425_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
void __init ixdpg425_pci_preinit(void)
{
- set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW);
- set_irq_type(IRQ_IXP4XX_GPIO7, IRQT_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
void __init nas100d_pci_preinit(void)
{
- set_irq_type(IRQ_NAS100D_PCI_INTA, IRQT_LOW);
- set_irq_type(IRQ_NAS100D_PCI_INTB, IRQT_LOW);
- set_irq_type(IRQ_NAS100D_PCI_INTC, IRQT_LOW);
- set_irq_type(IRQ_NAS100D_PCI_INTD, IRQT_LOW);
- set_irq_type(IRQ_NAS100D_PCI_INTE, IRQT_LOW);
+ set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_NAS100D_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_NAS100D_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_NAS100D_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_NAS100D_PCI_INTE, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
void __init nslu2_pci_preinit(void)
{
- set_irq_type(IRQ_NSLU2_PCI_INTA, IRQT_LOW);
- set_irq_type(IRQ_NSLU2_PCI_INTB, IRQT_LOW);
- set_irq_type(IRQ_NSLU2_PCI_INTC, IRQT_LOW);
+ set_irq_type(IRQ_NSLU2_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_NSLU2_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_NSLU2_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
void __init wg302v2_pci_preinit(void)
{
- set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
- set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC);
switch (type) {
- case IRQT_HIGH:
+ case IRQ_TYPE_LEVEL_HIGH:
mode = IOPC_TM_HIGH;
level_triggered = 1;
break;
- case IRQT_LOW:
+ case IRQ_TYPE_LEVEL_LOW:
mode = IOPC_TM_LOW;
level_triggered = 1;
break;
- case IRQT_RISING:
+ case IRQ_TYPE_EDGE_RISING:
mode = IOPC_TM_RISING;
break;
- case IRQT_FALLING:
+ case IRQ_TYPE_EDGE_FALLING:
mode = IOPC_TM_FALLING;
break;
- case IRQT_BOTHEDGE:
+ case IRQ_TYPE_EDGE_BOTH:
mode = IOPC_TM_EDGE;
break;
default:
irq = _irq - NETX_IRQ_HIF_CHAINED(0);
- if (type & __IRQT_RISEDGE) {
+ if (type & IRQ_TYPE_EDGE_RISING) {
DEBUG_IRQ("rising edges\n");
val |= (1 << 26) << irq;
}
- if (type & __IRQT_FALEDGE) {
+ if (type & IRQ_TYPE_EDGE_FALLING) {
DEBUG_IRQ("falling edges\n");
val &= ~((1 << 26) << irq);
}
- if (type & __IRQT_LOWLVL) {
+ if (type & IRQ_TYPE_LEVEL_LOW) {
DEBUG_IRQ("low level\n");
val &= ~((1 << 26) << irq);
}
- if (type & __IRQT_HIGHLVL) {
+ if (type & IRQ_TYPE_LEVEL_HIGH) {
DEBUG_IRQ("high level\n");
val |= (1 << 26) << irq;
}
return;
}
/* the CF I/O IRQ is really active-low */
- set_irq_type(OMAP_GPIO_IRQ(62), IRQT_FALLING);
+ set_irq_type(OMAP_GPIO_IRQ(62), IRQ_TYPE_EDGE_FALLING);
}
static void __init osk_init_irq(void)
omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */
gpio_request(4, "ts_int");
gpio_direction_input(4);
- set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING);
+ set_irq_type(OMAP_GPIO_IRQ(4), IRQ_TYPE_EDGE_FALLING);
spi_register_board_info(mistral_boardinfo,
ARRAY_SIZE(mistral_boardinfo));
int ret = 0;
gpio_direction_input(OMAP_MPUIO(2));
- set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQT_RISING);
+ set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQ_TYPE_EDGE_RISING);
#ifdef CONFIG_PM
/* share the IRQ in case someone wants to use the
* button for more than wakeup from system sleep.
if (omap_get_gpio_datain(PALMZ71_USBDETECT_GPIO)) {
printk(KERN_INFO "PM: Power cable connected\n");
set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO),
- IRQT_FALLING);
+ IRQ_TYPE_EDGE_FALLING);
} else {
printk(KERN_INFO "PM: Power cable disconnected\n");
set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO),
- IRQT_RISING);
+ IRQ_TYPE_EDGE_RISING);
}
return IRQ_HANDLED;
}
omap_request_gpio(13);
omap_request_gpio(14);
omap_request_gpio(15);
- set_irq_type(OMAP_GPIO_IRQ(12), IRQT_RISING);
- set_irq_type(OMAP_GPIO_IRQ(13), IRQT_RISING);
- set_irq_type(OMAP_GPIO_IRQ(14), IRQT_RISING);
- set_irq_type(OMAP_GPIO_IRQ(15), IRQT_RISING);
+ set_irq_type(OMAP_GPIO_IRQ(12), IRQ_TYPE_EDGE_RISING);
+ set_irq_type(OMAP_GPIO_IRQ(13), IRQ_TYPE_EDGE_RISING);
+ set_irq_type(OMAP_GPIO_IRQ(14), IRQ_TYPE_EDGE_RISING);
+ set_irq_type(OMAP_GPIO_IRQ(15), IRQ_TYPE_EDGE_RISING);
platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
omap_board_config = voiceblue_config;
*/
omap_request_gpio(13);
omap_set_gpio_direction(13, 1);
- set_irq_type(OMAP_GPIO_IRQ(13), IRQT_RISING);
+ set_irq_type(OMAP_GPIO_IRQ(13), IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
}
omap_request_gpio(SW_DOWN_GPIO58);
omap_set_gpio_direction(SW_DOWN_GPIO58, 1);
- set_irq_type(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), IRQT_RISING);
+ set_irq_type(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), IRQ_TYPE_EDGE_RISING);
if (request_irq(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), &apollon_sw_interrupt,
IRQF_SHARED, "enter sw",
&apollon_sw_interrupt))
return;
- set_irq_type(OMAP_GPIO_IRQ(SW_UP_GPIO17), IRQT_RISING);
+ set_irq_type(OMAP_GPIO_IRQ(SW_UP_GPIO17), IRQ_TYPE_EDGE_RISING);
if (request_irq(OMAP_GPIO_IRQ(SW_UP_GPIO17), &apollon_sw_interrupt,
IRQF_SHARED, "up sw",
&apollon_sw_interrupt))
return;
- set_irq_type(OMAP_GPIO_IRQ(SW_DOWN_GPIO58), IRQT_RISING);
+ set_irq_type(OMAP_GPIO_IRQ(SW_DOWN_GPIO58), IRQ_TYPE_EDGE_RISING);
if (request_irq(OMAP_GPIO_IRQ(SW_DOWN_GPIO58), &apollon_sw_interrupt,
IRQF_SHARED, "down sw",
&apollon_sw_interrupt))
pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
if (gpio_request(pin, "PCI Int1") == 0) {
if (gpio_direction_input(pin) == 0) {
- set_irq_type(gpio_to_irq(pin), IRQT_LOW);
+ set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "db88f5281_pci_preinit faield to "
"set_irq_type pin %d\n", pin);
pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
if (gpio_request(pin, "PCI Int2") == 0) {
if (gpio_direction_input(pin) == 0) {
- set_irq_type(gpio_to_irq(pin), IRQT_LOW);
+ set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "db88f5281_pci_preinit faield "
"to set_irq_type pin %d\n", pin);
desc = irq_desc + irq;
switch (type) {
- case IRQT_HIGH:
+ case IRQ_TYPE_LEVEL_HIGH:
desc->handle_irq = handle_level_irq;
desc->status |= IRQ_LEVEL;
orion5x_clrbits(GPIO_IN_POL, (1 << pin));
break;
- case IRQT_LOW:
+ case IRQ_TYPE_LEVEL_LOW:
desc->handle_irq = handle_level_irq;
desc->status |= IRQ_LEVEL;
orion5x_setbits(GPIO_IN_POL, (1 << pin));
break;
- case IRQT_RISING:
+ case IRQ_TYPE_EDGE_RISING:
desc->handle_irq = handle_edge_irq;
desc->status &= ~IRQ_LEVEL;
orion5x_clrbits(GPIO_IN_POL, (1 << pin));
break;
- case IRQT_FALLING:
+ case IRQ_TYPE_EDGE_FALLING:
desc->handle_irq = handle_edge_irq;
desc->status &= ~IRQ_LEVEL;
orion5x_setbits(GPIO_IN_POL, (1 << pin));
break;
- case IRQT_BOTHEDGE:
+ case IRQ_TYPE_EDGE_BOTH:
desc->handle_irq = handle_edge_irq;
desc->status &= ~IRQ_LEVEL;
/*
if (cause & (1 << pin)) {
irq = gpio_to_irq(pin);
desc = irq_desc + irq;
- if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
+ if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
/* Swap polarity (race with GPIO line) */
u32 polarity = readl(GPIO_IN_POL);
polarity ^= 1 << pin;
pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
if (gpio_request(pin, "PCI IntA") == 0) {
if (gpio_direction_input(pin) == 0) {
- set_irq_type(gpio_to_irq(pin), IRQT_LOW);
+ set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "rd88f5182_pci_preinit faield to "
"set_irq_type pin %d\n", pin);
pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
if (gpio_request(pin, "PCI IntB") == 0) {
if (gpio_direction_input(pin) == 0) {
- set_irq_type(gpio_to_irq(pin), IRQT_LOW);
+ set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "rd88f5182_pci_preinit faield to "
"set_irq_type pin %d\n", pin);
pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN;
if (gpio_request(pin, "PCI Int1") == 0) {
if (gpio_direction_input(pin) == 0) {
- set_irq_type(gpio_to_irq(pin), IRQT_LOW);
+ set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "qnap_ts209_pci_preinit failed to "
"set_irq_type pin %d\n", pin);
pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN;
if (gpio_request(pin, "PCI Int2") == 0) {
if (gpio_direction_input(pin) == 0) {
- set_irq_type(gpio_to_irq(pin), IRQT_LOW);
+ set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "qnap_ts209_pci_preinit failed "
"to set_irq_type pin %d\n", pin);
static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
{
switch (type) {
- case IRQT_RISING:
+ case IRQ_TYPE_EDGE_RISING:
__raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */
set_irq_handler(irq, handle_edge_irq);
break;
- case IRQT_FALLING:
+ case IRQ_TYPE_EDGE_FALLING:
__raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */
set_irq_handler(irq, handle_edge_irq);
break;
- case IRQT_LOW:
+ case IRQ_TYPE_LEVEL_LOW:
__raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */
set_irq_handler(irq, handle_level_irq);
break;
- case IRQT_HIGH:
+ case IRQ_TYPE_LEVEL_HIGH:
__raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */
set_irq_handler(irq, handle_level_irq);
break;
- /* IRQT_BOTHEDGE is not supported */
+ /* IRQ_TYPE_EDGE_BOTH is not supported */
default:
printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
return -1;
cmx270_it8152_irq_gpio = irq_gpio;
- set_irq_type(gpio_to_irq(irq_gpio), IRQT_RISING);
+ set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx270_it8152_irq_demux);
}
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
- set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
+ set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
}
}
set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler);
- set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
+ set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
}
#ifdef CONFIG_PM
MST_INTSETCLR = 0;
set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
- set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
+ set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
}
#ifdef CONFIG_PM
if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED, "AC Input Detect", sharpsl_ac_isr)) {
dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin));
}
- else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin),IRQT_BOTHEDGE);
+ else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin),IRQ_TYPE_EDGE_BOTH);
if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED, "Battery Cover", sharpsl_fatal_isr)) {
dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock));
}
- else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock),IRQT_FALLING);
+ else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock),IRQ_TYPE_EDGE_FALLING);
if (sharpsl_pm.machinfo->gpio_fatal) {
if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED, "Fatal Battery", sharpsl_fatal_isr)) {
dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal));
}
- else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal),IRQT_FALLING);
+ else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal),IRQ_TYPE_EDGE_FALLING);
}
if (sharpsl_pm.machinfo->batfull_irq)
if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED, "CO", sharpsl_chrg_full_isr)) {
dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull));
}
- else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull),IRQT_RISING);
+ else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull),IRQ_TYPE_EDGE_RISING);
}
}
[2] = {
.start = TRIZEPS4_ETH_IRQ,
.end = TRIZEPS4_ETH_IRQ,
- .flags = (IORESOURCE_IRQ | IRQT_RISING),
+ .flags = (IORESOURCE_IRQ | IRQ_TYPE_EDGE_RISING),
},
};
static void __init cerf_init_irq(void)
{
sa1100_init_irq();
- set_irq_type(CERF_ETH_IRQ, IRQT_RISING);
+ set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING);
}
static struct map_desc cerf_io_desc[] __initdata = {
set_irq_chip(irq, &h3800_gpio_irqchip);
}
#endif
- set_irq_type(IRQ_GPIO_H3800_ASIC, IRQT_RISING);
+ set_irq_type(IRQ_GPIO_H3800_ASIC, IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(IRQ_GPIO_H3800_ASIC, h3800_IRQ_demux);
}
else
mask = GPIO11_27_MASK(irq);
- if (type == IRQT_PROBE) {
+ if (type == IRQ_TYPE_PROBE) {
if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
return 0;
- type = __IRQT_RISEDGE | __IRQT_FALEDGE;
+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
- if (type & __IRQT_RISEDGE) {
+ if (type & IRQ_TYPE_EDGE_RISING) {
GPIO_IRQ_rising_edge |= mask;
} else
GPIO_IRQ_rising_edge &= ~mask;
- if (type & __IRQT_FALEDGE) {
+ if (type & IRQ_TYPE_EDGE_FALLING) {
GPIO_IRQ_falling_edge |= mask;
} else
GPIO_IRQ_falling_edge &= ~mask;
/*
* Install handler for GPIO25.
*/
- set_irq_type(IRQ_GPIO25, IRQT_RISING);
+ set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler);
/*
GPDR &= ~GPIO_ETH0_IRQ;
- set_irq_type(GPIO_ETH0_IRQ, IRQT_FALLING);
+ set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING);
}
MACHINE_START(PLEB, "PLEB")
pgd_t *pgd;
pmd_t *pmd;
pte_t *pte, entry;
- int ret = 0;
+ int ret;
pgd = pgd_offset(vma->vm_mm, address);
if (pgd_none(*pgd))
pte = pte_offset_map(pmd, address);
entry = *pte;
+ /*
+ * If this page is present, it's actually being shared.
+ */
+ ret = pte_present(entry);
+
/*
* If this page isn't present, or is already setup to
* fault (ie, is old), we can safely ignore any issues.
*/
- if (pte_present(entry) && pte_val(entry) & shared_pte_mask) {
+ if (ret && pte_val(entry) & shared_pte_mask) {
flush_cache_page(vma, address, pte_pfn(entry));
pte_val(entry) &= ~shared_pte_mask;
set_pte_at(vma->vm_mm, address, pte, entry);
flush_tlb_page(vma, address);
- ret = 1;
}
pte_unmap(pte);
return ret;
void __iomem *reg = port->base;
switch (type) {
- case IRQT_RISING:
+ case IRQ_TYPE_EDGE_RISING:
edge = GPIO_INT_RISE_EDGE;
break;
- case IRQT_FALLING:
+ case IRQ_TYPE_EDGE_FALLING:
edge = GPIO_INT_FALL_EDGE;
break;
- case IRQT_LOW:
+ case IRQ_TYPE_LEVEL_LOW:
edge = GPIO_INT_LOW_LEV;
break;
- case IRQT_HIGH:
+ case IRQ_TYPE_LEVEL_HIGH:
edge = GPIO_INT_HIGH_LEV;
break;
- default: /* this includes IRQT_BOTHEDGE */
+ default: /* this includes IRQ_TYPE_EDGE_BOTH */
return -EINVAL;
}
u32 gpio_bit = 1 << gpio;
MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
- trigger & __IRQT_LOWLVL);
+ trigger & IRQ_TYPE_LEVEL_LOW);
MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
- trigger & __IRQT_HIGHLVL);
+ trigger & IRQ_TYPE_LEVEL_HIGH);
MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
- trigger & __IRQT_RISEDGE);
+ trigger & IRQ_TYPE_EDGE_RISING);
MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
- trigger & __IRQT_FALEDGE);
+ trigger & IRQ_TYPE_EDGE_FALLING);
if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
if (trigger != 0)
case METHOD_MPUIO:
reg += OMAP_MPUIO_GPIO_INT_EDGE;
l = __raw_readl(reg);
- if (trigger & __IRQT_RISEDGE)
+ if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
- else if (trigger & __IRQT_FALEDGE)
+ else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_INT_CONTROL;
l = __raw_readl(reg);
- if (trigger & __IRQT_RISEDGE)
+ if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
- else if (trigger & __IRQT_FALEDGE)
+ else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
gpio &= 0x07;
l = __raw_readl(reg);
l &= ~(3 << (gpio << 1));
- if (trigger & __IRQT_RISEDGE)
+ if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 2 << (gpio << 1);
- if (trigger & __IRQT_FALEDGE)
+ if (trigger & IRQ_TYPE_EDGE_FALLING)
l |= 1 << (gpio << 1);
if (trigger)
/* Enable wake-up during idle for dynamic tick */
case METHOD_GPIO_730:
reg += OMAP730_GPIO_INT_CONTROL;
l = __raw_readl(reg);
- if (trigger & __IRQT_RISEDGE)
+ if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
- else if (trigger & __IRQT_FALEDGE)
+ else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
_set_gpio_direction(bank, get_gpio_index(gpio), 1);
_set_gpio_irqenable(bank, gpio, 0);
_clear_gpio_irqstatus(bank, gpio);
- _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
+ _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
}
/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
/* Set trigger to none. You need to enable the desired trigger with
* request_irq() or set_irq_type().
*/
- _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
+ _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
#ifdef CONFIG_ARCH_OMAP15XX
if (bank->method == METHOD_GPIO_1510) {
depends on ARCH_S3C2410
default y if ARCH_S3C2410
select NO_IOPORT
- select HAVE_GPIO_LIB
+ select ARCH_REQUIRE_GPIOLIB
help
Base platform code for any Samsung S3C24XX device
/* Set the external interrupt to pointed trigger type */
switch (type)
{
- case IRQT_NOEDGE:
+ case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
- case IRQT_RISING:
+ case IRQ_TYPE_EDGE_RISING:
newvalue = S3C2410_EXTINT_RISEEDGE;
break;
- case IRQT_FALLING:
+ case IRQ_TYPE_EDGE_FALLING:
newvalue = S3C2410_EXTINT_FALLEDGE;
break;
- case IRQT_BOTHEDGE:
+ case IRQ_TYPE_EDGE_BOTH:
newvalue = S3C2410_EXTINT_BOTHEDGE;
break;
- case IRQT_LOW:
+ case IRQ_TYPE_LEVEL_LOW:
newvalue = S3C2410_EXTINT_LOWLEV;
break;
- case IRQT_HIGH:
+ case IRQ_TYPE_LEVEL_HIGH:
newvalue = S3C2410_EXTINT_HILEV;
break;
select HAVE_IDE
select HAVE_OPROFILE
select HAVE_ARCH_KGDB if !SMP
+ select HAVE_ARCH_TRACEHOOK
# Identify this as a Sparc32 build
config SPARC32
--- /dev/null
+# User exported sparc header files
+include include/asm-generic/Kbuild.asm
+
+header-y += ipcbuf_32.h
+header-y += ipcbuf_64.h
+header-y += posix_types_32.h
+header-y += posix_types_64.h
+header-y += ptrace_32.h
+header-y += ptrace_64.h
+header-y += sigcontext_32.h
+header-y += sigcontext_64.h
+header-y += siginfo_32.h
+header-y += siginfo_64.h
+header-y += signal_32.h
+header-y += signal_64.h
+header-y += stat_32.h
+header-y += stat_64.h
+header-y += statfs_32.h
+header-y += statfs_64.h
+header-y += unistd_32.h
+header-y += unistd_64.h
+
+header-y += apc.h
+header-y += asi.h
+header-y += bpp.h
+header-y += display7seg.h
+header-y += envctrl.h
+header-y += fbio.h
+header-y += jsflash.h
+header-y += openprom.h
+header-y += openprom_32.h
+header-y += openprom_64.h
+header-y += openpromio.h
+header-y += perfctr.h
+header-y += psrcompat.h
+header-y += psr.h
+header-y += pstate.h
+header-y += reg.h
+header-y += reg_32.h
+header-y += reg_64.h
+header-y += traps.h
+header-y += uctx.h
+header-y += utrap.h
+header-y += vfc_ioctls.h
+header-y += watchdog.h
--- /dev/null
+#ifndef AGP_H
+#define AGP_H 1
+
+/* dummy for now */
+
+#define map_page_into_agp(page)
+#define unmap_page_from_agp(page)
+#define flush_agp_cache() mb()
+
+/* Convert a physical address to an address suitable for the GART. */
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
+/* GATT allocation. Returns/accepts GATT kernel virtual address. */
+#define alloc_gatt_pages(order) \
+ ((char *)__get_free_pages(GFP_KERNEL, (order)))
+#define free_gatt_pages(table, order) \
+ free_pages((unsigned long)(table), (order))
+
+#endif
--- /dev/null
+/*
+ * apb.h: Advanced PCI Bridge Configuration Registers and Bits
+ *
+ * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
+ */
+
+#ifndef _SPARC64_APB_H
+#define _SPARC64_APB_H
+
+#define APB_TICK_REGISTER 0xb0
+#define APB_INT_ACK 0xb8
+#define APB_PRIMARY_MASTER_RETRY_LIMIT 0xc0
+#define APB_DMA_ASFR 0xc8
+#define APB_DMA_AFAR 0xd0
+#define APB_PIO_TARGET_RETRY_LIMIT 0xd8
+#define APB_PIO_TARGET_LATENCY_TIMER 0xd9
+#define APB_DMA_TARGET_RETRY_LIMIT 0xda
+#define APB_DMA_TARGET_LATENCY_TIMER 0xdb
+#define APB_SECONDARY_MASTER_RETRY_LIMIT 0xdc
+#define APB_SECONDARY_CONTROL 0xdd
+#define APB_IO_ADDRESS_MAP 0xde
+#define APB_MEM_ADDRESS_MAP 0xdf
+
+#define APB_PCI_CONTROL_LOW 0xe0
+# define APB_PCI_CTL_LOW_ARB_PARK (1 << 21)
+# define APB_PCI_CTL_LOW_ERRINT_EN (1 << 8)
+
+#define APB_PCI_CONTROL_HIGH 0xe4
+# define APB_PCI_CTL_HIGH_SERR (1 << 2)
+# define APB_PCI_CTL_HIGH_ARBITER_EN (1 << 0)
+
+#define APB_PIO_ASFR 0xe8
+#define APB_PIO_AFAR 0xf0
+#define APB_DIAG_REGISTER 0xf8
+
+#endif /* !(_SPARC64_APB_H) */
--- /dev/null
+/* apc - Driver definitions for power management functions
+ * of Aurora Personality Chip (APC) on SPARCstation-4/5 and
+ * derivatives
+ *
+ * Copyright (c) 2001 Eric Brower (ebrower@usa.net)
+ *
+ */
+
+#ifndef _SPARC_APC_H
+#define _SPARC_APC_H
+
+#include <linux/ioctl.h>
+
+#define APC_IOC 'A'
+
+#define APCIOCGFANCTL _IOR(APC_IOC, 0x00, int) /* Get fan speed */
+#define APCIOCSFANCTL _IOW(APC_IOC, 0x01, int) /* Set fan speed */
+
+#define APCIOCGCPWR _IOR(APC_IOC, 0x02, int) /* Get CPOWER state */
+#define APCIOCSCPWR _IOW(APC_IOC, 0x03, int) /* Set CPOWER state */
+
+#define APCIOCGBPORT _IOR(APC_IOC, 0x04, int) /* Get BPORT state */
+#define APCIOCSBPORT _IOW(APC_IOC, 0x05, int) /* Set BPORT state */
+
+/*
+ * Register offsets
+ */
+#define APC_IDLE_REG 0x00
+#define APC_FANCTL_REG 0x20
+#define APC_CPOWER_REG 0x24
+#define APC_BPORT_REG 0x30
+
+#define APC_REGMASK 0x01
+#define APC_BPMASK 0x03
+
+/*
+ * IDLE - CPU standby values (set to initiate standby)
+ */
+#define APC_IDLE_ON 0x01
+
+/*
+ * FANCTL - Fan speed control state values
+ */
+#define APC_FANCTL_HI 0x00 /* Fan speed high */
+#define APC_FANCTL_LO 0x01 /* Fan speed low */
+
+/*
+ * CPWR - Convenience power outlet state values
+ */
+#define APC_CPOWER_ON 0x00 /* Conv power on */
+#define APC_CPOWER_OFF 0x01 /* Conv power off */
+
+/*
+ * BPA/BPB - Read-Write "Bit Ports" state values (reset to 0 at power-on)
+ *
+ * WARNING: Internal usage of bit ports is platform dependent--
+ * don't modify BPORT settings unless you know what you are doing.
+ *
+ * On SS5 BPA seems to toggle onboard ethernet loopback... -E
+ */
+#define APC_BPORT_A 0x01 /* Bit Port A */
+#define APC_BPORT_B 0x02 /* Bit Port B */
+
+#endif /* !(_SPARC_APC_H) */
--- /dev/null
+#ifndef _SPARC_ASI_H
+#define _SPARC_ASI_H
+
+/* asi.h: Address Space Identifier values for the sparc.
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ *
+ * Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au)
+ * Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su>
+ */
+
+/* The first batch are for the sun4c. */
+
+#define ASI_NULL1 0x00
+#define ASI_NULL2 0x01
+
+/* sun4c and sun4 control registers and mmu/vac ops */
+#define ASI_CONTROL 0x02
+#define ASI_SEGMAP 0x03
+#define ASI_PTE 0x04
+#define ASI_HWFLUSHSEG 0x05
+#define ASI_HWFLUSHPAGE 0x06
+#define ASI_REGMAP 0x06
+#define ASI_HWFLUSHCONTEXT 0x07
+
+#define ASI_USERTXT 0x08
+#define ASI_KERNELTXT 0x09
+#define ASI_USERDATA 0x0a
+#define ASI_KERNELDATA 0x0b
+
+/* VAC Cache flushing on sun4c and sun4 */
+#define ASI_FLUSHSEG 0x0c
+#define ASI_FLUSHPG 0x0d
+#define ASI_FLUSHCTX 0x0e
+
+/* SPARCstation-5: only 6 bits are decoded. */
+/* wo = Write Only, rw = Read Write; */
+/* ss = Single Size, as = All Sizes; */
+#define ASI_M_RES00 0x00 /* Don't touch... */
+#define ASI_M_UNA01 0x01 /* Same here... */
+#define ASI_M_MXCC 0x02 /* Access to TI VIKING MXCC registers */
+#define ASI_M_FLUSH_PROBE 0x03 /* Reference MMU Flush/Probe; rw, ss */
+#define ASI_M_MMUREGS 0x04 /* MMU Registers; rw, ss */
+#define ASI_M_TLBDIAG 0x05 /* MMU TLB only Diagnostics */
+#define ASI_M_DIAGS 0x06 /* Reference MMU Diagnostics */
+#define ASI_M_IODIAG 0x07 /* MMU I/O TLB only Diagnostics */
+#define ASI_M_USERTXT 0x08 /* Same as ASI_USERTXT; rw, as */
+#define ASI_M_KERNELTXT 0x09 /* Same as ASI_KERNELTXT; rw, as */
+#define ASI_M_USERDATA 0x0A /* Same as ASI_USERDATA; rw, as */
+#define ASI_M_KERNELDATA 0x0B /* Same as ASI_KERNELDATA; rw, as */
+#define ASI_M_TXTC_TAG 0x0C /* Instruction Cache Tag; rw, ss */
+#define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */
+#define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */
+#define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */
+
+/* The following cache flushing ASIs work only with the 'sta'
+ * instruction. Results are unpredictable for 'swap' and 'ldstuba',
+ * so don't do it.
+ */
+
+/* These ASI flushes affect external caches too. */
+#define ASI_M_FLUSH_PAGE 0x10 /* Flush I&D Cache Line (page); wo, ss */
+#define ASI_M_FLUSH_SEG 0x11 /* Flush I&D Cache Line (seg); wo, ss */
+#define ASI_M_FLUSH_REGION 0x12 /* Flush I&D Cache Line (region); wo, ss */
+#define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */
+#define ASI_M_FLUSH_USER 0x14 /* Flush I&D Cache Line (user); wo, ss */
+
+/* Block-copy operations are available only on certain V8 cpus. */
+#define ASI_M_BCOPY 0x17 /* Block copy */
+
+/* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */
+#define ASI_M_IFLUSH_PAGE 0x18 /* Flush I Cache Line (page); wo, ss */
+#define ASI_M_IFLUSH_SEG 0x19 /* Flush I Cache Line (seg); wo, ss */
+#define ASI_M_IFLUSH_REGION 0x1A /* Flush I Cache Line (region); wo, ss */
+#define ASI_M_IFLUSH_CTX 0x1B /* Flush I Cache Line (context); wo, ss */
+#define ASI_M_IFLUSH_USER 0x1C /* Flush I Cache Line (user); wo, ss */
+
+/* Block-fill operations are available on certain V8 cpus */
+#define ASI_M_BFILL 0x1F
+
+/* This allows direct access to main memory, actually 0x20 to 0x2f are
+ * the available ASI's for physical ram pass-through, but I don't have
+ * any idea what the other ones do....
+ */
+
+#define ASI_M_BYPASS 0x20 /* Reference MMU bypass; rw, as */
+#define ASI_M_FBMEM 0x29 /* Graphics card frame buffer access */
+#define ASI_M_VMEUS 0x2A /* VME user 16-bit access */
+#define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */
+#define ASI_M_VMEUT 0x2C /* VME user 32-bit access */
+#define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */
+#define ASI_M_SBUS 0x2E /* Direct SBus access */
+#define ASI_M_CTL 0x2F /* Control Space (ECC and MXCC are here) */
+
+
+/* This is ROSS HyperSparc only. */
+#define ASI_M_FLUSH_IWHOLE 0x31 /* Flush entire ICACHE; wo, ss */
+
+/* Tsunami/Viking/TurboSparc i/d cache flash clear. */
+#define ASI_M_IC_FLCLEAR 0x36
+#define ASI_M_DC_FLCLEAR 0x37
+
+#define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */
+
+#define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */
+/* only available on SuperSparc I */
+/* #define ASI_M_VIKING_TMP2 0x41 */ /* Emulation temporary 2 on Viking */
+
+#define ASI_M_ACTION 0x4c /* Breakpoint Action Register (GNU/Viking) */
+
+/* V9 Architecture mandary ASIs. */
+#define ASI_N 0x04 /* Nucleus */
+#define ASI_NL 0x0c /* Nucleus, little endian */
+#define ASI_AIUP 0x10 /* Primary, user */
+#define ASI_AIUS 0x11 /* Secondary, user */
+#define ASI_AIUPL 0x18 /* Primary, user, little endian */
+#define ASI_AIUSL 0x19 /* Secondary, user, little endian */
+#define ASI_P 0x80 /* Primary, implicit */
+#define ASI_S 0x81 /* Secondary, implicit */
+#define ASI_PNF 0x82 /* Primary, no fault */
+#define ASI_SNF 0x83 /* Secondary, no fault */
+#define ASI_PL 0x88 /* Primary, implicit, l-endian */
+#define ASI_SL 0x89 /* Secondary, implicit, l-endian */
+#define ASI_PNFL 0x8a /* Primary, no fault, l-endian */
+#define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
+
+/* SpitFire and later extended ASIs. The "(III)" marker designates
+ * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates
+ * Chip Multi Threading specific ASIs. "(NG)" designates Niagara specific
+ * ASIs, "(4V)" designates SUN4V specific ASIs.
+ */
+#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */
+#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
+#define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */
+#define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */
+#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/
+#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
+#define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/
+#define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */
+#define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */
+#define ASI_MMU 0x21 /* (4V) MMU Context Registers */
+#define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
+ * secondary, user
+ */
+#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */
+#define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */
+#define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */
+#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */
+#define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */
+#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
+#define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */
+#define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */
+#define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */
+#define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */
+#define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */
+#define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */
+#define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */
+#define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */
+#define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */
+#define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */
+#define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */
+#define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */
+#define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */
+#define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */
+#define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */
+#define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */
+#define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */
+#define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */
+#define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */
+#define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */
+#define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */
+#define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */
+#define ASI_LSU_CONTROL 0x45 /* Load-store control unit */
+#define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */
+#define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */
+#define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/
+#define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */
+#define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */
+#define ASI_UPA_CONFIG 0x4a /* UPA config space */
+#define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */
+#define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */
+#define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */
+#define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */
+#define ASI_AFSR 0x4c /* Async fault status register */
+#define ASI_AFAR 0x4d /* Async fault address register */
+#define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */
+#define ASI_IMMU 0x50 /* Insn-MMU main register space */
+#define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */
+#define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */
+#define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */
+#define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */
+#define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */
+#define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */
+#define ASI_DMMU 0x58 /* Data-MMU main register space */
+#define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */
+#define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */
+#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */
+#define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */
+#define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */
+#define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */
+#define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */
+#define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */
+#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */
+#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */
+#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */
+#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */
+#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */
+#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */
+#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */
+#define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */
+#define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/
+#define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */
+#define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */
+#define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */
+#define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */
+#define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */
+#define ASI_EC_W 0x76 /* E-cache diag write access */
+#define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */
+#define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */
+#define ASI_INTR_W 0x77 /* IRQ vector dispatch write */
+#define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */
+#define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */
+#define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/
+#define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/
+#define ASI_EC_R 0x7e /* E-cache diag read access */
+#define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */
+#define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */
+#define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */
+#define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/
+#define ASI_INTR_R 0x7f /* IRQ vector dispatch read */
+#define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */
+#define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */
+#define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
+#define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */
+#define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */
+#define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */
+#define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */
+#define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */
+#define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */
+#define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */
+#define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */
+#define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */
+#define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */
+#define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */
+#define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */
+#define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */
+#define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */
+#define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */
+#define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/
+#define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */
+#define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/
+#define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */
+#define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */
+#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load,
+ * primary, implicit
+ */
+#define ASI_BLK_P 0xf0 /* Primary, blk ld/st */
+#define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */
+#define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */
+#define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */
+
+#endif /* _SPARC_ASI_H */
--- /dev/null
+/* asmmacro.h: Assembler macros.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu)
+ */
+
+#ifndef _SPARC_ASMMACRO_H
+#define _SPARC_ASMMACRO_H
+
+#include <asm/btfixup.h>
+#include <asm/asi.h>
+
+#define GET_PROCESSOR4M_ID(reg) \
+ rd %tbr, %reg; \
+ srl %reg, 12, %reg; \
+ and %reg, 3, %reg;
+
+#define GET_PROCESSOR4D_ID(reg) \
+ lda [%g0] ASI_M_VIKING_TMP1, %reg;
+
+/* All trap entry points _must_ begin with this macro or else you
+ * lose. It makes sure the kernel has a proper window so that
+ * c-code can be called.
+ */
+#define SAVE_ALL_HEAD \
+ sethi %hi(trap_setup), %l4; \
+ jmpl %l4 + %lo(trap_setup), %l6;
+#define SAVE_ALL \
+ SAVE_ALL_HEAD \
+ nop;
+
+/* All traps low-level code here must end with this macro. */
+#define RESTORE_ALL b ret_trap_entry; clr %l6;
+
+/* sun4 probably wants half word accesses to ASI_SEGMAP, while sun4c+
+ likes byte accesses. These are to avoid ifdef mania. */
+
+#ifdef CONFIG_SUN4
+#define lduXa lduha
+#define stXa stha
+#else
+#define lduXa lduba
+#define stXa stba
+#endif
+
+#endif /* !(_SPARC_ASMMACRO_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_ATOMIC_H
+#define ___ASM_SPARC_ATOMIC_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/atomic_64.h>
+#else
+#include <asm/atomic_32.h>
+#endif
+#endif
--- /dev/null
+/* atomic.h: These still suck, but the I-cache hit rate is higher.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 2000 Anton Blanchard (anton@linuxcare.com.au)
+ * Copyright (C) 2007 Kyle McMartin (kyle@parisc-linux.org)
+ *
+ * Additions by Keith M Wesolowski (wesolows@foobazco.org) based
+ * on asm-parisc/atomic.h Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>.
+ */
+
+#ifndef __ARCH_SPARC_ATOMIC__
+#define __ARCH_SPARC_ATOMIC__
+
+#include <linux/types.h>
+
+typedef struct { volatile int counter; } atomic_t;
+
+#ifdef __KERNEL__
+
+#define ATOMIC_INIT(i) { (i) }
+
+extern int __atomic_add_return(int, atomic_t *);
+extern int atomic_cmpxchg(atomic_t *, int, int);
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+extern int atomic_add_unless(atomic_t *, int, int);
+extern void atomic_set(atomic_t *, int);
+
+#define atomic_read(v) ((v)->counter)
+
+#define atomic_add(i, v) ((void)__atomic_add_return( (int)(i), (v)))
+#define atomic_sub(i, v) ((void)__atomic_add_return(-(int)(i), (v)))
+#define atomic_inc(v) ((void)__atomic_add_return( 1, (v)))
+#define atomic_dec(v) ((void)__atomic_add_return( -1, (v)))
+
+#define atomic_add_return(i, v) (__atomic_add_return( (int)(i), (v)))
+#define atomic_sub_return(i, v) (__atomic_add_return(-(int)(i), (v)))
+#define atomic_inc_return(v) (__atomic_add_return( 1, (v)))
+#define atomic_dec_return(v) (__atomic_add_return( -1, (v)))
+
+#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
+
+/*
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+
+#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
+#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
+
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
+/* This is the old 24-bit implementation. It's still used internally
+ * by some sparc-specific code, notably the semaphore implementation.
+ */
+typedef struct { volatile int counter; } atomic24_t;
+
+#ifndef CONFIG_SMP
+
+#define ATOMIC24_INIT(i) { (i) }
+#define atomic24_read(v) ((v)->counter)
+#define atomic24_set(v, i) (((v)->counter) = i)
+
+#else
+/* We do the bulk of the actual work out of line in two common
+ * routines in assembler, see arch/sparc/lib/atomic.S for the
+ * "fun" details.
+ *
+ * For SMP the trick is you embed the spin lock byte within
+ * the word, use the low byte so signedness is easily retained
+ * via a quick arithmetic shift. It looks like this:
+ *
+ * ----------------------------------------
+ * | signed 24-bit counter value | lock | atomic_t
+ * ----------------------------------------
+ * 31 8 7 0
+ */
+
+#define ATOMIC24_INIT(i) { ((i) << 8) }
+
+static inline int atomic24_read(const atomic24_t *v)
+{
+ int ret = v->counter;
+
+ while(ret & 0xff)
+ ret = v->counter;
+
+ return ret >> 8;
+}
+
+#define atomic24_set(v, i) (((v)->counter) = ((i) << 8))
+#endif
+
+static inline int __atomic24_add(int i, atomic24_t *v)
+{
+ register volatile int *ptr asm("g1");
+ register int increment asm("g2");
+ register int tmp1 asm("g3");
+ register int tmp2 asm("g4");
+ register int tmp3 asm("g7");
+
+ ptr = &v->counter;
+ increment = i;
+
+ __asm__ __volatile__(
+ "mov %%o7, %%g4\n\t"
+ "call ___atomic24_add\n\t"
+ " add %%o7, 8, %%o7\n"
+ : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
+ : "0" (increment), "r" (ptr)
+ : "memory", "cc");
+
+ return increment;
+}
+
+static inline int __atomic24_sub(int i, atomic24_t *v)
+{
+ register volatile int *ptr asm("g1");
+ register int increment asm("g2");
+ register int tmp1 asm("g3");
+ register int tmp2 asm("g4");
+ register int tmp3 asm("g7");
+
+ ptr = &v->counter;
+ increment = i;
+
+ __asm__ __volatile__(
+ "mov %%o7, %%g4\n\t"
+ "call ___atomic24_sub\n\t"
+ " add %%o7, 8, %%o7\n"
+ : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
+ : "0" (increment), "r" (ptr)
+ : "memory", "cc");
+
+ return increment;
+}
+
+#define atomic24_add(i, v) ((void)__atomic24_add((i), (v)))
+#define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v)))
+
+#define atomic24_dec_return(v) __atomic24_sub(1, (v))
+#define atomic24_inc_return(v) __atomic24_add(1, (v))
+
+#define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0)
+#define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0)
+
+#define atomic24_inc(v) ((void)__atomic24_add(1, (v)))
+#define atomic24_dec(v) ((void)__atomic24_sub(1, (v)))
+
+#define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0)
+
+/* Atomic operations are already serializing */
+#define smp_mb__before_atomic_dec() barrier()
+#define smp_mb__after_atomic_dec() barrier()
+#define smp_mb__before_atomic_inc() barrier()
+#define smp_mb__after_atomic_inc() barrier()
+
+#endif /* !(__KERNEL__) */
+
+#include <asm-generic/atomic.h>
+#endif /* !(__ARCH_SPARC_ATOMIC__) */
--- /dev/null
+/* atomic.h: Thankfully the V9 is at least reasonable for this
+ * stuff.
+ *
+ * Copyright (C) 1996, 1997, 2000 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef __ARCH_SPARC64_ATOMIC__
+#define __ARCH_SPARC64_ATOMIC__
+
+#include <linux/types.h>
+#include <asm/system.h>
+
+typedef struct { volatile int counter; } atomic_t;
+typedef struct { volatile __s64 counter; } atomic64_t;
+
+#define ATOMIC_INIT(i) { (i) }
+#define ATOMIC64_INIT(i) { (i) }
+
+#define atomic_read(v) ((v)->counter)
+#define atomic64_read(v) ((v)->counter)
+
+#define atomic_set(v, i) (((v)->counter) = i)
+#define atomic64_set(v, i) (((v)->counter) = i)
+
+extern void atomic_add(int, atomic_t *);
+extern void atomic64_add(int, atomic64_t *);
+extern void atomic_sub(int, atomic_t *);
+extern void atomic64_sub(int, atomic64_t *);
+
+extern int atomic_add_ret(int, atomic_t *);
+extern int atomic64_add_ret(int, atomic64_t *);
+extern int atomic_sub_ret(int, atomic_t *);
+extern int atomic64_sub_ret(int, atomic64_t *);
+
+#define atomic_dec_return(v) atomic_sub_ret(1, v)
+#define atomic64_dec_return(v) atomic64_sub_ret(1, v)
+
+#define atomic_inc_return(v) atomic_add_ret(1, v)
+#define atomic64_inc_return(v) atomic64_add_ret(1, v)
+
+#define atomic_sub_return(i, v) atomic_sub_ret(i, v)
+#define atomic64_sub_return(i, v) atomic64_sub_ret(i, v)
+
+#define atomic_add_return(i, v) atomic_add_ret(i, v)
+#define atomic64_add_return(i, v) atomic64_add_ret(i, v)
+
+/*
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
+
+#define atomic_sub_and_test(i, v) (atomic_sub_ret(i, v) == 0)
+#define atomic64_sub_and_test(i, v) (atomic64_sub_ret(i, v) == 0)
+
+#define atomic_dec_and_test(v) (atomic_sub_ret(1, v) == 0)
+#define atomic64_dec_and_test(v) (atomic64_sub_ret(1, v) == 0)
+
+#define atomic_inc(v) atomic_add(1, v)
+#define atomic64_inc(v) atomic64_add(1, v)
+
+#define atomic_dec(v) atomic_sub(1, v)
+#define atomic64_dec(v) atomic64_sub(1, v)
+
+#define atomic_add_negative(i, v) (atomic_add_ret(i, v) < 0)
+#define atomic64_add_negative(i, v) (atomic64_add_ret(i, v) < 0)
+
+#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+
+static inline int atomic_add_unless(atomic_t *v, int a, int u)
+{
+ int c, old;
+ c = atomic_read(v);
+ for (;;) {
+ if (unlikely(c == (u)))
+ break;
+ old = atomic_cmpxchg((v), c, c + (a));
+ if (likely(old == c))
+ break;
+ c = old;
+ }
+ return c != (u);
+}
+
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
+#define atomic64_cmpxchg(v, o, n) \
+ ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
+#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
+
+static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+ long c, old;
+ c = atomic64_read(v);
+ for (;;) {
+ if (unlikely(c == (u)))
+ break;
+ old = atomic64_cmpxchg((v), c, c + (a));
+ if (likely(old == c))
+ break;
+ c = old;
+ }
+ return c != (u);
+}
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
+/* Atomic operations are already serializing */
+#ifdef CONFIG_SMP
+#define smp_mb__before_atomic_dec() membar_storeload_loadload();
+#define smp_mb__after_atomic_dec() membar_storeload_storestore();
+#define smp_mb__before_atomic_inc() membar_storeload_loadload();
+#define smp_mb__after_atomic_inc() membar_storeload_storestore();
+#else
+#define smp_mb__before_atomic_dec() barrier()
+#define smp_mb__after_atomic_dec() barrier()
+#define smp_mb__before_atomic_inc() barrier()
+#define smp_mb__after_atomic_inc() barrier()
+#endif
+
+#include <asm-generic/atomic.h>
+#endif /* !(__ARCH_SPARC64_ATOMIC__) */
--- /dev/null
+#ifndef ___ASM_SPARC_AUXIO_H
+#define ___ASM_SPARC_AUXIO_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/auxio_64.h>
+#else
+#include <asm/auxio_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * auxio.h: Definitions and code for the Auxiliary I/O register.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_AUXIO_H
+#define _SPARC_AUXIO_H
+
+#include <asm/system.h>
+#include <asm/vaddrs.h>
+
+/* This register is an unsigned char in IO space. It does two things.
+ * First, it is used to control the front panel LED light on machines
+ * that have it (good for testing entry points to trap handlers and irq's)
+ * Secondly, it controls various floppy drive parameters.
+ */
+#define AUXIO_ORMEIN 0xf0 /* All writes must set these bits. */
+#define AUXIO_ORMEIN4M 0xc0 /* sun4m - All writes must set these bits. */
+#define AUXIO_FLPY_DENS 0x20 /* Floppy density, high if set. Read only. */
+#define AUXIO_FLPY_DCHG 0x10 /* A disk change occurred. Read only. */
+#define AUXIO_EDGE_ON 0x10 /* sun4m - On means Jumper block is in. */
+#define AUXIO_FLPY_DSEL 0x08 /* Drive select/start-motor. Write only. */
+#define AUXIO_LINK_TEST 0x08 /* sun4m - On means TPE Carrier detect. */
+
+/* Set the following to one, then zero, after doing a pseudo DMA transfer. */
+#define AUXIO_FLPY_TCNT 0x04 /* Floppy terminal count. Write only. */
+
+/* Set the following to zero to eject the floppy. */
+#define AUXIO_FLPY_EJCT 0x02 /* Eject floppy disk. Write only. */
+#define AUXIO_LED 0x01 /* On if set, off if unset. Read/Write */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * NOTE: these routines are implementation dependent--
+ * understand the hardware you are querying!
+ */
+extern void set_auxio(unsigned char bits_on, unsigned char bits_off);
+extern unsigned char get_auxio(void); /* .../asm/floppy.h */
+
+/*
+ * The following routines are provided for driver-compatibility
+ * with sparc64 (primarily sunlance.c)
+ */
+
+#define AUXIO_LTE_ON 1
+#define AUXIO_LTE_OFF 0
+
+/* auxio_set_lte - Set Link Test Enable (TPE Link Detect)
+ *
+ * on - AUXIO_LTE_ON or AUXIO_LTE_OFF
+ */
+#define auxio_set_lte(on) \
+do { \
+ if(on) { \
+ set_auxio(AUXIO_LINK_TEST, 0); \
+ } else { \
+ set_auxio(0, AUXIO_LINK_TEST); \
+ } \
+} while (0)
+
+#define AUXIO_LED_ON 1
+#define AUXIO_LED_OFF 0
+
+/* auxio_set_led - Set system front panel LED
+ *
+ * on - AUXIO_LED_ON or AUXIO_LED_OFF
+ */
+#define auxio_set_led(on) \
+do { \
+ if(on) { \
+ set_auxio(AUXIO_LED, 0); \
+ } else { \
+ set_auxio(0, AUXIO_LED); \
+ } \
+} while (0)
+
+#endif /* !(__ASSEMBLY__) */
+
+
+/* AUXIO2 (Power Off Control) */
+extern __volatile__ unsigned char * auxio_power_register;
+
+#define AUXIO_POWER_DETECT_FAILURE 32
+#define AUXIO_POWER_CLEAR_FAILURE 2
+#define AUXIO_POWER_OFF 1
+
+
+#endif /* !(_SPARC_AUXIO_H) */
--- /dev/null
+/*
+ * auxio.h: Definitions and code for the Auxiliary I/O registers.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ *
+ * Refactoring for unified NCR/PCIO support 2002 Eric Brower (ebrower@usa.net)
+ */
+#ifndef _SPARC64_AUXIO_H
+#define _SPARC64_AUXIO_H
+
+/* AUXIO implementations:
+ * sbus-based NCR89C105 "Slavio"
+ * LED/Floppy (AUX1) register
+ * Power (AUX2) register
+ *
+ * ebus-based auxio on PCIO
+ * LED Auxio Register
+ * Power Auxio Register
+ *
+ * Register definitions from NCR _NCR89C105 Chip Specification_
+ *
+ * SLAVIO AUX1 @ 0x1900000
+ * -------------------------------------------------
+ * | (R) | (R) | D | (R) | E | M | T | L |
+ * -------------------------------------------------
+ * (R) - bit 7:6,4 are reserved and should be masked in s/w
+ * D - Floppy Density Sense (1=high density) R/O
+ * E - Link Test Enable, directly reflected on AT&T 7213 LTE pin
+ * M - Monitor/Mouse Mux, directly reflected on MON_MSE_MUX pin
+ * T - Terminal Count: sends TC pulse to 82077 floppy controller
+ * L - System LED on front panel (0=off, 1=on)
+ */
+#define AUXIO_AUX1_MASK 0xc0 /* Mask bits */
+#define AUXIO_AUX1_FDENS 0x20 /* Floppy Density Sense */
+#define AUXIO_AUX1_LTE 0x08 /* Link Test Enable */
+#define AUXIO_AUX1_MMUX 0x04 /* Monitor/Mouse Mux */
+#define AUXIO_AUX1_FTCNT 0x02 /* Terminal Count, */
+#define AUXIO_AUX1_LED 0x01 /* System LED */
+
+/* SLAVIO AUX2 @ 0x1910000
+ * -------------------------------------------------
+ * | (R) | (R) | D | (R) | (R) | (R) | C | F |
+ * -------------------------------------------------
+ * (R) - bits 7:6,4:2 are reserved and should be masked in s/w
+ * D - Power Failure Detect (1=power fail)
+ * C - Clear Power Failure Detect Int (1=clear)
+ * F - Power Off (1=power off)
+ */
+#define AUXIO_AUX2_MASK 0xdc /* Mask Bits */
+#define AUXIO_AUX2_PFAILDET 0x20 /* Power Fail Detect */
+#define AUXIO_AUX2_PFAILCLR 0x02 /* Clear Pwr Fail Det Intr */
+#define AUXIO_AUX2_PWR_OFF 0x01 /* Power Off */
+
+/* Register definitions from Sun Microsystems _PCIO_ p/n 802-7837
+ *
+ * PCIO LED Auxio @ 0x726000
+ * -------------------------------------------------
+ * | 31:1 Unused | LED |
+ * -------------------------------------------------
+ * Bits 31:1 unused
+ * LED - System LED on front panel (0=off, 1=on)
+ */
+#define AUXIO_PCIO_LED 0x01 /* System LED */
+
+/* PCIO Power Auxio @ 0x724000
+ * -------------------------------------------------
+ * | 31:2 Unused | CPO | SPO |
+ * -------------------------------------------------
+ * Bits 31:2 unused
+ * CPO - Courtesy Power Off (1=off)
+ * SPO - System Power Off (1=off)
+ */
+#define AUXIO_PCIO_CPWR_OFF 0x02 /* Courtesy Power Off */
+#define AUXIO_PCIO_SPWR_OFF 0x01 /* System Power Off */
+
+#ifndef __ASSEMBLY__
+
+extern void __iomem *auxio_register;
+
+#define AUXIO_LTE_ON 1
+#define AUXIO_LTE_OFF 0
+
+/* auxio_set_lte - Set Link Test Enable (TPE Link Detect)
+ *
+ * on - AUXIO_LTE_ON or AUXIO_LTE_OFF
+ */
+extern void auxio_set_lte(int on);
+
+#define AUXIO_LED_ON 1
+#define AUXIO_LED_OFF 0
+
+/* auxio_set_led - Set system front panel LED
+ *
+ * on - AUXIO_LED_ON or AUXIO_LED_OFF
+ */
+extern void auxio_set_led(int on);
+
+#endif /* ifndef __ASSEMBLY__ */
+
+#endif /* !(_SPARC64_AUXIO_H) */
--- /dev/null
+#ifndef __ASMSPARC_AUXVEC_H
+#define __ASMSPARC_AUXVEC_H
+
+#endif /* !(__ASMSPARC_AUXVEC_H) */
--- /dev/null
+#ifndef _SPARC64_BACKOFF_H
+#define _SPARC64_BACKOFF_H
+
+#define BACKOFF_LIMIT (4 * 1024)
+
+#ifdef CONFIG_SMP
+
+#define BACKOFF_SETUP(reg) \
+ mov 1, reg
+
+#define BACKOFF_SPIN(reg, tmp, label) \
+ mov reg, tmp; \
+88: brnz,pt tmp, 88b; \
+ sub tmp, 1, tmp; \
+ set BACKOFF_LIMIT, tmp; \
+ cmp reg, tmp; \
+ bg,pn %xcc, label; \
+ nop; \
+ ba,pt %xcc, label; \
+ sllx reg, 1, reg;
+
+#else
+
+#define BACKOFF_SETUP(reg)
+#define BACKOFF_SPIN(reg, tmp, label) \
+ ba,pt %xcc, label; \
+ nop;
+
+#endif
+
+#endif /* _SPARC64_BACKOFF_H */
--- /dev/null
+/*
+ * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
+ * systems.
+ *
+ * Copyright (C) 2000 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef _SPARC64_BBC_H
+#define _SPARC64_BBC_H
+
+/* Register sizes are indicated by "B" (Byte, 1-byte),
+ * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
+ * "Q" (Quad, 8 bytes) inside brackets.
+ */
+
+#define BBC_AID 0x00 /* [B] Agent ID */
+#define BBC_DEVP 0x01 /* [B] Device Present */
+#define BBC_ARB 0x02 /* [B] Arbitration */
+#define BBC_QUIESCE 0x03 /* [B] Quiesce */
+#define BBC_WDACTION 0x04 /* [B] Watchdog Action */
+#define BBC_SPG 0x06 /* [B] Soft POR Gen */
+#define BBC_SXG 0x07 /* [B] Soft XIR Gen */
+#define BBC_PSRC 0x08 /* [W] POR Source */
+#define BBC_XSRC 0x0c /* [B] XIR Source */
+#define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/
+#define BBC_ES_CTRL 0x0e /* [H] Energy Star Control */
+#define BBC_ES_ACT 0x10 /* [W] E* Assert Change Time */
+#define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
+#define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
+#define BBC_ES_ABT 0x16 /* [H] E* Assert Bypass Time */
+#define BBC_ES_PST 0x18 /* [W] E* PLL Settle Time */
+#define BBC_ES_FSL 0x1c /* [W] E* Frequency Switch Latency*/
+#define BBC_EBUST 0x20 /* [Q] EBUS Timing */
+#define BBC_JTAG_CMD 0x28 /* [W] JTAG+ Command */
+#define BBC_JTAG_CTRL 0x2c /* [B] JTAG+ Control */
+#define BBC_I2C_SEL 0x2d /* [B] I2C Selection */
+#define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
+#define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
+#define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
+#define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
+#define BBC_KBD_BEEP 0x32 /* [B] Keyboard Beep */
+#define BBC_KBD_BCNT 0x34 /* [W] Keyboard Beep Counter */
+
+#define BBC_REGS_SIZE 0x40
+
+/* There is a 2K scratch ram area at offset 0x80000 but I doubt
+ * we will use it for anything.
+ */
+
+/* Agent ID register. This register shows the Safari Agent ID
+ * for the processors. The value returned depends upon which
+ * cpu is reading the register.
+ */
+#define BBC_AID_ID 0x07 /* Safari ID */
+#define BBC_AID_RESV 0xf8 /* Reserved */
+
+/* Device Present register. One can determine which cpus are actually
+ * present in the machine by interrogating this register.
+ */
+#define BBC_DEVP_CPU0 0x01 /* Processor 0 present */
+#define BBC_DEVP_CPU1 0x02 /* Processor 1 present */
+#define BBC_DEVP_CPU2 0x04 /* Processor 2 present */
+#define BBC_DEVP_CPU3 0x08 /* Processor 3 present */
+#define BBC_DEVP_RESV 0xf0 /* Reserved */
+
+/* Arbitration register. This register is used to block access to
+ * the BBC from a particular cpu.
+ */
+#define BBC_ARB_CPU0 0x01 /* Enable cpu 0 BBC arbitratrion */
+#define BBC_ARB_CPU1 0x02 /* Enable cpu 1 BBC arbitratrion */
+#define BBC_ARB_CPU2 0x04 /* Enable cpu 2 BBC arbitratrion */
+#define BBC_ARB_CPU3 0x08 /* Enable cpu 3 BBC arbitratrion */
+#define BBC_ARB_RESV 0xf0 /* Reserved */
+
+/* Quiesce register. Bus and BBC segments for cpus can be disabled
+ * with this register, ie. for hot plugging.
+ */
+#define BBC_QUIESCE_S02 0x01 /* Quiesce Safari segment for cpu 0 and 2 */
+#define BBC_QUIESCE_S13 0x02 /* Quiesce Safari segment for cpu 1 and 3 */
+#define BBC_QUIESCE_B02 0x04 /* Quiesce BBC segment for cpu 0 and 2 */
+#define BBC_QUIESCE_B13 0x08 /* Quiesce BBC segment for cpu 1 and 3 */
+#define BBC_QUIESCE_FD0 0x10 /* Disable Fatal_Error[0] reporting */
+#define BBC_QUIESCE_FD1 0x20 /* Disable Fatal_Error[1] reporting */
+#define BBC_QUIESCE_FD2 0x40 /* Disable Fatal_Error[2] reporting */
+#define BBC_QUIESCE_FD3 0x80 /* Disable Fatal_Error[3] reporting */
+
+/* Watchdog Action register. When the watchdog device timer expires
+ * a line is enabled to the BBC. The action BBC takes when this line
+ * is asserted can be controlled by this regiser.
+ */
+#define BBC_WDACTION_RST 0x01 /* When set, watchdog causes system reset.
+ * When clear, BBC ignores watchdog signal.
+ */
+#define BBC_WDACTION_RESV 0xfe /* Reserved */
+
+/* Soft_POR_GEN register. The POR (Power On Reset) signal may be asserted
+ * for specific processors or all processors via this register.
+ */
+#define BBC_SPG_CPU0 0x01 /* Assert POR for processor 0 */
+#define BBC_SPG_CPU1 0x02 /* Assert POR for processor 1 */
+#define BBC_SPG_CPU2 0x04 /* Assert POR for processor 2 */
+#define BBC_SPG_CPU3 0x08 /* Assert POR for processor 3 */
+#define BBC_SPG_CPUALL 0x10 /* Reset all processors and reset
+ * the entire system.
+ */
+#define BBC_SPG_RESV 0xe0 /* Reserved */
+
+/* Soft_XIR_GEN register. The XIR (eXternally Initiated Reset) signal
+ * may be asserted to specific processors via this register.
+ */
+#define BBC_SXG_CPU0 0x01 /* Assert XIR for processor 0 */
+#define BBC_SXG_CPU1 0x02 /* Assert XIR for processor 1 */
+#define BBC_SXG_CPU2 0x04 /* Assert XIR for processor 2 */
+#define BBC_SXG_CPU3 0x08 /* Assert XIR for processor 3 */
+#define BBC_SXG_RESV 0xf0 /* Reserved */
+
+/* POR Source register. One may identify the cause of the most recent
+ * reset by reading this register.
+ */
+#define BBC_PSRC_SPG0 0x0001 /* CPU 0 reset via BBC_SPG register */
+#define BBC_PSRC_SPG1 0x0002 /* CPU 1 reset via BBC_SPG register */
+#define BBC_PSRC_SPG2 0x0004 /* CPU 2 reset via BBC_SPG register */
+#define BBC_PSRC_SPG3 0x0008 /* CPU 3 reset via BBC_SPG register */
+#define BBC_PSRC_SPGSYS 0x0010 /* System reset via BBC_SPG register */
+#define BBC_PSRC_JTAG 0x0020 /* System reset via JTAG+ */
+#define BBC_PSRC_BUTTON 0x0040 /* System reset via push-button dongle */
+#define BBC_PSRC_PWRUP 0x0080 /* System reset via power-up */
+#define BBC_PSRC_FE0 0x0100 /* CPU 0 reported Fatal_Error */
+#define BBC_PSRC_FE1 0x0200 /* CPU 1 reported Fatal_Error */
+#define BBC_PSRC_FE2 0x0400 /* CPU 2 reported Fatal_Error */
+#define BBC_PSRC_FE3 0x0800 /* CPU 3 reported Fatal_Error */
+#define BBC_PSRC_FE4 0x1000 /* Schizo reported Fatal_Error */
+#define BBC_PSRC_FE5 0x2000 /* Safari device 5 reported Fatal_Error */
+#define BBC_PSRC_FE6 0x4000 /* CPMS reported Fatal_Error */
+#define BBC_PSRC_SYNTH 0x8000 /* System reset when on-board clock synthesizers
+ * were updated.
+ */
+#define BBC_PSRC_WDT 0x10000 /* System reset via Super I/O watchdog */
+#define BBC_PSRC_RSC 0x20000 /* System reset via RSC remote monitoring
+ * device
+ */
+
+/* XIR Source register. The source of an XIR event sent to a processor may
+ * be determined via this register.
+ */
+#define BBC_XSRC_SXG0 0x01 /* CPU 0 received XIR via Soft_XIR_GEN reg */
+#define BBC_XSRC_SXG1 0x02 /* CPU 1 received XIR via Soft_XIR_GEN reg */
+#define BBC_XSRC_SXG2 0x04 /* CPU 2 received XIR via Soft_XIR_GEN reg */
+#define BBC_XSRC_SXG3 0x08 /* CPU 3 received XIR via Soft_XIR_GEN reg */
+#define BBC_XSRC_JTAG 0x10 /* All CPUs received XIR via JTAG+ */
+#define BBC_XSRC_W_OR_B 0x20 /* All CPUs received XIR either because:
+ * a) Super I/O watchdog fired, or
+ * b) XIR push button was activated
+ */
+#define BBC_XSRC_RESV 0xc0 /* Reserved */
+
+/* Clock Synthesizers Control register. This register provides the big-bang
+ * programming interface to the two clock synthesizers of the machine.
+ */
+#define BBC_CSC_SLOAD 0x01 /* Directly connected to S_LOAD pins */
+#define BBC_CSC_SDATA 0x02 /* Directly connected to S_DATA pins */
+#define BBC_CSC_SCLOCK 0x04 /* Directly connected to S_CLOCK pins */
+#define BBC_CSC_RESV 0x78 /* Reserved */
+#define BBC_CSC_RST 0x80 /* Generate system reset when S_LOAD==1 */
+
+/* Energy Star Control register. This register is used to generate the
+ * clock frequency change trigger to the main system devices (Schizo and
+ * the processors). The transition occurs when bits in this register
+ * go from 0 to 1, only one bit must be set at once else no action
+ * occurs. Basically the sequence of events is:
+ * a) Choose new frequency: full, 1/2 or 1/32
+ * b) Program this desired frequency into the cpus and Schizo.
+ * c) Set the same value in this register.
+ * d) 16 system clocks later, clear this register.
+ */
+#define BBC_ES_CTRL_1_1 0x01 /* Full frequency */
+#define BBC_ES_CTRL_1_2 0x02 /* 1/2 frequency */
+#define BBC_ES_CTRL_1_32 0x20 /* 1/32 frequency */
+#define BBC_ES_RESV 0xdc /* Reserved */
+
+/* Energy Star Assert Change Time register. This determines the number
+ * of BBC clock cycles (which is half the system frequency) between
+ * the detection of FREEZE_ACK being asserted and the assertion of
+ * the CLK_CHANGE_L[2:0] signals.
+ */
+#define BBC_ES_ACT_VAL 0xff
+
+/* Energy Star Assert Bypass Time register. This determines the number
+ * of BBC clock cycles (which is half the system frequency) between
+ * the assertion of the CLK_CHANGE_L[2:0] signals and the assertion of
+ * the ESTAR_PLL_BYPASS signal.
+ */
+#define BBC_ES_ABT_VAL 0xffff
+
+/* Energy Star PLL Settle Time register. This determines the number of
+ * BBC clock cycles (which is half the system frequency) between the
+ * de-assertion of CLK_CHANGE_L[2:0] and the de-assertion of the FREEZE_L
+ * signal.
+ */
+#define BBC_ES_PST_VAL 0xffffffff
+
+/* Energy Star Frequency Switch Latency register. This is the number of
+ * BBC clocks between the de-assertion of CLK_CHANGE_L[2:0] and the first
+ * edge of the Safari clock at the new frequency.
+ */
+#define BBC_ES_FSL_VAL 0xffffffff
+
+/* Keyboard Beep control register. This is a simple enabler for the audio
+ * beep sound.
+ */
+#define BBC_KBD_BEEP_ENABLE 0x01 /* Enable beep */
+#define BBC_KBD_BEEP_RESV 0xfe /* Reserved */
+
+/* Keyboard Beep Counter register. There is a free-running counter inside
+ * the BBC which runs at half the system clock. The bit set in this register
+ * determines when the audio sound is generated. So for example if bit
+ * 10 is set, the audio beep will oscillate at 1/(2**12). The keyboard beep
+ * generator automatically selects a different bit to use if the system clock
+ * is changed via Energy Star.
+ */
+#define BBC_KBD_BCNT_BITS 0x0007fc00
+#define BBC_KBC_BCNT_RESV 0xfff803ff
+
+#endif /* _SPARC64_BBC_H */
+
--- /dev/null
+/*
+ * bitext.h: Bit string operations on the sparc, specific to architecture.
+ *
+ * Copyright 2002 Pete Zaitcev <zaitcev@yahoo.com>
+ */
+
+#ifndef _SPARC_BITEXT_H
+#define _SPARC_BITEXT_H
+
+#include <linux/spinlock.h>
+
+struct bit_map {
+ spinlock_t lock;
+ unsigned long *map;
+ int size;
+ int used;
+ int last_off;
+ int last_size;
+ int first_free;
+ int num_colors;
+};
+
+extern int bit_map_string_get(struct bit_map *t, int len, int align);
+extern void bit_map_clear(struct bit_map *t, int offset, int len);
+extern void bit_map_init(struct bit_map *t, unsigned long *map, int size);
+
+#endif /* defined(_SPARC_BITEXT_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_BITOPS_H
+#define ___ASM_SPARC_BITOPS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/bitops_64.h>
+#else
+#include <asm/bitops_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * bitops.h: Bit string operations on the Sparc.
+ *
+ * Copyright 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright 1996 Eddie C. Dost (ecd@skynet.be)
+ * Copyright 2001 Anton Blanchard (anton@samba.org)
+ */
+
+#ifndef _SPARC_BITOPS_H
+#define _SPARC_BITOPS_H
+
+#include <linux/compiler.h>
+#include <asm/byteorder.h>
+
+#ifdef __KERNEL__
+
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+extern unsigned long ___set_bit(unsigned long *addr, unsigned long mask);
+extern unsigned long ___clear_bit(unsigned long *addr, unsigned long mask);
+extern unsigned long ___change_bit(unsigned long *addr, unsigned long mask);
+
+/*
+ * Set bit 'nr' in 32-bit quantity at address 'addr' where bit '0'
+ * is in the highest of the four bytes and bit '31' is the high bit
+ * within the first byte. Sparc is BIG-Endian. Unless noted otherwise
+ * all bit-ops return 0 if bit was previously clear and != 0 otherwise.
+ */
+static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
+{
+ unsigned long *ADDR, mask;
+
+ ADDR = ((unsigned long *) addr) + (nr >> 5);
+ mask = 1 << (nr & 31);
+
+ return ___set_bit(ADDR, mask) != 0;
+}
+
+static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
+{
+ unsigned long *ADDR, mask;
+
+ ADDR = ((unsigned long *) addr) + (nr >> 5);
+ mask = 1 << (nr & 31);
+
+ (void) ___set_bit(ADDR, mask);
+}
+
+static inline int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
+{
+ unsigned long *ADDR, mask;
+
+ ADDR = ((unsigned long *) addr) + (nr >> 5);
+ mask = 1 << (nr & 31);
+
+ return ___clear_bit(ADDR, mask) != 0;
+}
+
+static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
+{
+ unsigned long *ADDR, mask;
+
+ ADDR = ((unsigned long *) addr) + (nr >> 5);
+ mask = 1 << (nr & 31);
+
+ (void) ___clear_bit(ADDR, mask);
+}
+
+static inline int test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
+{
+ unsigned long *ADDR, mask;
+
+ ADDR = ((unsigned long *) addr) + (nr >> 5);
+ mask = 1 << (nr & 31);
+
+ return ___change_bit(ADDR, mask) != 0;
+}
+
+static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
+{
+ unsigned long *ADDR, mask;
+
+ ADDR = ((unsigned long *) addr) + (nr >> 5);
+ mask = 1 << (nr & 31);
+
+ (void) ___change_bit(ADDR, mask);
+}
+
+#include <asm-generic/bitops/non-atomic.h>
+
+#define smp_mb__before_clear_bit() do { } while(0)
+#define smp_mb__after_clear_bit() do { } while(0)
+
+#include <asm-generic/bitops/ffz.h>
+#include <asm-generic/bitops/__ffs.h>
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/ffs.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/lock.h>
+#include <asm-generic/bitops/find.h>
+#include <asm-generic/bitops/ext2-non-atomic.h>
+#include <asm-generic/bitops/ext2-atomic.h>
+#include <asm-generic/bitops/minix.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* defined(_SPARC_BITOPS_H) */
--- /dev/null
+/*
+ * bitops.h: Bit string operations on the V9.
+ *
+ * Copyright 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC64_BITOPS_H
+#define _SPARC64_BITOPS_H
+
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+#include <linux/compiler.h>
+#include <asm/byteorder.h>
+
+extern int test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
+extern int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
+extern int test_and_change_bit(unsigned long nr, volatile unsigned long *addr);
+extern void set_bit(unsigned long nr, volatile unsigned long *addr);
+extern void clear_bit(unsigned long nr, volatile unsigned long *addr);
+extern void change_bit(unsigned long nr, volatile unsigned long *addr);
+
+#include <asm-generic/bitops/non-atomic.h>
+
+#ifdef CONFIG_SMP
+#define smp_mb__before_clear_bit() membar_storeload_loadload()
+#define smp_mb__after_clear_bit() membar_storeload_storestore()
+#else
+#define smp_mb__before_clear_bit() barrier()
+#define smp_mb__after_clear_bit() barrier()
+#endif
+
+#include <asm-generic/bitops/ffz.h>
+#include <asm-generic/bitops/__ffs.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+
+#ifdef __KERNEL__
+
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/ffs.h>
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#ifdef ULTRA_HAS_POPULATION_COUNT
+
+static inline unsigned int hweight64(unsigned long w)
+{
+ unsigned int res;
+
+ __asm__ ("popc %1,%0" : "=r" (res) : "r" (w));
+ return res;
+}
+
+static inline unsigned int hweight32(unsigned int w)
+{
+ unsigned int res;
+
+ __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffffffff));
+ return res;
+}
+
+static inline unsigned int hweight16(unsigned int w)
+{
+ unsigned int res;
+
+ __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffff));
+ return res;
+}
+
+static inline unsigned int hweight8(unsigned int w)
+{
+ unsigned int res;
+
+ __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xff));
+ return res;
+}
+
+#else
+
+#include <asm-generic/bitops/hweight.h>
+
+#endif
+#include <asm-generic/bitops/lock.h>
+#endif /* __KERNEL__ */
+
+#include <asm-generic/bitops/find.h>
+
+#ifdef __KERNEL__
+
+#include <asm-generic/bitops/ext2-non-atomic.h>
+
+#define ext2_set_bit_atomic(lock,nr,addr) \
+ test_and_set_bit((nr) ^ 0x38,(unsigned long *)(addr))
+#define ext2_clear_bit_atomic(lock,nr,addr) \
+ test_and_clear_bit((nr) ^ 0x38,(unsigned long *)(addr))
+
+#include <asm-generic/bitops/minix.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* defined(_SPARC64_BITOPS_H) */
--- /dev/null
+#ifndef _SPARC_BPP_H
+#define _SPARC_BPP_H
+
+/*
+ * Copyright (c) 1995 Picture Elements
+ * Stephen Williams
+ * Gus Baldauf
+ *
+ * Linux/SPARC port by Peter Zaitcev.
+ * Integration into SPARC tree by Tom Dyas.
+ */
+
+#include <linux/ioctl.h>
+
+/*
+ * This is a driver that supports IEEE Std 1284-1994 communications
+ * with compliant or compatible devices. It will use whatever features
+ * the device supports, prefering those that are typically faster.
+ *
+ * When the device is opened, it is left in COMPATIBILITY mode, and
+ * writes work like any printer device. The driver only attempt to
+ * negotiate 1284 modes when needed so that plugs can be pulled,
+ * switch boxes switched, etc., without disrupting things. It will
+ * also leave the device in compatibility mode when closed.
+ */
+
+
+
+/*
+ * This driver also supplies ioctls to manually manipulate the
+ * pins. This is great for testing devices, or writing code to deal
+ * with bizzarro-mode of the ACME Special TurboThingy Plus.
+ *
+ * NOTE: These ioctl currently do not interact well with
+ * read/write. Caveat emptor.
+ *
+ * PUT_PINS allows us to assign the sense of all the pins, including
+ * the data pins if being driven by the host. The GET_PINS returns the
+ * pins that the peripheral drives, including data if appropriate.
+ */
+
+# define BPP_PUT_PINS _IOW('B', 1, int)
+# define BPP_GET_PINS _IOR('B', 2, char) /* that's bogus - should've been _IO */
+# define BPP_PUT_DATA _IOW('B', 3, int)
+# define BPP_GET_DATA _IOR('B', 4, char) /* ditto */
+
+/*
+ * Set the data bus to input mode. Disengage the data bin driver and
+ * be prepared to read values from the peripheral. If the arg is 0,
+ * then revert the bus to output mode.
+ */
+# define BPP_SET_INPUT _IOW('B', 5, int)
+
+/*
+ * These bits apply to the PUT operation...
+ */
+# define BPP_PP_nStrobe 0x0001
+# define BPP_PP_nAutoFd 0x0002
+# define BPP_PP_nInit 0x0004
+# define BPP_PP_nSelectIn 0x0008
+
+/*
+ * These apply to the GET operation, which also reads the current value
+ * of the previously put values. A bit mask of these will be returned
+ * as a bit mask in the return code of the ioctl().
+ */
+# define BPP_GP_nAck 0x0100
+# define BPP_GP_Busy 0x0200
+# define BPP_GP_PError 0x0400
+# define BPP_GP_Select 0x0800
+# define BPP_GP_nFault 0x1000
+
+#endif
--- /dev/null
+/*
+ * asm/btfixup.h: Macros for boot time linking.
+ *
+ * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+
+#ifndef _SPARC_BTFIXUP_H
+#define _SPARC_BTFIXUP_H
+
+#include <linux/init.h>
+
+#ifndef __ASSEMBLY__
+
+#ifdef MODULE
+extern unsigned int ___illegal_use_of_BTFIXUP_SIMM13_in_module(void);
+extern unsigned int ___illegal_use_of_BTFIXUP_SETHI_in_module(void);
+extern unsigned int ___illegal_use_of_BTFIXUP_HALF_in_module(void);
+extern unsigned int ___illegal_use_of_BTFIXUP_INT_in_module(void);
+
+#define BTFIXUP_SIMM13(__name) ___illegal_use_of_BTFIXUP_SIMM13_in_module()
+#define BTFIXUP_HALF(__name) ___illegal_use_of_BTFIXUP_HALF_in_module()
+#define BTFIXUP_SETHI(__name) ___illegal_use_of_BTFIXUP_SETHI_in_module()
+#define BTFIXUP_INT(__name) ___illegal_use_of_BTFIXUP_INT_in_module()
+#define BTFIXUP_BLACKBOX(__name) ___illegal_use_of_BTFIXUP_BLACKBOX_in_module
+
+#else
+
+#define BTFIXUP_SIMM13(__name) ___sf_##__name()
+#define BTFIXUP_HALF(__name) ___af_##__name()
+#define BTFIXUP_SETHI(__name) ___hf_##__name()
+#define BTFIXUP_INT(__name) ((unsigned int)&___i_##__name)
+/* This must be written in assembly and present in a sethi */
+#define BTFIXUP_BLACKBOX(__name) ___b_##__name
+#endif /* MODULE */
+
+/* Fixup call xx */
+
+#define BTFIXUPDEF_CALL(__type, __name, __args...) \
+ extern __type ___f_##__name(__args); \
+ extern unsigned ___fs_##__name[3];
+#define BTFIXUPDEF_CALL_CONST(__type, __name, __args...) \
+ extern __type ___f_##__name(__args) __attribute_const__; \
+ extern unsigned ___fs_##__name[3];
+#define BTFIXUP_CALL(__name) ___f_##__name
+
+#define BTFIXUPDEF_BLACKBOX(__name) \
+ extern unsigned ___bs_##__name[2];
+
+/* Put bottom 13bits into some register variable */
+
+#define BTFIXUPDEF_SIMM13(__name) \
+ static inline unsigned int ___sf_##__name(void) __attribute_const__; \
+ extern unsigned ___ss_##__name[2]; \
+ static inline unsigned int ___sf_##__name(void) { \
+ unsigned int ret; \
+ __asm__ ("or %%g0, ___s_" #__name ", %0" : "=r"(ret)); \
+ return ret; \
+ }
+#define BTFIXUPDEF_SIMM13_INIT(__name,__val) \
+ static inline unsigned int ___sf_##__name(void) __attribute_const__; \
+ extern unsigned ___ss_##__name[2]; \
+ static inline unsigned int ___sf_##__name(void) { \
+ unsigned int ret; \
+ __asm__ ("or %%g0, ___s_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
+ return ret; \
+ }
+
+/* Put either bottom 13 bits, or upper 22 bits into some register variable
+ * (depending on the value, this will lead into sethi FIX, reg; or
+ * mov FIX, reg; )
+ */
+
+#define BTFIXUPDEF_HALF(__name) \
+ static inline unsigned int ___af_##__name(void) __attribute_const__; \
+ extern unsigned ___as_##__name[2]; \
+ static inline unsigned int ___af_##__name(void) { \
+ unsigned int ret; \
+ __asm__ ("or %%g0, ___a_" #__name ", %0" : "=r"(ret)); \
+ return ret; \
+ }
+#define BTFIXUPDEF_HALF_INIT(__name,__val) \
+ static inline unsigned int ___af_##__name(void) __attribute_const__; \
+ extern unsigned ___as_##__name[2]; \
+ static inline unsigned int ___af_##__name(void) { \
+ unsigned int ret; \
+ __asm__ ("or %%g0, ___a_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
+ return ret; \
+ }
+
+/* Put upper 22 bits into some register variable */
+
+#define BTFIXUPDEF_SETHI(__name) \
+ static inline unsigned int ___hf_##__name(void) __attribute_const__; \
+ extern unsigned ___hs_##__name[2]; \
+ static inline unsigned int ___hf_##__name(void) { \
+ unsigned int ret; \
+ __asm__ ("sethi %%hi(___h_" #__name "), %0" : "=r"(ret)); \
+ return ret; \
+ }
+#define BTFIXUPDEF_SETHI_INIT(__name,__val) \
+ static inline unsigned int ___hf_##__name(void) __attribute_const__; \
+ extern unsigned ___hs_##__name[2]; \
+ static inline unsigned int ___hf_##__name(void) { \
+ unsigned int ret; \
+ __asm__ ("sethi %%hi(___h_" #__name "__btset_" #__val "), %0" : \
+ "=r"(ret)); \
+ return ret; \
+ }
+
+/* Put a full 32bit integer into some register variable */
+
+#define BTFIXUPDEF_INT(__name) \
+ extern unsigned char ___i_##__name; \
+ extern unsigned ___is_##__name[2];
+
+#define BTFIXUPCALL_NORM 0x00000000 /* Always call */
+#define BTFIXUPCALL_NOP 0x01000000 /* Possibly optimize to nop */
+#define BTFIXUPCALL_RETINT(i) (0x90102000|((i) & 0x1fff)) /* Possibly optimize to mov i, %o0 */
+#define BTFIXUPCALL_ORINT(i) (0x90122000|((i) & 0x1fff)) /* Possibly optimize to or %o0, i, %o0 */
+#define BTFIXUPCALL_RETO0 0x01000000 /* Return first parameter, actually a nop */
+#define BTFIXUPCALL_ANDNINT(i) (0x902a2000|((i) & 0x1fff)) /* Possibly optimize to andn %o0, i, %o0 */
+#define BTFIXUPCALL_SWAPO0O1 0xd27a0000 /* Possibly optimize to swap [%o0],%o1 */
+#define BTFIXUPCALL_SWAPO0G0 0xc07a0000 /* Possibly optimize to swap [%o0],%g0 */
+#define BTFIXUPCALL_SWAPG1G2 0xc4784000 /* Possibly optimize to swap [%g1],%g2 */
+#define BTFIXUPCALL_STG0O0 0xc0220000 /* Possibly optimize to st %g0,[%o0] */
+#define BTFIXUPCALL_STO1O0 0xd2220000 /* Possibly optimize to st %o1,[%o0] */
+
+#define BTFIXUPSET_CALL(__name, __addr, __insn) \
+ do { \
+ ___fs_##__name[0] |= 1; \
+ ___fs_##__name[1] = (unsigned long)__addr; \
+ ___fs_##__name[2] = __insn; \
+ } while (0)
+
+#define BTFIXUPSET_BLACKBOX(__name, __func) \
+ do { \
+ ___bs_##__name[0] |= 1; \
+ ___bs_##__name[1] = (unsigned long)__func; \
+ } while (0)
+
+#define BTFIXUPCOPY_CALL(__name, __from) \
+ do { \
+ ___fs_##__name[0] |= 1; \
+ ___fs_##__name[1] = ___fs_##__from[1]; \
+ ___fs_##__name[2] = ___fs_##__from[2]; \
+ } while (0)
+
+#define BTFIXUPSET_SIMM13(__name, __val) \
+ do { \
+ ___ss_##__name[0] |= 1; \
+ ___ss_##__name[1] = (unsigned)__val; \
+ } while (0)
+
+#define BTFIXUPCOPY_SIMM13(__name, __from) \
+ do { \
+ ___ss_##__name[0] |= 1; \
+ ___ss_##__name[1] = ___ss_##__from[1]; \
+ } while (0)
+
+#define BTFIXUPSET_HALF(__name, __val) \
+ do { \
+ ___as_##__name[0] |= 1; \
+ ___as_##__name[1] = (unsigned)__val; \
+ } while (0)
+
+#define BTFIXUPCOPY_HALF(__name, __from) \
+ do { \
+ ___as_##__name[0] |= 1; \
+ ___as_##__name[1] = ___as_##__from[1]; \
+ } while (0)
+
+#define BTFIXUPSET_SETHI(__name, __val) \
+ do { \
+ ___hs_##__name[0] |= 1; \
+ ___hs_##__name[1] = (unsigned)__val; \
+ } while (0)
+
+#define BTFIXUPCOPY_SETHI(__name, __from) \
+ do { \
+ ___hs_##__name[0] |= 1; \
+ ___hs_##__name[1] = ___hs_##__from[1]; \
+ } while (0)
+
+#define BTFIXUPSET_INT(__name, __val) \
+ do { \
+ ___is_##__name[0] |= 1; \
+ ___is_##__name[1] = (unsigned)__val; \
+ } while (0)
+
+#define BTFIXUPCOPY_INT(__name, __from) \
+ do { \
+ ___is_##__name[0] |= 1; \
+ ___is_##__name[1] = ___is_##__from[1]; \
+ } while (0)
+
+#define BTFIXUPVAL_CALL(__name) \
+ ((unsigned long)___fs_##__name[1])
+
+extern void btfixup(void);
+
+#else /* __ASSEMBLY__ */
+
+#define BTFIXUP_SETHI(__name) %hi(___h_ ## __name)
+#define BTFIXUP_SETHI_INIT(__name,__val) %hi(___h_ ## __name ## __btset_ ## __val)
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* !(_SPARC_BTFIXUP_H) */
--- /dev/null
+#ifndef _SPARC_BUG_H
+#define _SPARC_BUG_H
+
+#ifdef CONFIG_BUG
+#include <linux/compiler.h>
+
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+extern void do_BUG(const char *file, int line);
+#define BUG() do { \
+ do_BUG(__FILE__, __LINE__); \
+ __builtin_trap(); \
+} while (0)
+#else
+#define BUG() __builtin_trap()
+#endif
+
+#define HAVE_ARCH_BUG
+#endif
+
+#include <asm-generic/bug.h>
+
+#endif
--- /dev/null
+/* include/asm/bugs.h: Sparc probes for various bugs.
+ *
+ * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
+ */
+
+#ifdef CONFIG_SPARC32
+#include <asm/cpudata.h>
+#endif
+
+#ifdef CONFIG_SPARC64
+#include <asm/sstate.h>
+#endif
+
+extern unsigned long loops_per_jiffy;
+
+static void __init check_bugs(void)
+{
+#if defined(CONFIG_SPARC32) && !defined(CONFIG_SMP)
+ cpu_data(0).udelay_val = loops_per_jiffy;
+#endif
+#ifdef CONFIG_SPARC64
+ sstate_running();
+#endif
+}
--- /dev/null
+#ifndef _SPARC_BYTEORDER_H
+#define _SPARC_BYTEORDER_H
+
+#include <asm/types.h>
+#include <asm/asi.h>
+
+#ifdef __GNUC__
+
+#ifdef CONFIG_SPARC32
+#define __SWAB_64_THRU_32__
+#endif
+
+#ifdef CONFIG_SPARC64
+
+static inline __u16 ___arch__swab16p(const __u16 *addr)
+{
+ __u16 ret;
+
+ __asm__ __volatile__ ("lduha [%1] %2, %0"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PL));
+ return ret;
+}
+
+static inline __u32 ___arch__swab32p(const __u32 *addr)
+{
+ __u32 ret;
+
+ __asm__ __volatile__ ("lduwa [%1] %2, %0"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PL));
+ return ret;
+}
+
+static inline __u64 ___arch__swab64p(const __u64 *addr)
+{
+ __u64 ret;
+
+ __asm__ __volatile__ ("ldxa [%1] %2, %0"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PL));
+ return ret;
+}
+
+#define __arch__swab16p(x) ___arch__swab16p(x)
+#define __arch__swab32p(x) ___arch__swab32p(x)
+#define __arch__swab64p(x) ___arch__swab64p(x)
+
+#endif /* CONFIG_SPARC64 */
+
+#define __BYTEORDER_HAS_U64__
+
+#endif
+
+#include <linux/byteorder/big_endian.h>
+
+#endif /* _SPARC_BYTEORDER_H */
--- /dev/null
+/* cache.h: Cache specific code for the Sparc. These include flushing
+ * and direct tag/data line access.
+ *
+ * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC_CACHE_H
+#define _SPARC_CACHE_H
+
+#define L1_CACHE_SHIFT 5
+#define L1_CACHE_BYTES 32
+#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
+
+#ifdef CONFIG_SPARC32
+#define SMP_CACHE_BYTES_SHIFT 5
+#else
+#define SMP_CACHE_BYTES_SHIFT 6
+#endif
+
+#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
+
+#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+
+#ifdef CONFIG_SPARC32
+#include <asm/asi.h>
+
+/* Direct access to the instruction cache is provided through and
+ * alternate address space. The IDC bit must be off in the ICCR on
+ * HyperSparcs for these accesses to work. The code below does not do
+ * any checking, the caller must do so. These routines are for
+ * diagnostics only, but could end up being useful. Use with care.
+ * Also, you are asking for trouble if you execute these in one of the
+ * three instructions following a %asr/%psr access or modification.
+ */
+
+/* First, cache-tag access. */
+static inline unsigned int get_icache_tag(int setnum, int tagnum)
+{
+ unsigned int vaddr, retval;
+
+ vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
+ __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+ "=r" (retval) :
+ "r" (vaddr), "i" (ASI_M_TXTC_TAG));
+ return retval;
+}
+
+static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
+{
+ unsigned int vaddr;
+
+ vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
+ __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
+ "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
+ "memory");
+}
+
+/* Second cache-data access. The data is returned two-32bit quantities
+ * at a time.
+ */
+static inline void get_icache_data(int setnum, int tagnum, int subblock,
+ unsigned int *data)
+{
+ unsigned int value1, value2, vaddr;
+
+ vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
+ ((subblock&0x3) << 3);
+ __asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
+ "or %%g0, %%g2, %0\n\t"
+ "or %%g0, %%g3, %1\n\t" :
+ "=r" (value1), "=r" (value2) :
+ "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
+ "g2", "g3");
+ data[0] = value1; data[1] = value2;
+}
+
+static inline void put_icache_data(int setnum, int tagnum, int subblock,
+ unsigned int *data)
+{
+ unsigned int value1, value2, vaddr;
+
+ vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
+ ((subblock&0x3) << 3);
+ value1 = data[0]; value2 = data[1];
+ __asm__ __volatile__("or %%g0, %0, %%g2\n\t"
+ "or %%g0, %1, %%g3\n\t"
+ "stda %%g2, [%2] %3\n\t" : :
+ "r" (value1), "r" (value2),
+ "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
+ "g2", "g3", "memory" /* no joke */);
+}
+
+/* Different types of flushes with the ICACHE. Some of the flushes
+ * affect both the ICACHE and the external cache. Others only clear
+ * the ICACHE entries on the cpu itself. V8's (most) allow
+ * granularity of flushes on the packet (element in line), whole line,
+ * and entire cache (ie. all lines) level. The ICACHE only flushes are
+ * ROSS HyperSparc specific and are in ross.h
+ */
+
+/* Flushes which clear out both the on-chip and external caches */
+static inline void flush_ei_page(unsigned int addr)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+ "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
+ "memory");
+}
+
+static inline void flush_ei_seg(unsigned int addr)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+ "r" (addr), "i" (ASI_M_FLUSH_SEG) :
+ "memory");
+}
+
+static inline void flush_ei_region(unsigned int addr)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+ "r" (addr), "i" (ASI_M_FLUSH_REGION) :
+ "memory");
+}
+
+static inline void flush_ei_ctx(unsigned int addr)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+ "r" (addr), "i" (ASI_M_FLUSH_CTX) :
+ "memory");
+}
+
+static inline void flush_ei_user(unsigned int addr)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+ "r" (addr), "i" (ASI_M_FLUSH_USER) :
+ "memory");
+}
+#endif /* CONFIG_SPARC32 */
+
+#endif /* !(_SPARC_CACHE_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_CACHEFLUSH_H
+#define ___ASM_SPARC_CACHEFLUSH_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/cacheflush_64.h>
+#else
+#include <asm/cacheflush_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _SPARC_CACHEFLUSH_H
+#define _SPARC_CACHEFLUSH_H
+
+#include <linux/mm.h> /* Common for other includes */
+// #include <linux/kernel.h> from pgalloc.h
+// #include <linux/sched.h> from pgalloc.h
+
+// #include <asm/page.h>
+#include <asm/btfixup.h>
+
+/*
+ * Fine grained cache flushing.
+ */
+#ifdef CONFIG_SMP
+
+BTFIXUPDEF_CALL(void, local_flush_cache_all, void)
+BTFIXUPDEF_CALL(void, local_flush_cache_mm, struct mm_struct *)
+BTFIXUPDEF_CALL(void, local_flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long)
+BTFIXUPDEF_CALL(void, local_flush_cache_page, struct vm_area_struct *, unsigned long)
+
+#define local_flush_cache_all() BTFIXUP_CALL(local_flush_cache_all)()
+#define local_flush_cache_mm(mm) BTFIXUP_CALL(local_flush_cache_mm)(mm)
+#define local_flush_cache_range(vma,start,end) BTFIXUP_CALL(local_flush_cache_range)(vma,start,end)
+#define local_flush_cache_page(vma,addr) BTFIXUP_CALL(local_flush_cache_page)(vma,addr)
+
+BTFIXUPDEF_CALL(void, local_flush_page_to_ram, unsigned long)
+BTFIXUPDEF_CALL(void, local_flush_sig_insns, struct mm_struct *, unsigned long)
+
+#define local_flush_page_to_ram(addr) BTFIXUP_CALL(local_flush_page_to_ram)(addr)
+#define local_flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(local_flush_sig_insns)(mm,insn_addr)
+
+extern void smp_flush_cache_all(void);
+extern void smp_flush_cache_mm(struct mm_struct *mm);
+extern void smp_flush_cache_range(struct vm_area_struct *vma,
+ unsigned long start,
+ unsigned long end);
+extern void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
+
+extern void smp_flush_page_to_ram(unsigned long page);
+extern void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
+
+#endif /* CONFIG_SMP */
+
+BTFIXUPDEF_CALL(void, flush_cache_all, void)
+BTFIXUPDEF_CALL(void, flush_cache_mm, struct mm_struct *)
+BTFIXUPDEF_CALL(void, flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long)
+BTFIXUPDEF_CALL(void, flush_cache_page, struct vm_area_struct *, unsigned long)
+
+#define flush_cache_all() BTFIXUP_CALL(flush_cache_all)()
+#define flush_cache_mm(mm) BTFIXUP_CALL(flush_cache_mm)(mm)
+#define flush_cache_dup_mm(mm) BTFIXUP_CALL(flush_cache_mm)(mm)
+#define flush_cache_range(vma,start,end) BTFIXUP_CALL(flush_cache_range)(vma,start,end)
+#define flush_cache_page(vma,addr,pfn) BTFIXUP_CALL(flush_cache_page)(vma,addr)
+#define flush_icache_range(start, end) do { } while (0)
+#define flush_icache_page(vma, pg) do { } while (0)
+
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+ do { \
+ flush_cache_page(vma, vaddr, page_to_pfn(page));\
+ memcpy(dst, src, len); \
+ } while (0)
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+ do { \
+ flush_cache_page(vma, vaddr, page_to_pfn(page));\
+ memcpy(dst, src, len); \
+ } while (0)
+
+BTFIXUPDEF_CALL(void, __flush_page_to_ram, unsigned long)
+BTFIXUPDEF_CALL(void, flush_sig_insns, struct mm_struct *, unsigned long)
+
+#define __flush_page_to_ram(addr) BTFIXUP_CALL(__flush_page_to_ram)(addr)
+#define flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(flush_sig_insns)(mm,insn_addr)
+
+extern void sparc_flush_page_to_ram(struct page *page);
+
+#define flush_dcache_page(page) sparc_flush_page_to_ram(page)
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+
+#define flush_cache_vmap(start, end) flush_cache_all()
+#define flush_cache_vunmap(start, end) flush_cache_all()
+
+#endif /* _SPARC_CACHEFLUSH_H */
--- /dev/null
+#ifndef _SPARC64_CACHEFLUSH_H
+#define _SPARC64_CACHEFLUSH_H
+
+#include <asm/page.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/mm.h>
+
+/* Cache flush operations. */
+
+/* These are the same regardless of whether this is an SMP kernel or not. */
+#define flush_cache_mm(__mm) \
+ do { if ((__mm) == current->mm) flushw_user(); } while(0)
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+#define flush_cache_range(vma, start, end) \
+ flush_cache_mm((vma)->vm_mm)
+#define flush_cache_page(vma, page, pfn) \
+ flush_cache_mm((vma)->vm_mm)
+
+/*
+ * On spitfire, the icache doesn't snoop local stores and we don't
+ * use block commit stores (which invalidate icache lines) during
+ * module load, so we need this.
+ */
+extern void flush_icache_range(unsigned long start, unsigned long end);
+extern void __flush_icache_page(unsigned long);
+
+extern void __flush_dcache_page(void *addr, int flush_icache);
+extern void flush_dcache_page_impl(struct page *page);
+#ifdef CONFIG_SMP
+extern void smp_flush_dcache_page_impl(struct page *page, int cpu);
+extern void flush_dcache_page_all(struct mm_struct *mm, struct page *page);
+#else
+#define smp_flush_dcache_page_impl(page,cpu) flush_dcache_page_impl(page)
+#define flush_dcache_page_all(mm,page) flush_dcache_page_impl(page)
+#endif
+
+extern void __flush_dcache_range(unsigned long start, unsigned long end);
+extern void flush_dcache_page(struct page *page);
+
+#define flush_icache_page(vma, pg) do { } while(0)
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+
+extern void flush_ptrace_access(struct vm_area_struct *, struct page *,
+ unsigned long uaddr, void *kaddr,
+ unsigned long len, int write);
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+ do { \
+ flush_cache_page(vma, vaddr, page_to_pfn(page)); \
+ memcpy(dst, src, len); \
+ flush_ptrace_access(vma, page, vaddr, src, len, 0); \
+ } while (0)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+ do { \
+ flush_cache_page(vma, vaddr, page_to_pfn(page)); \
+ memcpy(dst, src, len); \
+ flush_ptrace_access(vma, page, vaddr, dst, len, 1); \
+ } while (0)
+
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+
+#define flush_cache_vmap(start, end) do { } while (0)
+#define flush_cache_vunmap(start, end) do { } while (0)
+
+#ifdef CONFIG_DEBUG_PAGEALLOC
+/* internal debugging function */
+void kernel_map_pages(struct page *page, int numpages, int enable);
+#endif
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _SPARC64_CACHEFLUSH_H */
--- /dev/null
+#ifndef _SPARC64_CHAFSR_H
+#define _SPARC64_CHAFSR_H
+
+/* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
+
+/* Comments indicate which processor variants on which the bit definition
+ * is valid. Codes are:
+ * ch --> cheetah
+ * ch+ --> cheetah plus
+ * jp --> jalapeno
+ */
+
+/* All bits of this register except M_SYNDROME and E_SYNDROME are
+ * read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only.
+ */
+
+/* Software bit set by linux trap handlers to indicate that the trap was
+ * signalled at %tl >= 1.
+ */
+#define CHAFSR_TL1 (1UL << 63UL) /* n/a */
+
+/* Unmapped error from system bus for prefetch queue or
+ * store queue read operation
+ */
+#define CHPAFSR_DTO (1UL << 59UL) /* ch+ */
+
+/* Bus error from system bus for prefetch queue or store queue
+ * read operation
+ */
+#define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */
+
+/* Hardware corrected E-cache Tag ECC error */
+#define CHPAFSR_THCE (1UL << 57UL) /* ch+ */
+/* System interface protocol error, hw timeout caused */
+#define JPAFSR_JETO (1UL << 57UL) /* jp */
+
+/* SW handled correctable E-cache Tag ECC error */
+#define CHPAFSR_TSCE (1UL << 56UL) /* ch+ */
+/* Parity error on system snoop results */
+#define JPAFSR_SCE (1UL << 56UL) /* jp */
+
+/* Uncorrectable E-cache Tag ECC error */
+#define CHPAFSR_TUE (1UL << 55UL) /* ch+ */
+/* System interface protocol error, illegal command detected */
+#define JPAFSR_JEIC (1UL << 55UL) /* jp */
+
+/* Uncorrectable system bus data ECC error due to prefetch
+ * or store fill request
+ */
+#define CHPAFSR_DUE (1UL << 54UL) /* ch+ */
+/* System interface protocol error, illegal ADTYPE detected */
+#define JPAFSR_JEIT (1UL << 54UL) /* jp */
+
+/* Multiple errors of the same type have occurred. This bit is set when
+ * an uncorrectable error or a SW correctable error occurs and the status
+ * bit to report that error is already set. When multiple errors of
+ * different types are indicated by setting multiple status bits.
+ *
+ * This bit is not set if multiple HW corrected errors with the same
+ * status bit occur, only uncorrectable and SW correctable ones have
+ * this behavior.
+ *
+ * This bit is not set when multiple ECC errors happen within a single
+ * 64-byte system bus transaction. Only the first ECC error in a 16-byte
+ * subunit will be logged. All errors in subsequent 16-byte subunits
+ * from the same 64-byte transaction are ignored.
+ */
+#define CHAFSR_ME (1UL << 53UL) /* ch,ch+,jp */
+
+/* Privileged state error has occurred. This is a capture of PSTATE.PRIV
+ * at the time the error is detected.
+ */
+#define CHAFSR_PRIV (1UL << 52UL) /* ch,ch+,jp */
+
+/* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error
+ * bits and record the most recently detected errors. Bits accumulate
+ * errors that have been detected since the last write to clear the bit.
+ */
+
+/* System interface protocol error. The processor asserts its' ERROR
+ * pin when this event occurs and it also logs a specific cause code
+ * into a JTAG scannable flop.
+ */
+#define CHAFSR_PERR (1UL << 51UL) /* ch,ch+,jp */
+
+/* Internal processor error. The processor asserts its' ERROR
+ * pin when this event occurs and it also logs a specific cause code
+ * into a JTAG scannable flop.
+ */
+#define CHAFSR_IERR (1UL << 50UL) /* ch,ch+,jp */
+
+/* System request parity error on incoming address */
+#define CHAFSR_ISAP (1UL << 49UL) /* ch,ch+,jp */
+
+/* HW Corrected system bus MTAG ECC error */
+#define CHAFSR_EMC (1UL << 48UL) /* ch,ch+ */
+/* Parity error on L2 cache tag SRAM */
+#define JPAFSR_ETP (1UL << 48UL) /* jp */
+
+/* Uncorrectable system bus MTAG ECC error */
+#define CHAFSR_EMU (1UL << 47UL) /* ch,ch+ */
+/* Out of range memory error has occurred */
+#define JPAFSR_OM (1UL << 47UL) /* jp */
+
+/* HW Corrected system bus data ECC error for read of interrupt vector */
+#define CHAFSR_IVC (1UL << 46UL) /* ch,ch+ */
+/* Error due to unsupported store */
+#define JPAFSR_UMS (1UL << 46UL) /* jp */
+
+/* Uncorrectable system bus data ECC error for read of interrupt vector */
+#define CHAFSR_IVU (1UL << 45UL) /* ch,ch+,jp */
+
+/* Unmapped error from system bus */
+#define CHAFSR_TO (1UL << 44UL) /* ch,ch+,jp */
+
+/* Bus error response from system bus */
+#define CHAFSR_BERR (1UL << 43UL) /* ch,ch+,jp */
+
+/* SW Correctable E-cache ECC error for instruction fetch or data access
+ * other than block load.
+ */
+#define CHAFSR_UCC (1UL << 42UL) /* ch,ch+,jp */
+
+/* Uncorrectable E-cache ECC error for instruction fetch or data access
+ * other than block load.
+ */
+#define CHAFSR_UCU (1UL << 41UL) /* ch,ch+,jp */
+
+/* Copyout HW Corrected ECC error */
+#define CHAFSR_CPC (1UL << 40UL) /* ch,ch+,jp */
+
+/* Copyout Uncorrectable ECC error */
+#define CHAFSR_CPU (1UL << 39UL) /* ch,ch+,jp */
+
+/* HW Corrected ECC error from E-cache for writeback */
+#define CHAFSR_WDC (1UL << 38UL) /* ch,ch+,jp */
+
+/* Uncorrectable ECC error from E-cache for writeback */
+#define CHAFSR_WDU (1UL << 37UL) /* ch,ch+,jp */
+
+/* HW Corrected ECC error from E-cache for store merge or block load */
+#define CHAFSR_EDC (1UL << 36UL) /* ch,ch+,jp */
+
+/* Uncorrectable ECC error from E-cache for store merge or block load */
+#define CHAFSR_EDU (1UL << 35UL) /* ch,ch+,jp */
+
+/* Uncorrectable system bus data ECC error for read of memory or I/O */
+#define CHAFSR_UE (1UL << 34UL) /* ch,ch+,jp */
+
+/* HW Corrected system bus data ECC error for read of memory or I/O */
+#define CHAFSR_CE (1UL << 33UL) /* ch,ch+,jp */
+
+/* Uncorrectable ECC error from remote cache/memory */
+#define JPAFSR_RUE (1UL << 32UL) /* jp */
+
+/* Correctable ECC error from remote cache/memory */
+#define JPAFSR_RCE (1UL << 31UL) /* jp */
+
+/* JBUS parity error on returned read data */
+#define JPAFSR_BP (1UL << 30UL) /* jp */
+
+/* JBUS parity error on data for writeback or block store */
+#define JPAFSR_WBP (1UL << 29UL) /* jp */
+
+/* Foreign read to DRAM incurring correctable ECC error */
+#define JPAFSR_FRC (1UL << 28UL) /* jp */
+
+/* Foreign read to DRAM incurring uncorrectable ECC error */
+#define JPAFSR_FRU (1UL << 27UL) /* jp */
+
+#define CHAFSR_ERRORS (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
+ CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
+ CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
+ CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
+ CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
+#define CHPAFSR_ERRORS (CHPAFSR_DTO | CHPAFSR_DBERR | CHPAFSR_THCE | \
+ CHPAFSR_TSCE | CHPAFSR_TUE | CHPAFSR_DUE | \
+ CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
+ CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
+ CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
+ CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
+ CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
+#define JPAFSR_ERRORS (JPAFSR_JETO | JPAFSR_SCE | JPAFSR_JEIC | \
+ JPAFSR_JEIT | CHAFSR_PERR | CHAFSR_IERR | \
+ CHAFSR_ISAP | JPAFSR_ETP | JPAFSR_OM | \
+ JPAFSR_UMS | CHAFSR_IVU | CHAFSR_TO | \
+ CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | \
+ CHAFSR_CPC | CHAFSR_CPU | CHAFSR_WDC | \
+ CHAFSR_WDU | CHAFSR_EDC | CHAFSR_EDU | \
+ CHAFSR_UE | CHAFSR_CE | JPAFSR_RUE | \
+ JPAFSR_RCE | JPAFSR_BP | JPAFSR_WBP | \
+ JPAFSR_FRC | JPAFSR_FRU)
+
+/* Active JBUS request signal when error occurred */
+#define JPAFSR_JBREQ (0x7UL << 24UL) /* jp */
+#define JPAFSR_JBREQ_SHIFT 24UL
+
+/* L2 cache way information */
+#define JPAFSR_ETW (0x3UL << 22UL) /* jp */
+#define JPAFSR_ETW_SHIFT 22UL
+
+/* System bus MTAG ECC syndrome. This field captures the status of the
+ * first occurrence of the highest-priority error according to the M_SYND
+ * overwrite policy. After the AFSR sticky bit, corresponding to the error
+ * for which the M_SYND is reported, is cleared, the contents of the M_SYND
+ * field will be unchanged by will be unfrozen for further error capture.
+ */
+#define CHAFSR_M_SYNDROME (0xfUL << 16UL) /* ch,ch+,jp */
+#define CHAFSR_M_SYNDROME_SHIFT 16UL
+
+/* Agenid Id of the foreign device causing the UE/CE errors */
+#define JPAFSR_AID (0x1fUL << 9UL) /* jp */
+#define JPAFSR_AID_SHIFT 9UL
+
+/* System bus or E-cache data ECC syndrome. This field captures the status
+ * of the first occurrence of the highest-priority error according to the
+ * E_SYND overwrite policy. After the AFSR sticky bit, corresponding to the
+ * error for which the E_SYND is reported, is cleare, the contents of the E_SYND
+ * field will be unchanged but will be unfrozen for further error capture.
+ */
+#define CHAFSR_E_SYNDROME (0x1ffUL << 0UL) /* ch,ch+,jp */
+#define CHAFSR_E_SYNDROME_SHIFT 0UL
+
+/* The AFSR must be explicitly cleared by software, it is not cleared automatically
+ * by a read. Writes to bits <51:33> with bits set will clear the corresponding
+ * bits in the AFSR. Bits associated with disrupting traps must be cleared before
+ * interrupts are re-enabled to prevent multiple traps for the same error. I.e.
+ * PSTATE.IE and AFSR bits control delivery of disrupting traps.
+ *
+ * Since there is only one AFAR, when multiple events have been logged by the
+ * bits in the AFSR, at most one of these events will have its status captured
+ * in the AFAR. The highest priority of those event bits will get AFAR logging.
+ * The AFAR will be unlocked and available to capture the address of another event
+ * as soon as the one bit in AFSR that corresponds to the event logged in AFAR is
+ * cleared. For example, if AFSR.CE is detected, then AFSR.UE (which overwrites
+ * the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked
+ * and ready for another event, even though AFSR.CE is still set. The same rules
+ * also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR.
+ */
+
+#endif /* _SPARC64_CHAFSR_H */
--- /dev/null
+#ifndef ___ASM_SPARC_CHECKSUM_H
+#define ___ASM_SPARC_CHECKSUM_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/checksum_64.h>
+#else
+#include <asm/checksum_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef __SPARC_CHECKSUM_H
+#define __SPARC_CHECKSUM_H
+
+/* checksum.h: IP/UDP/TCP checksum routines on the Sparc.
+ *
+ * Copyright(C) 1995 Linus Torvalds
+ * Copyright(C) 1995 Miguel de Icaza
+ * Copyright(C) 1996 David S. Miller
+ * Copyright(C) 1996 Eddie C. Dost
+ * Copyright(C) 1997 Jakub Jelinek
+ *
+ * derived from:
+ * Alpha checksum c-code
+ * ix86 inline assembly
+ * RFC1071 Computing the Internet Checksum
+ */
+
+#include <linux/in6.h>
+#include <asm/uaccess.h>
+
+/* computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+extern __wsum csum_partial(const void *buff, int len, __wsum sum);
+
+/* the same as csum_partial, but copies from fs:src while it
+ * checksums
+ *
+ * here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ */
+
+extern unsigned int __csum_partial_copy_sparc_generic (const unsigned char *, unsigned char *);
+
+static inline __wsum
+csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum)
+{
+ register unsigned int ret asm("o0") = (unsigned int)src;
+ register char *d asm("o1") = dst;
+ register int l asm("g1") = len;
+
+ __asm__ __volatile__ (
+ "call __csum_partial_copy_sparc_generic\n\t"
+ " mov %6, %%g7\n"
+ : "=&r" (ret), "=&r" (d), "=&r" (l)
+ : "0" (ret), "1" (d), "2" (l), "r" (sum)
+ : "o2", "o3", "o4", "o5", "o7",
+ "g2", "g3", "g4", "g5", "g7",
+ "memory", "cc");
+ return (__force __wsum)ret;
+}
+
+static inline __wsum
+csum_partial_copy_from_user(const void __user *src, void *dst, int len,
+ __wsum sum, int *err)
+ {
+ register unsigned long ret asm("o0") = (unsigned long)src;
+ register char *d asm("o1") = dst;
+ register int l asm("g1") = len;
+ register __wsum s asm("g7") = sum;
+
+ __asm__ __volatile__ (
+ ".section __ex_table,#alloc\n\t"
+ ".align 4\n\t"
+ ".word 1f,2\n\t"
+ ".previous\n"
+ "1:\n\t"
+ "call __csum_partial_copy_sparc_generic\n\t"
+ " st %8, [%%sp + 64]\n"
+ : "=&r" (ret), "=&r" (d), "=&r" (l), "=&r" (s)
+ : "0" (ret), "1" (d), "2" (l), "3" (s), "r" (err)
+ : "o2", "o3", "o4", "o5", "o7", "g2", "g3", "g4", "g5",
+ "cc", "memory");
+ return (__force __wsum)ret;
+}
+
+static inline __wsum
+csum_partial_copy_to_user(const void *src, void __user *dst, int len,
+ __wsum sum, int *err)
+{
+ if (!access_ok (VERIFY_WRITE, dst, len)) {
+ *err = -EFAULT;
+ return sum;
+ } else {
+ register unsigned long ret asm("o0") = (unsigned long)src;
+ register char __user *d asm("o1") = dst;
+ register int l asm("g1") = len;
+ register __wsum s asm("g7") = sum;
+
+ __asm__ __volatile__ (
+ ".section __ex_table,#alloc\n\t"
+ ".align 4\n\t"
+ ".word 1f,1\n\t"
+ ".previous\n"
+ "1:\n\t"
+ "call __csum_partial_copy_sparc_generic\n\t"
+ " st %8, [%%sp + 64]\n"
+ : "=&r" (ret), "=&r" (d), "=&r" (l), "=&r" (s)
+ : "0" (ret), "1" (d), "2" (l), "3" (s), "r" (err)
+ : "o2", "o3", "o4", "o5", "o7",
+ "g2", "g3", "g4", "g5",
+ "cc", "memory");
+ return (__force __wsum)ret;
+ }
+}
+
+#define HAVE_CSUM_COPY_USER
+#define csum_and_copy_to_user csum_partial_copy_to_user
+
+/* ihl is always 5 or greater, almost always is 5, and iph is word aligned
+ * the majority of the time.
+ */
+static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
+{
+ __sum16 sum;
+
+ /* Note: We must read %2 before we touch %0 for the first time,
+ * because GCC can legitimately use the same register for
+ * both operands.
+ */
+ __asm__ __volatile__("sub\t%2, 4, %%g4\n\t"
+ "ld\t[%1 + 0x00], %0\n\t"
+ "ld\t[%1 + 0x04], %%g2\n\t"
+ "ld\t[%1 + 0x08], %%g3\n\t"
+ "addcc\t%%g2, %0, %0\n\t"
+ "addxcc\t%%g3, %0, %0\n\t"
+ "ld\t[%1 + 0x0c], %%g2\n\t"
+ "ld\t[%1 + 0x10], %%g3\n\t"
+ "addxcc\t%%g2, %0, %0\n\t"
+ "addx\t%0, %%g0, %0\n"
+ "1:\taddcc\t%%g3, %0, %0\n\t"
+ "add\t%1, 4, %1\n\t"
+ "addxcc\t%0, %%g0, %0\n\t"
+ "subcc\t%%g4, 1, %%g4\n\t"
+ "be,a\t2f\n\t"
+ "sll\t%0, 16, %%g2\n\t"
+ "b\t1b\n\t"
+ "ld\t[%1 + 0x10], %%g3\n"
+ "2:\taddcc\t%0, %%g2, %%g2\n\t"
+ "srl\t%%g2, 16, %0\n\t"
+ "addx\t%0, %%g0, %0\n\t"
+ "xnor\t%%g0, %0, %0"
+ : "=r" (sum), "=&r" (iph)
+ : "r" (ihl), "1" (iph)
+ : "g2", "g3", "g4", "cc", "memory");
+ return sum;
+}
+
+/* Fold a partial checksum without adding pseudo headers. */
+static inline __sum16 csum_fold(__wsum sum)
+{
+ unsigned int tmp;
+
+ __asm__ __volatile__("addcc\t%0, %1, %1\n\t"
+ "srl\t%1, 16, %1\n\t"
+ "addx\t%1, %%g0, %1\n\t"
+ "xnor\t%%g0, %1, %0"
+ : "=&r" (sum), "=r" (tmp)
+ : "0" (sum), "1" ((__force u32)sum<<16)
+ : "cc");
+ return (__force __sum16)sum;
+}
+
+static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
+ unsigned short len,
+ unsigned short proto,
+ __wsum sum)
+{
+ __asm__ __volatile__("addcc\t%1, %0, %0\n\t"
+ "addxcc\t%2, %0, %0\n\t"
+ "addxcc\t%3, %0, %0\n\t"
+ "addx\t%0, %%g0, %0\n\t"
+ : "=r" (sum), "=r" (saddr)
+ : "r" (daddr), "r" (proto + len), "0" (sum),
+ "1" (saddr)
+ : "cc");
+ return sum;
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
+ unsigned short len,
+ unsigned short proto,
+ __wsum sum)
+{
+ return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+
+static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
+ const struct in6_addr *daddr,
+ __u32 len, unsigned short proto,
+ __wsum sum)
+{
+ __asm__ __volatile__ (
+ "addcc %3, %4, %%g4\n\t"
+ "addxcc %5, %%g4, %%g4\n\t"
+ "ld [%2 + 0x0c], %%g2\n\t"
+ "ld [%2 + 0x08], %%g3\n\t"
+ "addxcc %%g2, %%g4, %%g4\n\t"
+ "ld [%2 + 0x04], %%g2\n\t"
+ "addxcc %%g3, %%g4, %%g4\n\t"
+ "ld [%2 + 0x00], %%g3\n\t"
+ "addxcc %%g2, %%g4, %%g4\n\t"
+ "ld [%1 + 0x0c], %%g2\n\t"
+ "addxcc %%g3, %%g4, %%g4\n\t"
+ "ld [%1 + 0x08], %%g3\n\t"
+ "addxcc %%g2, %%g4, %%g4\n\t"
+ "ld [%1 + 0x04], %%g2\n\t"
+ "addxcc %%g3, %%g4, %%g4\n\t"
+ "ld [%1 + 0x00], %%g3\n\t"
+ "addxcc %%g2, %%g4, %%g4\n\t"
+ "addxcc %%g3, %%g4, %0\n\t"
+ "addx 0, %0, %0\n"
+ : "=&r" (sum)
+ : "r" (saddr), "r" (daddr),
+ "r"(htonl(len)), "r"(htonl(proto)), "r"(sum)
+ : "g2", "g3", "g4", "cc");
+
+ return csum_fold(sum);
+}
+
+/* this routine is used for miscellaneous IP-like checksums, mainly in icmp.c */
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+ return csum_fold(csum_partial(buff, len, 0));
+}
+
+#endif /* !(__SPARC_CHECKSUM_H) */
--- /dev/null
+#ifndef __SPARC64_CHECKSUM_H
+#define __SPARC64_CHECKSUM_H
+
+/* checksum.h: IP/UDP/TCP checksum routines on the V9.
+ *
+ * Copyright(C) 1995 Linus Torvalds
+ * Copyright(C) 1995 Miguel de Icaza
+ * Copyright(C) 1996 David S. Miller
+ * Copyright(C) 1996 Eddie C. Dost
+ * Copyright(C) 1997 Jakub Jelinek
+ *
+ * derived from:
+ * Alpha checksum c-code
+ * ix86 inline assembly
+ * RFC1071 Computing the Internet Checksum
+ */
+
+#include <linux/in6.h>
+#include <asm/uaccess.h>
+
+/* computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+extern __wsum csum_partial(const void * buff, int len, __wsum sum);
+
+/* the same as csum_partial, but copies from user space while it
+ * checksums
+ *
+ * here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ */
+extern __wsum csum_partial_copy_nocheck(const void *src, void *dst,
+ int len, __wsum sum);
+
+extern long __csum_partial_copy_from_user(const void __user *src,
+ void *dst, int len,
+ __wsum sum);
+
+static inline __wsum
+csum_partial_copy_from_user(const void __user *src,
+ void *dst, int len,
+ __wsum sum, int *err)
+{
+ long ret = __csum_partial_copy_from_user(src, dst, len, sum);
+ if (ret < 0)
+ *err = -EFAULT;
+ return (__force __wsum) ret;
+}
+
+/*
+ * Copy and checksum to user
+ */
+#define HAVE_CSUM_COPY_USER
+extern long __csum_partial_copy_to_user(const void *src,
+ void __user *dst, int len,
+ __wsum sum);
+
+static inline __wsum
+csum_and_copy_to_user(const void *src,
+ void __user *dst, int len,
+ __wsum sum, int *err)
+{
+ long ret = __csum_partial_copy_to_user(src, dst, len, sum);
+ if (ret < 0)
+ *err = -EFAULT;
+ return (__force __wsum) ret;
+}
+
+/* ihl is always 5 or greater, almost always is 5, and iph is word aligned
+ * the majority of the time.
+ */
+extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
+
+/* Fold a partial checksum without adding pseudo headers. */
+static inline __sum16 csum_fold(__wsum sum)
+{
+ unsigned int tmp;
+
+ __asm__ __volatile__(
+" addcc %0, %1, %1\n"
+" srl %1, 16, %1\n"
+" addc %1, %%g0, %1\n"
+" xnor %%g0, %1, %0\n"
+ : "=&r" (sum), "=r" (tmp)
+ : "0" (sum), "1" ((__force u32)sum<<16)
+ : "cc");
+ return (__force __sum16)sum;
+}
+
+static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
+ unsigned int len,
+ unsigned short proto,
+ __wsum sum)
+{
+ __asm__ __volatile__(
+" addcc %1, %0, %0\n"
+" addccc %2, %0, %0\n"
+" addccc %3, %0, %0\n"
+" addc %0, %%g0, %0\n"
+ : "=r" (sum), "=r" (saddr)
+ : "r" (daddr), "r" (proto + len), "0" (sum), "1" (saddr)
+ : "cc");
+ return sum;
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
+ unsigned short len,
+ unsigned short proto,
+ __wsum sum)
+{
+ return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+
+static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
+ const struct in6_addr *daddr,
+ __u32 len, unsigned short proto,
+ __wsum sum)
+{
+ __asm__ __volatile__ (
+" addcc %3, %4, %%g7\n"
+" addccc %5, %%g7, %%g7\n"
+" lduw [%2 + 0x0c], %%g2\n"
+" lduw [%2 + 0x08], %%g3\n"
+" addccc %%g2, %%g7, %%g7\n"
+" lduw [%2 + 0x04], %%g2\n"
+" addccc %%g3, %%g7, %%g7\n"
+" lduw [%2 + 0x00], %%g3\n"
+" addccc %%g2, %%g7, %%g7\n"
+" lduw [%1 + 0x0c], %%g2\n"
+" addccc %%g3, %%g7, %%g7\n"
+" lduw [%1 + 0x08], %%g3\n"
+" addccc %%g2, %%g7, %%g7\n"
+" lduw [%1 + 0x04], %%g2\n"
+" addccc %%g3, %%g7, %%g7\n"
+" lduw [%1 + 0x00], %%g3\n"
+" addccc %%g2, %%g7, %%g7\n"
+" addccc %%g3, %%g7, %0\n"
+" addc 0, %0, %0\n"
+ : "=&r" (sum)
+ : "r" (saddr), "r" (daddr), "r"(htonl(len)),
+ "r"(htonl(proto)), "r"(sum)
+ : "g2", "g3", "g7", "cc");
+
+ return csum_fold(sum);
+}
+
+/* this routine is used for miscellaneous IP-like checksums, mainly in icmp.c */
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+ return csum_fold(csum_partial(buff, len, 0));
+}
+
+#endif /* !(__SPARC64_CHECKSUM_H) */
--- /dev/null
+#ifndef _SPARC64_CHMCTRL_H
+#define _SPARC64_CHMCTRL_H
+
+/* Cheetah memory controller programmable registers. */
+#define CHMCTRL_TCTRL1 0x00 /* Memory Timing Control I */
+#define CHMCTRL_TCTRL2 0x08 /* Memory Timing Control II */
+#define CHMCTRL_TCTRL3 0x38 /* Memory Timing Control III */
+#define CHMCTRL_TCTRL4 0x40 /* Memory Timing Control IV */
+#define CHMCTRL_DECODE1 0x10 /* Memory Address Decode I */
+#define CHMCTRL_DECODE2 0x18 /* Memory Address Decode II */
+#define CHMCTRL_DECODE3 0x20 /* Memory Address Decode III */
+#define CHMCTRL_DECODE4 0x28 /* Memory Address Decode IV */
+#define CHMCTRL_MACTRL 0x30 /* Memory Address Control */
+
+/* Memory Timing Control I */
+#define TCTRL1_SDRAMCTL_DLY 0xf000000000000000UL
+#define TCTRL1_SDRAMCTL_DLY_SHIFT 60
+#define TCTRL1_SDRAMCLK_DLY 0x0e00000000000000UL
+#define TCTRL1_SDRAMCLK_DLY_SHIFT 57
+#define TCTRL1_R 0x0100000000000000UL
+#define TCTRL1_R_SHIFT 56
+#define TCTRL1_AUTORFR_CYCLE 0x00fe000000000000UL
+#define TCTRL1_AUTORFR_CYCLE_SHIFT 49
+#define TCTRL1_RD_WAIT 0x0001f00000000000UL
+#define TCTRL1_RD_WAIT_SHIFT 44
+#define TCTRL1_PC_CYCLE 0x00000fc000000000UL
+#define TCTRL1_PC_CYCLE_SHIFT 38
+#define TCTRL1_WR_MORE_RAS_PW 0x0000003f00000000UL
+#define TCTRL1_WR_MORE_RAS_PW_SHIFT 32
+#define TCTRL1_RD_MORE_RAW_PW 0x00000000fc000000UL
+#define TCTRL1_RD_MORE_RAS_PW_SHIFT 26
+#define TCTRL1_ACT_WR_DLY 0x0000000003f00000UL
+#define TCTRL1_ACT_WR_DLY_SHIFT 20
+#define TCTRL1_ACT_RD_DLY 0x00000000000fc000UL
+#define TCTRL1_ACT_RD_DLY_SHIFT 14
+#define TCTRL1_BANK_PRESENT 0x0000000000003000UL
+#define TCTRL1_BANK_PRESENT_SHIFT 12
+#define TCTRL1_RFR_INT 0x0000000000000ff8UL
+#define TCTRL1_RFR_INT_SHIFT 3
+#define TCTRL1_SET_MODE_REG 0x0000000000000004UL
+#define TCTRL1_SET_MODE_REG_SHIFT 2
+#define TCTRL1_RFR_ENABLE 0x0000000000000002UL
+#define TCTRL1_RFR_ENABLE_SHIFT 1
+#define TCTRL1_PRECHG_ALL 0x0000000000000001UL
+#define TCTRL1_PRECHG_ALL_SHIFT 0
+
+/* Memory Timing Control II */
+#define TCTRL2_WR_MSEL_DLY 0xfc00000000000000UL
+#define TCTRL2_WR_MSEL_DLY_SHIFT 58
+#define TCTRL2_RD_MSEL_DLY 0x03f0000000000000UL
+#define TCTRL2_RD_MSEL_DLY_SHIFT 52
+#define TCTRL2_WRDATA_THLD 0x000c000000000000UL
+#define TCTRL2_WRDATA_THLD_SHIFT 50
+#define TCTRL2_RDWR_RD_TI_DLY 0x0003f00000000000UL
+#define TCTRL2_RDWR_RD_TI_DLY_SHIFT 44
+#define TCTRL2_AUTOPRECHG_ENBL 0x0000080000000000UL
+#define TCTRL2_AUTOPRECHG_ENBL_SHIFT 43
+#define TCTRL2_RDWR_PI_MORE_DLY 0x000007c000000000UL
+#define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38
+#define TCTRL2_RDWR_1_DLY 0x0000003f00000000UL
+#define TCTRL2_RDWR_1_DLY_SHIFT 32
+#define TCTRL2_WRWR_PI_MORE_DLY 0x00000000f8000000UL
+#define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27
+#define TCTRL2_WRWR_1_DLY 0x0000000007e00000UL
+#define TCTRL2_WRWR_1_DLY_SHIFT 21
+#define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000UL
+#define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16
+#define TCTRL2_R 0x0000000000008000UL
+#define TCTRL2_R_SHIFT 15
+#define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
+#define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0
+
+/* Memory Timing Control III */
+#define TCTRL3_SDRAM_CTL_DLY 0xf000000000000000UL
+#define TCTRL3_SDRAM_CTL_DLY_SHIFT 60
+#define TCTRL3_SDRAM_CLK_DLY 0x0e00000000000000UL
+#define TCTRL3_SDRAM_CLK_DLY_SHIFT 57
+#define TCTRL3_R 0x0100000000000000UL
+#define TCTRL3_R_SHIFT 56
+#define TCTRL3_AUTO_RFR_CYCLE 0x00fe000000000000UL
+#define TCTRL3_AUTO_RFR_CYCLE_SHIFT 49
+#define TCTRL3_RD_WAIT 0x0001f00000000000UL
+#define TCTRL3_RD_WAIT_SHIFT 44
+#define TCTRL3_PC_CYCLE 0x00000fc000000000UL
+#define TCTRL3_PC_CYCLE_SHIFT 38
+#define TCTRL3_WR_MORE_RAW_PW 0x0000003f00000000UL
+#define TCTRL3_WR_MORE_RAW_PW_SHIFT 32
+#define TCTRL3_RD_MORE_RAW_PW 0x00000000fc000000UL
+#define TCTRL3_RD_MORE_RAW_PW_SHIFT 26
+#define TCTRL3_ACT_WR_DLY 0x0000000003f00000UL
+#define TCTRL3_ACT_WR_DLY_SHIFT 20
+#define TCTRL3_ACT_RD_DLY 0x00000000000fc000UL
+#define TCTRL3_ACT_RD_DLY_SHIFT 14
+#define TCTRL3_BANK_PRESENT 0x0000000000003000UL
+#define TCTRL3_BANK_PRESENT_SHIFT 12
+#define TCTRL3_RFR_INT 0x0000000000000ff8UL
+#define TCTRL3_RFR_INT_SHIFT 3
+#define TCTRL3_SET_MODE_REG 0x0000000000000004UL
+#define TCTRL3_SET_MODE_REG_SHIFT 2
+#define TCTRL3_RFR_ENABLE 0x0000000000000002UL
+#define TCTRL3_RFR_ENABLE_SHIFT 1
+#define TCTRL3_PRECHG_ALL 0x0000000000000001UL
+#define TCTRL3_PRECHG_ALL_SHIFT 0
+
+/* Memory Timing Control IV */
+#define TCTRL4_WR_MSEL_DLY 0xfc00000000000000UL
+#define TCTRL4_WR_MSEL_DLY_SHIFT 58
+#define TCTRL4_RD_MSEL_DLY 0x03f0000000000000UL
+#define TCTRL4_RD_MSEL_DLY_SHIFT 52
+#define TCTRL4_WRDATA_THLD 0x000c000000000000UL
+#define TCTRL4_WRDATA_THLD_SHIFT 50
+#define TCTRL4_RDWR_RD_RI_DLY 0x0003f00000000000UL
+#define TCTRL4_RDWR_RD_RI_DLY_SHIFT 44
+#define TCTRL4_AUTO_PRECHG_ENBL 0x0000080000000000UL
+#define TCTRL4_AUTO_PRECHG_ENBL_SHIFT 43
+#define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000UL
+#define TCTRL4_RD_WR_PI_MORE_DLY_SHIFT 38
+#define TCTRL4_RD_WR_TI_DLY 0x0000003f00000000UL
+#define TCTRL4_RD_WR_TI_DLY_SHIFT 32
+#define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000UL
+#define TCTRL4_WR_WR_PI_MORE_DLY_SHIFT 27
+#define TCTRL4_WR_WR_TI_DLY 0x0000000007e00000UL
+#define TCTRL4_WR_WR_TI_DLY_SHIFT 21
+#define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f000UL0
+#define TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT 16
+#define TCTRL4_R 0x0000000000008000UL
+#define TCTRL4_R_SHIFT 15
+#define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
+#define TCTRL4_SDRAM_MODE_REG_DATA_SHIFT 0
+
+/* All 4 memory address decoding registers have the
+ * same layout.
+ */
+#define MEM_DECODE_VALID 0x8000000000000000UL /* Valid */
+#define MEM_DECODE_VALID_SHIFT 63
+#define MEM_DECODE_UK 0x001ffe0000000000UL /* Upper mask */
+#define MEM_DECODE_UK_SHIFT 41
+#define MEM_DECODE_UM 0x0000001ffff00000UL /* Upper match */
+#define MEM_DECODE_UM_SHIFT 20
+#define MEM_DECODE_LK 0x000000000003c000UL /* Lower mask */
+#define MEM_DECODE_LK_SHIFT 14
+#define MEM_DECODE_LM 0x0000000000000f00UL /* Lower match */
+#define MEM_DECODE_LM_SHIFT 8
+
+#define PA_UPPER_BITS 0x000007fffc000000UL
+#define PA_UPPER_BITS_SHIFT 26
+#define PA_LOWER_BITS 0x00000000000003c0UL
+#define PA_LOWER_BITS_SHIFT 6
+
+#define MACTRL_R0 0x8000000000000000UL
+#define MACTRL_R0_SHIFT 63
+#define MACTRL_ADDR_LE_PW 0x7000000000000000UL
+#define MACTRL_ADDR_LE_PW_SHIFT 60
+#define MACTRL_CMD_PW 0x0f00000000000000UL
+#define MACTRL_CMD_PW_SHIFT 56
+#define MACTRL_HALF_MODE_WR_MSEL_DLY 0x00fc000000000000UL
+#define MACTRL_HALF_MODE_WR_MSEL_DLY_SHIFT 50
+#define MACTRL_HALF_MODE_RD_MSEL_DLY 0x0003f00000000000UL
+#define MACTRL_HALF_MODE_RD_MSEL_DLY_SHIFT 44
+#define MACTRL_HALF_MODE_SDRAM_CTL_DLY 0x00000f0000000000UL
+#define MACTRL_HALF_MODE_SDRAM_CTL_DLY_SHIFT 40
+#define MACTRL_HALF_MODE_SDRAM_CLK_DLY 0x000000e000000000UL
+#define MACTRL_HALF_MODE_SDRAM_CLK_DLY_SHIFT 37
+#define MACTRL_R1 0x0000001000000000UL
+#define MACTRL_R1_SHIFT 36
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000UL
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3_SHIFT 32
+#define MACTRL_ENC_INTLV_B3 0x00000000f8000000UL
+#define MACTRL_ENC_INTLV_B3_SHIFT 27
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000UL
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2_SHIFT 23
+#define MACTRL_ENC_INTLV_B2 0x00000000007c0000UL
+#define MACTRL_ENC_INTLV_B2_SHIFT 18
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000UL
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1_SHIFT 14
+#define MACTRL_ENC_INTLV_B1 0x0000000000003e00UL
+#define MACTRL_ENC_INTLV_B1_SHIFT 9
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0UL
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0_SHIFT 5
+#define MACTRL_ENC_INTLV_B0 0x000000000000001fUL
+#define MACTRL_ENC_INTLV_B0_SHIFT 0
+
+#endif /* _SPARC64_CHMCTRL_H */
--- /dev/null
+/*
+ * clock.h: Definitions for clock operations on the Sparc.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_CLOCK_H
+#define _SPARC_CLOCK_H
+
+/* Foo for now. */
+
+#endif /* !(_SPARC_CLOCK_H) */
--- /dev/null
+#ifndef _SPARC64_CMT_H
+#define _SPARC64_CMT_H
+
+/* cmt.h: Chip Multi-Threading register definitions
+ *
+ * Copyright (C) 2004 David S. Miller (davem@redhat.com)
+ */
+
+/* ASI_CORE_ID - private */
+#define LP_ID 0x0000000000000010UL
+#define LP_ID_MAX 0x00000000003f0000UL
+#define LP_ID_ID 0x000000000000003fUL
+
+/* ASI_INTR_ID - private */
+#define LP_INTR_ID 0x0000000000000000UL
+#define LP_INTR_ID_ID 0x00000000000003ffUL
+
+/* ASI_CESR_ID - private */
+#define CESR_ID 0x0000000000000040UL
+#define CESR_ID_ID 0x00000000000000ffUL
+
+/* ASI_CORE_AVAILABLE - shared */
+#define LP_AVAIL 0x0000000000000000UL
+#define LP_AVAIL_1 0x0000000000000002UL
+#define LP_AVAIL_0 0x0000000000000001UL
+
+/* ASI_CORE_ENABLE_STATUS - shared */
+#define LP_ENAB_STAT 0x0000000000000010UL
+#define LP_ENAB_STAT_1 0x0000000000000002UL
+#define LP_ENAB_STAT_0 0x0000000000000001UL
+
+/* ASI_CORE_ENABLE - shared */
+#define LP_ENAB 0x0000000000000020UL
+#define LP_ENAB_1 0x0000000000000002UL
+#define LP_ENAB_0 0x0000000000000001UL
+
+/* ASI_CORE_RUNNING - shared */
+#define LP_RUNNING_RW 0x0000000000000050UL
+#define LP_RUNNING_W1S 0x0000000000000060UL
+#define LP_RUNNING_W1C 0x0000000000000068UL
+#define LP_RUNNING_1 0x0000000000000002UL
+#define LP_RUNNING_0 0x0000000000000001UL
+
+/* ASI_CORE_RUNNING_STAT - shared */
+#define LP_RUN_STAT 0x0000000000000058UL
+#define LP_RUN_STAT_1 0x0000000000000002UL
+#define LP_RUN_STAT_0 0x0000000000000001UL
+
+/* ASI_XIR_STEERING - shared */
+#define LP_XIR_STEER 0x0000000000000030UL
+#define LP_XIR_STEER_1 0x0000000000000002UL
+#define LP_XIR_STEER_0 0x0000000000000001UL
+
+/* ASI_CMT_ERROR_STEERING - shared */
+#define CMT_ER_STEER 0x0000000000000040UL
+#define CMT_ER_STEER_1 0x0000000000000002UL
+#define CMT_ER_STEER_0 0x0000000000000001UL
+
+#endif /* _SPARC64_CMT_H */
--- /dev/null
+#ifndef _ASM_SPARC64_COMPAT_H
+#define _ASM_SPARC64_COMPAT_H
+/*
+ * Architecture specific compatibility types
+ */
+#include <linux/types.h>
+
+#define COMPAT_USER_HZ 100
+
+typedef u32 compat_size_t;
+typedef s32 compat_ssize_t;
+typedef s32 compat_time_t;
+typedef s32 compat_clock_t;
+typedef s32 compat_pid_t;
+typedef u16 __compat_uid_t;
+typedef u16 __compat_gid_t;
+typedef u32 __compat_uid32_t;
+typedef u32 __compat_gid32_t;
+typedef u16 compat_mode_t;
+typedef u32 compat_ino_t;
+typedef u16 compat_dev_t;
+typedef s32 compat_off_t;
+typedef s64 compat_loff_t;
+typedef s16 compat_nlink_t;
+typedef u16 compat_ipc_pid_t;
+typedef s32 compat_daddr_t;
+typedef u32 compat_caddr_t;
+typedef __kernel_fsid_t compat_fsid_t;
+typedef s32 compat_key_t;
+typedef s32 compat_timer_t;
+
+typedef s32 compat_int_t;
+typedef s32 compat_long_t;
+typedef s64 compat_s64;
+typedef u32 compat_uint_t;
+typedef u32 compat_ulong_t;
+typedef u64 compat_u64;
+
+struct compat_timespec {
+ compat_time_t tv_sec;
+ s32 tv_nsec;
+};
+
+struct compat_timeval {
+ compat_time_t tv_sec;
+ s32 tv_usec;
+};
+
+struct compat_stat {
+ compat_dev_t st_dev;
+ compat_ino_t st_ino;
+ compat_mode_t st_mode;
+ compat_nlink_t st_nlink;
+ __compat_uid_t st_uid;
+ __compat_gid_t st_gid;
+ compat_dev_t st_rdev;
+ compat_off_t st_size;
+ compat_time_t st_atime;
+ compat_ulong_t st_atime_nsec;
+ compat_time_t st_mtime;
+ compat_ulong_t st_mtime_nsec;
+ compat_time_t st_ctime;
+ compat_ulong_t st_ctime_nsec;
+ compat_off_t st_blksize;
+ compat_off_t st_blocks;
+ u32 __unused4[2];
+};
+
+struct compat_stat64 {
+ unsigned long long st_dev;
+
+ unsigned long long st_ino;
+
+ unsigned int st_mode;
+ unsigned int st_nlink;
+
+ unsigned int st_uid;
+ unsigned int st_gid;
+
+ unsigned long long st_rdev;
+
+ unsigned char __pad3[8];
+
+ long long st_size;
+ unsigned int st_blksize;
+
+ unsigned char __pad4[8];
+ unsigned int st_blocks;
+
+ unsigned int st_atime;
+ unsigned int st_atime_nsec;
+
+ unsigned int st_mtime;
+ unsigned int st_mtime_nsec;
+
+ unsigned int st_ctime;
+ unsigned int st_ctime_nsec;
+
+ unsigned int __unused4;
+ unsigned int __unused5;
+};
+
+struct compat_flock {
+ short l_type;
+ short l_whence;
+ compat_off_t l_start;
+ compat_off_t l_len;
+ compat_pid_t l_pid;
+ short __unused;
+};
+
+#define F_GETLK64 12
+#define F_SETLK64 13
+#define F_SETLKW64 14
+
+struct compat_flock64 {
+ short l_type;
+ short l_whence;
+ compat_loff_t l_start;
+ compat_loff_t l_len;
+ compat_pid_t l_pid;
+ short __unused;
+};
+
+struct compat_statfs {
+ int f_type;
+ int f_bsize;
+ int f_blocks;
+ int f_bfree;
+ int f_bavail;
+ int f_files;
+ int f_ffree;
+ compat_fsid_t f_fsid;
+ int f_namelen; /* SunOS ignores this field. */
+ int f_frsize;
+ int f_spare[5];
+};
+
+#define COMPAT_RLIM_INFINITY 0x7fffffff
+
+typedef u32 compat_old_sigset_t;
+
+#define _COMPAT_NSIG 64
+#define _COMPAT_NSIG_BPW 32
+
+typedef u32 compat_sigset_word;
+
+#define COMPAT_OFF_T_MAX 0x7fffffff
+#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
+
+/*
+ * A pointer passed in from user mode. This should not
+ * be used for syscall parameters, just declare them
+ * as pointers because the syscall entry code will have
+ * appropriately converted them already.
+ */
+typedef u32 compat_uptr_t;
+
+static inline void __user *compat_ptr(compat_uptr_t uptr)
+{
+ return (void __user *)(unsigned long)uptr;
+}
+
+static inline compat_uptr_t ptr_to_compat(void __user *uptr)
+{
+ return (u32)(unsigned long)uptr;
+}
+
+static inline void __user *compat_alloc_user_space(long len)
+{
+ struct pt_regs *regs = current_thread_info()->kregs;
+ unsigned long usp = regs->u_regs[UREG_I6];
+
+ if (!(test_thread_flag(TIF_32BIT)))
+ usp += STACK_BIAS;
+ else
+ usp &= 0xffffffffUL;
+
+ usp -= len;
+ usp &= ~0x7UL;
+
+ return (void __user *) usp;
+}
+
+struct compat_ipc64_perm {
+ compat_key_t key;
+ __compat_uid32_t uid;
+ __compat_gid32_t gid;
+ __compat_uid32_t cuid;
+ __compat_gid32_t cgid;
+ unsigned short __pad1;
+ compat_mode_t mode;
+ unsigned short __pad2;
+ unsigned short seq;
+ unsigned long __unused1; /* yes they really are 64bit pads */
+ unsigned long __unused2;
+};
+
+struct compat_semid64_ds {
+ struct compat_ipc64_perm sem_perm;
+ unsigned int __pad1;
+ compat_time_t sem_otime;
+ unsigned int __pad2;
+ compat_time_t sem_ctime;
+ u32 sem_nsems;
+ u32 __unused1;
+ u32 __unused2;
+};
+
+struct compat_msqid64_ds {
+ struct compat_ipc64_perm msg_perm;
+ unsigned int __pad1;
+ compat_time_t msg_stime;
+ unsigned int __pad2;
+ compat_time_t msg_rtime;
+ unsigned int __pad3;
+ compat_time_t msg_ctime;
+ unsigned int msg_cbytes;
+ unsigned int msg_qnum;
+ unsigned int msg_qbytes;
+ compat_pid_t msg_lspid;
+ compat_pid_t msg_lrpid;
+ unsigned int __unused1;
+ unsigned int __unused2;
+};
+
+struct compat_shmid64_ds {
+ struct compat_ipc64_perm shm_perm;
+ unsigned int __pad1;
+ compat_time_t shm_atime;
+ unsigned int __pad2;
+ compat_time_t shm_dtime;
+ unsigned int __pad3;
+ compat_time_t shm_ctime;
+ compat_size_t shm_segsz;
+ compat_pid_t shm_cpid;
+ compat_pid_t shm_lpid;
+ unsigned int shm_nattch;
+ unsigned int __unused1;
+ unsigned int __unused2;
+};
+
+#endif /* _ASM_SPARC64_COMPAT_H */
--- /dev/null
+#ifndef _COMPAT_SIGNAL_H
+#define _COMPAT_SIGNAL_H
+
+#include <linux/compat.h>
+#include <asm/signal.h>
+
+#ifdef CONFIG_COMPAT
+struct __new_sigaction32 {
+ unsigned sa_handler;
+ unsigned int sa_flags;
+ unsigned sa_restorer; /* not used by Linux/SPARC yet */
+ compat_sigset_t sa_mask;
+};
+
+struct __old_sigaction32 {
+ unsigned sa_handler;
+ compat_old_sigset_t sa_mask;
+ unsigned int sa_flags;
+ unsigned sa_restorer; /* not used by Linux/SPARC yet */
+};
+
+typedef struct sigaltstack32 {
+ u32 ss_sp;
+ int ss_flags;
+ compat_size_t ss_size;
+} stack_t32;
+#endif
+
+#endif /* !(_COMPAT_SIGNAL_H) */
--- /dev/null
+#ifndef _SPARC_CONTREGS_H
+#define _SPARC_CONTREGS_H
+
+/* contregs.h: Addresses of registers in the ASI_CONTROL alternate address
+ * space. These are for the mmu's context register, etc.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+/* 3=sun3
+ 4=sun4 (as in sun4 sysmaint student book)
+ c=sun4c (according to davem) */
+
+#define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
+#define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
+#define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
+#define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
+#define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
+#define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
+#define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
+#define AC_SYNC_ERR 0x60000000 /* c fault type */
+#define AC_SYNC_VA 0x60000004 /* c fault virtual address */
+#define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
+#define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */
+#define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */
+#define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */
+#define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */
+#define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */
+#define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */
+#define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/
+
+/* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */
+#define AC_M_PCR 0x0000 /* shv Processor Control Reg */
+#define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
+#define AC_M_CXR 0x0200 /* shv Context Register */
+#define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
+#define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
+#define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
+#define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
+#define AC_M_RESET 0x0700 /* hv Reset Reg */
+#define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
+#define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
+#define AC_M_IAPTP 0x1100 /* hv Instruction Access PTP */
+#define AC_M_DAPTP 0x1200 /* hv Data Access PTP */
+#define AC_M_ITR 0x1300 /* hv Index Tag Register */
+#define AC_M_TRCR 0x1400 /* hv TLB Replacement Control Reg */
+#define AC_M_SFSRX 0x1300 /* s Synch Fault Status Reg prim */
+#define AC_M_SFARX 0x1400 /* s Synch Fault Address Reg prim */
+#define AC_M_RPR1 0x1500 /* h Root Pointer Reg (entry 2) */
+#define AC_M_IAPTP1 0x1600 /* h Instruction Access PTP (entry 2) */
+#define AC_M_DAPTP1 0x1700 /* h Data Access PTP (entry 2) */
+
+#endif /* _SPARC_CONTREGS_H */
--- /dev/null
+#ifndef ___ASM_SPARC_CPUDATA_H
+#define ___ASM_SPARC_CPUDATA_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/cpudata_64.h>
+#else
+#include <asm/cpudata_32.h>
+#endif
+#endif
--- /dev/null
+/* cpudata.h: Per-cpu parameters.
+ *
+ * Copyright (C) 2004 Keith M Wesolowski (wesolows@foobazco.org)
+ *
+ * Based on include/asm/cpudata.h and Linux 2.4 smp.h
+ * both (C) David S. Miller.
+ */
+
+#ifndef _SPARC_CPUDATA_H
+#define _SPARC_CPUDATA_H
+
+#include <linux/percpu.h>
+
+typedef struct {
+ unsigned long udelay_val;
+ unsigned long clock_tick;
+ unsigned int multiplier;
+ unsigned int counter;
+ int prom_node;
+ int mid;
+ int next;
+} cpuinfo_sparc;
+
+DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
+#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
+
+#endif /* _SPARC_CPUDATA_H */
--- /dev/null
+/* cpudata.h: Per-cpu parameters.
+ *
+ * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC64_CPUDATA_H
+#define _SPARC64_CPUDATA_H
+
+#include <asm/hypervisor.h>
+#include <asm/asi.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/percpu.h>
+#include <linux/threads.h>
+
+typedef struct {
+ /* Dcache line 1 */
+ unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
+ unsigned int __pad0;
+ unsigned long clock_tick; /* %tick's per second */
+ unsigned long __pad;
+ unsigned int __pad1;
+ unsigned int __pad2;
+
+ /* Dcache line 2, rarely used */
+ unsigned int dcache_size;
+ unsigned int dcache_line_size;
+ unsigned int icache_size;
+ unsigned int icache_line_size;
+ unsigned int ecache_size;
+ unsigned int ecache_line_size;
+ int core_id;
+ int proc_id;
+} cpuinfo_sparc;
+
+DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
+#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
+#define local_cpu_data() __get_cpu_var(__cpu_data)
+
+/* Trap handling code needs to get at a few critical values upon
+ * trap entry and to process TSB misses. These cannot be in the
+ * per_cpu() area as we really need to lock them into the TLB and
+ * thus make them part of the main kernel image. As a result we
+ * try to make this as small as possible.
+ *
+ * This is padded out and aligned to 64-bytes to avoid false sharing
+ * on SMP.
+ */
+
+/* If you modify the size of this structure, please update
+ * TRAP_BLOCK_SZ_SHIFT below.
+ */
+struct thread_info;
+struct trap_per_cpu {
+/* D-cache line 1: Basic thread information, cpu and device mondo queues */
+ struct thread_info *thread;
+ unsigned long pgd_paddr;
+ unsigned long cpu_mondo_pa;
+ unsigned long dev_mondo_pa;
+
+/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
+ unsigned long resum_mondo_pa;
+ unsigned long resum_kernel_buf_pa;
+ unsigned long nonresum_mondo_pa;
+ unsigned long nonresum_kernel_buf_pa;
+
+/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
+ struct hv_fault_status fault_info;
+
+/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list. */
+ unsigned long cpu_mondo_block_pa;
+ unsigned long cpu_list_pa;
+ unsigned long tsb_huge;
+ unsigned long tsb_huge_temp;
+
+/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */
+ unsigned long irq_worklist_pa;
+ unsigned int cpu_mondo_qmask;
+ unsigned int dev_mondo_qmask;
+ unsigned int resum_qmask;
+ unsigned int nonresum_qmask;
+ void *hdesc;
+} __attribute__((aligned(64)));
+extern struct trap_per_cpu trap_block[NR_CPUS];
+extern void init_cur_cpu_trap(struct thread_info *);
+extern void setup_tba(void);
+extern int ncpus_probed;
+extern void __init cpu_probe(void);
+extern const struct seq_operations cpuinfo_op;
+
+extern unsigned long real_hard_smp_processor_id(void);
+
+struct cpuid_patch_entry {
+ unsigned int addr;
+ unsigned int cheetah_safari[4];
+ unsigned int cheetah_jbus[4];
+ unsigned int starfire[4];
+ unsigned int sun4v[4];
+};
+extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
+
+struct sun4v_1insn_patch_entry {
+ unsigned int addr;
+ unsigned int insn;
+};
+extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
+ __sun4v_1insn_patch_end;
+
+struct sun4v_2insn_patch_entry {
+ unsigned int addr;
+ unsigned int insns[2];
+};
+extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
+ __sun4v_2insn_patch_end;
+
+#endif /* !(__ASSEMBLY__) */
+
+#define TRAP_PER_CPU_THREAD 0x00
+#define TRAP_PER_CPU_PGD_PADDR 0x08
+#define TRAP_PER_CPU_CPU_MONDO_PA 0x10
+#define TRAP_PER_CPU_DEV_MONDO_PA 0x18
+#define TRAP_PER_CPU_RESUM_MONDO_PA 0x20
+#define TRAP_PER_CPU_RESUM_KBUF_PA 0x28
+#define TRAP_PER_CPU_NONRESUM_MONDO_PA 0x30
+#define TRAP_PER_CPU_NONRESUM_KBUF_PA 0x38
+#define TRAP_PER_CPU_FAULT_INFO 0x40
+#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
+#define TRAP_PER_CPU_CPU_LIST_PA 0xc8
+#define TRAP_PER_CPU_TSB_HUGE 0xd0
+#define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8
+#define TRAP_PER_CPU_IRQ_WORKLIST_PA 0xe0
+#define TRAP_PER_CPU_CPU_MONDO_QMASK 0xe8
+#define TRAP_PER_CPU_DEV_MONDO_QMASK 0xec
+#define TRAP_PER_CPU_RESUM_QMASK 0xf0
+#define TRAP_PER_CPU_NONRESUM_QMASK 0xf4
+
+#define TRAP_BLOCK_SZ_SHIFT 8
+
+#include <asm/scratchpad.h>
+
+#define __GET_CPUID(REG) \
+ /* Spitfire implementation (default). */ \
+661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
+ srlx REG, 17, REG; \
+ and REG, 0x1f, REG; \
+ nop; \
+ .section .cpuid_patch, "ax"; \
+ /* Instruction location. */ \
+ .word 661b; \
+ /* Cheetah Safari implementation. */ \
+ ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
+ srlx REG, 17, REG; \
+ and REG, 0x3ff, REG; \
+ nop; \
+ /* Cheetah JBUS implementation. */ \
+ ldxa [%g0] ASI_JBUS_CONFIG, REG; \
+ srlx REG, 17, REG; \
+ and REG, 0x1f, REG; \
+ nop; \
+ /* Starfire implementation. */ \
+ sethi %hi(0x1fff40000d0 >> 9), REG; \
+ sllx REG, 9, REG; \
+ or REG, 0xd0, REG; \
+ lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
+ /* sun4v implementation. */ \
+ mov SCRATCHPAD_CPUID, REG; \
+ ldxa [REG] ASI_SCRATCHPAD, REG; \
+ nop; \
+ nop; \
+ .previous;
+
+#ifdef CONFIG_SMP
+
+#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
+ __GET_CPUID(TMP) \
+ sethi %hi(trap_block), DEST; \
+ sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
+ or DEST, %lo(trap_block), DEST; \
+ add DEST, TMP, DEST; \
+
+/* Clobbers TMP, current address space PGD phys address into DEST. */
+#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
+ TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
+ ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
+
+/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
+#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \
+ TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
+ add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
+
+/* Clobbers TMP, loads DEST with current thread info pointer. */
+#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
+ TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
+ ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
+
+/* Given the current thread info pointer in THR, load the per-cpu
+ * area base of the current processor into DEST. REG1, REG2, and REG3 are
+ * clobbered.
+ *
+ * You absolutely cannot use DEST as a temporary in this code. The
+ * reason is that traps can happen during execution, and return from
+ * trap will load the fully resolved DEST per-cpu base. This can corrupt
+ * the calculations done by the macro mid-stream.
+ */
+#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
+ lduh [THR + TI_CPU], REG1; \
+ sethi %hi(__per_cpu_shift), REG3; \
+ sethi %hi(__per_cpu_base), REG2; \
+ ldx [REG3 + %lo(__per_cpu_shift)], REG3; \
+ ldx [REG2 + %lo(__per_cpu_base)], REG2; \
+ sllx REG1, REG3, REG3; \
+ add REG3, REG2, DEST;
+
+#else
+
+#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
+ sethi %hi(trap_block), DEST; \
+ or DEST, %lo(trap_block), DEST; \
+
+/* Uniprocessor versions, we know the cpuid is zero. */
+#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
+ TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
+ ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
+
+/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
+#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \
+ TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
+ add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
+
+#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
+ TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
+ ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
+
+/* No per-cpu areas on uniprocessor, so no need to load DEST. */
+#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
+
+#endif /* !(CONFIG_SMP) */
+
+#endif /* _SPARC64_CPUDATA_H */
--- /dev/null
+#ifndef __SPARC_CPUTIME_H
+#define __SPARC_CPUTIME_H
+
+#include <asm-generic/cputime.h>
+
+#endif /* __SPARC_CPUTIME_H */
--- /dev/null
+/* include/asm/current.h
+ *
+ * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ * Copyright (C) 2002 Pete Zaitcev (zaitcev@yahoo.com)
+ * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
+ *
+ * Derived from "include/asm-s390/current.h" by
+ * Martin Schwidefsky (schwidefsky@de.ibm.com)
+ * Derived from "include/asm-i386/current.h"
+*/
+#ifndef _SPARC_CURRENT_H
+#define _SPARC_CURRENT_H
+
+#include <linux/thread_info.h>
+
+#ifdef CONFIG_SPARC64
+register struct task_struct *current asm("g4");
+#endif
+
+#ifdef CONFIG_SPARC32
+/* We might want to consider using %g4 like sparc64 to shave a few cycles.
+ *
+ * Two stage process (inline + #define) for type-checking.
+ * We also obfuscate get_current() to check if anyone used that by mistake.
+ */
+struct task_struct;
+static inline struct task_struct *__get_current(void)
+{
+ return current_thread_info()->task;
+}
+#define current __get_current()
+#endif
+
+#endif /* !(_SPARC_CURRENT_H) */
--- /dev/null
+/*
+ * cypress.h: Cypress module specific definitions and defines.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_CYPRESS_H
+#define _SPARC_CYPRESS_H
+
+/* Cypress chips have %psr 'impl' of '0001' and 'vers' of '0001'. */
+
+/* The MMU control register fields on the Sparc Cypress 604/605 MMU's.
+ *
+ * ---------------------------------------------------------------
+ * |implvers| MCA | MCM |MV| MID |BM| C|RSV|MR|CM|CL|CE|RSV|NF|ME|
+ * ---------------------------------------------------------------
+ * 31 24 23-22 21-20 19 18-15 14 13 12 11 10 9 8 7-2 1 0
+ *
+ * MCA: MultiChip Access -- Used for configuration of multiple
+ * CY7C604/605 cache units.
+ * MCM: MultiChip Mask -- Again, for multiple cache unit config.
+ * MV: MultiChip Valid -- Indicates MCM and MCA have valid settings.
+ * MID: ModuleID -- Unique processor ID for MBus transactions. (605 only)
+ * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
+ * C: Cacheable -- Indicates whether accesses are cacheable while
+ * the MMU is off. 0=no 1=yes
+ * MR: MemoryReflection -- Indicates whether the bus attached to the
+ * MBus supports memory reflection. 0=no 1=yes (605 only)
+ * CM: CacheMode -- Indicates whether the cache is operating in write
+ * through or copy-back mode. 0=write-through 1=copy-back
+ * CL: CacheLock -- Indicates if the entire cache is locked or not.
+ * 0=not-locked 1=locked (604 only)
+ * CE: CacheEnable -- Is the virtual cache on? 0=no 1=yes
+ * NF: NoFault -- Do faults generate traps? 0=yes 1=no
+ * ME: MmuEnable -- Is the MMU doing translations? 0=no 1=yes
+ */
+
+#define CYPRESS_MCA 0x00c00000
+#define CYPRESS_MCM 0x00300000
+#define CYPRESS_MVALID 0x00080000
+#define CYPRESS_MIDMASK 0x00078000 /* Only on 605 */
+#define CYPRESS_BMODE 0x00004000
+#define CYPRESS_ACENABLE 0x00002000
+#define CYPRESS_MRFLCT 0x00000800 /* Only on 605 */
+#define CYPRESS_CMODE 0x00000400
+#define CYPRESS_CLOCK 0x00000200 /* Only on 604 */
+#define CYPRESS_CENABLE 0x00000100
+#define CYPRESS_NFAULT 0x00000002
+#define CYPRESS_MENABLE 0x00000001
+
+static inline void cypress_flush_page(unsigned long page)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+ "r" (page), "i" (ASI_M_FLUSH_PAGE));
+}
+
+static inline void cypress_flush_segment(unsigned long addr)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+ "r" (addr), "i" (ASI_M_FLUSH_SEG));
+}
+
+static inline void cypress_flush_region(unsigned long addr)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+ "r" (addr), "i" (ASI_M_FLUSH_REGION));
+}
+
+static inline void cypress_flush_context(void)
+{
+ __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
+ "i" (ASI_M_FLUSH_CTX));
+}
+
+/* XXX Displacement flushes for buggy chips and initial testing
+ * XXX go here.
+ */
+
+#endif /* !(_SPARC_CYPRESS_H) */
--- /dev/null
+#ifndef _SPARC64_DCR_H
+#define _SPARC64_DCR_H
+
+/* UltraSparc-III/III+ Dispatch Control Register, ASR 0x12 */
+#define DCR_DPE 0x0000000000001000 /* III+: D$ Parity Error Enable */
+#define DCR_OBS 0x0000000000000fc0 /* Observability Bus Controls */
+#define DCR_BPE 0x0000000000000020 /* Branch Predict Enable */
+#define DCR_RPE 0x0000000000000010 /* Return Address Prediction Enable */
+#define DCR_SI 0x0000000000000008 /* Single Instruction Disable */
+#define DCR_IPE 0x0000000000000004 /* III+: I$ Parity Error Enable */
+#define DCR_IFPOE 0x0000000000000002 /* IRQ FP Operation Enable */
+#define DCR_MS 0x0000000000000001 /* Multi-Scalar dispatch */
+
+#endif /* _SPARC64_DCR_H */
--- /dev/null
+#ifndef _SPARC64_DCU_H
+#define _SPARC64_DCU_H
+
+#include <linux/const.h>
+
+/* UltraSparc-III Data Cache Unit Control Register */
+#define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */
+#define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */
+#define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */
+#define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */
+#define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */
+#define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */
+#define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */
+#define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/
+#define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */
+#define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */
+#define DCU_VM _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask */
+#define DCU_PR _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */
+#define DCU_PW _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/
+#define DCU_VR _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */
+#define DCU_VW _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/
+#define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */
+#define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */
+#define DCU_DC _AC(0x0000000000000002,UL) /* Data Cache Enable */
+#define DCU_IC _AC(0x0000000000000001,UL) /* Instruction Cache Enable */
+
+#endif /* _SPARC64_DCU_H */
--- /dev/null
+#ifndef ___ASM_SPARC_DELAY_H
+#define ___ASM_SPARC_DELAY_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/delay_64.h>
+#else
+#include <asm/delay_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * delay.h: Linux delay routines on the Sparc.
+ *
+ * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu).
+ */
+
+#ifndef __SPARC_DELAY_H
+#define __SPARC_DELAY_H
+
+#include <asm/cpudata.h>
+
+static inline void __delay(unsigned long loops)
+{
+ __asm__ __volatile__("cmp %0, 0\n\t"
+ "1: bne 1b\n\t"
+ "subcc %0, 1, %0\n" :
+ "=&r" (loops) :
+ "0" (loops) :
+ "cc");
+}
+
+/* This is too messy with inline asm on the Sparc. */
+extern void __udelay(unsigned long usecs, unsigned long lpj);
+extern void __ndelay(unsigned long nsecs, unsigned long lpj);
+
+#ifdef CONFIG_SMP
+#define __udelay_val cpu_data(smp_processor_id()).udelay_val
+#else /* SMP */
+#define __udelay_val loops_per_jiffy
+#endif /* SMP */
+#define udelay(__usecs) __udelay(__usecs, __udelay_val)
+#define ndelay(__nsecs) __ndelay(__nsecs, __udelay_val)
+
+#endif /* defined(__SPARC_DELAY_H) */
--- /dev/null
+/* delay.h: Linux delay routines on sparc64.
+ *
+ * Copyright (C) 1996, 2004, 2007 David S. Miller (davem@davemloft.net).
+ */
+
+#ifndef _SPARC64_DELAY_H
+#define _SPARC64_DELAY_H
+
+#ifndef __ASSEMBLY__
+
+extern void __delay(unsigned long loops);
+extern void udelay(unsigned long usecs);
+#define mdelay(n) udelay((n) * 1000)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _SPARC64_DELAY_H */
--- /dev/null
+/*
+ * Arch specific extensions to struct device
+ *
+ * This file is released under the GPLv2
+ */
+#ifndef _ASM_SPARC_DEVICE_H
+#define _ASM_SPARC_DEVICE_H
+
+struct device_node;
+struct of_device;
+
+struct dev_archdata {
+ void *iommu;
+ void *stc;
+ void *host_controller;
+
+ struct device_node *prom_node;
+ struct of_device *op;
+
+ int numa_node;
+};
+
+#endif /* _ASM_SPARC_DEVICE_H */
--- /dev/null
+/*
+ *
+ * display7seg - Driver interface for the 7-segment display
+ * present on Sun Microsystems CP1400 and CP1500
+ *
+ * Copyright (c) 2000 Eric Brower <ebrower@usa.net>
+ *
+ */
+
+#ifndef __display7seg_h__
+#define __display7seg_h__
+
+#define D7S_IOC 'p'
+
+#define D7SIOCRD _IOR(D7S_IOC, 0x45, int) /* Read device state */
+#define D7SIOCWR _IOW(D7S_IOC, 0x46, int) /* Write device state */
+#define D7SIOCTM _IO (D7S_IOC, 0x47) /* Translate mode (FLIP)*/
+
+/*
+ * ioctl flag definitions
+ *
+ * POINT - Toggle decimal point (0=absent 1=present)
+ * ALARM - Toggle alarm LED (0=green 1=red)
+ * FLIP - Toggle inverted mode (0=normal 1=flipped)
+ * bits 0-4 - Character displayed (see definitions below)
+ *
+ * Display segments are defined as follows,
+ * subject to D7S_FLIP register state:
+ *
+ * a
+ * ---
+ * f| |b
+ * -g-
+ * e| |c
+ * ---
+ * d
+ */
+
+#define D7S_POINT (1 << 7) /* Decimal point*/
+#define D7S_ALARM (1 << 6) /* Alarm LED */
+#define D7S_FLIP (1 << 5) /* Flip display */
+
+#define D7S_0 0x00 /* Numerals 0-9 */
+#define D7S_1 0x01
+#define D7S_2 0x02
+#define D7S_3 0x03
+#define D7S_4 0x04
+#define D7S_5 0x05
+#define D7S_6 0x06
+#define D7S_7 0x07
+#define D7S_8 0x08
+#define D7S_9 0x09
+#define D7S_A 0x0A /* Letters A-F, H, L, P */
+#define D7S_B 0x0B
+#define D7S_C 0x0C
+#define D7S_D 0x0D
+#define D7S_E 0x0E
+#define D7S_F 0x0F
+#define D7S_H 0x10
+#define D7S_E2 0x11
+#define D7S_L 0x12
+#define D7S_P 0x13
+#define D7S_SEGA 0x14 /* Individual segments */
+#define D7S_SEGB 0x15
+#define D7S_SEGC 0x16
+#define D7S_SEGD 0x17
+#define D7S_SEGE 0x18
+#define D7S_SEGF 0x19
+#define D7S_SEGG 0x1A
+#define D7S_SEGABFG 0x1B /* Segment groupings */
+#define D7S_SEGCDEG 0x1C
+#define D7S_SEGBCEF 0x1D
+#define D7S_SEGADG 0x1E
+#define D7S_BLANK 0x1F /* Clear all segments */
+
+#define D7S_MIN_VAL 0x0
+#define D7S_MAX_VAL 0x1F
+
+#endif /* ifndef __display7seg_h__ */
--- /dev/null
+#include <asm-generic/div64.h>
--- /dev/null
+#ifndef ___ASM_SPARC_DMA_MAPPING_H
+#define ___ASM_SPARC_DMA_MAPPING_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/dma-mapping_64.h>
+#else
+#include <asm/dma-mapping_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _ASM_SPARC_DMA_MAPPING_H
+#define _ASM_SPARC_DMA_MAPPING_H
+
+
+#ifdef CONFIG_PCI
+#include <asm-generic/dma-mapping.h>
+#else
+#include <asm-generic/dma-mapping-broken.h>
+#endif /* PCI */
+
+#endif /* _ASM_SPARC_DMA_MAPPING_H */
--- /dev/null
+#ifndef _ASM_SPARC64_DMA_MAPPING_H
+#define _ASM_SPARC64_DMA_MAPPING_H
+
+#include <linux/scatterlist.h>
+#include <linux/mm.h>
+
+#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
+
+struct dma_ops {
+ void *(*alloc_coherent)(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag);
+ void (*free_coherent)(struct device *dev, size_t size,
+ void *cpu_addr, dma_addr_t dma_handle);
+ dma_addr_t (*map_single)(struct device *dev, void *cpu_addr,
+ size_t size,
+ enum dma_data_direction direction);
+ void (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
+ size_t size,
+ enum dma_data_direction direction);
+ int (*map_sg)(struct device *dev, struct scatterlist *sg, int nents,
+ enum dma_data_direction direction);
+ void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
+ int nhwentries,
+ enum dma_data_direction direction);
+ void (*sync_single_for_cpu)(struct device *dev,
+ dma_addr_t dma_handle, size_t size,
+ enum dma_data_direction direction);
+ void (*sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg,
+ int nelems,
+ enum dma_data_direction direction);
+};
+extern const struct dma_ops *dma_ops;
+
+extern int dma_supported(struct device *dev, u64 mask);
+extern int dma_set_mask(struct device *dev, u64 dma_mask);
+
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag)
+{
+ return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
+}
+
+static inline void dma_free_coherent(struct device *dev, size_t size,
+ void *cpu_addr, dma_addr_t dma_handle)
+{
+ dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
+}
+
+static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
+ size_t size,
+ enum dma_data_direction direction)
+{
+ return dma_ops->map_single(dev, cpu_addr, size, direction);
+}
+
+static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
+ size_t size,
+ enum dma_data_direction direction)
+{
+ dma_ops->unmap_single(dev, dma_addr, size, direction);
+}
+
+static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
+ unsigned long offset, size_t size,
+ enum dma_data_direction direction)
+{
+ return dma_ops->map_single(dev, page_address(page) + offset,
+ size, direction);
+}
+
+static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+ size_t size,
+ enum dma_data_direction direction)
+{
+ dma_ops->unmap_single(dev, dma_address, size, direction);
+}
+
+static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
+ int nents, enum dma_data_direction direction)
+{
+ return dma_ops->map_sg(dev, sg, nents, direction);
+}
+
+static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+ int nents, enum dma_data_direction direction)
+{
+ dma_ops->unmap_sg(dev, sg, nents, direction);
+}
+
+static inline void dma_sync_single_for_cpu(struct device *dev,
+ dma_addr_t dma_handle, size_t size,
+ enum dma_data_direction direction)
+{
+ dma_ops->sync_single_for_cpu(dev, dma_handle, size, direction);
+}
+
+static inline void dma_sync_single_for_device(struct device *dev,
+ dma_addr_t dma_handle,
+ size_t size,
+ enum dma_data_direction direction)
+{
+ /* No flushing needed to sync cpu writes to the device. */
+}
+
+static inline void dma_sync_single_range_for_cpu(struct device *dev,
+ dma_addr_t dma_handle,
+ unsigned long offset,
+ size_t size,
+ enum dma_data_direction direction)
+{
+ dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
+}
+
+static inline void dma_sync_single_range_for_device(struct device *dev,
+ dma_addr_t dma_handle,
+ unsigned long offset,
+ size_t size,
+ enum dma_data_direction direction)
+{
+ /* No flushing needed to sync cpu writes to the device. */
+}
+
+
+static inline void dma_sync_sg_for_cpu(struct device *dev,
+ struct scatterlist *sg, int nelems,
+ enum dma_data_direction direction)
+{
+ dma_ops->sync_sg_for_cpu(dev, sg, nelems, direction);
+}
+
+static inline void dma_sync_sg_for_device(struct device *dev,
+ struct scatterlist *sg, int nelems,
+ enum dma_data_direction direction)
+{
+ /* No flushing needed to sync cpu writes to the device. */
+}
+
+static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+ return (dma_addr == DMA_ERROR_CODE);
+}
+
+static inline int dma_get_cache_alignment(void)
+{
+ /* no easy way to get cache size on all processors, so return
+ * the maximum possible, to be safe */
+ return (1 << INTERNODE_CACHE_SHIFT);
+}
+
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+#define dma_is_consistent(d, h) (1)
+
+#endif /* _ASM_SPARC64_DMA_MAPPING_H */
--- /dev/null
+#ifndef ___ASM_SPARC_DMA_H
+#define ___ASM_SPARC_DMA_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/dma_64.h>
+#else
+#include <asm/dma_32.h>
+#endif
+#endif
--- /dev/null
+/* include/asm/dma.h
+ *
+ * Copyright 1995 (C) David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _ASM_SPARC_DMA_H
+#define _ASM_SPARC_DMA_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include <asm/vac-ops.h> /* for invalidate's, etc. */
+#include <asm/sbus.h>
+#include <asm/delay.h>
+#include <asm/oplib.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <linux/spinlock.h>
+
+struct page;
+extern spinlock_t dma_spin_lock;
+
+static inline unsigned long claim_dma_lock(void)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&dma_spin_lock, flags);
+ return flags;
+}
+
+static inline void release_dma_lock(unsigned long flags)
+{
+ spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* These are irrelevant for Sparc DMA, but we leave it in so that
+ * things can compile.
+ */
+#define MAX_DMA_CHANNELS 8
+#define MAX_DMA_ADDRESS (~0UL)
+#define DMA_MODE_READ 1
+#define DMA_MODE_WRITE 2
+
+/* Useful constants */
+#define SIZE_16MB (16*1024*1024)
+#define SIZE_64K (64*1024)
+
+/* SBUS DMA controller reg offsets */
+#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
+#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
+#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
+#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
+
+/* DVMA chip revisions */
+enum dvma_rev {
+ dvmarev0,
+ dvmaesc1,
+ dvmarev1,
+ dvmarev2,
+ dvmarev3,
+ dvmarevplus,
+ dvmahme
+};
+
+#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
+
+/* Linux DMA information structure, filled during probe. */
+struct sbus_dma {
+ struct sbus_dma *next;
+ struct sbus_dev *sdev;
+ void __iomem *regs;
+
+ /* Status, misc info */
+ int node; /* Prom node for this DMA device */
+ int running; /* Are we doing DMA now? */
+ int allocated; /* Are we "owned" by anyone yet? */
+
+ /* Transfer information. */
+ unsigned long addr; /* Start address of current transfer */
+ int nbytes; /* Size of current transfer */
+ int realbytes; /* For splitting up large transfers, etc. */
+
+ /* DMA revision */
+ enum dvma_rev revision;
+};
+
+extern struct sbus_dma *dma_chain;
+
+/* Broken hardware... */
+#ifdef CONFIG_SUN4
+/* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken?
+ * Or is rev0 present only on sun4 boxes? -jj */
+#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1)
+#else
+#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
+#endif
+#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
+
+/* Main routines in dma.c */
+extern void dvma_init(struct sbus_bus *);
+
+/* Fields in the cond_reg register */
+/* First, the version identification bits */
+#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
+#define DMA_VERS0 0x00000000 /* Sunray DMA version */
+#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
+#define DMA_VERS1 0x80000000 /* DMA rev 1 */
+#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
+#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
+#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
+
+#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
+#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
+#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
+#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
+#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
+#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
+#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
+#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
+#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
+#define DMA_RST_BPP DMA_RST_SCSI /* Reset the BPP controller */
+#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
+#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
+#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
+#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
+#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
+#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
+#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
+#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
+#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
+#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
+#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
+#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
+#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
+#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
+#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
+#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
+#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
+#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
+#define DMA_BRST32 0x00040000 /* SCSI/BPP: 32byte bursts */
+#define DMA_BRST16 0x00000000 /* SCSI/BPP: 16byte bursts */
+#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
+#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
+#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
+#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
+#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
+#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
+#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
+#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
+#define DMA_BPP_ON DMA_SCSI_ON /* Enable BPP dma */
+#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
+#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
+#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
+#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
+
+/* Values describing the burst-size property from the PROM */
+#define DMA_BURST1 0x01
+#define DMA_BURST2 0x02
+#define DMA_BURST4 0x04
+#define DMA_BURST8 0x08
+#define DMA_BURST16 0x10
+#define DMA_BURST32 0x20
+#define DMA_BURST64 0x40
+#define DMA_BURSTBITS 0x7f
+
+/* Determine highest possible final transfer address given a base */
+#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
+
+/* Yes, I hack a lot of elisp in my spare time... */
+#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
+#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
+#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
+#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
+#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
+#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
+#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
+#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
+#define DMA_BEGINDMA_W(regs) \
+ ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
+#define DMA_BEGINDMA_R(regs) \
+ ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
+
+/* For certain DMA chips, we need to disable ints upon irq entry
+ * and turn them back on when we are done. So in any ESP interrupt
+ * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
+ * when leaving the handler. You have been warned...
+ */
+#define DMA_IRQ_ENTRY(dma, dregs) do { \
+ if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
+ } while (0)
+
+#define DMA_IRQ_EXIT(dma, dregs) do { \
+ if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
+ } while(0)
+
+#if 0 /* P3 this stuff is inline in ledma.c:init_restart_ledma() */
+/* Pause until counter runs out or BIT isn't set in the DMA condition
+ * register.
+ */
+static inline void sparc_dma_pause(struct sparc_dma_registers *regs,
+ unsigned long bit)
+{
+ int ctr = 50000; /* Let's find some bugs ;) */
+
+ /* Busy wait until the bit is not set any more */
+ while((regs->cond_reg&bit) && (ctr>0)) {
+ ctr--;
+ __delay(5);
+ }
+
+ /* Check for bogus outcome. */
+ if(!ctr)
+ panic("DMA timeout");
+}
+
+/* Reset the friggin' thing... */
+#define DMA_RESET(dma) do { \
+ struct sparc_dma_registers *regs = dma->regs; \
+ /* Let the current FIFO drain itself */ \
+ sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
+ /* Reset the logic */ \
+ regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
+ __delay(400); /* let the bits set ;) */ \
+ regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
+ sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
+ /* Enable FAST transfers if available */ \
+ if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
+ dma->running = 0; \
+} while(0)
+#endif
+
+#define for_each_dvma(dma) \
+ for((dma) = dma_chain; (dma); (dma) = (dma)->next)
+
+extern int get_dma_list(char *);
+extern int request_dma(unsigned int, __const__ char *);
+extern void free_dma(unsigned int);
+
+/* From PCI */
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy (0)
+#endif
+
+/* Routines for data transfer buffers. */
+BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long)
+BTFIXUPDEF_CALL(void, mmu_unlockarea, char *, unsigned long)
+
+#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len)
+#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len)
+
+/* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */
+BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, char *, unsigned long, struct sbus_bus *sbus)
+BTFIXUPDEF_CALL(void, mmu_get_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
+BTFIXUPDEF_CALL(void, mmu_release_scsi_one, __u32, unsigned long, struct sbus_bus *sbus)
+BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
+
+#define mmu_get_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_get_scsi_one)(vaddr,len,sbus)
+#define mmu_get_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_get_scsi_sgl)(sg,sz,sbus)
+#define mmu_release_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_release_scsi_one)(vaddr,len,sbus)
+#define mmu_release_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_release_scsi_sgl)(sg,sz,sbus)
+
+/*
+ * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep.
+ *
+ * The mmu_map_dma_area establishes two mappings in one go.
+ * These mappings point to pages normally mapped at 'va' (linear address).
+ * First mapping is for CPU visible address at 'a', uncached.
+ * This is an alias, but it works because it is an uncached mapping.
+ * Second mapping is for device visible address, or "bus" address.
+ * The bus address is returned at '*pba'.
+ *
+ * These functions seem distinct, but are hard to split. On sun4c,
+ * at least for now, 'a' is equal to bus address, and retured in *pba.
+ * On sun4m, page attributes depend on the CPU type, so we have to
+ * know if we are mapping RAM or I/O, so it has to be an additional argument
+ * to a separate mapping function for CPU visible mappings.
+ */
+BTFIXUPDEF_CALL(int, mmu_map_dma_area, dma_addr_t *, unsigned long, unsigned long, int len)
+BTFIXUPDEF_CALL(struct page *, mmu_translate_dvma, unsigned long busa)
+BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, unsigned long busa, int len)
+
+#define mmu_map_dma_area(pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(pba,va,a,len)
+#define mmu_unmap_dma_area(ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(ba,len)
+#define mmu_translate_dvma(ba) BTFIXUP_CALL(mmu_translate_dvma)(ba)
+
+#endif /* !(_ASM_SPARC_DMA_H) */
--- /dev/null
+/*
+ * include/asm/dma.h
+ *
+ * Copyright 1996 (C) David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _ASM_SPARC64_DMA_H
+#define _ASM_SPARC64_DMA_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+
+#include <asm/sbus.h>
+#include <asm/delay.h>
+#include <asm/oplib.h>
+
+/* These are irrelevant for Sparc DMA, but we leave it in so that
+ * things can compile.
+ */
+#define MAX_DMA_CHANNELS 8
+#define DMA_MODE_READ 1
+#define DMA_MODE_WRITE 2
+#define MAX_DMA_ADDRESS (~0UL)
+
+/* Useful constants */
+#define SIZE_16MB (16*1024*1024)
+#define SIZE_64K (64*1024)
+
+/* SBUS DMA controller reg offsets */
+#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
+#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
+#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
+#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
+
+/* DVMA chip revisions */
+enum dvma_rev {
+ dvmarev0,
+ dvmaesc1,
+ dvmarev1,
+ dvmarev2,
+ dvmarev3,
+ dvmarevplus,
+ dvmahme
+};
+
+#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
+
+/* Linux DMA information structure, filled during probe. */
+struct sbus_dma {
+ struct sbus_dma *next;
+ struct sbus_dev *sdev;
+ void __iomem *regs;
+
+ /* Status, misc info */
+ int node; /* Prom node for this DMA device */
+ int running; /* Are we doing DMA now? */
+ int allocated; /* Are we "owned" by anyone yet? */
+
+ /* Transfer information. */
+ u32 addr; /* Start address of current transfer */
+ int nbytes; /* Size of current transfer */
+ int realbytes; /* For splitting up large transfers, etc. */
+
+ /* DMA revision */
+ enum dvma_rev revision;
+};
+
+extern struct sbus_dma *dma_chain;
+
+/* Broken hardware... */
+#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
+#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
+
+/* Main routines in dma.c */
+extern void dvma_init(struct sbus_bus *);
+
+/* Fields in the cond_reg register */
+/* First, the version identification bits */
+#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
+#define DMA_VERS0 0x00000000 /* Sunray DMA version */
+#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
+#define DMA_VERS1 0x80000000 /* DMA rev 1 */
+#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
+#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
+#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
+
+#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
+#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
+#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
+#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
+#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
+#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
+#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
+#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
+#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
+#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
+#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
+#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
+#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
+#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
+#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
+#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
+#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
+#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
+#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
+#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
+#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
+#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
+#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
+#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
+#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
+#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
+#define DMA_BRST64 0x000c0000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
+#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
+#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
+#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
+#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
+#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
+#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
+#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
+#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
+#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
+#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
+#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
+#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
+#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
+#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
+
+/* Values describing the burst-size property from the PROM */
+#define DMA_BURST1 0x01
+#define DMA_BURST2 0x02
+#define DMA_BURST4 0x04
+#define DMA_BURST8 0x08
+#define DMA_BURST16 0x10
+#define DMA_BURST32 0x20
+#define DMA_BURST64 0x40
+#define DMA_BURSTBITS 0x7f
+
+/* Determine highest possible final transfer address given a base */
+#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
+
+/* Yes, I hack a lot of elisp in my spare time... */
+#define DMA_ERROR_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_HNDL_ERROR))
+#define DMA_IRQ_P(regs) ((sbus_readl((regs) + DMA_CSR)) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
+#define DMA_WRITE_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_ST_WRITE))
+#define DMA_OFF(__regs) \
+do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
+ tmp &= ~DMA_ENABLE; \
+ sbus_writel(tmp, (__regs) + DMA_CSR); \
+} while(0)
+#define DMA_INTSOFF(__regs) \
+do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
+ tmp &= ~DMA_INT_ENAB; \
+ sbus_writel(tmp, (__regs) + DMA_CSR); \
+} while(0)
+#define DMA_INTSON(__regs) \
+do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
+ tmp |= DMA_INT_ENAB; \
+ sbus_writel(tmp, (__regs) + DMA_CSR); \
+} while(0)
+#define DMA_PUNTFIFO(__regs) \
+do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
+ tmp |= DMA_FIFO_INV; \
+ sbus_writel(tmp, (__regs) + DMA_CSR); \
+} while(0)
+#define DMA_SETSTART(__regs, __addr) \
+ sbus_writel((u32)(__addr), (__regs) + DMA_ADDR);
+#define DMA_BEGINDMA_W(__regs) \
+do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
+ tmp |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB); \
+ sbus_writel(tmp, (__regs) + DMA_CSR); \
+} while(0)
+#define DMA_BEGINDMA_R(__regs) \
+do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
+ tmp |= (DMA_ENABLE|DMA_INT_ENAB); \
+ tmp &= ~DMA_ST_WRITE; \
+ sbus_writel(tmp, (__regs) + DMA_CSR); \
+} while(0)
+
+/* For certain DMA chips, we need to disable ints upon irq entry
+ * and turn them back on when we are done. So in any ESP interrupt
+ * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
+ * when leaving the handler. You have been warned...
+ */
+#define DMA_IRQ_ENTRY(dma, dregs) do { \
+ if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
+ } while (0)
+
+#define DMA_IRQ_EXIT(dma, dregs) do { \
+ if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
+ } while(0)
+
+#define for_each_dvma(dma) \
+ for((dma) = dma_chain; (dma); (dma) = (dma)->next)
+
+/* From PCI */
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy (0)
+#endif
+
+#endif /* !(_ASM_SPARC64_DMA_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_EBUS_H
+#define ___ASM_SPARC_EBUS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/ebus_64.h>
+#else
+#include <asm/ebus_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * ebus.h: PCI to Ebus pseudo driver software state.
+ *
+ * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
+ *
+ * Adopted for sparc by V. Roganov and G. Raiko.
+ */
+
+#ifndef __SPARC_EBUS_H
+#define __SPARC_EBUS_H
+
+#ifndef _LINUX_IOPORT_H
+#include <linux/ioport.h>
+#endif
+#include <asm/oplib.h>
+#include <asm/prom.h>
+#include <asm/of_device.h>
+
+struct linux_ebus_child {
+ struct linux_ebus_child *next;
+ struct linux_ebus_device *parent;
+ struct linux_ebus *bus;
+ struct device_node *prom_node;
+ struct resource resource[PROMREG_MAX];
+ int num_addrs;
+ unsigned int irqs[PROMINTR_MAX];
+ int num_irqs;
+};
+
+struct linux_ebus_device {
+ struct of_device ofdev;
+ struct linux_ebus_device *next;
+ struct linux_ebus_child *children;
+ struct linux_ebus *bus;
+ struct device_node *prom_node;
+ struct resource resource[PROMREG_MAX];
+ int num_addrs;
+ unsigned int irqs[PROMINTR_MAX];
+ int num_irqs;
+};
+#define to_ebus_device(d) container_of(d, struct linux_ebus_device, ofdev.dev)
+
+struct linux_ebus {
+ struct of_device ofdev;
+ struct linux_ebus *next;
+ struct linux_ebus_device *devices;
+ struct linux_pbm_info *parent;
+ struct pci_dev *self;
+ struct device_node *prom_node;
+};
+#define to_ebus(d) container_of(d, struct linux_ebus, ofdev.dev)
+
+struct linux_ebus_dma {
+ unsigned int dcsr;
+ unsigned int dacr;
+ unsigned int dbcr;
+};
+
+#define EBUS_DCSR_INT_PEND 0x00000001
+#define EBUS_DCSR_ERR_PEND 0x00000002
+#define EBUS_DCSR_DRAIN 0x00000004
+#define EBUS_DCSR_INT_EN 0x00000010
+#define EBUS_DCSR_RESET 0x00000080
+#define EBUS_DCSR_WRITE 0x00000100
+#define EBUS_DCSR_EN_DMA 0x00000200
+#define EBUS_DCSR_CYC_PEND 0x00000400
+#define EBUS_DCSR_DIAG_RD_DONE 0x00000800
+#define EBUS_DCSR_DIAG_WR_DONE 0x00001000
+#define EBUS_DCSR_EN_CNT 0x00002000
+#define EBUS_DCSR_TC 0x00004000
+#define EBUS_DCSR_DIS_CSR_DRN 0x00010000
+#define EBUS_DCSR_BURST_SZ_MASK 0x000c0000
+#define EBUS_DCSR_BURST_SZ_1 0x00080000
+#define EBUS_DCSR_BURST_SZ_4 0x00000000
+#define EBUS_DCSR_BURST_SZ_8 0x00040000
+#define EBUS_DCSR_BURST_SZ_16 0x000c0000
+#define EBUS_DCSR_DIAG_EN 0x00100000
+#define EBUS_DCSR_DIS_ERR_PEND 0x00400000
+#define EBUS_DCSR_TCI_DIS 0x00800000
+#define EBUS_DCSR_EN_NEXT 0x01000000
+#define EBUS_DCSR_DMA_ON 0x02000000
+#define EBUS_DCSR_A_LOADED 0x04000000
+#define EBUS_DCSR_NA_LOADED 0x08000000
+#define EBUS_DCSR_DEV_ID_MASK 0xf0000000
+
+extern struct linux_ebus *ebus_chain;
+
+extern void ebus_init(void);
+
+#define for_each_ebus(bus) \
+ for((bus) = ebus_chain; (bus); (bus) = (bus)->next)
+
+#define for_each_ebusdev(dev, bus) \
+ for((dev) = (bus)->devices; (dev); (dev) = (dev)->next)
+
+#define for_each_edevchild(dev, child) \
+ for((child) = (dev)->children; (child); (child) = (child)->next)
+
+#endif /* !(__SPARC_EBUS_H) */
--- /dev/null
+/*
+ * ebus.h: PCI to Ebus pseudo driver software state.
+ *
+ * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
+ * Copyright (C) 1999 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef __SPARC64_EBUS_H
+#define __SPARC64_EBUS_H
+
+#include <asm/oplib.h>
+#include <asm/prom.h>
+#include <asm/of_device.h>
+
+struct linux_ebus_child {
+ struct linux_ebus_child *next;
+ struct linux_ebus_device *parent;
+ struct linux_ebus *bus;
+ struct device_node *prom_node;
+ struct resource resource[PROMREG_MAX];
+ int num_addrs;
+ unsigned int irqs[PROMINTR_MAX];
+ int num_irqs;
+};
+
+struct linux_ebus_device {
+ struct of_device ofdev;
+ struct linux_ebus_device *next;
+ struct linux_ebus_child *children;
+ struct linux_ebus *bus;
+ struct device_node *prom_node;
+ struct resource resource[PROMREG_MAX];
+ int num_addrs;
+ unsigned int irqs[PROMINTR_MAX];
+ int num_irqs;
+};
+#define to_ebus_device(d) container_of(d, struct linux_ebus_device, ofdev.dev)
+
+struct linux_ebus {
+ struct of_device ofdev;
+ struct linux_ebus *next;
+ struct linux_ebus_device *devices;
+ struct pci_dev *self;
+ int index;
+ int is_rio;
+ struct device_node *prom_node;
+};
+#define to_ebus(d) container_of(d, struct linux_ebus, ofdev.dev)
+
+struct ebus_dma_info {
+ spinlock_t lock;
+ void __iomem *regs;
+
+ unsigned int flags;
+#define EBUS_DMA_FLAG_USE_EBDMA_HANDLER 0x00000001
+#define EBUS_DMA_FLAG_TCI_DISABLE 0x00000002
+
+ /* These are only valid is EBUS_DMA_FLAG_USE_EBDMA_HANDLER is
+ * set.
+ */
+ void (*callback)(struct ebus_dma_info *p, int event, void *cookie);
+ void *client_cookie;
+ unsigned int irq;
+#define EBUS_DMA_EVENT_ERROR 1
+#define EBUS_DMA_EVENT_DMA 2
+#define EBUS_DMA_EVENT_DEVICE 4
+
+ unsigned char name[64];
+};
+
+extern int ebus_dma_register(struct ebus_dma_info *p);
+extern int ebus_dma_irq_enable(struct ebus_dma_info *p, int on);
+extern void ebus_dma_unregister(struct ebus_dma_info *p);
+extern int ebus_dma_request(struct ebus_dma_info *p, dma_addr_t bus_addr,
+ size_t len);
+extern void ebus_dma_prepare(struct ebus_dma_info *p, int write);
+extern unsigned int ebus_dma_residue(struct ebus_dma_info *p);
+extern unsigned int ebus_dma_addr(struct ebus_dma_info *p);
+extern void ebus_dma_enable(struct ebus_dma_info *p, int on);
+
+extern struct linux_ebus *ebus_chain;
+
+extern void ebus_init(void);
+
+#define for_each_ebus(bus) \
+ for((bus) = ebus_chain; (bus); (bus) = (bus)->next)
+
+#define for_each_ebusdev(dev, bus) \
+ for((dev) = (bus)->devices; (dev); (dev) = (dev)->next)
+
+#define for_each_edevchild(dev, child) \
+ for((child) = (dev)->children; (child); (child) = (child)->next)
+
+#endif /* !(__SPARC64_EBUS_H) */
--- /dev/null
+/*
+ * ecc.h: Definitions and defines for the external cache/memory
+ * controller on the sun4m.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_ECC_H
+#define _SPARC_ECC_H
+
+/* These registers are accessed through the SRMMU passthrough ASI 0x20 */
+#define ECC_ENABLE 0x00000000 /* ECC enable register */
+#define ECC_FSTATUS 0x00000008 /* ECC fault status register */
+#define ECC_FADDR 0x00000010 /* ECC fault address register */
+#define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */
+#define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */
+#define ECC_DMESG 0x00001000 /* Diagnostic message passing area */
+
+/* ECC MBus Arbiter Enable register:
+ *
+ * ----------------------------------------
+ * | |SBUS|MOD3|MOD2|MOD1|RSV|
+ * ----------------------------------------
+ * 31 5 4 3 2 1 0
+ *
+ * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on
+ * MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on
+ * MOD2: Enable MBus Arbiter on MBus module 2 0=off 1=on
+ * MOD1: Enable MBus Arbiter on MBus module 1 0=off 1=on
+ */
+
+#define ECC_MBAE_SBUS 0x00000010
+#define ECC_MBAE_MOD3 0x00000008
+#define ECC_MBAE_MOD2 0x00000004
+#define ECC_MBAE_MOD1 0x00000002
+
+/* ECC Fault Control Register layout:
+ *
+ * -----------------------------
+ * | RESV | ECHECK | EINT |
+ * -----------------------------
+ * 31 2 1 0
+ *
+ * ECHECK: Enable ECC checking. 0=off 1=on
+ * EINT: Enable Interrupts for correctable errors. 0=off 1=on
+ */
+#define ECC_FCR_CHECK 0x00000002
+#define ECC_FCR_INTENAB 0x00000001
+
+/* ECC Fault Address Register Zero layout:
+ *
+ * -----------------------------------------------------
+ * | MID | S | RSV | VA | BM |AT| C| SZ |TYP| PADDR |
+ * -----------------------------------------------------
+ * 31-28 27 26-22 21-14 13 12 11 10-8 7-4 3-0
+ *
+ * MID: ModuleID of the faulting processor. ie. who did it?
+ * S: Supervisor/Privileged access? 0=no 1=yes
+ * VA: Bits 19-12 of the virtual faulting address, these are the
+ * superset bits in the virtual cache and can be used for
+ * a flush operation if necessary.
+ * BM: Boot mode? 0=no 1=yes This is just like the SRMMU boot
+ * mode bit.
+ * AT: Did this fault happen during an atomic instruction? 0=no
+ * 1=yes. This means either an 'ldstub' or 'swap' instruction
+ * was in progress (but not finished) when this fault happened.
+ * This indicated whether the bus was locked when the fault
+ * occurred.
+ * C: Did the pte for this access indicate that it was cacheable?
+ * 0=no 1=yes
+ * SZ: The size of the transaction.
+ * TYP: The transaction type.
+ * PADDR: Bits 35-32 of the physical address for the fault.
+ */
+#define ECC_FADDR0_MIDMASK 0xf0000000
+#define ECC_FADDR0_S 0x08000000
+#define ECC_FADDR0_VADDR 0x003fc000
+#define ECC_FADDR0_BMODE 0x00002000
+#define ECC_FADDR0_ATOMIC 0x00001000
+#define ECC_FADDR0_CACHE 0x00000800
+#define ECC_FADDR0_SIZE 0x00000700
+#define ECC_FADDR0_TYPE 0x000000f0
+#define ECC_FADDR0_PADDR 0x0000000f
+
+/* ECC Fault Address Register One layout:
+ *
+ * -------------------------------------
+ * | Physical Address 31-0 |
+ * -------------------------------------
+ * 31 0
+ *
+ * You get the upper 4 bits of the physical address from the
+ * PADDR field in ECC Fault Address Zero register.
+ */
+
+/* ECC Fault Status Register layout:
+ *
+ * ----------------------------------------------
+ * | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C|
+ * ----------------------------------------------
+ * 31-18 17 16 15-8 7-4 3 2 1 0
+ *
+ * C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only)
+ * MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes)
+ * SYNDROME: Controller is mentally unstable.
+ * DWORD:
+ * UNC: Uncorrectable error. 0=no 1=yes
+ * TIMEO: Timeout occurred. 0=no 1=yes
+ * BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only)
+ * C: Correctable error? 0=no 1=yes
+ */
+
+#define ECC_FSR_C2ERR 0x00020000
+#define ECC_FSR_MULT 0x00010000
+#define ECC_FSR_SYND 0x0000ff00
+#define ECC_FSR_DWORD 0x000000f0
+#define ECC_FSR_UNC 0x00000008
+#define ECC_FSR_TIMEO 0x00000004
+#define ECC_FSR_BADSLOT 0x00000002
+#define ECC_FSR_C 0x00000001
+
+#endif /* !(_SPARC_ECC_H) */
--- /dev/null
+/*
+ * eeprom.h: Definitions for the Sun eeprom.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+/* The EEPROM and the Mostek Mk48t02 use the same IO address space
+ * for their registers/data areas. The IDPROM lives here too.
+ */
--- /dev/null
+#ifndef ___ASM_SPARC_ELF_H
+#define ___ASM_SPARC_ELF_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/elf_64.h>
+#else
+#include <asm/elf_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef __ASMSPARC_ELF_H
+#define __ASMSPARC_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+
+#include <asm/ptrace.h>
+
+/*
+ * Sparc section types
+ */
+#define STT_REGISTER 13
+
+/*
+ * Sparc ELF relocation types
+ */
+#define R_SPARC_NONE 0
+#define R_SPARC_8 1
+#define R_SPARC_16 2
+#define R_SPARC_32 3
+#define R_SPARC_DISP8 4
+#define R_SPARC_DISP16 5
+#define R_SPARC_DISP32 6
+#define R_SPARC_WDISP30 7
+#define R_SPARC_WDISP22 8
+#define R_SPARC_HI22 9
+#define R_SPARC_22 10
+#define R_SPARC_13 11
+#define R_SPARC_LO10 12
+#define R_SPARC_GOT10 13
+#define R_SPARC_GOT13 14
+#define R_SPARC_GOT22 15
+#define R_SPARC_PC10 16
+#define R_SPARC_PC22 17
+#define R_SPARC_WPLT30 18
+#define R_SPARC_COPY 19
+#define R_SPARC_GLOB_DAT 20
+#define R_SPARC_JMP_SLOT 21
+#define R_SPARC_RELATIVE 22
+#define R_SPARC_UA32 23
+#define R_SPARC_PLT32 24
+#define R_SPARC_HIPLT22 25
+#define R_SPARC_LOPLT10 26
+#define R_SPARC_PCPLT32 27
+#define R_SPARC_PCPLT22 28
+#define R_SPARC_PCPLT10 29
+#define R_SPARC_10 30
+#define R_SPARC_11 31
+#define R_SPARC_64 32
+#define R_SPARC_OLO10 33
+#define R_SPARC_WDISP16 40
+#define R_SPARC_WDISP19 41
+#define R_SPARC_7 43
+#define R_SPARC_5 44
+#define R_SPARC_6 45
+
+/* Bits present in AT_HWCAP, primarily for Sparc32. */
+
+#define HWCAP_SPARC_FLUSH 1 /* CPU supports flush instruction. */
+#define HWCAP_SPARC_STBAR 2
+#define HWCAP_SPARC_SWAP 4
+#define HWCAP_SPARC_MULDIV 8
+#define HWCAP_SPARC_V9 16
+#define HWCAP_SPARC_ULTRA3 32
+
+#define CORE_DUMP_USE_REGSET
+
+/* Format is:
+ * G0 --> G7
+ * O0 --> O7
+ * L0 --> L7
+ * I0 --> I7
+ * PSR, PC, nPC, Y, WIM, TBR
+ */
+typedef unsigned long elf_greg_t;
+#define ELF_NGREG 38
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct {
+ union {
+ unsigned long pr_regs[32];
+ double pr_dregs[16];
+ } pr_fr;
+ unsigned long __unused;
+ unsigned long pr_fsr;
+ unsigned char pr_qcnt;
+ unsigned char pr_q_entrysize;
+ unsigned char pr_en;
+ unsigned int pr_q[64];
+} elf_fpregset_t;
+
+#include <asm/mbus.h>
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ((x)->e_machine == EM_SPARC)
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_ARCH EM_SPARC
+#define ELF_CLASS ELFCLASS32
+#define ELF_DATA ELFDATA2MSB
+
+#define USE_ELF_CORE_DUMP
+#ifndef CONFIG_SUN4
+#define ELF_EXEC_PAGESIZE 4096
+#else
+#define ELF_EXEC_PAGESIZE 8192
+#endif
+
+
+/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
+ use of this is to invoke "./ld.so someprog" to test out a new version of
+ the loader. We need to make sure that it is out of the way of the program
+ that it will "exec", and that there is sufficient room for the brk. */
+
+#define ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE)
+
+/* This yields a mask that user programs can use to figure out what
+ instruction set this cpu supports. This can NOT be done in userspace
+ on Sparc. */
+
+/* Sun4c has none of the capabilities, most sun4m's have them all.
+ * XXX This is gross, set some global variable at boot time. -DaveM
+ */
+#define ELF_HWCAP ((ARCH_SUN4C_SUN4) ? 0 : \
+ (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \
+ HWCAP_SPARC_SWAP | \
+ ((srmmu_modtype != Cypress && \
+ srmmu_modtype != Cypress_vE && \
+ srmmu_modtype != Cypress_vD) ? \
+ HWCAP_SPARC_MULDIV : 0)))
+
+/* This yields a string that ld.so will use to load implementation
+ specific libraries for optimization. This is more specific in
+ intent than poking at uname or /proc/cpuinfo. */
+
+#define ELF_PLATFORM (NULL)
+
+#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+
+#endif /* !(__ASMSPARC_ELF_H) */
--- /dev/null
+#ifndef __ASM_SPARC64_ELF_H
+#define __ASM_SPARC64_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+
+#include <asm/ptrace.h>
+#include <asm/processor.h>
+#include <asm/uaccess.h>
+#include <asm/spitfire.h>
+
+/*
+ * Sparc section types
+ */
+#define STT_REGISTER 13
+
+/*
+ * Sparc ELF relocation types
+ */
+#define R_SPARC_NONE 0
+#define R_SPARC_8 1
+#define R_SPARC_16 2
+#define R_SPARC_32 3
+#define R_SPARC_DISP8 4
+#define R_SPARC_DISP16 5
+#define R_SPARC_DISP32 6
+#define R_SPARC_WDISP30 7
+#define R_SPARC_WDISP22 8
+#define R_SPARC_HI22 9
+#define R_SPARC_22 10
+#define R_SPARC_13 11
+#define R_SPARC_LO10 12
+#define R_SPARC_GOT10 13
+#define R_SPARC_GOT13 14
+#define R_SPARC_GOT22 15
+#define R_SPARC_PC10 16
+#define R_SPARC_PC22 17
+#define R_SPARC_WPLT30 18
+#define R_SPARC_COPY 19
+#define R_SPARC_GLOB_DAT 20
+#define R_SPARC_JMP_SLOT 21
+#define R_SPARC_RELATIVE 22
+#define R_SPARC_UA32 23
+#define R_SPARC_PLT32 24
+#define R_SPARC_HIPLT22 25
+#define R_SPARC_LOPLT10 26
+#define R_SPARC_PCPLT32 27
+#define R_SPARC_PCPLT22 28
+#define R_SPARC_PCPLT10 29
+#define R_SPARC_10 30
+#define R_SPARC_11 31
+#define R_SPARC_64 32
+#define R_SPARC_OLO10 33
+#define R_SPARC_WDISP16 40
+#define R_SPARC_WDISP19 41
+#define R_SPARC_7 43
+#define R_SPARC_5 44
+#define R_SPARC_6 45
+
+/* Bits present in AT_HWCAP, primarily for Sparc32. */
+
+#define HWCAP_SPARC_FLUSH 1 /* CPU supports flush instruction. */
+#define HWCAP_SPARC_STBAR 2
+#define HWCAP_SPARC_SWAP 4
+#define HWCAP_SPARC_MULDIV 8
+#define HWCAP_SPARC_V9 16
+#define HWCAP_SPARC_ULTRA3 32
+#define HWCAP_SPARC_BLKINIT 64
+#define HWCAP_SPARC_N2 128
+
+#define CORE_DUMP_USE_REGSET
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_ARCH EM_SPARCV9
+#define ELF_CLASS ELFCLASS64
+#define ELF_DATA ELFDATA2MSB
+
+/* Format of 64-bit elf_gregset_t is:
+ * G0 --> G7
+ * O0 --> O7
+ * L0 --> L7
+ * I0 --> I7
+ * TSTATE
+ * TPC
+ * TNPC
+ * Y
+ */
+typedef unsigned long elf_greg_t;
+#define ELF_NGREG 36
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct {
+ unsigned long pr_regs[32];
+ unsigned long pr_fsr;
+ unsigned long pr_gsr;
+ unsigned long pr_fprs;
+} elf_fpregset_t;
+
+/* Format of 32-bit elf_gregset_t is:
+ * G0 --> G7
+ * O0 --> O7
+ * L0 --> L7
+ * I0 --> I7
+ * PSR, PC, nPC, Y, WIM, TBR
+ */
+typedef unsigned int compat_elf_greg_t;
+#define COMPAT_ELF_NGREG 38
+typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG];
+
+typedef struct {
+ union {
+ unsigned int pr_regs[32];
+ unsigned long pr_dregs[16];
+ } pr_fr;
+ unsigned int __unused;
+ unsigned int pr_fsr;
+ unsigned char pr_qcnt;
+ unsigned char pr_q_entrysize;
+ unsigned char pr_en;
+ unsigned int pr_q[64];
+} compat_elf_fpregset_t;
+
+/* UltraSparc extensions. Still unused, but will be eventually. */
+typedef struct {
+ unsigned int pr_type;
+ unsigned int pr_align;
+ union {
+ struct {
+ union {
+ unsigned int pr_regs[32];
+ unsigned long pr_dregs[16];
+ long double pr_qregs[8];
+ } pr_xfr;
+ } pr_v8p;
+ unsigned int pr_xfsr;
+ unsigned int pr_fprs;
+ unsigned int pr_xg[8];
+ unsigned int pr_xo[8];
+ unsigned long pr_tstate;
+ unsigned int pr_filler[8];
+ } pr_un;
+} elf_xregset_t;
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
+#define compat_elf_check_arch(x) ((x)->e_machine == EM_SPARC || \
+ (x)->e_machine == EM_SPARC32PLUS)
+#define compat_start_thread start_thread32
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE PAGE_SIZE
+
+/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
+ use of this is to invoke "./ld.so someprog" to test out a new version of
+ the loader. We need to make sure that it is out of the way of the program
+ that it will "exec", and that there is sufficient room for the brk. */
+
+#define ELF_ET_DYN_BASE 0x0000010000000000UL
+#define COMPAT_ELF_ET_DYN_BASE 0x0000000070000000UL
+
+
+/* This yields a mask that user programs can use to figure out what
+ instruction set this cpu supports. */
+
+/* On Ultra, we support all of the v8 capabilities. */
+static inline unsigned int sparc64_elf_hwcap(void)
+{
+ unsigned int cap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
+ HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
+ HWCAP_SPARC_V9);
+
+ if (tlb_type == cheetah || tlb_type == cheetah_plus)
+ cap |= HWCAP_SPARC_ULTRA3;
+ else if (tlb_type == hypervisor) {
+ if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
+ sun4v_chip_type == SUN4V_CHIP_NIAGARA2)
+ cap |= HWCAP_SPARC_BLKINIT;
+ if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2)
+ cap |= HWCAP_SPARC_N2;
+ }
+
+ return cap;
+}
+
+#define ELF_HWCAP sparc64_elf_hwcap();
+
+/* This yields a string that ld.so will use to load implementation
+ specific libraries for optimization. This is more specific in
+ intent than poking at uname or /proc/cpuinfo. */
+
+#define ELF_PLATFORM (NULL)
+
+#define SET_PERSONALITY(ex, ibcs2) \
+do { unsigned long new_flags = current_thread_info()->flags; \
+ new_flags &= _TIF_32BIT; \
+ if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
+ new_flags |= _TIF_32BIT; \
+ else \
+ new_flags &= ~_TIF_32BIT; \
+ if ((current_thread_info()->flags & _TIF_32BIT) \
+ != new_flags) \
+ set_thread_flag(TIF_ABI_PENDING); \
+ else \
+ clear_thread_flag(TIF_ABI_PENDING); \
+ /* flush_thread will update pgd cache */ \
+ if (ibcs2) \
+ set_personality(PER_SVR4); \
+ else if (current->personality != PER_LINUX32) \
+ set_personality(PER_LINUX); \
+} while (0)
+
+#endif /* !(__ASM_SPARC64_ELF_H) */
--- /dev/null
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
--- /dev/null
+/*
+ *
+ * envctrl.h: Definitions for access to the i2c environment
+ * monitoring on Ultrasparc systems.
+ *
+ * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
+ * Copyright (C) 2000 Vinh Truong (vinh.truong@eng.sun.com)
+ * VT - Add all ioctl commands and environment status definitions
+ * VT - Add application note
+ */
+#ifndef _SPARC64_ENVCTRL_H
+#define _SPARC64_ENVCTRL_H 1
+
+#include <linux/ioctl.h>
+
+/* Application note:
+ *
+ * The driver supports 4 operations: open(), close(), ioctl(), read()
+ * The device name is /dev/envctrl.
+ * Below is sample usage:
+ *
+ * fd = open("/dev/envtrl", O_RDONLY);
+ * if (ioctl(fd, ENVCTRL_READ_SHUTDOWN_TEMPERATURE, 0) < 0)
+ * printf("error\n");
+ * ret = read(fd, buf, 10);
+ * close(fd);
+ *
+ * Notice in the case of cpu voltage and temperature, the default is
+ * cpu0. If we need to know the info of cpu1, cpu2, cpu3, we need to
+ * pass in cpu number in ioctl() last parameter. For example, to
+ * get the voltage of cpu2:
+ *
+ * ioctlbuf[0] = 2;
+ * if (ioctl(fd, ENVCTRL_READ_CPU_VOLTAGE, ioctlbuf) < 0)
+ * printf("error\n");
+ * ret = read(fd, buf, 10);
+ *
+ * All the return values are in ascii. So check read return value
+ * and do appropriate conversions in your application.
+ */
+
+/* IOCTL commands */
+
+/* Note: these commands reflect possible monitor features.
+ * Some boards choose to support some of the features only.
+ */
+#define ENVCTRL_RD_CPU_TEMPERATURE _IOR('p', 0x40, int)
+#define ENVCTRL_RD_CPU_VOLTAGE _IOR('p', 0x41, int)
+#define ENVCTRL_RD_FAN_STATUS _IOR('p', 0x42, int)
+#define ENVCTRL_RD_WARNING_TEMPERATURE _IOR('p', 0x43, int)
+#define ENVCTRL_RD_SHUTDOWN_TEMPERATURE _IOR('p', 0x44, int)
+#define ENVCTRL_RD_VOLTAGE_STATUS _IOR('p', 0x45, int)
+#define ENVCTRL_RD_SCSI_TEMPERATURE _IOR('p', 0x46, int)
+#define ENVCTRL_RD_ETHERNET_TEMPERATURE _IOR('p', 0x47, int)
+#define ENVCTRL_RD_MTHRBD_TEMPERATURE _IOR('p', 0x48, int)
+
+#define ENVCTRL_RD_GLOBALADDRESS _IOR('p', 0x49, int)
+
+/* Read return values for a voltage status request. */
+#define ENVCTRL_VOLTAGE_POWERSUPPLY_GOOD 0x01
+#define ENVCTRL_VOLTAGE_BAD 0x02
+#define ENVCTRL_POWERSUPPLY_BAD 0x03
+#define ENVCTRL_VOLTAGE_POWERSUPPLY_BAD 0x04
+
+/* Read return values for a fan status request.
+ * A failure match means either the fan fails or
+ * the fan is not connected. Some boards have optional
+ * connectors to connect extra fans.
+ *
+ * There are maximum 8 monitor fans. Some are cpu fans
+ * some are system fans. The mask below only indicates
+ * fan by order number.
+ * Below is a sample application:
+ *
+ * if (ioctl(fd, ENVCTRL_READ_FAN_STATUS, 0) < 0) {
+ * printf("ioctl fan failed\n");
+ * }
+ * if (read(fd, rslt, 1) <= 0) {
+ * printf("error or fan not monitored\n");
+ * } else {
+ * if (rslt[0] == ENVCTRL_ALL_FANS_GOOD) {
+ * printf("all fans good\n");
+ * } else if (rslt[0] == ENVCTRL_ALL_FANS_BAD) {
+ * printf("all fans bad\n");
+ * } else {
+ * if (rslt[0] & ENVCTRL_FAN0_FAILURE_MASK) {
+ * printf("fan 0 failed or not connected\n");
+ * }
+ * ......
+ */
+
+#define ENVCTRL_ALL_FANS_GOOD 0x00
+#define ENVCTRL_FAN0_FAILURE_MASK 0x01
+#define ENVCTRL_FAN1_FAILURE_MASK 0x02
+#define ENVCTRL_FAN2_FAILURE_MASK 0x04
+#define ENVCTRL_FAN3_FAILURE_MASK 0x08
+#define ENVCTRL_FAN4_FAILURE_MASK 0x10
+#define ENVCTRL_FAN5_FAILURE_MASK 0x20
+#define ENVCTRL_FAN6_FAILURE_MASK 0x40
+#define ENVCTRL_FAN7_FAILURE_MASK 0x80
+#define ENVCTRL_ALL_FANS_BAD 0xFF
+
+#endif /* !(_SPARC64_ENVCTRL_H) */
--- /dev/null
+#ifndef _SPARC_ERRNO_H
+#define _SPARC_ERRNO_H
+
+/* These match the SunOS error numbering scheme. */
+
+#include <asm-generic/errno-base.h>
+
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define EINPROGRESS 36 /* Operation now in progress */
+#define EALREADY 37 /* Operation already in progress */
+#define ENOTSOCK 38 /* Socket operation on non-socket */
+#define EDESTADDRREQ 39 /* Destination address required */
+#define EMSGSIZE 40 /* Message too long */
+#define EPROTOTYPE 41 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 42 /* Protocol not available */
+#define EPROTONOSUPPORT 43 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 44 /* Socket type not supported */
+#define EOPNOTSUPP 45 /* Op not supported on transport endpoint */
+#define EPFNOSUPPORT 46 /* Protocol family not supported */
+#define EAFNOSUPPORT 47 /* Address family not supported by protocol */
+#define EADDRINUSE 48 /* Address already in use */
+#define EADDRNOTAVAIL 49 /* Cannot assign requested address */
+#define ENETDOWN 50 /* Network is down */
+#define ENETUNREACH 51 /* Network is unreachable */
+#define ENETRESET 52 /* Net dropped connection because of reset */
+#define ECONNABORTED 53 /* Software caused connection abort */
+#define ECONNRESET 54 /* Connection reset by peer */
+#define ENOBUFS 55 /* No buffer space available */
+#define EISCONN 56 /* Transport endpoint is already connected */
+#define ENOTCONN 57 /* Transport endpoint is not connected */
+#define ESHUTDOWN 58 /* No send after transport endpoint shutdown */
+#define ETOOMANYREFS 59 /* Too many references: cannot splice */
+#define ETIMEDOUT 60 /* Connection timed out */
+#define ECONNREFUSED 61 /* Connection refused */
+#define ELOOP 62 /* Too many symbolic links encountered */
+#define ENAMETOOLONG 63 /* File name too long */
+#define EHOSTDOWN 64 /* Host is down */
+#define EHOSTUNREACH 65 /* No route to host */
+#define ENOTEMPTY 66 /* Directory not empty */
+#define EPROCLIM 67 /* SUNOS: Too many processes */
+#define EUSERS 68 /* Too many users */
+#define EDQUOT 69 /* Quota exceeded */
+#define ESTALE 70 /* Stale NFS file handle */
+#define EREMOTE 71 /* Object is remote */
+#define ENOSTR 72 /* Device not a stream */
+#define ETIME 73 /* Timer expired */
+#define ENOSR 74 /* Out of streams resources */
+#define ENOMSG 75 /* No message of desired type */
+#define EBADMSG 76 /* Not a data message */
+#define EIDRM 77 /* Identifier removed */
+#define EDEADLK 78 /* Resource deadlock would occur */
+#define ENOLCK 79 /* No record locks available */
+#define ENONET 80 /* Machine is not on the network */
+#define ERREMOTE 81 /* SunOS: Too many lvls of remote in path */
+#define ENOLINK 82 /* Link has been severed */
+#define EADV 83 /* Advertise error */
+#define ESRMNT 84 /* Srmount error */
+#define ECOMM 85 /* Communication error on send */
+#define EPROTO 86 /* Protocol error */
+#define EMULTIHOP 87 /* Multihop attempted */
+#define EDOTDOT 88 /* RFS specific error */
+#define EREMCHG 89 /* Remote address changed */
+#define ENOSYS 90 /* Function not implemented */
+
+/* The rest have no SunOS equivalent. */
+#define ESTRPIPE 91 /* Streams pipe error */
+#define EOVERFLOW 92 /* Value too large for defined data type */
+#define EBADFD 93 /* File descriptor in bad state */
+#define ECHRNG 94 /* Channel number out of range */
+#define EL2NSYNC 95 /* Level 2 not synchronized */
+#define EL3HLT 96 /* Level 3 halted */
+#define EL3RST 97 /* Level 3 reset */
+#define ELNRNG 98 /* Link number out of range */
+#define EUNATCH 99 /* Protocol driver not attached */
+#define ENOCSI 100 /* No CSI structure available */
+#define EL2HLT 101 /* Level 2 halted */
+#define EBADE 102 /* Invalid exchange */
+#define EBADR 103 /* Invalid request descriptor */
+#define EXFULL 104 /* Exchange full */
+#define ENOANO 105 /* No anode */
+#define EBADRQC 106 /* Invalid request code */
+#define EBADSLT 107 /* Invalid slot */
+#define EDEADLOCK 108 /* File locking deadlock error */
+#define EBFONT 109 /* Bad font file format */
+#define ELIBEXEC 110 /* Cannot exec a shared library directly */
+#define ENODATA 111 /* No data available */
+#define ELIBBAD 112 /* Accessing a corrupted shared library */
+#define ENOPKG 113 /* Package not installed */
+#define ELIBACC 114 /* Can not access a needed shared library */
+#define ENOTUNIQ 115 /* Name not unique on network */
+#define ERESTART 116 /* Interrupted syscall should be restarted */
+#define EUCLEAN 117 /* Structure needs cleaning */
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#define EISNAM 120 /* Is a named type file */
+#define EREMOTEIO 121 /* Remote I/O error */
+#define EILSEQ 122 /* Illegal byte sequence */
+#define ELIBMAX 123 /* Atmpt to link in too many shared libs */
+#define ELIBSCN 124 /* .lib section in a.out corrupted */
+
+#define ENOMEDIUM 125 /* No medium found */
+#define EMEDIUMTYPE 126 /* Wrong medium type */
+#define ECANCELED 127 /* Operation Cancelled */
+#define ENOKEY 128 /* Required key not available */
+#define EKEYEXPIRED 129 /* Key has expired */
+#define EKEYREVOKED 130 /* Key has been revoked */
+#define EKEYREJECTED 131 /* Key was rejected by service */
+
+/* for robust mutexes */
+#define EOWNERDEAD 132 /* Owner died */
+#define ENOTRECOVERABLE 133 /* State not recoverable */
+
+#endif
--- /dev/null
+#ifndef _SPARC64_ESTATE_H
+#define _SPARC64_ESTATE_H
+
+/* UltraSPARC-III E-cache Error Enable */
+#define ESTATE_ERROR_FMT 0x0000000000040000 /* Force MTAG ECC */
+#define ESTATE_ERROR_FMESS 0x000000000003c000 /* Forced MTAG ECC val */
+#define ESTATE_ERROR_FMD 0x0000000000002000 /* Force DATA ECC */
+#define ESTATE_ERROR_FDECC 0x0000000000001ff0 /* Forced DATA ECC val */
+#define ESTATE_ERROR_UCEEN 0x0000000000000008 /* See below */
+#define ESTATE_ERROR_NCEEN 0x0000000000000002 /* See below */
+#define ESTATE_ERROR_CEEN 0x0000000000000001 /* See below */
+
+/* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache
+ * errors 2) uncorrectable E-cache errors. Such events only occur on reads
+ * of the E-cache by the local processor for: 1) data loads 2) instruction
+ * fetches 3) atomic operations. Such events _cannot_ occur for: 1) merge
+ * 2) writeback 2) copyout. The AFSR bits associated with these traps are
+ * UCC and UCU.
+ */
+
+/* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps
+ * for uncorrectable ECC errors and system errors.
+ *
+ * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT,
+ * or system bus BusERR:
+ * 1) As the result of an instruction fetch, will generate instruction_access_error
+ * 2) As the result of a load etc. will generate data_access_error.
+ * 3) As the result of store merge completion, writeback, or copyout will
+ * generate a disrupting ECC_error trap.
+ * 4) As the result of such errors on instruction vector fetch can generate any
+ * of the 3 trap types.
+ *
+ * The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE,
+ * BERR, and TO.
+ */
+
+/* CEEN enables the ECC_error trap for hardware corrected ECC errors. System bus
+ * reads resulting in a hardware corrected data or MTAG ECC error will generate an
+ * ECC_error disrupting trap with this bit enabled.
+ *
+ * This same trap will also be generated when a hardware corrected ECC error results
+ * during store merge, writeback, and copyout operations.
+ */
+
+/* In general, if the trap enable bits above are disabled the AFSR bits will still
+ * log the events even though the trap will not be generated by the processor.
+ */
+
+#endif /* _SPARC64_ESTATE_H */
--- /dev/null
+#ifndef _SPARC_FB_H_
+#define _SPARC_FB_H_
+#include <linux/fb.h>
+#include <linux/fs.h>
+#include <asm/page.h>
+#include <asm/prom.h>
+
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+ unsigned long off)
+{
+#ifdef CONFIG_SPARC64
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+#endif
+}
+
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+ struct device *dev = info->device;
+ struct device_node *node;
+
+ node = dev->archdata.prom_node;
+ if (node &&
+ node == of_console_device)
+ return 1;
+
+ return 0;
+}
+
+#endif /* _SPARC_FB_H_ */
--- /dev/null
+#ifndef __LINUX_FBIO_H
+#define __LINUX_FBIO_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+/* Constants used for fbio SunOS compatibility */
+/* (C) 1996 Miguel de Icaza */
+
+/* Frame buffer types */
+#define FBTYPE_NOTYPE -1
+#define FBTYPE_SUN1BW 0 /* mono */
+#define FBTYPE_SUN1COLOR 1
+#define FBTYPE_SUN2BW 2
+#define FBTYPE_SUN2COLOR 3
+#define FBTYPE_SUN2GP 4
+#define FBTYPE_SUN5COLOR 5
+#define FBTYPE_SUN3COLOR 6
+#define FBTYPE_MEMCOLOR 7
+#define FBTYPE_SUN4COLOR 8
+
+#define FBTYPE_NOTSUN1 9
+#define FBTYPE_NOTSUN2 10
+#define FBTYPE_NOTSUN3 11
+
+#define FBTYPE_SUNFAST_COLOR 12 /* cg6 */
+#define FBTYPE_SUNROP_COLOR 13
+#define FBTYPE_SUNFB_VIDEO 14
+#define FBTYPE_SUNGIFB 15
+#define FBTYPE_SUNGPLAS 16
+#define FBTYPE_SUNGP3 17
+#define FBTYPE_SUNGT 18
+#define FBTYPE_SUNLEO 19 /* zx Leo card */
+#define FBTYPE_MDICOLOR 20 /* cg14 */
+#define FBTYPE_TCXCOLOR 21 /* SUNW,tcx card */
+
+#define FBTYPE_LASTPLUSONE 21 /* This is not last + 1 in fact... */
+
+/* Does not seem to be listed in the Sun file either */
+#define FBTYPE_CREATOR 22
+#define FBTYPE_PCI_IGA1682 23
+#define FBTYPE_P9100COLOR 24
+
+#define FBTYPE_PCI_GENERIC 1000
+#define FBTYPE_PCI_MACH64 1001
+
+/* fbio ioctls */
+/* Returned by FBIOGTYPE */
+struct fbtype {
+ int fb_type; /* fb type, see above */
+ int fb_height; /* pixels */
+ int fb_width; /* pixels */
+ int fb_depth;
+ int fb_cmsize; /* color map entries */
+ int fb_size; /* fb size in bytes */
+};
+#define FBIOGTYPE _IOR('F', 0, struct fbtype)
+
+struct fbcmap {
+ int index; /* first element (0 origin) */
+ int count;
+ unsigned char __user *red;
+ unsigned char __user *green;
+ unsigned char __user *blue;
+};
+
+#ifdef __KERNEL__
+#define FBIOPUTCMAP_SPARC _IOW('F', 3, struct fbcmap)
+#define FBIOGETCMAP_SPARC _IOW('F', 4, struct fbcmap)
+#else
+#define FBIOPUTCMAP _IOW('F', 3, struct fbcmap)
+#define FBIOGETCMAP _IOW('F', 4, struct fbcmap)
+#endif
+
+/* # of device specific values */
+#define FB_ATTR_NDEVSPECIFIC 8
+/* # of possible emulations */
+#define FB_ATTR_NEMUTYPES 4
+
+struct fbsattr {
+ int flags;
+ int emu_type; /* -1 if none */
+ int dev_specific[FB_ATTR_NDEVSPECIFIC];
+};
+
+struct fbgattr {
+ int real_type; /* real frame buffer type */
+ int owner; /* unknown */
+ struct fbtype fbtype; /* real frame buffer fbtype */
+ struct fbsattr sattr;
+ int emu_types[FB_ATTR_NEMUTYPES]; /* supported emulations */
+};
+#define FBIOSATTR _IOW('F', 5, struct fbgattr) /* Unsupported: */
+#define FBIOGATTR _IOR('F', 6, struct fbgattr) /* supported */
+
+#define FBIOSVIDEO _IOW('F', 7, int)
+#define FBIOGVIDEO _IOR('F', 8, int)
+
+struct fbcursor {
+ short set; /* what to set, choose from the list above */
+ short enable; /* cursor on/off */
+ struct fbcurpos pos; /* cursor position */
+ struct fbcurpos hot; /* cursor hot spot */
+ struct fbcmap cmap; /* color map info */
+ struct fbcurpos size; /* cursor bit map size */
+ char __user *image; /* cursor image bits */
+ char __user *mask; /* cursor mask bits */
+};
+
+/* set/get cursor attributes/shape */
+#define FBIOSCURSOR _IOW('F', 24, struct fbcursor)
+#define FBIOGCURSOR _IOWR('F', 25, struct fbcursor)
+
+/* set/get cursor position */
+#define FBIOSCURPOS _IOW('F', 26, struct fbcurpos)
+#define FBIOGCURPOS _IOW('F', 27, struct fbcurpos)
+
+/* get max cursor size */
+#define FBIOGCURMAX _IOR('F', 28, struct fbcurpos)
+
+/* wid manipulation */
+struct fb_wid_alloc {
+#define FB_WID_SHARED_8 0
+#define FB_WID_SHARED_24 1
+#define FB_WID_DBL_8 2
+#define FB_WID_DBL_24 3
+ __u32 wa_type;
+ __s32 wa_index; /* Set on return */
+ __u32 wa_count;
+};
+struct fb_wid_item {
+ __u32 wi_type;
+ __s32 wi_index;
+ __u32 wi_attrs;
+ __u32 wi_values[32];
+};
+struct fb_wid_list {
+ __u32 wl_flags;
+ __u32 wl_count;
+ struct fb_wid_item *wl_list;
+};
+
+#define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc)
+#define FBIO_WID_FREE _IOW('F', 31, struct fb_wid_alloc)
+#define FBIO_WID_PUT _IOW('F', 32, struct fb_wid_list)
+#define FBIO_WID_GET _IOWR('F', 33, struct fb_wid_list)
+
+/* Creator ioctls */
+#define FFB_IOCTL ('F'<<8)
+#define FFB_SYS_INFO (FFB_IOCTL|80)
+#define FFB_CLUTREAD (FFB_IOCTL|81)
+#define FFB_CLUTPOST (FFB_IOCTL|82)
+#define FFB_SETDIAGMODE (FFB_IOCTL|83)
+#define FFB_GETMONITORID (FFB_IOCTL|84)
+#define FFB_GETVIDEOMODE (FFB_IOCTL|85)
+#define FFB_SETVIDEOMODE (FFB_IOCTL|86)
+#define FFB_SETSERVER (FFB_IOCTL|87)
+#define FFB_SETOVCTL (FFB_IOCTL|88)
+#define FFB_GETOVCTL (FFB_IOCTL|89)
+#define FFB_GETSAXNUM (FFB_IOCTL|90)
+#define FFB_FBDEBUG (FFB_IOCTL|91)
+
+/* Cg14 ioctls */
+#define MDI_IOCTL ('M'<<8)
+#define MDI_RESET (MDI_IOCTL|1)
+#define MDI_GET_CFGINFO (MDI_IOCTL|2)
+#define MDI_SET_PIXELMODE (MDI_IOCTL|3)
+# define MDI_32_PIX 32
+# define MDI_16_PIX 16
+# define MDI_8_PIX 8
+
+struct mdi_cfginfo {
+ int mdi_ncluts; /* Number of implemented CLUTs in this MDI */
+ int mdi_type; /* FBTYPE name */
+ int mdi_height; /* height */
+ int mdi_width; /* widht */
+ int mdi_size; /* available ram */
+ int mdi_mode; /* 8bpp, 16bpp or 32bpp */
+ int mdi_pixfreq; /* pixel clock (from PROM) */
+};
+
+/* SparcLinux specific ioctl for the MDI, should be replaced for
+ * the SET_XLUT/SET_CLUTn ioctls instead
+ */
+#define MDI_CLEAR_XLUT (MDI_IOCTL|9)
+
+/* leo & ffb ioctls */
+struct fb_clut_alloc {
+ __u32 clutid; /* Set on return */
+ __u32 flag;
+ __u32 index;
+};
+
+struct fb_clut {
+#define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
+ __u32 flag;
+ __u32 clutid;
+ __u32 offset;
+ __u32 count;
+ char * red;
+ char * green;
+ char * blue;
+};
+
+struct fb_clut32 {
+ __u32 flag;
+ __u32 clutid;
+ __u32 offset;
+ __u32 count;
+ __u32 red;
+ __u32 green;
+ __u32 blue;
+};
+
+#define LEO_CLUTALLOC _IOWR('L', 53, struct fb_clut_alloc)
+#define LEO_CLUTFREE _IOW('L', 54, struct fb_clut_alloc)
+#define LEO_CLUTREAD _IOW('L', 55, struct fb_clut)
+#define LEO_CLUTPOST _IOW('L', 56, struct fb_clut)
+#define LEO_SETGAMMA _IOW('L', 68, int) /* Not yet implemented */
+#define LEO_GETGAMMA _IOR('L', 69, int) /* Not yet implemented */
+
+#ifdef __KERNEL__
+/* Addresses on the fd of a cgsix that are mappable */
+#define CG6_FBC 0x70000000
+#define CG6_TEC 0x70001000
+#define CG6_BTREGS 0x70002000
+#define CG6_FHC 0x70004000
+#define CG6_THC 0x70005000
+#define CG6_ROM 0x70006000
+#define CG6_RAM 0x70016000
+#define CG6_DHC 0x80000000
+
+#define CG3_MMAP_OFFSET 0x4000000
+
+/* Addresses on the fd of a tcx that are mappable */
+#define TCX_RAM8BIT 0x00000000
+#define TCX_RAM24BIT 0x01000000
+#define TCX_UNK3 0x10000000
+#define TCX_UNK4 0x20000000
+#define TCX_CONTROLPLANE 0x28000000
+#define TCX_UNK6 0x30000000
+#define TCX_UNK7 0x38000000
+#define TCX_TEC 0x70000000
+#define TCX_BTREGS 0x70002000
+#define TCX_THC 0x70004000
+#define TCX_DHC 0x70008000
+#define TCX_ALT 0x7000a000
+#define TCX_SYNC 0x7000e000
+#define TCX_UNK2 0x70010000
+
+/* CG14 definitions */
+
+/* Offsets into the OBIO space: */
+#define CG14_REGS 0 /* registers */
+#define CG14_CURSORREGS 0x1000 /* cursor registers */
+#define CG14_DACREGS 0x2000 /* DAC registers */
+#define CG14_XLUT 0x3000 /* X Look Up Table -- ??? */
+#define CG14_CLUT1 0x4000 /* Color Look Up Table */
+#define CG14_CLUT2 0x5000 /* Color Look Up Table */
+#define CG14_CLUT3 0x6000 /* Color Look Up Table */
+#define CG14_AUTO 0xf000
+
+#endif /* KERNEL */
+
+/* These are exported to userland for applications to use */
+/* Mappable offsets for the cg14: control registers */
+#define MDI_DIRECT_MAP 0x10000000
+#define MDI_CTLREG_MAP 0x20000000
+#define MDI_CURSOR_MAP 0x30000000
+#define MDI_SHDW_VRT_MAP 0x40000000
+
+/* Mappable offsets for the cg14: frame buffer resolutions */
+/* 32 bits */
+#define MDI_CHUNKY_XBGR_MAP 0x50000000
+#define MDI_CHUNKY_BGR_MAP 0x60000000
+
+/* 16 bits */
+#define MDI_PLANAR_X16_MAP 0x70000000
+#define MDI_PLANAR_C16_MAP 0x80000000
+
+/* 8 bit is done as CG3 MMAP offset */
+/* 32 bits, planar */
+#define MDI_PLANAR_X32_MAP 0x90000000
+#define MDI_PLANAR_B32_MAP 0xa0000000
+#define MDI_PLANAR_G32_MAP 0xb0000000
+#define MDI_PLANAR_R32_MAP 0xc0000000
+
+/* Mappable offsets on leo */
+#define LEO_SS0_MAP 0x00000000
+#define LEO_LC_SS0_USR_MAP 0x00800000
+#define LEO_LD_SS0_MAP 0x00801000
+#define LEO_LX_CURSOR_MAP 0x00802000
+#define LEO_SS1_MAP 0x00803000
+#define LEO_LC_SS1_USR_MAP 0x01003000
+#define LEO_LD_SS1_MAP 0x01004000
+#define LEO_UNK_MAP 0x01005000
+#define LEO_LX_KRN_MAP 0x01006000
+#define LEO_LC_SS0_KRN_MAP 0x01007000
+#define LEO_LC_SS1_KRN_MAP 0x01008000
+#define LEO_LD_GBL_MAP 0x01009000
+#define LEO_UNK2_MAP 0x0100a000
+
+#ifdef __KERNEL__
+struct fbcmap32 {
+ int index; /* first element (0 origin) */
+ int count;
+ u32 red;
+ u32 green;
+ u32 blue;
+};
+
+#define FBIOPUTCMAP32 _IOW('F', 3, struct fbcmap32)
+#define FBIOGETCMAP32 _IOW('F', 4, struct fbcmap32)
+
+struct fbcursor32 {
+ short set; /* what to set, choose from the list above */
+ short enable; /* cursor on/off */
+ struct fbcurpos pos; /* cursor position */
+ struct fbcurpos hot; /* cursor hot spot */
+ struct fbcmap32 cmap; /* color map info */
+ struct fbcurpos size; /* cursor bit map size */
+ u32 image; /* cursor image bits */
+ u32 mask; /* cursor mask bits */
+};
+
+#define FBIOSCURSOR32 _IOW('F', 24, struct fbcursor32)
+#define FBIOGCURSOR32 _IOW('F', 25, struct fbcursor32)
+#endif
+
+#endif /* __LINUX_FBIO_H */
--- /dev/null
+#ifndef _SPARC_FCNTL_H
+#define _SPARC_FCNTL_H
+
+/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
+ located on an ext2 file system */
+#define O_APPEND 0x0008
+#define FASYNC 0x0040 /* fcntl, for BSD compatibility */
+#define O_CREAT 0x0200 /* not fcntl */
+#define O_TRUNC 0x0400 /* not fcntl */
+#define O_EXCL 0x0800 /* not fcntl */
+#define O_SYNC 0x2000
+#define O_NONBLOCK 0x4000
+#if defined(__sparc__) && defined(__arch64__)
+#define O_NDELAY 0x0004
+#else
+#define O_NDELAY (0x0004 | O_NONBLOCK)
+#endif
+#define O_NOCTTY 0x8000 /* not fcntl */
+#define O_LARGEFILE 0x40000
+#define O_DIRECT 0x100000 /* direct disk access hint */
+#define O_NOATIME 0x200000
+#define O_CLOEXEC 0x400000
+
+#define F_GETOWN 5 /* for sockets. */
+#define F_SETOWN 6 /* for sockets. */
+#define F_GETLK 7
+#define F_SETLK 8
+#define F_SETLKW 9
+
+/* for posix fcntl() and lockf() */
+#define F_RDLCK 1
+#define F_WRLCK 2
+#define F_UNLCK 3
+
+#define __ARCH_FLOCK_PAD short __unused;
+#define __ARCH_FLOCK64_PAD short __unused;
+
+#include <asm-generic/fcntl.h>
+
+#endif
--- /dev/null
+/*
+ * fhc.h: Structures for central/fhc pseudo driver on Sunfire/Starfire/Wildfire.
+ *
+ * Copyright (C) 1997, 1999 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef _SPARC64_FHC_H
+#define _SPARC64_FHC_H
+
+#include <linux/timer.h>
+
+#include <asm/oplib.h>
+#include <asm/prom.h>
+#include <asm/upa.h>
+
+struct linux_fhc;
+
+/* Clock board register offsets. */
+#define CLOCK_CTRL 0x00UL /* Main control */
+#define CLOCK_STAT1 0x10UL /* Status one */
+#define CLOCK_STAT2 0x20UL /* Status two */
+#define CLOCK_PWRSTAT 0x30UL /* Power status */
+#define CLOCK_PWRPRES 0x40UL /* Power presence */
+#define CLOCK_TEMP 0x50UL /* Temperature */
+#define CLOCK_IRQDIAG 0x60UL /* IRQ diagnostics */
+#define CLOCK_PWRSTAT2 0x70UL /* Power status two */
+
+#define CLOCK_CTRL_LLED 0x04 /* Left LED, 0 == on */
+#define CLOCK_CTRL_MLED 0x02 /* Mid LED, 1 == on */
+#define CLOCK_CTRL_RLED 0x01 /* RIght LED, 1 == on */
+
+struct linux_central {
+ struct linux_fhc *child;
+ unsigned long cfreg;
+ unsigned long clkregs;
+ unsigned long clkver;
+ int slots;
+ struct device_node *prom_node;
+
+ struct linux_prom_ranges central_ranges[PROMREG_MAX];
+ int num_central_ranges;
+};
+
+/* Firehose controller register offsets */
+struct fhc_regs {
+ unsigned long pregs; /* FHC internal regs */
+#define FHC_PREGS_ID 0x00UL /* FHC ID */
+#define FHC_ID_VERS 0xf0000000 /* Version of this FHC */
+#define FHC_ID_PARTID 0x0ffff000 /* Part ID code (0x0f9f == FHC) */
+#define FHC_ID_MANUF 0x0000007e /* Manufacturer (0x3e == SUN's JEDEC)*/
+#define FHC_ID_RESV 0x00000001 /* Read as one */
+#define FHC_PREGS_RCS 0x10UL /* FHC Reset Control/Status Register */
+#define FHC_RCS_POR 0x80000000 /* Last reset was a power cycle */
+#define FHC_RCS_SPOR 0x40000000 /* Last reset was sw power on reset */
+#define FHC_RCS_SXIR 0x20000000 /* Last reset was sw XIR reset */
+#define FHC_RCS_BPOR 0x10000000 /* Last reset was due to POR button */
+#define FHC_RCS_BXIR 0x08000000 /* Last reset was due to XIR button */
+#define FHC_RCS_WEVENT 0x04000000 /* CPU reset was due to wakeup event */
+#define FHC_RCS_CFATAL 0x02000000 /* Centerplane Fatal Error signalled */
+#define FHC_RCS_FENAB 0x01000000 /* Fatal errors elicit system reset */
+#define FHC_PREGS_CTRL 0x20UL /* FHC Control Register */
+#define FHC_CONTROL_ICS 0x00100000 /* Ignore Centerplane Signals */
+#define FHC_CONTROL_FRST 0x00080000 /* Fatal Error Reset Enable */
+#define FHC_CONTROL_LFAT 0x00040000 /* AC/DC signalled a local error */
+#define FHC_CONTROL_SLINE 0x00010000 /* Firmware Synchronization Line */
+#define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
+#define FHC_CONTROL_POFF 0x00004000 /* AC/DC Controller PLL Disable */
+#define FHC_CONTROL_FOFF 0x00002000 /* FHC Controller PLL Disable */
+#define FHC_CONTROL_AOFF 0x00001000 /* CPU A SRAM/SBD Low Power Mode */
+#define FHC_CONTROL_BOFF 0x00000800 /* CPU B SRAM/SBD Low Power Mode */
+#define FHC_CONTROL_PSOFF 0x00000400 /* Turns off this FHC's power supply */
+#define FHC_CONTROL_IXIST 0x00000200 /* 0=FHC tells clock board it exists */
+#define FHC_CONTROL_XMSTR 0x00000100 /* 1=Causes this FHC to be XIR master*/
+#define FHC_CONTROL_LLED 0x00000040 /* 0=Left LED ON */
+#define FHC_CONTROL_MLED 0x00000020 /* 1=Middle LED ON */
+#define FHC_CONTROL_RLED 0x00000010 /* 1=Right LED */
+#define FHC_CONTROL_BPINS 0x00000003 /* Spare Bidirectional Pins */
+#define FHC_PREGS_BSR 0x30UL /* FHC Board Status Register */
+#define FHC_BSR_DA64 0x00040000 /* Port A: 0=128bit 1=64bit data path */
+#define FHC_BSR_DB64 0x00020000 /* Port B: 0=128bit 1=64bit data path */
+#define FHC_BSR_BID 0x0001e000 /* Board ID */
+#define FHC_BSR_SA 0x00001c00 /* Port A UPA Speed (from the pins) */
+#define FHC_BSR_SB 0x00000380 /* Port B UPA Speed (from the pins) */
+#define FHC_BSR_NDIAG 0x00000040 /* Not in Diag Mode */
+#define FHC_BSR_NTBED 0x00000020 /* Not in TestBED Mode */
+#define FHC_BSR_NIA 0x0000001c /* Jumper, bit 18 in PROM space */
+#define FHC_BSR_SI 0x00000001 /* Spare input pin value */
+#define FHC_PREGS_ECC 0x40UL /* FHC ECC Control Register (16 bits) */
+#define FHC_PREGS_JCTRL 0xf0UL /* FHC JTAG Control Register */
+#define FHC_JTAG_CTRL_MENAB 0x80000000 /* Indicates this is JTAG Master */
+#define FHC_JTAG_CTRL_MNONE 0x40000000 /* Indicates no JTAG Master present */
+#define FHC_PREGS_JCMD 0x100UL /* FHC JTAG Command Register */
+ unsigned long ireg; /* FHC IGN reg */
+#define FHC_IREG_IGN 0x00UL /* This FHC's IGN */
+ unsigned long ffregs; /* FHC fanfail regs */
+#define FHC_FFREGS_IMAP 0x00UL /* FHC Fanfail IMAP */
+#define FHC_FFREGS_ICLR 0x10UL /* FHC Fanfail ICLR */
+ unsigned long sregs; /* FHC system regs */
+#define FHC_SREGS_IMAP 0x00UL /* FHC System IMAP */
+#define FHC_SREGS_ICLR 0x10UL /* FHC System ICLR */
+ unsigned long uregs; /* FHC uart regs */
+#define FHC_UREGS_IMAP 0x00UL /* FHC Uart IMAP */
+#define FHC_UREGS_ICLR 0x10UL /* FHC Uart ICLR */
+ unsigned long tregs; /* FHC TOD regs */
+#define FHC_TREGS_IMAP 0x00UL /* FHC TOD IMAP */
+#define FHC_TREGS_ICLR 0x10UL /* FHC TOD ICLR */
+};
+
+struct linux_fhc {
+ struct linux_fhc *next;
+ struct linux_central *parent; /* NULL if not central FHC */
+ struct fhc_regs fhc_regs;
+ int board;
+ int jtag_master;
+ struct device_node *prom_node;
+
+ struct linux_prom_ranges fhc_ranges[PROMREG_MAX];
+ int num_fhc_ranges;
+};
+
+#endif /* !(_SPARC64_FHC_H) */
--- /dev/null
+/*
+ * fixmap.h: compile-time virtual memory allocation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Ingo Molnar
+ *
+ * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
+ */
+
+#ifndef _ASM_FIXMAP_H
+#define _ASM_FIXMAP_H
+
+#include <linux/kernel.h>
+#include <asm/page.h>
+#ifdef CONFIG_HIGHMEM
+#include <linux/threads.h>
+#include <asm/kmap_types.h>
+#endif
+
+/*
+ * Here we define all the compile-time 'special' virtual
+ * addresses. The point is to have a constant address at
+ * compile time, but to set the physical address only
+ * in the boot process. We allocate these special addresses
+ * from the top of unused virtual memory (0xfd000000 - 1 page) backwards.
+ * Also this lets us do fail-safe vmalloc(), we
+ * can guarantee that these special addresses and
+ * vmalloc()-ed addresses never overlap.
+ *
+ * these 'compile-time allocated' memory buffers are
+ * fixed-size 4k pages. (or larger if used with an increment
+ * highger than 1) use fixmap_set(idx,phys) to associate
+ * physical memory with fixmap indices.
+ *
+ * TLB entries of such buffers will not be flushed across
+ * task switches.
+ */
+
+/*
+ * on UP currently we will have no trace of the fixmap mechanism,
+ * no page table allocations, etc. This might change in the
+ * future, say framebuffers for the console driver(s) could be
+ * fix-mapped?
+ */
+enum fixed_addresses {
+ FIX_HOLE,
+#ifdef CONFIG_HIGHMEM
+ FIX_KMAP_BEGIN,
+ FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
+#endif
+ __end_of_fixed_addresses
+};
+
+extern void __set_fixmap (enum fixed_addresses idx,
+ unsigned long phys, pgprot_t flags);
+
+#define set_fixmap(idx, phys) \
+ __set_fixmap(idx, phys, PAGE_KERNEL)
+/*
+ * Some hardware wants to get fixmapped without caching.
+ */
+#define set_fixmap_nocache(idx, phys) \
+ __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
+/*
+ * used by vmalloc.c.
+ *
+ * Leave one empty page between IO pages at 0xfd000000 and
+ * the start of the fixmap.
+ */
+#define FIXADDR_TOP (0xfcfff000UL)
+#define FIXADDR_SIZE ((__end_of_fixed_addresses) << PAGE_SHIFT)
+#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
+
+#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
+#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
+
+extern void __this_fixmap_does_not_exist(void);
+
+/*
+ * 'index to address' translation. If anyone tries to use the idx
+ * directly without tranlation, we catch the bug with a NULL-deference
+ * kernel oops. Illegal ranges of incoming indices are caught too.
+ */
+static inline unsigned long fix_to_virt(const unsigned int idx)
+{
+ /*
+ * this branch gets completely eliminated after inlining,
+ * except when someone tries to use fixaddr indices in an
+ * illegal way. (such as mixing up address types or using
+ * out-of-range indices).
+ *
+ * If it doesn't get removed, the linker will complain
+ * loudly with a reasonably clear error message..
+ */
+ if (idx >= __end_of_fixed_addresses)
+ __this_fixmap_does_not_exist();
+
+ return __fix_to_virt(idx);
+}
+
+static inline unsigned long virt_to_fix(const unsigned long vaddr)
+{
+ BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
+ return __virt_to_fix(vaddr);
+}
+
+#endif
--- /dev/null
+#ifndef ___ASM_SPARC_FLOPPY_H
+#define ___ASM_SPARC_FLOPPY_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/floppy_64.h>
+#else
+#include <asm/floppy_32.h>
+#endif
+#endif
--- /dev/null
+/* asm/floppy.h: Sparc specific parts of the Floppy driver.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef __ASM_SPARC_FLOPPY_H
+#define __ASM_SPARC_FLOPPY_H
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/idprom.h>
+#include <asm/machines.h>
+#include <asm/oplib.h>
+#include <asm/auxio.h>
+#include <asm/irq.h>
+
+/* We don't need no stinkin' I/O port allocation crap. */
+#undef release_region
+#undef request_region
+#define release_region(X, Y) do { } while(0)
+#define request_region(X, Y, Z) (1)
+
+/* References:
+ * 1) Netbsd Sun floppy driver.
+ * 2) NCR 82077 controller manual
+ * 3) Intel 82077 controller manual
+ */
+struct sun_flpy_controller {
+ volatile unsigned char status_82072; /* Main Status reg. */
+#define dcr_82072 status_82072 /* Digital Control reg. */
+#define status1_82077 status_82072 /* Auxiliary Status reg. 1 */
+
+ volatile unsigned char data_82072; /* Data fifo. */
+#define status2_82077 data_82072 /* Auxiliary Status reg. 2 */
+
+ volatile unsigned char dor_82077; /* Digital Output reg. */
+ volatile unsigned char tapectl_82077; /* What the? Tape control reg? */
+
+ volatile unsigned char status_82077; /* Main Status Register. */
+#define drs_82077 status_82077 /* Digital Rate Select reg. */
+
+ volatile unsigned char data_82077; /* Data fifo. */
+ volatile unsigned char ___unused;
+ volatile unsigned char dir_82077; /* Digital Input reg. */
+#define dcr_82077 dir_82077 /* Config Control reg. */
+};
+
+/* You'll only ever find one controller on a SparcStation anyways. */
+static struct sun_flpy_controller *sun_fdc = NULL;
+extern volatile unsigned char *fdc_status;
+
+struct sun_floppy_ops {
+ unsigned char (*fd_inb)(int port);
+ void (*fd_outb)(unsigned char value, int port);
+};
+
+static struct sun_floppy_ops sun_fdops;
+
+#define fd_inb(port) sun_fdops.fd_inb(port)
+#define fd_outb(value,port) sun_fdops.fd_outb(value,port)
+#define fd_enable_dma() sun_fd_enable_dma()
+#define fd_disable_dma() sun_fd_disable_dma()
+#define fd_request_dma() (0) /* nothing... */
+#define fd_free_dma() /* nothing... */
+#define fd_clear_dma_ff() /* nothing... */
+#define fd_set_dma_mode(mode) sun_fd_set_dma_mode(mode)
+#define fd_set_dma_addr(addr) sun_fd_set_dma_addr(addr)
+#define fd_set_dma_count(count) sun_fd_set_dma_count(count)
+#define fd_enable_irq() /* nothing... */
+#define fd_disable_irq() /* nothing... */
+#define fd_cacheflush(addr, size) /* nothing... */
+#define fd_request_irq() sun_fd_request_irq()
+#define fd_free_irq() /* nothing... */
+#if 0 /* P3: added by Alain, these cause a MMU corruption. 19960524 XXX */
+#define fd_dma_mem_alloc(size) ((unsigned long) vmalloc(size))
+#define fd_dma_mem_free(addr,size) (vfree((void *)(addr)))
+#endif
+
+/* XXX This isn't really correct. XXX */
+#define get_dma_residue(x) (0)
+
+#define FLOPPY0_TYPE 4
+#define FLOPPY1_TYPE 0
+
+/* Super paranoid... */
+#undef HAVE_DISABLE_HLT
+
+/* Here is where we catch the floppy driver trying to initialize,
+ * therefore this is where we call the PROM device tree probing
+ * routine etc. on the Sparc.
+ */
+#define FDC1 sun_floppy_init()
+
+#define N_FDC 1
+#define N_DRIVE 8
+
+/* No 64k boundary crossing problems on the Sparc. */
+#define CROSS_64KB(a,s) (0)
+
+/* Routines unique to each controller type on a Sun. */
+static void sun_set_dor(unsigned char value, int fdc_82077)
+{
+ if (sparc_cpu_model == sun4c) {
+ unsigned int bits = 0;
+ if (value & 0x10)
+ bits |= AUXIO_FLPY_DSEL;
+ if ((value & 0x80) == 0)
+ bits |= AUXIO_FLPY_EJCT;
+ set_auxio(bits, (~bits) & (AUXIO_FLPY_DSEL|AUXIO_FLPY_EJCT));
+ }
+ if (fdc_82077) {
+ sun_fdc->dor_82077 = value;
+ }
+}
+
+static unsigned char sun_read_dir(void)
+{
+ if (sparc_cpu_model == sun4c)
+ return (get_auxio() & AUXIO_FLPY_DCHG) ? 0x80 : 0;
+ else
+ return sun_fdc->dir_82077;
+}
+
+static unsigned char sun_82072_fd_inb(int port)
+{
+ udelay(5);
+ switch(port & 7) {
+ default:
+ printk("floppy: Asked to read unknown port %d\n", port);
+ panic("floppy: Port bolixed.");
+ case 4: /* FD_STATUS */
+ return sun_fdc->status_82072 & ~STATUS_DMA;
+ case 5: /* FD_DATA */
+ return sun_fdc->data_82072;
+ case 7: /* FD_DIR */
+ return sun_read_dir();
+ };
+ panic("sun_82072_fd_inb: How did I get here?");
+}
+
+static void sun_82072_fd_outb(unsigned char value, int port)
+{
+ udelay(5);
+ switch(port & 7) {
+ default:
+ printk("floppy: Asked to write to unknown port %d\n", port);
+ panic("floppy: Port bolixed.");
+ case 2: /* FD_DOR */
+ sun_set_dor(value, 0);
+ break;
+ case 5: /* FD_DATA */
+ sun_fdc->data_82072 = value;
+ break;
+ case 7: /* FD_DCR */
+ sun_fdc->dcr_82072 = value;
+ break;
+ case 4: /* FD_STATUS */
+ sun_fdc->status_82072 = value;
+ break;
+ };
+ return;
+}
+
+static unsigned char sun_82077_fd_inb(int port)
+{
+ udelay(5);
+ switch(port & 7) {
+ default:
+ printk("floppy: Asked to read unknown port %d\n", port);
+ panic("floppy: Port bolixed.");
+ case 0: /* FD_STATUS_0 */
+ return sun_fdc->status1_82077;
+ case 1: /* FD_STATUS_1 */
+ return sun_fdc->status2_82077;
+ case 2: /* FD_DOR */
+ return sun_fdc->dor_82077;
+ case 3: /* FD_TDR */
+ return sun_fdc->tapectl_82077;
+ case 4: /* FD_STATUS */
+ return sun_fdc->status_82077 & ~STATUS_DMA;
+ case 5: /* FD_DATA */
+ return sun_fdc->data_82077;
+ case 7: /* FD_DIR */
+ return sun_read_dir();
+ };
+ panic("sun_82077_fd_inb: How did I get here?");
+}
+
+static void sun_82077_fd_outb(unsigned char value, int port)
+{
+ udelay(5);
+ switch(port & 7) {
+ default:
+ printk("floppy: Asked to write to unknown port %d\n", port);
+ panic("floppy: Port bolixed.");
+ case 2: /* FD_DOR */
+ sun_set_dor(value, 1);
+ break;
+ case 5: /* FD_DATA */
+ sun_fdc->data_82077 = value;
+ break;
+ case 7: /* FD_DCR */
+ sun_fdc->dcr_82077 = value;
+ break;
+ case 4: /* FD_STATUS */
+ sun_fdc->status_82077 = value;
+ break;
+ case 3: /* FD_TDR */
+ sun_fdc->tapectl_82077 = value;
+ break;
+ };
+ return;
+}
+
+/* For pseudo-dma (Sun floppy drives have no real DMA available to
+ * them so we must eat the data fifo bytes directly ourselves) we have
+ * three state variables. doing_pdma tells our inline low-level
+ * assembly floppy interrupt entry point whether it should sit and eat
+ * bytes from the fifo or just transfer control up to the higher level
+ * floppy interrupt c-code. I tried very hard but I could not get the
+ * pseudo-dma to work in c-code without getting many overruns and
+ * underruns. If non-zero, doing_pdma encodes the direction of
+ * the transfer for debugging. 1=read 2=write
+ */
+extern char *pdma_vaddr;
+extern unsigned long pdma_size;
+extern volatile int doing_pdma;
+
+/* This is software state */
+extern char *pdma_base;
+extern unsigned long pdma_areasize;
+
+/* Common routines to all controller types on the Sparc. */
+static inline void virtual_dma_init(void)
+{
+ /* nothing... */
+}
+
+static inline void sun_fd_disable_dma(void)
+{
+ doing_pdma = 0;
+ if (pdma_base) {
+ mmu_unlockarea(pdma_base, pdma_areasize);
+ pdma_base = NULL;
+ }
+}
+
+static inline void sun_fd_set_dma_mode(int mode)
+{
+ switch(mode) {
+ case DMA_MODE_READ:
+ doing_pdma = 1;
+ break;
+ case DMA_MODE_WRITE:
+ doing_pdma = 2;
+ break;
+ default:
+ printk("Unknown dma mode %d\n", mode);
+ panic("floppy: Giving up...");
+ }
+}
+
+static inline void sun_fd_set_dma_addr(char *buffer)
+{
+ pdma_vaddr = buffer;
+}
+
+static inline void sun_fd_set_dma_count(int length)
+{
+ pdma_size = length;
+}
+
+static inline void sun_fd_enable_dma(void)
+{
+ pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size);
+ pdma_base = pdma_vaddr;
+ pdma_areasize = pdma_size;
+}
+
+/* Our low-level entry point in arch/sparc/kernel/entry.S */
+extern int sparc_floppy_request_irq(int irq, unsigned long flags,
+ irq_handler_t irq_handler);
+
+static int sun_fd_request_irq(void)
+{
+ static int once = 0;
+ int error;
+
+ if(!once) {
+ once = 1;
+ error = sparc_floppy_request_irq(FLOPPY_IRQ,
+ IRQF_DISABLED,
+ floppy_interrupt);
+ return ((error == 0) ? 0 : -1);
+ } else return 0;
+}
+
+static struct linux_prom_registers fd_regs[2];
+
+static int sun_floppy_init(void)
+{
+ char state[128];
+ int tnode, fd_node, num_regs;
+ struct resource r;
+
+ use_virtual_dma = 1;
+
+ FLOPPY_IRQ = 11;
+ /* Forget it if we aren't on a machine that could possibly
+ * ever have a floppy drive.
+ */
+ if((sparc_cpu_model != sun4c && sparc_cpu_model != sun4m) ||
+ ((idprom->id_machtype == (SM_SUN4C | SM_4C_SLC)) ||
+ (idprom->id_machtype == (SM_SUN4C | SM_4C_ELC)))) {
+ /* We certainly don't have a floppy controller. */
+ goto no_sun_fdc;
+ }
+ /* Well, try to find one. */
+ tnode = prom_getchild(prom_root_node);
+ fd_node = prom_searchsiblings(tnode, "obio");
+ if(fd_node != 0) {
+ tnode = prom_getchild(fd_node);
+ fd_node = prom_searchsiblings(tnode, "SUNW,fdtwo");
+ } else {
+ fd_node = prom_searchsiblings(tnode, "fd");
+ }
+ if(fd_node == 0) {
+ goto no_sun_fdc;
+ }
+
+ /* The sun4m lets us know if the controller is actually usable. */
+ if(sparc_cpu_model == sun4m &&
+ prom_getproperty(fd_node, "status", state, sizeof(state)) != -1) {
+ if(!strcmp(state, "disabled")) {
+ goto no_sun_fdc;
+ }
+ }
+ num_regs = prom_getproperty(fd_node, "reg", (char *) fd_regs, sizeof(fd_regs));
+ num_regs = (num_regs / sizeof(fd_regs[0]));
+ prom_apply_obio_ranges(fd_regs, num_regs);
+ memset(&r, 0, sizeof(r));
+ r.flags = fd_regs[0].which_io;
+ r.start = fd_regs[0].phys_addr;
+ sun_fdc = (struct sun_flpy_controller *)
+ sbus_ioremap(&r, 0, fd_regs[0].reg_size, "floppy");
+
+ /* Last minute sanity check... */
+ if(sun_fdc->status_82072 == 0xff) {
+ sun_fdc = NULL;
+ goto no_sun_fdc;
+ }
+
+ sun_fdops.fd_inb = sun_82077_fd_inb;
+ sun_fdops.fd_outb = sun_82077_fd_outb;
+ fdc_status = &sun_fdc->status_82077;
+
+ if (sun_fdc->dor_82077 == 0x80) {
+ sun_fdc->dor_82077 = 0x02;
+ if (sun_fdc->dor_82077 == 0x80) {
+ sun_fdops.fd_inb = sun_82072_fd_inb;
+ sun_fdops.fd_outb = sun_82072_fd_outb;
+ fdc_status = &sun_fdc->status_82072;
+ }
+ }
+
+ /* Success... */
+ allowed_drive_mask = 0x01;
+ return (int) sun_fdc;
+
+no_sun_fdc:
+ return -1;
+}
+
+static int sparc_eject(void)
+{
+ set_dor(0x00, 0xff, 0x90);
+ udelay(500);
+ set_dor(0x00, 0x6f, 0x00);
+ udelay(500);
+ return 0;
+}
+
+#define fd_eject(drive) sparc_eject()
+
+#define EXTRA_FLOPPY_PARAMS
+
+#endif /* !(__ASM_SPARC_FLOPPY_H) */
--- /dev/null
+/* floppy.h: Sparc specific parts of the Floppy driver.
+ *
+ * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ *
+ * Ultra/PCI support added: Sep 1997 Eddie C. Dost (ecd@skynet.be)
+ */
+
+#ifndef __ASM_SPARC64_FLOPPY_H
+#define __ASM_SPARC64_FLOPPY_H
+
+#include <linux/init.h>
+#include <linux/pci.h>
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/idprom.h>
+#include <asm/oplib.h>
+#include <asm/auxio.h>
+#include <asm/sbus.h>
+#include <asm/irq.h>
+
+
+/*
+ * Define this to enable exchanging drive 0 and 1 if only drive 1 is
+ * probed on PCI machines.
+ */
+#undef PCI_FDC_SWAP_DRIVES
+
+
+/* References:
+ * 1) Netbsd Sun floppy driver.
+ * 2) NCR 82077 controller manual
+ * 3) Intel 82077 controller manual
+ */
+struct sun_flpy_controller {
+ volatile unsigned char status1_82077; /* Auxiliary Status reg. 1 */
+ volatile unsigned char status2_82077; /* Auxiliary Status reg. 2 */
+ volatile unsigned char dor_82077; /* Digital Output reg. */
+ volatile unsigned char tapectl_82077; /* Tape Control reg */
+ volatile unsigned char status_82077; /* Main Status Register. */
+#define drs_82077 status_82077 /* Digital Rate Select reg. */
+ volatile unsigned char data_82077; /* Data fifo. */
+ volatile unsigned char ___unused;
+ volatile unsigned char dir_82077; /* Digital Input reg. */
+#define dcr_82077 dir_82077 /* Config Control reg. */
+};
+
+/* You'll only ever find one controller on an Ultra anyways. */
+static struct sun_flpy_controller *sun_fdc = (struct sun_flpy_controller *)-1;
+unsigned long fdc_status;
+static struct sbus_dev *floppy_sdev = NULL;
+
+struct sun_floppy_ops {
+ unsigned char (*fd_inb) (unsigned long port);
+ void (*fd_outb) (unsigned char value, unsigned long port);
+ void (*fd_enable_dma) (void);
+ void (*fd_disable_dma) (void);
+ void (*fd_set_dma_mode) (int);
+ void (*fd_set_dma_addr) (char *);
+ void (*fd_set_dma_count) (int);
+ unsigned int (*get_dma_residue) (void);
+ int (*fd_request_irq) (void);
+ void (*fd_free_irq) (void);
+ int (*fd_eject) (int);
+};
+
+static struct sun_floppy_ops sun_fdops;
+
+#define fd_inb(port) sun_fdops.fd_inb(port)
+#define fd_outb(value,port) sun_fdops.fd_outb(value,port)
+#define fd_enable_dma() sun_fdops.fd_enable_dma()
+#define fd_disable_dma() sun_fdops.fd_disable_dma()
+#define fd_request_dma() (0) /* nothing... */
+#define fd_free_dma() /* nothing... */
+#define fd_clear_dma_ff() /* nothing... */
+#define fd_set_dma_mode(mode) sun_fdops.fd_set_dma_mode(mode)
+#define fd_set_dma_addr(addr) sun_fdops.fd_set_dma_addr(addr)
+#define fd_set_dma_count(count) sun_fdops.fd_set_dma_count(count)
+#define get_dma_residue(x) sun_fdops.get_dma_residue()
+#define fd_cacheflush(addr, size) /* nothing... */
+#define fd_request_irq() sun_fdops.fd_request_irq()
+#define fd_free_irq() sun_fdops.fd_free_irq()
+#define fd_eject(drive) sun_fdops.fd_eject(drive)
+
+/* Super paranoid... */
+#undef HAVE_DISABLE_HLT
+
+static int sun_floppy_types[2] = { 0, 0 };
+
+/* Here is where we catch the floppy driver trying to initialize,
+ * therefore this is where we call the PROM device tree probing
+ * routine etc. on the Sparc.
+ */
+#define FLOPPY0_TYPE sun_floppy_init()
+#define FLOPPY1_TYPE sun_floppy_types[1]
+
+#define FDC1 ((unsigned long)sun_fdc)
+
+#define N_FDC 1
+#define N_DRIVE 8
+
+/* No 64k boundary crossing problems on the Sparc. */
+#define CROSS_64KB(a,s) (0)
+
+static unsigned char sun_82077_fd_inb(unsigned long port)
+{
+ udelay(5);
+ switch(port & 7) {
+ default:
+ printk("floppy: Asked to read unknown port %lx\n", port);
+ panic("floppy: Port bolixed.");
+ case 4: /* FD_STATUS */
+ return sbus_readb(&sun_fdc->status_82077) & ~STATUS_DMA;
+ case 5: /* FD_DATA */
+ return sbus_readb(&sun_fdc->data_82077);
+ case 7: /* FD_DIR */
+ /* XXX: Is DCL on 0x80 in sun4m? */
+ return sbus_readb(&sun_fdc->dir_82077);
+ };
+ panic("sun_82072_fd_inb: How did I get here?");
+}
+
+static void sun_82077_fd_outb(unsigned char value, unsigned long port)
+{
+ udelay(5);
+ switch(port & 7) {
+ default:
+ printk("floppy: Asked to write to unknown port %lx\n", port);
+ panic("floppy: Port bolixed.");
+ case 2: /* FD_DOR */
+ /* Happily, the 82077 has a real DOR register. */
+ sbus_writeb(value, &sun_fdc->dor_82077);
+ break;
+ case 5: /* FD_DATA */
+ sbus_writeb(value, &sun_fdc->data_82077);
+ break;
+ case 7: /* FD_DCR */
+ sbus_writeb(value, &sun_fdc->dcr_82077);
+ break;
+ case 4: /* FD_STATUS */
+ sbus_writeb(value, &sun_fdc->status_82077);
+ break;
+ };
+ return;
+}
+
+/* For pseudo-dma (Sun floppy drives have no real DMA available to
+ * them so we must eat the data fifo bytes directly ourselves) we have
+ * three state variables. doing_pdma tells our inline low-level
+ * assembly floppy interrupt entry point whether it should sit and eat
+ * bytes from the fifo or just transfer control up to the higher level
+ * floppy interrupt c-code. I tried very hard but I could not get the
+ * pseudo-dma to work in c-code without getting many overruns and
+ * underruns. If non-zero, doing_pdma encodes the direction of
+ * the transfer for debugging. 1=read 2=write
+ */
+unsigned char *pdma_vaddr;
+unsigned long pdma_size;
+volatile int doing_pdma = 0;
+
+/* This is software state */
+char *pdma_base = NULL;
+unsigned long pdma_areasize;
+
+/* Common routines to all controller types on the Sparc. */
+static void sun_fd_disable_dma(void)
+{
+ doing_pdma = 0;
+ if (pdma_base) {
+ mmu_unlockarea(pdma_base, pdma_areasize);
+ pdma_base = NULL;
+ }
+}
+
+static void sun_fd_set_dma_mode(int mode)
+{
+ switch(mode) {
+ case DMA_MODE_READ:
+ doing_pdma = 1;
+ break;
+ case DMA_MODE_WRITE:
+ doing_pdma = 2;
+ break;
+ default:
+ printk("Unknown dma mode %d\n", mode);
+ panic("floppy: Giving up...");
+ }
+}
+
+static void sun_fd_set_dma_addr(char *buffer)
+{
+ pdma_vaddr = buffer;
+}
+
+static void sun_fd_set_dma_count(int length)
+{
+ pdma_size = length;
+}
+
+static void sun_fd_enable_dma(void)
+{
+ pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size);
+ pdma_base = pdma_vaddr;
+ pdma_areasize = pdma_size;
+}
+
+irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie)
+{
+ if (likely(doing_pdma)) {
+ void __iomem *stat = (void __iomem *) fdc_status;
+ unsigned char *vaddr = pdma_vaddr;
+ unsigned long size = pdma_size;
+ u8 val;
+
+ while (size) {
+ val = readb(stat);
+ if (unlikely(!(val & 0x80))) {
+ pdma_vaddr = vaddr;
+ pdma_size = size;
+ return IRQ_HANDLED;
+ }
+ if (unlikely(!(val & 0x20))) {
+ pdma_vaddr = vaddr;
+ pdma_size = size;
+ doing_pdma = 0;
+ goto main_interrupt;
+ }
+ if (val & 0x40) {
+ /* read */
+ *vaddr++ = readb(stat + 1);
+ } else {
+ unsigned char data = *vaddr++;
+
+ /* write */
+ writeb(data, stat + 1);
+ }
+ size--;
+ }
+
+ pdma_vaddr = vaddr;
+ pdma_size = size;
+
+ /* Send Terminal Count pulse to floppy controller. */
+ val = readb(auxio_register);
+ val |= AUXIO_AUX1_FTCNT;
+ writeb(val, auxio_register);
+ val &= ~AUXIO_AUX1_FTCNT;
+ writeb(val, auxio_register);
+
+ doing_pdma = 0;
+ }
+
+main_interrupt:
+ return floppy_interrupt(irq, dev_cookie);
+}
+
+static int sun_fd_request_irq(void)
+{
+ static int once = 0;
+ int error;
+
+ if(!once) {
+ once = 1;
+
+ error = request_irq(FLOPPY_IRQ, sparc_floppy_irq,
+ IRQF_DISABLED, "floppy", NULL);
+
+ return ((error == 0) ? 0 : -1);
+ }
+ return 0;
+}
+
+static void sun_fd_free_irq(void)
+{
+}
+
+static unsigned int sun_get_dma_residue(void)
+{
+ /* XXX This isn't really correct. XXX */
+ return 0;
+}
+
+static int sun_fd_eject(int drive)
+{
+ set_dor(0x00, 0xff, 0x90);
+ udelay(500);
+ set_dor(0x00, 0x6f, 0x00);
+ udelay(500);
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+#include <asm/ebus.h>
+#include <asm/ns87303.h>
+
+static struct ebus_dma_info sun_pci_fd_ebus_dma;
+static struct pci_dev *sun_pci_ebus_dev;
+static int sun_pci_broken_drive = -1;
+
+struct sun_pci_dma_op {
+ unsigned int addr;
+ int len;
+ int direction;
+ char *buf;
+};
+static struct sun_pci_dma_op sun_pci_dma_current = { -1U, 0, 0, NULL};
+static struct sun_pci_dma_op sun_pci_dma_pending = { -1U, 0, 0, NULL};
+
+extern irqreturn_t floppy_interrupt(int irq, void *dev_id);
+
+static unsigned char sun_pci_fd_inb(unsigned long port)
+{
+ udelay(5);
+ return inb(port);
+}
+
+static void sun_pci_fd_outb(unsigned char val, unsigned long port)
+{
+ udelay(5);
+ outb(val, port);
+}
+
+static void sun_pci_fd_broken_outb(unsigned char val, unsigned long port)
+{
+ udelay(5);
+ /*
+ * XXX: Due to SUN's broken floppy connector on AX and AXi
+ * we need to turn on MOTOR_0 also, if the floppy is
+ * jumpered to DS1 (like most PC floppies are). I hope
+ * this does not hurt correct hardware like the AXmp.
+ * (Eddie, Sep 12 1998).
+ */
+ if (port == ((unsigned long)sun_fdc) + 2) {
+ if (((val & 0x03) == sun_pci_broken_drive) && (val & 0x20)) {
+ val |= 0x10;
+ }
+ }
+ outb(val, port);
+}
+
+#ifdef PCI_FDC_SWAP_DRIVES
+static void sun_pci_fd_lde_broken_outb(unsigned char val, unsigned long port)
+{
+ udelay(5);
+ /*
+ * XXX: Due to SUN's broken floppy connector on AX and AXi
+ * we need to turn on MOTOR_0 also, if the floppy is
+ * jumpered to DS1 (like most PC floppies are). I hope
+ * this does not hurt correct hardware like the AXmp.
+ * (Eddie, Sep 12 1998).
+ */
+ if (port == ((unsigned long)sun_fdc) + 2) {
+ if (((val & 0x03) == sun_pci_broken_drive) && (val & 0x10)) {
+ val &= ~(0x03);
+ val |= 0x21;
+ }
+ }
+ outb(val, port);
+}
+#endif /* PCI_FDC_SWAP_DRIVES */
+
+static void sun_pci_fd_enable_dma(void)
+{
+ BUG_ON((NULL == sun_pci_dma_pending.buf) ||
+ (0 == sun_pci_dma_pending.len) ||
+ (0 == sun_pci_dma_pending.direction));
+
+ sun_pci_dma_current.buf = sun_pci_dma_pending.buf;
+ sun_pci_dma_current.len = sun_pci_dma_pending.len;
+ sun_pci_dma_current.direction = sun_pci_dma_pending.direction;
+
+ sun_pci_dma_pending.buf = NULL;
+ sun_pci_dma_pending.len = 0;
+ sun_pci_dma_pending.direction = 0;
+ sun_pci_dma_pending.addr = -1U;
+
+ sun_pci_dma_current.addr =
+ pci_map_single(sun_pci_ebus_dev,
+ sun_pci_dma_current.buf,
+ sun_pci_dma_current.len,
+ sun_pci_dma_current.direction);
+
+ ebus_dma_enable(&sun_pci_fd_ebus_dma, 1);
+
+ if (ebus_dma_request(&sun_pci_fd_ebus_dma,
+ sun_pci_dma_current.addr,
+ sun_pci_dma_current.len))
+ BUG();
+}
+
+static void sun_pci_fd_disable_dma(void)
+{
+ ebus_dma_enable(&sun_pci_fd_ebus_dma, 0);
+ if (sun_pci_dma_current.addr != -1U)
+ pci_unmap_single(sun_pci_ebus_dev,
+ sun_pci_dma_current.addr,
+ sun_pci_dma_current.len,
+ sun_pci_dma_current.direction);
+ sun_pci_dma_current.addr = -1U;
+}
+
+static void sun_pci_fd_set_dma_mode(int mode)
+{
+ if (mode == DMA_MODE_WRITE)
+ sun_pci_dma_pending.direction = PCI_DMA_TODEVICE;
+ else
+ sun_pci_dma_pending.direction = PCI_DMA_FROMDEVICE;
+
+ ebus_dma_prepare(&sun_pci_fd_ebus_dma, mode != DMA_MODE_WRITE);
+}
+
+static void sun_pci_fd_set_dma_count(int length)
+{
+ sun_pci_dma_pending.len = length;
+}
+
+static void sun_pci_fd_set_dma_addr(char *buffer)
+{
+ sun_pci_dma_pending.buf = buffer;
+}
+
+static unsigned int sun_pci_get_dma_residue(void)
+{
+ return ebus_dma_residue(&sun_pci_fd_ebus_dma);
+}
+
+static int sun_pci_fd_request_irq(void)
+{
+ return ebus_dma_irq_enable(&sun_pci_fd_ebus_dma, 1);
+}
+
+static void sun_pci_fd_free_irq(void)
+{
+ ebus_dma_irq_enable(&sun_pci_fd_ebus_dma, 0);
+}
+
+static int sun_pci_fd_eject(int drive)
+{
+ return -EINVAL;
+}
+
+void sun_pci_fd_dma_callback(struct ebus_dma_info *p, int event, void *cookie)
+{
+ floppy_interrupt(0, NULL);
+}
+
+/*
+ * Floppy probing, we'd like to use /dev/fd0 for a single Floppy on PCI,
+ * even if this is configured using DS1, thus looks like /dev/fd1 with
+ * the cabling used in Ultras.
+ */
+#define DOR (port + 2)
+#define MSR (port + 4)
+#define FIFO (port + 5)
+
+static void sun_pci_fd_out_byte(unsigned long port, unsigned char val,
+ unsigned long reg)
+{
+ unsigned char status;
+ int timeout = 1000;
+
+ while (!((status = inb(MSR)) & 0x80) && --timeout)
+ udelay(100);
+ outb(val, reg);
+}
+
+static unsigned char sun_pci_fd_sensei(unsigned long port)
+{
+ unsigned char result[2] = { 0x70, 0x00 };
+ unsigned char status;
+ int i = 0;
+
+ sun_pci_fd_out_byte(port, 0x08, FIFO);
+ do {
+ int timeout = 1000;
+
+ while (!((status = inb(MSR)) & 0x80) && --timeout)
+ udelay(100);
+
+ if (!timeout)
+ break;
+
+ if ((status & 0xf0) == 0xd0)
+ result[i++] = inb(FIFO);
+ else
+ break;
+ } while (i < 2);
+
+ return result[0];
+}
+
+static void sun_pci_fd_reset(unsigned long port)
+{
+ unsigned char mask = 0x00;
+ unsigned char status;
+ int timeout = 10000;
+
+ outb(0x80, MSR);
+ do {
+ status = sun_pci_fd_sensei(port);
+ if ((status & 0xc0) == 0xc0)
+ mask |= 1 << (status & 0x03);
+ else
+ udelay(100);
+ } while ((mask != 0x0f) && --timeout);
+}
+
+static int sun_pci_fd_test_drive(unsigned long port, int drive)
+{
+ unsigned char status, data;
+ int timeout = 1000;
+ int ready;
+
+ sun_pci_fd_reset(port);
+
+ data = (0x10 << drive) | 0x0c | drive;
+ sun_pci_fd_out_byte(port, data, DOR);
+
+ sun_pci_fd_out_byte(port, 0x07, FIFO);
+ sun_pci_fd_out_byte(port, drive & 0x03, FIFO);
+
+ do {
+ udelay(100);
+ status = sun_pci_fd_sensei(port);
+ } while (((status & 0xc0) == 0x80) && --timeout);
+
+ if (!timeout)
+ ready = 0;
+ else
+ ready = (status & 0x10) ? 0 : 1;
+
+ sun_pci_fd_reset(port);
+ return ready;
+}
+#undef FIFO
+#undef MSR
+#undef DOR
+
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_PCI
+static int __init ebus_fdthree_p(struct linux_ebus_device *edev)
+{
+ if (!strcmp(edev->prom_node->name, "fdthree"))
+ return 1;
+ if (!strcmp(edev->prom_node->name, "floppy")) {
+ const char *compat;
+
+ compat = of_get_property(edev->prom_node,
+ "compatible", NULL);
+ if (compat && !strcmp(compat, "fdthree"))
+ return 1;
+ }
+ return 0;
+}
+#endif
+
+static unsigned long __init sun_floppy_init(void)
+{
+ char state[128];
+ struct sbus_bus *bus;
+ struct sbus_dev *sdev = NULL;
+ static int initialized = 0;
+
+ if (initialized)
+ return sun_floppy_types[0];
+ initialized = 1;
+
+ for_all_sbusdev (sdev, bus) {
+ if (!strcmp(sdev->prom_name, "SUNW,fdtwo"))
+ break;
+ }
+ if(sdev) {
+ floppy_sdev = sdev;
+ FLOPPY_IRQ = sdev->irqs[0];
+ } else {
+#ifdef CONFIG_PCI
+ struct linux_ebus *ebus;
+ struct linux_ebus_device *edev = NULL;
+ unsigned long config = 0;
+ void __iomem *auxio_reg;
+ const char *state_prop;
+
+ for_each_ebus(ebus) {
+ for_each_ebusdev(edev, ebus) {
+ if (ebus_fdthree_p(edev))
+ goto ebus_done;
+ }
+ }
+ ebus_done:
+ if (!edev)
+ return 0;
+
+ state_prop = of_get_property(edev->prom_node, "status", NULL);
+ if (state_prop && !strncmp(state_prop, "disabled", 8))
+ return 0;
+
+ FLOPPY_IRQ = edev->irqs[0];
+
+ /* Make sure the high density bit is set, some systems
+ * (most notably Ultra5/Ultra10) come up with it clear.
+ */
+ auxio_reg = (void __iomem *) edev->resource[2].start;
+ writel(readl(auxio_reg)|0x2, auxio_reg);
+
+ sun_pci_ebus_dev = ebus->self;
+
+ spin_lock_init(&sun_pci_fd_ebus_dma.lock);
+
+ /* XXX ioremap */
+ sun_pci_fd_ebus_dma.regs = (void __iomem *)
+ edev->resource[1].start;
+ if (!sun_pci_fd_ebus_dma.regs)
+ return 0;
+
+ sun_pci_fd_ebus_dma.flags = (EBUS_DMA_FLAG_USE_EBDMA_HANDLER |
+ EBUS_DMA_FLAG_TCI_DISABLE);
+ sun_pci_fd_ebus_dma.callback = sun_pci_fd_dma_callback;
+ sun_pci_fd_ebus_dma.client_cookie = NULL;
+ sun_pci_fd_ebus_dma.irq = FLOPPY_IRQ;
+ strcpy(sun_pci_fd_ebus_dma.name, "floppy");
+ if (ebus_dma_register(&sun_pci_fd_ebus_dma))
+ return 0;
+
+ /* XXX ioremap */
+ sun_fdc = (struct sun_flpy_controller *)edev->resource[0].start;
+
+ sun_fdops.fd_inb = sun_pci_fd_inb;
+ sun_fdops.fd_outb = sun_pci_fd_outb;
+
+ can_use_virtual_dma = use_virtual_dma = 0;
+ sun_fdops.fd_enable_dma = sun_pci_fd_enable_dma;
+ sun_fdops.fd_disable_dma = sun_pci_fd_disable_dma;
+ sun_fdops.fd_set_dma_mode = sun_pci_fd_set_dma_mode;
+ sun_fdops.fd_set_dma_addr = sun_pci_fd_set_dma_addr;
+ sun_fdops.fd_set_dma_count = sun_pci_fd_set_dma_count;
+ sun_fdops.get_dma_residue = sun_pci_get_dma_residue;
+
+ sun_fdops.fd_request_irq = sun_pci_fd_request_irq;
+ sun_fdops.fd_free_irq = sun_pci_fd_free_irq;
+
+ sun_fdops.fd_eject = sun_pci_fd_eject;
+
+ fdc_status = (unsigned long) &sun_fdc->status_82077;
+
+ /*
+ * XXX: Find out on which machines this is really needed.
+ */
+ if (1) {
+ sun_pci_broken_drive = 1;
+ sun_fdops.fd_outb = sun_pci_fd_broken_outb;
+ }
+
+ allowed_drive_mask = 0;
+ if (sun_pci_fd_test_drive((unsigned long)sun_fdc, 0))
+ sun_floppy_types[0] = 4;
+ if (sun_pci_fd_test_drive((unsigned long)sun_fdc, 1))
+ sun_floppy_types[1] = 4;
+
+ /*
+ * Find NS87303 SuperIO config registers (through ecpp).
+ */
+ for_each_ebus(ebus) {
+ for_each_ebusdev(edev, ebus) {
+ if (!strcmp(edev->prom_node->name, "ecpp")) {
+ config = edev->resource[1].start;
+ goto config_done;
+ }
+ }
+ }
+ config_done:
+
+ /*
+ * Sanity check, is this really the NS87303?
+ */
+ switch (config & 0x3ff) {
+ case 0x02e:
+ case 0x15c:
+ case 0x26e:
+ case 0x398:
+ break;
+ default:
+ config = 0;
+ }
+
+ if (!config)
+ return sun_floppy_types[0];
+
+ /* Enable PC-AT mode. */
+ ns87303_modify(config, ASC, 0, 0xc0);
+
+#ifdef PCI_FDC_SWAP_DRIVES
+ /*
+ * If only Floppy 1 is present, swap drives.
+ */
+ if (!sun_floppy_types[0] && sun_floppy_types[1]) {
+ /*
+ * Set the drive exchange bit in FCR on NS87303,
+ * make sure other bits are sane before doing so.
+ */
+ ns87303_modify(config, FER, FER_EDM, 0);
+ ns87303_modify(config, ASC, ASC_DRV2_SEL, 0);
+ ns87303_modify(config, FCR, 0, FCR_LDE);
+
+ config = sun_floppy_types[0];
+ sun_floppy_types[0] = sun_floppy_types[1];
+ sun_floppy_types[1] = config;
+
+ if (sun_pci_broken_drive != -1) {
+ sun_pci_broken_drive = 1 - sun_pci_broken_drive;
+ sun_fdops.fd_outb = sun_pci_fd_lde_broken_outb;
+ }
+ }
+#endif /* PCI_FDC_SWAP_DRIVES */
+
+ return sun_floppy_types[0];
+#else
+ return 0;
+#endif
+ }
+ prom_getproperty(sdev->prom_node, "status", state, sizeof(state));
+ if(!strncmp(state, "disabled", 8))
+ return 0;
+
+ /*
+ * We cannot do sbus_ioremap here: it does request_region,
+ * which the generic floppy driver tries to do once again.
+ * But we must use the sdev resource values as they have
+ * had parent ranges applied.
+ */
+ sun_fdc = (struct sun_flpy_controller *)
+ (sdev->resource[0].start +
+ ((sdev->resource[0].flags & 0x1ffUL) << 32UL));
+
+ /* Last minute sanity check... */
+ if(sbus_readb(&sun_fdc->status1_82077) == 0xff) {
+ sun_fdc = (struct sun_flpy_controller *)-1;
+ return 0;
+ }
+
+ sun_fdops.fd_inb = sun_82077_fd_inb;
+ sun_fdops.fd_outb = sun_82077_fd_outb;
+
+ can_use_virtual_dma = use_virtual_dma = 1;
+ sun_fdops.fd_enable_dma = sun_fd_enable_dma;
+ sun_fdops.fd_disable_dma = sun_fd_disable_dma;
+ sun_fdops.fd_set_dma_mode = sun_fd_set_dma_mode;
+ sun_fdops.fd_set_dma_addr = sun_fd_set_dma_addr;
+ sun_fdops.fd_set_dma_count = sun_fd_set_dma_count;
+ sun_fdops.get_dma_residue = sun_get_dma_residue;
+
+ sun_fdops.fd_request_irq = sun_fd_request_irq;
+ sun_fdops.fd_free_irq = sun_fd_free_irq;
+
+ sun_fdops.fd_eject = sun_fd_eject;
+
+ fdc_status = (unsigned long) &sun_fdc->status_82077;
+
+ /* Success... */
+ allowed_drive_mask = 0x01;
+ sun_floppy_types[0] = 4;
+ sun_floppy_types[1] = 0;
+
+ return sun_floppy_types[0];
+}
+
+#define EXTRA_FLOPPY_PARAMS
+
+static DEFINE_SPINLOCK(dma_spin_lock);
+
+#define claim_dma_lock() \
+({ unsigned long flags; \
+ spin_lock_irqsave(&dma_spin_lock, flags); \
+ flags; \
+})
+
+#define release_dma_lock(__flags) \
+ spin_unlock_irqrestore(&dma_spin_lock, __flags);
+
+#endif /* !(__ASM_SPARC64_FLOPPY_H) */
--- /dev/null
+/* fpumacro.h: FPU related macros.
+ *
+ * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC64_FPUMACRO_H
+#define _SPARC64_FPUMACRO_H
+
+#include <asm/asi.h>
+#include <asm/visasm.h>
+
+struct fpustate {
+ u32 regs[64];
+};
+
+#define FPUSTATE (struct fpustate *)(current_thread_info()->fpregs)
+
+static inline unsigned long fprs_read(void)
+{
+ unsigned long retval;
+
+ __asm__ __volatile__("rd %%fprs, %0" : "=r" (retval));
+
+ return retval;
+}
+
+static inline void fprs_write(unsigned long val)
+{
+ __asm__ __volatile__("wr %0, 0x0, %%fprs" : : "r" (val));
+}
+
+#endif /* !(_SPARC64_FPUMACRO_H) */
--- /dev/null
+#ifndef _ASM_SPARC64_FTRACE
+#define _ASM_SPARC64_FTRACE
+
+#ifdef CONFIG_MCOUNT
+#define MCOUNT_ADDR ((long)(_mcount))
+#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
+
+#ifndef __ASSEMBLY__
+extern void _mcount(void);
+#endif
+
+#endif
+
+#endif /* _ASM_SPARC64_FTRACE */
--- /dev/null
+#ifndef ___ASM_SPARC_FUTEX_H
+#define ___ASM_SPARC_FUTEX_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/futex_64.h>
+#else
+#include <asm/futex_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#include <asm-generic/futex.h>
+
+#endif
--- /dev/null
+#ifndef _SPARC64_FUTEX_H
+#define _SPARC64_FUTEX_H
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+#include <asm/system.h>
+
+#define __futex_cas_op(insn, ret, oldval, uaddr, oparg) \
+ __asm__ __volatile__( \
+ "\n1: lduwa [%3] %%asi, %2\n" \
+ " " insn "\n" \
+ "2: casa [%3] %%asi, %2, %1\n" \
+ " cmp %2, %1\n" \
+ " bne,pn %%icc, 1b\n" \
+ " mov 0, %0\n" \
+ "3:\n" \
+ " .section .fixup,#alloc,#execinstr\n" \
+ " .align 4\n" \
+ "4: sethi %%hi(3b), %0\n" \
+ " jmpl %0 + %%lo(3b), %%g0\n" \
+ " mov %5, %0\n" \
+ " .previous\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 4\n" \
+ " .word 1b, 4b\n" \
+ " .word 2b, 4b\n" \
+ " .previous\n" \
+ : "=&r" (ret), "=&r" (oldval), "=&r" (tem) \
+ : "r" (uaddr), "r" (oparg), "i" (-EFAULT) \
+ : "memory")
+
+static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
+{
+ int op = (encoded_op >> 28) & 7;
+ int cmp = (encoded_op >> 24) & 15;
+ int oparg = (encoded_op << 8) >> 20;
+ int cmparg = (encoded_op << 20) >> 20;
+ int oldval = 0, ret, tem;
+
+ if (unlikely(!access_ok(VERIFY_WRITE, uaddr, sizeof(int))))
+ return -EFAULT;
+ if (unlikely((((unsigned long) uaddr) & 0x3UL)))
+ return -EINVAL;
+
+ if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+ oparg = 1 << oparg;
+
+ pagefault_disable();
+
+ switch (op) {
+ case FUTEX_OP_SET:
+ __futex_cas_op("mov\t%4, %1", ret, oldval, uaddr, oparg);
+ break;
+ case FUTEX_OP_ADD:
+ __futex_cas_op("add\t%2, %4, %1", ret, oldval, uaddr, oparg);
+ break;
+ case FUTEX_OP_OR:
+ __futex_cas_op("or\t%2, %4, %1", ret, oldval, uaddr, oparg);
+ break;
+ case FUTEX_OP_ANDN:
+ __futex_cas_op("and\t%2, %4, %1", ret, oldval, uaddr, oparg);
+ break;
+ case FUTEX_OP_XOR:
+ __futex_cas_op("xor\t%2, %4, %1", ret, oldval, uaddr, oparg);
+ break;
+ default:
+ ret = -ENOSYS;
+ }
+
+ pagefault_enable();
+
+ if (!ret) {
+ switch (cmp) {
+ case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+ case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+ case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+ case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+ case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+ case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+ default: ret = -ENOSYS;
+ }
+ }
+ return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
+{
+ __asm__ __volatile__(
+ "\n1: casa [%3] %%asi, %2, %0\n"
+ "2:\n"
+ " .section .fixup,#alloc,#execinstr\n"
+ " .align 4\n"
+ "3: sethi %%hi(2b), %0\n"
+ " jmpl %0 + %%lo(2b), %%g0\n"
+ " mov %4, %0\n"
+ " .previous\n"
+ " .section __ex_table,\"a\"\n"
+ " .align 4\n"
+ " .word 1b, 3b\n"
+ " .previous\n"
+ : "=r" (newval)
+ : "0" (newval), "r" (oldval), "r" (uaddr), "i" (-EFAULT)
+ : "memory");
+
+ return newval;
+}
+
+#endif /* !(_SPARC64_FUTEX_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_HARDIRQ_H
+#define ___ASM_SPARC_HARDIRQ_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/hardirq_64.h>
+#else
+#include <asm/hardirq_32.h>
+#endif
+#endif
--- /dev/null
+/* hardirq.h: 32-bit Sparc hard IRQ support.
+ *
+ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1998-2000 Anton Blanchard (anton@samba.org)
+ */
+
+#ifndef __SPARC_HARDIRQ_H
+#define __SPARC_HARDIRQ_H
+
+#include <linux/threads.h>
+#include <linux/spinlock.h>
+#include <linux/cache.h>
+
+/* entry.S is sensitive to the offsets of these fields */ /* XXX P3 Is it? */
+typedef struct {
+ unsigned int __softirq_pending;
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
+
+#define HARDIRQ_BITS 8
+
+#endif /* __SPARC_HARDIRQ_H */
--- /dev/null
+/* hardirq.h: 64-bit Sparc hard IRQ support.
+ *
+ * Copyright (C) 1997, 1998, 2005 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef __SPARC64_HARDIRQ_H
+#define __SPARC64_HARDIRQ_H
+
+#include <asm/cpudata.h>
+
+#define __ARCH_IRQ_STAT
+#define local_softirq_pending() \
+ (local_cpu_data().__softirq_pending)
+
+void ack_bad_irq(unsigned int irq);
+
+#define HARDIRQ_BITS 8
+
+#endif /* !(__SPARC64_HARDIRQ_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_HEAD_H
+#define ___ASM_SPARC_HEAD_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/head_64.h>
+#else
+#include <asm/head_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef __SPARC_HEAD_H
+#define __SPARC_HEAD_H
+
+#define KERNBASE 0xf0000000 /* First address the kernel will eventually be */
+#define LOAD_ADDR 0x4000 /* prom jumps to us here unless this is elf /boot */
+#define SUN4C_SEGSZ (1 << 18)
+#define SRMMU_L1_KBASE_OFFSET ((KERNBASE>>24)<<2) /* Used in boot remapping. */
+#define INTS_ENAB 0x01 /* entry.S uses this. */
+
+#define SUN4_PROM_VECTOR 0xFFE81000 /* SUN4 PROM needs to be hardwired */
+
+#define WRITE_PAUSE nop; nop; nop; /* Have to do this after %wim/%psr chg */
+#define NOP_INSN 0x01000000 /* Used to patch sparc_save_state */
+
+/* Here are some trap goodies */
+
+/* Generic trap entry. */
+#define TRAP_ENTRY(type, label) \
+ rd %psr, %l0; b label; rd %wim, %l3; nop;
+
+/* Data/text faults. Defaults to sun4c version at boot time. */
+#define SPARC_TFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 1, %l7;
+#define SPARC_DFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 0, %l7;
+#define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
+#define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
+
+/* This is for traps we should NEVER get. */
+#define BAD_TRAP(num) \
+ rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
+
+/* This is for traps when we want just skip the instruction which caused it */
+#define SKIP_TRAP(type, name) \
+ jmpl %l2, %g0; rett %l2 + 4; nop; nop;
+
+/* Notice that for the system calls we pull a trick. We load up a
+ * different pointer to the system call vector table in %l7, but call
+ * the same generic system call low-level entry point. The trap table
+ * entry sequences are also HyperSparc pipeline friendly ;-)
+ */
+
+/* Software trap for Linux system calls. */
+#define LINUX_SYSCALL_TRAP \
+ sethi %hi(sys_call_table), %l7; \
+ or %l7, %lo(sys_call_table), %l7; \
+ b linux_sparc_syscall; \
+ rd %psr, %l0;
+
+#define BREAKPOINT_TRAP \
+ b breakpoint_trap; \
+ rd %psr,%l0; \
+ nop; \
+ nop;
+
+#ifdef CONFIG_KGDB
+#define KGDB_TRAP(num) \
+ b kgdb_trap_low; \
+ rd %psr,%l0; \
+ nop; \
+ nop;
+#else
+#define KGDB_TRAP(num) \
+ BAD_TRAP(num)
+#endif
+
+/* The Get Condition Codes software trap for userland. */
+#define GETCC_TRAP \
+ b getcc_trap_handler; mov %psr, %l0; nop; nop;
+
+/* The Set Condition Codes software trap for userland. */
+#define SETCC_TRAP \
+ b setcc_trap_handler; mov %psr, %l0; nop; nop;
+
+/* The Get PSR software trap for userland. */
+#define GETPSR_TRAP \
+ mov %psr, %i0; jmp %l2; rett %l2 + 4; nop;
+
+/* This is for hard interrupts from level 1-14, 15 is non-maskable (nmi) and
+ * gets handled with another macro.
+ */
+#define TRAP_ENTRY_INTERRUPT(int_level) \
+ mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
+
+/* NMI's (Non Maskable Interrupts) are special, you can't keep them
+ * from coming in, and basically if you get one, the shows over. ;(
+ * On the sun4c they are usually asynchronous memory errors, on the
+ * the sun4m they could be either due to mem errors or a software
+ * initiated interrupt from the prom/kern on an SMP box saying "I
+ * command you to do CPU tricks, read your mailbox for more info."
+ */
+#define NMI_TRAP \
+ rd %wim, %l3; b linux_trap_nmi_sun4c; mov %psr, %l0; nop;
+
+/* Window overflows/underflows are special and we need to try to be as
+ * efficient as possible here....
+ */
+#define WINDOW_SPILL \
+ rd %psr, %l0; rd %wim, %l3; b spill_window_entry; andcc %l0, PSR_PS, %g0;
+
+#define WINDOW_FILL \
+ rd %psr, %l0; rd %wim, %l3; b fill_window_entry; andcc %l0, PSR_PS, %g0;
+
+#endif /* __SPARC_HEAD_H */
--- /dev/null
+#ifndef _SPARC64_HEAD_H
+#define _SPARC64_HEAD_H
+
+#include <asm/pstate.h>
+
+ /* wrpr %g0, val, %gl */
+#define SET_GL(val) \
+ .word 0xa1902000 | val
+
+ /* rdpr %gl, %gN */
+#define GET_GL_GLOBAL(N) \
+ .word 0x81540000 | (N << 25)
+
+#define KERNBASE 0x400000
+
+#define PTREGS_OFF (STACK_BIAS + STACKFRAME_SZ)
+
+#define __CHEETAH_ID 0x003e0014
+#define __JALAPENO_ID 0x003e0016
+#define __SERRANO_ID 0x003e0022
+
+#define CHEETAH_MANUF 0x003e
+#define CHEETAH_IMPL 0x0014 /* Ultra-III */
+#define CHEETAH_PLUS_IMPL 0x0015 /* Ultra-III+ */
+#define JALAPENO_IMPL 0x0016 /* Ultra-IIIi */
+#define JAGUAR_IMPL 0x0018 /* Ultra-IV */
+#define PANTHER_IMPL 0x0019 /* Ultra-IV+ */
+#define SERRANO_IMPL 0x0022 /* Ultra-IIIi+ */
+
+#define BRANCH_IF_SUN4V(tmp1,label) \
+ sethi %hi(is_sun4v), %tmp1; \
+ lduw [%tmp1 + %lo(is_sun4v)], %tmp1; \
+ brnz,pn %tmp1, label; \
+ nop
+
+#define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \
+ rdpr %ver, %tmp1; \
+ sethi %hi(__CHEETAH_ID), %tmp2; \
+ srlx %tmp1, 32, %tmp1; \
+ or %tmp2, %lo(__CHEETAH_ID), %tmp2;\
+ cmp %tmp1, %tmp2; \
+ be,pn %icc, label; \
+ nop;
+
+#define BRANCH_IF_JALAPENO(tmp1,tmp2,label) \
+ rdpr %ver, %tmp1; \
+ sethi %hi(__JALAPENO_ID), %tmp2; \
+ srlx %tmp1, 32, %tmp1; \
+ or %tmp2, %lo(__JALAPENO_ID), %tmp2;\
+ cmp %tmp1, %tmp2; \
+ be,pn %icc, label; \
+ nop;
+
+#define BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(tmp1,tmp2,label) \
+ rdpr %ver, %tmp1; \
+ srlx %tmp1, (32 + 16), %tmp2; \
+ cmp %tmp2, CHEETAH_MANUF; \
+ bne,pt %xcc, 99f; \
+ sllx %tmp1, 16, %tmp1; \
+ srlx %tmp1, (32 + 16), %tmp2; \
+ cmp %tmp2, CHEETAH_PLUS_IMPL; \
+ bgeu,pt %xcc, label; \
+99: nop;
+
+#define BRANCH_IF_ANY_CHEETAH(tmp1,tmp2,label) \
+ rdpr %ver, %tmp1; \
+ srlx %tmp1, (32 + 16), %tmp2; \
+ cmp %tmp2, CHEETAH_MANUF; \
+ bne,pt %xcc, 99f; \
+ sllx %tmp1, 16, %tmp1; \
+ srlx %tmp1, (32 + 16), %tmp2; \
+ cmp %tmp2, CHEETAH_IMPL; \
+ bgeu,pt %xcc, label; \
+99: nop;
+
+#endif /* !(_SPARC64_HEAD_H) */
--- /dev/null
+/*
+ * highmem.h: virtual kernel memory mappings for high memory
+ *
+ * Used in CONFIG_HIGHMEM systems for memory pages which
+ * are not addressable by direct kernel virtual addresses.
+ *
+ * Copyright (C) 1999 Gerhard Wichert, Siemens AG
+ * Gerhard.Wichert@pdb.siemens.de
+ *
+ *
+ * Redesigned the x86 32-bit VM architecture to deal with
+ * up to 16 Terrabyte physical memory. With current x86 CPUs
+ * we now support up to 64 Gigabytes physical RAM.
+ *
+ * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
+ */
+
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#ifdef __KERNEL__
+
+#include <linux/interrupt.h>
+#include <asm/fixmap.h>
+#include <asm/vaddrs.h>
+#include <asm/kmap_types.h>
+#include <asm/pgtable.h>
+
+/* declarations for highmem.c */
+extern unsigned long highstart_pfn, highend_pfn;
+
+extern pte_t *kmap_pte;
+extern pgprot_t kmap_prot;
+extern pte_t *pkmap_page_table;
+
+extern void kmap_init(void) __init;
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM. Currently the simplest way to do this is to align the
+ * pkmap region on a pagetable boundary (4MB).
+ */
+#define LAST_PKMAP 1024
+#define PKMAP_SIZE (LAST_PKMAP << PAGE_SHIFT)
+#define PKMAP_BASE PMD_ALIGN(SRMMU_NOCACHE_VADDR + (SRMMU_MAX_NOCACHE_PAGES << PAGE_SHIFT))
+
+#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
+#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+
+#define PKMAP_END (PKMAP_ADDR(LAST_PKMAP))
+
+extern void *kmap_high(struct page *page);
+extern void kunmap_high(struct page *page);
+
+static inline void *kmap(struct page *page)
+{
+ BUG_ON(in_interrupt());
+ if (!PageHighMem(page))
+ return page_address(page);
+ return kmap_high(page);
+}
+
+static inline void kunmap(struct page *page)
+{
+ BUG_ON(in_interrupt());
+ if (!PageHighMem(page))
+ return;
+ kunmap_high(page);
+}
+
+extern void *kmap_atomic(struct page *page, enum km_type type);
+extern void kunmap_atomic(void *kvaddr, enum km_type type);
+extern struct page *kmap_atomic_to_page(void *vaddr);
+
+#define flush_cache_kmaps() flush_cache_all()
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_HIGHMEM_H */
--- /dev/null
+#ifndef _ASM_SPARC64_HUGETLB_H
+#define _ASM_SPARC64_HUGETLB_H
+
+#include <asm/page.h>
+
+
+void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte);
+
+pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep);
+
+void hugetlb_prefault_arch_hook(struct mm_struct *mm);
+
+static inline int is_hugepage_only_range(struct mm_struct *mm,
+ unsigned long addr,
+ unsigned long len) {
+ return 0;
+}
+
+/*
+ * If the arch doesn't supply something else, assume that hugepage
+ * size aligned regions are ok without further preparation.
+ */
+static inline int prepare_hugepage_range(struct file *file,
+ unsigned long addr, unsigned long len)
+{
+ if (len & ~HPAGE_MASK)
+ return -EINVAL;
+ if (addr & ~HPAGE_MASK)
+ return -EINVAL;
+ return 0;
+}
+
+static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
+ unsigned long addr, unsigned long end,
+ unsigned long floor,
+ unsigned long ceiling)
+{
+ free_pgd_range(tlb, addr, end, floor, ceiling);
+}
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+ unsigned long addr, pte_t *ptep)
+{
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+ return pte_none(pte);
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+ return pte_wrprotect(pte);
+}
+
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep)
+{
+ ptep_set_wrprotect(mm, addr, ptep);
+}
+
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+ unsigned long addr, pte_t *ptep,
+ pte_t pte, int dirty)
+{
+ return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+ return *ptep;
+}
+
+static inline int arch_prepare_hugepage(struct page *page)
+{
+ return 0;
+}
+
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+
+#endif /* _ASM_SPARC64_HUGETLB_H */
--- /dev/null
+#ifndef _SPARC64_HVTRAP_H
+#define _SPARC64_HVTRAP_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+struct hvtramp_mapping {
+ __u64 vaddr;
+ __u64 tte;
+};
+
+struct hvtramp_descr {
+ __u32 cpu;
+ __u32 num_mappings;
+ __u64 fault_info_va;
+ __u64 fault_info_pa;
+ __u64 thread_reg;
+ struct hvtramp_mapping maps[1];
+};
+
+extern void hv_cpu_startup(unsigned long hvdescr_pa);
+
+#endif
+
+#define HVTRAMP_DESCR_CPU 0x00
+#define HVTRAMP_DESCR_NUM_MAPPINGS 0x04
+#define HVTRAMP_DESCR_FAULT_INFO_VA 0x08
+#define HVTRAMP_DESCR_FAULT_INFO_PA 0x10
+#define HVTRAMP_DESCR_THREAD_REG 0x18
+#define HVTRAMP_DESCR_MAPS 0x20
+
+#define HVTRAMP_MAPPING_VADDR 0x00
+#define HVTRAMP_MAPPING_TTE 0x08
+#define HVTRAMP_MAPPING_SIZE 0x10
+
+#endif /* _SPARC64_HVTRAP_H */
--- /dev/null
+#ifndef __ASM_SPARC_HW_IRQ_H
+#define __ASM_SPARC_HW_IRQ_H
+
+/* Dummy include. */
+
+#endif
--- /dev/null
+#ifndef _SPARC64_HYPERVISOR_H
+#define _SPARC64_HYPERVISOR_H
+
+/* Sun4v hypervisor interfaces and defines.
+ *
+ * Hypervisor calls are made via traps to software traps number 0x80
+ * and above. Registers %o0 to %o5 serve as argument, status, and
+ * return value registers.
+ *
+ * There are two kinds of these traps. First there are the normal
+ * "fast traps" which use software trap 0x80 and encode the function
+ * to invoke by number in register %o5. Argument and return value
+ * handling is as follows:
+ *
+ * -----------------------------------------------
+ * | %o5 | function number | undefined |
+ * | %o0 | argument 0 | return status |
+ * | %o1 | argument 1 | return value 1 |
+ * | %o2 | argument 2 | return value 2 |
+ * | %o3 | argument 3 | return value 3 |
+ * | %o4 | argument 4 | return value 4 |
+ * -----------------------------------------------
+ *
+ * The second type are "hyper-fast traps" which encode the function
+ * number in the software trap number itself. So these use trap
+ * numbers > 0x80. The register usage for hyper-fast traps is as
+ * follows:
+ *
+ * -----------------------------------------------
+ * | %o0 | argument 0 | return status |
+ * | %o1 | argument 1 | return value 1 |
+ * | %o2 | argument 2 | return value 2 |
+ * | %o3 | argument 3 | return value 3 |
+ * | %o4 | argument 4 | return value 4 |
+ * -----------------------------------------------
+ *
+ * Registers providing explicit arguments to the hypervisor calls
+ * are volatile across the call. Upon return their values are
+ * undefined unless explicitly specified as containing a particular
+ * return value by the specific call. The return status is always
+ * returned in register %o0, zero indicates a successful execution of
+ * the hypervisor call and other values indicate an error status as
+ * defined below. So, for example, if a hyper-fast trap takes
+ * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
+ * the call and %o3, %o4, and %o5 would be preserved.
+ *
+ * If the hypervisor trap is invalid, or the fast trap function number
+ * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
+ * of the argument and return values are significant.
+ */
+
+/* Trap numbers. */
+#define HV_FAST_TRAP 0x80
+#define HV_MMU_MAP_ADDR_TRAP 0x83
+#define HV_MMU_UNMAP_ADDR_TRAP 0x84
+#define HV_TTRACE_ADDENTRY_TRAP 0x85
+#define HV_CORE_TRAP 0xff
+
+/* Error codes. */
+#define HV_EOK 0 /* Successful return */
+#define HV_ENOCPU 1 /* Invalid CPU id */
+#define HV_ENORADDR 2 /* Invalid real address */
+#define HV_ENOINTR 3 /* Invalid interrupt id */
+#define HV_EBADPGSZ 4 /* Invalid pagesize encoding */
+#define HV_EBADTSB 5 /* Invalid TSB description */
+#define HV_EINVAL 6 /* Invalid argument */
+#define HV_EBADTRAP 7 /* Invalid function number */
+#define HV_EBADALIGN 8 /* Invalid address alignment */
+#define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */
+#define HV_ENOACCESS 10 /* No access to resource */
+#define HV_EIO 11 /* I/O error */
+#define HV_ECPUERROR 12 /* CPU in error state */
+#define HV_ENOTSUPPORTED 13 /* Function not supported */
+#define HV_ENOMAP 14 /* No mapping found */
+#define HV_ETOOMANY 15 /* Too many items specified */
+#define HV_ECHANNEL 16 /* Invalid LDC channel */
+#define HV_EBUSY 17 /* Resource busy */
+
+/* mach_exit()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MACH_EXIT
+ * ARG0: exit code
+ * ERRORS: This service does not return.
+ *
+ * Stop all CPUs in the virtual domain and place them into the stopped
+ * state. The 64-bit exit code may be passed to a service entity as
+ * the domain's exit status. On systems without a service entity, the
+ * domain will undergo a reset, and the boot firmware will be
+ * reloaded.
+ *
+ * This function will never return to the guest that invokes it.
+ *
+ * Note: By convention an exit code of zero denotes a successful exit by
+ * the guest code. A non-zero exit code denotes a guest specific
+ * error indication.
+ *
+ */
+#define HV_FAST_MACH_EXIT 0x00
+
+#ifndef __ASSEMBLY__
+extern void sun4v_mach_exit(unsigned long exit_code);
+#endif
+
+/* Domain services. */
+
+/* mach_desc()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MACH_DESC
+ * ARG0: buffer
+ * ARG1: length
+ * RET0: status
+ * RET1: length
+ * ERRORS: HV_EBADALIGN Buffer is badly aligned
+ * HV_ENORADDR Buffer is to an illegal real address.
+ * HV_EINVAL Buffer length is too small for complete
+ * machine description.
+ *
+ * Copy the most current machine description into the buffer indicated
+ * by the real address in ARG0. The buffer provided must be 16 byte
+ * aligned. Upon success or HV_EINVAL, this service returns the
+ * actual size of the machine description in the RET1 return value.
+ *
+ * Note: A method of determining the appropriate buffer size for the
+ * machine description is to first call this service with a buffer
+ * length of 0 bytes.
+ */
+#define HV_FAST_MACH_DESC 0x01
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mach_desc(unsigned long buffer_pa,
+ unsigned long buf_len,
+ unsigned long *real_buf_len);
+#endif
+
+/* mach_sir()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MACH_SIR
+ * ERRORS: This service does not return.
+ *
+ * Perform a software initiated reset of the virtual machine domain.
+ * All CPUs are captured as soon as possible, all hardware devices are
+ * returned to the entry default state, and the domain is restarted at
+ * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
+ * of the CPUs. The single CPU restarted is selected as determined by
+ * platform specific policy. Memory is preserved across this
+ * operation.
+ */
+#define HV_FAST_MACH_SIR 0x02
+
+#ifndef __ASSEMBLY__
+extern void sun4v_mach_sir(void);
+#endif
+
+/* mach_set_watchdog()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MACH_SET_WATCHDOG
+ * ARG0: timeout in milliseconds
+ * RET0: status
+ * RET1: time remaining in milliseconds
+ *
+ * A guest uses this API to set a watchdog timer. Once the gues has set
+ * the timer, it must call the timer service again either to disable or
+ * postpone the expiration. If the timer expires before being reset or
+ * disabled, then the hypervisor take a platform specific action leading
+ * to guest termination within a bounded time period. The platform action
+ * may include recovery actions such as reporting the expiration to a
+ * Service Processor, and/or automatically restarting the gues.
+ *
+ * The 'timeout' parameter is specified in milliseconds, however the
+ * implementated granularity is given by the 'watchdog-resolution'
+ * property in the 'platform' node of the guest's machine description.
+ * The largest allowed timeout value is specified by the
+ * 'watchdog-max-timeout' property of the 'platform' node.
+ *
+ * If the 'timeout' argument is not zero, the watchdog timer is set to
+ * expire after a minimum of 'timeout' milliseconds.
+ *
+ * If the 'timeout' argument is zero, the watchdog timer is disabled.
+ *
+ * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
+ * property, the hypervisor leaves the watchdog timer state unchanged,
+ * and returns a status of EINVAL.
+ *
+ * The 'time remaining' return value is valid regardless of whether the
+ * return status is EOK or EINVAL. A non-zero return value indicates the
+ * number of milliseconds that were remaining until the timer was to expire.
+ * If less than one millisecond remains, the return value is '1'. If the
+ * watchdog timer was disabled at the time of the call, the return value is
+ * zero.
+ *
+ * If the hypervisor cannot support the exact timeout value requested, but
+ * can support a larger timeout value, the hypervisor may round the actual
+ * timeout to a value larger than the requested timeout, consequently the
+ * 'time remaining' return value may be larger than the previously requested
+ * timeout value.
+ *
+ * Any guest OS debugger should be aware that the watchdog service may be in
+ * use. Consequently, it is recommended that the watchdog service is
+ * disabled upon debugger entry (e.g. reaching a breakpoint), and then
+ * re-enabled upon returning to normal execution. The API has been designed
+ * with this in mind, and the 'time remaining' result of the disable call may
+ * be used directly as the timeout argument of the re-enable call.
+ */
+#define HV_FAST_MACH_SET_WATCHDOG 0x05
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
+ unsigned long *orig_timeout);
+#endif
+
+/* CPU services.
+ *
+ * CPUs represent devices that can execute software threads. A single
+ * chip that contains multiple cores or strands is represented as
+ * multiple CPUs with unique CPU identifiers. CPUs are exported to
+ * OBP via the machine description (and to the OS via the OBP device
+ * tree). CPUs are always in one of three states: stopped, running,
+ * or error.
+ *
+ * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
+ * CPU within a logical domain. Operations that are to be performed
+ * on multiple CPUs specify them via a CPU list. A CPU list is an
+ * array in real memory, of which each 16-bit word is a CPU ID. CPU
+ * lists are passed through the API as two arguments. The first is
+ * the number of entries (16-bit words) in the CPU list, and the
+ * second is the (real address) pointer to the CPU ID list.
+ */
+
+/* cpu_start()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CPU_START
+ * ARG0: CPU ID
+ * ARG1: PC
+ * ARG2: RTBA
+ * ARG3: target ARG0
+ * RET0: status
+ * ERRORS: ENOCPU Invalid CPU ID
+ * EINVAL Target CPU ID is not in the stopped state
+ * ENORADDR Invalid PC or RTBA real address
+ * EBADALIGN Unaligned PC or unaligned RTBA
+ * EWOULDBLOCK Starting resources are not available
+ *
+ * Start CPU with given CPU ID with PC in %pc and with a real trap
+ * base address value of RTBA. The indicated CPU must be in the
+ * stopped state. The supplied RTBA must be aligned on a 256 byte
+ * boundary. On successful completion, the specified CPU will be in
+ * the running state and will be supplied with "target ARG0" in %o0
+ * and RTBA in %tba.
+ */
+#define HV_FAST_CPU_START 0x10
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_cpu_start(unsigned long cpuid,
+ unsigned long pc,
+ unsigned long rtba,
+ unsigned long arg0);
+#endif
+
+/* cpu_stop()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CPU_STOP
+ * ARG0: CPU ID
+ * RET0: status
+ * ERRORS: ENOCPU Invalid CPU ID
+ * EINVAL Target CPU ID is the current cpu
+ * EINVAL Target CPU ID is not in the running state
+ * EWOULDBLOCK Stopping resources are not available
+ * ENOTSUPPORTED Not supported on this platform
+ *
+ * The specified CPU is stopped. The indicated CPU must be in the
+ * running state. On completion, it will be in the stopped state. It
+ * is not legal to stop the current CPU.
+ *
+ * Note: As this service cannot be used to stop the current cpu, this service
+ * may not be used to stop the last running CPU in a domain. To stop
+ * and exit a running domain, a guest must use the mach_exit() service.
+ */
+#define HV_FAST_CPU_STOP 0x11
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_cpu_stop(unsigned long cpuid);
+#endif
+
+/* cpu_yield()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CPU_YIELD
+ * RET0: status
+ * ERRORS: No possible error.
+ *
+ * Suspend execution on the current CPU. Execution will resume when
+ * an interrupt (device, %stick_compare, or cross-call) is targeted to
+ * the CPU. On some CPUs, this API may be used by the hypervisor to
+ * save power by disabling hardware strands.
+ */
+#define HV_FAST_CPU_YIELD 0x12
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_cpu_yield(void);
+#endif
+
+/* cpu_qconf()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CPU_QCONF
+ * ARG0: queue
+ * ARG1: base real address
+ * ARG2: number of entries
+ * RET0: status
+ * ERRORS: ENORADDR Invalid base real address
+ * EINVAL Invalid queue or number of entries is less
+ * than 2 or too large.
+ * EBADALIGN Base real address is not correctly aligned
+ * for size.
+ *
+ * Configure the given queue to be placed at the given base real
+ * address, with the given number of entries. The number of entries
+ * must be a power of 2. The base real address must be aligned
+ * exactly to match the queue size. Each queue entry is 64 bytes
+ * long, so for example a 32 entry queue must be aligned on a 2048
+ * byte real address boundary.
+ *
+ * The specified queue is unconfigured if the number of entries is given
+ * as zero.
+ *
+ * For the current version of this API service, the argument queue is defined
+ * as follows:
+ *
+ * queue description
+ * ----- -------------------------
+ * 0x3c cpu mondo queue
+ * 0x3d device mondo queue
+ * 0x3e resumable error queue
+ * 0x3f non-resumable error queue
+ *
+ * Note: The maximum number of entries for each queue for a specific cpu may
+ * be determined from the machine description.
+ */
+#define HV_FAST_CPU_QCONF 0x14
+#define HV_CPU_QUEUE_CPU_MONDO 0x3c
+#define HV_CPU_QUEUE_DEVICE_MONDO 0x3d
+#define HV_CPU_QUEUE_RES_ERROR 0x3e
+#define HV_CPU_QUEUE_NONRES_ERROR 0x3f
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_cpu_qconf(unsigned long type,
+ unsigned long queue_paddr,
+ unsigned long num_queue_entries);
+#endif
+
+/* cpu_qinfo()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CPU_QINFO
+ * ARG0: queue
+ * RET0: status
+ * RET1: base real address
+ * RET1: number of entries
+ * ERRORS: EINVAL Invalid queue
+ *
+ * Return the configuration info for the given queue. The base real
+ * address and number of entries of the defined queue are returned.
+ * The queue argument values are the same as for cpu_qconf() above.
+ *
+ * If the specified queue is a valid queue number, but no queue has
+ * been defined, the number of entries will be set to zero and the
+ * base real address returned is undefined.
+ */
+#define HV_FAST_CPU_QINFO 0x15
+
+/* cpu_mondo_send()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CPU_MONDO_SEND
+ * ARG0-1: CPU list
+ * ARG2: data real address
+ * RET0: status
+ * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list
+ * is not 2-byte aligned.
+ * ENORADDR Invalid data mondo address, or invalid cpu list
+ * address.
+ * ENOCPU Invalid cpu in CPU list
+ * EWOULDBLOCK Some or all of the listed CPUs did not receive
+ * the mondo
+ * ECPUERROR One or more of the listed CPUs are in error
+ * state, use HV_FAST_CPU_STATE to see which ones
+ * EINVAL CPU list includes caller's CPU ID
+ *
+ * Send a mondo interrupt to the CPUs in the given CPU list with the
+ * 64-bytes at the given data real address. The data must be 64-byte
+ * aligned. The mondo data will be delivered to the cpu_mondo queues
+ * of the recipient CPUs.
+ *
+ * In all cases, error or not, the CPUs in the CPU list to which the
+ * mondo has been successfully delivered will be indicated by having
+ * their entry in CPU list updated with the value 0xffff.
+ */
+#define HV_FAST_CPU_MONDO_SEND 0x42
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count, unsigned long cpu_list_pa, unsigned long mondo_block_pa);
+#endif
+
+/* cpu_myid()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CPU_MYID
+ * RET0: status
+ * RET1: CPU ID
+ * ERRORS: No errors defined.
+ *
+ * Return the hypervisor ID handle for the current CPU. Use by a
+ * virtual CPU to discover it's own identity.
+ */
+#define HV_FAST_CPU_MYID 0x16
+
+/* cpu_state()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CPU_STATE
+ * ARG0: CPU ID
+ * RET0: status
+ * RET1: state
+ * ERRORS: ENOCPU Invalid CPU ID
+ *
+ * Retrieve the current state of the CPU with the given CPU ID.
+ */
+#define HV_FAST_CPU_STATE 0x17
+#define HV_CPU_STATE_STOPPED 0x01
+#define HV_CPU_STATE_RUNNING 0x02
+#define HV_CPU_STATE_ERROR 0x03
+
+#ifndef __ASSEMBLY__
+extern long sun4v_cpu_state(unsigned long cpuid);
+#endif
+
+/* cpu_set_rtba()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CPU_SET_RTBA
+ * ARG0: RTBA
+ * RET0: status
+ * RET1: previous RTBA
+ * ERRORS: ENORADDR Invalid RTBA real address
+ * EBADALIGN RTBA is incorrectly aligned for a trap table
+ *
+ * Set the real trap base address of the local cpu to the given RTBA.
+ * The supplied RTBA must be aligned on a 256 byte boundary. Upon
+ * success the previous value of the RTBA is returned in RET1.
+ *
+ * Note: This service does not affect %tba
+ */
+#define HV_FAST_CPU_SET_RTBA 0x18
+
+/* cpu_set_rtba()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CPU_GET_RTBA
+ * RET0: status
+ * RET1: previous RTBA
+ * ERRORS: No possible error.
+ *
+ * Returns the current value of RTBA in RET1.
+ */
+#define HV_FAST_CPU_GET_RTBA 0x19
+
+/* MMU services.
+ *
+ * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
+ */
+#ifndef __ASSEMBLY__
+struct hv_tsb_descr {
+ unsigned short pgsz_idx;
+ unsigned short assoc;
+ unsigned int num_ttes; /* in TTEs */
+ unsigned int ctx_idx;
+ unsigned int pgsz_mask;
+ unsigned long tsb_base;
+ unsigned long resv;
+};
+#endif
+#define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00
+#define HV_TSB_DESCR_ASSOC_OFFSET 0x02
+#define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04
+#define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08
+#define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c
+#define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10
+#define HV_TSB_DESCR_RESV_OFFSET 0x18
+
+/* Page size bitmask. */
+#define HV_PGSZ_MASK_8K (1 << 0)
+#define HV_PGSZ_MASK_64K (1 << 1)
+#define HV_PGSZ_MASK_512K (1 << 2)
+#define HV_PGSZ_MASK_4MB (1 << 3)
+#define HV_PGSZ_MASK_32MB (1 << 4)
+#define HV_PGSZ_MASK_256MB (1 << 5)
+#define HV_PGSZ_MASK_2GB (1 << 6)
+#define HV_PGSZ_MASK_16GB (1 << 7)
+
+/* Page size index. The value given in the TSB descriptor must correspond
+ * to the smallest page size specified in the pgsz_mask page size bitmask.
+ */
+#define HV_PGSZ_IDX_8K 0
+#define HV_PGSZ_IDX_64K 1
+#define HV_PGSZ_IDX_512K 2
+#define HV_PGSZ_IDX_4MB 3
+#define HV_PGSZ_IDX_32MB 4
+#define HV_PGSZ_IDX_256MB 5
+#define HV_PGSZ_IDX_2GB 6
+#define HV_PGSZ_IDX_16GB 7
+
+/* MMU fault status area.
+ *
+ * MMU related faults have their status and fault address information
+ * placed into a memory region made available by privileged code. Each
+ * virtual processor must make a mmu_fault_area_conf() call to tell the
+ * hypervisor where that processor's fault status should be stored.
+ *
+ * The fault status block is a multiple of 64-bytes and must be aligned
+ * on a 64-byte boundary.
+ */
+#ifndef __ASSEMBLY__
+struct hv_fault_status {
+ unsigned long i_fault_type;
+ unsigned long i_fault_addr;
+ unsigned long i_fault_ctx;
+ unsigned long i_reserved[5];
+ unsigned long d_fault_type;
+ unsigned long d_fault_addr;
+ unsigned long d_fault_ctx;
+ unsigned long d_reserved[5];
+};
+#endif
+#define HV_FAULT_I_TYPE_OFFSET 0x00
+#define HV_FAULT_I_ADDR_OFFSET 0x08
+#define HV_FAULT_I_CTX_OFFSET 0x10
+#define HV_FAULT_D_TYPE_OFFSET 0x40
+#define HV_FAULT_D_ADDR_OFFSET 0x48
+#define HV_FAULT_D_CTX_OFFSET 0x50
+
+#define HV_FAULT_TYPE_FAST_MISS 1
+#define HV_FAULT_TYPE_FAST_PROT 2
+#define HV_FAULT_TYPE_MMU_MISS 3
+#define HV_FAULT_TYPE_INV_RA 4
+#define HV_FAULT_TYPE_PRIV_VIOL 5
+#define HV_FAULT_TYPE_PROT_VIOL 6
+#define HV_FAULT_TYPE_NFO 7
+#define HV_FAULT_TYPE_NFO_SEFF 8
+#define HV_FAULT_TYPE_INV_VA 9
+#define HV_FAULT_TYPE_INV_ASI 10
+#define HV_FAULT_TYPE_NC_ATOMIC 11
+#define HV_FAULT_TYPE_PRIV_ACT 12
+#define HV_FAULT_TYPE_RESV1 13
+#define HV_FAULT_TYPE_UNALIGNED 14
+#define HV_FAULT_TYPE_INV_PGSZ 15
+/* Values 16 --> -2 are reserved. */
+#define HV_FAULT_TYPE_MULTIPLE -1
+
+/* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
+ * and mmu_{map,unmap}_perm_addr().
+ */
+#define HV_MMU_DMMU 0x01
+#define HV_MMU_IMMU 0x02
+#define HV_MMU_ALL (HV_MMU_DMMU | HV_MMU_IMMU)
+
+/* mmu_map_addr()
+ * TRAP: HV_MMU_MAP_ADDR_TRAP
+ * ARG0: virtual address
+ * ARG1: mmu context
+ * ARG2: TTE
+ * ARG3: flags (HV_MMU_{IMMU,DMMU})
+ * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
+ * EBADPGSZ Invalid page size value
+ * ENORADDR Invalid real address in TTE
+ *
+ * Create a non-permanent mapping using the given TTE, virtual
+ * address, and mmu context. The flags argument determines which
+ * (data, or instruction, or both) TLB the mapping gets loaded into.
+ *
+ * The behavior is undefined if the valid bit is clear in the TTE.
+ *
+ * Note: This API call is for privileged code to specify temporary translation
+ * mappings without the need to create and manage a TSB.
+ */
+
+/* mmu_unmap_addr()
+ * TRAP: HV_MMU_UNMAP_ADDR_TRAP
+ * ARG0: virtual address
+ * ARG1: mmu context
+ * ARG2: flags (HV_MMU_{IMMU,DMMU})
+ * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
+ *
+ * Demaps the given virtual address in the given mmu context on this
+ * CPU. This function is intended to be used to demap pages mapped
+ * with mmu_map_addr. This service is equivalent to invoking
+ * mmu_demap_page() with only the current CPU in the CPU list. The
+ * flags argument determines which (data, or instruction, or both) TLB
+ * the mapping gets unmapped from.
+ *
+ * Attempting to perform an unmap operation for a previously defined
+ * permanent mapping will have undefined results.
+ */
+
+/* mmu_tsb_ctx0()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMU_TSB_CTX0
+ * ARG0: number of TSB descriptions
+ * ARG1: TSB descriptions pointer
+ * RET0: status
+ * ERRORS: ENORADDR Invalid TSB descriptions pointer or
+ * TSB base within a descriptor
+ * EBADALIGN TSB descriptions pointer is not aligned
+ * to an 8-byte boundary, or TSB base
+ * within a descriptor is not aligned for
+ * the given TSB size
+ * EBADPGSZ Invalid page size in a TSB descriptor
+ * EBADTSB Invalid associativity or size in a TSB
+ * descriptor
+ * EINVAL Invalid number of TSB descriptions, or
+ * invalid context index in a TSB
+ * descriptor, or index page size not
+ * equal to smallest page size in page
+ * size bitmask field.
+ *
+ * Configures the TSBs for the current CPU for virtual addresses with
+ * context zero. The TSB descriptions pointer is a pointer to an
+ * array of the given number of TSB descriptions.
+ *
+ * Note: The maximum number of TSBs available to a virtual CPU is given by the
+ * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
+ * machine description.
+ */
+#define HV_FAST_MMU_TSB_CTX0 0x20
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
+ unsigned long tsb_desc_ra);
+#endif
+
+/* mmu_tsb_ctxnon0()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMU_TSB_CTXNON0
+ * ARG0: number of TSB descriptions
+ * ARG1: TSB descriptions pointer
+ * RET0: status
+ * ERRORS: Same as for mmu_tsb_ctx0() above.
+ *
+ * Configures the TSBs for the current CPU for virtual addresses with
+ * non-zero contexts. The TSB descriptions pointer is a pointer to an
+ * array of the given number of TSB descriptions.
+ *
+ * Note: A maximum of 16 TSBs may be specified in the TSB description list.
+ */
+#define HV_FAST_MMU_TSB_CTXNON0 0x21
+
+/* mmu_demap_page()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMU_DEMAP_PAGE
+ * ARG0: reserved, must be zero
+ * ARG1: reserved, must be zero
+ * ARG2: virtual address
+ * ARG3: mmu context
+ * ARG4: flags (HV_MMU_{IMMU,DMMU})
+ * RET0: status
+ * ERRORS: EINVAL Invalid virutal address, context, or
+ * flags value
+ * ENOTSUPPORTED ARG0 or ARG1 is non-zero
+ *
+ * Demaps any page mapping of the given virtual address in the given
+ * mmu context for the current virtual CPU. Any virtually tagged
+ * caches are guaranteed to be kept consistent. The flags argument
+ * determines which TLB (instruction, or data, or both) participate in
+ * the operation.
+ *
+ * ARG0 and ARG1 are both reserved and must be set to zero.
+ */
+#define HV_FAST_MMU_DEMAP_PAGE 0x22
+
+/* mmu_demap_ctx()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMU_DEMAP_CTX
+ * ARG0: reserved, must be zero
+ * ARG1: reserved, must be zero
+ * ARG2: mmu context
+ * ARG3: flags (HV_MMU_{IMMU,DMMU})
+ * RET0: status
+ * ERRORS: EINVAL Invalid context or flags value
+ * ENOTSUPPORTED ARG0 or ARG1 is non-zero
+ *
+ * Demaps all non-permanent virtual page mappings previously specified
+ * for the given context for the current virtual CPU. Any virtual
+ * tagged caches are guaranteed to be kept consistent. The flags
+ * argument determines which TLB (instruction, or data, or both)
+ * participate in the operation.
+ *
+ * ARG0 and ARG1 are both reserved and must be set to zero.
+ */
+#define HV_FAST_MMU_DEMAP_CTX 0x23
+
+/* mmu_demap_all()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMU_DEMAP_ALL
+ * ARG0: reserved, must be zero
+ * ARG1: reserved, must be zero
+ * ARG2: flags (HV_MMU_{IMMU,DMMU})
+ * RET0: status
+ * ERRORS: EINVAL Invalid flags value
+ * ENOTSUPPORTED ARG0 or ARG1 is non-zero
+ *
+ * Demaps all non-permanent virtual page mappings previously specified
+ * for the current virtual CPU. Any virtual tagged caches are
+ * guaranteed to be kept consistent. The flags argument determines
+ * which TLB (instruction, or data, or both) participate in the
+ * operation.
+ *
+ * ARG0 and ARG1 are both reserved and must be set to zero.
+ */
+#define HV_FAST_MMU_DEMAP_ALL 0x24
+
+#ifndef __ASSEMBLY__
+extern void sun4v_mmu_demap_all(void);
+#endif
+
+/* mmu_map_perm_addr()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMU_MAP_PERM_ADDR
+ * ARG0: virtual address
+ * ARG1: reserved, must be zero
+ * ARG2: TTE
+ * ARG3: flags (HV_MMU_{IMMU,DMMU})
+ * RET0: status
+ * ERRORS: EINVAL Invalid virutal address or flags value
+ * EBADPGSZ Invalid page size value
+ * ENORADDR Invalid real address in TTE
+ * ETOOMANY Too many mappings (max of 8 reached)
+ *
+ * Create a permanent mapping using the given TTE and virtual address
+ * for context 0 on the calling virtual CPU. A maximum of 8 such
+ * permanent mappings may be specified by privileged code. Mappings
+ * may be removed with mmu_unmap_perm_addr().
+ *
+ * The behavior is undefined if a TTE with the valid bit clear is given.
+ *
+ * Note: This call is used to specify address space mappings for which
+ * privileged code does not expect to receive misses. For example,
+ * this mechanism can be used to map kernel nucleus code and data.
+ */
+#define HV_FAST_MMU_MAP_PERM_ADDR 0x25
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
+ unsigned long set_to_zero,
+ unsigned long tte,
+ unsigned long flags);
+#endif
+
+/* mmu_fault_area_conf()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF
+ * ARG0: real address
+ * RET0: status
+ * RET1: previous mmu fault area real address
+ * ERRORS: ENORADDR Invalid real address
+ * EBADALIGN Invalid alignment for fault area
+ *
+ * Configure the MMU fault status area for the calling CPU. A 64-byte
+ * aligned real address specifies where MMU fault status information
+ * is placed. The return value is the previously specified area, or 0
+ * for the first invocation. Specifying a fault area at real address
+ * 0 is not allowed.
+ */
+#define HV_FAST_MMU_FAULT_AREA_CONF 0x26
+
+/* mmu_enable()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMU_ENABLE
+ * ARG0: enable flag
+ * ARG1: return target address
+ * RET0: status
+ * ERRORS: ENORADDR Invalid real address when disabling
+ * translation.
+ * EBADALIGN The return target address is not
+ * aligned to an instruction.
+ * EINVAL The enable flag request the current
+ * operating mode (e.g. disable if already
+ * disabled)
+ *
+ * Enable or disable virtual address translation for the calling CPU
+ * within the virtual machine domain. If the enable flag is zero,
+ * translation is disabled, any non-zero value will enable
+ * translation.
+ *
+ * When this function returns, the newly selected translation mode
+ * will be active. If the mmu is being enabled, then the return
+ * target address is a virtual address else it is a real address.
+ *
+ * Upon successful completion, control will be returned to the given
+ * return target address (ie. the cpu will jump to that address). On
+ * failure, the previous mmu mode remains and the trap simply returns
+ * as normal with the appropriate error code in RET0.
+ */
+#define HV_FAST_MMU_ENABLE 0x27
+
+/* mmu_unmap_perm_addr()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMU_UNMAP_PERM_ADDR
+ * ARG0: virtual address
+ * ARG1: reserved, must be zero
+ * ARG2: flags (HV_MMU_{IMMU,DMMU})
+ * RET0: status
+ * ERRORS: EINVAL Invalid virutal address or flags value
+ * ENOMAP Specified mapping was not found
+ *
+ * Demaps any permanent page mapping (established via
+ * mmu_map_perm_addr()) at the given virtual address for context 0 on
+ * the current virtual CPU. Any virtual tagged caches are guaranteed
+ * to be kept consistent.
+ */
+#define HV_FAST_MMU_UNMAP_PERM_ADDR 0x28
+
+/* mmu_tsb_ctx0_info()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMU_TSB_CTX0_INFO
+ * ARG0: max TSBs
+ * ARG1: buffer pointer
+ * RET0: status
+ * RET1: number of TSBs
+ * ERRORS: EINVAL Supplied buffer is too small
+ * EBADALIGN The buffer pointer is badly aligned
+ * ENORADDR Invalid real address for buffer pointer
+ *
+ * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
+ * into the provided buffer. The size of the buffer is given in ARG1
+ * in terms of the number of TSB description entries.
+ *
+ * Upon return, RET1 always contains the number of TSB descriptions
+ * previously configured. If zero TSBs were configured, EOK is
+ * returned with RET1 containing 0.
+ */
+#define HV_FAST_MMU_TSB_CTX0_INFO 0x29
+
+/* mmu_tsb_ctxnon0_info()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMU_TSB_CTXNON0_INFO
+ * ARG0: max TSBs
+ * ARG1: buffer pointer
+ * RET0: status
+ * RET1: number of TSBs
+ * ERRORS: EINVAL Supplied buffer is too small
+ * EBADALIGN The buffer pointer is badly aligned
+ * ENORADDR Invalid real address for buffer pointer
+ *
+ * Return the TSB configuration as previous defined by
+ * mmu_tsb_ctxnon0() into the provided buffer. The size of the buffer
+ * is given in ARG1 in terms of the number of TSB description entries.
+ *
+ * Upon return, RET1 always contains the number of TSB descriptions
+ * previously configured. If zero TSBs were configured, EOK is
+ * returned with RET1 containing 0.
+ */
+#define HV_FAST_MMU_TSB_CTXNON0_INFO 0x2a
+
+/* mmu_fault_area_info()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMU_FAULT_AREA_INFO
+ * RET0: status
+ * RET1: fault area real address
+ * ERRORS: No errors defined.
+ *
+ * Return the currently defined MMU fault status area for the current
+ * CPU. The real address of the fault status area is returned in
+ * RET1, or 0 is returned in RET1 if no fault status area is defined.
+ *
+ * Note: mmu_fault_area_conf() may be called with the return value (RET1)
+ * from this service if there is a need to save and restore the fault
+ * area for a cpu.
+ */
+#define HV_FAST_MMU_FAULT_AREA_INFO 0x2b
+
+/* Cache and Memory services. */
+
+/* mem_scrub()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MEM_SCRUB
+ * ARG0: real address
+ * ARG1: length
+ * RET0: status
+ * RET1: length scrubbed
+ * ERRORS: ENORADDR Invalid real address
+ * EBADALIGN Start address or length are not correctly
+ * aligned
+ * EINVAL Length is zero
+ *
+ * Zero the memory contents in the range real address to real address
+ * plus length minus 1. Also, valid ECC will be generated for that
+ * memory address range. Scrubbing is started at the given real
+ * address, but may not scrub the entire given length. The actual
+ * length scrubbed will be returned in RET1.
+ *
+ * The real address and length must be aligned on an 8K boundary, or
+ * contain the start address and length from a sun4v error report.
+ *
+ * Note: There are two uses for this function. The first use is to block clear
+ * and initialize memory and the second is to scrub an u ncorrectable
+ * error reported via a resumable or non-resumable trap. The second
+ * use requires the arguments to be equal to the real address and length
+ * provided in a sun4v memory error report.
+ */
+#define HV_FAST_MEM_SCRUB 0x31
+
+/* mem_sync()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MEM_SYNC
+ * ARG0: real address
+ * ARG1: length
+ * RET0: status
+ * RET1: length synced
+ * ERRORS: ENORADDR Invalid real address
+ * EBADALIGN Start address or length are not correctly
+ * aligned
+ * EINVAL Length is zero
+ *
+ * Force the next access within the real address to real address plus
+ * length minus 1 to be fetches from main system memory. Less than
+ * the given length may be synced, the actual amount synced is
+ * returned in RET1. The real address and length must be aligned on
+ * an 8K boundary.
+ */
+#define HV_FAST_MEM_SYNC 0x32
+
+/* Time of day services.
+ *
+ * The hypervisor maintains the time of day on a per-domain basis.
+ * Changing the time of day in one domain does not affect the time of
+ * day on any other domain.
+ *
+ * Time is described by a single unsigned 64-bit word which is the
+ * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
+ * 1970).
+ */
+
+/* tod_get()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_TOD_GET
+ * RET0: status
+ * RET1: TOD
+ * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
+ * ENOTSUPPORTED If TOD not supported on this platform
+ *
+ * Return the current time of day. May block if TOD access is
+ * temporarily not possible.
+ */
+#define HV_FAST_TOD_GET 0x50
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_tod_get(unsigned long *time);
+#endif
+
+/* tod_set()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_TOD_SET
+ * ARG0: TOD
+ * RET0: status
+ * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
+ * ENOTSUPPORTED If TOD not supported on this platform
+ *
+ * The current time of day is set to the value specified in ARG0. May
+ * block if TOD access is temporarily not possible.
+ */
+#define HV_FAST_TOD_SET 0x51
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_tod_set(unsigned long time);
+#endif
+
+/* Console services */
+
+/* con_getchar()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CONS_GETCHAR
+ * RET0: status
+ * RET1: character
+ * ERRORS: EWOULDBLOCK No character available.
+ *
+ * Returns a character from the console device. If no character is
+ * available then an EWOULDBLOCK error is returned. If a character is
+ * available, then the returned status is EOK and the character value
+ * is in RET1.
+ *
+ * A virtual BREAK is represented by the 64-bit value -1.
+ *
+ * A virtual HUP signal is represented by the 64-bit value -2.
+ */
+#define HV_FAST_CONS_GETCHAR 0x60
+
+/* con_putchar()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CONS_PUTCHAR
+ * ARG0: character
+ * RET0: status
+ * ERRORS: EINVAL Illegal character
+ * EWOULDBLOCK Output buffer currently full, would block
+ *
+ * Send a character to the console device. Only character values
+ * between 0 and 255 may be used. Values outside this range are
+ * invalid except for the 64-bit value -1 which is used to send a
+ * virtual BREAK.
+ */
+#define HV_FAST_CONS_PUTCHAR 0x61
+
+/* con_read()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CONS_READ
+ * ARG0: buffer real address
+ * ARG1: buffer size in bytes
+ * RET0: status
+ * RET1: bytes read or BREAK or HUP
+ * ERRORS: EWOULDBLOCK No character available.
+ *
+ * Reads characters into a buffer from the console device. If no
+ * character is available then an EWOULDBLOCK error is returned.
+ * If a character is available, then the returned status is EOK
+ * and the number of bytes read into the given buffer is provided
+ * in RET1.
+ *
+ * A virtual BREAK is represented by the 64-bit RET1 value -1.
+ *
+ * A virtual HUP signal is represented by the 64-bit RET1 value -2.
+ *
+ * If BREAK or HUP are indicated, no bytes were read into buffer.
+ */
+#define HV_FAST_CONS_READ 0x62
+
+/* con_write()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_CONS_WRITE
+ * ARG0: buffer real address
+ * ARG1: buffer size in bytes
+ * RET0: status
+ * RET1: bytes written
+ * ERRORS: EWOULDBLOCK Output buffer currently full, would block
+ *
+ * Send a characters in buffer to the console device. Breaks must be
+ * sent using con_putchar().
+ */
+#define HV_FAST_CONS_WRITE 0x63
+
+#ifndef __ASSEMBLY__
+extern long sun4v_con_getchar(long *status);
+extern long sun4v_con_putchar(long c);
+extern long sun4v_con_read(unsigned long buffer,
+ unsigned long size,
+ unsigned long *bytes_read);
+extern unsigned long sun4v_con_write(unsigned long buffer,
+ unsigned long size,
+ unsigned long *bytes_written);
+#endif
+
+/* mach_set_soft_state()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
+ * ARG0: software state
+ * ARG1: software state description pointer
+ * RET0: status
+ * ERRORS: EINVAL software state not valid or software state
+ * description is not NULL terminated
+ * ENORADDR software state description pointer is not a
+ * valid real address
+ * EBADALIGNED software state description is not correctly
+ * aligned
+ *
+ * This allows the guest to report it's soft state to the hypervisor. There
+ * are two primary components to this state. The first part states whether
+ * the guest software is running or not. The second containts optional
+ * details specific to the software.
+ *
+ * The software state argument is defined below in HV_SOFT_STATE_*, and
+ * indicates whether the guest is operating normally or in a transitional
+ * state.
+ *
+ * The software state description argument is a real address of a data buffer
+ * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
+ * terminated 7-bit ASCII string of up to 31 characters not including the
+ * NULL termination.
+ */
+#define HV_FAST_MACH_SET_SOFT_STATE 0x70
+#define HV_SOFT_STATE_NORMAL 0x01
+#define HV_SOFT_STATE_TRANSITION 0x02
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
+ unsigned long msg_string_ra);
+#endif
+
+/* mach_get_soft_state()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
+ * ARG0: software state description pointer
+ * RET0: status
+ * RET1: software state
+ * ERRORS: ENORADDR software state description pointer is not a
+ * valid real address
+ * EBADALIGNED software state description is not correctly
+ * aligned
+ *
+ * Retrieve the current value of the guest's software state. The rules
+ * for the software state pointer are the same as for mach_set_soft_state()
+ * above.
+ */
+#define HV_FAST_MACH_GET_SOFT_STATE 0x71
+
+/* svc_send()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_SVC_SEND
+ * ARG0: service ID
+ * ARG1: buffer real address
+ * ARG2: buffer size
+ * RET0: STATUS
+ * RET1: sent_bytes
+ *
+ * Be careful, all output registers are clobbered by this operation,
+ * so for example it is not possible to save away a value in %o4
+ * across the trap.
+ */
+#define HV_FAST_SVC_SEND 0x80
+
+/* svc_recv()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_SVC_RECV
+ * ARG0: service ID
+ * ARG1: buffer real address
+ * ARG2: buffer size
+ * RET0: STATUS
+ * RET1: recv_bytes
+ *
+ * Be careful, all output registers are clobbered by this operation,
+ * so for example it is not possible to save away a value in %o4
+ * across the trap.
+ */
+#define HV_FAST_SVC_RECV 0x81
+
+/* svc_getstatus()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_SVC_GETSTATUS
+ * ARG0: service ID
+ * RET0: STATUS
+ * RET1: status bits
+ */
+#define HV_FAST_SVC_GETSTATUS 0x82
+
+/* svc_setstatus()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_SVC_SETSTATUS
+ * ARG0: service ID
+ * ARG1: bits to set
+ * RET0: STATUS
+ */
+#define HV_FAST_SVC_SETSTATUS 0x83
+
+/* svc_clrstatus()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_SVC_CLRSTATUS
+ * ARG0: service ID
+ * ARG1: bits to clear
+ * RET0: STATUS
+ */
+#define HV_FAST_SVC_CLRSTATUS 0x84
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_svc_send(unsigned long svc_id,
+ unsigned long buffer,
+ unsigned long buffer_size,
+ unsigned long *sent_bytes);
+extern unsigned long sun4v_svc_recv(unsigned long svc_id,
+ unsigned long buffer,
+ unsigned long buffer_size,
+ unsigned long *recv_bytes);
+extern unsigned long sun4v_svc_getstatus(unsigned long svc_id,
+ unsigned long *status_bits);
+extern unsigned long sun4v_svc_setstatus(unsigned long svc_id,
+ unsigned long status_bits);
+extern unsigned long sun4v_svc_clrstatus(unsigned long svc_id,
+ unsigned long status_bits);
+#endif
+
+/* Trap trace services.
+ *
+ * The hypervisor provides a trap tracing capability for privileged
+ * code running on each virtual CPU. Privileged code provides a
+ * round-robin trap trace queue within which the hypervisor writes
+ * 64-byte entries detailing hyperprivileged traps taken n behalf of
+ * privileged code. This is provided as a debugging capability for
+ * privileged code.
+ *
+ * The trap trace control structure is 64-bytes long and placed at the
+ * start (offset 0) of the trap trace buffer, and is described as
+ * follows:
+ */
+#ifndef __ASSEMBLY__
+struct hv_trap_trace_control {
+ unsigned long head_offset;
+ unsigned long tail_offset;
+ unsigned long __reserved[0x30 / sizeof(unsigned long)];
+};
+#endif
+#define HV_TRAP_TRACE_CTRL_HEAD_OFFSET 0x00
+#define HV_TRAP_TRACE_CTRL_TAIL_OFFSET 0x08
+
+/* The head offset is the offset of the most recently completed entry
+ * in the trap-trace buffer. The tail offset is the offset of the
+ * next entry to be written. The control structure is owned and
+ * modified by the hypervisor. A guest may not modify the control
+ * structure contents. Attempts to do so will result in undefined
+ * behavior for the guest.
+ *
+ * Each trap trace buffer entry is layed out as follows:
+ */
+#ifndef __ASSEMBLY__
+struct hv_trap_trace_entry {
+ unsigned char type; /* Hypervisor or guest entry? */
+ unsigned char hpstate; /* Hyper-privileged state */
+ unsigned char tl; /* Trap level */
+ unsigned char gl; /* Global register level */
+ unsigned short tt; /* Trap type */
+ unsigned short tag; /* Extended trap identifier */
+ unsigned long tstate; /* Trap state */
+ unsigned long tick; /* Tick */
+ unsigned long tpc; /* Trap PC */
+ unsigned long f1; /* Entry specific */
+ unsigned long f2; /* Entry specific */
+ unsigned long f3; /* Entry specific */
+ unsigned long f4; /* Entry specific */
+};
+#endif
+#define HV_TRAP_TRACE_ENTRY_TYPE 0x00
+#define HV_TRAP_TRACE_ENTRY_HPSTATE 0x01
+#define HV_TRAP_TRACE_ENTRY_TL 0x02
+#define HV_TRAP_TRACE_ENTRY_GL 0x03
+#define HV_TRAP_TRACE_ENTRY_TT 0x04
+#define HV_TRAP_TRACE_ENTRY_TAG 0x06
+#define HV_TRAP_TRACE_ENTRY_TSTATE 0x08
+#define HV_TRAP_TRACE_ENTRY_TICK 0x10
+#define HV_TRAP_TRACE_ENTRY_TPC 0x18
+#define HV_TRAP_TRACE_ENTRY_F1 0x20
+#define HV_TRAP_TRACE_ENTRY_F2 0x28
+#define HV_TRAP_TRACE_ENTRY_F3 0x30
+#define HV_TRAP_TRACE_ENTRY_F4 0x38
+
+/* The type field is encoded as follows. */
+#define HV_TRAP_TYPE_UNDEF 0x00 /* Entry content undefined */
+#define HV_TRAP_TYPE_HV 0x01 /* Hypervisor trap entry */
+#define HV_TRAP_TYPE_GUEST 0xff /* Added via ttrace_addentry() */
+
+/* ttrace_buf_conf()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_TTRACE_BUF_CONF
+ * ARG0: real address
+ * ARG1: number of entries
+ * RET0: status
+ * RET1: number of entries
+ * ERRORS: ENORADDR Invalid real address
+ * EINVAL Size is too small
+ * EBADALIGN Real address not aligned on 64-byte boundary
+ *
+ * Requests hypervisor trap tracing and declares a virtual CPU's trap
+ * trace buffer to the hypervisor. The real address supplies the real
+ * base address of the trap trace queue and must be 64-byte aligned.
+ * Specifying a value of 0 for the number of entries disables trap
+ * tracing for the calling virtual CPU. The buffer allocated must be
+ * sized for a power of two number of 64-byte trap trace entries plus
+ * an initial 64-byte control structure.
+ *
+ * This may be invoked any number of times so that a virtual CPU may
+ * relocate a trap trace buffer or create "snapshots" of information.
+ *
+ * If the real address is illegal or badly aligned, then trap tracing
+ * is disabled and an error is returned.
+ *
+ * Upon failure with EINVAL, this service call returns in RET1 the
+ * minimum number of buffer entries required. Upon other failures
+ * RET1 is undefined.
+ */
+#define HV_FAST_TTRACE_BUF_CONF 0x90
+
+/* ttrace_buf_info()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_TTRACE_BUF_INFO
+ * RET0: status
+ * RET1: real address
+ * RET2: size
+ * ERRORS: None defined.
+ *
+ * Returns the size and location of the previously declared trap-trace
+ * buffer. In the event that no buffer was previously defined, or the
+ * buffer is disabled, this call will return a size of zero bytes.
+ */
+#define HV_FAST_TTRACE_BUF_INFO 0x91
+
+/* ttrace_enable()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_TTRACE_ENABLE
+ * ARG0: enable
+ * RET0: status
+ * RET1: previous enable state
+ * ERRORS: EINVAL No trap trace buffer currently defined
+ *
+ * Enable or disable trap tracing, and return the previous enabled
+ * state in RET1. Future systems may define various flags for the
+ * enable argument (ARG0), for the moment a guest should pass
+ * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
+ * tracing - which will ensure future compatability.
+ */
+#define HV_FAST_TTRACE_ENABLE 0x92
+
+/* ttrace_freeze()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_TTRACE_FREEZE
+ * ARG0: freeze
+ * RET0: status
+ * RET1: previous freeze state
+ * ERRORS: EINVAL No trap trace buffer currently defined
+ *
+ * Freeze or unfreeze trap tracing, returning the previous freeze
+ * state in RET1. A guest should pass a non-zero value to freeze and
+ * a zero value to unfreeze all tracing. The returned previous state
+ * is 0 for not frozen and 1 for frozen.
+ */
+#define HV_FAST_TTRACE_FREEZE 0x93
+
+/* ttrace_addentry()
+ * TRAP: HV_TTRACE_ADDENTRY_TRAP
+ * ARG0: tag (16-bits)
+ * ARG1: data word 0
+ * ARG2: data word 1
+ * ARG3: data word 2
+ * ARG4: data word 3
+ * RET0: status
+ * ERRORS: EINVAL No trap trace buffer currently defined
+ *
+ * Add an entry to the trap trace buffer. Upon return only ARG0/RET0
+ * is modified - none of the other registers holding arguments are
+ * volatile across this hypervisor service.
+ */
+
+/* Core dump services.
+ *
+ * Since the hypervisor viraulizes and thus obscures a lot of the
+ * physical machine layout and state, traditional OS crash dumps can
+ * be difficult to diagnose especially when the problem is a
+ * configuration error of some sort.
+ *
+ * The dump services provide an opaque buffer into which the
+ * hypervisor can place it's internal state in order to assist in
+ * debugging such situations. The contents are opaque and extremely
+ * platform and hypervisor implementation specific. The guest, during
+ * a core dump, requests that the hypervisor update any information in
+ * the dump buffer in preparation to being dumped as part of the
+ * domain's memory image.
+ */
+
+/* dump_buf_update()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_DUMP_BUF_UPDATE
+ * ARG0: real address
+ * ARG1: size
+ * RET0: status
+ * RET1: required size of dump buffer
+ * ERRORS: ENORADDR Invalid real address
+ * EBADALIGN Real address is not aligned on a 64-byte
+ * boundary
+ * EINVAL Size is non-zero but less than minimum size
+ * required
+ * ENOTSUPPORTED Operation not supported on current logical
+ * domain
+ *
+ * Declare a domain dump buffer to the hypervisor. The real address
+ * provided for the domain dump buffer must be 64-byte aligned. The
+ * size specifies the size of the dump buffer and may be larger than
+ * the minimum size specified in the machine description. The
+ * hypervisor will fill the dump buffer with opaque data.
+ *
+ * Note: A guest may elect to include dump buffer contents as part of a crash
+ * dump to assist with debugging. This function may be called any number
+ * of times so that a guest may relocate a dump buffer, or create
+ * "snapshots" of any dump-buffer information. Each call to
+ * dump_buf_update() atomically declares the new dump buffer to the
+ * hypervisor.
+ *
+ * A specified size of 0 unconfigures the dump buffer. If the real
+ * address is illegal or badly aligned, then any currently active dump
+ * buffer is disabled and an error is returned.
+ *
+ * In the event that the call fails with EINVAL, RET1 contains the
+ * minimum size requires by the hypervisor for a valid dump buffer.
+ */
+#define HV_FAST_DUMP_BUF_UPDATE 0x94
+
+/* dump_buf_info()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_DUMP_BUF_INFO
+ * RET0: status
+ * RET1: real address of current dump buffer
+ * RET2: size of current dump buffer
+ * ERRORS: No errors defined.
+ *
+ * Return the currently configures dump buffer description. A
+ * returned size of 0 bytes indicates an undefined dump buffer. In
+ * this case the return address in RET1 is undefined.
+ */
+#define HV_FAST_DUMP_BUF_INFO 0x95
+
+/* Device interrupt services.
+ *
+ * Device interrupts are allocated to system bus bridges by the hypervisor,
+ * and described to OBP in the machine description. OBP then describes
+ * these interrupts to the OS via properties in the device tree.
+ *
+ * Terminology:
+ *
+ * cpuid Unique opaque value which represents a target cpu.
+ *
+ * devhandle Device handle. It uniquely identifies a device, and
+ * consistes of the lower 28-bits of the hi-cell of the
+ * first entry of the device's "reg" property in the
+ * OBP device tree.
+ *
+ * devino Device interrupt number. Specifies the relative
+ * interrupt number within the device. The unique
+ * combination of devhandle and devino are used to
+ * identify a specific device interrupt.
+ *
+ * Note: The devino value is the same as the values in the
+ * "interrupts" property or "interrupt-map" property
+ * in the OBP device tree for that device.
+ *
+ * sysino System interrupt number. A 64-bit unsigned interger
+ * representing a unique interrupt within a virtual
+ * machine.
+ *
+ * intr_state A flag representing the interrupt state for a given
+ * sysino. The state values are defined below.
+ *
+ * intr_enabled A flag representing the 'enabled' state for a given
+ * sysino. The enable values are defined below.
+ */
+
+#define HV_INTR_STATE_IDLE 0 /* Nothing pending */
+#define HV_INTR_STATE_RECEIVED 1 /* Interrupt received by hardware */
+#define HV_INTR_STATE_DELIVERED 2 /* Interrupt delivered to queue */
+
+#define HV_INTR_DISABLED 0 /* sysino not enabled */
+#define HV_INTR_ENABLED 1 /* sysino enabled */
+
+/* intr_devino_to_sysino()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_INTR_DEVINO2SYSINO
+ * ARG0: devhandle
+ * ARG1: devino
+ * RET0: status
+ * RET1: sysino
+ * ERRORS: EINVAL Invalid devhandle/devino
+ *
+ * Converts a device specific interrupt number of the given
+ * devhandle/devino into a system specific ino (sysino).
+ */
+#define HV_FAST_INTR_DEVINO2SYSINO 0xa0
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
+ unsigned long devino);
+#endif
+
+/* intr_getenabled()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_INTR_GETENABLED
+ * ARG0: sysino
+ * RET0: status
+ * RET1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
+ * ERRORS: EINVAL Invalid sysino
+ *
+ * Returns interrupt enabled state in RET1 for the interrupt defined
+ * by the given sysino.
+ */
+#define HV_FAST_INTR_GETENABLED 0xa1
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_intr_getenabled(unsigned long sysino);
+#endif
+
+/* intr_setenabled()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_INTR_SETENABLED
+ * ARG0: sysino
+ * ARG1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
+ * RET0: status
+ * ERRORS: EINVAL Invalid sysino or intr_enabled value
+ *
+ * Set the 'enabled' state of the interrupt sysino.
+ */
+#define HV_FAST_INTR_SETENABLED 0xa2
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_intr_setenabled(unsigned long sysino, unsigned long intr_enabled);
+#endif
+
+/* intr_getstate()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_INTR_GETSTATE
+ * ARG0: sysino
+ * RET0: status
+ * RET1: intr_state (HV_INTR_STATE_*)
+ * ERRORS: EINVAL Invalid sysino
+ *
+ * Returns current state of the interrupt defined by the given sysino.
+ */
+#define HV_FAST_INTR_GETSTATE 0xa3
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_intr_getstate(unsigned long sysino);
+#endif
+
+/* intr_setstate()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_INTR_SETSTATE
+ * ARG0: sysino
+ * ARG1: intr_state (HV_INTR_STATE_*)
+ * RET0: status
+ * ERRORS: EINVAL Invalid sysino or intr_state value
+ *
+ * Sets the current state of the interrupt described by the given sysino
+ * value.
+ *
+ * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
+ * interrupt for sysino.
+ */
+#define HV_FAST_INTR_SETSTATE 0xa4
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
+#endif
+
+/* intr_gettarget()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_INTR_GETTARGET
+ * ARG0: sysino
+ * RET0: status
+ * RET1: cpuid
+ * ERRORS: EINVAL Invalid sysino
+ *
+ * Returns CPU that is the current target of the interrupt defined by
+ * the given sysino. The CPU value returned is undefined if the target
+ * has not been set via intr_settarget().
+ */
+#define HV_FAST_INTR_GETTARGET 0xa5
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_intr_gettarget(unsigned long sysino);
+#endif
+
+/* intr_settarget()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_INTR_SETTARGET
+ * ARG0: sysino
+ * ARG1: cpuid
+ * RET0: status
+ * ERRORS: EINVAL Invalid sysino
+ * ENOCPU Invalid cpuid
+ *
+ * Set the target CPU for the interrupt defined by the given sysino.
+ */
+#define HV_FAST_INTR_SETTARGET 0xa6
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
+#endif
+
+/* vintr_get_cookie()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_VINTR_GET_COOKIE
+ * ARG0: device handle
+ * ARG1: device ino
+ * RET0: status
+ * RET1: cookie
+ */
+#define HV_FAST_VINTR_GET_COOKIE 0xa7
+
+/* vintr_set_cookie()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_VINTR_SET_COOKIE
+ * ARG0: device handle
+ * ARG1: device ino
+ * ARG2: cookie
+ * RET0: status
+ */
+#define HV_FAST_VINTR_SET_COOKIE 0xa8
+
+/* vintr_get_valid()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_VINTR_GET_VALID
+ * ARG0: device handle
+ * ARG1: device ino
+ * RET0: status
+ * RET1: valid state
+ */
+#define HV_FAST_VINTR_GET_VALID 0xa9
+
+/* vintr_set_valid()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_VINTR_SET_VALID
+ * ARG0: device handle
+ * ARG1: device ino
+ * ARG2: valid state
+ * RET0: status
+ */
+#define HV_FAST_VINTR_SET_VALID 0xaa
+
+/* vintr_get_state()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_VINTR_GET_STATE
+ * ARG0: device handle
+ * ARG1: device ino
+ * RET0: status
+ * RET1: state
+ */
+#define HV_FAST_VINTR_GET_STATE 0xab
+
+/* vintr_set_state()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_VINTR_SET_STATE
+ * ARG0: device handle
+ * ARG1: device ino
+ * ARG2: state
+ * RET0: status
+ */
+#define HV_FAST_VINTR_SET_STATE 0xac
+
+/* vintr_get_target()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_VINTR_GET_TARGET
+ * ARG0: device handle
+ * ARG1: device ino
+ * RET0: status
+ * RET1: cpuid
+ */
+#define HV_FAST_VINTR_GET_TARGET 0xad
+
+/* vintr_set_target()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_VINTR_SET_TARGET
+ * ARG0: device handle
+ * ARG1: device ino
+ * ARG2: cpuid
+ * RET0: status
+ */
+#define HV_FAST_VINTR_SET_TARGET 0xae
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
+ unsigned long dev_ino,
+ unsigned long *cookie);
+extern unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle,
+ unsigned long dev_ino,
+ unsigned long cookie);
+extern unsigned long sun4v_vintr_get_valid(unsigned long dev_handle,
+ unsigned long dev_ino,
+ unsigned long *valid);
+extern unsigned long sun4v_vintr_set_valid(unsigned long dev_handle,
+ unsigned long dev_ino,
+ unsigned long valid);
+extern unsigned long sun4v_vintr_get_state(unsigned long dev_handle,
+ unsigned long dev_ino,
+ unsigned long *state);
+extern unsigned long sun4v_vintr_set_state(unsigned long dev_handle,
+ unsigned long dev_ino,
+ unsigned long state);
+extern unsigned long sun4v_vintr_get_target(unsigned long dev_handle,
+ unsigned long dev_ino,
+ unsigned long *cpuid);
+extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
+ unsigned long dev_ino,
+ unsigned long cpuid);
+#endif
+
+/* PCI IO services.
+ *
+ * See the terminology descriptions in the device interrupt services
+ * section above as those apply here too. Here are terminology
+ * definitions specific to these PCI IO services:
+ *
+ * tsbnum TSB number. Indentifies which io-tsb is used.
+ * For this version of the specification, tsbnum
+ * must be zero.
+ *
+ * tsbindex TSB index. Identifies which entry in the TSB
+ * is used. The first entry is zero.
+ *
+ * tsbid A 64-bit aligned data structure which contains
+ * a tsbnum and a tsbindex. Bits 63:32 contain the
+ * tsbnum and bits 31:00 contain the tsbindex.
+ *
+ * Use the HV_PCI_TSBID() macro to construct such
+ * values.
+ *
+ * io_attributes IO attributes for IOMMU mappings. One of more
+ * of the attritbute bits are stores in a 64-bit
+ * value. The values are defined below.
+ *
+ * r_addr 64-bit real address
+ *
+ * pci_device PCI device address. A PCI device address identifies
+ * a specific device on a specific PCI bus segment.
+ * A PCI device address ia a 32-bit unsigned integer
+ * with the following format:
+ *
+ * 00000000.bbbbbbbb.dddddfff.00000000
+ *
+ * Use the HV_PCI_DEVICE_BUILD() macro to construct
+ * such values.
+ *
+ * pci_config_offset
+ * PCI configureation space offset. For conventional
+ * PCI a value between 0 and 255. For extended
+ * configuration space, a value between 0 and 4095.
+ *
+ * Note: For PCI configuration space accesses, the offset
+ * must be aligned to the access size.
+ *
+ * error_flag A return value which specifies if the action succeeded
+ * or failed. 0 means no error, non-0 means some error
+ * occurred while performing the service.
+ *
+ * io_sync_direction
+ * Direction definition for pci_dma_sync(), defined
+ * below in HV_PCI_SYNC_*.
+ *
+ * io_page_list A list of io_page_addresses, an io_page_address is
+ * a real address.
+ *
+ * io_page_list_p A pointer to an io_page_list.
+ *
+ * "size based byte swap" - Some functions do size based byte swapping
+ * which allows sw to access pointers and
+ * counters in native form when the processor
+ * operates in a different endianness than the
+ * IO bus. Size-based byte swapping converts a
+ * multi-byte field between big-endian and
+ * little-endian format.
+ */
+
+#define HV_PCI_MAP_ATTR_READ 0x01
+#define HV_PCI_MAP_ATTR_WRITE 0x02
+
+#define HV_PCI_DEVICE_BUILD(b,d,f) \
+ ((((b) & 0xff) << 16) | \
+ (((d) & 0x1f) << 11) | \
+ (((f) & 0x07) << 8))
+
+#define HV_PCI_TSBID(__tsb_num, __tsb_index) \
+ ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index)))
+
+#define HV_PCI_SYNC_FOR_DEVICE 0x01
+#define HV_PCI_SYNC_FOR_CPU 0x02
+
+/* pci_iommu_map()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_IOMMU_MAP
+ * ARG0: devhandle
+ * ARG1: tsbid
+ * ARG2: #ttes
+ * ARG3: io_attributes
+ * ARG4: io_page_list_p
+ * RET0: status
+ * RET1: #ttes mapped
+ * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex/io_attributes
+ * EBADALIGN Improperly aligned real address
+ * ENORADDR Invalid real address
+ *
+ * Create IOMMU mappings in the sun4v device defined by the given
+ * devhandle. The mappings are created in the TSB defined by the
+ * tsbnum component of the given tsbid. The first mapping is created
+ * in the TSB i ndex defined by the tsbindex component of the given tsbid.
+ * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
+ * the second at tsbnum, tsbindex + 1, etc.
+ *
+ * All mappings are created with the attributes defined by the io_attributes
+ * argument. The page mapping addresses are described in the io_page_list
+ * defined by the given io_page_list_p, which is a pointer to the io_page_list.
+ * The first entry in the io_page_list is the address for the first iotte, the
+ * 2nd for the 2nd iotte, and so on.
+ *
+ * Each io_page_address in the io_page_list must be appropriately aligned.
+ * #ttes must be greater than zero. For this version of the spec, the tsbnum
+ * component of the given tsbid must be zero.
+ *
+ * Returns the actual number of mappings creates, which may be less than
+ * or equal to the argument #ttes. If the function returns a value which
+ * is less than the #ttes, the caller may continus to call the function with
+ * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
+ * mapped.
+ *
+ * Note: This function does not imply an iotte cache flush. The guest must
+ * demap an entry before re-mapping it.
+ */
+#define HV_FAST_PCI_IOMMU_MAP 0xb0
+
+/* pci_iommu_demap()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_IOMMU_DEMAP
+ * ARG0: devhandle
+ * ARG1: tsbid
+ * ARG2: #ttes
+ * RET0: status
+ * RET1: #ttes demapped
+ * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
+ *
+ * Demap and flush IOMMU mappings in the device defined by the given
+ * devhandle. Demaps up to #ttes entries in the TSB defined by the tsbnum
+ * component of the given tsbid, starting at the TSB index defined by the
+ * tsbindex component of the given tsbid.
+ *
+ * For this version of the spec, the tsbnum of the given tsbid must be zero.
+ * #ttes must be greater than zero.
+ *
+ * Returns the actual number of ttes demapped, which may be less than or equal
+ * to the argument #ttes. If #ttes demapped is less than #ttes, the caller
+ * may continue to call this function with updated tsbid and #ttes arguments
+ * until all pages are demapped.
+ *
+ * Note: Entries do not have to be mapped to be demapped. A demap of an
+ * unmapped page will flush the entry from the tte cache.
+ */
+#define HV_FAST_PCI_IOMMU_DEMAP 0xb1
+
+/* pci_iommu_getmap()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_IOMMU_GETMAP
+ * ARG0: devhandle
+ * ARG1: tsbid
+ * RET0: status
+ * RET1: io_attributes
+ * RET2: real address
+ * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
+ * ENOMAP Mapping is not valid, no translation exists
+ *
+ * Read and return the mapping in the device described by the given devhandle
+ * and tsbid. If successful, the io_attributes shall be returned in RET1
+ * and the page address of the mapping shall be returned in RET2.
+ *
+ * For this version of the spec, the tsbnum component of the given tsbid
+ * must be zero.
+ */
+#define HV_FAST_PCI_IOMMU_GETMAP 0xb2
+
+/* pci_iommu_getbypass()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_IOMMU_GETBYPASS
+ * ARG0: devhandle
+ * ARG1: real address
+ * ARG2: io_attributes
+ * RET0: status
+ * RET1: io_addr
+ * ERRORS: EINVAL Invalid devhandle/io_attributes
+ * ENORADDR Invalid real address
+ * ENOTSUPPORTED Function not supported in this implementation.
+ *
+ * Create a "special" mapping in the device described by the given devhandle,
+ * for the given real address and attributes. Return the IO address in RET1
+ * if successful.
+ */
+#define HV_FAST_PCI_IOMMU_GETBYPASS 0xb3
+
+/* pci_config_get()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_CONFIG_GET
+ * ARG0: devhandle
+ * ARG1: pci_device
+ * ARG2: pci_config_offset
+ * ARG3: size
+ * RET0: status
+ * RET1: error_flag
+ * RET2: data
+ * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
+ * EBADALIGN pci_config_offset not size aligned
+ * ENOACCESS Access to this offset is not permitted
+ *
+ * Read PCI configuration space for the adapter described by the given
+ * devhandle. Read size (1, 2, or 4) bytes of data from the given
+ * pci_device, at pci_config_offset from the beginning of the device's
+ * configuration space. If there was no error, RET1 is set to zero and
+ * RET2 is set to the data read. Insignificant bits in RET2 are not
+ * guarenteed to have any specific value and therefore must be ignored.
+ *
+ * The data returned in RET2 is size based byte swapped.
+ *
+ * If an error occurs during the read, set RET1 to a non-zero value. The
+ * given pci_config_offset must be 'size' aligned.
+ */
+#define HV_FAST_PCI_CONFIG_GET 0xb4
+
+/* pci_config_put()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_CONFIG_PUT
+ * ARG0: devhandle
+ * ARG1: pci_device
+ * ARG2: pci_config_offset
+ * ARG3: size
+ * ARG4: data
+ * RET0: status
+ * RET1: error_flag
+ * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
+ * EBADALIGN pci_config_offset not size aligned
+ * ENOACCESS Access to this offset is not permitted
+ *
+ * Write PCI configuration space for the adapter described by the given
+ * devhandle. Write size (1, 2, or 4) bytes of data in a single operation,
+ * at pci_config_offset from the beginning of the device's configuration
+ * space. The data argument contains the data to be written to configuration
+ * space. Prior to writing, the data is size based byte swapped.
+ *
+ * If an error occurs during the write access, do not generate an error
+ * report, do set RET1 to a non-zero value. Otherwise RET1 is zero.
+ * The given pci_config_offset must be 'size' aligned.
+ *
+ * This function is permitted to read from offset zero in the configuration
+ * space described by the given pci_device if necessary to ensure that the
+ * write access to config space completes.
+ */
+#define HV_FAST_PCI_CONFIG_PUT 0xb5
+
+/* pci_peek()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_PEEK
+ * ARG0: devhandle
+ * ARG1: real address
+ * ARG2: size
+ * RET0: status
+ * RET1: error_flag
+ * RET2: data
+ * ERRORS: EINVAL Invalid devhandle or size
+ * EBADALIGN Improperly aligned real address
+ * ENORADDR Bad real address
+ * ENOACCESS Guest access prohibited
+ *
+ * Attempt to read the IO address given by the given devhandle, real address,
+ * and size. Size must be 1, 2, 4, or 8. The read is performed as a single
+ * access operation using the given size. If an error occurs when reading
+ * from the given location, do not generate an error report, but return a
+ * non-zero value in RET1. If the read was successful, return zero in RET1
+ * and return the actual data read in RET2. The data returned is size based
+ * byte swapped.
+ *
+ * Non-significant bits in RET2 are not guarenteed to have any specific value
+ * and therefore must be ignored. If RET1 is returned as non-zero, the data
+ * value is not guarenteed to have any specific value and should be ignored.
+ *
+ * The caller must have permission to read from the given devhandle, real
+ * address, which must be an IO address. The argument real address must be a
+ * size aligned address.
+ *
+ * The hypervisor implementation of this function must block access to any
+ * IO address that the guest does not have explicit permission to access.
+ */
+#define HV_FAST_PCI_PEEK 0xb6
+
+/* pci_poke()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_POKE
+ * ARG0: devhandle
+ * ARG1: real address
+ * ARG2: size
+ * ARG3: data
+ * ARG4: pci_device
+ * RET0: status
+ * RET1: error_flag
+ * ERRORS: EINVAL Invalid devhandle, size, or pci_device
+ * EBADALIGN Improperly aligned real address
+ * ENORADDR Bad real address
+ * ENOACCESS Guest access prohibited
+ * ENOTSUPPORTED Function is not supported by implementation
+ *
+ * Attempt to write data to the IO address given by the given devhandle,
+ * real address, and size. Size must be 1, 2, 4, or 8. The write is
+ * performed as a single access operation using the given size. Prior to
+ * writing the data is size based swapped.
+ *
+ * If an error occurs when writing to the given location, do not generate an
+ * error report, but return a non-zero value in RET1. If the write was
+ * successful, return zero in RET1.
+ *
+ * pci_device describes the configuration address of the device being
+ * written to. The implementation may safely read from offset 0 with
+ * the configuration space of the device described by devhandle and
+ * pci_device in order to guarantee that the write portion of the operation
+ * completes
+ *
+ * Any error that occurs due to the read shall be reported using the normal
+ * error reporting mechanisms .. the read error is not suppressed.
+ *
+ * The caller must have permission to write to the given devhandle, real
+ * address, which must be an IO address. The argument real address must be a
+ * size aligned address. The caller must have permission to read from
+ * the given devhandle, pci_device cofiguration space offset 0.
+ *
+ * The hypervisor implementation of this function must block access to any
+ * IO address that the guest does not have explicit permission to access.
+ */
+#define HV_FAST_PCI_POKE 0xb7
+
+/* pci_dma_sync()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_DMA_SYNC
+ * ARG0: devhandle
+ * ARG1: real address
+ * ARG2: size
+ * ARG3: io_sync_direction
+ * RET0: status
+ * RET1: #synced
+ * ERRORS: EINVAL Invalid devhandle or io_sync_direction
+ * ENORADDR Bad real address
+ *
+ * Synchronize a memory region described by the given real address and size,
+ * for the device defined by the given devhandle using the direction(s)
+ * defined by the given io_sync_direction. The argument size is the size of
+ * the memory region in bytes.
+ *
+ * Return the actual number of bytes synchronized in the return value #synced,
+ * which may be less than or equal to the argument size. If the return
+ * value #synced is less than size, the caller must continue to call this
+ * function with updated real address and size arguments until the entire
+ * memory region is synchronized.
+ */
+#define HV_FAST_PCI_DMA_SYNC 0xb8
+
+/* PCI MSI services. */
+
+#define HV_MSITYPE_MSI32 0x00
+#define HV_MSITYPE_MSI64 0x01
+
+#define HV_MSIQSTATE_IDLE 0x00
+#define HV_MSIQSTATE_ERROR 0x01
+
+#define HV_MSIQ_INVALID 0x00
+#define HV_MSIQ_VALID 0x01
+
+#define HV_MSISTATE_IDLE 0x00
+#define HV_MSISTATE_DELIVERED 0x01
+
+#define HV_MSIVALID_INVALID 0x00
+#define HV_MSIVALID_VALID 0x01
+
+#define HV_PCIE_MSGTYPE_PME_MSG 0x18
+#define HV_PCIE_MSGTYPE_PME_ACK_MSG 0x1b
+#define HV_PCIE_MSGTYPE_CORR_MSG 0x30
+#define HV_PCIE_MSGTYPE_NONFATAL_MSG 0x31
+#define HV_PCIE_MSGTYPE_FATAL_MSG 0x33
+
+#define HV_MSG_INVALID 0x00
+#define HV_MSG_VALID 0x01
+
+/* pci_msiq_conf()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSIQ_CONF
+ * ARG0: devhandle
+ * ARG1: msiqid
+ * ARG2: real address
+ * ARG3: number of entries
+ * RET0: status
+ * ERRORS: EINVAL Invalid devhandle, msiqid or nentries
+ * EBADALIGN Improperly aligned real address
+ * ENORADDR Bad real address
+ *
+ * Configure the MSI queue given by the devhandle and msiqid arguments,
+ * and to be placed at the given real address and be of the given
+ * number of entries. The real address must be aligned exactly to match
+ * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry
+ * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ
+ * Head and Tail are initialized so that the MSI-EQ is 'empty'.
+ *
+ * Implementation Note: Certain implementations have fixed sized queues. In
+ * that case, number of entries must contain the correct
+ * value.
+ */
+#define HV_FAST_PCI_MSIQ_CONF 0xc0
+
+/* pci_msiq_info()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSIQ_INFO
+ * ARG0: devhandle
+ * ARG1: msiqid
+ * RET0: status
+ * RET1: real address
+ * RET2: number of entries
+ * ERRORS: EINVAL Invalid devhandle or msiqid
+ *
+ * Return the configuration information for the MSI queue described
+ * by the given devhandle and msiqid. The base address of the queue
+ * is returned in ARG1 and the number of entries is returned in ARG2.
+ * If the queue is unconfigured, the real address is undefined and the
+ * number of entries will be returned as zero.
+ */
+#define HV_FAST_PCI_MSIQ_INFO 0xc1
+
+/* pci_msiq_getvalid()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
+ * ARG0: devhandle
+ * ARG1: msiqid
+ * RET0: status
+ * RET1: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
+ * ERRORS: EINVAL Invalid devhandle or msiqid
+ *
+ * Get the valid state of the MSI-EQ described by the given devhandle and
+ * msiqid.
+ */
+#define HV_FAST_PCI_MSIQ_GETVALID 0xc2
+
+/* pci_msiq_setvalid()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSIQ_SETVALID
+ * ARG0: devhandle
+ * ARG1: msiqid
+ * ARG2: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
+ * RET0: status
+ * ERRORS: EINVAL Invalid devhandle or msiqid or msiqvalid
+ * value or MSI EQ is uninitialized
+ *
+ * Set the valid state of the MSI-EQ described by the given devhandle and
+ * msiqid to the given msiqvalid.
+ */
+#define HV_FAST_PCI_MSIQ_SETVALID 0xc3
+
+/* pci_msiq_getstate()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSIQ_GETSTATE
+ * ARG0: devhandle
+ * ARG1: msiqid
+ * RET0: status
+ * RET1: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
+ * ERRORS: EINVAL Invalid devhandle or msiqid
+ *
+ * Get the state of the MSI-EQ described by the given devhandle and
+ * msiqid.
+ */
+#define HV_FAST_PCI_MSIQ_GETSTATE 0xc4
+
+/* pci_msiq_getvalid()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
+ * ARG0: devhandle
+ * ARG1: msiqid
+ * ARG2: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
+ * RET0: status
+ * ERRORS: EINVAL Invalid devhandle or msiqid or msiqstate
+ * value or MSI EQ is uninitialized
+ *
+ * Set the state of the MSI-EQ described by the given devhandle and
+ * msiqid to the given msiqvalid.
+ */
+#define HV_FAST_PCI_MSIQ_SETSTATE 0xc5
+
+/* pci_msiq_gethead()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSIQ_GETHEAD
+ * ARG0: devhandle
+ * ARG1: msiqid
+ * RET0: status
+ * RET1: msiqhead
+ * ERRORS: EINVAL Invalid devhandle or msiqid
+ *
+ * Get the current MSI EQ queue head for the MSI-EQ described by the
+ * given devhandle and msiqid.
+ */
+#define HV_FAST_PCI_MSIQ_GETHEAD 0xc6
+
+/* pci_msiq_sethead()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSIQ_SETHEAD
+ * ARG0: devhandle
+ * ARG1: msiqid
+ * ARG2: msiqhead
+ * RET0: status
+ * ERRORS: EINVAL Invalid devhandle or msiqid or msiqhead,
+ * or MSI EQ is uninitialized
+ *
+ * Set the current MSI EQ queue head for the MSI-EQ described by the
+ * given devhandle and msiqid.
+ */
+#define HV_FAST_PCI_MSIQ_SETHEAD 0xc7
+
+/* pci_msiq_gettail()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSIQ_GETTAIL
+ * ARG0: devhandle
+ * ARG1: msiqid
+ * RET0: status
+ * RET1: msiqtail
+ * ERRORS: EINVAL Invalid devhandle or msiqid
+ *
+ * Get the current MSI EQ queue tail for the MSI-EQ described by the
+ * given devhandle and msiqid.
+ */
+#define HV_FAST_PCI_MSIQ_GETTAIL 0xc8
+
+/* pci_msi_getvalid()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSI_GETVALID
+ * ARG0: devhandle
+ * ARG1: msinum
+ * RET0: status
+ * RET1: msivalidstate
+ * ERRORS: EINVAL Invalid devhandle or msinum
+ *
+ * Get the current valid/enabled state for the MSI defined by the
+ * given devhandle and msinum.
+ */
+#define HV_FAST_PCI_MSI_GETVALID 0xc9
+
+/* pci_msi_setvalid()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSI_SETVALID
+ * ARG0: devhandle
+ * ARG1: msinum
+ * ARG2: msivalidstate
+ * RET0: status
+ * ERRORS: EINVAL Invalid devhandle or msinum or msivalidstate
+ *
+ * Set the current valid/enabled state for the MSI defined by the
+ * given devhandle and msinum.
+ */
+#define HV_FAST_PCI_MSI_SETVALID 0xca
+
+/* pci_msi_getmsiq()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSI_GETMSIQ
+ * ARG0: devhandle
+ * ARG1: msinum
+ * RET0: status
+ * RET1: msiqid
+ * ERRORS: EINVAL Invalid devhandle or msinum or MSI is unbound
+ *
+ * Get the MSI EQ that the MSI defined by the given devhandle and
+ * msinum is bound to.
+ */
+#define HV_FAST_PCI_MSI_GETMSIQ 0xcb
+
+/* pci_msi_setmsiq()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSI_SETMSIQ
+ * ARG0: devhandle
+ * ARG1: msinum
+ * ARG2: msitype
+ * ARG3: msiqid
+ * RET0: status
+ * ERRORS: EINVAL Invalid devhandle or msinum or msiqid
+ *
+ * Set the MSI EQ that the MSI defined by the given devhandle and
+ * msinum is bound to.
+ */
+#define HV_FAST_PCI_MSI_SETMSIQ 0xcc
+
+/* pci_msi_getstate()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSI_GETSTATE
+ * ARG0: devhandle
+ * ARG1: msinum
+ * RET0: status
+ * RET1: msistate
+ * ERRORS: EINVAL Invalid devhandle or msinum
+ *
+ * Get the state of the MSI defined by the given devhandle and msinum.
+ * If not initialized, return HV_MSISTATE_IDLE.
+ */
+#define HV_FAST_PCI_MSI_GETSTATE 0xcd
+
+/* pci_msi_setstate()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSI_SETSTATE
+ * ARG0: devhandle
+ * ARG1: msinum
+ * ARG2: msistate
+ * RET0: status
+ * ERRORS: EINVAL Invalid devhandle or msinum or msistate
+ *
+ * Set the state of the MSI defined by the given devhandle and msinum.
+ */
+#define HV_FAST_PCI_MSI_SETSTATE 0xce
+
+/* pci_msg_getmsiq()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSG_GETMSIQ
+ * ARG0: devhandle
+ * ARG1: msgtype
+ * RET0: status
+ * RET1: msiqid
+ * ERRORS: EINVAL Invalid devhandle or msgtype
+ *
+ * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
+ */
+#define HV_FAST_PCI_MSG_GETMSIQ 0xd0
+
+/* pci_msg_setmsiq()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSG_SETMSIQ
+ * ARG0: devhandle
+ * ARG1: msgtype
+ * ARG2: msiqid
+ * RET0: status
+ * ERRORS: EINVAL Invalid devhandle, msgtype, or msiqid
+ *
+ * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
+ */
+#define HV_FAST_PCI_MSG_SETMSIQ 0xd1
+
+/* pci_msg_getvalid()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSG_GETVALID
+ * ARG0: devhandle
+ * ARG1: msgtype
+ * RET0: status
+ * RET1: msgvalidstate
+ * ERRORS: EINVAL Invalid devhandle or msgtype
+ *
+ * Get the valid/enabled state of the MSG defined by the given
+ * devhandle and msgtype.
+ */
+#define HV_FAST_PCI_MSG_GETVALID 0xd2
+
+/* pci_msg_setvalid()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_PCI_MSG_SETVALID
+ * ARG0: devhandle
+ * ARG1: msgtype
+ * ARG2: msgvalidstate
+ * RET0: status
+ * ERRORS: EINVAL Invalid devhandle or msgtype or msgvalidstate
+ *
+ * Set the valid/enabled state of the MSG defined by the given
+ * devhandle and msgtype.
+ */
+#define HV_FAST_PCI_MSG_SETVALID 0xd3
+
+/* Logical Domain Channel services. */
+
+#define LDC_CHANNEL_DOWN 0
+#define LDC_CHANNEL_UP 1
+#define LDC_CHANNEL_RESETTING 2
+
+/* ldc_tx_qconf()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_TX_QCONF
+ * ARG0: channel ID
+ * ARG1: real address base of queue
+ * ARG2: num entries in queue
+ * RET0: status
+ *
+ * Configure transmit queue for the LDC endpoint specified by the
+ * given channel ID, to be placed at the given real address, and
+ * be of the given num entries. Num entries must be a power of two.
+ * The real address base of the queue must be aligned on the queue
+ * size. Each queue entry is 64-bytes, so for example, a 32 entry
+ * queue must be aligned on a 2048 byte real address boundary.
+ *
+ * Upon configuration of a valid transmit queue the head and tail
+ * pointers are set to a hypervisor specific identical value indicating
+ * that the queue initially is empty.
+ *
+ * The endpoint's transmit queue is un-configured if num entries is zero.
+ *
+ * The maximum number of entries for each queue for a specific cpu may be
+ * determined from the machine description. A transmit queue may be
+ * specified even in the event that the LDC is down (peer endpoint has no
+ * receive queue specified). Transmission will begin as soon as the peer
+ * endpoint defines a receive queue.
+ *
+ * It is recommended that a guest wait for a transmit queue to empty prior
+ * to reconfiguring it, or un-configuring it. Re or un-configuring of a
+ * non-empty transmit queue behaves exactly as defined above, however it
+ * is undefined as to how many of the pending entries in the original queue
+ * will be delivered prior to the re-configuration taking effect.
+ * Furthermore, as the queue configuration causes a reset of the head and
+ * tail pointers there is no way for a guest to determine how many entries
+ * have been sent after the configuration operation.
+ */
+#define HV_FAST_LDC_TX_QCONF 0xe0
+
+/* ldc_tx_qinfo()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_TX_QINFO
+ * ARG0: channel ID
+ * RET0: status
+ * RET1: real address base of queue
+ * RET2: num entries in queue
+ *
+ * Return the configuration info for the transmit queue of LDC endpoint
+ * defined by the given channel ID. The real address is the currently
+ * defined real address base of the defined queue, and num entries is the
+ * size of the queue in terms of number of entries.
+ *
+ * If the specified channel ID is a valid endpoint number, but no transmit
+ * queue has been defined this service will return success, but with num
+ * entries set to zero and the real address will have an undefined value.
+ */
+#define HV_FAST_LDC_TX_QINFO 0xe1
+
+/* ldc_tx_get_state()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_TX_GET_STATE
+ * ARG0: channel ID
+ * RET0: status
+ * RET1: head offset
+ * RET2: tail offset
+ * RET3: channel state
+ *
+ * Return the transmit state, and the head and tail queue pointers, for
+ * the transmit queue of the LDC endpoint defined by the given channel ID.
+ * The head and tail values are the byte offset of the head and tail
+ * positions of the transmit queue for the specified endpoint.
+ */
+#define HV_FAST_LDC_TX_GET_STATE 0xe2
+
+/* ldc_tx_set_qtail()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_TX_SET_QTAIL
+ * ARG0: channel ID
+ * ARG1: tail offset
+ * RET0: status
+ *
+ * Update the tail pointer for the transmit queue associated with the LDC
+ * endpoint defined by the given channel ID. The tail offset specified
+ * must be aligned on a 64 byte boundary, and calculated so as to increase
+ * the number of pending entries on the transmit queue. Any attempt to
+ * decrease the number of pending transmit queue entires is considered
+ * an invalid tail offset and will result in an EINVAL error.
+ *
+ * Since the tail of the transmit queue may not be moved backwards, the
+ * transmit queue may be flushed by configuring a new transmit queue,
+ * whereupon the hypervisor will configure the initial transmit head and
+ * tail pointers to be equal.
+ */
+#define HV_FAST_LDC_TX_SET_QTAIL 0xe3
+
+/* ldc_rx_qconf()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_RX_QCONF
+ * ARG0: channel ID
+ * ARG1: real address base of queue
+ * ARG2: num entries in queue
+ * RET0: status
+ *
+ * Configure receive queue for the LDC endpoint specified by the
+ * given channel ID, to be placed at the given real address, and
+ * be of the given num entries. Num entries must be a power of two.
+ * The real address base of the queue must be aligned on the queue
+ * size. Each queue entry is 64-bytes, so for example, a 32 entry
+ * queue must be aligned on a 2048 byte real address boundary.
+ *
+ * The endpoint's transmit queue is un-configured if num entries is zero.
+ *
+ * If a valid receive queue is specified for a local endpoint the LDC is
+ * in the up state for the purpose of transmission to this endpoint.
+ *
+ * The maximum number of entries for each queue for a specific cpu may be
+ * determined from the machine description.
+ *
+ * As receive queue configuration causes a reset of the queue's head and
+ * tail pointers there is no way for a gues to determine how many entries
+ * have been received between a preceeding ldc_get_rx_state() API call
+ * and the completion of the configuration operation. It should be noted
+ * that datagram delivery is not guarenteed via domain channels anyway,
+ * and therefore any higher protocol should be resilient to datagram
+ * loss if necessary. However, to overcome this specific race potential
+ * it is recommended, for example, that a higher level protocol be employed
+ * to ensure either retransmission, or ensure that no datagrams are pending
+ * on the peer endpoint's transmit queue prior to the configuration process.
+ */
+#define HV_FAST_LDC_RX_QCONF 0xe4
+
+/* ldc_rx_qinfo()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_RX_QINFO
+ * ARG0: channel ID
+ * RET0: status
+ * RET1: real address base of queue
+ * RET2: num entries in queue
+ *
+ * Return the configuration info for the receive queue of LDC endpoint
+ * defined by the given channel ID. The real address is the currently
+ * defined real address base of the defined queue, and num entries is the
+ * size of the queue in terms of number of entries.
+ *
+ * If the specified channel ID is a valid endpoint number, but no receive
+ * queue has been defined this service will return success, but with num
+ * entries set to zero and the real address will have an undefined value.
+ */
+#define HV_FAST_LDC_RX_QINFO 0xe5
+
+/* ldc_rx_get_state()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_RX_GET_STATE
+ * ARG0: channel ID
+ * RET0: status
+ * RET1: head offset
+ * RET2: tail offset
+ * RET3: channel state
+ *
+ * Return the receive state, and the head and tail queue pointers, for
+ * the receive queue of the LDC endpoint defined by the given channel ID.
+ * The head and tail values are the byte offset of the head and tail
+ * positions of the receive queue for the specified endpoint.
+ */
+#define HV_FAST_LDC_RX_GET_STATE 0xe6
+
+/* ldc_rx_set_qhead()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_RX_SET_QHEAD
+ * ARG0: channel ID
+ * ARG1: head offset
+ * RET0: status
+ *
+ * Update the head pointer for the receive queue associated with the LDC
+ * endpoint defined by the given channel ID. The head offset specified
+ * must be aligned on a 64 byte boundary, and calculated so as to decrease
+ * the number of pending entries on the receive queue. Any attempt to
+ * increase the number of pending receive queue entires is considered
+ * an invalid head offset and will result in an EINVAL error.
+ *
+ * The receive queue may be flushed by setting the head offset equal
+ * to the current tail offset.
+ */
+#define HV_FAST_LDC_RX_SET_QHEAD 0xe7
+
+/* LDC Map Table Entry. Each slot is defined by a translation table
+ * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
+ * hypervisor invalidation cookie.
+ */
+#define LDC_MTE_PADDR 0x0fffffffffffe000 /* pa[55:13] */
+#define LDC_MTE_COPY_W 0x0000000000000400 /* copy write access */
+#define LDC_MTE_COPY_R 0x0000000000000200 /* copy read access */
+#define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */
+#define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access */
+#define LDC_MTE_EXEC 0x0000000000000040 /* execute */
+#define LDC_MTE_WRITE 0x0000000000000020 /* read */
+#define LDC_MTE_READ 0x0000000000000010 /* write */
+#define LDC_MTE_SZALL 0x000000000000000f /* page size bits */
+#define LDC_MTE_SZ16GB 0x0000000000000007 /* 16GB page */
+#define LDC_MTE_SZ2GB 0x0000000000000006 /* 2GB page */
+#define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page */
+#define LDC_MTE_SZ32MB 0x0000000000000004 /* 32MB page */
+#define LDC_MTE_SZ4MB 0x0000000000000003 /* 4MB page */
+#define LDC_MTE_SZ512K 0x0000000000000002 /* 512K page */
+#define LDC_MTE_SZ64K 0x0000000000000001 /* 64K page */
+#define LDC_MTE_SZ8K 0x0000000000000000 /* 8K page */
+
+#ifndef __ASSEMBLY__
+struct ldc_mtable_entry {
+ unsigned long mte;
+ unsigned long cookie;
+};
+#endif
+
+/* ldc_set_map_table()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_SET_MAP_TABLE
+ * ARG0: channel ID
+ * ARG1: table real address
+ * ARG2: num entries
+ * RET0: status
+ *
+ * Register the MTE table at the given table real address, with the
+ * specified num entries, for the LDC indicated by the given channel
+ * ID.
+ */
+#define HV_FAST_LDC_SET_MAP_TABLE 0xea
+
+/* ldc_get_map_table()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_GET_MAP_TABLE
+ * ARG0: channel ID
+ * RET0: status
+ * RET1: table real address
+ * RET2: num entries
+ *
+ * Return the configuration of the current mapping table registered
+ * for the given channel ID.
+ */
+#define HV_FAST_LDC_GET_MAP_TABLE 0xeb
+
+#define LDC_COPY_IN 0
+#define LDC_COPY_OUT 1
+
+/* ldc_copy()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_COPY
+ * ARG0: channel ID
+ * ARG1: LDC_COPY_* direction code
+ * ARG2: target real address
+ * ARG3: local real address
+ * ARG4: length in bytes
+ * RET0: status
+ * RET1: actual length in bytes
+ */
+#define HV_FAST_LDC_COPY 0xec
+
+#define LDC_MEM_READ 1
+#define LDC_MEM_WRITE 2
+#define LDC_MEM_EXEC 4
+
+/* ldc_mapin()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_MAPIN
+ * ARG0: channel ID
+ * ARG1: cookie
+ * RET0: status
+ * RET1: real address
+ * RET2: LDC_MEM_* permissions
+ */
+#define HV_FAST_LDC_MAPIN 0xed
+
+/* ldc_unmap()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_UNMAP
+ * ARG0: real address
+ * RET0: status
+ */
+#define HV_FAST_LDC_UNMAP 0xee
+
+/* ldc_revoke()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_LDC_REVOKE
+ * ARG0: channel ID
+ * ARG1: cookie
+ * ARG2: ldc_mtable_entry cookie
+ * RET0: status
+ */
+#define HV_FAST_LDC_REVOKE 0xef
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
+ unsigned long ra,
+ unsigned long num_entries);
+extern unsigned long sun4v_ldc_tx_qinfo(unsigned long channel,
+ unsigned long *ra,
+ unsigned long *num_entries);
+extern unsigned long sun4v_ldc_tx_get_state(unsigned long channel,
+ unsigned long *head_off,
+ unsigned long *tail_off,
+ unsigned long *chan_state);
+extern unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel,
+ unsigned long tail_off);
+extern unsigned long sun4v_ldc_rx_qconf(unsigned long channel,
+ unsigned long ra,
+ unsigned long num_entries);
+extern unsigned long sun4v_ldc_rx_qinfo(unsigned long channel,
+ unsigned long *ra,
+ unsigned long *num_entries);
+extern unsigned long sun4v_ldc_rx_get_state(unsigned long channel,
+ unsigned long *head_off,
+ unsigned long *tail_off,
+ unsigned long *chan_state);
+extern unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel,
+ unsigned long head_off);
+extern unsigned long sun4v_ldc_set_map_table(unsigned long channel,
+ unsigned long ra,
+ unsigned long num_entries);
+extern unsigned long sun4v_ldc_get_map_table(unsigned long channel,
+ unsigned long *ra,
+ unsigned long *num_entries);
+extern unsigned long sun4v_ldc_copy(unsigned long channel,
+ unsigned long dir_code,
+ unsigned long tgt_raddr,
+ unsigned long lcl_raddr,
+ unsigned long len,
+ unsigned long *actual_len);
+extern unsigned long sun4v_ldc_mapin(unsigned long channel,
+ unsigned long cookie,
+ unsigned long *ra,
+ unsigned long *perm);
+extern unsigned long sun4v_ldc_unmap(unsigned long ra);
+extern unsigned long sun4v_ldc_revoke(unsigned long channel,
+ unsigned long cookie,
+ unsigned long mte_cookie);
+#endif
+
+/* Performance counter services. */
+
+#define HV_PERF_JBUS_PERF_CTRL_REG 0x00
+#define HV_PERF_JBUS_PERF_CNT_REG 0x01
+#define HV_PERF_DRAM_PERF_CTRL_REG_0 0x02
+#define HV_PERF_DRAM_PERF_CNT_REG_0 0x03
+#define HV_PERF_DRAM_PERF_CTRL_REG_1 0x04
+#define HV_PERF_DRAM_PERF_CNT_REG_1 0x05
+#define HV_PERF_DRAM_PERF_CTRL_REG_2 0x06
+#define HV_PERF_DRAM_PERF_CNT_REG_2 0x07
+#define HV_PERF_DRAM_PERF_CTRL_REG_3 0x08
+#define HV_PERF_DRAM_PERF_CNT_REG_3 0x09
+
+/* get_perfreg()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_GET_PERFREG
+ * ARG0: performance reg number
+ * RET0: status
+ * RET1: performance reg value
+ * ERRORS: EINVAL Invalid performance register number
+ * ENOACCESS No access allowed to performance counters
+ *
+ * Read the value of the given DRAM/JBUS performance counter/control register.
+ */
+#define HV_FAST_GET_PERFREG 0x100
+
+/* set_perfreg()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_SET_PERFREG
+ * ARG0: performance reg number
+ * ARG1: performance reg value
+ * RET0: status
+ * ERRORS: EINVAL Invalid performance register number
+ * ENOACCESS No access allowed to performance counters
+ *
+ * Write the given performance reg value to the given DRAM/JBUS
+ * performance counter/control register.
+ */
+#define HV_FAST_SET_PERFREG 0x101
+
+/* MMU statistics services.
+ *
+ * The hypervisor maintains MMU statistics and privileged code provides
+ * a buffer where these statistics can be collected. It is continually
+ * updated once configured. The layout is as follows:
+ */
+#ifndef __ASSEMBLY__
+struct hv_mmu_statistics {
+ unsigned long immu_tsb_hits_ctx0_8k_tte;
+ unsigned long immu_tsb_ticks_ctx0_8k_tte;
+ unsigned long immu_tsb_hits_ctx0_64k_tte;
+ unsigned long immu_tsb_ticks_ctx0_64k_tte;
+ unsigned long __reserved1[2];
+ unsigned long immu_tsb_hits_ctx0_4mb_tte;
+ unsigned long immu_tsb_ticks_ctx0_4mb_tte;
+ unsigned long __reserved2[2];
+ unsigned long immu_tsb_hits_ctx0_256mb_tte;
+ unsigned long immu_tsb_ticks_ctx0_256mb_tte;
+ unsigned long __reserved3[4];
+ unsigned long immu_tsb_hits_ctxnon0_8k_tte;
+ unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
+ unsigned long immu_tsb_hits_ctxnon0_64k_tte;
+ unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
+ unsigned long __reserved4[2];
+ unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
+ unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
+ unsigned long __reserved5[2];
+ unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
+ unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
+ unsigned long __reserved6[4];
+ unsigned long dmmu_tsb_hits_ctx0_8k_tte;
+ unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
+ unsigned long dmmu_tsb_hits_ctx0_64k_tte;
+ unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
+ unsigned long __reserved7[2];
+ unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
+ unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
+ unsigned long __reserved8[2];
+ unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
+ unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
+ unsigned long __reserved9[4];
+ unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
+ unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
+ unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
+ unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
+ unsigned long __reserved10[2];
+ unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
+ unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
+ unsigned long __reserved11[2];
+ unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
+ unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
+ unsigned long __reserved12[4];
+};
+#endif
+
+/* mmustat_conf()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMUSTAT_CONF
+ * ARG0: real address
+ * RET0: status
+ * RET1: real address
+ * ERRORS: ENORADDR Invalid real address
+ * EBADALIGN Real address not aligned on 64-byte boundary
+ * EBADTRAP API not supported on this processor
+ *
+ * Enable MMU statistic gathering using the buffer at the given real
+ * address on the current virtual CPU. The new buffer real address
+ * is given in ARG1, and the previously specified buffer real address
+ * is returned in RET1, or is returned as zero for the first invocation.
+ *
+ * If the passed in real address argument is zero, this will disable
+ * MMU statistic collection on the current virtual CPU. If an error is
+ * returned then no statistics are collected.
+ *
+ * The buffer contents should be initialized to all zeros before being
+ * given to the hypervisor or else the statistics will be meaningless.
+ */
+#define HV_FAST_MMUSTAT_CONF 0x102
+
+/* mmustat_info()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_MMUSTAT_INFO
+ * RET0: status
+ * RET1: real address
+ * ERRORS: EBADTRAP API not supported on this processor
+ *
+ * Return the current state and real address of the currently configured
+ * MMU statistics buffer on the current virtual CPU.
+ */
+#define HV_FAST_MMUSTAT_INFO 0x103
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mmustat_conf(unsigned long ra, unsigned long *orig_ra);
+extern unsigned long sun4v_mmustat_info(unsigned long *ra);
+#endif
+
+/* NCS crypto services */
+
+/* ncs_request() sub-function numbers */
+#define HV_NCS_QCONF 0x01
+#define HV_NCS_QTAIL_UPDATE 0x02
+
+#ifndef __ASSEMBLY__
+struct hv_ncs_queue_entry {
+ /* MAU Control Register */
+ unsigned long mau_control;
+#define MAU_CONTROL_INV_PARITY 0x0000000000002000
+#define MAU_CONTROL_STRAND 0x0000000000001800
+#define MAU_CONTROL_BUSY 0x0000000000000400
+#define MAU_CONTROL_INT 0x0000000000000200
+#define MAU_CONTROL_OP 0x00000000000001c0
+#define MAU_CONTROL_OP_SHIFT 6
+#define MAU_OP_LOAD_MA_MEMORY 0x0
+#define MAU_OP_STORE_MA_MEMORY 0x1
+#define MAU_OP_MODULAR_MULT 0x2
+#define MAU_OP_MODULAR_REDUCE 0x3
+#define MAU_OP_MODULAR_EXP_LOOP 0x4
+#define MAU_CONTROL_LEN 0x000000000000003f
+#define MAU_CONTROL_LEN_SHIFT 0
+
+ /* Real address of bytes to load or store bytes
+ * into/out-of the MAU.
+ */
+ unsigned long mau_mpa;
+
+ /* Modular Arithmetic MA Offset Register. */
+ unsigned long mau_ma;
+
+ /* Modular Arithmetic N Prime Register. */
+ unsigned long mau_np;
+};
+
+struct hv_ncs_qconf_arg {
+ unsigned long mid; /* MAU ID, 1 per core on Niagara */
+ unsigned long base; /* Real address base of queue */
+ unsigned long end; /* Real address end of queue */
+ unsigned long num_ents; /* Number of entries in queue */
+};
+
+struct hv_ncs_qtail_update_arg {
+ unsigned long mid; /* MAU ID, 1 per core on Niagara */
+ unsigned long tail; /* New tail index to use */
+ unsigned long syncflag; /* only SYNCFLAG_SYNC is implemented */
+#define HV_NCS_SYNCFLAG_SYNC 0x00
+#define HV_NCS_SYNCFLAG_ASYNC 0x01
+};
+#endif
+
+/* ncs_request()
+ * TRAP: HV_FAST_TRAP
+ * FUNCTION: HV_FAST_NCS_REQUEST
+ * ARG0: NCS sub-function
+ * ARG1: sub-function argument real address
+ * ARG2: size in bytes of sub-function argument
+ * RET0: status
+ *
+ * The MAU chip of the Niagara processor is not directly accessible
+ * to privileged code, instead it is programmed indirectly via this
+ * hypervisor API.
+ *
+ * The interfaces defines a queue of MAU operations to perform.
+ * Privileged code registers a queue with the hypervisor by invoking
+ * this HVAPI with the HV_NCS_QCONF sub-function, which defines the
+ * base, end, and number of entries of the queue. Each queue entry
+ * contains a MAU register struct block.
+ *
+ * The privileged code then proceeds to add entries to the queue and
+ * then invoke the HV_NCS_QTAIL_UPDATE sub-function. Since only
+ * synchronous operations are supported by the current hypervisor,
+ * HV_NCS_QTAIL_UPDATE will run all the pending queue entries to
+ * completion and return HV_EOK, or return an error code.
+ *
+ * The real address of the sub-function argument must be aligned on at
+ * least an 8-byte boundary.
+ *
+ * The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte
+ * offset, into the queue and must be less than or equal the 'num_ents'
+ * argument given in the HV_NCS_QCONF call.
+ */
+#define HV_FAST_NCS_REQUEST 0x110
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_ncs_request(unsigned long request,
+ unsigned long arg_ra,
+ unsigned long arg_size);
+#endif
+
+#define HV_FAST_FIRE_GET_PERFREG 0x120
+#define HV_FAST_FIRE_SET_PERFREG 0x121
+
+/* Function numbers for HV_CORE_TRAP. */
+#define HV_CORE_SET_VER 0x00
+#define HV_CORE_PUTCHAR 0x01
+#define HV_CORE_EXIT 0x02
+#define HV_CORE_GET_VER 0x03
+
+/* Hypervisor API groups for use with HV_CORE_SET_VER and
+ * HV_CORE_GET_VER.
+ */
+#define HV_GRP_SUN4V 0x0000
+#define HV_GRP_CORE 0x0001
+#define HV_GRP_INTR 0x0002
+#define HV_GRP_SOFT_STATE 0x0003
+#define HV_GRP_PCI 0x0100
+#define HV_GRP_LDOM 0x0101
+#define HV_GRP_SVC_CHAN 0x0102
+#define HV_GRP_NCS 0x0103
+#define HV_GRP_RNG 0x0104
+#define HV_GRP_NIAG_PERF 0x0200
+#define HV_GRP_FIRE_PERF 0x0201
+#define HV_GRP_N2_CPU 0x0202
+#define HV_GRP_NIU 0x0204
+#define HV_GRP_VF_CPU 0x0205
+#define HV_GRP_DIAG 0x0300
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_get_version(unsigned long group,
+ unsigned long *major,
+ unsigned long *minor);
+extern unsigned long sun4v_set_version(unsigned long group,
+ unsigned long major,
+ unsigned long minor,
+ unsigned long *actual_minor);
+
+extern int sun4v_hvapi_register(unsigned long group, unsigned long major,
+ unsigned long *minor);
+extern void sun4v_hvapi_unregister(unsigned long group);
+extern int sun4v_hvapi_get(unsigned long group,
+ unsigned long *major,
+ unsigned long *minor);
+extern void sun4v_hvapi_init(void);
+#endif
+
+#endif /* !(_SPARC64_HYPERVISOR_H) */
--- /dev/null
+/* ide.h: SPARC PCI specific IDE glue.
+ *
+ * Copyright (C) 1997 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
+ * Adaptation from sparc64 version to sparc by Pete Zaitcev.
+ */
+
+#ifndef _SPARC_IDE_H
+#define _SPARC_IDE_H
+
+#ifdef __KERNEL__
+
+#include <asm/io.h>
+#ifdef CONFIG_SPARC64
+#include <asm/pgalloc.h>
+#include <asm/spitfire.h>
+#include <asm/cacheflush.h>
+#include <asm/page.h>
+#else
+#include <asm/pgtable.h>
+#include <asm/psr.h>
+#endif
+
+#define __ide_insl(data_reg, buffer, wcount) \
+ __ide_insw(data_reg, buffer, (wcount)<<1)
+#define __ide_outsl(data_reg, buffer, wcount) \
+ __ide_outsw(data_reg, buffer, (wcount)<<1)
+
+/* On sparc, I/O ports and MMIO registers are accessed identically. */
+#define __ide_mm_insw __ide_insw
+#define __ide_mm_insl __ide_insl
+#define __ide_mm_outsw __ide_outsw
+#define __ide_mm_outsl __ide_outsl
+
+static inline void __ide_insw(void __iomem *port, void *dst, u32 count)
+{
+#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
+ unsigned long end = (unsigned long)dst + (count << 1);
+#endif
+ u16 *ps = dst;
+ u32 *pi;
+
+ if(((unsigned long)ps) & 0x2) {
+ *ps++ = __raw_readw(port);
+ count--;
+ }
+ pi = (u32 *)ps;
+ while(count >= 2) {
+ u32 w;
+
+ w = __raw_readw(port) << 16;
+ w |= __raw_readw(port);
+ *pi++ = w;
+ count -= 2;
+ }
+ ps = (u16 *)pi;
+ if(count)
+ *ps++ = __raw_readw(port);
+
+#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
+ __flush_dcache_range((unsigned long)dst, end);
+#endif
+}
+
+static inline void __ide_outsw(void __iomem *port, const void *src, u32 count)
+{
+#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
+ unsigned long end = (unsigned long)src + (count << 1);
+#endif
+ const u16 *ps = src;
+ const u32 *pi;
+
+ if(((unsigned long)src) & 0x2) {
+ __raw_writew(*ps++, port);
+ count--;
+ }
+ pi = (const u32 *)ps;
+ while(count >= 2) {
+ u32 w;
+
+ w = *pi++;
+ __raw_writew((w >> 16), port);
+ __raw_writew(w, port);
+ count -= 2;
+ }
+ ps = (const u16 *)pi;
+ if(count)
+ __raw_writew(*ps, port);
+
+#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
+ __flush_dcache_range((unsigned long)src, end);
+#endif
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _SPARC_IDE_H */
--- /dev/null
+/*
+ * idprom.h: Macros and defines for idprom routines
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_IDPROM_H
+#define _SPARC_IDPROM_H
+
+#include <linux/types.h>
+
+struct idprom {
+ u8 id_format; /* Format identifier (always 0x01) */
+ u8 id_machtype; /* Machine type */
+ u8 id_ethaddr[6]; /* Hardware ethernet address */
+ s32 id_date; /* Date of manufacture */
+ u32 id_sernum:24; /* Unique serial number */
+ u8 id_cksum; /* Checksum - xor of the data bytes */
+ u8 reserved[16];
+};
+
+extern struct idprom *idprom;
+extern void idprom_init(void);
+
+#endif /* !(_SPARC_IDPROM_H) */
--- /dev/null
+#ifndef _SPARC64_INTR_QUEUE_H
+#define _SPARC64_INTR_QUEUE_H
+
+/* Sun4v interrupt queue registers, accessed via ASI_QUEUE. */
+
+#define INTRQ_CPU_MONDO_HEAD 0x3c0 /* CPU mondo head */
+#define INTRQ_CPU_MONDO_TAIL 0x3c8 /* CPU mondo tail */
+#define INTRQ_DEVICE_MONDO_HEAD 0x3d0 /* Device mondo head */
+#define INTRQ_DEVICE_MONDO_TAIL 0x3d8 /* Device mondo tail */
+#define INTRQ_RESUM_MONDO_HEAD 0x3e0 /* Resumable error mondo head */
+#define INTRQ_RESUM_MONDO_TAIL 0x3e8 /* Resumable error mondo tail */
+#define INTRQ_NONRESUM_MONDO_HEAD 0x3f0 /* Non-resumable error mondo head */
+#define INTRQ_NONRESUM_MONDO_TAIL 0x3f8 /* Non-resumable error mondo head */
+
+#endif /* !(_SPARC64_INTR_QUEUE_H) */
--- /dev/null
+/* io-unit.h: Definitions for the sun4d IO-UNIT.
+ *
+ * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+#ifndef _SPARC_IO_UNIT_H
+#define _SPARC_IO_UNIT_H
+
+#include <linux/spinlock.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+/* The io-unit handles all virtual to physical address translations
+ * that occur between the SBUS and physical memory. Access by
+ * the cpu to IO registers and similar go over the xdbus so are
+ * translated by the on chip SRMMU. The io-unit and the srmmu do
+ * not need to have the same translations at all, in fact most
+ * of the time the translations they handle are a disjunct set.
+ * Basically the io-unit handles all dvma sbus activity.
+ */
+
+/* AIEEE, unlike the nice sun4m, these monsters have
+ fixed DMA range 64M */
+
+#define IOUNIT_DMA_BASE 0xfc000000 /* TOP - 64M */
+#define IOUNIT_DMA_SIZE 0x04000000 /* 64M */
+/* We use last 1M for sparc_dvma_malloc */
+#define IOUNIT_DVMA_SIZE 0x00100000 /* 1M */
+
+/* The format of an iopte in the external page tables */
+#define IOUPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
+#define IOUPTE_CACHE 0x00000080 /* Cached (in Viking/MXCC) */
+/* XXX Jakub, find out how to program SBUS streaming cache on XDBUS/sun4d.
+ * XXX Actually, all you should need to do is find out where the registers
+ * XXX are and copy over the sparc64 implementation I wrote. There may be
+ * XXX some horrible hwbugs though, so be careful. -DaveM
+ */
+#define IOUPTE_STREAM 0x00000040 /* Translation can use streaming cache */
+#define IOUPTE_INTRA 0x00000008 /* SBUS direct slot->slot transfer */
+#define IOUPTE_WRITE 0x00000004 /* Writeable */
+#define IOUPTE_VALID 0x00000002 /* IOPTE is valid */
+#define IOUPTE_PARITY 0x00000001 /* Parity is checked during DVMA */
+
+struct iounit_struct {
+ unsigned long bmap[(IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 3)) / sizeof(unsigned long)];
+ spinlock_t lock;
+ iopte_t *page_table;
+ unsigned long rotor[3];
+ unsigned long limit[4];
+};
+
+#define IOUNIT_BMAP1_START 0x00000000
+#define IOUNIT_BMAP1_END (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 1))
+#define IOUNIT_BMAP2_START IOUNIT_BMAP1_END
+#define IOUNIT_BMAP2_END IOUNIT_BMAP2_START + (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 2))
+#define IOUNIT_BMAPM_START IOUNIT_BMAP2_END
+#define IOUNIT_BMAPM_END ((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT)
+
+extern __u32 iounit_map_dma_init(struct sbus_bus *, int);
+#define iounit_map_dma_finish(sbus, addr, len) mmu_release_scsi_one(addr, len, sbus)
+extern __u32 iounit_map_dma_page(__u32, void *, struct sbus_bus *);
+
+#endif /* !(_SPARC_IO_UNIT_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_IO_H
+#define ___ASM_SPARC_IO_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/io_64.h>
+#else
+#include <asm/io_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef __SPARC_IO_H
+#define __SPARC_IO_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/ioport.h> /* struct resource */
+
+#include <asm/page.h> /* IO address mapping routines need this */
+#include <asm/system.h>
+
+#define page_to_phys(page) (((page) - mem_map) << PAGE_SHIFT)
+
+static inline u32 flip_dword (u32 l)
+{
+ return ((l&0xff)<<24) | (((l>>8)&0xff)<<16) | (((l>>16)&0xff)<<8)| ((l>>24)&0xff);
+}
+
+static inline u16 flip_word (u16 w)
+{
+ return ((w&0xff) << 8) | ((w>>8)&0xff);
+}
+
+#define mmiowb()
+
+/*
+ * Memory mapped I/O to PCI
+ */
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+ return *(__force volatile u8 *)addr;
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+ return *(__force volatile u16 *)addr;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+ return *(__force volatile u32 *)addr;
+}
+
+static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
+{
+ *(__force volatile u8 *)addr = b;
+}
+
+static inline void __raw_writew(u16 w, volatile void __iomem *addr)
+{
+ *(__force volatile u16 *)addr = w;
+}
+
+static inline void __raw_writel(u32 l, volatile void __iomem *addr)
+{
+ *(__force volatile u32 *)addr = l;
+}
+
+static inline u8 __readb(const volatile void __iomem *addr)
+{
+ return *(__force volatile u8 *)addr;
+}
+
+static inline u16 __readw(const volatile void __iomem *addr)
+{
+ return flip_word(*(__force volatile u16 *)addr);
+}
+
+static inline u32 __readl(const volatile void __iomem *addr)
+{
+ return flip_dword(*(__force volatile u32 *)addr);
+}
+
+static inline void __writeb(u8 b, volatile void __iomem *addr)
+{
+ *(__force volatile u8 *)addr = b;
+}
+
+static inline void __writew(u16 w, volatile void __iomem *addr)
+{
+ *(__force volatile u16 *)addr = flip_word(w);
+}
+
+static inline void __writel(u32 l, volatile void __iomem *addr)
+{
+ *(__force volatile u32 *)addr = flip_dword(l);
+}
+
+#define readb(__addr) __readb(__addr)
+#define readw(__addr) __readw(__addr)
+#define readl(__addr) __readl(__addr)
+#define readb_relaxed(__addr) readb(__addr)
+#define readw_relaxed(__addr) readw(__addr)
+#define readl_relaxed(__addr) readl(__addr)
+
+#define writeb(__b, __addr) __writeb((__b),(__addr))
+#define writew(__w, __addr) __writew((__w),(__addr))
+#define writel(__l, __addr) __writel((__l),(__addr))
+
+/*
+ * I/O space operations
+ *
+ * Arrangement on a Sun is somewhat complicated.
+ *
+ * First of all, we want to use standard Linux drivers
+ * for keyboard, PC serial, etc. These drivers think
+ * they access I/O space and use inb/outb.
+ * On the other hand, EBus bridge accepts PCI *memory*
+ * cycles and converts them into ISA *I/O* cycles.
+ * Ergo, we want inb & outb to generate PCI memory cycles.
+ *
+ * If we want to issue PCI *I/O* cycles, we do this
+ * with a low 64K fixed window in PCIC. This window gets
+ * mapped somewhere into virtual kernel space and we
+ * can use inb/outb again.
+ */
+#define inb_local(__addr) __readb((void __iomem *)(unsigned long)(__addr))
+#define inb(__addr) __readb((void __iomem *)(unsigned long)(__addr))
+#define inw(__addr) __readw((void __iomem *)(unsigned long)(__addr))
+#define inl(__addr) __readl((void __iomem *)(unsigned long)(__addr))
+
+#define outb_local(__b, __addr) __writeb(__b, (void __iomem *)(unsigned long)(__addr))
+#define outb(__b, __addr) __writeb(__b, (void __iomem *)(unsigned long)(__addr))
+#define outw(__w, __addr) __writew(__w, (void __iomem *)(unsigned long)(__addr))
+#define outl(__l, __addr) __writel(__l, (void __iomem *)(unsigned long)(__addr))
+
+#define inb_p(__addr) inb(__addr)
+#define outb_p(__b, __addr) outb(__b, __addr)
+#define inw_p(__addr) inw(__addr)
+#define outw_p(__w, __addr) outw(__w, __addr)
+#define inl_p(__addr) inl(__addr)
+#define outl_p(__l, __addr) outl(__l, __addr)
+
+void outsb(unsigned long addr, const void *src, unsigned long cnt);
+void outsw(unsigned long addr, const void *src, unsigned long cnt);
+void outsl(unsigned long addr, const void *src, unsigned long cnt);
+void insb(unsigned long addr, void *dst, unsigned long count);
+void insw(unsigned long addr, void *dst, unsigned long count);
+void insl(unsigned long addr, void *dst, unsigned long count);
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * SBus accessors.
+ *
+ * SBus has only one, memory mapped, I/O space.
+ * We do not need to flip bytes for SBus of course.
+ */
+static inline u8 _sbus_readb(const volatile void __iomem *addr)
+{
+ return *(__force volatile u8 *)addr;
+}
+
+static inline u16 _sbus_readw(const volatile void __iomem *addr)
+{
+ return *(__force volatile u16 *)addr;
+}
+
+static inline u32 _sbus_readl(const volatile void __iomem *addr)
+{
+ return *(__force volatile u32 *)addr;
+}
+
+static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
+{
+ *(__force volatile u8 *)addr = b;
+}
+
+static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
+{
+ *(__force volatile u16 *)addr = w;
+}
+
+static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
+{
+ *(__force volatile u32 *)addr = l;
+}
+
+/*
+ * The only reason for #define's is to hide casts to unsigned long.
+ */
+#define sbus_readb(__addr) _sbus_readb(__addr)
+#define sbus_readw(__addr) _sbus_readw(__addr)
+#define sbus_readl(__addr) _sbus_readl(__addr)
+#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr)
+#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr)
+#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
+
+static inline void sbus_memset_io(volatile void __iomem *__dst, int c, __kernel_size_t n)
+{
+ while(n--) {
+ sbus_writeb(c, __dst);
+ __dst++;
+ }
+}
+
+static inline void
+_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
+{
+ volatile void __iomem *d = dst;
+
+ while (n--) {
+ writeb(c, d);
+ d++;
+ }
+}
+
+#define memset_io(d,c,sz) _memset_io(d,c,sz)
+
+static inline void
+_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
+{
+ char *d = dst;
+
+ while (n--) {
+ char tmp = readb(src);
+ *d++ = tmp;
+ src++;
+ }
+}
+
+#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
+
+static inline void
+_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
+{
+ const char *s = src;
+ volatile void __iomem *d = dst;
+
+ while (n--) {
+ char tmp = *s++;
+ writeb(tmp, d);
+ d++;
+ }
+}
+
+#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
+
+#ifdef __KERNEL__
+
+/*
+ * Bus number may be embedded in the higher bits of the physical address.
+ * This is why we have no bus number argument to ioremap().
+ */
+extern void __iomem *ioremap(unsigned long offset, unsigned long size);
+#define ioremap_nocache(X,Y) ioremap((X),(Y))
+#define ioremap_wc(X,Y) ioremap((X),(Y))
+extern void iounmap(volatile void __iomem *addr);
+
+#define ioread8(X) readb(X)
+#define ioread16(X) readw(X)
+#define ioread32(X) readl(X)
+#define iowrite8(val,X) writeb(val,X)
+#define iowrite16(val,X) writew(val,X)
+#define iowrite32(val,X) writel(val,X)
+
+static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
+{
+ insb((unsigned long __force)port, buf, count);
+}
+static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
+{
+ insw((unsigned long __force)port, buf, count);
+}
+
+static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
+{
+ insl((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+ outsb((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+ outsw((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+ outsl((unsigned long __force)port, buf, count);
+}
+
+/* Create a virtual mapping cookie for an IO port range */
+extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+extern void ioport_unmap(void __iomem *);
+
+/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+struct pci_dev;
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
+
+/*
+ * Bus number may be in res->flags... somewhere.
+ */
+extern void __iomem *sbus_ioremap(struct resource *res, unsigned long offset,
+ unsigned long size, char *name);
+extern void sbus_iounmap(volatile void __iomem *vaddr, unsigned long size);
+
+
+/*
+ * At the moment, we do not use CMOS_READ anywhere outside of rtc.c,
+ * so rtc_port is static in it. This should not change unless a new
+ * hardware pops up.
+ */
+#define RTC_PORT(x) (rtc_port + (x))
+#define RTC_ALWAYS_BCD 0
+
+#endif
+
+#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p) __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p) p
+
+#endif /* !(__SPARC_IO_H) */
--- /dev/null
+#ifndef __SPARC64_IO_H
+#define __SPARC64_IO_H
+
+#include <linux/kernel.h>
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#include <asm/page.h> /* IO address mapping routines need this */
+#include <asm/system.h>
+#include <asm/asi.h>
+
+/* PC crapola... */
+#define __SLOW_DOWN_IO do { } while (0)
+#define SLOW_DOWN_IO do { } while (0)
+
+/* BIO layer definitions. */
+extern unsigned long kern_base, kern_size;
+#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
+
+static inline u8 _inb(unsigned long addr)
+{
+ u8 ret;
+
+ __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+
+ return ret;
+}
+
+static inline u16 _inw(unsigned long addr)
+{
+ u16 ret;
+
+ __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+
+ return ret;
+}
+
+static inline u32 _inl(unsigned long addr)
+{
+ u32 ret;
+
+ __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+
+ return ret;
+}
+
+static inline void _outb(u8 b, unsigned long addr)
+{
+ __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
+ : /* no outputs */
+ : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+}
+
+static inline void _outw(u16 w, unsigned long addr)
+{
+ __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
+ : /* no outputs */
+ : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+}
+
+static inline void _outl(u32 l, unsigned long addr)
+{
+ __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
+ : /* no outputs */
+ : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+}
+
+#define inb(__addr) (_inb((unsigned long)(__addr)))
+#define inw(__addr) (_inw((unsigned long)(__addr)))
+#define inl(__addr) (_inl((unsigned long)(__addr)))
+#define outb(__b, __addr) (_outb((u8)(__b), (unsigned long)(__addr)))
+#define outw(__w, __addr) (_outw((u16)(__w), (unsigned long)(__addr)))
+#define outl(__l, __addr) (_outl((u32)(__l), (unsigned long)(__addr)))
+
+#define inb_p(__addr) inb(__addr)
+#define outb_p(__b, __addr) outb(__b, __addr)
+#define inw_p(__addr) inw(__addr)
+#define outw_p(__w, __addr) outw(__w, __addr)
+#define inl_p(__addr) inl(__addr)
+#define outl_p(__l, __addr) outl(__l, __addr)
+
+extern void outsb(unsigned long, const void *, unsigned long);
+extern void outsw(unsigned long, const void *, unsigned long);
+extern void outsl(unsigned long, const void *, unsigned long);
+extern void insb(unsigned long, void *, unsigned long);
+extern void insw(unsigned long, void *, unsigned long);
+extern void insl(unsigned long, void *, unsigned long);
+
+static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
+{
+ insb((unsigned long __force)port, buf, count);
+}
+static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
+{
+ insw((unsigned long __force)port, buf, count);
+}
+
+static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
+{
+ insl((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+ outsb((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+ outsw((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+ outsl((unsigned long __force)port, buf, count);
+}
+
+/* Memory functions, same as I/O accesses on Ultra. */
+static inline u8 _readb(const volatile void __iomem *addr)
+{ u8 ret;
+
+ __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+ return ret;
+}
+
+static inline u16 _readw(const volatile void __iomem *addr)
+{ u16 ret;
+
+ __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+
+ return ret;
+}
+
+static inline u32 _readl(const volatile void __iomem *addr)
+{ u32 ret;
+
+ __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+
+ return ret;
+}
+
+static inline u64 _readq(const volatile void __iomem *addr)
+{ u64 ret;
+
+ __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+
+ return ret;
+}
+
+static inline void _writeb(u8 b, volatile void __iomem *addr)
+{
+ __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
+ : /* no outputs */
+ : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+}
+
+static inline void _writew(u16 w, volatile void __iomem *addr)
+{
+ __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
+ : /* no outputs */
+ : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+}
+
+static inline void _writel(u32 l, volatile void __iomem *addr)
+{
+ __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
+ : /* no outputs */
+ : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+}
+
+static inline void _writeq(u64 q, volatile void __iomem *addr)
+{
+ __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
+ : /* no outputs */
+ : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+ : "memory");
+}
+
+#define readb(__addr) _readb(__addr)
+#define readw(__addr) _readw(__addr)
+#define readl(__addr) _readl(__addr)
+#define readq(__addr) _readq(__addr)
+#define readb_relaxed(__addr) _readb(__addr)
+#define readw_relaxed(__addr) _readw(__addr)
+#define readl_relaxed(__addr) _readl(__addr)
+#define readq_relaxed(__addr) _readq(__addr)
+#define writeb(__b, __addr) _writeb(__b, __addr)
+#define writew(__w, __addr) _writew(__w, __addr)
+#define writel(__l, __addr) _writel(__l, __addr)
+#define writeq(__q, __addr) _writeq(__q, __addr)
+
+/* Now versions without byte-swapping. */
+static inline u8 _raw_readb(unsigned long addr)
+{
+ u8 ret;
+
+ __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+ return ret;
+}
+
+static inline u16 _raw_readw(unsigned long addr)
+{
+ u16 ret;
+
+ __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+ return ret;
+}
+
+static inline u32 _raw_readl(unsigned long addr)
+{
+ u32 ret;
+
+ __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+ return ret;
+}
+
+static inline u64 _raw_readq(unsigned long addr)
+{
+ u64 ret;
+
+ __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+ return ret;
+}
+
+static inline void _raw_writeb(u8 b, unsigned long addr)
+{
+ __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
+ : /* no outputs */
+ : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+static inline void _raw_writew(u16 w, unsigned long addr)
+{
+ __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
+ : /* no outputs */
+ : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+static inline void _raw_writel(u32 l, unsigned long addr)
+{
+ __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
+ : /* no outputs */
+ : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+static inline void _raw_writeq(u64 q, unsigned long addr)
+{
+ __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
+ : /* no outputs */
+ : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+#define __raw_readb(__addr) (_raw_readb((unsigned long)(__addr)))
+#define __raw_readw(__addr) (_raw_readw((unsigned long)(__addr)))
+#define __raw_readl(__addr) (_raw_readl((unsigned long)(__addr)))
+#define __raw_readq(__addr) (_raw_readq((unsigned long)(__addr)))
+#define __raw_writeb(__b, __addr) (_raw_writeb((u8)(__b), (unsigned long)(__addr)))
+#define __raw_writew(__w, __addr) (_raw_writew((u16)(__w), (unsigned long)(__addr)))
+#define __raw_writel(__l, __addr) (_raw_writel((u32)(__l), (unsigned long)(__addr)))
+#define __raw_writeq(__q, __addr) (_raw_writeq((u64)(__q), (unsigned long)(__addr)))
+
+/* Valid I/O Space regions are anywhere, because each PCI bus supported
+ * can live in an arbitrary area of the physical address range.
+ */
+#define IO_SPACE_LIMIT 0xffffffffffffffffUL
+
+/* Now, SBUS variants, only difference from PCI is that we do
+ * not use little-endian ASIs.
+ */
+static inline u8 _sbus_readb(const volatile void __iomem *addr)
+{
+ u8 ret;
+
+ __asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+ : "memory");
+
+ return ret;
+}
+
+static inline u16 _sbus_readw(const volatile void __iomem *addr)
+{
+ u16 ret;
+
+ __asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+ : "memory");
+
+ return ret;
+}
+
+static inline u32 _sbus_readl(const volatile void __iomem *addr)
+{
+ u32 ret;
+
+ __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+ : "memory");
+
+ return ret;
+}
+
+static inline u64 _sbus_readq(const volatile void __iomem *addr)
+{
+ u64 ret;
+
+ __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+ : "memory");
+
+ return ret;
+}
+
+static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
+{
+ __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
+ : /* no outputs */
+ : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+ : "memory");
+}
+
+static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
+{
+ __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
+ : /* no outputs */
+ : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+ : "memory");
+}
+
+static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
+{
+ __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
+ : /* no outputs */
+ : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+ : "memory");
+}
+
+static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
+{
+ __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
+ : /* no outputs */
+ : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+ : "memory");
+}
+
+#define sbus_readb(__addr) _sbus_readb(__addr)
+#define sbus_readw(__addr) _sbus_readw(__addr)
+#define sbus_readl(__addr) _sbus_readl(__addr)
+#define sbus_readq(__addr) _sbus_readq(__addr)
+#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr)
+#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr)
+#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
+#define sbus_writeq(__l, __addr) _sbus_writeq(__l, __addr)
+
+static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
+{
+ while(n--) {
+ sbus_writeb(c, dst);
+ dst++;
+ }
+}
+
+#define sbus_memset_io(d,c,sz) _sbus_memset_io(d,c,sz)
+
+static inline void
+_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
+{
+ volatile void __iomem *d = dst;
+
+ while (n--) {
+ writeb(c, d);
+ d++;
+ }
+}
+
+#define memset_io(d,c,sz) _memset_io(d,c,sz)
+
+static inline void
+_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
+{
+ char *d = dst;
+
+ while (n--) {
+ char tmp = readb(src);
+ *d++ = tmp;
+ src++;
+ }
+}
+
+#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
+
+static inline void
+_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
+{
+ const char *s = src;
+ volatile void __iomem *d = dst;
+
+ while (n--) {
+ char tmp = *s++;
+ writeb(tmp, d);
+ d++;
+ }
+}
+
+#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
+
+#define mmiowb()
+
+#ifdef __KERNEL__
+
+/* On sparc64 we have the whole physical IO address space accessible
+ * using physically addressed loads and stores, so this does nothing.
+ */
+static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
+{
+ return (void __iomem *)offset;
+}
+
+#define ioremap_nocache(X,Y) ioremap((X),(Y))
+#define ioremap_wc(X,Y) ioremap((X),(Y))
+
+static inline void iounmap(volatile void __iomem *addr)
+{
+}
+
+#define ioread8(X) readb(X)
+#define ioread16(X) readw(X)
+#define ioread32(X) readl(X)
+#define iowrite8(val,X) writeb(val,X)
+#define iowrite16(val,X) writew(val,X)
+#define iowrite32(val,X) writel(val,X)
+
+/* Create a virtual mapping cookie for an IO port range */
+extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+extern void ioport_unmap(void __iomem *);
+
+/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+struct pci_dev;
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
+
+/* Similarly for SBUS. */
+#define sbus_ioremap(__res, __offset, __size, __name) \
+({ unsigned long __ret; \
+ __ret = (__res)->start + (((__res)->flags & 0x1ffUL) << 32UL); \
+ __ret += (unsigned long) (__offset); \
+ if (! request_region((__ret), (__size), (__name))) \
+ __ret = 0UL; \
+ (void __iomem *) __ret; \
+})
+
+#define sbus_iounmap(__addr, __size) \
+ release_region((unsigned long)(__addr), (__size))
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p) __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p) p
+
+#endif
+
+#endif /* !(__SPARC64_IO_H) */
--- /dev/null
+#ifndef _SPARC_IOCTL_H
+#define _SPARC_IOCTL_H
+
+/*
+ * Our DIR and SIZE overlap in order to simulteneously provide
+ * a non-zero _IOC_NONE (for binary compatibility) and
+ * 14 bits of size as on i386. Here's the layout:
+ *
+ * 0xE0000000 DIR
+ * 0x80000000 DIR = WRITE
+ * 0x40000000 DIR = READ
+ * 0x20000000 DIR = NONE
+ * 0x3FFF0000 SIZE (overlaps NONE bit)
+ * 0x0000FF00 TYPE
+ * 0x000000FF NR (CMD)
+ */
+
+#define _IOC_NRBITS 8
+#define _IOC_TYPEBITS 8
+#define _IOC_SIZEBITS 13 /* Actually 14, see below. */
+#define _IOC_DIRBITS 3
+
+#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
+#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
+#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
+#define _IOC_XSIZEMASK ((1 << (_IOC_SIZEBITS+1))-1)
+#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
+
+#define _IOC_NRSHIFT 0
+#define _IOC_TYPESHIFT (_IOC_NRSHIFT + _IOC_NRBITS)
+#define _IOC_SIZESHIFT (_IOC_TYPESHIFT + _IOC_TYPEBITS)
+#define _IOC_DIRSHIFT (_IOC_SIZESHIFT + _IOC_SIZEBITS)
+
+#define _IOC_NONE 1U
+#define _IOC_READ 2U
+#define _IOC_WRITE 4U
+
+#define _IOC(dir,type,nr,size) \
+ (((dir) << _IOC_DIRSHIFT) | \
+ ((type) << _IOC_TYPESHIFT) | \
+ ((nr) << _IOC_NRSHIFT) | \
+ ((size) << _IOC_SIZESHIFT))
+
+#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
+#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
+#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
+#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
+
+/* Used to decode ioctl numbers in drivers despite the leading underscore... */
+#define _IOC_DIR(nr) \
+ ( (((((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) & (_IOC_WRITE|_IOC_READ)) != 0)? \
+ (((nr) >> _IOC_DIRSHIFT) & (_IOC_WRITE|_IOC_READ)): \
+ (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) )
+#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
+#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
+#define _IOC_SIZE(nr) \
+ ((((((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) & (_IOC_WRITE|_IOC_READ)) == 0)? \
+ 0: (((nr) >> _IOC_SIZESHIFT) & _IOC_XSIZEMASK))
+
+/* ...and for the PCMCIA and sound. */
+#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
+#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
+#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
+#define IOCSIZE_MASK (_IOC_XSIZEMASK << _IOC_SIZESHIFT)
+#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
+
+#endif /* !(_SPARC_IOCTL_H) */
--- /dev/null
+#ifndef _ASM_SPARC_IOCTLS_H
+#define _ASM_SPARC_IOCTLS_H
+
+#include <asm/ioctl.h>
+
+/* Big T */
+#define TCGETA _IOR('T', 1, struct termio)
+#define TCSETA _IOW('T', 2, struct termio)
+#define TCSETAW _IOW('T', 3, struct termio)
+#define TCSETAF _IOW('T', 4, struct termio)
+#define TCSBRK _IO('T', 5)
+#define TCXONC _IO('T', 6)
+#define TCFLSH _IO('T', 7)
+#define TCGETS _IOR('T', 8, struct termios)
+#define TCSETS _IOW('T', 9, struct termios)
+#define TCSETSW _IOW('T', 10, struct termios)
+#define TCSETSF _IOW('T', 11, struct termios)
+#define TCGETS2 _IOR('T', 12, struct termios2)
+#define TCSETS2 _IOW('T', 13, struct termios2)
+#define TCSETSW2 _IOW('T', 14, struct termios2)
+#define TCSETSF2 _IOW('T', 15, struct termios2)
+
+/* Note that all the ioctls that are not available in Linux have a
+ * double underscore on the front to: a) avoid some programs to
+ * think we support some ioctls under Linux (autoconfiguration stuff)
+ */
+/* Little t */
+#define TIOCGETD _IOR('t', 0, int)
+#define TIOCSETD _IOW('t', 1, int)
+#define __TIOCHPCL _IO('t', 2) /* SunOS Specific */
+#define __TIOCMODG _IOR('t', 3, int) /* SunOS Specific */
+#define __TIOCMODS _IOW('t', 4, int) /* SunOS Specific */
+#define __TIOCGETP _IOR('t', 8, struct sgttyb) /* SunOS Specific */
+#define __TIOCSETP _IOW('t', 9, struct sgttyb) /* SunOS Specific */
+#define __TIOCSETN _IOW('t', 10, struct sgttyb) /* SunOS Specific */
+#define TIOCEXCL _IO('t', 13)
+#define TIOCNXCL _IO('t', 14)
+#define __TIOCFLUSH _IOW('t', 16, int) /* SunOS Specific */
+#define __TIOCSETC _IOW('t', 17, struct tchars) /* SunOS Specific */
+#define __TIOCGETC _IOR('t', 18, struct tchars) /* SunOS Specific */
+#define __TIOCTCNTL _IOW('t', 32, int) /* SunOS Specific */
+#define __TIOCSIGNAL _IOW('t', 33, int) /* SunOS Specific */
+#define __TIOCSETX _IOW('t', 34, int) /* SunOS Specific */
+#define __TIOCGETX _IOR('t', 35, int) /* SunOS Specific */
+#define TIOCCONS _IO('t', 36)
+#define TIOCGSOFTCAR _IOR('t', 100, int)
+#define TIOCSSOFTCAR _IOW('t', 101, int)
+#define __TIOCUCNTL _IOW('t', 102, int) /* SunOS Specific */
+#define TIOCSWINSZ _IOW('t', 103, struct winsize)
+#define TIOCGWINSZ _IOR('t', 104, struct winsize)
+#define __TIOCREMOTE _IOW('t', 105, int) /* SunOS Specific */
+#define TIOCMGET _IOR('t', 106, int)
+#define TIOCMBIC _IOW('t', 107, int)
+#define TIOCMBIS _IOW('t', 108, int)
+#define TIOCMSET _IOW('t', 109, int)
+#define TIOCSTART _IO('t', 110)
+#define TIOCSTOP _IO('t', 111)
+#define TIOCPKT _IOW('t', 112, int)
+#define TIOCNOTTY _IO('t', 113)
+#define TIOCSTI _IOW('t', 114, char)
+#define TIOCOUTQ _IOR('t', 115, int)
+#define __TIOCGLTC _IOR('t', 116, struct ltchars) /* SunOS Specific */
+#define __TIOCSLTC _IOW('t', 117, struct ltchars) /* SunOS Specific */
+/* 118 is the non-posix setpgrp tty ioctl */
+/* 119 is the non-posix getpgrp tty ioctl */
+#define __TIOCCDTR _IO('t', 120) /* SunOS Specific */
+#define __TIOCSDTR _IO('t', 121) /* SunOS Specific */
+#define TIOCCBRK _IO('t', 122)
+#define TIOCSBRK _IO('t', 123)
+#define __TIOCLGET _IOW('t', 124, int) /* SunOS Specific */
+#define __TIOCLSET _IOW('t', 125, int) /* SunOS Specific */
+#define __TIOCLBIC _IOW('t', 126, int) /* SunOS Specific */
+#define __TIOCLBIS _IOW('t', 127, int) /* SunOS Specific */
+#define __TIOCISPACE _IOR('t', 128, int) /* SunOS Specific */
+#define __TIOCISIZE _IOR('t', 129, int) /* SunOS Specific */
+#define TIOCSPGRP _IOW('t', 130, int)
+#define TIOCGPGRP _IOR('t', 131, int)
+#define TIOCSCTTY _IO('t', 132)
+#define TIOCGSID _IOR('t', 133, int)
+/* Get minor device of a pty master's FD -- Solaris equiv is ISPTM */
+#define TIOCGPTN _IOR('t', 134, unsigned int) /* Get Pty Number */
+#define TIOCSPTLCK _IOW('t', 135, int) /* Lock/unlock PTY */
+
+/* Little f */
+#define FIOCLEX _IO('f', 1)
+#define FIONCLEX _IO('f', 2)
+#define FIOASYNC _IOW('f', 125, int)
+#define FIONBIO _IOW('f', 126, int)
+#define FIONREAD _IOR('f', 127, int)
+#define TIOCINQ FIONREAD
+#define FIOQSIZE _IOR('f', 128, loff_t)
+
+/* SCARY Rutgers local SunOS kernel hackery, perhaps I will support it
+ * someday. This is completely bogus, I know...
+ */
+#define __TCGETSTAT _IO('T', 200) /* Rutgers specific */
+#define __TCSETSTAT _IO('T', 201) /* Rutgers specific */
+
+/* Linux specific, no SunOS equivalent. */
+#define TIOCLINUX 0x541C
+#define TIOCGSERIAL 0x541E
+#define TIOCSSERIAL 0x541F
+#define TCSBRKP 0x5425
+#define TIOCSERCONFIG 0x5453
+#define TIOCSERGWILD 0x5454
+#define TIOCSERSWILD 0x5455
+#define TIOCGLCKTRMIOS 0x5456
+#define TIOCSLCKTRMIOS 0x5457
+#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
+#define TIOCSERGETLSR 0x5459 /* Get line status register */
+#define TIOCSERGETMULTI 0x545A /* Get multiport config */
+#define TIOCSERSETMULTI 0x545B /* Set multiport config */
+#define TIOCMIWAIT 0x545C /* Wait for change on serial input line(s) */
+#define TIOCGICOUNT 0x545D /* Read serial port inline interrupt counts */
+
+/* Kernel definitions */
+#ifdef __KERNEL__
+#define TIOCGETC __TIOCGETC
+#define TIOCGETP __TIOCGETP
+#define TIOCGLTC __TIOCGLTC
+#define TIOCSLTC __TIOCSLTC
+#define TIOCSETP __TIOCSETP
+#define TIOCSETN __TIOCSETN
+#define TIOCSETC __TIOCSETC
+#endif
+
+/* Used for packet mode */
+#define TIOCPKT_DATA 0
+#define TIOCPKT_FLUSHREAD 1
+#define TIOCPKT_FLUSHWRITE 2
+#define TIOCPKT_STOP 4
+#define TIOCPKT_START 8
+#define TIOCPKT_NOSTOP 16
+#define TIOCPKT_DOSTOP 32
+
+#endif /* !(_ASM_SPARC_IOCTLS_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_IOMMU_H
+#define ___ASM_SPARC_IOMMU_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/iommu_64.h>
+#else
+#include <asm/iommu_32.h>
+#endif
+#endif
--- /dev/null
+/* iommu.h: Definitions for the sun4m IOMMU.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_IOMMU_H
+#define _SPARC_IOMMU_H
+
+#include <asm/page.h>
+#include <asm/bitext.h>
+
+/* The iommu handles all virtual to physical address translations
+ * that occur between the SBUS and physical memory. Access by
+ * the cpu to IO registers and similar go over the mbus so are
+ * translated by the on chip SRMMU. The iommu and the srmmu do
+ * not need to have the same translations at all, in fact most
+ * of the time the translations they handle are a disjunct set.
+ * Basically the iommu handles all dvma sbus activity.
+ */
+
+/* The IOMMU registers occupy three pages in IO space. */
+struct iommu_regs {
+ /* First page */
+ volatile unsigned long control; /* IOMMU control */
+ volatile unsigned long base; /* Physical base of iopte page table */
+ volatile unsigned long _unused1[3];
+ volatile unsigned long tlbflush; /* write only */
+ volatile unsigned long pageflush; /* write only */
+ volatile unsigned long _unused2[1017];
+ /* Second page */
+ volatile unsigned long afsr; /* Async-fault status register */
+ volatile unsigned long afar; /* Async-fault physical address */
+ volatile unsigned long _unused3[2];
+ volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
+ volatile unsigned long sbuscfg1;
+ volatile unsigned long sbuscfg2;
+ volatile unsigned long sbuscfg3;
+ volatile unsigned long mfsr; /* Memory-fault status register */
+ volatile unsigned long mfar; /* Memory-fault physical address */
+ volatile unsigned long _unused4[1014];
+ /* Third page */
+ volatile unsigned long mid; /* IOMMU module-id */
+};
+
+#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
+#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
+#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
+#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
+#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
+#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
+#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
+#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
+#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
+#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
+#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
+#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
+
+#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
+#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
+#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
+#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
+#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
+#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
+#define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
+#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
+#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
+#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
+
+#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
+#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
+#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
+#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
+ produced by this device as pure
+ physical. */
+
+#define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
+#define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
+#define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
+#define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
+#define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
+ on the even word of the access, low bit
+ indicated odd word caused the parity error */
+#define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
+#define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
+#define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
+
+#define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
+#define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
+#define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
+#define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
+#define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
+#define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
+#define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
+
+/* The format of an iopte in the page tables */
+#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
+#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
+#define IOPTE_WRITE 0x00000004 /* Writeable */
+#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
+#define IOPTE_WAZ 0x00000001 /* Write as zeros */
+
+struct iommu_struct {
+ struct iommu_regs *regs;
+ iopte_t *page_table;
+ /* For convenience */
+ unsigned long start; /* First managed virtual address */
+ unsigned long end; /* Last managed virtual address */
+
+ struct bit_map usemap;
+};
+
+static inline void iommu_invalidate(struct iommu_regs *regs)
+{
+ regs->tlbflush = 0;
+}
+
+static inline void iommu_invalidate_page(struct iommu_regs *regs, unsigned long ba)
+{
+ regs->pageflush = (ba & PAGE_MASK);
+}
+
+#endif /* !(_SPARC_IOMMU_H) */
--- /dev/null
+/* iommu.h: Definitions for the sun5 IOMMU.
+ *
+ * Copyright (C) 1996, 1999, 2007 David S. Miller (davem@davemloft.net)
+ */
+#ifndef _SPARC64_IOMMU_H
+#define _SPARC64_IOMMU_H
+
+/* The format of an iopte in the page tables. */
+#define IOPTE_VALID 0x8000000000000000UL
+#define IOPTE_64K 0x2000000000000000UL
+#define IOPTE_STBUF 0x1000000000000000UL
+#define IOPTE_INTRA 0x0800000000000000UL
+#define IOPTE_CONTEXT 0x07ff800000000000UL
+#define IOPTE_PAGE 0x00007fffffffe000UL
+#define IOPTE_CACHE 0x0000000000000010UL
+#define IOPTE_WRITE 0x0000000000000002UL
+
+#define IOMMU_NUM_CTXS 4096
+
+struct iommu_arena {
+ unsigned long *map;
+ unsigned int hint;
+ unsigned int limit;
+};
+
+struct iommu {
+ spinlock_t lock;
+ struct iommu_arena arena;
+ void (*flush_all)(struct iommu *);
+ iopte_t *page_table;
+ u32 page_table_map_base;
+ unsigned long iommu_control;
+ unsigned long iommu_tsbbase;
+ unsigned long iommu_flush;
+ unsigned long iommu_flushinv;
+ unsigned long iommu_tags;
+ unsigned long iommu_ctxflush;
+ unsigned long write_complete_reg;
+ unsigned long dummy_page;
+ unsigned long dummy_page_pa;
+ unsigned long ctx_lowest_free;
+ DECLARE_BITMAP(ctx_bitmap, IOMMU_NUM_CTXS);
+ u32 dma_addr_mask;
+};
+
+struct strbuf {
+ int strbuf_enabled;
+ unsigned long strbuf_control;
+ unsigned long strbuf_pflush;
+ unsigned long strbuf_fsync;
+ unsigned long strbuf_ctxflush;
+ unsigned long strbuf_ctxmatch_base;
+ unsigned long strbuf_flushflag_pa;
+ volatile unsigned long *strbuf_flushflag;
+ volatile unsigned long __flushflag_buf[(64+(64-1)) / sizeof(long)];
+};
+
+extern int iommu_table_init(struct iommu *iommu, int tsbsize,
+ u32 dma_offset, u32 dma_addr_mask,
+ int numa_node);
+
+#endif /* !(_SPARC64_IOMMU_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_IPCBUF_H
+#define ___ASM_SPARC_IPCBUF_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/ipcbuf_64.h>
+#else
+#include <asm/ipcbuf_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _SPARC_IPCBUF_H
+#define _SPARC_IPCBUF_H
+
+/*
+ * The ipc64_perm structure for sparc architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit mode
+ * - 32-bit seq
+ * - 2 miscellaneous 64-bit values (so that this structure matches
+ * sparc64 ipc64_perm)
+ */
+
+struct ipc64_perm
+{
+ __kernel_key_t key;
+ __kernel_uid32_t uid;
+ __kernel_gid32_t gid;
+ __kernel_uid32_t cuid;
+ __kernel_gid32_t cgid;
+ unsigned short __pad1;
+ __kernel_mode_t mode;
+ unsigned short __pad2;
+ unsigned short seq;
+ unsigned long long __unused1;
+ unsigned long long __unused2;
+};
+
+#endif /* _SPARC_IPCBUF_H */
--- /dev/null
+#ifndef _SPARC64_IPCBUF_H
+#define _SPARC64_IPCBUF_H
+
+/*
+ * The ipc64_perm structure for sparc64 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit seq
+ * - 2 miscellaneous 64-bit values
+ */
+
+struct ipc64_perm
+{
+ __kernel_key_t key;
+ __kernel_uid_t uid;
+ __kernel_gid_t gid;
+ __kernel_uid_t cuid;
+ __kernel_gid_t cgid;
+ __kernel_mode_t mode;
+ unsigned short __pad1;
+ unsigned short seq;
+ unsigned long __unused1;
+ unsigned long __unused2;
+};
+
+#endif /* _SPARC64_IPCBUF_H */
--- /dev/null
+#ifndef ___ASM_SPARC_IRQ_H
+#define ___ASM_SPARC_IRQ_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/irq_64.h>
+#else
+#include <asm/irq_32.h>
+#endif
+#endif
--- /dev/null
+/* irq.h: IRQ registers on the Sparc.
+ *
+ * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC_IRQ_H
+#define _SPARC_IRQ_H
+
+#include <linux/interrupt.h>
+
+#define NR_IRQS 16
+
+#define irq_canonicalize(irq) (irq)
+
+#endif
--- /dev/null
+/* irq.h: IRQ registers on the 64-bit Sparc.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
+ */
+
+#ifndef _SPARC64_IRQ_H
+#define _SPARC64_IRQ_H
+
+#include <linux/linkage.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <asm/pil.h>
+#include <asm/ptrace.h>
+
+/* IMAP/ICLR register defines */
+#define IMAP_VALID 0x80000000UL /* IRQ Enabled */
+#define IMAP_TID_UPA 0x7c000000UL /* UPA TargetID */
+#define IMAP_TID_JBUS 0x7c000000UL /* JBUS TargetID */
+#define IMAP_TID_SHIFT 26
+#define IMAP_AID_SAFARI 0x7c000000UL /* Safari AgentID */
+#define IMAP_AID_SHIFT 26
+#define IMAP_NID_SAFARI 0x03e00000UL /* Safari NodeID */
+#define IMAP_NID_SHIFT 21
+#define IMAP_IGN 0x000007c0UL /* IRQ Group Number */
+#define IMAP_INO 0x0000003fUL /* IRQ Number */
+#define IMAP_INR 0x000007ffUL /* Full interrupt number*/
+
+#define ICLR_IDLE 0x00000000UL /* Idle state */
+#define ICLR_TRANSMIT 0x00000001UL /* Transmit state */
+#define ICLR_PENDING 0x00000003UL /* Pending state */
+
+/* The largest number of unique interrupt sources we support.
+ * If this needs to ever be larger than 255, you need to change
+ * the type of ino_bucket->virt_irq as appropriate.
+ *
+ * ino_bucket->virt_irq allocation is made during {sun4v_,}build_irq().
+ */
+#define NR_IRQS 255
+
+extern void irq_install_pre_handler(int virt_irq,
+ void (*func)(unsigned int, void *, void *),
+ void *arg1, void *arg2);
+#define irq_canonicalize(irq) (irq)
+extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
+extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
+extern unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino);
+extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
+ unsigned int msi_devino_start,
+ unsigned int msi_devino_end);
+extern void sun4v_destroy_msi(unsigned int virt_irq);
+extern unsigned int sun4u_build_msi(u32 portid, unsigned int *virt_irq_p,
+ unsigned int msi_devino_start,
+ unsigned int msi_devino_end,
+ unsigned long imap_base,
+ unsigned long iclr_base);
+extern void sun4u_destroy_msi(unsigned int virt_irq);
+extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
+
+extern unsigned char virt_irq_alloc(unsigned int dev_handle,
+ unsigned int dev_ino);
+#ifdef CONFIG_PCI_MSI
+extern void virt_irq_free(unsigned int virt_irq);
+#endif
+
+extern void __init init_IRQ(void);
+extern void fixup_irqs(void);
+
+static inline void set_softint(unsigned long bits)
+{
+ __asm__ __volatile__("wr %0, 0x0, %%set_softint"
+ : /* No outputs */
+ : "r" (bits));
+}
+
+static inline void clear_softint(unsigned long bits)
+{
+ __asm__ __volatile__("wr %0, 0x0, %%clear_softint"
+ : /* No outputs */
+ : "r" (bits));
+}
+
+static inline unsigned long get_softint(void)
+{
+ unsigned long retval;
+
+ __asm__ __volatile__("rd %%softint, %0"
+ : "=r" (retval));
+ return retval;
+}
+
+#endif
--- /dev/null
+#include <asm-generic/irq_regs.h>
--- /dev/null
+#ifndef ___ASM_SPARC_IRQFLAGS_H
+#define ___ASM_SPARC_IRQFLAGS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/irqflags_64.h>
+#else
+#include <asm/irqflags_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * include/asm/irqflags.h
+ *
+ * IRQ flags handling
+ *
+ * This file gets included from lowlevel asm headers too, to provide
+ * wrapped versions of the local_irq_*() APIs, based on the
+ * raw_local_irq_*() functions from the lowlevel headers.
+ */
+#ifndef _ASM_IRQFLAGS_H
+#define _ASM_IRQFLAGS_H
+
+#ifndef __ASSEMBLY__
+
+extern void raw_local_irq_restore(unsigned long);
+extern unsigned long __raw_local_irq_save(void);
+extern void raw_local_irq_enable(void);
+
+static inline unsigned long getipl(void)
+{
+ unsigned long retval;
+
+ __asm__ __volatile__("rd %%psr, %0" : "=r" (retval));
+ return retval;
+}
+
+#define raw_local_save_flags(flags) ((flags) = getipl())
+#define raw_local_irq_save(flags) ((flags) = __raw_local_irq_save())
+#define raw_local_irq_disable() ((void) __raw_local_irq_save())
+#define raw_irqs_disabled() ((getipl() & PSR_PIL) != 0)
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+ return ((flags & PSR_PIL) != 0);
+}
+
+#endif /* (__ASSEMBLY__) */
+
+#endif /* !(_ASM_IRQFLAGS_H) */
--- /dev/null
+/*
+ * include/asm/irqflags.h
+ *
+ * IRQ flags handling
+ *
+ * This file gets included from lowlevel asm headers too, to provide
+ * wrapped versions of the local_irq_*() APIs, based on the
+ * raw_local_irq_*() functions from the lowlevel headers.
+ */
+#ifndef _ASM_IRQFLAGS_H
+#define _ASM_IRQFLAGS_H
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned long __raw_local_save_flags(void)
+{
+ unsigned long flags;
+
+ __asm__ __volatile__(
+ "rdpr %%pil, %0"
+ : "=r" (flags)
+ );
+
+ return flags;
+}
+
+#define raw_local_save_flags(flags) \
+ do { (flags) = __raw_local_save_flags(); } while (0)
+
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+ __asm__ __volatile__(
+ "wrpr %0, %%pil"
+ : /* no output */
+ : "r" (flags)
+ : "memory"
+ );
+}
+
+static inline void raw_local_irq_disable(void)
+{
+ __asm__ __volatile__(
+ "wrpr 15, %%pil"
+ : /* no outputs */
+ : /* no inputs */
+ : "memory"
+ );
+}
+
+static inline void raw_local_irq_enable(void)
+{
+ __asm__ __volatile__(
+ "wrpr 0, %%pil"
+ : /* no outputs */
+ : /* no inputs */
+ : "memory"
+ );
+}
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+ return (flags > 0);
+}
+
+static inline int raw_irqs_disabled(void)
+{
+ unsigned long flags = __raw_local_save_flags();
+
+ return raw_irqs_disabled_flags(flags);
+}
+
+/*
+ * For spinlocks, etc:
+ */
+static inline unsigned long __raw_local_irq_save(void)
+{
+ unsigned long flags = __raw_local_save_flags();
+
+ raw_local_irq_disable();
+
+ return flags;
+}
+
+#define raw_local_irq_save(flags) \
+ do { (flags) = __raw_local_irq_save(); } while (0)
+
+#endif /* (__ASSEMBLY__) */
+
+#endif /* !(_ASM_IRQFLAGS_H) */
--- /dev/null
+/*
+ * jsflash.h: OS Flash SIMM support for JavaStations.
+ *
+ * Copyright (C) 1999 Pete Zaitcev
+ */
+
+#ifndef _SPARC_JSFLASH_H
+#define _SPARC_JSFLASH_H
+
+#ifndef _SPARC_TYPES_H
+#include <asm/types.h>
+#endif
+
+/*
+ * Semantics of the offset is a full address.
+ * Hardcode it or get it from probe ioctl.
+ *
+ * We use full bus address, so that we would be
+ * automatically compatible with possible future systems.
+ */
+
+#define JSFLASH_IDENT (('F'<<8)|54)
+struct jsflash_ident_arg {
+ __u64 off; /* 0x20000000 is included */
+ __u32 size;
+ char name[32]; /* With trailing zero */
+};
+
+#define JSFLASH_ERASE (('F'<<8)|55)
+/* Put 0 as argument, may be flags or sector number... */
+
+#define JSFLASH_PROGRAM (('F'<<8)|56)
+struct jsflash_program_arg {
+ __u64 data; /* char* for sparc and sparc64 */
+ __u64 off;
+ __u32 size;
+};
+
+#endif /* _SPARC_JSFLASH_H */
--- /dev/null
+#ifndef ___ASM_SPARC_KDEBUG_H
+#define ___ASM_SPARC_KDEBUG_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/kdebug_64.h>
+#else
+#include <asm/kdebug_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * kdebug.h: Defines and definitions for debugging the Linux kernel
+ * under various kernel debuggers.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_KDEBUG_H
+#define _SPARC_KDEBUG_H
+
+#include <asm/openprom.h>
+#include <asm/vaddrs.h>
+
+/* Breakpoints are enter through trap table entry 126. So in sparc assembly
+ * if you want to drop into the debugger you do:
+ *
+ * t DEBUG_BP_TRAP
+ */
+
+#define DEBUG_BP_TRAP 126
+
+#ifndef __ASSEMBLY__
+/* The debug vector is passed in %o1 at boot time. It is a pointer to
+ * a structure in the debuggers address space. Here is its format.
+ */
+
+typedef unsigned int (*debugger_funct)(void);
+
+struct kernel_debug {
+ /* First the entry point into the debugger. You jump here
+ * to give control over to the debugger.
+ */
+ unsigned long kdebug_entry;
+ unsigned long kdebug_trapme; /* Figure out later... */
+ /* The following is the number of pages that the debugger has
+ * taken from to total pool.
+ */
+ unsigned long *kdebug_stolen_pages;
+ /* Ok, after you remap yourself and/or change the trap table
+ * from what you were left with at boot time you have to call
+ * this synchronization function so the debugger can check out
+ * what you have done.
+ */
+ debugger_funct teach_debugger;
+}; /* I think that is it... */
+
+extern struct kernel_debug *linux_dbvec;
+
+/* Use this macro in C-code to enter the debugger. */
+static inline void sp_enter_debugger(void)
+{
+ __asm__ __volatile__("jmpl %0, %%o7\n\t"
+ "nop\n\t" : :
+ "r" (linux_dbvec) : "o7", "memory");
+}
+
+#define SP_ENTER_DEBUGGER do { \
+ if((linux_dbvec!=0) && ((*(short *)linux_dbvec)!=-1)) \
+ sp_enter_debugger(); \
+ } while(0)
+
+enum die_val {
+ DIE_UNUSED,
+};
+
+#endif /* !(__ASSEMBLY__) */
+
+/* Some nice offset defines for assembler code. */
+#define KDEBUG_ENTRY_OFF 0x0
+#define KDEBUG_DUNNO_OFF 0x4
+#define KDEBUG_DUNNO2_OFF 0x8
+#define KDEBUG_TEACH_OFF 0xc
+
+#endif /* !(_SPARC_KDEBUG_H) */
--- /dev/null
+#ifndef _SPARC64_KDEBUG_H
+#define _SPARC64_KDEBUG_H
+
+struct pt_regs;
+
+extern void bad_trap(struct pt_regs *, long);
+
+/* Grossly misnamed. */
+enum die_val {
+ DIE_OOPS = 1,
+ DIE_DEBUG, /* ta 0x70 */
+ DIE_DEBUG_2, /* ta 0x71 */
+ DIE_DIE,
+ DIE_TRAP,
+ DIE_TRAP_TL1,
+ DIE_CALL,
+};
+
+#endif
--- /dev/null
+#ifndef _SPARC_KGDB_H
+#define _SPARC_KGDB_H
+
+#ifdef CONFIG_SPARC32
+#define BUFMAX 2048
+#else
+#define BUFMAX 4096
+#endif
+
+enum regnames {
+ GDB_G0, GDB_G1, GDB_G2, GDB_G3, GDB_G4, GDB_G5, GDB_G6, GDB_G7,
+ GDB_O0, GDB_O1, GDB_O2, GDB_O3, GDB_O4, GDB_O5, GDB_SP, GDB_O7,
+ GDB_L0, GDB_L1, GDB_L2, GDB_L3, GDB_L4, GDB_L5, GDB_L6, GDB_L7,
+ GDB_I0, GDB_I1, GDB_I2, GDB_I3, GDB_I4, GDB_I5, GDB_FP, GDB_I7,
+ GDB_F0,
+ GDB_F31 = GDB_F0 + 31,
+#ifdef CONFIG_SPARC32
+ GDB_Y, GDB_PSR, GDB_WIM, GDB_TBR, GDB_PC, GDB_NPC,
+ GDB_FSR, GDB_CSR,
+#else
+ GDB_F32 = GDB_F0 + 32,
+ GDB_F62 = GDB_F32 + 15,
+ GDB_PC, GDB_NPC, GDB_STATE, GDB_FSR, GDB_FPRS, GDB_Y,
+#endif
+};
+
+#ifdef CONFIG_SPARC32
+#define NUMREGBYTES ((GDB_CSR + 1) * 4)
+#else
+#define NUMREGBYTES ((GDB_Y + 1) * 8)
+#endif
+
+extern void arch_kgdb_breakpoint(void);
+
+#define BREAK_INSTR_SIZE 4
+#define CACHE_FLUSH_IS_SAFE 1
+
+#endif /* _SPARC_KGDB_H */
--- /dev/null
+#ifndef _ASM_KMAP_TYPES_H
+#define _ASM_KMAP_TYPES_H
+
+/* Dummy header just to define km_type. None of this
+ * is actually used on sparc. -DaveM
+ */
+
+enum km_type {
+ KM_BOUNCE_READ,
+ KM_SKB_SUNRPC_DATA,
+ KM_SKB_DATA_SOFTIRQ,
+ KM_USER0,
+ KM_USER1,
+ KM_BIO_SRC_IRQ,
+ KM_BIO_DST_IRQ,
+ KM_PTE0,
+ KM_PTE1,
+ KM_IRQ0,
+ KM_IRQ1,
+ KM_SOFTIRQ0,
+ KM_SOFTIRQ1,
+ KM_TYPE_NR
+};
+
+#endif
--- /dev/null
+#ifndef _SPARC64_KPROBES_H
+#define _SPARC64_KPROBES_H
+
+#include <linux/types.h>
+#include <linux/percpu.h>
+
+typedef u32 kprobe_opcode_t;
+
+#define BREAKPOINT_INSTRUCTION 0x91d02070 /* ta 0x70 */
+#define BREAKPOINT_INSTRUCTION_2 0x91d02071 /* ta 0x71 */
+#define MAX_INSN_SIZE 2
+
+#define kretprobe_blacklist_size 0
+
+#define arch_remove_kprobe(p) do {} while (0)
+
+#define flush_insn_slot(p) \
+do { flushi(&(p)->ainsn.insn[0]); \
+ flushi(&(p)->ainsn.insn[1]); \
+} while (0)
+
+void kretprobe_trampoline(void);
+
+/* Architecture specific copy of original instruction*/
+struct arch_specific_insn {
+ /* copy of the original instruction */
+ kprobe_opcode_t insn[MAX_INSN_SIZE];
+};
+
+struct prev_kprobe {
+ struct kprobe *kp;
+ unsigned long status;
+ unsigned long orig_tnpc;
+ unsigned long orig_tstate_pil;
+};
+
+/* per-cpu kprobe control block */
+struct kprobe_ctlblk {
+ unsigned long kprobe_status;
+ unsigned long kprobe_orig_tnpc;
+ unsigned long kprobe_orig_tstate_pil;
+ struct pt_regs jprobe_saved_regs;
+ struct prev_kprobe prev_kprobe;
+};
+
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+ unsigned long val, void *data);
+extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
+#endif /* _SPARC64_KPROBES_H */
--- /dev/null
+#ifndef _SPARC64_LDC_H
+#define _SPARC64_LDC_H
+
+#include <asm/hypervisor.h>
+
+extern int ldom_domaining_enabled;
+extern void ldom_set_var(const char *var, const char *value);
+extern void ldom_reboot(const char *boot_command);
+extern void ldom_power_off(void);
+
+/* The event handler will be evoked when link state changes
+ * or data becomes available on the receive side.
+ *
+ * For non-RAW links, if the LDC_EVENT_RESET event arrives the
+ * driver should reset all of it's internal state and reinvoke
+ * ldc_connect() to try and bring the link up again.
+ *
+ * For RAW links, ldc_connect() is not used. Instead the driver
+ * just waits for the LDC_EVENT_UP event.
+ */
+struct ldc_channel_config {
+ void (*event)(void *arg, int event);
+
+ u32 mtu;
+ unsigned int rx_irq;
+ unsigned int tx_irq;
+ u8 mode;
+#define LDC_MODE_RAW 0x00
+#define LDC_MODE_UNRELIABLE 0x01
+#define LDC_MODE_RESERVED 0x02
+#define LDC_MODE_STREAM 0x03
+
+ u8 debug;
+#define LDC_DEBUG_HS 0x01
+#define LDC_DEBUG_STATE 0x02
+#define LDC_DEBUG_RX 0x04
+#define LDC_DEBUG_TX 0x08
+#define LDC_DEBUG_DATA 0x10
+};
+
+#define LDC_EVENT_RESET 0x01
+#define LDC_EVENT_UP 0x02
+#define LDC_EVENT_DATA_READY 0x04
+
+#define LDC_STATE_INVALID 0x00
+#define LDC_STATE_INIT 0x01
+#define LDC_STATE_BOUND 0x02
+#define LDC_STATE_READY 0x03
+#define LDC_STATE_CONNECTED 0x04
+
+struct ldc_channel;
+
+/* Allocate state for a channel. */
+extern struct ldc_channel *ldc_alloc(unsigned long id,
+ const struct ldc_channel_config *cfgp,
+ void *event_arg);
+
+/* Shut down and free state for a channel. */
+extern void ldc_free(struct ldc_channel *lp);
+
+/* Register TX and RX queues of the link with the hypervisor. */
+extern int ldc_bind(struct ldc_channel *lp, const char *name);
+
+/* For non-RAW protocols we need to complete a handshake before
+ * communication can proceed. ldc_connect() does that, if the
+ * handshake completes successfully, an LDC_EVENT_UP event will
+ * be sent up to the driver.
+ */
+extern int ldc_connect(struct ldc_channel *lp);
+extern int ldc_disconnect(struct ldc_channel *lp);
+
+extern int ldc_state(struct ldc_channel *lp);
+
+/* Read and write operations. Only valid when the link is up. */
+extern int ldc_write(struct ldc_channel *lp, const void *buf,
+ unsigned int size);
+extern int ldc_read(struct ldc_channel *lp, void *buf, unsigned int size);
+
+#define LDC_MAP_SHADOW 0x01
+#define LDC_MAP_DIRECT 0x02
+#define LDC_MAP_IO 0x04
+#define LDC_MAP_R 0x08
+#define LDC_MAP_W 0x10
+#define LDC_MAP_X 0x20
+#define LDC_MAP_RW (LDC_MAP_R | LDC_MAP_W)
+#define LDC_MAP_RWX (LDC_MAP_R | LDC_MAP_W | LDC_MAP_X)
+#define LDC_MAP_ALL 0x03f
+
+struct ldc_trans_cookie {
+ u64 cookie_addr;
+ u64 cookie_size;
+};
+
+struct scatterlist;
+extern int ldc_map_sg(struct ldc_channel *lp,
+ struct scatterlist *sg, int num_sg,
+ struct ldc_trans_cookie *cookies, int ncookies,
+ unsigned int map_perm);
+
+extern int ldc_map_single(struct ldc_channel *lp,
+ void *buf, unsigned int len,
+ struct ldc_trans_cookie *cookies, int ncookies,
+ unsigned int map_perm);
+
+extern void ldc_unmap(struct ldc_channel *lp, struct ldc_trans_cookie *cookies,
+ int ncookies);
+
+extern int ldc_copy(struct ldc_channel *lp, int copy_dir,
+ void *buf, unsigned int len, unsigned long offset,
+ struct ldc_trans_cookie *cookies, int ncookies);
+
+static inline int ldc_get_dring_entry(struct ldc_channel *lp,
+ void *buf, unsigned int len,
+ unsigned long offset,
+ struct ldc_trans_cookie *cookies,
+ int ncookies)
+{
+ return ldc_copy(lp, LDC_COPY_IN, buf, len, offset, cookies, ncookies);
+}
+
+static inline int ldc_put_dring_entry(struct ldc_channel *lp,
+ void *buf, unsigned int len,
+ unsigned long offset,
+ struct ldc_trans_cookie *cookies,
+ int ncookies)
+{
+ return ldc_copy(lp, LDC_COPY_OUT, buf, len, offset, cookies, ncookies);
+}
+
+extern void *ldc_alloc_exp_dring(struct ldc_channel *lp, unsigned int len,
+ struct ldc_trans_cookie *cookies,
+ int *ncookies, unsigned int map_perm);
+
+extern void ldc_free_exp_dring(struct ldc_channel *lp, void *buf,
+ unsigned int len,
+ struct ldc_trans_cookie *cookies, int ncookies);
+
+#endif /* _SPARC64_LDC_H */
--- /dev/null
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+/* Nothing to see here... */
+
+#endif
--- /dev/null
+#ifndef _SPARC64_LMB_H
+#define _SPARC64_LMB_H
+
+#include <asm/oplib.h>
+
+#define LMB_DBG(fmt...) prom_printf(fmt)
+
+#define LMB_REAL_LIMIT 0
+
+#endif /* !(_SPARC64_LMB_H) */
--- /dev/null
+#ifndef _SPARC_LOCAL_H
+#define _SPARC_LOCAL_H
+
+#include <asm-generic/local.h>
+
+#endif
--- /dev/null
+#ifndef _SPARC64_LSU_H
+#define _SPARC64_LSU_H
+
+#include <linux/const.h>
+
+/* LSU Control Register */
+#define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
+#define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/
+#define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/
+#define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/
+#define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/
+#define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/
+#define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables. */
+#define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable. */
+#define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable. */
+#define LSU_CONTROL_DC _AC(0x0000000000000002,UL) /* Data cache enable. */
+#define LSU_CONTROL_IC _AC(0x0000000000000001,UL) /* Instruction cache enable.*/
+
+#endif /* !(_SPARC64_LSU_H) */
--- /dev/null
+/*
+ * machines.h: Defines for taking apart the machine type value in the
+ * idprom and determining the kind of machine we are on.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_MACHINES_H
+#define _SPARC_MACHINES_H
+
+struct Sun_Machine_Models {
+ char *name;
+ unsigned char id_machtype;
+};
+
+/* Current number of machines we know about that has an IDPROM
+ * machtype entry including one entry for the 0x80 OBP machines.
+ */
+#define NUM_SUN_MACHINES 15
+
+/* The machine type in the idprom area looks like this:
+ *
+ * ---------------
+ * | ARCH | MACH |
+ * ---------------
+ * 7 4 3 0
+ *
+ * The ARCH field determines the architecture line (sun4, sun4c, etc).
+ * The MACH field determines the machine make within that architecture.
+ */
+
+#define SM_ARCH_MASK 0xf0
+#define SM_SUN4 0x20
+#define SM_SUN4C 0x50
+#define SM_SUN4M 0x70
+#define SM_SUN4M_OBP 0x80
+
+#define SM_TYP_MASK 0x0f
+/* Sun4 machines */
+#define SM_4_260 0x01 /* Sun 4/200 series */
+#define SM_4_110 0x02 /* Sun 4/100 series */
+#define SM_4_330 0x03 /* Sun 4/300 series */
+#define SM_4_470 0x04 /* Sun 4/400 series */
+
+/* Sun4c machines Full Name - PROM NAME */
+#define SM_4C_SS1 0x01 /* Sun4c SparcStation 1 - Sun 4/60 */
+#define SM_4C_IPC 0x02 /* Sun4c SparcStation IPC - Sun 4/40 */
+#define SM_4C_SS1PLUS 0x03 /* Sun4c SparcStation 1+ - Sun 4/65 */
+#define SM_4C_SLC 0x04 /* Sun4c SparcStation SLC - Sun 4/20 */
+#define SM_4C_SS2 0x05 /* Sun4c SparcStation 2 - Sun 4/75 */
+#define SM_4C_ELC 0x06 /* Sun4c SparcStation ELC - Sun 4/25 */
+#define SM_4C_IPX 0x07 /* Sun4c SparcStation IPX - Sun 4/50 */
+
+/* Sun4m machines, these predate the OpenBoot. These values only mean
+ * something if the value in the ARCH field is SM_SUN4M, if it is
+ * SM_SUN4M_OBP then you have the following situation:
+ * 1) You either have a sun4d, a sun4e, or a recently made sun4m.
+ * 2) You have to consult OpenBoot to determine which machine this is.
+ */
+#define SM_4M_SS60 0x01 /* Sun4m SparcSystem 600 */
+#define SM_4M_SS50 0x02 /* Sun4m SparcStation 10 */
+#define SM_4M_SS40 0x03 /* Sun4m SparcStation 5 */
+
+/* Sun4d machines -- N/A */
+/* Sun4e machines -- N/A */
+/* Sun4u machines -- N/A */
+
+#endif /* !(_SPARC_MACHINES_H) */
--- /dev/null
+/*
+ * mbus.h: Various defines for MBUS modules.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_MBUS_H
+#define _SPARC_MBUS_H
+
+#include <asm/ross.h> /* HyperSparc stuff */
+#include <asm/cypress.h> /* Cypress Chips */
+#include <asm/viking.h> /* Ugh, bug city... */
+
+enum mbus_module {
+ HyperSparc = 0,
+ Cypress = 1,
+ Cypress_vE = 2,
+ Cypress_vD = 3,
+ Swift_ok = 4,
+ Swift_bad_c = 5,
+ Swift_lots_o_bugs = 6,
+ Tsunami = 7,
+ Viking_12 = 8,
+ Viking_2x = 9,
+ Viking_30 = 10,
+ Viking_35 = 11,
+ Viking_new = 12,
+ TurboSparc = 13,
+ SRMMU_INVAL_MOD = 14,
+};
+
+extern enum mbus_module srmmu_modtype;
+extern unsigned int viking_rev, swift_rev, cypress_rev;
+
+/* HW Mbus module bugs we have to deal with */
+#define HWBUG_COPYBACK_BROKEN 0x00000001
+#define HWBUG_ASIFLUSH_BROKEN 0x00000002
+#define HWBUG_VACFLUSH_BITROT 0x00000004
+#define HWBUG_KERN_ACCBROKEN 0x00000008
+#define HWBUG_KERN_CBITBROKEN 0x00000010
+#define HWBUG_MODIFIED_BITROT 0x00000020
+#define HWBUG_PC_BADFAULT_ADDR 0x00000040
+#define HWBUG_SUPERSCALAR_BAD 0x00000080
+#define HWBUG_PACINIT_BITROT 0x00000100
+
+/* First the module type values. To find out which you have, just load
+ * the mmu control register from ASI_M_MMUREG alternate address space and
+ * shift the value right 28 bits.
+ */
+/* IMPL field means the company which produced the chip. */
+#define MBUS_VIKING 0x4 /* bleech, Texas Instruments Module */
+#define MBUS_LSI 0x3 /* LSI Logics */
+#define MBUS_ROSS 0x1 /* Ross is nice */
+#define MBUS_FMI 0x0 /* Fujitsu Microelectronics/Swift */
+
+/* Ross Module versions */
+#define ROSS_604_REV_CDE 0x0 /* revisions c, d, and e */
+#define ROSS_604_REV_F 0x1 /* revision f */
+#define ROSS_605 0xf /* revision a, a.1, and a.2 */
+#define ROSS_605_REV_B 0xe /* revision b */
+
+/* TI Viking Module versions */
+#define VIKING_REV_12 0x1 /* Version 1.2 or SPARCclassic's CPU */
+#define VIKING_REV_2 0x2 /* Version 2.1, 2.2, 2.3, and 2.4 */
+#define VIKING_REV_30 0x3 /* Version 3.0 */
+#define VIKING_REV_35 0x4 /* Version 3.5 */
+
+/* LSI Logics. */
+#define LSI_L64815 0x0
+
+/* Fujitsu */
+#define FMI_AURORA 0x4 /* MB8690x, a Swift module... */
+#define FMI_TURBO 0x5 /* MB86907, a TurboSparc module... */
+
+/* For multiprocessor support we need to be able to obtain the CPU id and
+ * the MBUS Module id.
+ */
+
+/* The CPU ID is encoded in the trap base register, 20 bits to the left of
+ * bit zero, with 2 bits being significant.
+ */
+#define TBR_ID_SHIFT 20
+
+static inline int get_cpuid(void)
+{
+ register int retval;
+ __asm__ __volatile__("rd %%tbr, %0\n\t"
+ "srl %0, %1, %0\n\t" :
+ "=r" (retval) :
+ "i" (TBR_ID_SHIFT));
+ return (retval & 3);
+}
+
+static inline int get_modid(void)
+{
+ return (get_cpuid() | 0x8);
+}
+
+
+#endif /* !(_SPARC_MBUS_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_MC146818RTC_H
+#define ___ASM_SPARC_MC146818RTC_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/mc146818rtc_64.h>
+#else
+#include <asm/mc146818rtc_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef __ASM_SPARC_MC146818RTC_H
+#define __ASM_SPARC_MC146818RTC_H
+
+#include <asm/io.h>
+
+#ifndef RTC_PORT
+#define RTC_PORT(x) (0x70 + (x))
+#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
+#endif
+
+/*
+ * The yet supported machines all access the RTC index register via
+ * an ISA port access but the way to access the date register differs ...
+ */
+#define CMOS_READ(addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+inb_p(RTC_PORT(1)); \
+})
+#define CMOS_WRITE(val, addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+outb_p((val),RTC_PORT(1)); \
+})
+
+#define RTC_IRQ 8
+
+#endif /* __ASM_SPARC_MC146818RTC_H */
--- /dev/null
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef __ASM_SPARC64_MC146818RTC_H
+#define __ASM_SPARC64_MC146818RTC_H
+
+#include <asm/io.h>
+
+#ifndef RTC_PORT
+#ifdef CONFIG_PCI
+extern unsigned long ds1287_regs;
+#else
+#define ds1287_regs (0UL)
+#endif
+#define RTC_PORT(x) (ds1287_regs + (x))
+#define RTC_ALWAYS_BCD 0
+#endif
+
+/*
+ * The yet supported machines all access the RTC index register via
+ * an ISA port access but the way to access the date register differs ...
+ */
+#define CMOS_READ(addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+inb_p(RTC_PORT(1)); \
+})
+#define CMOS_WRITE(val, addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+outb_p((val),RTC_PORT(1)); \
+})
+
+#define RTC_IRQ 8
+
+#endif /* __ASM_SPARC64_MC146818RTC_H */
--- /dev/null
+#ifndef _SPARC64_MDESC_H
+#define _SPARC64_MDESC_H
+
+#include <linux/types.h>
+#include <linux/cpumask.h>
+#include <asm/prom.h>
+
+struct mdesc_handle;
+
+/* Machine description operations are to be surrounded by grab and
+ * release calls. The mdesc_handle returned from the grab is
+ * the first argument to all of the operational calls that work
+ * on mdescs.
+ */
+extern struct mdesc_handle *mdesc_grab(void);
+extern void mdesc_release(struct mdesc_handle *);
+
+#define MDESC_NODE_NULL (~(u64)0)
+
+extern u64 mdesc_node_by_name(struct mdesc_handle *handle,
+ u64 from_node, const char *name);
+#define mdesc_for_each_node_by_name(__hdl, __node, __name) \
+ for (__node = mdesc_node_by_name(__hdl, MDESC_NODE_NULL, __name); \
+ (__node) != MDESC_NODE_NULL; \
+ __node = mdesc_node_by_name(__hdl, __node, __name))
+
+/* Access to property values returned from mdesc_get_property() are
+ * only valid inside of a mdesc_grab()/mdesc_release() sequence.
+ * Once mdesc_release() is called, the memory backed up by these
+ * pointers may reference freed up memory.
+ *
+ * Therefore callers must make copies of any property values
+ * they need.
+ *
+ * These same rules apply to mdesc_node_name().
+ */
+extern const void *mdesc_get_property(struct mdesc_handle *handle,
+ u64 node, const char *name, int *lenp);
+extern const char *mdesc_node_name(struct mdesc_handle *hp, u64 node);
+
+/* MD arc iteration, the standard sequence is:
+ *
+ * unsigned long arc;
+ * mdesc_for_each_arc(arc, handle, node, MDESC_ARC_TYPE_{FWD,BACK}) {
+ * unsigned long target = mdesc_arc_target(handle, arc);
+ * ...
+ * }
+ */
+
+#define MDESC_ARC_TYPE_FWD "fwd"
+#define MDESC_ARC_TYPE_BACK "back"
+
+extern u64 mdesc_next_arc(struct mdesc_handle *handle, u64 from,
+ const char *arc_type);
+#define mdesc_for_each_arc(__arc, __hdl, __node, __type) \
+ for (__arc = mdesc_next_arc(__hdl, __node, __type); \
+ (__arc) != MDESC_NODE_NULL; \
+ __arc = mdesc_next_arc(__hdl, __arc, __type))
+
+extern u64 mdesc_arc_target(struct mdesc_handle *hp, u64 arc);
+
+extern void mdesc_update(void);
+
+struct mdesc_notifier_client {
+ void (*add)(struct mdesc_handle *handle, u64 node);
+ void (*remove)(struct mdesc_handle *handle, u64 node);
+
+ const char *node_name;
+ struct mdesc_notifier_client *next;
+};
+
+extern void mdesc_register_notifier(struct mdesc_notifier_client *client);
+
+extern void mdesc_fill_in_cpu_data(cpumask_t mask);
+
+extern void sun4v_mdesc_init(void);
+
+#endif
--- /dev/null
+#ifndef _SPARC_MEMREG_H
+#define _SPARC_MEMREG_H
+/* memreg.h: Definitions of the values found in the synchronous
+ * and asynchronous memory error registers when a fault
+ * occurs on the sun4c.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+/* First the synchronous error codes, these are usually just
+ * normal page faults.
+ */
+
+#define SUN4C_SYNC_WDRESET 0x0001 /* watchdog reset */
+#define SUN4C_SYNC_SIZE 0x0002 /* bad access size? whuz this? */
+#define SUN4C_SYNC_PARITY 0x0008 /* bad ram chips caused a parity error */
+#define SUN4C_SYNC_SBUS 0x0010 /* the SBUS had some problems... */
+#define SUN4C_SYNC_NOMEM 0x0020 /* translation to non-existent ram */
+#define SUN4C_SYNC_PROT 0x0040 /* access violated pte protections */
+#define SUN4C_SYNC_NPRESENT 0x0080 /* pte said that page was not present */
+#define SUN4C_SYNC_BADWRITE 0x8000 /* while writing something went bogus */
+
+#define SUN4C_SYNC_BOLIXED \
+ (SUN4C_SYNC_WDRESET | SUN4C_SYNC_SIZE | SUN4C_SYNC_SBUS | \
+ SUN4C_SYNC_NOMEM | SUN4C_SYNC_PARITY)
+
+/* Now the asynchronous error codes, these are almost always produced
+ * by the cache writing things back to memory and getting a bad translation.
+ * Bad DVMA transactions can cause these faults too.
+ */
+
+#define SUN4C_ASYNC_BADDVMA 0x0010 /* error during DVMA access */
+#define SUN4C_ASYNC_NOMEM 0x0020 /* write back pointed to bad phys addr */
+#define SUN4C_ASYNC_BADWB 0x0080 /* write back points to non-present page */
+
+/* Memory parity error register with associated bit constants. */
+#ifndef __ASSEMBLY__
+extern __volatile__ unsigned long __iomem *sun4c_memerr_reg;
+#endif
+
+#define SUN4C_MPE_ERROR 0x80 /* Parity error detected. (ro) */
+#define SUN4C_MPE_MULTI 0x40 /* Multiple parity errors detected. (ro) */
+#define SUN4C_MPE_TEST 0x20 /* Write inverse parity. (rw) */
+#define SUN4C_MPE_CHECK 0x10 /* Enable parity checking. (rw) */
+#define SUN4C_MPE_ERR00 0x08 /* Parity error in bits 0-7. (ro) */
+#define SUN4C_MPE_ERR08 0x04 /* Parity error in bits 8-15. (ro) */
+#define SUN4C_MPE_ERR16 0x02 /* Parity error in bits 16-23. (ro) */
+#define SUN4C_MPE_ERR24 0x01 /* Parity error in bits 24-31. (ro) */
+#define SUN4C_MPE_ERRS 0x0F /* Bit mask for the error bits. (ro) */
+
+#endif /* !(_SPARC_MEMREG_H) */
--- /dev/null
+#ifndef __SPARC_MMAN_H__
+#define __SPARC_MMAN_H__
+
+#include <asm-generic/mman.h>
+
+/* SunOS'ified... */
+
+#define MAP_RENAME MAP_ANONYMOUS /* In SunOS terminology */
+#define MAP_NORESERVE 0x40 /* don't reserve swap pages */
+#define MAP_INHERIT 0x80 /* SunOS doesn't do this, but... */
+#define MAP_LOCKED 0x100 /* lock the mapping */
+#define _MAP_NEW 0x80000000 /* Binary compatibility is fun... */
+
+#define MAP_GROWSDOWN 0x0200 /* stack-like segment */
+#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
+#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
+
+#define MCL_CURRENT 0x2000 /* lock all currently mapped pages */
+#define MCL_FUTURE 0x4000 /* lock all additions to address space */
+
+#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
+#define MAP_NONBLOCK 0x10000 /* do not block on IO */
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+#define arch_mmap_check(addr,len,flags) sparc_mmap_check(addr,len)
+int sparc_mmap_check(unsigned long addr, unsigned long len);
+#endif
+#endif
+
+#endif /* __SPARC_MMAN_H__ */
--- /dev/null
+#ifndef ___ASM_SPARC_MMU_H
+#define ___ASM_SPARC_MMU_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/mmu_64.h>
+#else
+#include <asm/mmu_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef __MMU_H
+#define __MMU_H
+
+/* Default "unsigned long" context */
+typedef unsigned long mm_context_t;
+
+#endif
--- /dev/null
+#ifndef __MMU_H
+#define __MMU_H
+
+#include <linux/const.h>
+#include <asm/page.h>
+#include <asm/hypervisor.h>
+
+#define CTX_NR_BITS 13
+
+#define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
+
+/* UltraSPARC-III+ and later have a feature whereby you can
+ * select what page size the various Data-TLB instances in the
+ * chip. In order to gracefully support this, we put the version
+ * field in a spot outside of the areas of the context register
+ * where this parameter is specified.
+ */
+#define CTX_VERSION_SHIFT 22
+#define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT)
+
+#define CTX_PGSZ_8KB _AC(0x0,UL)
+#define CTX_PGSZ_64KB _AC(0x1,UL)
+#define CTX_PGSZ_512KB _AC(0x2,UL)
+#define CTX_PGSZ_4MB _AC(0x3,UL)
+#define CTX_PGSZ_BITS _AC(0x7,UL)
+#define CTX_PGSZ0_NUC_SHIFT 61
+#define CTX_PGSZ1_NUC_SHIFT 58
+#define CTX_PGSZ0_SHIFT 16
+#define CTX_PGSZ1_SHIFT 19
+#define CTX_PGSZ_MASK ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \
+ (CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))
+
+#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
+#define CTX_PGSZ_BASE CTX_PGSZ_8KB
+#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
+#define CTX_PGSZ_BASE CTX_PGSZ_64KB
+#else
+#error No page size specified in kernel configuration
+#endif
+
+#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#define CTX_PGSZ_HUGE CTX_PGSZ_4MB
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
+#define CTX_PGSZ_HUGE CTX_PGSZ_512KB
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#define CTX_PGSZ_HUGE CTX_PGSZ_64KB
+#endif
+
+#define CTX_PGSZ_KERN CTX_PGSZ_4MB
+
+/* Thus, when running on UltraSPARC-III+ and later, we use the following
+ * PRIMARY_CONTEXT register values for the kernel context.
+ */
+#define CTX_CHEETAH_PLUS_NUC \
+ ((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \
+ (CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT))
+
+#define CTX_CHEETAH_PLUS_CTX0 \
+ ((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \
+ (CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT))
+
+/* If you want "the TLB context number" use CTX_NR_MASK. If you
+ * want "the bits I program into the context registers" use
+ * CTX_HW_MASK.
+ */
+#define CTX_NR_MASK TAG_CONTEXT_BITS
+#define CTX_HW_MASK (CTX_NR_MASK | CTX_PGSZ_MASK)
+
+#define CTX_FIRST_VERSION ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL))
+#define CTX_VALID(__ctx) \
+ (!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
+#define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
+#define CTX_NRBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_NR_MASK)
+
+#ifndef __ASSEMBLY__
+
+#define TSB_ENTRY_ALIGNMENT 16
+
+struct tsb {
+ unsigned long tag;
+ unsigned long pte;
+} __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));
+
+extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte);
+extern void tsb_flush(unsigned long ent, unsigned long tag);
+extern void tsb_init(struct tsb *tsb, unsigned long size);
+
+struct tsb_config {
+ struct tsb *tsb;
+ unsigned long tsb_rss_limit;
+ unsigned long tsb_nentries;
+ unsigned long tsb_reg_val;
+ unsigned long tsb_map_vaddr;
+ unsigned long tsb_map_pte;
+};
+
+#define MM_TSB_BASE 0
+
+#ifdef CONFIG_HUGETLB_PAGE
+#define MM_TSB_HUGE 1
+#define MM_NUM_TSBS 2
+#else
+#define MM_NUM_TSBS 1
+#endif
+
+typedef struct {
+ spinlock_t lock;
+ unsigned long sparc64_ctx_val;
+ unsigned long huge_pte_count;
+ struct tsb_config tsb_block[MM_NUM_TSBS];
+ struct hv_tsb_descr tsb_descr[MM_NUM_TSBS];
+} mm_context_t;
+
+#endif /* !__ASSEMBLY__ */
+
+#define TSB_CONFIG_TSB 0x00
+#define TSB_CONFIG_RSS_LIMIT 0x08
+#define TSB_CONFIG_NENTRIES 0x10
+#define TSB_CONFIG_REG_VAL 0x18
+#define TSB_CONFIG_MAP_VADDR 0x20
+#define TSB_CONFIG_MAP_PTE 0x28
+
+#endif /* __MMU_H */
--- /dev/null
+#ifndef ___ASM_SPARC_MMU_CONTEXT_H
+#define ___ASM_SPARC_MMU_CONTEXT_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/mmu_context_64.h>
+#else
+#include <asm/mmu_context_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef __SPARC_MMU_CONTEXT_H
+#define __SPARC_MMU_CONTEXT_H
+
+#include <asm/btfixup.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm-generic/mm_hooks.h>
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+/*
+ * Initialize a new mmu context. This is invoked when a new
+ * address space instance (unique or shared) is instantiated.
+ */
+#define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0)
+
+/*
+ * Destroy a dead context. This occurs when mmput drops the
+ * mm_users count to zero, the mmaps have been released, and
+ * all the page tables have been flushed. Our job is to destroy
+ * any remaining processor-specific state.
+ */
+BTFIXUPDEF_CALL(void, destroy_context, struct mm_struct *)
+
+#define destroy_context(mm) BTFIXUP_CALL(destroy_context)(mm)
+
+/* Switch the current MM context. */
+BTFIXUPDEF_CALL(void, switch_mm, struct mm_struct *, struct mm_struct *, struct task_struct *)
+
+#define switch_mm(old_mm, mm, tsk) BTFIXUP_CALL(switch_mm)(old_mm, mm, tsk)
+
+#define deactivate_mm(tsk,mm) do { } while (0)
+
+/* Activate a new MM instance for the current task. */
+#define activate_mm(active_mm, mm) switch_mm((active_mm), (mm), NULL)
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__SPARC_MMU_CONTEXT_H) */
--- /dev/null
+#ifndef __SPARC64_MMU_CONTEXT_H
+#define __SPARC64_MMU_CONTEXT_H
+
+/* Derived heavily from Linus's Alpha/AXP ASN code... */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/spinlock.h>
+#include <asm/system.h>
+#include <asm/spitfire.h>
+#include <asm-generic/mm_hooks.h>
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+extern spinlock_t ctx_alloc_lock;
+extern unsigned long tlb_context_cache;
+extern unsigned long mmu_context_bmap[];
+
+extern void get_new_mmu_context(struct mm_struct *mm);
+#ifdef CONFIG_SMP
+extern void smp_new_mmu_context_version(void);
+#else
+#define smp_new_mmu_context_version() do { } while (0)
+#endif
+
+extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
+extern void destroy_context(struct mm_struct *mm);
+
+extern void __tsb_context_switch(unsigned long pgd_pa,
+ struct tsb_config *tsb_base,
+ struct tsb_config *tsb_huge,
+ unsigned long tsb_descr_pa);
+
+static inline void tsb_context_switch(struct mm_struct *mm)
+{
+ __tsb_context_switch(__pa(mm->pgd),
+ &mm->context.tsb_block[0],
+#ifdef CONFIG_HUGETLB_PAGE
+ (mm->context.tsb_block[1].tsb ?
+ &mm->context.tsb_block[1] :
+ NULL)
+#else
+ NULL
+#endif
+ , __pa(&mm->context.tsb_descr[0]));
+}
+
+extern void tsb_grow(struct mm_struct *mm, unsigned long tsb_index, unsigned long mm_rss);
+#ifdef CONFIG_SMP
+extern void smp_tsb_sync(struct mm_struct *mm);
+#else
+#define smp_tsb_sync(__mm) do { } while (0)
+#endif
+
+/* Set MMU context in the actual hardware. */
+#define load_secondary_context(__mm) \
+ __asm__ __volatile__( \
+ "\n661: stxa %0, [%1] %2\n" \
+ " .section .sun4v_1insn_patch, \"ax\"\n" \
+ " .word 661b\n" \
+ " stxa %0, [%1] %3\n" \
+ " .previous\n" \
+ " flush %%g6\n" \
+ : /* No outputs */ \
+ : "r" (CTX_HWBITS((__mm)->context)), \
+ "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
+
+extern void __flush_tlb_mm(unsigned long, unsigned long);
+
+/* Switch the current MM context. Interrupts are disabled. */
+static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
+{
+ unsigned long ctx_valid, flags;
+ int cpu;
+
+ if (unlikely(mm == &init_mm))
+ return;
+
+ spin_lock_irqsave(&mm->context.lock, flags);
+ ctx_valid = CTX_VALID(mm->context);
+ if (!ctx_valid)
+ get_new_mmu_context(mm);
+
+ /* We have to be extremely careful here or else we will miss
+ * a TSB grow if we switch back and forth between a kernel
+ * thread and an address space which has it's TSB size increased
+ * on another processor.
+ *
+ * It is possible to play some games in order to optimize the
+ * switch, but the safest thing to do is to unconditionally
+ * perform the secondary context load and the TSB context switch.
+ *
+ * For reference the bad case is, for address space "A":
+ *
+ * CPU 0 CPU 1
+ * run address space A
+ * set cpu0's bits in cpu_vm_mask
+ * switch to kernel thread, borrow
+ * address space A via entry_lazy_tlb
+ * run address space A
+ * set cpu1's bit in cpu_vm_mask
+ * flush_tlb_pending()
+ * reset cpu_vm_mask to just cpu1
+ * TSB grow
+ * run address space A
+ * context was valid, so skip
+ * TSB context switch
+ *
+ * At that point cpu0 continues to use a stale TSB, the one from
+ * before the TSB grow performed on cpu1. cpu1 did not cross-call
+ * cpu0 to update it's TSB because at that point the cpu_vm_mask
+ * only had cpu1 set in it.
+ */
+ load_secondary_context(mm);
+ tsb_context_switch(mm);
+
+ /* Any time a processor runs a context on an address space
+ * for the first time, we must flush that context out of the
+ * local TLB.
+ */
+ cpu = smp_processor_id();
+ if (!ctx_valid || !cpu_isset(cpu, mm->cpu_vm_mask)) {
+ cpu_set(cpu, mm->cpu_vm_mask);
+ __flush_tlb_mm(CTX_HWBITS(mm->context),
+ SECONDARY_CONTEXT);
+ }
+ spin_unlock_irqrestore(&mm->context.lock, flags);
+}
+
+#define deactivate_mm(tsk,mm) do { } while (0)
+
+/* Activate a new MM instance for the current task. */
+static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)
+{
+ unsigned long flags;
+ int cpu;
+
+ spin_lock_irqsave(&mm->context.lock, flags);
+ if (!CTX_VALID(mm->context))
+ get_new_mmu_context(mm);
+ cpu = smp_processor_id();
+ if (!cpu_isset(cpu, mm->cpu_vm_mask))
+ cpu_set(cpu, mm->cpu_vm_mask);
+
+ load_secondary_context(mm);
+ __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);
+ tsb_context_switch(mm);
+ spin_unlock_irqrestore(&mm->context.lock, flags);
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__SPARC64_MMU_CONTEXT_H) */
--- /dev/null
+#ifndef _SPARC64_MMZONE_H
+#define _SPARC64_MMZONE_H
+
+#ifdef CONFIG_NEED_MULTIPLE_NODES
+
+extern struct pglist_data *node_data[];
+
+#define NODE_DATA(nid) (node_data[nid])
+#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
+#define node_end_pfn(nid) (NODE_DATA(nid)->node_end_pfn)
+
+extern int numa_cpu_lookup_table[];
+extern cpumask_t numa_cpumask_lookup_table[];
+
+#endif /* CONFIG_NEED_MULTIPLE_NODES */
+
+#endif /* _SPARC64_MMZONE_H */
--- /dev/null
+#ifndef ___ASM_SPARC_MODULE_H
+#define ___ASM_SPARC_MODULE_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/module_64.h>
+#else
+#include <asm/module_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _ASM_SPARC_MODULE_H
+#define _ASM_SPARC_MODULE_H
+struct mod_arch_specific { };
+#define Elf_Shdr Elf32_Shdr
+#define Elf_Sym Elf32_Sym
+#define Elf_Ehdr Elf32_Ehdr
+#endif /* _ASM_SPARC_MODULE_H */
--- /dev/null
+#ifndef _ASM_SPARC64_MODULE_H
+#define _ASM_SPARC64_MODULE_H
+struct mod_arch_specific { };
+#define Elf_Shdr Elf64_Shdr
+#define Elf_Sym Elf64_Sym
+#define Elf_Ehdr Elf64_Ehdr
+#endif /* _ASM_SPARC64_MODULE_H */
--- /dev/null
+#ifndef ___ASM_SPARC_MOSTEK_H
+#define ___ASM_SPARC_MOSTEK_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/mostek_64.h>
+#else
+#include <asm/mostek_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * mostek.h: Describes the various Mostek time of day clock registers.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
+ * Added intersil code 05/25/98 Chris Davis (cdavis@cois.on.ca)
+ */
+
+#ifndef _SPARC_MOSTEK_H
+#define _SPARC_MOSTEK_H
+
+#include <asm/idprom.h>
+#include <asm/io.h>
+
+/* M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
+ *
+ * Data
+ * Address Function
+ * Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
+ * 7ff - - - - - - - - Year 00-99
+ * 7fe 0 0 0 - - - - - Month 01-12
+ * 7fd 0 0 - - - - - - Date 01-31
+ * 7fc 0 FT 0 0 0 - - - Day 01-07
+ * 7fb KS 0 - - - - - - Hours 00-23
+ * 7fa 0 - - - - - - - Minutes 00-59
+ * 7f9 ST - - - - - - - Seconds 00-59
+ * 7f8 W R S - - - - - Control
+ *
+ * * ST is STOP BIT
+ * * W is WRITE BIT
+ * * R is READ BIT
+ * * S is SIGN BIT
+ * * FT is FREQ TEST BIT
+ * * KS is KICK START BIT
+ */
+
+/* The Mostek 48t02 real time clock and NVRAM chip. The registers
+ * other than the control register are in binary coded decimal. Some
+ * control bits also live outside the control register.
+ */
+#define mostek_read(_addr) readb(_addr)
+#define mostek_write(_addr,_val) writeb(_val, _addr)
+#define MOSTEK_EEPROM 0x0000UL
+#define MOSTEK_IDPROM 0x07d8UL
+#define MOSTEK_CREG 0x07f8UL
+#define MOSTEK_SEC 0x07f9UL
+#define MOSTEK_MIN 0x07faUL
+#define MOSTEK_HOUR 0x07fbUL
+#define MOSTEK_DOW 0x07fcUL
+#define MOSTEK_DOM 0x07fdUL
+#define MOSTEK_MONTH 0x07feUL
+#define MOSTEK_YEAR 0x07ffUL
+
+struct mostek48t02 {
+ volatile char eeprom[2008]; /* This is the eeprom, don't touch! */
+ struct idprom idprom; /* The idprom lives here. */
+ volatile unsigned char creg; /* Control register */
+ volatile unsigned char sec; /* Seconds (0-59) */
+ volatile unsigned char min; /* Minutes (0-59) */
+ volatile unsigned char hour; /* Hour (0-23) */
+ volatile unsigned char dow; /* Day of the week (1-7) */
+ volatile unsigned char dom; /* Day of the month (1-31) */
+ volatile unsigned char month; /* Month of year (1-12) */
+ volatile unsigned char year; /* Year (0-99) */
+};
+
+extern spinlock_t mostek_lock;
+extern void __iomem *mstk48t02_regs;
+
+/* Control register values. */
+#define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */
+#define MSTK_CREG_READ 0x40 /* Stop updates to allow a clean read. */
+#define MSTK_CREG_SIGN 0x20 /* Slow/speed clock in calibration mode. */
+
+/* Control bits that live in the other registers. */
+#define MSTK_STOP 0x80 /* Stop the clock oscillator. (sec) */
+#define MSTK_KICK_START 0x80 /* Kick start the clock chip. (hour) */
+#define MSTK_FREQ_TEST 0x40 /* Frequency test mode. (day) */
+
+#define MSTK_YEAR_ZERO 1968 /* If year reg has zero, it is 1968. */
+#define MSTK_CVT_YEAR(yr) ((yr) + MSTK_YEAR_ZERO)
+
+/* Masks that define how much space each value takes up. */
+#define MSTK_SEC_MASK 0x7f
+#define MSTK_MIN_MASK 0x7f
+#define MSTK_HOUR_MASK 0x3f
+#define MSTK_DOW_MASK 0x07
+#define MSTK_DOM_MASK 0x3f
+#define MSTK_MONTH_MASK 0x1f
+#define MSTK_YEAR_MASK 0xffU
+
+/* Binary coded decimal conversion macros. */
+#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
+#define MSTK_DECIMAL_TO_REGVAL(x) ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
+
+/* Generic register set and get macros for internal use. */
+#define MSTK_GET(regs,var,mask) (MSTK_REGVAL_TO_DECIMAL(((struct mostek48t02 *)regs)->var & MSTK_ ## mask ## _MASK))
+#define MSTK_SET(regs,var,value,mask) do { ((struct mostek48t02 *)regs)->var &= ~(MSTK_ ## mask ## _MASK); ((struct mostek48t02 *)regs)->var |= MSTK_DECIMAL_TO_REGVAL(value) & (MSTK_ ## mask ## _MASK); } while (0)
+
+/* Macros to make register access easier on our fingers. These give you
+ * the decimal value of the register requested if applicable. You pass
+ * the a pointer to a 'struct mostek48t02'.
+ */
+#define MSTK_REG_CREG(regs) (((struct mostek48t02 *)regs)->creg)
+#define MSTK_REG_SEC(regs) MSTK_GET(regs,sec,SEC)
+#define MSTK_REG_MIN(regs) MSTK_GET(regs,min,MIN)
+#define MSTK_REG_HOUR(regs) MSTK_GET(regs,hour,HOUR)
+#define MSTK_REG_DOW(regs) MSTK_GET(regs,dow,DOW)
+#define MSTK_REG_DOM(regs) MSTK_GET(regs,dom,DOM)
+#define MSTK_REG_MONTH(regs) MSTK_GET(regs,month,MONTH)
+#define MSTK_REG_YEAR(regs) MSTK_GET(regs,year,YEAR)
+
+#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,sec,value,SEC)
+#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,min,value,MIN)
+#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,hour,value,HOUR)
+#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,dow,value,DOW)
+#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,dom,value,DOM)
+#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,month,value,MONTH)
+#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,year,value,YEAR)
+
+
+/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
+ * same (basically) layout of the 48t02 chip except for the extra
+ * NVRAM on board (8 KB against the 48t02's 2 KB).
+ */
+struct mostek48t08 {
+ char offset[6*1024]; /* Magic things may be here, who knows? */
+ struct mostek48t02 regs; /* Here is what we are interested in. */
+};
+
+#ifdef CONFIG_SUN4
+enum sparc_clock_type { MSTK48T02, MSTK48T08, \
+INTERSIL, MSTK_INVALID };
+#else
+enum sparc_clock_type { MSTK48T02, MSTK48T08, \
+MSTK_INVALID };
+#endif
+
+#ifdef CONFIG_SUN4
+/* intersil on a sun 4/260 code data from harris doc */
+struct intersil_dt {
+ volatile unsigned char int_csec;
+ volatile unsigned char int_hour;
+ volatile unsigned char int_min;
+ volatile unsigned char int_sec;
+ volatile unsigned char int_month;
+ volatile unsigned char int_day;
+ volatile unsigned char int_year;
+ volatile unsigned char int_dow;
+};
+
+struct intersil {
+ struct intersil_dt clk;
+ struct intersil_dt cmp;
+ volatile unsigned char int_intr_reg;
+ volatile unsigned char int_cmd_reg;
+};
+
+#define INTERSIL_STOP 0x0
+#define INTERSIL_START 0x8
+#define INTERSIL_INTR_DISABLE 0x0
+#define INTERSIL_INTR_ENABLE 0x10
+#define INTERSIL_32K 0x0
+#define INTERSIL_NORMAL 0x0
+#define INTERSIL_24H 0x4
+#define INTERSIL_INT_100HZ 0x2
+
+/* end of intersil info */
+#endif
+
+#endif /* !(_SPARC_MOSTEK_H) */
--- /dev/null
+/* mostek.h: Describes the various Mostek time of day clock registers.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
+ */
+
+#ifndef _SPARC64_MOSTEK_H
+#define _SPARC64_MOSTEK_H
+
+#include <asm/idprom.h>
+
+/* M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
+ *
+ * Data
+ * Address Function
+ * Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
+ * 7ff - - - - - - - - Year 00-99
+ * 7fe 0 0 0 - - - - - Month 01-12
+ * 7fd 0 0 - - - - - - Date 01-31
+ * 7fc 0 FT 0 0 0 - - - Day 01-07
+ * 7fb KS 0 - - - - - - Hours 00-23
+ * 7fa 0 - - - - - - - Minutes 00-59
+ * 7f9 ST - - - - - - - Seconds 00-59
+ * 7f8 W R S - - - - - Control
+ *
+ * * ST is STOP BIT
+ * * W is WRITE BIT
+ * * R is READ BIT
+ * * S is SIGN BIT
+ * * FT is FREQ TEST BIT
+ * * KS is KICK START BIT
+ */
+
+/* The Mostek 48t02 real time clock and NVRAM chip. The registers
+ * other than the control register are in binary coded decimal. Some
+ * control bits also live outside the control register.
+ *
+ * We now deal with physical addresses for I/O to the chip. -DaveM
+ */
+static inline u8 mostek_read(void __iomem *addr)
+{
+ u8 ret;
+
+ __asm__ __volatile__("lduba [%1] %2, %0"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+ return ret;
+}
+
+static inline void mostek_write(void __iomem *addr, u8 val)
+{
+ __asm__ __volatile__("stba %0, [%1] %2"
+ : /* no outputs */
+ : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+#define MOSTEK_EEPROM 0x0000UL
+#define MOSTEK_IDPROM 0x07d8UL
+#define MOSTEK_CREG 0x07f8UL
+#define MOSTEK_SEC 0x07f9UL
+#define MOSTEK_MIN 0x07faUL
+#define MOSTEK_HOUR 0x07fbUL
+#define MOSTEK_DOW 0x07fcUL
+#define MOSTEK_DOM 0x07fdUL
+#define MOSTEK_MONTH 0x07feUL
+#define MOSTEK_YEAR 0x07ffUL
+
+extern spinlock_t mostek_lock;
+extern void __iomem *mstk48t02_regs;
+
+/* Control register values. */
+#define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */
+#define MSTK_CREG_READ 0x40 /* Stop updates to allow a clean read. */
+#define MSTK_CREG_SIGN 0x20 /* Slow/speed clock in calibration mode. */
+
+/* Control bits that live in the other registers. */
+#define MSTK_STOP 0x80 /* Stop the clock oscillator. (sec) */
+#define MSTK_KICK_START 0x80 /* Kick start the clock chip. (hour) */
+#define MSTK_FREQ_TEST 0x40 /* Frequency test mode. (day) */
+
+#define MSTK_YEAR_ZERO 1968 /* If year reg has zero, it is 1968. */
+#define MSTK_CVT_YEAR(yr) ((yr) + MSTK_YEAR_ZERO)
+
+/* Masks that define how much space each value takes up. */
+#define MSTK_SEC_MASK 0x7f
+#define MSTK_MIN_MASK 0x7f
+#define MSTK_HOUR_MASK 0x3f
+#define MSTK_DOW_MASK 0x07
+#define MSTK_DOM_MASK 0x3f
+#define MSTK_MONTH_MASK 0x1f
+#define MSTK_YEAR_MASK 0xffU
+
+/* Binary coded decimal conversion macros. */
+#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
+#define MSTK_DECIMAL_TO_REGVAL(x) ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
+
+/* Generic register set and get macros for internal use. */
+#define MSTK_GET(regs,name) \
+ (MSTK_REGVAL_TO_DECIMAL(mostek_read(regs + MOSTEK_ ## name) & MSTK_ ## name ## _MASK))
+#define MSTK_SET(regs,name,value) \
+do { u8 __val = mostek_read(regs + MOSTEK_ ## name); \
+ __val &= ~(MSTK_ ## name ## _MASK); \
+ __val |= (MSTK_DECIMAL_TO_REGVAL(value) & \
+ (MSTK_ ## name ## _MASK)); \
+ mostek_write(regs + MOSTEK_ ## name, __val); \
+} while(0)
+
+/* Macros to make register access easier on our fingers. These give you
+ * the decimal value of the register requested if applicable. You pass
+ * the a pointer to a 'struct mostek48t02'.
+ */
+#define MSTK_REG_CREG(regs) (mostek_read((regs) + MOSTEK_CREG))
+#define MSTK_REG_SEC(regs) MSTK_GET(regs,SEC)
+#define MSTK_REG_MIN(regs) MSTK_GET(regs,MIN)
+#define MSTK_REG_HOUR(regs) MSTK_GET(regs,HOUR)
+#define MSTK_REG_DOW(regs) MSTK_GET(regs,DOW)
+#define MSTK_REG_DOM(regs) MSTK_GET(regs,DOM)
+#define MSTK_REG_MONTH(regs) MSTK_GET(regs,MONTH)
+#define MSTK_REG_YEAR(regs) MSTK_GET(regs,YEAR)
+
+#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,SEC,value)
+#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,MIN,value)
+#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,HOUR,value)
+#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,DOW,value)
+#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,DOM,value)
+#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,MONTH,value)
+#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,YEAR,value)
+
+
+/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
+ * same (basically) layout of the 48t02 chip except for the extra
+ * NVRAM on board (8 KB against the 48t02's 2 KB).
+ */
+#define MOSTEK_48T08_OFFSET 0x0000UL /* Lower NVRAM portions */
+#define MOSTEK_48T08_48T02 0x1800UL /* Offset to 48T02 chip */
+
+/* SUN5 systems usually have 48t59 model clock chipsets. But we keep the older
+ * clock chip definitions around just in case.
+ */
+#define MOSTEK_48T59_OFFSET 0x0000UL /* Lower NVRAM portions */
+#define MOSTEK_48T59_48T02 0x1800UL /* Offset to 48T02 chip */
+
+#endif /* !(_SPARC64_MOSTEK_H) */
--- /dev/null
+/*
+ * mpmbox.h: Interface and defines for the OpenProm mailbox
+ * facilities for MP machines under Linux.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_MPMBOX_H
+#define _SPARC_MPMBOX_H
+
+/* The prom allocates, for each CPU on the machine an unsigned
+ * byte in physical ram. You probe the device tree prom nodes
+ * for these values. The purpose of this byte is to be able to
+ * pass messages from one cpu to another.
+ */
+
+/* These are the main message types we have to look for in our
+ * Cpu mailboxes, based upon these values we decide what course
+ * of action to take.
+ */
+
+/* The CPU is executing code in the kernel. */
+#define MAILBOX_ISRUNNING 0xf0
+
+/* Another CPU called romvec->pv_exit(), you should call
+ * prom_stopcpu() when you see this in your mailbox.
+ */
+#define MAILBOX_EXIT 0xfb
+
+/* Another CPU called romvec->pv_enter(), you should call
+ * prom_cpuidle() when this is seen.
+ */
+#define MAILBOX_GOSPIN 0xfc
+
+/* Another CPU has hit a breakpoint either into kadb or the prom
+ * itself. Just like MAILBOX_GOSPIN, you should call prom_cpuidle()
+ * at this point.
+ */
+#define MAILBOX_BPT_SPIN 0xfd
+
+/* Oh geese, some other nitwit got a damn watchdog reset. The party's
+ * over so go call prom_stopcpu().
+ */
+#define MAILBOX_WDOG_STOP 0xfe
+
+#ifndef __ASSEMBLY__
+
+/* Handy macro's to determine a cpu's state. */
+
+/* Is the cpu still in Power On Self Test? */
+#define MBOX_POST_P(letter) ((letter) >= 0x00 && (letter) <= 0x7f)
+
+/* Is the cpu at the 'ok' prompt of the PROM? */
+#define MBOX_PROMPROMPT_P(letter) ((letter) >= 0x80 && (letter) <= 0x8f)
+
+/* Is the cpu spinning in the PROM? */
+#define MBOX_PROMSPIN_P(letter) ((letter) >= 0x90 && (letter) <= 0xef)
+
+/* Sanity check... This is junk mail, throw it out. */
+#define MBOX_BOGON_P(letter) ((letter) >= 0xf1 && (letter) <= 0xfa)
+
+/* Is the cpu actively running an application/kernel-code? */
+#define MBOX_RUNNING_P(letter) ((letter) == MAILBOX_ISRUNNING)
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC_MPMBOX_H) */
--- /dev/null
+#ifndef _SPARC_MSGBUF_H
+#define _SPARC_MSGBUF_H
+
+/*
+ * The msqid64_ds structure for sparc64 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+#if defined(__sparc__) && defined(__arch64__)
+# define PADDING(x)
+#else
+# define PADDING(x) unsigned int x;
+#endif
+
+
+struct msqid64_ds {
+ struct ipc64_perm msg_perm;
+ PADDING(__pad1)
+ __kernel_time_t msg_stime; /* last msgsnd time */
+ PADDING(__pad2)
+ __kernel_time_t msg_rtime; /* last msgrcv time */
+ PADDING(__pad3)
+ __kernel_time_t msg_ctime; /* last change time */
+ unsigned long msg_cbytes; /* current number of bytes on queue */
+ unsigned long msg_qnum; /* number of messages in queue */
+ unsigned long msg_qbytes; /* max number of bytes on queue */
+ __kernel_pid_t msg_lspid; /* pid of last msgsnd */
+ __kernel_pid_t msg_lrpid; /* last receive pid */
+ unsigned long __unused1;
+ unsigned long __unused2;
+};
+#undef PADDING
+#endif /* _SPARC_MSGBUF_H */
--- /dev/null
+/*
+ * msi.h: Defines specific to the MBus - Sbus - Interface.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
+ */
+
+#ifndef _SPARC_MSI_H
+#define _SPARC_MSI_H
+
+/*
+ * Locations of MSI Registers.
+ */
+#define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
+
+/*
+ * Useful bits in the MSI Registers.
+ */
+#define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
+
+
+static inline void msi_set_sync(void)
+{
+ __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
+ "andn %%g3, %2, %%g3\n\t"
+ "sta %%g3, [%0] %1\n\t" : :
+ "r" (MSI_MBUS_ARBEN),
+ "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
+}
+
+#endif /* !(_SPARC_MSI_H) */
--- /dev/null
+/*
+ * Pull in the generic implementation for the mutex fastpath.
+ *
+ * TODO: implement optimized primitives instead, or leave the generic
+ * implementation in place, or pick the atomic_xchg() based generic
+ * implementation. (see asm-generic/mutex-xchg.h for details)
+ */
+
+#include <asm-generic/mutex-dec.h>
--- /dev/null
+/*
+ * mxcc.h: Definitions of the Viking MXCC registers
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_MXCC_H
+#define _SPARC_MXCC_H
+
+/* These registers are accessed through ASI 0x2. */
+#define MXCC_DATSTREAM 0x1C00000 /* Data stream register */
+#define MXCC_SRCSTREAM 0x1C00100 /* Source stream register */
+#define MXCC_DESSTREAM 0x1C00200 /* Destination stream register */
+#define MXCC_RMCOUNT 0x1C00300 /* Count of references and misses */
+#define MXCC_STEST 0x1C00804 /* Internal self-test */
+#define MXCC_CREG 0x1C00A04 /* Control register */
+#define MXCC_SREG 0x1C00B00 /* Status register */
+#define MXCC_RREG 0x1C00C04 /* Reset register */
+#define MXCC_EREG 0x1C00E00 /* Error code register */
+#define MXCC_PREG 0x1C00F04 /* Address port register */
+
+/* Some MXCC constants. */
+#define MXCC_STREAM_SIZE 0x20 /* Size in bytes of one stream r/w */
+
+/* The MXCC Control Register:
+ *
+ * ----------------------------------------------------------------------
+ * | | RRC | RSV |PRE|MCE|PARE|ECE|RSV|
+ * ----------------------------------------------------------------------
+ * 31 10 9 8-6 5 4 3 2 1-0
+ *
+ * RRC: Controls what you read from MXCC_RMCOUNT reg.
+ * 0=Misses 1=References
+ * PRE: Prefetch enable
+ * MCE: Multiple Command Enable
+ * PARE: Parity enable
+ * ECE: External cache enable
+ */
+
+#define MXCC_CTL_RRC 0x00000200
+#define MXCC_CTL_PRE 0x00000020
+#define MXCC_CTL_MCE 0x00000010
+#define MXCC_CTL_PARE 0x00000008
+#define MXCC_CTL_ECE 0x00000004
+
+/* The MXCC Error Register:
+ *
+ * --------------------------------------------------------
+ * |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR|
+ * --------------------------------------------------------
+ * 31 30 29 28 27 26 25 24-15 14-7 6 5-3 2-0
+ *
+ * ME: Multiple Errors have occurred
+ * CE: Cache consistency Error
+ * PEW: Parity Error during a Write operation
+ * PEE: Parity Error involving the External cache
+ * ASE: ASynchronous Error
+ * EIV: This register is toast
+ * MOPC: MXCC Operation Code for instance causing error
+ * ECODE: The Error CODE
+ * PRIV: A privileged mode error? 0=no 1=yes
+ * HPADDR: High PhysicalADDRess bits (35-32)
+ */
+
+#define MXCC_ERR_ME 0x80000000
+#define MXCC_ERR_CE 0x20000000
+#define MXCC_ERR_PEW 0x10000000
+#define MXCC_ERR_PEE 0x08000000
+#define MXCC_ERR_ASE 0x04000000
+#define MXCC_ERR_EIV 0x02000000
+#define MXCC_ERR_MOPC 0x01FF8000
+#define MXCC_ERR_ECODE 0x00007F80
+#define MXCC_ERR_PRIV 0x00000040
+#define MXCC_ERR_HPADDR 0x0000000f
+
+/* The MXCC Port register:
+ *
+ * -----------------------------------------------------
+ * | | MID | |
+ * -----------------------------------------------------
+ * 31 21 20-18 17 0
+ *
+ * MID: The moduleID of the cpu your read this from.
+ */
+
+#ifndef __ASSEMBLY__
+
+static inline void mxcc_set_stream_src(unsigned long *paddr)
+{
+ unsigned long data0 = paddr[0];
+ unsigned long data1 = paddr[1];
+
+ __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
+ "or %%g0, %1, %%g3\n\t"
+ "stda %%g2, [%2] %3\n\t" : :
+ "r" (data0), "r" (data1),
+ "r" (MXCC_SRCSTREAM),
+ "i" (ASI_M_MXCC) : "g2", "g3");
+}
+
+static inline void mxcc_set_stream_dst(unsigned long *paddr)
+{
+ unsigned long data0 = paddr[0];
+ unsigned long data1 = paddr[1];
+
+ __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
+ "or %%g0, %1, %%g3\n\t"
+ "stda %%g2, [%2] %3\n\t" : :
+ "r" (data0), "r" (data1),
+ "r" (MXCC_DESSTREAM),
+ "i" (ASI_M_MXCC) : "g2", "g3");
+}
+
+static inline unsigned long mxcc_get_creg(void)
+{
+ unsigned long mxcc_control;
+
+ __asm__ __volatile__("set 0xffffffff, %%g2\n\t"
+ "set 0xffffffff, %%g3\n\t"
+ "stda %%g2, [%1] %2\n\t"
+ "lda [%3] %2, %0\n\t" :
+ "=r" (mxcc_control) :
+ "r" (MXCC_EREG), "i" (ASI_M_MXCC),
+ "r" (MXCC_CREG) : "g2", "g3");
+ return mxcc_control;
+}
+
+static inline void mxcc_set_creg(unsigned long mxcc_control)
+{
+ __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
+ "r" (mxcc_control), "r" (MXCC_CREG),
+ "i" (ASI_M_MXCC));
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* !(_SPARC_MXCC_H) */
--- /dev/null
+/* ns87303.h: Configuration Register Description for the
+ * National Semiconductor PC87303 (SuperIO).
+ *
+ * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
+ */
+
+#ifndef _SPARC_NS87303_H
+#define _SPARC_NS87303_H 1
+
+/*
+ * Control Register Index Values
+ */
+#define FER 0x00
+#define FAR 0x01
+#define PTR 0x02
+#define FCR 0x03
+#define PCR 0x04
+#define KRR 0x05
+#define PMC 0x06
+#define TUP 0x07
+#define SID 0x08
+#define ASC 0x09
+#define CS0CF0 0x0a
+#define CS0CF1 0x0b
+#define CS1CF0 0x0c
+#define CS1CF1 0x0d
+
+/* Function Enable Register (FER) bits */
+#define FER_EDM 0x10 /* Encoded Drive and Motor pin information */
+
+/* Function Address Register (FAR) bits */
+#define FAR_LPT_MASK 0x03
+#define FAR_LPTB 0x00
+#define FAR_LPTA 0x01
+#define FAR_LPTC 0x02
+
+/* Power and Test Register (PTR) bits */
+#define PTR_LPTB_IRQ7 0x08
+#define PTR_LEVEL_IRQ 0x80 /* When not ECP/EPP: Use level IRQ */
+#define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controlls direction */
+ /* of the parallel port */
+
+/* Function Control Register (FCR) bits */
+#define FCR_LDE 0x10 /* Logical Drive Exchange */
+#define FCR_ZWS_ENA 0x20 /* Enable short host read/write in ECP/EPP */
+
+/* Printer Control Register (PCR) bits */
+#define PCR_EPP_ENABLE 0x01
+#define PCR_EPP_IEEE 0x02 /* Enable EPP Version 1.9 (IEEE 1284) */
+#define PCR_ECP_ENABLE 0x04
+#define PCR_ECP_CLK_ENA 0x08 /* If 0 ECP Clock is stopped on Power down */
+#define PCR_IRQ_POLAR 0x20 /* If 0 IRQ is level high or negative pulse, */
+ /* if 1 polarity is inverted */
+#define PCR_IRQ_ODRAIN 0x40 /* If 1, IRQ is open drain */
+
+/* Tape UARTs and Parallel Port Config Register (TUP) bits */
+#define TUP_EPP_TIMO 0x02 /* Enable EPP timeout IRQ */
+
+/* Advanced SuperIO Config Register (ASC) bits */
+#define ASC_LPT_IRQ7 0x01 /* Always use IRQ7 for LPT */
+#define ASC_DRV2_SEL 0x02 /* Logical Drive Exchange controlled by TDR */
+
+#define FER_RESERVED 0x00
+#define FAR_RESERVED 0x00
+#define PTR_RESERVED 0x73
+#define FCR_RESERVED 0xc4
+#define PCR_RESERVED 0x10
+#define KRR_RESERVED 0x00
+#define PMC_RESERVED 0x98
+#define TUP_RESERVED 0xfb
+#define SIP_RESERVED 0x00
+#define ASC_RESERVED 0x18
+#define CS0CF0_RESERVED 0x00
+#define CS0CF1_RESERVED 0x08
+#define CS1CF0_RESERVED 0x00
+#define CS1CF1_RESERVED 0x08
+
+#ifdef __KERNEL__
+
+#include <linux/spinlock.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+
+extern spinlock_t ns87303_lock;
+
+static inline int ns87303_modify(unsigned long port, unsigned int index,
+ unsigned char clr, unsigned char set)
+{
+ static unsigned char reserved[] = {
+ FER_RESERVED, FAR_RESERVED, PTR_RESERVED, FCR_RESERVED,
+ PCR_RESERVED, KRR_RESERVED, PMC_RESERVED, TUP_RESERVED,
+ SIP_RESERVED, ASC_RESERVED, CS0CF0_RESERVED, CS0CF1_RESERVED,
+ CS1CF0_RESERVED, CS1CF1_RESERVED
+ };
+ unsigned long flags;
+ unsigned char value;
+
+ if (index > 0x0d)
+ return -EINVAL;
+
+ spin_lock_irqsave(&ns87303_lock, flags);
+
+ outb(index, port);
+ value = inb(port + 1);
+ value &= ~(reserved[index] | clr);
+ value |= set;
+ outb(value, port + 1);
+ outb(value, port + 1);
+
+ spin_unlock_irqrestore(&ns87303_lock, flags);
+
+ return 0;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* !(_SPARC_NS87303_H) */
--- /dev/null
+/*
+ * obio.h: Some useful locations in 0xFXXXXXXXX PA obio space on sun4d.
+ *
+ * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
+ */
+
+#ifndef _SPARC_OBIO_H
+#define _SPARC_OBIO_H
+
+#include <asm/asi.h>
+
+/* This weird monster likes to use the very upper parts of
+ 36bit PA for these things :) */
+
+/* CSR space (for each XDBUS)
+ * ------------------------------------------------------------------------
+ * | 0xFE | DEVID | | XDBUS ID | |
+ * ------------------------------------------------------------------------
+ * 35 28 27 20 19 10 9 8 7 0
+ */
+
+#define CSR_BASE_ADDR 0xe0000000
+#define CSR_CPU_SHIFT (32 - 4 - 5)
+#define CSR_XDBUS_SHIFT 8
+
+#define CSR_BASE(cpu) (((CSR_BASE_ADDR >> CSR_CPU_SHIFT) + cpu) << CSR_CPU_SHIFT)
+
+/* ECSR space (not for each XDBUS)
+ * ------------------------------------------------------------------------
+ * | 0xF | DEVID[7:1] | |
+ * ------------------------------------------------------------------------
+ * 35 32 31 25 24 0
+ */
+
+#define ECSR_BASE_ADDR 0x00000000
+#define ECSR_CPU_SHIFT (32 - 5)
+#define ECSR_DEV_SHIFT (32 - 8)
+
+#define ECSR_BASE(cpu) ((cpu) << ECSR_CPU_SHIFT)
+#define ECSR_DEV_BASE(devid) ((devid) << ECSR_DEV_SHIFT)
+
+/* Bus Watcher */
+#define BW_LOCAL_BASE 0xfff00000
+
+#define BW_CID 0x00000000
+#define BW_DBUS_CTRL 0x00000008
+#define BW_DBUS_DATA 0x00000010
+#define BW_CTRL 0x00001000
+#define BW_INTR_TABLE 0x00001040
+#define BW_INTR_TABLE_CLEAR 0x00001080
+#define BW_PRESCALER 0x000010c0
+#define BW_PTIMER_LIMIT 0x00002000
+#define BW_PTIMER_COUNTER2 0x00002004
+#define BW_PTIMER_NDLIMIT 0x00002008
+#define BW_PTIMER_CTRL 0x0000200c
+#define BW_PTIMER_COUNTER 0x00002010
+#define BW_TIMER_LIMIT 0x00003000
+#define BW_TIMER_COUNTER2 0x00003004
+#define BW_TIMER_NDLIMIT 0x00003008
+#define BW_TIMER_CTRL 0x0000300c
+#define BW_TIMER_COUNTER 0x00003010
+
+/* BW Control */
+#define BW_CTRL_USER_TIMER 0x00000004 /* Is User Timer Free run enabled */
+
+/* Boot Bus */
+#define BB_LOCAL_BASE 0xf0000000
+
+#define BB_STAT1 0x00100000
+#define BB_STAT2 0x00120000
+#define BB_STAT3 0x00140000
+#define BB_LEDS 0x002e0000
+
+/* Bits in BB_STAT2 */
+#define BB_STAT2_AC_INTR 0x04 /* Aiee! 5ms and power is gone... */
+#define BB_STAT2_TMP_INTR 0x10 /* My Penguins are burning. Are you able to smell it? */
+#define BB_STAT2_FAN_INTR 0x20 /* My fan refuses to work */
+#define BB_STAT2_PWR_INTR 0x40 /* On SC2000, one of the two ACs died. Ok, we go on... */
+#define BB_STAT2_MASK (BB_STAT2_AC_INTR|BB_STAT2_TMP_INTR|BB_STAT2_FAN_INTR|BB_STAT2_PWR_INTR)
+
+/* Cache Controller */
+#define CC_BASE 0x1F00000
+#define CC_DATSTREAM 0x1F00000 /* Data stream register */
+#define CC_DATSIZE 0x1F0003F /* Size */
+#define CC_SRCSTREAM 0x1F00100 /* Source stream register */
+#define CC_DESSTREAM 0x1F00200 /* Destination stream register */
+#define CC_RMCOUNT 0x1F00300 /* Count of references and misses */
+#define CC_IPEN 0x1F00406 /* Pending Interrupts */
+#define CC_IMSK 0x1F00506 /* Interrupt Mask */
+#define CC_ICLR 0x1F00606 /* Clear pending Interrupts */
+#define CC_IGEN 0x1F00704 /* Generate Interrupt register */
+#define CC_STEST 0x1F00804 /* Internal self-test */
+#define CC_CREG 0x1F00A04 /* Control register */
+#define CC_SREG 0x1F00B00 /* Status register */
+#define CC_RREG 0x1F00C04 /* Reset register */
+#define CC_EREG 0x1F00E00 /* Error code register */
+#define CC_CID 0x1F00F04 /* Component ID */
+
+#ifndef __ASSEMBLY__
+
+static inline int bw_get_intr_mask(int sbus_level)
+{
+ int mask;
+
+ __asm__ __volatile__ ("lduha [%1] %2, %0" :
+ "=r" (mask) :
+ "r" (BW_LOCAL_BASE + BW_INTR_TABLE + (sbus_level << 3)),
+ "i" (ASI_M_CTL));
+ return mask;
+}
+
+static inline void bw_clear_intr_mask(int sbus_level, int mask)
+{
+ __asm__ __volatile__ ("stha %0, [%1] %2" : :
+ "r" (mask),
+ "r" (BW_LOCAL_BASE + BW_INTR_TABLE_CLEAR + (sbus_level << 3)),
+ "i" (ASI_M_CTL));
+}
+
+static inline unsigned bw_get_prof_limit(int cpu)
+{
+ unsigned limit;
+
+ __asm__ __volatile__ ("lda [%1] %2, %0" :
+ "=r" (limit) :
+ "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
+ "i" (ASI_M_CTL));
+ return limit;
+}
+
+static inline void bw_set_prof_limit(int cpu, unsigned limit)
+{
+ __asm__ __volatile__ ("sta %0, [%1] %2" : :
+ "r" (limit),
+ "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
+ "i" (ASI_M_CTL));
+}
+
+static inline unsigned bw_get_ctrl(int cpu)
+{
+ unsigned ctrl;
+
+ __asm__ __volatile__ ("lda [%1] %2, %0" :
+ "=r" (ctrl) :
+ "r" (CSR_BASE(cpu) + BW_CTRL),
+ "i" (ASI_M_CTL));
+ return ctrl;
+}
+
+static inline void bw_set_ctrl(int cpu, unsigned ctrl)
+{
+ __asm__ __volatile__ ("sta %0, [%1] %2" : :
+ "r" (ctrl),
+ "r" (CSR_BASE(cpu) + BW_CTRL),
+ "i" (ASI_M_CTL));
+}
+
+extern unsigned char cpu_leds[32];
+
+static inline void show_leds(int cpuid)
+{
+ cpuid &= 0x1e;
+ __asm__ __volatile__ ("stba %0, [%1] %2" : :
+ "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
+ "r" (ECSR_BASE(cpuid) | BB_LEDS),
+ "i" (ASI_M_CTL));
+}
+
+static inline unsigned cc_get_ipen(void)
+{
+ unsigned pending;
+
+ __asm__ __volatile__ ("lduha [%1] %2, %0" :
+ "=r" (pending) :
+ "r" (CC_IPEN),
+ "i" (ASI_M_MXCC));
+ return pending;
+}
+
+static inline void cc_set_iclr(unsigned clear)
+{
+ __asm__ __volatile__ ("stha %0, [%1] %2" : :
+ "r" (clear),
+ "r" (CC_ICLR),
+ "i" (ASI_M_MXCC));
+}
+
+static inline unsigned cc_get_imsk(void)
+{
+ unsigned mask;
+
+ __asm__ __volatile__ ("lduha [%1] %2, %0" :
+ "=r" (mask) :
+ "r" (CC_IMSK),
+ "i" (ASI_M_MXCC));
+ return mask;
+}
+
+static inline void cc_set_imsk(unsigned mask)
+{
+ __asm__ __volatile__ ("stha %0, [%1] %2" : :
+ "r" (mask),
+ "r" (CC_IMSK),
+ "i" (ASI_M_MXCC));
+}
+
+static inline unsigned cc_get_imsk_other(int cpuid)
+{
+ unsigned mask;
+
+ __asm__ __volatile__ ("lduha [%1] %2, %0" :
+ "=r" (mask) :
+ "r" (ECSR_BASE(cpuid) | CC_IMSK),
+ "i" (ASI_M_CTL));
+ return mask;
+}
+
+static inline void cc_set_imsk_other(int cpuid, unsigned mask)
+{
+ __asm__ __volatile__ ("stha %0, [%1] %2" : :
+ "r" (mask),
+ "r" (ECSR_BASE(cpuid) | CC_IMSK),
+ "i" (ASI_M_CTL));
+}
+
+static inline void cc_set_igen(unsigned gen)
+{
+ __asm__ __volatile__ ("sta %0, [%1] %2" : :
+ "r" (gen),
+ "r" (CC_IGEN),
+ "i" (ASI_M_MXCC));
+}
+
+/* +-------+-------------+-----------+------------------------------------+
+ * | bcast | devid | sid | levels mask |
+ * +-------+-------------+-----------+------------------------------------+
+ * 31 30 23 22 15 14 0
+ */
+#define IGEN_MESSAGE(bcast, devid, sid, levels) \
+ (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
+
+static inline void sun4d_send_ipi(int cpu, int level)
+{
+ cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1)));
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* !(_SPARC_OBIO_H) */
--- /dev/null
+#ifndef _ASM_SPARC_OF_DEVICE_H
+#define _ASM_SPARC_OF_DEVICE_H
+#ifdef __KERNEL__
+
+#include <linux/device.h>
+#include <linux/of.h>
+#include <linux/mod_devicetable.h>
+#include <asm/openprom.h>
+
+/*
+ * The of_device is a kind of "base class" that is a superset of
+ * struct device for use by devices attached to an OF node and
+ * probed using OF properties.
+ */
+struct of_device
+{
+ struct device_node *node;
+ struct device dev;
+ struct resource resource[PROMREG_MAX];
+ unsigned int irqs[PROMINTR_MAX];
+ int num_irqs;
+
+ void *sysdata;
+
+ int slot;
+ int portid;
+ int clock_freq;
+};
+
+extern void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name);
+extern void of_iounmap(struct resource *res, void __iomem *base, unsigned long size);
+
+/* These are just here during the transition */
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_SPARC_OF_DEVICE_H */
--- /dev/null
+#ifndef ___ASM_SPARC_OF_PLATFORM_H
+#define ___ASM_SPARC_OF_PLATFORM_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/of_platform_64.h>
+#else
+#include <asm/of_platform_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _ASM_SPARC_OF_PLATFORM_H
+#define _ASM_SPARC_OF_PLATFORM_H
+/*
+ * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
+ * <benh@kernel.crashing.org>
+ * Modified for Sparc by merging parts of asm/of_device.h
+ * by Stephen Rothwell
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+/* This is just here during the transition */
+#include <linux/of_platform.h>
+
+extern struct bus_type ebus_bus_type;
+extern struct bus_type sbus_bus_type;
+
+#define of_bus_type of_platform_bus_type /* for compatibility */
+
+#endif /* _ASM_SPARC_OF_PLATFORM_H */
--- /dev/null
+#ifndef _ASM_SPARC64_OF_PLATFORM_H
+#define _ASM_SPARC64_OF_PLATFORM_H
+/*
+ * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
+ * <benh@kernel.crashing.org>
+ * Modified for Sparc by merging parts of asm/of_device.h
+ * by Stephen Rothwell
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+/* This is just here during the transition */
+#include <linux/of_platform.h>
+
+extern struct bus_type isa_bus_type;
+extern struct bus_type ebus_bus_type;
+extern struct bus_type sbus_bus_type;
+
+#define of_bus_type of_platform_bus_type /* for compatibility */
+
+#endif /* _ASM_SPARC64_OF_PLATFORM_H */
--- /dev/null
+#ifndef ___ASM_SPARC_OPENPROM_H
+#define ___ASM_SPARC_OPENPROM_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/openprom_64.h>
+#else
+#include <asm/openprom_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef __SPARC_OPENPROM_H
+#define __SPARC_OPENPROM_H
+
+/* openprom.h: Prom structures and defines for access to the OPENBOOT
+ * prom routines and data areas.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+/* Empirical constants... */
+#define LINUX_OPPROM_MAGIC 0x10010407
+
+#ifndef __ASSEMBLY__
+/* V0 prom device operations. */
+struct linux_dev_v0_funcs {
+ int (*v0_devopen)(char *device_str);
+ int (*v0_devclose)(int dev_desc);
+ int (*v0_rdblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
+ int (*v0_wrblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
+ int (*v0_wrnetdev)(int dev_desc, int num_bytes, char *buf);
+ int (*v0_rdnetdev)(int dev_desc, int num_bytes, char *buf);
+ int (*v0_rdchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
+ int (*v0_wrchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
+ int (*v0_seekdev)(int dev_desc, long logical_offst, int from);
+};
+
+/* V2 and later prom device operations. */
+struct linux_dev_v2_funcs {
+ int (*v2_inst2pkg)(int d); /* Convert ihandle to phandle */
+ char * (*v2_dumb_mem_alloc)(char *va, unsigned sz);
+ void (*v2_dumb_mem_free)(char *va, unsigned sz);
+
+ /* To map devices into virtual I/O space. */
+ char * (*v2_dumb_mmap)(char *virta, int which_io, unsigned paddr, unsigned sz);
+ void (*v2_dumb_munmap)(char *virta, unsigned size);
+
+ int (*v2_dev_open)(char *devpath);
+ void (*v2_dev_close)(int d);
+ int (*v2_dev_read)(int d, char *buf, int nbytes);
+ int (*v2_dev_write)(int d, char *buf, int nbytes);
+ int (*v2_dev_seek)(int d, int hi, int lo);
+
+ /* Never issued (multistage load support) */
+ void (*v2_wheee2)(void);
+ void (*v2_wheee3)(void);
+};
+
+struct linux_mlist_v0 {
+ struct linux_mlist_v0 *theres_more;
+ char *start_adr;
+ unsigned num_bytes;
+};
+
+struct linux_mem_v0 {
+ struct linux_mlist_v0 **v0_totphys;
+ struct linux_mlist_v0 **v0_prommap;
+ struct linux_mlist_v0 **v0_available; /* What we can use */
+};
+
+/* Arguments sent to the kernel from the boot prompt. */
+struct linux_arguments_v0 {
+ char *argv[8];
+ char args[100];
+ char boot_dev[2];
+ int boot_dev_ctrl;
+ int boot_dev_unit;
+ int dev_partition;
+ char *kernel_file_name;
+ void *aieee1; /* XXX */
+};
+
+/* V2 and up boot things. */
+struct linux_bootargs_v2 {
+ char **bootpath;
+ char **bootargs;
+ int *fd_stdin;
+ int *fd_stdout;
+};
+
+/* The top level PROM vector. */
+struct linux_romvec {
+ /* Version numbers. */
+ unsigned int pv_magic_cookie;
+ unsigned int pv_romvers;
+ unsigned int pv_plugin_revision;
+ unsigned int pv_printrev;
+
+ /* Version 0 memory descriptors. */
+ struct linux_mem_v0 pv_v0mem;
+
+ /* Node operations. */
+ struct linux_nodeops *pv_nodeops;
+
+ char **pv_bootstr;
+ struct linux_dev_v0_funcs pv_v0devops;
+
+ char *pv_stdin;
+ char *pv_stdout;
+#define PROMDEV_KBD 0 /* input from keyboard */
+#define PROMDEV_SCREEN 0 /* output to screen */
+#define PROMDEV_TTYA 1 /* in/out to ttya */
+#define PROMDEV_TTYB 2 /* in/out to ttyb */
+
+ /* Blocking getchar/putchar. NOT REENTRANT! (grr) */
+ int (*pv_getchar)(void);
+ void (*pv_putchar)(int ch);
+
+ /* Non-blocking variants. */
+ int (*pv_nbgetchar)(void);
+ int (*pv_nbputchar)(int ch);
+
+ void (*pv_putstr)(char *str, int len);
+
+ /* Miscellany. */
+ void (*pv_reboot)(char *bootstr);
+ void (*pv_printf)(__const__ char *fmt, ...);
+ void (*pv_abort)(void);
+ __volatile__ int *pv_ticks;
+ void (*pv_halt)(void);
+ void (**pv_synchook)(void);
+
+ /* Evaluate a forth string, not different proto for V0 and V2->up. */
+ union {
+ void (*v0_eval)(int len, char *str);
+ void (*v2_eval)(char *str);
+ } pv_fortheval;
+
+ struct linux_arguments_v0 **pv_v0bootargs;
+
+ /* Get ether address. */
+ unsigned int (*pv_enaddr)(int d, char *enaddr);
+
+ struct linux_bootargs_v2 pv_v2bootargs;
+ struct linux_dev_v2_funcs pv_v2devops;
+
+ int filler[15];
+
+ /* This one is sun4c/sun4 only. */
+ void (*pv_setctxt)(int ctxt, char *va, int pmeg);
+
+ /* Prom version 3 Multiprocessor routines. This stuff is crazy.
+ * No joke. Calling these when there is only one cpu probably
+ * crashes the machine, have to test this. :-)
+ */
+
+ /* v3_cpustart() will start the cpu 'whichcpu' in mmu-context
+ * 'thiscontext' executing at address 'prog_counter'
+ */
+ int (*v3_cpustart)(unsigned int whichcpu, int ctxtbl_ptr,
+ int thiscontext, char *prog_counter);
+
+ /* v3_cpustop() will cause cpu 'whichcpu' to stop executing
+ * until a resume cpu call is made.
+ */
+ int (*v3_cpustop)(unsigned int whichcpu);
+
+ /* v3_cpuidle() will idle cpu 'whichcpu' until a stop or
+ * resume cpu call is made.
+ */
+ int (*v3_cpuidle)(unsigned int whichcpu);
+
+ /* v3_cpuresume() will resume processor 'whichcpu' executing
+ * starting with whatever 'pc' and 'npc' were left at the
+ * last 'idle' or 'stop' call.
+ */
+ int (*v3_cpuresume)(unsigned int whichcpu);
+};
+
+/* Routines for traversing the prom device tree. */
+struct linux_nodeops {
+ int (*no_nextnode)(int node);
+ int (*no_child)(int node);
+ int (*no_proplen)(int node, char *name);
+ int (*no_getprop)(int node, char *name, char *val);
+ int (*no_setprop)(int node, char *name, char *val, int len);
+ char * (*no_nextprop)(int node, char *name);
+};
+
+/* More fun PROM structures for device probing. */
+#define PROMREG_MAX 16
+#define PROMVADDR_MAX 16
+#define PROMINTR_MAX 15
+
+struct linux_prom_registers {
+ unsigned int which_io; /* is this in OBIO space? */
+ unsigned int phys_addr; /* The physical address of this register */
+ unsigned int reg_size; /* How many bytes does this register take up? */
+};
+
+struct linux_prom_irqs {
+ int pri; /* IRQ priority */
+ int vector; /* This is foobar, what does it do? */
+};
+
+/* Element of the "ranges" vector */
+struct linux_prom_ranges {
+ unsigned int ot_child_space;
+ unsigned int ot_child_base; /* Bus feels this */
+ unsigned int ot_parent_space;
+ unsigned int ot_parent_base; /* CPU looks from here */
+ unsigned int or_size;
+};
+
+/* Ranges and reg properties are a bit different for PCI. */
+struct linux_prom_pci_registers {
+ /*
+ * We don't know what information this field contain.
+ * We guess, PCI device function is in bits 15:8
+ * So, ...
+ */
+ unsigned int which_io; /* Let it be which_io */
+
+ unsigned int phys_hi;
+ unsigned int phys_lo;
+
+ unsigned int size_hi;
+ unsigned int size_lo;
+};
+
+struct linux_prom_pci_ranges {
+ unsigned int child_phys_hi; /* Only certain bits are encoded here. */
+ unsigned int child_phys_mid;
+ unsigned int child_phys_lo;
+
+ unsigned int parent_phys_hi;
+ unsigned int parent_phys_lo;
+
+ unsigned int size_hi;
+ unsigned int size_lo;
+};
+
+struct linux_prom_pci_assigned_addresses {
+ unsigned int which_io;
+
+ unsigned int phys_hi;
+ unsigned int phys_lo;
+
+ unsigned int size_hi;
+ unsigned int size_lo;
+};
+
+struct linux_prom_ebus_ranges {
+ unsigned int child_phys_hi;
+ unsigned int child_phys_lo;
+
+ unsigned int parent_phys_hi;
+ unsigned int parent_phys_mid;
+ unsigned int parent_phys_lo;
+
+ unsigned int size;
+};
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__SPARC_OPENPROM_H) */
--- /dev/null
+#ifndef __SPARC64_OPENPROM_H
+#define __SPARC64_OPENPROM_H
+
+/* openprom.h: Prom structures and defines for access to the OPENBOOT
+ * prom routines and data areas.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __ASSEMBLY__
+/* V0 prom device operations. */
+struct linux_dev_v0_funcs {
+ int (*v0_devopen)(char *device_str);
+ int (*v0_devclose)(int dev_desc);
+ int (*v0_rdblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
+ int (*v0_wrblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
+ int (*v0_wrnetdev)(int dev_desc, int num_bytes, char *buf);
+ int (*v0_rdnetdev)(int dev_desc, int num_bytes, char *buf);
+ int (*v0_rdchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
+ int (*v0_wrchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
+ int (*v0_seekdev)(int dev_desc, long logical_offst, int from);
+};
+
+/* V2 and later prom device operations. */
+struct linux_dev_v2_funcs {
+ int (*v2_inst2pkg)(int d); /* Convert ihandle to phandle */
+ char * (*v2_dumb_mem_alloc)(char *va, unsigned sz);
+ void (*v2_dumb_mem_free)(char *va, unsigned sz);
+
+ /* To map devices into virtual I/O space. */
+ char * (*v2_dumb_mmap)(char *virta, int which_io, unsigned paddr, unsigned sz);
+ void (*v2_dumb_munmap)(char *virta, unsigned size);
+
+ int (*v2_dev_open)(char *devpath);
+ void (*v2_dev_close)(int d);
+ int (*v2_dev_read)(int d, char *buf, int nbytes);
+ int (*v2_dev_write)(int d, char *buf, int nbytes);
+ int (*v2_dev_seek)(int d, int hi, int lo);
+
+ /* Never issued (multistage load support) */
+ void (*v2_wheee2)(void);
+ void (*v2_wheee3)(void);
+};
+
+struct linux_mlist_v0 {
+ struct linux_mlist_v0 *theres_more;
+ unsigned start_adr;
+ unsigned num_bytes;
+};
+
+struct linux_mem_v0 {
+ struct linux_mlist_v0 **v0_totphys;
+ struct linux_mlist_v0 **v0_prommap;
+ struct linux_mlist_v0 **v0_available; /* What we can use */
+};
+
+/* Arguments sent to the kernel from the boot prompt. */
+struct linux_arguments_v0 {
+ char *argv[8];
+ char args[100];
+ char boot_dev[2];
+ int boot_dev_ctrl;
+ int boot_dev_unit;
+ int dev_partition;
+ char *kernel_file_name;
+ void *aieee1; /* XXX */
+};
+
+/* V2 and up boot things. */
+struct linux_bootargs_v2 {
+ char **bootpath;
+ char **bootargs;
+ int *fd_stdin;
+ int *fd_stdout;
+};
+
+/* The top level PROM vector. */
+struct linux_romvec {
+ /* Version numbers. */
+ unsigned int pv_magic_cookie;
+ unsigned int pv_romvers;
+ unsigned int pv_plugin_revision;
+ unsigned int pv_printrev;
+
+ /* Version 0 memory descriptors. */
+ struct linux_mem_v0 pv_v0mem;
+
+ /* Node operations. */
+ struct linux_nodeops *pv_nodeops;
+
+ char **pv_bootstr;
+ struct linux_dev_v0_funcs pv_v0devops;
+
+ char *pv_stdin;
+ char *pv_stdout;
+#define PROMDEV_KBD 0 /* input from keyboard */
+#define PROMDEV_SCREEN 0 /* output to screen */
+#define PROMDEV_TTYA 1 /* in/out to ttya */
+#define PROMDEV_TTYB 2 /* in/out to ttyb */
+
+ /* Blocking getchar/putchar. NOT REENTRANT! (grr) */
+ int (*pv_getchar)(void);
+ void (*pv_putchar)(int ch);
+
+ /* Non-blocking variants. */
+ int (*pv_nbgetchar)(void);
+ int (*pv_nbputchar)(int ch);
+
+ void (*pv_putstr)(char *str, int len);
+
+ /* Miscellany. */
+ void (*pv_reboot)(char *bootstr);
+ void (*pv_printf)(__const__ char *fmt, ...);
+ void (*pv_abort)(void);
+ __volatile__ int *pv_ticks;
+ void (*pv_halt)(void);
+ void (**pv_synchook)(void);
+
+ /* Evaluate a forth string, not different proto for V0 and V2->up. */
+ union {
+ void (*v0_eval)(int len, char *str);
+ void (*v2_eval)(char *str);
+ } pv_fortheval;
+
+ struct linux_arguments_v0 **pv_v0bootargs;
+
+ /* Get ether address. */
+ unsigned int (*pv_enaddr)(int d, char *enaddr);
+
+ struct linux_bootargs_v2 pv_v2bootargs;
+ struct linux_dev_v2_funcs pv_v2devops;
+
+ int filler[15];
+
+ /* This one is sun4c/sun4 only. */
+ void (*pv_setctxt)(int ctxt, char *va, int pmeg);
+
+ /* Prom version 3 Multiprocessor routines. This stuff is crazy.
+ * No joke. Calling these when there is only one cpu probably
+ * crashes the machine, have to test this. :-)
+ */
+
+ /* v3_cpustart() will start the cpu 'whichcpu' in mmu-context
+ * 'thiscontext' executing at address 'prog_counter'
+ */
+ int (*v3_cpustart)(unsigned int whichcpu, int ctxtbl_ptr,
+ int thiscontext, char *prog_counter);
+
+ /* v3_cpustop() will cause cpu 'whichcpu' to stop executing
+ * until a resume cpu call is made.
+ */
+ int (*v3_cpustop)(unsigned int whichcpu);
+
+ /* v3_cpuidle() will idle cpu 'whichcpu' until a stop or
+ * resume cpu call is made.
+ */
+ int (*v3_cpuidle)(unsigned int whichcpu);
+
+ /* v3_cpuresume() will resume processor 'whichcpu' executing
+ * starting with whatever 'pc' and 'npc' were left at the
+ * last 'idle' or 'stop' call.
+ */
+ int (*v3_cpuresume)(unsigned int whichcpu);
+};
+
+/* Routines for traversing the prom device tree. */
+struct linux_nodeops {
+ int (*no_nextnode)(int node);
+ int (*no_child)(int node);
+ int (*no_proplen)(int node, char *name);
+ int (*no_getprop)(int node, char *name, char *val);
+ int (*no_setprop)(int node, char *name, char *val, int len);
+ char * (*no_nextprop)(int node, char *name);
+};
+
+/* More fun PROM structures for device probing. */
+#define PROMREG_MAX 24
+#define PROMVADDR_MAX 16
+#define PROMINTR_MAX 32
+
+struct linux_prom_registers {
+ unsigned which_io; /* hi part of physical address */
+ unsigned phys_addr; /* The physical address of this register */
+ int reg_size; /* How many bytes does this register take up? */
+};
+
+struct linux_prom64_registers {
+ unsigned long phys_addr;
+ unsigned long reg_size;
+};
+
+struct linux_prom_irqs {
+ int pri; /* IRQ priority */
+ int vector; /* This is foobar, what does it do? */
+};
+
+/* Element of the "ranges" vector */
+struct linux_prom_ranges {
+ unsigned int ot_child_space;
+ unsigned int ot_child_base; /* Bus feels this */
+ unsigned int ot_parent_space;
+ unsigned int ot_parent_base; /* CPU looks from here */
+ unsigned int or_size;
+};
+
+struct linux_prom64_ranges {
+ unsigned long ot_child_base; /* Bus feels this */
+ unsigned long ot_parent_base; /* CPU looks from here */
+ unsigned long or_size;
+};
+
+/* Ranges and reg properties are a bit different for PCI. */
+struct linux_prom_pci_registers {
+ unsigned int phys_hi;
+ unsigned int phys_mid;
+ unsigned int phys_lo;
+
+ unsigned int size_hi;
+ unsigned int size_lo;
+};
+
+struct linux_prom_pci_ranges {
+ unsigned int child_phys_hi; /* Only certain bits are encoded here. */
+ unsigned int child_phys_mid;
+ unsigned int child_phys_lo;
+
+ unsigned int parent_phys_hi;
+ unsigned int parent_phys_lo;
+
+ unsigned int size_hi;
+ unsigned int size_lo;
+};
+
+struct linux_prom_pci_intmap {
+ unsigned int phys_hi;
+ unsigned int phys_mid;
+ unsigned int phys_lo;
+
+ unsigned int interrupt;
+
+ int cnode;
+ unsigned int cinterrupt;
+};
+
+struct linux_prom_pci_intmask {
+ unsigned int phys_hi;
+ unsigned int phys_mid;
+ unsigned int phys_lo;
+ unsigned int interrupt;
+};
+
+struct linux_prom_ebus_ranges {
+ unsigned int child_phys_hi;
+ unsigned int child_phys_lo;
+
+ unsigned int parent_phys_hi;
+ unsigned int parent_phys_mid;
+ unsigned int parent_phys_lo;
+
+ unsigned int size;
+};
+
+struct linux_prom_ebus_intmap {
+ unsigned int phys_hi;
+ unsigned int phys_lo;
+
+ unsigned int interrupt;
+
+ int cnode;
+ unsigned int cinterrupt;
+};
+
+struct linux_prom_ebus_intmask {
+ unsigned int phys_hi;
+ unsigned int phys_lo;
+ unsigned int interrupt;
+};
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__SPARC64_OPENPROM_H) */
--- /dev/null
+#ifndef _SPARC_OPENPROMIO_H
+#define _SPARC_OPENPROMIO_H
+
+#include <linux/compiler.h>
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+/*
+ * SunOS and Solaris /dev/openprom definitions. The ioctl values
+ * were chosen to be exactly equal to the SunOS equivalents.
+ */
+
+struct openpromio
+{
+ u_int oprom_size; /* Actual size of the oprom_array. */
+ char oprom_array[1]; /* Holds property names and values. */
+};
+
+#define OPROMMAXPARAM 4096 /* Maximum size of oprom_array. */
+
+#define OPROMGETOPT 0x20004F01
+#define OPROMSETOPT 0x20004F02
+#define OPROMNXTOPT 0x20004F03
+#define OPROMSETOPT2 0x20004F04
+#define OPROMNEXT 0x20004F05
+#define OPROMCHILD 0x20004F06
+#define OPROMGETPROP 0x20004F07
+#define OPROMNXTPROP 0x20004F08
+#define OPROMU2P 0x20004F09
+#define OPROMGETCONS 0x20004F0A
+#define OPROMGETFBNAME 0x20004F0B
+#define OPROMGETBOOTARGS 0x20004F0C
+/* Linux extensions */ /* Arguments in oprom_array: */
+#define OPROMSETCUR 0x20004FF0 /* int node - Sets current node */
+#define OPROMPCI2NODE 0x20004FF1 /* int pci_bus, pci_devfn - Sets current node to PCI device's node */
+#define OPROMPATH2NODE 0x20004FF2 /* char path[] - Set current node from fully qualified PROM path */
+
+/*
+ * Return values from OPROMGETCONS:
+ */
+
+#define OPROMCONS_NOT_WSCONS 0
+#define OPROMCONS_STDIN_IS_KBD 0x1 /* stdin device is kbd */
+#define OPROMCONS_STDOUT_IS_FB 0x2 /* stdout is a framebuffer */
+#define OPROMCONS_OPENPROM 0x4 /* supports openboot */
+
+
+/*
+ * NetBSD/OpenBSD /dev/openprom definitions.
+ */
+
+struct opiocdesc
+{
+ int op_nodeid; /* PROM Node ID (value-result) */
+ int op_namelen; /* Length of op_name. */
+ char __user *op_name; /* Pointer to the property name. */
+ int op_buflen; /* Length of op_buf (value-result) */
+ char __user *op_buf; /* Pointer to buffer. */
+};
+
+#define OPIOCGET _IOWR('O', 1, struct opiocdesc)
+#define OPIOCSET _IOW('O', 2, struct opiocdesc)
+#define OPIOCNEXTPROP _IOWR('O', 3, struct opiocdesc)
+#define OPIOCGETOPTNODE _IOR('O', 4, int)
+#define OPIOCGETNEXT _IOWR('O', 5, int)
+#define OPIOCGETCHILD _IOWR('O', 6, int)
+
+#endif /* _SPARC_OPENPROMIO_H */
+
--- /dev/null
+#ifndef ___ASM_SPARC_OPLIB_H
+#define ___ASM_SPARC_OPLIB_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/oplib_64.h>
+#else
+#include <asm/oplib_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * oplib.h: Describes the interface and available routines in the
+ * Linux Prom library.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __SPARC_OPLIB_H
+#define __SPARC_OPLIB_H
+
+#include <asm/openprom.h>
+#include <linux/spinlock.h>
+#include <linux/compiler.h>
+
+/* The master romvec pointer... */
+extern struct linux_romvec *romvec;
+
+/* Enumeration to describe the prom major version we have detected. */
+enum prom_major_version {
+ PROM_V0, /* Original sun4c V0 prom */
+ PROM_V2, /* sun4c and early sun4m V2 prom */
+ PROM_V3, /* sun4m and later, up to sun4d/sun4e machines V3 */
+ PROM_P1275, /* IEEE compliant ISA based Sun PROM, only sun4u */
+ PROM_SUN4, /* Old sun4 proms are totally different, but we'll shoehorn it to make it fit */
+};
+
+extern enum prom_major_version prom_vers;
+/* Revision, and firmware revision. */
+extern unsigned int prom_rev, prom_prev;
+
+/* Root node of the prom device tree, this stays constant after
+ * initialization is complete.
+ */
+extern int prom_root_node;
+
+/* Pointer to prom structure containing the device tree traversal
+ * and usage utility functions. Only prom-lib should use these,
+ * users use the interface defined by the library only!
+ */
+extern struct linux_nodeops *prom_nodeops;
+
+/* The functions... */
+
+/* You must call prom_init() before using any of the library services,
+ * preferably as early as possible. Pass it the romvec pointer.
+ */
+extern void prom_init(struct linux_romvec *rom_ptr);
+
+/* Boot argument acquisition, returns the boot command line string. */
+extern char *prom_getbootargs(void);
+
+/* Device utilities. */
+
+/* Map and unmap devices in IO space at virtual addresses. Note that the
+ * virtual address you pass is a request and the prom may put your mappings
+ * somewhere else, so check your return value as that is where your new
+ * mappings really are!
+ *
+ * Another note, these are only available on V2 or higher proms!
+ */
+extern char *prom_mapio(char *virt_hint, int io_space, unsigned int phys_addr, unsigned int num_bytes);
+extern void prom_unmapio(char *virt_addr, unsigned int num_bytes);
+
+/* Device operations. */
+
+/* Open the device described by the passed string. Note, that the format
+ * of the string is different on V0 vs. V2->higher proms. The caller must
+ * know what he/she is doing! Returns the device descriptor, an int.
+ */
+extern int prom_devopen(char *device_string);
+
+/* Close a previously opened device described by the passed integer
+ * descriptor.
+ */
+extern int prom_devclose(int device_handle);
+
+/* Do a seek operation on the device described by the passed integer
+ * descriptor.
+ */
+extern void prom_seek(int device_handle, unsigned int seek_hival,
+ unsigned int seek_lowval);
+
+/* Miscellaneous routines, don't really fit in any category per se. */
+
+/* Reboot the machine with the command line passed. */
+extern void prom_reboot(char *boot_command);
+
+/* Evaluate the forth string passed. */
+extern void prom_feval(char *forth_string);
+
+/* Enter the prom, with possibility of continuation with the 'go'
+ * command in newer proms.
+ */
+extern void prom_cmdline(void);
+
+/* Enter the prom, with no chance of continuation for the stand-alone
+ * which calls this.
+ */
+extern void prom_halt(void) __attribute__ ((noreturn));
+
+/* Set the PROM 'sync' callback function to the passed function pointer.
+ * When the user gives the 'sync' command at the prom prompt while the
+ * kernel is still active, the prom will call this routine.
+ *
+ * XXX The arguments are different on V0 vs. V2->higher proms, grrr! XXX
+ */
+typedef void (*sync_func_t)(void);
+extern void prom_setsync(sync_func_t func_ptr);
+
+/* Acquire the IDPROM of the root node in the prom device tree. This
+ * gets passed a buffer where you would like it stuffed. The return value
+ * is the format type of this idprom or 0xff on error.
+ */
+extern unsigned char prom_get_idprom(char *idp_buffer, int idpbuf_size);
+
+/* Get the prom major version. */
+extern int prom_version(void);
+
+/* Get the prom plugin revision. */
+extern int prom_getrev(void);
+
+/* Get the prom firmware revision. */
+extern int prom_getprev(void);
+
+/* Character operations to/from the console.... */
+
+/* Non-blocking get character from console. */
+extern int prom_nbgetchar(void);
+
+/* Non-blocking put character to console. */
+extern int prom_nbputchar(char character);
+
+/* Blocking get character from console. */
+extern char prom_getchar(void);
+
+/* Blocking put character to console. */
+extern void prom_putchar(char character);
+
+/* Prom's internal routines, don't use in kernel/boot code. */
+extern void prom_printf(char *fmt, ...);
+extern void prom_write(const char *buf, unsigned int len);
+
+/* Multiprocessor operations... */
+
+/* Start the CPU with the given device tree node, context table, and context
+ * at the passed program counter.
+ */
+extern int prom_startcpu(int cpunode, struct linux_prom_registers *context_table,
+ int context, char *program_counter);
+
+/* Stop the CPU with the passed device tree node. */
+extern int prom_stopcpu(int cpunode);
+
+/* Idle the CPU with the passed device tree node. */
+extern int prom_idlecpu(int cpunode);
+
+/* Re-Start the CPU with the passed device tree node. */
+extern int prom_restartcpu(int cpunode);
+
+/* PROM memory allocation facilities... */
+
+/* Allocated at possibly the given virtual address a chunk of the
+ * indicated size.
+ */
+extern char *prom_alloc(char *virt_hint, unsigned int size);
+
+/* Free a previously allocated chunk. */
+extern void prom_free(char *virt_addr, unsigned int size);
+
+/* Sun4/sun4c specific memory-management startup hook. */
+
+/* Map the passed segment in the given context at the passed
+ * virtual address.
+ */
+extern void prom_putsegment(int context, unsigned long virt_addr,
+ int physical_segment);
+
+
+/* PROM device tree traversal functions... */
+
+#ifdef PROMLIB_INTERNAL
+
+/* Internal version of prom_getchild. */
+extern int __prom_getchild(int parent_node);
+
+/* Internal version of prom_getsibling. */
+extern int __prom_getsibling(int node);
+
+#endif
+
+
+/* Get the child node of the given node, or zero if no child exists. */
+extern int prom_getchild(int parent_node);
+
+/* Get the next sibling node of the given node, or zero if no further
+ * siblings exist.
+ */
+extern int prom_getsibling(int node);
+
+/* Get the length, at the passed node, of the given property type.
+ * Returns -1 on error (ie. no such property at this node).
+ */
+extern int prom_getproplen(int thisnode, char *property);
+
+/* Fetch the requested property using the given buffer. Returns
+ * the number of bytes the prom put into your buffer or -1 on error.
+ */
+extern int __must_check prom_getproperty(int thisnode, char *property,
+ char *prop_buffer, int propbuf_size);
+
+/* Acquire an integer property. */
+extern int prom_getint(int node, char *property);
+
+/* Acquire an integer property, with a default value. */
+extern int prom_getintdefault(int node, char *property, int defval);
+
+/* Acquire a boolean property, 0=FALSE 1=TRUE. */
+extern int prom_getbool(int node, char *prop);
+
+/* Acquire a string property, null string on error. */
+extern void prom_getstring(int node, char *prop, char *buf, int bufsize);
+
+/* Does the passed node have the given "name"? YES=1 NO=0 */
+extern int prom_nodematch(int thisnode, char *name);
+
+/* Search all siblings starting at the passed node for "name" matching
+ * the given string. Returns the node on success, zero on failure.
+ */
+extern int prom_searchsiblings(int node_start, char *name);
+
+/* Return the first property type, as a string, for the given node.
+ * Returns a null string on error.
+ */
+extern char *prom_firstprop(int node, char *buffer);
+
+/* Returns the next property after the passed property for the given
+ * node. Returns null string on failure.
+ */
+extern char *prom_nextprop(int node, char *prev_property, char *buffer);
+
+/* Returns phandle of the path specified */
+extern int prom_finddevice(char *name);
+
+/* Returns 1 if the specified node has given property. */
+extern int prom_node_has_property(int node, char *property);
+
+/* Set the indicated property at the given node with the passed value.
+ * Returns the number of bytes of your value that the prom took.
+ */
+extern int prom_setprop(int node, char *prop_name, char *prop_value,
+ int value_size);
+
+extern int prom_pathtoinode(char *path);
+extern int prom_inst2pkg(int);
+
+/* Dorking with Bus ranges... */
+
+/* Apply promlib probes OBIO ranges to registers. */
+extern void prom_apply_obio_ranges(struct linux_prom_registers *obioregs, int nregs);
+
+/* Apply ranges of any prom node (and optionally parent node as well) to registers. */
+extern void prom_apply_generic_ranges(int node, int parent,
+ struct linux_prom_registers *sbusregs, int nregs);
+
+/* CPU probing helpers. */
+int cpu_find_by_instance(int instance, int *prom_node, int *mid);
+int cpu_find_by_mid(int mid, int *prom_node);
+int cpu_get_hwmid(int prom_node);
+
+extern spinlock_t prom_lock;
+
+#endif /* !(__SPARC_OPLIB_H) */
--- /dev/null
+/* oplib.h: Describes the interface and available routines in the
+ * Linux Prom library.
+ *
+ * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1996 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+
+#ifndef __SPARC64_OPLIB_H
+#define __SPARC64_OPLIB_H
+
+#include <asm/openprom.h>
+
+/* OBP version string. */
+extern char prom_version[];
+
+/* Root node of the prom device tree, this stays constant after
+ * initialization is complete.
+ */
+extern int prom_root_node;
+
+/* PROM stdin and stdout */
+extern int prom_stdin, prom_stdout;
+
+/* /chosen node of the prom device tree, this stays constant after
+ * initialization is complete.
+ */
+extern int prom_chosen_node;
+
+/* Helper values and strings in arch/sparc64/kernel/head.S */
+extern const char prom_peer_name[];
+extern const char prom_compatible_name[];
+extern const char prom_root_compatible[];
+extern const char prom_cpu_compatible[];
+extern const char prom_finddev_name[];
+extern const char prom_chosen_path[];
+extern const char prom_cpu_path[];
+extern const char prom_getprop_name[];
+extern const char prom_mmu_name[];
+extern const char prom_callmethod_name[];
+extern const char prom_translate_name[];
+extern const char prom_map_name[];
+extern const char prom_unmap_name[];
+extern int prom_mmu_ihandle_cache;
+extern unsigned int prom_boot_mapped_pc;
+extern unsigned int prom_boot_mapping_mode;
+extern unsigned long prom_boot_mapping_phys_high, prom_boot_mapping_phys_low;
+
+struct linux_mlist_p1275 {
+ struct linux_mlist_p1275 *theres_more;
+ unsigned long start_adr;
+ unsigned long num_bytes;
+};
+
+struct linux_mem_p1275 {
+ struct linux_mlist_p1275 **p1275_totphys;
+ struct linux_mlist_p1275 **p1275_prommap;
+ struct linux_mlist_p1275 **p1275_available; /* What we can use */
+};
+
+/* The functions... */
+
+/* You must call prom_init() before using any of the library services,
+ * preferably as early as possible. Pass it the romvec pointer.
+ */
+extern void prom_init(void *cif_handler, void *cif_stack);
+
+/* Boot argument acquisition, returns the boot command line string. */
+extern char *prom_getbootargs(void);
+
+/* Device utilities. */
+
+/* Device operations. */
+
+/* Open the device described by the passed string. Note, that the format
+ * of the string is different on V0 vs. V2->higher proms. The caller must
+ * know what he/she is doing! Returns the device descriptor, an int.
+ */
+extern int prom_devopen(const char *device_string);
+
+/* Close a previously opened device described by the passed integer
+ * descriptor.
+ */
+extern int prom_devclose(int device_handle);
+
+/* Do a seek operation on the device described by the passed integer
+ * descriptor.
+ */
+extern void prom_seek(int device_handle, unsigned int seek_hival,
+ unsigned int seek_lowval);
+
+/* Miscellaneous routines, don't really fit in any category per se. */
+
+/* Reboot the machine with the command line passed. */
+extern void prom_reboot(const char *boot_command);
+
+/* Evaluate the forth string passed. */
+extern void prom_feval(const char *forth_string);
+
+/* Enter the prom, with possibility of continuation with the 'go'
+ * command in newer proms.
+ */
+extern void prom_cmdline(void);
+
+/* Enter the prom, with no chance of continuation for the stand-alone
+ * which calls this.
+ */
+extern void prom_halt(void) __attribute__ ((noreturn));
+
+/* Halt and power-off the machine. */
+extern void prom_halt_power_off(void) __attribute__ ((noreturn));
+
+/* Set the PROM 'sync' callback function to the passed function pointer.
+ * When the user gives the 'sync' command at the prom prompt while the
+ * kernel is still active, the prom will call this routine.
+ *
+ */
+typedef int (*callback_func_t)(long *cmd);
+extern void prom_setcallback(callback_func_t func_ptr);
+
+/* Acquire the IDPROM of the root node in the prom device tree. This
+ * gets passed a buffer where you would like it stuffed. The return value
+ * is the format type of this idprom or 0xff on error.
+ */
+extern unsigned char prom_get_idprom(char *idp_buffer, int idpbuf_size);
+
+/* Character operations to/from the console.... */
+
+/* Non-blocking get character from console. */
+extern int prom_nbgetchar(void);
+
+/* Non-blocking put character to console. */
+extern int prom_nbputchar(char character);
+
+/* Blocking get character from console. */
+extern char prom_getchar(void);
+
+/* Blocking put character to console. */
+extern void prom_putchar(char character);
+
+/* Prom's internal routines, don't use in kernel/boot code. */
+extern void prom_printf(const char *fmt, ...);
+extern void prom_write(const char *buf, unsigned int len);
+
+/* Multiprocessor operations... */
+#ifdef CONFIG_SMP
+/* Start the CPU with the given device tree node at the passed program
+ * counter with the given arg passed in via register %o0.
+ */
+extern void prom_startcpu(int cpunode, unsigned long pc, unsigned long arg);
+
+/* Start the CPU with the given cpu ID at the passed program
+ * counter with the given arg passed in via register %o0.
+ */
+extern void prom_startcpu_cpuid(int cpuid, unsigned long pc, unsigned long arg);
+
+/* Stop the CPU with the given cpu ID. */
+extern void prom_stopcpu_cpuid(int cpuid);
+
+/* Stop the current CPU. */
+extern void prom_stopself(void);
+
+/* Idle the current CPU. */
+extern void prom_idleself(void);
+
+/* Resume the CPU with the passed device tree node. */
+extern void prom_resumecpu(int cpunode);
+#endif
+
+/* Power management interfaces. */
+
+/* Put the current CPU to sleep. */
+extern void prom_sleepself(void);
+
+/* Put the entire system to sleep. */
+extern int prom_sleepsystem(void);
+
+/* Initiate a wakeup event. */
+extern int prom_wakeupsystem(void);
+
+/* MMU and memory related OBP interfaces. */
+
+/* Get unique string identifying SIMM at given physical address. */
+extern int prom_getunumber(int syndrome_code,
+ unsigned long phys_addr,
+ char *buf, int buflen);
+
+/* Retain physical memory to the caller across soft resets. */
+extern unsigned long prom_retain(const char *name,
+ unsigned long pa_low, unsigned long pa_high,
+ long size, long align);
+
+/* Load explicit I/D TLB entries into the calling processor. */
+extern long prom_itlb_load(unsigned long index,
+ unsigned long tte_data,
+ unsigned long vaddr);
+
+extern long prom_dtlb_load(unsigned long index,
+ unsigned long tte_data,
+ unsigned long vaddr);
+
+/* Map/Unmap client program address ranges. First the format of
+ * the mapping mode argument.
+ */
+#define PROM_MAP_WRITE 0x0001 /* Writable */
+#define PROM_MAP_READ 0x0002 /* Readable - sw */
+#define PROM_MAP_EXEC 0x0004 /* Executable - sw */
+#define PROM_MAP_LOCKED 0x0010 /* Locked, use i/dtlb load calls for this instead */
+#define PROM_MAP_CACHED 0x0020 /* Cacheable in both L1 and L2 caches */
+#define PROM_MAP_SE 0x0040 /* Side-Effects */
+#define PROM_MAP_GLOB 0x0080 /* Global */
+#define PROM_MAP_IE 0x0100 /* Invert-Endianness */
+#define PROM_MAP_DEFAULT (PROM_MAP_WRITE | PROM_MAP_READ | PROM_MAP_EXEC | PROM_MAP_CACHED)
+
+extern int prom_map(int mode, unsigned long size,
+ unsigned long vaddr, unsigned long paddr);
+extern void prom_unmap(unsigned long size, unsigned long vaddr);
+
+
+/* PROM device tree traversal functions... */
+
+#ifdef PROMLIB_INTERNAL
+
+/* Internal version of prom_getchild. */
+extern int __prom_getchild(int parent_node);
+
+/* Internal version of prom_getsibling. */
+extern int __prom_getsibling(int node);
+
+#endif
+
+/* Get the child node of the given node, or zero if no child exists. */
+extern int prom_getchild(int parent_node);
+
+/* Get the next sibling node of the given node, or zero if no further
+ * siblings exist.
+ */
+extern int prom_getsibling(int node);
+
+/* Get the length, at the passed node, of the given property type.
+ * Returns -1 on error (ie. no such property at this node).
+ */
+extern int prom_getproplen(int thisnode, const char *property);
+
+/* Fetch the requested property using the given buffer. Returns
+ * the number of bytes the prom put into your buffer or -1 on error.
+ */
+extern int prom_getproperty(int thisnode, const char *property,
+ char *prop_buffer, int propbuf_size);
+
+/* Acquire an integer property. */
+extern int prom_getint(int node, const char *property);
+
+/* Acquire an integer property, with a default value. */
+extern int prom_getintdefault(int node, const char *property, int defval);
+
+/* Acquire a boolean property, 0=FALSE 1=TRUE. */
+extern int prom_getbool(int node, const char *prop);
+
+/* Acquire a string property, null string on error. */
+extern void prom_getstring(int node, const char *prop, char *buf, int bufsize);
+
+/* Does the passed node have the given "name"? YES=1 NO=0 */
+extern int prom_nodematch(int thisnode, const char *name);
+
+/* Search all siblings starting at the passed node for "name" matching
+ * the given string. Returns the node on success, zero on failure.
+ */
+extern int prom_searchsiblings(int node_start, const char *name);
+
+/* Return the first property type, as a string, for the given node.
+ * Returns a null string on error. Buffer should be at least 32B long.
+ */
+extern char *prom_firstprop(int node, char *buffer);
+
+/* Returns the next property after the passed property for the given
+ * node. Returns null string on failure. Buffer should be at least 32B long.
+ */
+extern char *prom_nextprop(int node, const char *prev_property, char *buffer);
+
+/* Returns 1 if the specified node has given property. */
+extern int prom_node_has_property(int node, const char *property);
+
+/* Returns phandle of the path specified */
+extern int prom_finddevice(const char *name);
+
+/* Set the indicated property at the given node with the passed value.
+ * Returns the number of bytes of your value that the prom took.
+ */
+extern int prom_setprop(int node, const char *prop_name, char *prop_value,
+ int value_size);
+
+extern int prom_pathtoinode(const char *path);
+extern int prom_inst2pkg(int);
+extern int prom_service_exists(const char *service_name);
+extern void prom_sun4v_guest_soft_state(void);
+
+extern int prom_ihandle2path(int handle, char *buffer, int bufsize);
+
+/* Client interface level routines. */
+extern long p1275_cmd(const char *, long, ...);
+
+#if 0
+#define P1275_SIZE(x) ((((long)((x) / 32)) << 32) | (x))
+#else
+#define P1275_SIZE(x) x
+#endif
+
+/* We support at most 16 input and 1 output argument */
+#define P1275_ARG_NUMBER 0
+#define P1275_ARG_IN_STRING 1
+#define P1275_ARG_OUT_BUF 2
+#define P1275_ARG_OUT_32B 3
+#define P1275_ARG_IN_FUNCTION 4
+#define P1275_ARG_IN_BUF 5
+#define P1275_ARG_IN_64B 6
+
+#define P1275_IN(x) ((x) & 0xf)
+#define P1275_OUT(x) (((x) << 4) & 0xf0)
+#define P1275_INOUT(i,o) (P1275_IN(i)|P1275_OUT(o))
+#define P1275_ARG(n,x) ((x) << ((n)*3 + 8))
+
+#endif /* !(__SPARC64_OPLIB_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_PAGE_H
+#define ___ASM_SPARC_PAGE_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/page_64.h>
+#else
+#include <asm/page_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * page.h: Various defines and such for MMU operations on the Sparc for
+ * the Linux kernel.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_PAGE_H
+#define _SPARC_PAGE_H
+
+#ifdef CONFIG_SUN4
+#define PAGE_SHIFT 13
+#else
+#define PAGE_SHIFT 12
+#endif
+#ifndef __ASSEMBLY__
+/* I have my suspicions... -DaveM */
+#define PAGE_SIZE (1UL << PAGE_SHIFT)
+#else
+#define PAGE_SIZE (1 << PAGE_SHIFT)
+#endif
+#define PAGE_MASK (~(PAGE_SIZE-1))
+
+#include <asm/btfixup.h>
+
+#ifndef __ASSEMBLY__
+
+#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
+#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE)
+#define clear_user_page(addr, vaddr, page) \
+ do { clear_page(addr); \
+ sparc_flush_page_to_ram(page); \
+ } while (0)
+#define copy_user_page(to, from, vaddr, page) \
+ do { copy_page(to, from); \
+ sparc_flush_page_to_ram(page); \
+ } while (0)
+
+/* The following structure is used to hold the physical
+ * memory configuration of the machine. This is filled in
+ * prom_meminit() and is later used by mem_init() to set up
+ * mem_map[]. We statically allocate SPARC_PHYS_BANKS+1 of
+ * these structs, this is arbitrary. The entry after the
+ * last valid one has num_bytes==0.
+ */
+struct sparc_phys_banks {
+ unsigned long base_addr;
+ unsigned long num_bytes;
+};
+
+#define SPARC_PHYS_BANKS 32
+
+extern struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1];
+
+/* Cache alias structure. Entry is valid if context != -1. */
+struct cache_palias {
+ unsigned long vaddr;
+ int context;
+};
+
+/* passing structs on the Sparc slow us down tremendously... */
+
+/* #define STRICT_MM_TYPECHECKS */
+
+#ifdef STRICT_MM_TYPECHECKS
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct { unsigned long pte; } pte_t;
+typedef struct { unsigned long iopte; } iopte_t;
+typedef struct { unsigned long pmdv[16]; } pmd_t;
+typedef struct { unsigned long pgd; } pgd_t;
+typedef struct { unsigned long ctxd; } ctxd_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct { unsigned long iopgprot; } iopgprot_t;
+
+#define pte_val(x) ((x).pte)
+#define iopte_val(x) ((x).iopte)
+#define pmd_val(x) ((x).pmdv[0])
+#define pgd_val(x) ((x).pgd)
+#define ctxd_val(x) ((x).ctxd)
+#define pgprot_val(x) ((x).pgprot)
+#define iopgprot_val(x) ((x).iopgprot)
+
+#define __pte(x) ((pte_t) { (x) } )
+#define __iopte(x) ((iopte_t) { (x) } )
+/* #define __pmd(x) ((pmd_t) { (x) } ) */ /* XXX procedure with loop */
+#define __pgd(x) ((pgd_t) { (x) } )
+#define __ctxd(x) ((ctxd_t) { (x) } )
+#define __pgprot(x) ((pgprot_t) { (x) } )
+#define __iopgprot(x) ((iopgprot_t) { (x) } )
+
+#else
+/*
+ * .. while these make it easier on the compiler
+ */
+typedef unsigned long pte_t;
+typedef unsigned long iopte_t;
+typedef struct { unsigned long pmdv[16]; } pmd_t;
+typedef unsigned long pgd_t;
+typedef unsigned long ctxd_t;
+typedef unsigned long pgprot_t;
+typedef unsigned long iopgprot_t;
+
+#define pte_val(x) (x)
+#define iopte_val(x) (x)
+#define pmd_val(x) ((x).pmdv[0])
+#define pgd_val(x) (x)
+#define ctxd_val(x) (x)
+#define pgprot_val(x) (x)
+#define iopgprot_val(x) (x)
+
+#define __pte(x) (x)
+#define __iopte(x) (x)
+/* #define __pmd(x) (x) */ /* XXX later */
+#define __pgd(x) (x)
+#define __ctxd(x) (x)
+#define __pgprot(x) (x)
+#define __iopgprot(x) (x)
+
+#endif
+
+typedef struct page *pgtable_t;
+
+extern unsigned long sparc_unmapped_base;
+
+BTFIXUPDEF_SETHI(sparc_unmapped_base)
+
+#define TASK_UNMAPPED_BASE BTFIXUP_SETHI(sparc_unmapped_base)
+
+#else /* !(__ASSEMBLY__) */
+
+#define __pgprot(x) (x)
+
+#endif /* !(__ASSEMBLY__) */
+
+#define PAGE_OFFSET 0xf0000000
+#ifndef __ASSEMBLY__
+extern unsigned long phys_base;
+extern unsigned long pfn_base;
+#endif
+#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + phys_base)
+#define __va(x) ((void *)((unsigned long) (x) - phys_base + PAGE_OFFSET))
+
+#define virt_to_phys __pa
+#define phys_to_virt __va
+
+#define ARCH_PFN_OFFSET (pfn_base)
+#define virt_to_page(kaddr) (mem_map + ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT)))
+
+#define pfn_valid(pfn) (((pfn) >= (pfn_base)) && (((pfn)-(pfn_base)) < max_mapnr))
+#define virt_addr_valid(kaddr) ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT) < max_mapnr)
+
+#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
+ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#include <asm-generic/memory_model.h>
+#include <asm-generic/page.h>
+
+#endif /* _SPARC_PAGE_H */
--- /dev/null
+#ifndef _SPARC64_PAGE_H
+#define _SPARC64_PAGE_H
+
+#include <linux/const.h>
+
+#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
+#define PAGE_SHIFT 13
+#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
+#define PAGE_SHIFT 16
+#else
+#error No page size specified in kernel configuration
+#endif
+
+#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
+#define PAGE_MASK (~(PAGE_SIZE-1))
+
+/* Flushing for D-cache alias handling is only needed if
+ * the page size is smaller than 16K.
+ */
+#if PAGE_SHIFT < 14
+#define DCACHE_ALIASING_POSSIBLE
+#endif
+
+#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#define HPAGE_SHIFT 22
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
+#define HPAGE_SHIFT 19
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#define HPAGE_SHIFT 16
+#endif
+
+#ifdef CONFIG_HUGETLB_PAGE
+#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
+#define HPAGE_MASK (~(HPAGE_SIZE - 1UL))
+#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
+#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
+#endif
+
+#ifndef __ASSEMBLY__
+
+extern void _clear_page(void *page);
+#define clear_page(X) _clear_page((void *)(X))
+struct page;
+extern void clear_user_page(void *addr, unsigned long vaddr, struct page *page);
+#define copy_page(X,Y) memcpy((void *)(X), (void *)(Y), PAGE_SIZE)
+extern void copy_user_page(void *to, void *from, unsigned long vaddr, struct page *topage);
+
+/* Unlike sparc32, sparc64's parameter passing API is more
+ * sane in that structures which as small enough are passed
+ * in registers instead of on the stack. Thus, setting
+ * STRICT_MM_TYPECHECKS does not generate worse code so
+ * let's enable it to get the type checking.
+ */
+
+#define STRICT_MM_TYPECHECKS
+
+#ifdef STRICT_MM_TYPECHECKS
+/* These are used to make use of C type-checking.. */
+typedef struct { unsigned long pte; } pte_t;
+typedef struct { unsigned long iopte; } iopte_t;
+typedef struct { unsigned int pmd; } pmd_t;
+typedef struct { unsigned int pgd; } pgd_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+
+#define pte_val(x) ((x).pte)
+#define iopte_val(x) ((x).iopte)
+#define pmd_val(x) ((x).pmd)
+#define pgd_val(x) ((x).pgd)
+#define pgprot_val(x) ((x).pgprot)
+
+#define __pte(x) ((pte_t) { (x) } )
+#define __iopte(x) ((iopte_t) { (x) } )
+#define __pmd(x) ((pmd_t) { (x) } )
+#define __pgd(x) ((pgd_t) { (x) } )
+#define __pgprot(x) ((pgprot_t) { (x) } )
+
+#else
+/* .. while these make it easier on the compiler */
+typedef unsigned long pte_t;
+typedef unsigned long iopte_t;
+typedef unsigned int pmd_t;
+typedef unsigned int pgd_t;
+typedef unsigned long pgprot_t;
+
+#define pte_val(x) (x)
+#define iopte_val(x) (x)
+#define pmd_val(x) (x)
+#define pgd_val(x) (x)
+#define pgprot_val(x) (x)
+
+#define __pte(x) (x)
+#define __iopte(x) (x)
+#define __pmd(x) (x)
+#define __pgd(x) (x)
+#define __pgprot(x) (x)
+
+#endif /* (STRICT_MM_TYPECHECKS) */
+
+typedef struct page *pgtable_t;
+
+#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_32BIT) ? \
+ (_AC(0x0000000070000000,UL)) : \
+ (_AC(0xfffff80000000000,UL) + (1UL << 32UL)))
+
+#include <asm-generic/memory_model.h>
+
+#endif /* !(__ASSEMBLY__) */
+
+/* We used to stick this into a hard-coded global register (%g4)
+ * but that does not make sense anymore.
+ */
+#define PAGE_OFFSET _AC(0xFFFFF80000000000,UL)
+
+#ifndef __ASSEMBLY__
+
+#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
+#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
+
+#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
+
+#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr)>>PAGE_SHIFT)
+
+#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+
+#define virt_to_phys __pa
+#define phys_to_virt __va
+
+#endif /* !(__ASSEMBLY__) */
+
+#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
+ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#include <asm-generic/page.h>
+
+#endif /* _SPARC64_PAGE_H */
--- /dev/null
+#ifndef _ASMSPARC_PARAM_H
+#define _ASMSPARC_PARAM_H
+
+#ifdef __KERNEL__
+# define HZ CONFIG_HZ /* Internal kernel timer frequency */
+# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
+# define CLOCKS_PER_SEC (USER_HZ)
+#endif
+
+#ifndef HZ
+#define HZ 100
+#endif
+
+#define EXEC_PAGESIZE 8192 /* Thanks for sun4's we carry baggage... */
+
+#ifndef NOGROUP
+#define NOGROUP (-1)
+#endif
+
+#define MAXHOSTNAMELEN 64 /* max length of hostname */
+
+#endif
--- /dev/null
+/* parport.h: sparc64 specific parport initialization and dma.
+ *
+ * Copyright (C) 1999 Eddie C. Dost (ecd@skynet.be)
+ */
+
+#ifndef _ASM_SPARC64_PARPORT_H
+#define _ASM_SPARC64_PARPORT_H 1
+
+#include <asm/ebus.h>
+#include <asm/ns87303.h>
+#include <asm/of_device.h>
+#include <asm/prom.h>
+
+#define PARPORT_PC_MAX_PORTS PARPORT_MAX
+
+/*
+ * While sparc64 doesn't have an ISA DMA API, we provide something that looks
+ * close enough to make parport_pc happy
+ */
+#define HAS_DMA
+
+static DEFINE_SPINLOCK(dma_spin_lock);
+
+#define claim_dma_lock() \
+({ unsigned long flags; \
+ spin_lock_irqsave(&dma_spin_lock, flags); \
+ flags; \
+})
+
+#define release_dma_lock(__flags) \
+ spin_unlock_irqrestore(&dma_spin_lock, __flags);
+
+static struct sparc_ebus_info {
+ struct ebus_dma_info info;
+ unsigned int addr;
+ unsigned int count;
+ int lock;
+
+ struct parport *port;
+} sparc_ebus_dmas[PARPORT_PC_MAX_PORTS];
+
+static DECLARE_BITMAP(dma_slot_map, PARPORT_PC_MAX_PORTS);
+
+static inline int request_dma(unsigned int dmanr, const char *device_id)
+{
+ if (dmanr >= PARPORT_PC_MAX_PORTS)
+ return -EINVAL;
+ if (xchg(&sparc_ebus_dmas[dmanr].lock, 1) != 0)
+ return -EBUSY;
+ return 0;
+}
+
+static inline void free_dma(unsigned int dmanr)
+{
+ if (dmanr >= PARPORT_PC_MAX_PORTS) {
+ printk(KERN_WARNING "Trying to free DMA%d\n", dmanr);
+ return;
+ }
+ if (xchg(&sparc_ebus_dmas[dmanr].lock, 0) == 0) {
+ printk(KERN_WARNING "Trying to free free DMA%d\n", dmanr);
+ return;
+ }
+}
+
+static inline void enable_dma(unsigned int dmanr)
+{
+ ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 1);
+
+ if (ebus_dma_request(&sparc_ebus_dmas[dmanr].info,
+ sparc_ebus_dmas[dmanr].addr,
+ sparc_ebus_dmas[dmanr].count))
+ BUG();
+}
+
+static inline void disable_dma(unsigned int dmanr)
+{
+ ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 0);
+}
+
+static inline void clear_dma_ff(unsigned int dmanr)
+{
+ /* nothing */
+}
+
+static inline void set_dma_mode(unsigned int dmanr, char mode)
+{
+ ebus_dma_prepare(&sparc_ebus_dmas[dmanr].info, (mode != DMA_MODE_WRITE));
+}
+
+static inline void set_dma_addr(unsigned int dmanr, unsigned int addr)
+{
+ sparc_ebus_dmas[dmanr].addr = addr;
+}
+
+static inline void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+ sparc_ebus_dmas[dmanr].count = count;
+}
+
+static inline unsigned int get_dma_residue(unsigned int dmanr)
+{
+ return ebus_dma_residue(&sparc_ebus_dmas[dmanr].info);
+}
+
+static int __devinit ecpp_probe(struct of_device *op, const struct of_device_id *match)
+{
+ unsigned long base = op->resource[0].start;
+ unsigned long config = op->resource[1].start;
+ unsigned long d_base = op->resource[2].start;
+ unsigned long d_len;
+ struct device_node *parent;
+ struct parport *p;
+ int slot, err;
+
+ parent = op->node->parent;
+ if (!strcmp(parent->name, "dma")) {
+ p = parport_pc_probe_port(base, base + 0x400,
+ op->irqs[0], PARPORT_DMA_NOFIFO,
+ op->dev.parent->parent);
+ if (!p)
+ return -ENOMEM;
+ dev_set_drvdata(&op->dev, p);
+ return 0;
+ }
+
+ for (slot = 0; slot < PARPORT_PC_MAX_PORTS; slot++) {
+ if (!test_and_set_bit(slot, dma_slot_map))
+ break;
+ }
+ err = -ENODEV;
+ if (slot >= PARPORT_PC_MAX_PORTS)
+ goto out_err;
+
+ spin_lock_init(&sparc_ebus_dmas[slot].info.lock);
+
+ d_len = (op->resource[2].end - d_base) + 1UL;
+ sparc_ebus_dmas[slot].info.regs =
+ of_ioremap(&op->resource[2], 0, d_len, "ECPP DMA");
+
+ if (!sparc_ebus_dmas[slot].info.regs)
+ goto out_clear_map;
+
+ sparc_ebus_dmas[slot].info.flags = 0;
+ sparc_ebus_dmas[slot].info.callback = NULL;
+ sparc_ebus_dmas[slot].info.client_cookie = NULL;
+ sparc_ebus_dmas[slot].info.irq = 0xdeadbeef;
+ strcpy(sparc_ebus_dmas[slot].info.name, "parport");
+ if (ebus_dma_register(&sparc_ebus_dmas[slot].info))
+ goto out_unmap_regs;
+
+ ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 1);
+
+ /* Configure IRQ to Push Pull, Level Low */
+ /* Enable ECP, set bit 2 of the CTR first */
+ outb(0x04, base + 0x02);
+ ns87303_modify(config, PCR,
+ PCR_EPP_ENABLE |
+ PCR_IRQ_ODRAIN,
+ PCR_ECP_ENABLE |
+ PCR_ECP_CLK_ENA |
+ PCR_IRQ_POLAR);
+
+ /* CTR bit 5 controls direction of port */
+ ns87303_modify(config, PTR,
+ 0, PTR_LPT_REG_DIR);
+
+ p = parport_pc_probe_port(base, base + 0x400,
+ op->irqs[0],
+ slot,
+ op->dev.parent);
+ err = -ENOMEM;
+ if (!p)
+ goto out_disable_irq;
+
+ dev_set_drvdata(&op->dev, p);
+
+ return 0;
+
+out_disable_irq:
+ ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 0);
+ ebus_dma_unregister(&sparc_ebus_dmas[slot].info);
+
+out_unmap_regs:
+ of_iounmap(&op->resource[2], sparc_ebus_dmas[slot].info.regs, d_len);
+
+out_clear_map:
+ clear_bit(slot, dma_slot_map);
+
+out_err:
+ return err;
+}
+
+static int __devexit ecpp_remove(struct of_device *op)
+{
+ struct parport *p = dev_get_drvdata(&op->dev);
+ int slot = p->dma;
+
+ parport_pc_unregister_port(p);
+
+ if (slot != PARPORT_DMA_NOFIFO) {
+ unsigned long d_base = op->resource[2].start;
+ unsigned long d_len;
+
+ d_len = (op->resource[2].end - d_base) + 1UL;
+
+ ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 0);
+ ebus_dma_unregister(&sparc_ebus_dmas[slot].info);
+ of_iounmap(&op->resource[2],
+ sparc_ebus_dmas[slot].info.regs,
+ d_len);
+ clear_bit(slot, dma_slot_map);
+ }
+
+ return 0;
+}
+
+static struct of_device_id ecpp_match[] = {
+ {
+ .name = "ecpp",
+ },
+ {
+ .name = "parallel",
+ .compatible = "ecpp",
+ },
+ {
+ .name = "parallel",
+ .compatible = "ns87317-ecpp",
+ },
+ {},
+};
+
+static struct of_platform_driver ecpp_driver = {
+ .name = "ecpp",
+ .match_table = ecpp_match,
+ .probe = ecpp_probe,
+ .remove = __devexit_p(ecpp_remove),
+};
+
+static int parport_pc_find_nonpci_ports(int autoirq, int autodma)
+{
+ of_register_driver(&ecpp_driver, &of_bus_type);
+
+ return 0;
+}
+
+#endif /* !(_ASM_SPARC64_PARPORT_H */
--- /dev/null
+/*
+ *
+ * pbm.h: PCI bus module pseudo driver software state
+ * Adopted from sparc64 by V. Roganov and G. Raiko
+ *
+ * Original header:
+ * pbm.h: U2P PCI bus module pseudo driver software state.
+ *
+ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ *
+ * To put things into perspective, consider sparc64 with a few PCI controllers.
+ * Each type would have an own structure, with instances related one to one.
+ * We have only pcic on sparc, but we want to be compatible with sparc64 pbm.h.
+ * All three represent different abstractions.
+ * pci_bus - Linux PCI subsystem view of a PCI bus (including bridged buses)
+ * pbm - Arch-specific view of a PCI bus (sparc or sparc64)
+ * pcic - Chip-specific information for PCIC.
+ */
+
+#ifndef __SPARC_PBM_H
+#define __SPARC_PBM_H
+
+#include <linux/pci.h>
+#include <asm/oplib.h>
+#include <asm/prom.h>
+
+struct linux_pbm_info {
+ int prom_node;
+ char prom_name[64];
+ /* struct linux_prom_pci_ranges pbm_ranges[PROMREG_MAX]; */
+ /* int num_pbm_ranges; */
+
+ /* Now things for the actual PCI bus probes. */
+ unsigned int pci_first_busno; /* Can it be nonzero? */
+ struct pci_bus *pci_bus; /* Was inline, MJ allocs now */
+};
+
+/* PCI devices which are not bridges have this placed in their pci_dev
+ * sysdata member. This makes OBP aware PCI device drivers easier to
+ * code.
+ */
+struct pcidev_cookie {
+ struct linux_pbm_info *pbm;
+ struct device_node *prom_node;
+};
+
+#endif /* !(__SPARC_PBM_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_PCI_H
+#define ___ASM_SPARC_PCI_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/pci_64.h>
+#else
+#include <asm/pci_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef __SPARC_PCI_H
+#define __SPARC_PCI_H
+
+#ifdef __KERNEL__
+
+/* Can be used to override the logic in pci_scan_bus for skipping
+ * already-configured bus numbers - to be used for buggy BIOSes
+ * or architectures with incomplete PCI setup by the loader.
+ */
+#define pcibios_assign_all_busses() 0
+#define pcibios_scan_all_fns(a, b) 0
+
+#define PCIBIOS_MIN_IO 0UL
+#define PCIBIOS_MIN_MEM 0UL
+
+#define PCI_IRQ_NONE 0xffffffff
+
+static inline void pcibios_set_master(struct pci_dev *dev)
+{
+ /* No special bus mastering setup handling */
+}
+
+static inline void pcibios_penalize_isa_irq(int irq, int active)
+{
+ /* We don't do dynamic PCI IRQ allocation */
+}
+
+/* Dynamic DMA mapping stuff.
+ */
+#define PCI_DMA_BUS_IS_PHYS (0)
+
+#include <asm/scatterlist.h>
+
+struct pci_dev;
+
+/* Allocate and map kernel buffer using consistent mode DMA for a device.
+ * hwdev should be valid struct pci_dev pointer for PCI devices.
+ */
+extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle);
+
+/* Free and unmap a consistent DMA buffer.
+ * cpu_addr is what was returned from pci_alloc_consistent,
+ * size must be the same as what as passed into pci_alloc_consistent,
+ * and likewise dma_addr must be the same as what *dma_addrp was set to.
+ *
+ * References to the memory and mappings assosciated with cpu_addr/dma_addr
+ * past this call are illegal.
+ */
+extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle);
+
+/* Map a single buffer of the indicated size for DMA in streaming mode.
+ * The 32-bit bus address to use is returned.
+ *
+ * Once the device is given the dma address, the device owns this memory
+ * until either pci_unmap_single or pci_dma_sync_single_for_cpu is performed.
+ */
+extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction);
+
+/* Unmap a single streaming mode DMA translation. The dma_addr and size
+ * must match what was provided for in a previous pci_map_single call. All
+ * other usages are undefined.
+ *
+ * After this call, reads by the cpu to the buffer are guaranteed to see
+ * whatever the device wrote there.
+ */
+extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction);
+
+/* pci_unmap_{single,page} is not a nop, thus... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
+ dma_addr_t ADDR_NAME;
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
+ __u32 LEN_NAME;
+#define pci_unmap_addr(PTR, ADDR_NAME) \
+ ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
+ (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME) \
+ ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
+ (((PTR)->LEN_NAME) = (VAL))
+
+/*
+ * Same as above, only with pages instead of mapped addresses.
+ */
+extern dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page,
+ unsigned long offset, size_t size, int direction);
+extern void pci_unmap_page(struct pci_dev *hwdev,
+ dma_addr_t dma_address, size_t size, int direction);
+
+/* Map a set of buffers described by scatterlist in streaming
+ * mode for DMA. This is the scather-gather version of the
+ * above pci_map_single interface. Here the scatter gather list
+ * elements are each tagged with the appropriate dma address
+ * and length. They are obtained via sg_dma_{address,length}(SG).
+ *
+ * NOTE: An implementation may be able to use a smaller number of
+ * DMA address/length pairs than there are SG table elements.
+ * (for example via virtual mapping capabilities)
+ * The routine returns the number of addr/length pairs actually
+ * used, at most nents.
+ *
+ * Device ownership issues as mentioned above for pci_map_single are
+ * the same here.
+ */
+extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction);
+
+/* Unmap a set of streaming mode DMA translations.
+ * Again, cpu read rules concerning calls here are the same as for
+ * pci_unmap_single() above.
+ */
+extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nhwents, int direction);
+
+/* Make physical memory consistent for a single
+ * streaming mode DMA translation after a transfer.
+ *
+ * If you perform a pci_map_single() but wish to interrogate the
+ * buffer using the cpu, yet do not wish to teardown the PCI dma
+ * mapping, you must call this function before doing so. At the
+ * next point you give the PCI dma address back to the card, you
+ * must first perform a pci_dma_sync_for_device, and then the device
+ * again owns the buffer.
+ */
+extern void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
+extern void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
+
+/* Make physical memory consistent for a set of streaming
+ * mode DMA translations after a transfer.
+ *
+ * The same as pci_dma_sync_single_* but for a scatter-gather list,
+ * same rules and usage.
+ */
+extern void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
+extern void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
+
+/* Return whether the given PCI device DMA address mask can
+ * be supported properly. For example, if your device can
+ * only drive the low 24-bits during PCI bus mastering, then
+ * you would pass 0x00ffffff as the mask to this function.
+ */
+static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
+{
+ return 1;
+}
+
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+ enum pci_dma_burst_strategy *strat,
+ unsigned long *strategy_parameter)
+{
+ *strat = PCI_DMA_BURST_INFINITY;
+ *strategy_parameter = ~0UL;
+}
+#endif
+
+#define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0)
+
+static inline int pci_dma_mapping_error(struct pci_dev *pdev,
+ dma_addr_t dma_addr)
+{
+ return (dma_addr == PCI_DMA_ERROR_CODE);
+}
+
+struct device_node;
+extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
+
+#endif /* __KERNEL__ */
+
+/* generic pci stuff */
+#include <asm-generic/pci.h>
+
+#endif /* __SPARC_PCI_H */
--- /dev/null
+#ifndef __SPARC64_PCI_H
+#define __SPARC64_PCI_H
+
+#ifdef __KERNEL__
+
+#include <linux/dma-mapping.h>
+
+/* Can be used to override the logic in pci_scan_bus for skipping
+ * already-configured bus numbers - to be used for buggy BIOSes
+ * or architectures with incomplete PCI setup by the loader.
+ */
+#define pcibios_assign_all_busses() 0
+#define pcibios_scan_all_fns(a, b) 0
+
+#define PCIBIOS_MIN_IO 0UL
+#define PCIBIOS_MIN_MEM 0UL
+
+#define PCI_IRQ_NONE 0xffffffff
+
+#define PCI_CACHE_LINE_BYTES 64
+
+static inline void pcibios_set_master(struct pci_dev *dev)
+{
+ /* No special bus mastering setup handling */
+}
+
+static inline void pcibios_penalize_isa_irq(int irq, int active)
+{
+ /* We don't do dynamic PCI IRQ allocation */
+}
+
+/* The PCI address space does not equal the physical memory
+ * address space. The networking and block device layers use
+ * this boolean for bounce buffer decisions.
+ */
+#define PCI_DMA_BUS_IS_PHYS (0)
+
+static inline void *pci_alloc_consistent(struct pci_dev *pdev, size_t size,
+ dma_addr_t *dma_handle)
+{
+ return dma_alloc_coherent(&pdev->dev, size, dma_handle, GFP_ATOMIC);
+}
+
+static inline void pci_free_consistent(struct pci_dev *pdev, size_t size,
+ void *vaddr, dma_addr_t dma_handle)
+{
+ return dma_free_coherent(&pdev->dev, size, vaddr, dma_handle);
+}
+
+static inline dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr,
+ size_t size, int direction)
+{
+ return dma_map_single(&pdev->dev, ptr, size,
+ (enum dma_data_direction) direction);
+}
+
+static inline void pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr,
+ size_t size, int direction)
+{
+ dma_unmap_single(&pdev->dev, dma_addr, size,
+ (enum dma_data_direction) direction);
+}
+
+#define pci_map_page(dev, page, off, size, dir) \
+ pci_map_single(dev, (page_address(page) + (off)), size, dir)
+#define pci_unmap_page(dev,addr,sz,dir) \
+ pci_unmap_single(dev,addr,sz,dir)
+
+/* pci_unmap_{single,page} is not a nop, thus... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
+ dma_addr_t ADDR_NAME;
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
+ __u32 LEN_NAME;
+#define pci_unmap_addr(PTR, ADDR_NAME) \
+ ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
+ (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME) \
+ ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
+ (((PTR)->LEN_NAME) = (VAL))
+
+static inline int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sg,
+ int nents, int direction)
+{
+ return dma_map_sg(&pdev->dev, sg, nents,
+ (enum dma_data_direction) direction);
+}
+
+static inline void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sg,
+ int nents, int direction)
+{
+ dma_unmap_sg(&pdev->dev, sg, nents,
+ (enum dma_data_direction) direction);
+}
+
+static inline void pci_dma_sync_single_for_cpu(struct pci_dev *pdev,
+ dma_addr_t dma_handle,
+ size_t size, int direction)
+{
+ dma_sync_single_for_cpu(&pdev->dev, dma_handle, size,
+ (enum dma_data_direction) direction);
+}
+
+static inline void pci_dma_sync_single_for_device(struct pci_dev *pdev,
+ dma_addr_t dma_handle,
+ size_t size, int direction)
+{
+ /* No flushing needed to sync cpu writes to the device. */
+}
+
+static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev,
+ struct scatterlist *sg,
+ int nents, int direction)
+{
+ dma_sync_sg_for_cpu(&pdev->dev, sg, nents,
+ (enum dma_data_direction) direction);
+}
+
+static inline void pci_dma_sync_sg_for_device(struct pci_dev *pdev,
+ struct scatterlist *sg,
+ int nelems, int direction)
+{
+ /* No flushing needed to sync cpu writes to the device. */
+}
+
+/* Return whether the given PCI device DMA address mask can
+ * be supported properly. For example, if your device can
+ * only drive the low 24-bits during PCI bus mastering, then
+ * you would pass 0x00ffffff as the mask to this function.
+ */
+extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
+
+/* PCI IOMMU mapping bypass support. */
+
+/* PCI 64-bit addressing works for all slots on all controller
+ * types on sparc64. However, it requires that the device
+ * can drive enough of the 64 bits.
+ */
+#define PCI64_REQUIRED_MASK (~(dma64_addr_t)0)
+#define PCI64_ADDR_BASE 0xfffc000000000000UL
+
+static inline int pci_dma_mapping_error(struct pci_dev *pdev,
+ dma_addr_t dma_addr)
+{
+ return dma_mapping_error(&pdev->dev, dma_addr);
+}
+
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+ enum pci_dma_burst_strategy *strat,
+ unsigned long *strategy_parameter)
+{
+ unsigned long cacheline_size;
+ u8 byte;
+
+ pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
+ if (byte == 0)
+ cacheline_size = 1024;
+ else
+ cacheline_size = (int) byte * 4;
+
+ *strat = PCI_DMA_BURST_BOUNDARY;
+ *strategy_parameter = cacheline_size;
+}
+#endif
+
+/* Return the index of the PCI controller for device PDEV. */
+
+extern int pci_domain_nr(struct pci_bus *bus);
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+ return 1;
+}
+
+/* Platform support for /proc/bus/pci/X/Y mmap()s. */
+
+#define HAVE_PCI_MMAP
+#define HAVE_ARCH_PCI_GET_UNMAPPED_AREA
+#define get_pci_unmapped_area get_fb_unmapped_area
+
+extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+ enum pci_mmap_state mmap_state,
+ int write_combine);
+
+extern void
+pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
+ struct resource *res);
+
+extern void
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+ struct pci_bus_region *region);
+
+extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *);
+
+static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+{
+ return PCI_IRQ_NONE;
+}
+
+struct device_node;
+extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
+
+#define HAVE_ARCH_PCI_RESOURCE_TO_USER
+extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
+ const struct resource *rsrc,
+ resource_size_t *start, resource_size_t *end);
+#endif /* __KERNEL__ */
+
+#endif /* __SPARC64_PCI_H */
--- /dev/null
+/*
+ * pcic.h: JavaEngine 1 specific PCI definitions.
+ *
+ * Copyright (C) 1998 V. Roganov and G. Raiko
+ */
+
+#ifndef __SPARC_PCIC_H
+#define __SPARC_PCIC_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <linux/smp.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <asm/pbm.h>
+
+struct linux_pcic {
+ void __iomem *pcic_regs;
+ unsigned long pcic_io;
+ void __iomem *pcic_config_space_addr;
+ void __iomem *pcic_config_space_data;
+ struct resource pcic_res_regs;
+ struct resource pcic_res_io;
+ struct resource pcic_res_cfg_addr;
+ struct resource pcic_res_cfg_data;
+ struct linux_pbm_info pbm;
+ struct pcic_ca2irq *pcic_imap;
+ int pcic_imdim;
+};
+
+extern int pcic_probe(void);
+/* Erm... MJ redefined pcibios_present() so that it does not work early. */
+extern int pcic_present(void);
+extern void sun4m_pci_init_IRQ(void);
+
+#endif
+
+/* Size of PCI I/O space which we relocate. */
+#define PCI_SPACE_SIZE 0x1000000 /* 16 MB */
+
+/* PCIC Register Set. */
+#define PCI_DIAGNOSTIC_0 0x40 /* 32 bits */
+#define PCI_SIZE_0 0x44 /* 32 bits */
+#define PCI_SIZE_1 0x48 /* 32 bits */
+#define PCI_SIZE_2 0x4c /* 32 bits */
+#define PCI_SIZE_3 0x50 /* 32 bits */
+#define PCI_SIZE_4 0x54 /* 32 bits */
+#define PCI_SIZE_5 0x58 /* 32 bits */
+#define PCI_PIO_CONTROL 0x60 /* 8 bits */
+#define PCI_DVMA_CONTROL 0x62 /* 8 bits */
+#define PCI_DVMA_CONTROL_INACTIVITY_REQ (1<<0)
+#define PCI_DVMA_CONTROL_IOTLB_ENABLE (1<<0)
+#define PCI_DVMA_CONTROL_IOTLB_DISABLE 0
+#define PCI_DVMA_CONTROL_INACTIVITY_ACK (1<<4)
+#define PCI_INTERRUPT_CONTROL 0x63 /* 8 bits */
+#define PCI_CPU_INTERRUPT_PENDING 0x64 /* 32 bits */
+#define PCI_DIAGNOSTIC_1 0x68 /* 16 bits */
+#define PCI_SOFTWARE_INT_CLEAR 0x6a /* 16 bits */
+#define PCI_SOFTWARE_INT_SET 0x6e /* 16 bits */
+#define PCI_SYS_INT_PENDING 0x70 /* 32 bits */
+#define PCI_SYS_INT_PENDING_PIO 0x40000000
+#define PCI_SYS_INT_PENDING_DMA 0x20000000
+#define PCI_SYS_INT_PENDING_PCI 0x10000000
+#define PCI_SYS_INT_PENDING_APSR 0x08000000
+#define PCI_SYS_INT_TARGET_MASK 0x74 /* 32 bits */
+#define PCI_SYS_INT_TARGET_MASK_CLEAR 0x78 /* 32 bits */
+#define PCI_SYS_INT_TARGET_MASK_SET 0x7c /* 32 bits */
+#define PCI_SYS_INT_PENDING_CLEAR 0x83 /* 8 bits */
+#define PCI_SYS_INT_PENDING_CLEAR_ALL 0x80
+#define PCI_SYS_INT_PENDING_CLEAR_PIO 0x40
+#define PCI_SYS_INT_PENDING_CLEAR_DMA 0x20
+#define PCI_SYS_INT_PENDING_CLEAR_PCI 0x10
+#define PCI_IOTLB_CONTROL 0x84 /* 8 bits */
+#define PCI_INT_SELECT_LO 0x88 /* 16 bits */
+#define PCI_ARBITRATION_SELECT 0x8a /* 16 bits */
+#define PCI_INT_SELECT_HI 0x8c /* 16 bits */
+#define PCI_HW_INT_OUTPUT 0x8e /* 16 bits */
+#define PCI_IOTLB_RAM_INPUT 0x90 /* 32 bits */
+#define PCI_IOTLB_CAM_INPUT 0x94 /* 32 bits */
+#define PCI_IOTLB_RAM_OUTPUT 0x98 /* 32 bits */
+#define PCI_IOTLB_CAM_OUTPUT 0x9c /* 32 bits */
+#define PCI_SMBAR0 0xa0 /* 8 bits */
+#define PCI_MSIZE0 0xa1 /* 8 bits */
+#define PCI_PMBAR0 0xa2 /* 8 bits */
+#define PCI_SMBAR1 0xa4 /* 8 bits */
+#define PCI_MSIZE1 0xa5 /* 8 bits */
+#define PCI_PMBAR1 0xa6 /* 8 bits */
+#define PCI_SIBAR 0xa8 /* 8 bits */
+#define PCI_SIBAR_ADDRESS_MASK 0xf
+#define PCI_ISIZE 0xa9 /* 8 bits */
+#define PCI_ISIZE_16M 0xf
+#define PCI_ISIZE_32M 0xe
+#define PCI_ISIZE_64M 0xc
+#define PCI_ISIZE_128M 0x8
+#define PCI_ISIZE_256M 0x0
+#define PCI_PIBAR 0xaa /* 8 bits */
+#define PCI_CPU_COUNTER_LIMIT_HI 0xac /* 32 bits */
+#define PCI_CPU_COUNTER_LIMIT_LO 0xb0 /* 32 bits */
+#define PCI_CPU_COUNTER_LIMIT 0xb4 /* 32 bits */
+#define PCI_SYS_LIMIT 0xb8 /* 32 bits */
+#define PCI_SYS_COUNTER 0xbc /* 32 bits */
+#define PCI_SYS_COUNTER_OVERFLOW (1<<31) /* Limit reached */
+#define PCI_SYS_LIMIT_PSEUDO 0xc0 /* 32 bits */
+#define PCI_USER_TIMER_CONTROL 0xc4 /* 8 bits */
+#define PCI_USER_TIMER_CONFIG 0xc5 /* 8 bits */
+#define PCI_COUNTER_IRQ 0xc6 /* 8 bits */
+#define PCI_COUNTER_IRQ_SET(sys_irq, cpu_irq) ((((sys_irq) & 0xf) << 4) | \
+ ((cpu_irq) & 0xf))
+#define PCI_COUNTER_IRQ_SYS(v) (((v) >> 4) & 0xf)
+#define PCI_COUNTER_IRQ_CPU(v) ((v) & 0xf)
+#define PCI_PIO_ERROR_COMMAND 0xc7 /* 8 bits */
+#define PCI_PIO_ERROR_ADDRESS 0xc8 /* 32 bits */
+#define PCI_IOTLB_ERROR_ADDRESS 0xcc /* 32 bits */
+#define PCI_SYS_STATUS 0xd0 /* 8 bits */
+#define PCI_SYS_STATUS_RESET_ENABLE (1<<0)
+#define PCI_SYS_STATUS_RESET (1<<1)
+#define PCI_SYS_STATUS_WATCHDOG_RESET (1<<4)
+#define PCI_SYS_STATUS_PCI_RESET (1<<5)
+#define PCI_SYS_STATUS_PCI_RESET_ENABLE (1<<6)
+#define PCI_SYS_STATUS_PCI_SATTELITE_MODE (1<<7)
+
+#endif /* !(__SPARC_PCIC_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_PERCPU_H
+#define ___ASM_SPARC_PERCPU_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/percpu_64.h>
+#else
+#include <asm/percpu_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef __ARCH_SPARC_PERCPU__
+#define __ARCH_SPARC_PERCPU__
+
+#include <asm-generic/percpu.h>
+
+#endif /* __ARCH_SPARC_PERCPU__ */
--- /dev/null
+#ifndef __ARCH_SPARC64_PERCPU__
+#define __ARCH_SPARC64_PERCPU__
+
+#include <linux/compiler.h>
+
+register unsigned long __local_per_cpu_offset asm("g5");
+
+#ifdef CONFIG_SMP
+
+extern void real_setup_per_cpu_areas(void);
+
+extern unsigned long __per_cpu_base;
+extern unsigned long __per_cpu_shift;
+#define __per_cpu_offset(__cpu) \
+ (__per_cpu_base + ((unsigned long)(__cpu) << __per_cpu_shift))
+#define per_cpu_offset(x) (__per_cpu_offset(x))
+
+#define __my_cpu_offset __local_per_cpu_offset
+
+#else /* ! SMP */
+
+#define real_setup_per_cpu_areas() do { } while (0)
+
+#endif /* SMP */
+
+#include <asm-generic/percpu.h>
+
+#endif /* __ARCH_SPARC64_PERCPU__ */
--- /dev/null
+/*----------------------------------------
+ PERFORMANCE INSTRUMENTATION
+ Guillaume Thouvenin 08/10/98
+ David S. Miller 10/06/98
+ ---------------------------------------*/
+#ifndef PERF_COUNTER_API
+#define PERF_COUNTER_API
+
+/* sys_perfctr() interface. First arg is operation code
+ * from enumeration below. The meaning of further arguments
+ * are determined by the operation code.
+ *
+ * int sys_perfctr(int opcode, unsigned long arg0,
+ * unsigned long arg1, unsigned long arg2)
+ *
+ * Pointers which are passed by the user are pointers to 64-bit
+ * integers.
+ *
+ * Once enabled, performance counter state is retained until the
+ * process either exits or performs an exec. That is, performance
+ * counters remain enabled for fork/clone children.
+ */
+enum perfctr_opcode {
+ /* Enable UltraSparc performance counters, ARG0 is pointer
+ * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
+ * to 64-bit accumulator for D1 counter. ARG2 is a pointer to
+ * the initial PCR register value to use.
+ */
+ PERFCTR_ON,
+
+ /* Disable UltraSparc performance counters. The PCR is written
+ * with zero and the user counter accumulator pointers and
+ * working PCR register value are forgotten.
+ */
+ PERFCTR_OFF,
+
+ /* Add current D0 and D1 PIC values into user pointers given
+ * in PERFCTR_ON operation. The PIC is cleared before returning.
+ */
+ PERFCTR_READ,
+
+ /* Clear the PIC register. */
+ PERFCTR_CLRPIC,
+
+ /* Begin using a new PCR value, the pointer to which is passed
+ * in ARG0. The PIC is also cleared after the new PCR value is
+ * written.
+ */
+ PERFCTR_SETPCR,
+
+ /* Store in pointer given in ARG0 the current PCR register value
+ * being used.
+ */
+ PERFCTR_GETPCR
+};
+
+/* I don't want the kernel's namespace to be polluted with this
+ * stuff when this file is included. --DaveM
+ */
+#ifndef __KERNEL__
+
+#define PRIV 0x00000001
+#define SYS 0x00000002
+#define USR 0x00000004
+
+/* Pic.S0 Selection Bit Field Encoding, Ultra-I/II */
+#define CYCLE_CNT 0x00000000
+#define INSTR_CNT 0x00000010
+#define DISPATCH0_IC_MISS 0x00000020
+#define DISPATCH0_STOREBUF 0x00000030
+#define IC_REF 0x00000080
+#define DC_RD 0x00000090
+#define DC_WR 0x000000A0
+#define LOAD_USE 0x000000B0
+#define EC_REF 0x000000C0
+#define EC_WRITE_HIT_RDO 0x000000D0
+#define EC_SNOOP_INV 0x000000E0
+#define EC_RD_HIT 0x000000F0
+
+/* Pic.S0 Selection Bit Field Encoding, Ultra-III */
+#define US3_CYCLE_CNT 0x00000000
+#define US3_INSTR_CNT 0x00000010
+#define US3_DISPATCH0_IC_MISS 0x00000020
+#define US3_DISPATCH0_BR_TGT 0x00000030
+#define US3_DISPATCH0_2ND_BR 0x00000040
+#define US3_RSTALL_STOREQ 0x00000050
+#define US3_RSTALL_IU_USE 0x00000060
+#define US3_IC_REF 0x00000080
+#define US3_DC_RD 0x00000090
+#define US3_DC_WR 0x000000a0
+#define US3_EC_REF 0x000000c0
+#define US3_EC_WR_HIT_RTO 0x000000d0
+#define US3_EC_SNOOP_INV 0x000000e0
+#define US3_EC_RD_MISS 0x000000f0
+#define US3_PC_PORT0_RD 0x00000100
+#define US3_SI_SNOOP 0x00000110
+#define US3_SI_CIQ_FLOW 0x00000120
+#define US3_SI_OWNED 0x00000130
+#define US3_SW_COUNT_0 0x00000140
+#define US3_IU_BR_MISS_TAKEN 0x00000150
+#define US3_IU_BR_COUNT_TAKEN 0x00000160
+#define US3_DISP_RS_MISPRED 0x00000170
+#define US3_FA_PIPE_COMPL 0x00000180
+#define US3_MC_READS_0 0x00000200
+#define US3_MC_READS_1 0x00000210
+#define US3_MC_READS_2 0x00000220
+#define US3_MC_READS_3 0x00000230
+#define US3_MC_STALLS_0 0x00000240
+#define US3_MC_STALLS_2 0x00000250
+
+/* Pic.S1 Selection Bit Field Encoding, Ultra-I/II */
+#define CYCLE_CNT_D1 0x00000000
+#define INSTR_CNT_D1 0x00000800
+#define DISPATCH0_IC_MISPRED 0x00001000
+#define DISPATCH0_FP_USE 0x00001800
+#define IC_HIT 0x00004000
+#define DC_RD_HIT 0x00004800
+#define DC_WR_HIT 0x00005000
+#define LOAD_USE_RAW 0x00005800
+#define EC_HIT 0x00006000
+#define EC_WB 0x00006800
+#define EC_SNOOP_CB 0x00007000
+#define EC_IT_HIT 0x00007800
+
+/* Pic.S1 Selection Bit Field Encoding, Ultra-III */
+#define US3_CYCLE_CNT_D1 0x00000000
+#define US3_INSTR_CNT_D1 0x00000800
+#define US3_DISPATCH0_MISPRED 0x00001000
+#define US3_IC_MISS_CANCELLED 0x00001800
+#define US3_RE_ENDIAN_MISS 0x00002000
+#define US3_RE_FPU_BYPASS 0x00002800
+#define US3_RE_DC_MISS 0x00003000
+#define US3_RE_EC_MISS 0x00003800
+#define US3_IC_MISS 0x00004000
+#define US3_DC_RD_MISS 0x00004800
+#define US3_DC_WR_MISS 0x00005000
+#define US3_RSTALL_FP_USE 0x00005800
+#define US3_EC_MISSES 0x00006000
+#define US3_EC_WB 0x00006800
+#define US3_EC_SNOOP_CB 0x00007000
+#define US3_EC_IC_MISS 0x00007800
+#define US3_RE_PC_MISS 0x00008000
+#define US3_ITLB_MISS 0x00008800
+#define US3_DTLB_MISS 0x00009000
+#define US3_WC_MISS 0x00009800
+#define US3_WC_SNOOP_CB 0x0000a000
+#define US3_WC_SCRUBBED 0x0000a800
+#define US3_WC_WB_WO_READ 0x0000b000
+#define US3_PC_SOFT_HIT 0x0000c000
+#define US3_PC_SNOOP_INV 0x0000c800
+#define US3_PC_HARD_HIT 0x0000d000
+#define US3_PC_PORT1_RD 0x0000d800
+#define US3_SW_COUNT_1 0x0000e000
+#define US3_IU_STAT_BR_MIS_UNTAKEN 0x0000e800
+#define US3_IU_STAT_BR_COUNT_UNTAKEN 0x0000f000
+#define US3_PC_MS_MISSES 0x0000f800
+#define US3_MC_WRITES_0 0x00010800
+#define US3_MC_WRITES_1 0x00011000
+#define US3_MC_WRITES_2 0x00011800
+#define US3_MC_WRITES_3 0x00012000
+#define US3_MC_STALLS_1 0x00012800
+#define US3_MC_STALLS_3 0x00013000
+#define US3_RE_RAW_MISS 0x00013800
+#define US3_FM_PIPE_COMPLETION 0x00014000
+
+struct vcounter_struct {
+ unsigned long long vcnt0;
+ unsigned long long vcnt1;
+};
+
+#endif /* !(__KERNEL__) */
+
+#endif /* !(PERF_COUNTER_API) */
--- /dev/null
+#ifndef ___ASM_SPARC_PGALLOC_H
+#define ___ASM_SPARC_PGALLOC_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/pgalloc_64.h>
+#else
+#include <asm/pgalloc_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _SPARC_PGALLOC_H
+#define _SPARC_PGALLOC_H
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+
+#include <asm/page.h>
+#include <asm/btfixup.h>
+
+struct page;
+
+extern struct pgtable_cache_struct {
+ unsigned long *pgd_cache;
+ unsigned long *pte_cache;
+ unsigned long pgtable_cache_sz;
+ unsigned long pgd_cache_sz;
+} pgt_quicklists;
+#define pgd_quicklist (pgt_quicklists.pgd_cache)
+#define pmd_quicklist ((unsigned long *)0)
+#define pte_quicklist (pgt_quicklists.pte_cache)
+#define pgtable_cache_size (pgt_quicklists.pgtable_cache_sz)
+#define pgd_cache_size (pgt_quicklists.pgd_cache_sz)
+
+extern void check_pgt_cache(void);
+BTFIXUPDEF_CALL(void, do_check_pgt_cache, int, int)
+#define do_check_pgt_cache(low,high) BTFIXUP_CALL(do_check_pgt_cache)(low,high)
+
+BTFIXUPDEF_CALL(pgd_t *, get_pgd_fast, void)
+#define get_pgd_fast() BTFIXUP_CALL(get_pgd_fast)()
+
+BTFIXUPDEF_CALL(void, free_pgd_fast, pgd_t *)
+#define free_pgd_fast(pgd) BTFIXUP_CALL(free_pgd_fast)(pgd)
+
+#define pgd_free(mm, pgd) free_pgd_fast(pgd)
+#define pgd_alloc(mm) get_pgd_fast()
+
+BTFIXUPDEF_CALL(void, pgd_set, pgd_t *, pmd_t *)
+#define pgd_set(pgdp,pmdp) BTFIXUP_CALL(pgd_set)(pgdp,pmdp)
+#define pgd_populate(MM, PGD, PMD) pgd_set(PGD, PMD)
+
+BTFIXUPDEF_CALL(pmd_t *, pmd_alloc_one, struct mm_struct *, unsigned long)
+#define pmd_alloc_one(mm, address) BTFIXUP_CALL(pmd_alloc_one)(mm, address)
+
+BTFIXUPDEF_CALL(void, free_pmd_fast, pmd_t *)
+#define free_pmd_fast(pmd) BTFIXUP_CALL(free_pmd_fast)(pmd)
+
+#define pmd_free(mm, pmd) free_pmd_fast(pmd)
+#define __pmd_free_tlb(tlb, pmd) pmd_free((tlb)->mm, pmd)
+
+BTFIXUPDEF_CALL(void, pmd_populate, pmd_t *, struct page *)
+#define pmd_populate(MM, PMD, PTE) BTFIXUP_CALL(pmd_populate)(PMD, PTE)
+#define pmd_pgtable(pmd) pmd_page(pmd)
+BTFIXUPDEF_CALL(void, pmd_set, pmd_t *, pte_t *)
+#define pmd_populate_kernel(MM, PMD, PTE) BTFIXUP_CALL(pmd_set)(PMD, PTE)
+
+BTFIXUPDEF_CALL(pgtable_t , pte_alloc_one, struct mm_struct *, unsigned long)
+#define pte_alloc_one(mm, address) BTFIXUP_CALL(pte_alloc_one)(mm, address)
+BTFIXUPDEF_CALL(pte_t *, pte_alloc_one_kernel, struct mm_struct *, unsigned long)
+#define pte_alloc_one_kernel(mm, addr) BTFIXUP_CALL(pte_alloc_one_kernel)(mm, addr)
+
+BTFIXUPDEF_CALL(void, free_pte_fast, pte_t *)
+#define pte_free_kernel(mm, pte) BTFIXUP_CALL(free_pte_fast)(pte)
+
+BTFIXUPDEF_CALL(void, pte_free, pgtable_t )
+#define pte_free(mm, pte) BTFIXUP_CALL(pte_free)(pte)
+#define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, pte)
+
+#endif /* _SPARC_PGALLOC_H */
--- /dev/null
+#ifndef _SPARC64_PGALLOC_H
+#define _SPARC64_PGALLOC_H
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/quicklist.h>
+
+#include <asm/spitfire.h>
+#include <asm/cpudata.h>
+#include <asm/cacheflush.h>
+#include <asm/page.h>
+
+/* Page table allocation/freeing. */
+
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+ return quicklist_alloc(0, GFP_KERNEL, NULL);
+}
+
+static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+ quicklist_free(0, NULL, pgd);
+}
+
+#define pud_populate(MM, PUD, PMD) pud_set(PUD, PMD)
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+ return quicklist_alloc(0, GFP_KERNEL, NULL);
+}
+
+static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+ quicklist_free(0, NULL, pmd);
+}
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+ unsigned long address)
+{
+ return quicklist_alloc(0, GFP_KERNEL, NULL);
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+ unsigned long address)
+{
+ struct page *page;
+ void *pg;
+
+ pg = quicklist_alloc(0, GFP_KERNEL, NULL);
+ if (!pg)
+ return NULL;
+ page = virt_to_page(pg);
+ pgtable_page_ctor(page);
+ return page;
+}
+
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+ quicklist_free(0, NULL, pte);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
+{
+ pgtable_page_dtor(ptepage);
+ quicklist_free_page(0, NULL, ptepage);
+}
+
+
+#define pmd_populate_kernel(MM, PMD, PTE) pmd_set(PMD, PTE)
+#define pmd_populate(MM,PMD,PTE_PAGE) \
+ pmd_populate_kernel(MM,PMD,page_address(PTE_PAGE))
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+static inline void check_pgt_cache(void)
+{
+ quicklist_trim(0, NULL, 25, 16);
+}
+
+#endif /* _SPARC64_PGALLOC_H */
--- /dev/null
+#ifndef ___ASM_SPARC_PGTABLE_H
+#define ___ASM_SPARC_PGTABLE_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/pgtable_64.h>
+#else
+#include <asm/pgtable_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _SPARC_PGTABLE_H
+#define _SPARC_PGTABLE_H
+
+/* asm/pgtable.h: Defines and functions used to work
+ * with Sparc page tables.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+
+#ifndef __ASSEMBLY__
+#include <asm-generic/4level-fixup.h>
+
+#include <linux/spinlock.h>
+#include <linux/swap.h>
+#include <asm/types.h>
+#ifdef CONFIG_SUN4
+#include <asm/pgtsun4.h>
+#else
+#include <asm/pgtsun4c.h>
+#endif
+#include <asm/pgtsrmmu.h>
+#include <asm/vac-ops.h>
+#include <asm/oplib.h>
+#include <asm/btfixup.h>
+#include <asm/system.h>
+
+
+struct vm_area_struct;
+struct page;
+
+extern void load_mmu(void);
+extern unsigned long calc_highpages(void);
+
+BTFIXUPDEF_SIMM13(pgdir_shift)
+BTFIXUPDEF_SETHI(pgdir_size)
+BTFIXUPDEF_SETHI(pgdir_mask)
+
+BTFIXUPDEF_SIMM13(ptrs_per_pmd)
+BTFIXUPDEF_SIMM13(ptrs_per_pgd)
+BTFIXUPDEF_SIMM13(user_ptrs_per_pgd)
+
+#define pte_ERROR(e) __builtin_trap()
+#define pmd_ERROR(e) __builtin_trap()
+#define pgd_ERROR(e) __builtin_trap()
+
+BTFIXUPDEF_INT(page_none)
+BTFIXUPDEF_INT(page_copy)
+BTFIXUPDEF_INT(page_readonly)
+BTFIXUPDEF_INT(page_kernel)
+
+#define PMD_SHIFT SUN4C_PMD_SHIFT
+#define PMD_SIZE (1UL << PMD_SHIFT)
+#define PMD_MASK (~(PMD_SIZE-1))
+#define PMD_ALIGN(__addr) (((__addr) + ~PMD_MASK) & PMD_MASK)
+#define PGDIR_SHIFT BTFIXUP_SIMM13(pgdir_shift)
+#define PGDIR_SIZE BTFIXUP_SETHI(pgdir_size)
+#define PGDIR_MASK BTFIXUP_SETHI(pgdir_mask)
+#define PTRS_PER_PTE 1024
+#define PTRS_PER_PMD BTFIXUP_SIMM13(ptrs_per_pmd)
+#define PTRS_PER_PGD BTFIXUP_SIMM13(ptrs_per_pgd)
+#define USER_PTRS_PER_PGD BTFIXUP_SIMM13(user_ptrs_per_pgd)
+#define FIRST_USER_ADDRESS 0
+#define PTE_SIZE (PTRS_PER_PTE*4)
+
+#define PAGE_NONE __pgprot(BTFIXUP_INT(page_none))
+extern pgprot_t PAGE_SHARED;
+#define PAGE_COPY __pgprot(BTFIXUP_INT(page_copy))
+#define PAGE_READONLY __pgprot(BTFIXUP_INT(page_readonly))
+
+extern unsigned long page_kernel;
+
+#ifdef MODULE
+#define PAGE_KERNEL page_kernel
+#else
+#define PAGE_KERNEL __pgprot(BTFIXUP_INT(page_kernel))
+#endif
+
+/* Top-level page directory */
+extern pgd_t swapper_pg_dir[1024];
+
+extern void paging_init(void);
+
+/* Page table for 0-4MB for everybody, on the Sparc this
+ * holds the same as on the i386.
+ */
+extern pte_t pg0[1024];
+extern pte_t pg1[1024];
+extern pte_t pg2[1024];
+extern pte_t pg3[1024];
+
+extern unsigned long ptr_in_current_pgd;
+
+/* Here is a trick, since mmap.c need the initializer elements for
+ * protection_map[] to be constant at compile time, I set the following
+ * to all zeros. I set it to the real values after I link in the
+ * appropriate MMU page table routines at boot time.
+ */
+#define __P000 __pgprot(0)
+#define __P001 __pgprot(0)
+#define __P010 __pgprot(0)
+#define __P011 __pgprot(0)
+#define __P100 __pgprot(0)
+#define __P101 __pgprot(0)
+#define __P110 __pgprot(0)
+#define __P111 __pgprot(0)
+
+#define __S000 __pgprot(0)
+#define __S001 __pgprot(0)
+#define __S010 __pgprot(0)
+#define __S011 __pgprot(0)
+#define __S100 __pgprot(0)
+#define __S101 __pgprot(0)
+#define __S110 __pgprot(0)
+#define __S111 __pgprot(0)
+
+extern int num_contexts;
+
+/* First physical page can be anywhere, the following is needed so that
+ * va-->pa and vice versa conversions work properly without performance
+ * hit for all __pa()/__va() operations.
+ */
+extern unsigned long phys_base;
+extern unsigned long pfn_base;
+
+/*
+ * BAD_PAGETABLE is used when we need a bogus page-table, while
+ * BAD_PAGE is used for a bogus page.
+ *
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern pte_t * __bad_pagetable(void);
+extern pte_t __bad_page(void);
+extern unsigned long empty_zero_page;
+
+#define BAD_PAGETABLE __bad_pagetable()
+#define BAD_PAGE __bad_page()
+#define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))
+
+/*
+ */
+BTFIXUPDEF_CALL_CONST(struct page *, pmd_page, pmd_t)
+BTFIXUPDEF_CALL_CONST(unsigned long, pgd_page_vaddr, pgd_t)
+
+#define pmd_page(pmd) BTFIXUP_CALL(pmd_page)(pmd)
+#define pgd_page_vaddr(pgd) BTFIXUP_CALL(pgd_page_vaddr)(pgd)
+
+BTFIXUPDEF_SETHI(none_mask)
+BTFIXUPDEF_CALL_CONST(int, pte_present, pte_t)
+BTFIXUPDEF_CALL(void, pte_clear, pte_t *)
+
+static inline int pte_none(pte_t pte)
+{
+ return !(pte_val(pte) & ~BTFIXUP_SETHI(none_mask));
+}
+
+#define pte_present(pte) BTFIXUP_CALL(pte_present)(pte)
+#define pte_clear(mm,addr,pte) BTFIXUP_CALL(pte_clear)(pte)
+
+BTFIXUPDEF_CALL_CONST(int, pmd_bad, pmd_t)
+BTFIXUPDEF_CALL_CONST(int, pmd_present, pmd_t)
+BTFIXUPDEF_CALL(void, pmd_clear, pmd_t *)
+
+static inline int pmd_none(pmd_t pmd)
+{
+ return !(pmd_val(pmd) & ~BTFIXUP_SETHI(none_mask));
+}
+
+#define pmd_bad(pmd) BTFIXUP_CALL(pmd_bad)(pmd)
+#define pmd_present(pmd) BTFIXUP_CALL(pmd_present)(pmd)
+#define pmd_clear(pmd) BTFIXUP_CALL(pmd_clear)(pmd)
+
+BTFIXUPDEF_CALL_CONST(int, pgd_none, pgd_t)
+BTFIXUPDEF_CALL_CONST(int, pgd_bad, pgd_t)
+BTFIXUPDEF_CALL_CONST(int, pgd_present, pgd_t)
+BTFIXUPDEF_CALL(void, pgd_clear, pgd_t *)
+
+#define pgd_none(pgd) BTFIXUP_CALL(pgd_none)(pgd)
+#define pgd_bad(pgd) BTFIXUP_CALL(pgd_bad)(pgd)
+#define pgd_present(pgd) BTFIXUP_CALL(pgd_present)(pgd)
+#define pgd_clear(pgd) BTFIXUP_CALL(pgd_clear)(pgd)
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+BTFIXUPDEF_HALF(pte_writei)
+BTFIXUPDEF_HALF(pte_dirtyi)
+BTFIXUPDEF_HALF(pte_youngi)
+
+static int pte_write(pte_t pte) __attribute_const__;
+static inline int pte_write(pte_t pte)
+{
+ return pte_val(pte) & BTFIXUP_HALF(pte_writei);
+}
+
+static int pte_dirty(pte_t pte) __attribute_const__;
+static inline int pte_dirty(pte_t pte)
+{
+ return pte_val(pte) & BTFIXUP_HALF(pte_dirtyi);
+}
+
+static int pte_young(pte_t pte) __attribute_const__;
+static inline int pte_young(pte_t pte)
+{
+ return pte_val(pte) & BTFIXUP_HALF(pte_youngi);
+}
+
+/*
+ * The following only work if pte_present() is not true.
+ */
+BTFIXUPDEF_HALF(pte_filei)
+
+static int pte_file(pte_t pte) __attribute_const__;
+static inline int pte_file(pte_t pte)
+{
+ return pte_val(pte) & BTFIXUP_HALF(pte_filei);
+}
+
+static inline int pte_special(pte_t pte)
+{
+ return 0;
+}
+
+/*
+ */
+BTFIXUPDEF_HALF(pte_wrprotecti)
+BTFIXUPDEF_HALF(pte_mkcleani)
+BTFIXUPDEF_HALF(pte_mkoldi)
+
+static pte_t pte_wrprotect(pte_t pte) __attribute_const__;
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_wrprotecti));
+}
+
+static pte_t pte_mkclean(pte_t pte) __attribute_const__;
+static inline pte_t pte_mkclean(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkcleani));
+}
+
+static pte_t pte_mkold(pte_t pte) __attribute_const__;
+static inline pte_t pte_mkold(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkoldi));
+}
+
+BTFIXUPDEF_CALL_CONST(pte_t, pte_mkwrite, pte_t)
+BTFIXUPDEF_CALL_CONST(pte_t, pte_mkdirty, pte_t)
+BTFIXUPDEF_CALL_CONST(pte_t, pte_mkyoung, pte_t)
+
+#define pte_mkwrite(pte) BTFIXUP_CALL(pte_mkwrite)(pte)
+#define pte_mkdirty(pte) BTFIXUP_CALL(pte_mkdirty)(pte)
+#define pte_mkyoung(pte) BTFIXUP_CALL(pte_mkyoung)(pte)
+
+#define pte_mkspecial(pte) (pte)
+
+#define pfn_pte(pfn, prot) mk_pte(pfn_to_page(pfn), prot)
+
+BTFIXUPDEF_CALL(unsigned long, pte_pfn, pte_t)
+#define pte_pfn(pte) BTFIXUP_CALL(pte_pfn)(pte)
+#define pte_page(pte) pfn_to_page(pte_pfn(pte))
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+BTFIXUPDEF_CALL_CONST(pte_t, mk_pte, struct page *, pgprot_t)
+
+BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_phys, unsigned long, pgprot_t)
+BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_io, unsigned long, pgprot_t, int)
+BTFIXUPDEF_CALL_CONST(pgprot_t, pgprot_noncached, pgprot_t)
+
+#define mk_pte(page,pgprot) BTFIXUP_CALL(mk_pte)(page,pgprot)
+#define mk_pte_phys(page,pgprot) BTFIXUP_CALL(mk_pte_phys)(page,pgprot)
+#define mk_pte_io(page,pgprot,space) BTFIXUP_CALL(mk_pte_io)(page,pgprot,space)
+
+#define pgprot_noncached(pgprot) BTFIXUP_CALL(pgprot_noncached)(pgprot)
+
+BTFIXUPDEF_INT(pte_modify_mask)
+
+static pte_t pte_modify(pte_t pte, pgprot_t newprot) __attribute_const__;
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+ return __pte((pte_val(pte) & BTFIXUP_INT(pte_modify_mask)) |
+ pgprot_val(newprot));
+}
+
+#define pgd_index(address) ((address) >> PGDIR_SHIFT)
+
+/* to find an entry in a page-table-directory */
+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/* Find an entry in the second-level page table.. */
+BTFIXUPDEF_CALL(pmd_t *, pmd_offset, pgd_t *, unsigned long)
+#define pmd_offset(dir,addr) BTFIXUP_CALL(pmd_offset)(dir,addr)
+
+/* Find an entry in the third-level page table.. */
+BTFIXUPDEF_CALL(pte_t *, pte_offset_kernel, pmd_t *, unsigned long)
+#define pte_offset_kernel(dir,addr) BTFIXUP_CALL(pte_offset_kernel)(dir,addr)
+
+/*
+ * This shortcut works on sun4m (and sun4d) because the nocache area is static,
+ * and sun4c is guaranteed to have no highmem anyway.
+ */
+#define pte_offset_map(d, a) pte_offset_kernel(d,a)
+#define pte_offset_map_nested(d, a) pte_offset_kernel(d,a)
+
+#define pte_unmap(pte) do{}while(0)
+#define pte_unmap_nested(pte) do{}while(0)
+
+/* Certain architectures need to do special things when pte's
+ * within a page table are directly modified. Thus, the following
+ * hook is made available.
+ */
+
+BTFIXUPDEF_CALL(void, set_pte, pte_t *, pte_t)
+
+#define set_pte(ptep,pteval) BTFIXUP_CALL(set_pte)(ptep,pteval)
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+
+struct seq_file;
+BTFIXUPDEF_CALL(void, mmu_info, struct seq_file *)
+
+#define mmu_info(p) BTFIXUP_CALL(mmu_info)(p)
+
+/* Fault handler stuff... */
+#define FAULT_CODE_PROT 0x1
+#define FAULT_CODE_WRITE 0x2
+#define FAULT_CODE_USER 0x4
+
+BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t)
+
+#define update_mmu_cache(vma,addr,pte) BTFIXUP_CALL(update_mmu_cache)(vma,addr,pte)
+
+BTFIXUPDEF_CALL(void, sparc_mapiorange, unsigned int, unsigned long,
+ unsigned long, unsigned int)
+BTFIXUPDEF_CALL(void, sparc_unmapiorange, unsigned long, unsigned int)
+#define sparc_mapiorange(bus,pa,va,len) BTFIXUP_CALL(sparc_mapiorange)(bus,pa,va,len)
+#define sparc_unmapiorange(va,len) BTFIXUP_CALL(sparc_unmapiorange)(va,len)
+
+extern int invalid_segment;
+
+/* Encode and de-code a swap entry */
+BTFIXUPDEF_CALL(unsigned long, __swp_type, swp_entry_t)
+BTFIXUPDEF_CALL(unsigned long, __swp_offset, swp_entry_t)
+BTFIXUPDEF_CALL(swp_entry_t, __swp_entry, unsigned long, unsigned long)
+
+#define __swp_type(__x) BTFIXUP_CALL(__swp_type)(__x)
+#define __swp_offset(__x) BTFIXUP_CALL(__swp_offset)(__x)
+#define __swp_entry(__type,__off) BTFIXUP_CALL(__swp_entry)(__type,__off)
+
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
+
+/* file-offset-in-pte helpers */
+BTFIXUPDEF_CALL(unsigned long, pte_to_pgoff, pte_t pte);
+BTFIXUPDEF_CALL(pte_t, pgoff_to_pte, unsigned long pgoff);
+
+#define pte_to_pgoff(pte) BTFIXUP_CALL(pte_to_pgoff)(pte)
+#define pgoff_to_pte(off) BTFIXUP_CALL(pgoff_to_pte)(off)
+
+/*
+ * This is made a constant because mm/fremap.c required a constant.
+ * Note that layout of these bits is different between sun4c.c and srmmu.c.
+ */
+#define PTE_FILE_MAX_BITS 24
+
+/*
+ */
+struct ctx_list {
+ struct ctx_list *next;
+ struct ctx_list *prev;
+ unsigned int ctx_number;
+ struct mm_struct *ctx_mm;
+};
+
+extern struct ctx_list *ctx_list_pool; /* Dynamically allocated */
+extern struct ctx_list ctx_free; /* Head of free list */
+extern struct ctx_list ctx_used; /* Head of used contexts list */
+
+#define NO_CONTEXT -1
+
+static inline void remove_from_ctx_list(struct ctx_list *entry)
+{
+ entry->next->prev = entry->prev;
+ entry->prev->next = entry->next;
+}
+
+static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
+{
+ entry->next = head;
+ (entry->prev = head->prev)->next = entry;
+ head->prev = entry;
+}
+#define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
+#define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
+
+static inline unsigned long
+__get_phys (unsigned long addr)
+{
+ switch (sparc_cpu_model){
+ case sun4:
+ case sun4c:
+ return sun4c_get_pte (addr) << PAGE_SHIFT;
+ case sun4m:
+ case sun4d:
+ return ((srmmu_get_pte (addr) & 0xffffff00) << 4);
+ default:
+ return 0;
+ }
+}
+
+static inline int
+__get_iospace (unsigned long addr)
+{
+ switch (sparc_cpu_model){
+ case sun4:
+ case sun4c:
+ return -1; /* Don't check iospace on sun4c */
+ case sun4m:
+ case sun4d:
+ return (srmmu_get_pte (addr) >> 28);
+ default:
+ return -1;
+ }
+}
+
+extern unsigned long *sparc_valid_addr_bitmap;
+
+/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
+#define kern_addr_valid(addr) \
+ (test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap))
+
+extern int io_remap_pfn_range(struct vm_area_struct *vma,
+ unsigned long from, unsigned long pfn,
+ unsigned long size, pgprot_t prot);
+
+/*
+ * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
+ * its high 4 bits. These macros/functions put it there or get it from there.
+ */
+#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
+#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
+#define GET_PFN(pfn) (pfn & 0x0fffffffUL)
+
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
+({ \
+ int __changed = !pte_same(*(__ptep), __entry); \
+ if (__changed) { \
+ set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
+ flush_tlb_page(__vma, __address); \
+ } \
+ (sparc_cpu_model == sun4c) || __changed; \
+})
+
+#include <asm-generic/pgtable.h>
+
+#endif /* !(__ASSEMBLY__) */
+
+#define VMALLOC_START 0xfe600000
+/* XXX Alter this when I get around to fixing sun4c - Anton */
+#define VMALLOC_END 0xffc00000
+
+
+/* We provide our own get_unmapped_area to cope with VA holes for userland */
+#define HAVE_ARCH_UNMAPPED_AREA
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init() do { } while (0)
+
+#endif /* !(_SPARC_PGTABLE_H) */
--- /dev/null
+/*
+ * pgtable.h: SpitFire page table operations.
+ *
+ * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+
+#ifndef _SPARC64_PGTABLE_H
+#define _SPARC64_PGTABLE_H
+
+/* This file contains the functions and defines necessary to modify and use
+ * the SpitFire page tables.
+ */
+
+#include <asm-generic/pgtable-nopud.h>
+
+#include <linux/compiler.h>
+#include <linux/const.h>
+#include <asm/types.h>
+#include <asm/spitfire.h>
+#include <asm/asi.h>
+#include <asm/system.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+
+/* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
+ * The page copy blockops can use 0x6000000 to 0x8000000.
+ * The TSB is mapped in the 0x8000000 to 0xa000000 range.
+ * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
+ * The vmalloc area spans 0x100000000 to 0x200000000.
+ * Since modules need to be in the lowest 32-bits of the address space,
+ * we place them right before the OBP area from 0x10000000 to 0xf0000000.
+ * There is a single static kernel PMD which maps from 0x0 to address
+ * 0x400000000.
+ */
+#define TLBTEMP_BASE _AC(0x0000000006000000,UL)
+#define TSBMAP_BASE _AC(0x0000000008000000,UL)
+#define MODULES_VADDR _AC(0x0000000010000000,UL)
+#define MODULES_LEN _AC(0x00000000e0000000,UL)
+#define MODULES_END _AC(0x00000000f0000000,UL)
+#define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
+#define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
+#define VMALLOC_START _AC(0x0000000100000000,UL)
+#define VMALLOC_END _AC(0x0000000200000000,UL)
+#define VMEMMAP_BASE _AC(0x0000000200000000,UL)
+
+#define vmemmap ((struct page *)VMEMMAP_BASE)
+
+/* XXX All of this needs to be rethought so we can take advantage
+ * XXX cheetah's full 64-bit virtual address space, ie. no more hole
+ * XXX in the middle like on spitfire. -DaveM
+ */
+/*
+ * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
+ * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
+ * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
+ * table is a single page long). The next higher PMD_BITS determine pmd#
+ * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
+ * since the pmd entries are 4 bytes, and each pmd page is a single page
+ * long). Finally, the higher few bits determine pgde#.
+ */
+
+/* PMD_SHIFT determines the size of the area a second-level page
+ * table can map
+ */
+#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
+#define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
+#define PMD_MASK (~(PMD_SIZE-1))
+#define PMD_BITS (PAGE_SHIFT - 2)
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
+#define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
+#define PGDIR_MASK (~(PGDIR_SIZE-1))
+#define PGDIR_BITS (PAGE_SHIFT - 2)
+
+#ifndef __ASSEMBLY__
+
+#include <linux/sched.h>
+
+/* Entries per page directory level. */
+#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
+#define PTRS_PER_PMD (1UL << PMD_BITS)
+#define PTRS_PER_PGD (1UL << PGDIR_BITS)
+
+/* Kernel has a separate 44bit address space. */
+#define FIRST_USER_ADDRESS 0
+
+#define pte_ERROR(e) __builtin_trap()
+#define pmd_ERROR(e) __builtin_trap()
+#define pgd_ERROR(e) __builtin_trap()
+
+#endif /* !(__ASSEMBLY__) */
+
+/* PTE bits which are the same in SUN4U and SUN4V format. */
+#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
+#define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
+
+/* SUN4U pte bits... */
+#define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
+#define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
+#define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
+#define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
+#define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
+#define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
+#define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
+#define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
+#define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
+#define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
+#define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */
+#define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
+#define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
+#define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
+#define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
+#define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
+#define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
+#define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */
+#define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
+#define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
+#define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
+#define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
+#define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
+#define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
+#define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
+#define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
+#define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
+#define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
+
+/* SUN4V pte bits... */
+#define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
+#define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
+#define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
+#define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
+#define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
+#define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
+#define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
+#define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
+#define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
+#define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
+#define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
+#define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
+#define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
+#define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
+#define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
+#define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */
+#define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
+#define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
+#define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
+#define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
+#define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
+#define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
+#define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
+#define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
+#define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
+#define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
+#define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */
+
+#if PAGE_SHIFT == 13
+#define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
+#define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
+#elif PAGE_SHIFT == 16
+#define _PAGE_SZBITS_4U _PAGE_SZ64K_4U
+#define _PAGE_SZBITS_4V _PAGE_SZ64K_4V
+#else
+#error Wrong PAGE_SHIFT specified
+#endif
+
+#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
+#define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
+#define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U
+#define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U
+#define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V
+#endif
+
+/* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
+#define __P000 __pgprot(0)
+#define __P001 __pgprot(0)
+#define __P010 __pgprot(0)
+#define __P011 __pgprot(0)
+#define __P100 __pgprot(0)
+#define __P101 __pgprot(0)
+#define __P110 __pgprot(0)
+#define __P111 __pgprot(0)
+
+#define __S000 __pgprot(0)
+#define __S001 __pgprot(0)
+#define __S010 __pgprot(0)
+#define __S011 __pgprot(0)
+#define __S100 __pgprot(0)
+#define __S101 __pgprot(0)
+#define __S110 __pgprot(0)
+#define __S111 __pgprot(0)
+
+#ifndef __ASSEMBLY__
+
+extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
+
+extern unsigned long pte_sz_bits(unsigned long size);
+
+extern pgprot_t PAGE_KERNEL;
+extern pgprot_t PAGE_KERNEL_LOCKED;
+extern pgprot_t PAGE_COPY;
+extern pgprot_t PAGE_SHARED;
+
+/* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
+extern unsigned long _PAGE_IE;
+extern unsigned long _PAGE_E;
+extern unsigned long _PAGE_CACHE;
+
+extern unsigned long pg_iobits;
+extern unsigned long _PAGE_ALL_SZ_BITS;
+extern unsigned long _PAGE_SZBITS;
+
+extern struct page *mem_map_zero;
+#define ZERO_PAGE(vaddr) (mem_map_zero)
+
+/* PFNs are real physical page numbers. However, mem_map only begins to record
+ * per-page information starting at pfn_base. This is to handle systems where
+ * the first physical page in the machine is at some huge physical address,
+ * such as 4GB. This is common on a partitioned E10000, for example.
+ */
+static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
+{
+ unsigned long paddr = pfn << PAGE_SHIFT;
+ unsigned long sz_bits;
+
+ sz_bits = 0UL;
+ if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) {
+ __asm__ __volatile__(
+ "\n661: sethi %%uhi(%1), %0\n"
+ " sllx %0, 32, %0\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " mov %2, %0\n"
+ " nop\n"
+ " .previous\n"
+ : "=r" (sz_bits)
+ : "i" (_PAGE_SZBITS_4U), "i" (_PAGE_SZBITS_4V));
+ }
+ return __pte(paddr | sz_bits | pgprot_val(prot));
+}
+#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
+
+/* This one can be done with two shifts. */
+static inline unsigned long pte_pfn(pte_t pte)
+{
+ unsigned long ret;
+
+ __asm__ __volatile__(
+ "\n661: sllx %1, %2, %0\n"
+ " srlx %0, %3, %0\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " sllx %1, %4, %0\n"
+ " srlx %0, %5, %0\n"
+ " .previous\n"
+ : "=r" (ret)
+ : "r" (pte_val(pte)),
+ "i" (21), "i" (21 + PAGE_SHIFT),
+ "i" (8), "i" (8 + PAGE_SHIFT));
+
+ return ret;
+}
+#define pte_page(x) pfn_to_page(pte_pfn(x))
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
+{
+ unsigned long mask, tmp;
+
+ /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347)
+ * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8)
+ *
+ * Even if we use negation tricks the result is still a 6
+ * instruction sequence, so don't try to play fancy and just
+ * do the most straightforward implementation.
+ *
+ * Note: We encode this into 3 sun4v 2-insn patch sequences.
+ */
+
+ __asm__ __volatile__(
+ "\n661: sethi %%uhi(%2), %1\n"
+ " sethi %%hi(%2), %0\n"
+ "\n662: or %1, %%ulo(%2), %1\n"
+ " or %0, %%lo(%2), %0\n"
+ "\n663: sllx %1, 32, %1\n"
+ " or %0, %1, %0\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " sethi %%uhi(%3), %1\n"
+ " sethi %%hi(%3), %0\n"
+ " .word 662b\n"
+ " or %1, %%ulo(%3), %1\n"
+ " or %0, %%lo(%3), %0\n"
+ " .word 663b\n"
+ " sllx %1, 32, %1\n"
+ " or %0, %1, %0\n"
+ " .previous\n"
+ : "=r" (mask), "=r" (tmp)
+ : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
+ _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U |
+ _PAGE_SZBITS_4U),
+ "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
+ _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V |
+ _PAGE_SZBITS_4V));
+
+ return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
+}
+
+static inline pte_t pgoff_to_pte(unsigned long off)
+{
+ off <<= PAGE_SHIFT;
+
+ __asm__ __volatile__(
+ "\n661: or %0, %2, %0\n"
+ " .section .sun4v_1insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " or %0, %3, %0\n"
+ " .previous\n"
+ : "=r" (off)
+ : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
+
+ return __pte(off);
+}
+
+static inline pgprot_t pgprot_noncached(pgprot_t prot)
+{
+ unsigned long val = pgprot_val(prot);
+
+ __asm__ __volatile__(
+ "\n661: andn %0, %2, %0\n"
+ " or %0, %3, %0\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " andn %0, %4, %0\n"
+ " or %0, %5, %0\n"
+ " .previous\n"
+ : "=r" (val)
+ : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
+ "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
+
+ return __pgprot(val);
+}
+/* Various pieces of code check for platform support by ifdef testing
+ * on "pgprot_noncached". That's broken and should be fixed, but for
+ * now...
+ */
+#define pgprot_noncached pgprot_noncached
+
+#ifdef CONFIG_HUGETLB_PAGE
+static inline pte_t pte_mkhuge(pte_t pte)
+{
+ unsigned long mask;
+
+ __asm__ __volatile__(
+ "\n661: sethi %%uhi(%1), %0\n"
+ " sllx %0, 32, %0\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " mov %2, %0\n"
+ " nop\n"
+ " .previous\n"
+ : "=r" (mask)
+ : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
+
+ return __pte(pte_val(pte) | mask);
+}
+#endif
+
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+ unsigned long val = pte_val(pte), tmp;
+
+ __asm__ __volatile__(
+ "\n661: or %0, %3, %0\n"
+ " nop\n"
+ "\n662: nop\n"
+ " nop\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " sethi %%uhi(%4), %1\n"
+ " sllx %1, 32, %1\n"
+ " .word 662b\n"
+ " or %1, %%lo(%4), %1\n"
+ " or %0, %1, %0\n"
+ " .previous\n"
+ : "=r" (val), "=r" (tmp)
+ : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
+ "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
+
+ return __pte(val);
+}
+
+static inline pte_t pte_mkclean(pte_t pte)
+{
+ unsigned long val = pte_val(pte), tmp;
+
+ __asm__ __volatile__(
+ "\n661: andn %0, %3, %0\n"
+ " nop\n"
+ "\n662: nop\n"
+ " nop\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " sethi %%uhi(%4), %1\n"
+ " sllx %1, 32, %1\n"
+ " .word 662b\n"
+ " or %1, %%lo(%4), %1\n"
+ " andn %0, %1, %0\n"
+ " .previous\n"
+ : "=r" (val), "=r" (tmp)
+ : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
+ "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
+
+ return __pte(val);
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+ unsigned long val = pte_val(pte), mask;
+
+ __asm__ __volatile__(
+ "\n661: mov %1, %0\n"
+ " nop\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " sethi %%uhi(%2), %0\n"
+ " sllx %0, 32, %0\n"
+ " .previous\n"
+ : "=r" (mask)
+ : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
+
+ return __pte(val | mask);
+}
+
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+ unsigned long val = pte_val(pte), tmp;
+
+ __asm__ __volatile__(
+ "\n661: andn %0, %3, %0\n"
+ " nop\n"
+ "\n662: nop\n"
+ " nop\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " sethi %%uhi(%4), %1\n"
+ " sllx %1, 32, %1\n"
+ " .word 662b\n"
+ " or %1, %%lo(%4), %1\n"
+ " andn %0, %1, %0\n"
+ " .previous\n"
+ : "=r" (val), "=r" (tmp)
+ : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
+ "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
+
+ return __pte(val);
+}
+
+static inline pte_t pte_mkold(pte_t pte)
+{
+ unsigned long mask;
+
+ __asm__ __volatile__(
+ "\n661: mov %1, %0\n"
+ " nop\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " sethi %%uhi(%2), %0\n"
+ " sllx %0, 32, %0\n"
+ " .previous\n"
+ : "=r" (mask)
+ : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
+
+ mask |= _PAGE_R;
+
+ return __pte(pte_val(pte) & ~mask);
+}
+
+static inline pte_t pte_mkyoung(pte_t pte)
+{
+ unsigned long mask;
+
+ __asm__ __volatile__(
+ "\n661: mov %1, %0\n"
+ " nop\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " sethi %%uhi(%2), %0\n"
+ " sllx %0, 32, %0\n"
+ " .previous\n"
+ : "=r" (mask)
+ : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
+
+ mask |= _PAGE_R;
+
+ return __pte(pte_val(pte) | mask);
+}
+
+static inline pte_t pte_mkspecial(pte_t pte)
+{
+ return pte;
+}
+
+static inline unsigned long pte_young(pte_t pte)
+{
+ unsigned long mask;
+
+ __asm__ __volatile__(
+ "\n661: mov %1, %0\n"
+ " nop\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " sethi %%uhi(%2), %0\n"
+ " sllx %0, 32, %0\n"
+ " .previous\n"
+ : "=r" (mask)
+ : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
+
+ return (pte_val(pte) & mask);
+}
+
+static inline unsigned long pte_dirty(pte_t pte)
+{
+ unsigned long mask;
+
+ __asm__ __volatile__(
+ "\n661: mov %1, %0\n"
+ " nop\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " sethi %%uhi(%2), %0\n"
+ " sllx %0, 32, %0\n"
+ " .previous\n"
+ : "=r" (mask)
+ : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
+
+ return (pte_val(pte) & mask);
+}
+
+static inline unsigned long pte_write(pte_t pte)
+{
+ unsigned long mask;
+
+ __asm__ __volatile__(
+ "\n661: mov %1, %0\n"
+ " nop\n"
+ " .section .sun4v_2insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " sethi %%uhi(%2), %0\n"
+ " sllx %0, 32, %0\n"
+ " .previous\n"
+ : "=r" (mask)
+ : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
+
+ return (pte_val(pte) & mask);
+}
+
+static inline unsigned long pte_exec(pte_t pte)
+{
+ unsigned long mask;
+
+ __asm__ __volatile__(
+ "\n661: sethi %%hi(%1), %0\n"
+ " .section .sun4v_1insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " mov %2, %0\n"
+ " .previous\n"
+ : "=r" (mask)
+ : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
+
+ return (pte_val(pte) & mask);
+}
+
+static inline unsigned long pte_file(pte_t pte)
+{
+ unsigned long val = pte_val(pte);
+
+ __asm__ __volatile__(
+ "\n661: and %0, %2, %0\n"
+ " .section .sun4v_1insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " and %0, %3, %0\n"
+ " .previous\n"
+ : "=r" (val)
+ : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
+
+ return val;
+}
+
+static inline unsigned long pte_present(pte_t pte)
+{
+ unsigned long val = pte_val(pte);
+
+ __asm__ __volatile__(
+ "\n661: and %0, %2, %0\n"
+ " .section .sun4v_1insn_patch, \"ax\"\n"
+ " .word 661b\n"
+ " and %0, %3, %0\n"
+ " .previous\n"
+ : "=r" (val)
+ : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
+
+ return val;
+}
+
+static inline int pte_special(pte_t pte)
+{
+ return 0;
+}
+
+#define pmd_set(pmdp, ptep) \
+ (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
+#define pud_set(pudp, pmdp) \
+ (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
+#define __pmd_page(pmd) \
+ ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
+#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
+#define pud_page_vaddr(pud) \
+ ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
+#define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud))
+#define pmd_none(pmd) (!pmd_val(pmd))
+#define pmd_bad(pmd) (0)
+#define pmd_present(pmd) (pmd_val(pmd) != 0U)
+#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U)
+#define pud_none(pud) (!pud_val(pud))
+#define pud_bad(pud) (0)
+#define pud_present(pud) (pud_val(pud) != 0U)
+#define pud_clear(pudp) (pud_val(*(pudp)) = 0U)
+
+/* Same in both SUN4V and SUN4U. */
+#define pte_none(pte) (!pte_val(pte))
+
+/* to find an entry in a page-table-directory. */
+#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/* Find an entry in the second-level page table.. */
+#define pmd_offset(pudp, address) \
+ ((pmd_t *) pud_page_vaddr(*(pudp)) + \
+ (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
+
+/* Find an entry in the third-level page table.. */
+#define pte_index(dir, address) \
+ ((pte_t *) __pmd_page(*(dir)) + \
+ ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+#define pte_offset_kernel pte_index
+#define pte_offset_map pte_index
+#define pte_offset_map_nested pte_index
+#define pte_unmap(pte) do { } while (0)
+#define pte_unmap_nested(pte) do { } while (0)
+
+/* Actual page table PTE updates. */
+extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
+
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
+{
+ pte_t orig = *ptep;
+
+ *ptep = pte;
+
+ /* It is more efficient to let flush_tlb_kernel_range()
+ * handle init_mm tlb flushes.
+ *
+ * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
+ * and SUN4V pte layout, so this inline test is fine.
+ */
+ if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
+ tlb_batch_add(mm, addr, ptep, orig);
+}
+
+#define pte_clear(mm,addr,ptep) \
+ set_pte_at((mm), (addr), (ptep), __pte(0UL))
+
+#ifdef DCACHE_ALIASING_POSSIBLE
+#define __HAVE_ARCH_MOVE_PTE
+#define move_pte(pte, prot, old_addr, new_addr) \
+({ \
+ pte_t newpte = (pte); \
+ if (tlb_type != hypervisor && pte_present(pte)) { \
+ unsigned long this_pfn = pte_pfn(pte); \
+ \
+ if (pfn_valid(this_pfn) && \
+ (((old_addr) ^ (new_addr)) & (1 << 13))) \
+ flush_dcache_page_all(current->mm, \
+ pfn_to_page(this_pfn)); \
+ } \
+ newpte; \
+})
+#endif
+
+extern pgd_t swapper_pg_dir[2048];
+extern pmd_t swapper_low_pmd_dir[2048];
+
+extern void paging_init(void);
+extern unsigned long find_ecache_flush_span(unsigned long size);
+
+/* These do nothing with the way I have things setup. */
+#define mmu_lockarea(vaddr, len) (vaddr)
+#define mmu_unlockarea(vaddr, len) do { } while(0)
+
+struct vm_area_struct;
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+
+/* Encode and de-code a swap entry */
+#define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
+#define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
+#define __swp_entry(type, offset) \
+ ( (swp_entry_t) \
+ { \
+ (((long)(type) << PAGE_SHIFT) | \
+ ((long)(offset) << (PAGE_SHIFT + 8UL))) \
+ } )
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
+
+/* File offset in PTE support. */
+extern unsigned long pte_file(pte_t);
+#define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
+extern pte_t pgoff_to_pte(unsigned long);
+#define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
+
+extern unsigned long *sparc64_valid_addr_bitmap;
+
+/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
+#define kern_addr_valid(addr) \
+ (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
+
+extern int page_in_phys_avail(unsigned long paddr);
+
+extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
+ unsigned long pfn,
+ unsigned long size, pgprot_t prot);
+
+/*
+ * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
+ * its high 4 bits. These macros/functions put it there or get it from there.
+ */
+#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
+#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
+#define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
+
+#include <asm-generic/pgtable.h>
+
+/* We provide our own get_unmapped_area to cope with VA holes and
+ * SHM area cache aliasing for userland.
+ */
+#define HAVE_ARCH_UNMAPPED_AREA
+#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
+
+/* We provide a special get_unmapped_area for framebuffer mmaps to try and use
+ * the largest alignment possible such that larget PTEs can be used.
+ */
+extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
+ unsigned long, unsigned long,
+ unsigned long);
+#define HAVE_ARCH_FB_UNMAPPED_AREA
+
+extern void pgtable_cache_init(void);
+extern void sun4v_register_fault_status(void);
+extern void sun4v_ktsb_register(void);
+extern void __init cheetah_ecache_flush_init(void);
+extern void sun4v_patch_tlb_handlers(void);
+
+extern unsigned long cmdline_memory_size;
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC64_PGTABLE_H) */
--- /dev/null
+/*
+ * pgtsrmmu.h: SRMMU page table defines and code.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_PGTSRMMU_H
+#define _SPARC_PGTSRMMU_H
+
+#include <asm/page.h>
+
+#ifdef __ASSEMBLY__
+#include <asm/thread_info.h> /* TI_UWINMASK for WINDOW_FLUSH */
+#endif
+
+/* Number of contexts is implementation-dependent; 64k is the most we support */
+#define SRMMU_MAX_CONTEXTS 65536
+
+/* PMD_SHIFT determines the size of the area a second-level page table entry can map */
+#define SRMMU_REAL_PMD_SHIFT 18
+#define SRMMU_REAL_PMD_SIZE (1UL << SRMMU_REAL_PMD_SHIFT)
+#define SRMMU_REAL_PMD_MASK (~(SRMMU_REAL_PMD_SIZE-1))
+#define SRMMU_REAL_PMD_ALIGN(__addr) (((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK)
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define SRMMU_PGDIR_SHIFT 24
+#define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT)
+#define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1))
+#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
+
+#define SRMMU_REAL_PTRS_PER_PTE 64
+#define SRMMU_REAL_PTRS_PER_PMD 64
+#define SRMMU_PTRS_PER_PGD 256
+
+#define SRMMU_REAL_PTE_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PTE*4)
+#define SRMMU_PMD_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PMD*4)
+#define SRMMU_PGD_TABLE_SIZE (SRMMU_PTRS_PER_PGD*4)
+
+/*
+ * To support pagetables in highmem, Linux introduces APIs which
+ * return struct page* and generally manipulate page tables when
+ * they are not mapped into kernel space. Our hardware page tables
+ * are smaller than pages. We lump hardware tabes into big, page sized
+ * software tables.
+ *
+ * PMD_SHIFT determines the size of the area a second-level page table entry
+ * can map, and our pmd_t is 16 times larger than normal. The values which
+ * were once defined here are now generic for 4c and srmmu, so they're
+ * found in pgtable.h.
+ */
+#define SRMMU_PTRS_PER_PMD 4
+
+/* Definition of the values in the ET field of PTD's and PTE's */
+#define SRMMU_ET_MASK 0x3
+#define SRMMU_ET_INVALID 0x0
+#define SRMMU_ET_PTD 0x1
+#define SRMMU_ET_PTE 0x2
+#define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */
+
+/* Physical page extraction from PTP's and PTE's. */
+#define SRMMU_CTX_PMASK 0xfffffff0
+#define SRMMU_PTD_PMASK 0xfffffff0
+#define SRMMU_PTE_PMASK 0xffffff00
+
+/* The pte non-page bits. Some notes:
+ * 1) cache, dirty, valid, and ref are frobbable
+ * for both supervisor and user pages.
+ * 2) exec and write will only give the desired effect
+ * on user pages
+ * 3) use priv and priv_readonly for changing the
+ * characteristics of supervisor ptes
+ */
+#define SRMMU_CACHE 0x80
+#define SRMMU_DIRTY 0x40
+#define SRMMU_REF 0x20
+#define SRMMU_NOREAD 0x10
+#define SRMMU_EXEC 0x08
+#define SRMMU_WRITE 0x04
+#define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */
+#define SRMMU_PRIV 0x1c
+#define SRMMU_PRIV_RDONLY 0x18
+
+#define SRMMU_FILE 0x40 /* Implemented in software */
+
+#define SRMMU_PTE_FILE_SHIFT 8 /* == 32-PTE_FILE_MAX_BITS */
+
+#define SRMMU_CHG_MASK (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
+
+/* SRMMU swap entry encoding
+ *
+ * We use 5 bits for the type and 19 for the offset. This gives us
+ * 32 swapfiles of 4GB each. Encoding looks like:
+ *
+ * oooooooooooooooooootttttRRRRRRRR
+ * fedcba9876543210fedcba9876543210
+ *
+ * The bottom 8 bits are reserved for protection and status bits, especially
+ * FILE and PRESENT.
+ */
+#define SRMMU_SWP_TYPE_MASK 0x1f
+#define SRMMU_SWP_TYPE_SHIFT SRMMU_PTE_FILE_SHIFT
+#define SRMMU_SWP_OFF_MASK 0x7ffff
+#define SRMMU_SWP_OFF_SHIFT (SRMMU_PTE_FILE_SHIFT + 5)
+
+/* Some day I will implement true fine grained access bits for
+ * user pages because the SRMMU gives us the capabilities to
+ * enforce all the protection levels that vma's can have.
+ * XXX But for now...
+ */
+#define SRMMU_PAGE_NONE __pgprot(SRMMU_CACHE | \
+ SRMMU_PRIV | SRMMU_REF)
+#define SRMMU_PAGE_SHARED __pgprot(SRMMU_VALID | SRMMU_CACHE | \
+ SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
+#define SRMMU_PAGE_COPY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
+ SRMMU_EXEC | SRMMU_REF)
+#define SRMMU_PAGE_RDONLY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
+ SRMMU_EXEC | SRMMU_REF)
+#define SRMMU_PAGE_KERNEL __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
+ SRMMU_DIRTY | SRMMU_REF)
+
+/* SRMMU Register addresses in ASI 0x4. These are valid for all
+ * current SRMMU implementations that exist.
+ */
+#define SRMMU_CTRL_REG 0x00000000
+#define SRMMU_CTXTBL_PTR 0x00000100
+#define SRMMU_CTX_REG 0x00000200
+#define SRMMU_FAULT_STATUS 0x00000300
+#define SRMMU_FAULT_ADDR 0x00000400
+
+#define WINDOW_FLUSH(tmp1, tmp2) \
+ mov 0, tmp1; \
+98: ld [%g6 + TI_UWINMASK], tmp2; \
+ orcc %g0, tmp2, %g0; \
+ add tmp1, 1, tmp1; \
+ bne 98b; \
+ save %sp, -64, %sp; \
+99: subcc tmp1, 1, tmp1; \
+ bne 99b; \
+ restore %g0, %g0, %g0;
+
+#ifndef __ASSEMBLY__
+
+/* This makes sense. Honest it does - Anton */
+/* XXX Yes but it's ugly as sin. FIXME. -KMW */
+extern void *srmmu_nocache_pool;
+#define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
+#define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
+#define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
+
+/* Accessing the MMU control register. */
+static inline unsigned int srmmu_get_mmureg(void)
+{
+ unsigned int retval;
+ __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
+ "=r" (retval) :
+ "i" (ASI_M_MMUREGS));
+ return retval;
+}
+
+static inline void srmmu_set_mmureg(unsigned long regval)
+{
+ __asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
+ "r" (regval), "i" (ASI_M_MMUREGS) : "memory");
+
+}
+
+static inline void srmmu_set_ctable_ptr(unsigned long paddr)
+{
+ paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
+ __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
+ "r" (paddr), "r" (SRMMU_CTXTBL_PTR),
+ "i" (ASI_M_MMUREGS) :
+ "memory");
+}
+
+static inline unsigned long srmmu_get_ctable_ptr(void)
+{
+ unsigned int retval;
+
+ __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+ "=r" (retval) :
+ "r" (SRMMU_CTXTBL_PTR),
+ "i" (ASI_M_MMUREGS));
+ return (retval & SRMMU_CTX_PMASK) << 4;
+}
+
+static inline void srmmu_set_context(int context)
+{
+ __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
+ "r" (context), "r" (SRMMU_CTX_REG),
+ "i" (ASI_M_MMUREGS) : "memory");
+}
+
+static inline int srmmu_get_context(void)
+{
+ register int retval;
+ __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+ "=r" (retval) :
+ "r" (SRMMU_CTX_REG),
+ "i" (ASI_M_MMUREGS));
+ return retval;
+}
+
+static inline unsigned int srmmu_get_fstatus(void)
+{
+ unsigned int retval;
+
+ __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+ "=r" (retval) :
+ "r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS));
+ return retval;
+}
+
+static inline unsigned int srmmu_get_faddr(void)
+{
+ unsigned int retval;
+
+ __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+ "=r" (retval) :
+ "r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS));
+ return retval;
+}
+
+/* This is guaranteed on all SRMMU's. */
+static inline void srmmu_flush_whole_tlb(void)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+ "r" (0x400), /* Flush entire TLB!! */
+ "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+/* These flush types are not available on all chips... */
+static inline void srmmu_flush_tlb_ctx(void)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+ "r" (0x300), /* Flush TLB ctx.. */
+ "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+static inline void srmmu_flush_tlb_region(unsigned long addr)
+{
+ addr &= SRMMU_PGDIR_MASK;
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+ "r" (addr | 0x200), /* Flush TLB region.. */
+ "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+
+static inline void srmmu_flush_tlb_segment(unsigned long addr)
+{
+ addr &= SRMMU_REAL_PMD_MASK;
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+ "r" (addr | 0x100), /* Flush TLB segment.. */
+ "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+static inline void srmmu_flush_tlb_page(unsigned long page)
+{
+ page &= PAGE_MASK;
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+ "r" (page), /* Flush TLB page.. */
+ "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+static inline unsigned long srmmu_hwprobe(unsigned long vaddr)
+{
+ unsigned long retval;
+
+ vaddr &= PAGE_MASK;
+ __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+ "=r" (retval) :
+ "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
+
+ return retval;
+}
+
+static inline int
+srmmu_get_pte (unsigned long addr)
+{
+ register unsigned long entry;
+
+ __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
+ "=r" (entry):
+ "r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
+ return entry;
+}
+
+extern unsigned long (*srmmu_read_physical)(unsigned long paddr);
+extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word);
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC_PGTSRMMU_H) */
--- /dev/null
+/*
+ * pgtsun4.h: Sun4 specific pgtable.h defines and code.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+#ifndef _SPARC_PGTSUN4C_H
+#define _SPARC_PGTSUN4C_H
+
+#include <asm/contregs.h>
+
+/* PMD_SHIFT determines the size of the area a second-level page table can map */
+#define SUN4C_PMD_SHIFT 23
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define SUN4C_PGDIR_SHIFT 23
+#define SUN4C_PGDIR_SIZE (1UL << SUN4C_PGDIR_SHIFT)
+#define SUN4C_PGDIR_MASK (~(SUN4C_PGDIR_SIZE-1))
+#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
+
+/* To represent how the sun4c mmu really lays things out. */
+#define SUN4C_REAL_PGDIR_SHIFT 18
+#define SUN4C_REAL_PGDIR_SIZE (1UL << SUN4C_REAL_PGDIR_SHIFT)
+#define SUN4C_REAL_PGDIR_MASK (~(SUN4C_REAL_PGDIR_SIZE-1))
+#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
+
+/* 19 bit PFN on sun4 */
+#define SUN4C_PFN_MASK 0x7ffff
+
+/* Don't increase these unless the structures in sun4c.c are fixed */
+#define SUN4C_MAX_SEGMAPS 256
+#define SUN4C_MAX_CONTEXTS 16
+
+/*
+ * To be efficient, and not have to worry about allocating such
+ * a huge pgd, we make the kernel sun4c tables each hold 1024
+ * entries and the pgd similarly just like the i386 tables.
+ */
+#define SUN4C_PTRS_PER_PTE 1024
+#define SUN4C_PTRS_PER_PMD 1
+#define SUN4C_PTRS_PER_PGD 1024
+
+/*
+ * Sparc SUN4C pte fields.
+ */
+#define _SUN4C_PAGE_VALID 0x80000000
+#define _SUN4C_PAGE_SILENT_READ 0x80000000 /* synonym */
+#define _SUN4C_PAGE_DIRTY 0x40000000
+#define _SUN4C_PAGE_SILENT_WRITE 0x40000000 /* synonym */
+#define _SUN4C_PAGE_PRIV 0x20000000 /* privileged page */
+#define _SUN4C_PAGE_NOCACHE 0x10000000 /* non-cacheable page */
+#define _SUN4C_PAGE_PRESENT 0x08000000 /* implemented in software */
+#define _SUN4C_PAGE_IO 0x04000000 /* I/O page */
+#define _SUN4C_PAGE_FILE 0x02000000 /* implemented in software */
+#define _SUN4C_PAGE_READ 0x00800000 /* implemented in software */
+#define _SUN4C_PAGE_WRITE 0x00400000 /* implemented in software */
+#define _SUN4C_PAGE_ACCESSED 0x00200000 /* implemented in software */
+#define _SUN4C_PAGE_MODIFIED 0x00100000 /* implemented in software */
+
+#define _SUN4C_READABLE (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
+ _SUN4C_PAGE_ACCESSED)
+#define _SUN4C_WRITEABLE (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
+ _SUN4C_PAGE_MODIFIED)
+
+#define _SUN4C_PAGE_CHG_MASK (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
+
+#define SUN4C_PAGE_NONE __pgprot(_SUN4C_PAGE_PRESENT)
+#define SUN4C_PAGE_SHARED __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
+ _SUN4C_PAGE_WRITE)
+#define SUN4C_PAGE_COPY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
+#define SUN4C_PAGE_READONLY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
+#define SUN4C_PAGE_KERNEL __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
+ _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
+
+/* SUN4C swap entry encoding
+ *
+ * We use 5 bits for the type and 19 for the offset. This gives us
+ * 32 swapfiles of 4GB each. Encoding looks like:
+ *
+ * RRRRRRRRooooooooooooooooooottttt
+ * fedcba9876543210fedcba9876543210
+ *
+ * The top 8 bits are reserved for protection and status bits, especially
+ * FILE and PRESENT.
+ */
+#define SUN4C_SWP_TYPE_MASK 0x1f
+#define SUN4C_SWP_OFF_MASK 0x7ffff
+#define SUN4C_SWP_OFF_SHIFT 5
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned long sun4c_get_synchronous_error(void)
+{
+ unsigned long sync_err;
+
+ __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+ "=r" (sync_err) :
+ "r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
+ return sync_err;
+}
+
+static inline unsigned long sun4c_get_synchronous_address(void)
+{
+ unsigned long sync_addr;
+
+ __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+ "=r" (sync_addr) :
+ "r" (AC_SYNC_VA), "i" (ASI_CONTROL));
+ return sync_addr;
+}
+
+/* SUN4 pte, segmap, and context manipulation */
+static inline unsigned long sun4c_get_segmap(unsigned long addr)
+{
+ register unsigned long entry;
+
+ __asm__ __volatile__("\n\tlduha [%1] %2, %0\n\t" :
+ "=r" (entry) :
+ "r" (addr), "i" (ASI_SEGMAP));
+ return entry;
+}
+
+static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
+{
+ __asm__ __volatile__("\n\tstha %1, [%0] %2; nop; nop; nop;\n\t" : :
+ "r" (addr), "r" (entry),
+ "i" (ASI_SEGMAP)
+ : "memory");
+}
+
+static inline unsigned long sun4c_get_pte(unsigned long addr)
+{
+ register unsigned long entry;
+
+ __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" :
+ "=r" (entry) :
+ "r" (addr), "i" (ASI_PTE));
+ return entry;
+}
+
+static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
+{
+ __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
+ "r" (addr),
+ "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
+ : "memory");
+}
+
+static inline int sun4c_get_context(void)
+{
+ register int ctx;
+
+ __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
+ "=r" (ctx) :
+ "r" (AC_CONTEXT), "i" (ASI_CONTROL));
+
+ return ctx;
+}
+
+static inline int sun4c_set_context(int ctx)
+{
+ __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
+ "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
+ : "memory");
+
+ return ctx;
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC_PGTSUN4_H) */
--- /dev/null
+/*
+ * pgtsun4c.h: Sun4c specific pgtable.h defines and code.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_PGTSUN4C_H
+#define _SPARC_PGTSUN4C_H
+
+#include <asm/contregs.h>
+
+/* PMD_SHIFT determines the size of the area a second-level page table can map */
+#define SUN4C_PMD_SHIFT 22
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define SUN4C_PGDIR_SHIFT 22
+#define SUN4C_PGDIR_SIZE (1UL << SUN4C_PGDIR_SHIFT)
+#define SUN4C_PGDIR_MASK (~(SUN4C_PGDIR_SIZE-1))
+#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
+
+/* To represent how the sun4c mmu really lays things out. */
+#define SUN4C_REAL_PGDIR_SHIFT 18
+#define SUN4C_REAL_PGDIR_SIZE (1UL << SUN4C_REAL_PGDIR_SHIFT)
+#define SUN4C_REAL_PGDIR_MASK (~(SUN4C_REAL_PGDIR_SIZE-1))
+#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
+
+/* 16 bit PFN on sun4c */
+#define SUN4C_PFN_MASK 0xffff
+
+/* Don't increase these unless the structures in sun4c.c are fixed */
+#define SUN4C_MAX_SEGMAPS 256
+#define SUN4C_MAX_CONTEXTS 16
+
+/*
+ * To be efficient, and not have to worry about allocating such
+ * a huge pgd, we make the kernel sun4c tables each hold 1024
+ * entries and the pgd similarly just like the i386 tables.
+ */
+#define SUN4C_PTRS_PER_PTE 1024
+#define SUN4C_PTRS_PER_PMD 1
+#define SUN4C_PTRS_PER_PGD 1024
+
+/*
+ * Sparc SUN4C pte fields.
+ */
+#define _SUN4C_PAGE_VALID 0x80000000
+#define _SUN4C_PAGE_SILENT_READ 0x80000000 /* synonym */
+#define _SUN4C_PAGE_DIRTY 0x40000000
+#define _SUN4C_PAGE_SILENT_WRITE 0x40000000 /* synonym */
+#define _SUN4C_PAGE_PRIV 0x20000000 /* privileged page */
+#define _SUN4C_PAGE_NOCACHE 0x10000000 /* non-cacheable page */
+#define _SUN4C_PAGE_PRESENT 0x08000000 /* implemented in software */
+#define _SUN4C_PAGE_IO 0x04000000 /* I/O page */
+#define _SUN4C_PAGE_FILE 0x02000000 /* implemented in software */
+#define _SUN4C_PAGE_READ 0x00800000 /* implemented in software */
+#define _SUN4C_PAGE_WRITE 0x00400000 /* implemented in software */
+#define _SUN4C_PAGE_ACCESSED 0x00200000 /* implemented in software */
+#define _SUN4C_PAGE_MODIFIED 0x00100000 /* implemented in software */
+
+#define _SUN4C_READABLE (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
+ _SUN4C_PAGE_ACCESSED)
+#define _SUN4C_WRITEABLE (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
+ _SUN4C_PAGE_MODIFIED)
+
+#define _SUN4C_PAGE_CHG_MASK (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
+
+#define SUN4C_PAGE_NONE __pgprot(_SUN4C_PAGE_PRESENT)
+#define SUN4C_PAGE_SHARED __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
+ _SUN4C_PAGE_WRITE)
+#define SUN4C_PAGE_COPY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
+#define SUN4C_PAGE_READONLY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
+#define SUN4C_PAGE_KERNEL __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
+ _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
+
+/* SUN4C swap entry encoding
+ *
+ * We use 5 bits for the type and 19 for the offset. This gives us
+ * 32 swapfiles of 4GB each. Encoding looks like:
+ *
+ * RRRRRRRRooooooooooooooooooottttt
+ * fedcba9876543210fedcba9876543210
+ *
+ * The top 8 bits are reserved for protection and status bits, especially
+ * FILE and PRESENT.
+ */
+#define SUN4C_SWP_TYPE_MASK 0x1f
+#define SUN4C_SWP_OFF_MASK 0x7ffff
+#define SUN4C_SWP_OFF_SHIFT 5
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned long sun4c_get_synchronous_error(void)
+{
+ unsigned long sync_err;
+
+ __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+ "=r" (sync_err) :
+ "r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
+ return sync_err;
+}
+
+static inline unsigned long sun4c_get_synchronous_address(void)
+{
+ unsigned long sync_addr;
+
+ __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+ "=r" (sync_addr) :
+ "r" (AC_SYNC_VA), "i" (ASI_CONTROL));
+ return sync_addr;
+}
+
+/* SUN4C pte, segmap, and context manipulation */
+static inline unsigned long sun4c_get_segmap(unsigned long addr)
+{
+ register unsigned long entry;
+
+ __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
+ "=r" (entry) :
+ "r" (addr), "i" (ASI_SEGMAP));
+
+ return entry;
+}
+
+static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
+{
+
+ __asm__ __volatile__("\n\tstba %1, [%0] %2; nop; nop; nop;\n\t" : :
+ "r" (addr), "r" (entry),
+ "i" (ASI_SEGMAP)
+ : "memory");
+}
+
+static inline unsigned long sun4c_get_pte(unsigned long addr)
+{
+ register unsigned long entry;
+
+ __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" :
+ "=r" (entry) :
+ "r" (addr), "i" (ASI_PTE));
+ return entry;
+}
+
+static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
+{
+ __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
+ "r" (addr),
+ "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
+ : "memory");
+}
+
+static inline int sun4c_get_context(void)
+{
+ register int ctx;
+
+ __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
+ "=r" (ctx) :
+ "r" (AC_CONTEXT), "i" (ASI_CONTROL));
+
+ return ctx;
+}
+
+static inline int sun4c_set_context(int ctx)
+{
+ __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
+ "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
+ : "memory");
+
+ return ctx;
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC_PGTSUN4C_H) */
--- /dev/null
+#ifndef _SPARC64_PIL_H
+#define _SPARC64_PIL_H
+
+/* To avoid some locking problems, we hard allocate certain PILs
+ * for SMP cross call messages that must do a etrap/rtrap.
+ *
+ * A local_irq_disable() does not block the cross call delivery, so
+ * when SMP locking is an issue we reschedule the event into a PIL
+ * interrupt which is blocked by local_irq_disable().
+ *
+ * In fact any XCALL which has to etrap/rtrap has a problem because
+ * it is difficult to prevent rtrap from running BH's, and that would
+ * need to be done if the XCALL arrived while %pil==15.
+ */
+#define PIL_SMP_CALL_FUNC 1
+#define PIL_SMP_RECEIVE_SIGNAL 2
+#define PIL_SMP_CAPTURE 3
+#define PIL_SMP_CTX_NEW_VERSION 4
+#define PIL_DEVICE_IRQ 5
+#define PIL_SMP_CALL_FUNC_SNGL 6
+
+#endif /* !(_SPARC64_PIL_H) */
--- /dev/null
+#ifndef __SPARC_POLL_H
+#define __SPARC_POLL_H
+
+#define POLLWRNORM POLLOUT
+#define POLLWRBAND 256
+#define POLLMSG 512
+#define POLLREMOVE 1024
+#define POLLRDHUP 2048
+
+#include <asm-generic/poll.h>
+
+#endif
--- /dev/null
+#ifndef ___ASM_SPARC_POSIX_TYPES_H
+#define ___ASM_SPARC_POSIX_TYPES_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/posix_types_64.h>
+#else
+#include <asm/posix_types_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef __ARCH_SPARC_POSIX_TYPES_H
+#define __ARCH_SPARC_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc. Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned int __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef long int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_pid_t;
+typedef unsigned short __kernel_ipc_pid_t;
+typedef unsigned short __kernel_uid_t;
+typedef unsigned short __kernel_gid_t;
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_umode_t;
+typedef short __kernel_nlink_t;
+typedef long __kernel_daddr_t;
+typedef long __kernel_off_t;
+typedef char * __kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+typedef unsigned short __kernel_old_dev_t;
+typedef int __kernel_clockid_t;
+typedef int __kernel_timer_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+ int val[2];
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__)
+
+#undef __FD_SET
+static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+ unsigned long _tmp = fd / __NFDBITS;
+ unsigned long _rem = fd % __NFDBITS;
+ fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static inline void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+ unsigned long _tmp = fd / __NFDBITS;
+ unsigned long _rem = fd % __NFDBITS;
+ fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static inline int __FD_ISSET(unsigned long fd, __const__ __kernel_fd_set *p)
+{
+ unsigned long _tmp = fd / __NFDBITS;
+ unsigned long _rem = fd % __NFDBITS;
+ return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant cases (8 or 32 longs,
+ * for 256 and 1024-bit fd_sets respectively)
+ */
+#undef __FD_ZERO
+static inline void __FD_ZERO(__kernel_fd_set *p)
+{
+ unsigned long *tmp = p->fds_bits;
+ int i;
+
+ if (__builtin_constant_p(__FDSET_LONGS)) {
+ switch (__FDSET_LONGS) {
+ case 32:
+ tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+ tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+ tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
+ tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
+ tmp[16] = 0; tmp[17] = 0; tmp[18] = 0; tmp[19] = 0;
+ tmp[20] = 0; tmp[21] = 0; tmp[22] = 0; tmp[23] = 0;
+ tmp[24] = 0; tmp[25] = 0; tmp[26] = 0; tmp[27] = 0;
+ tmp[28] = 0; tmp[29] = 0; tmp[30] = 0; tmp[31] = 0;
+ return;
+ case 16:
+ tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+ tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+ tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
+ tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
+ return;
+ case 8:
+ tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+ tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+ return;
+ case 4:
+ tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+ return;
+ }
+ }
+ i = __FDSET_LONGS;
+ while (i) {
+ i--;
+ *tmp = 0;
+ tmp++;
+ }
+}
+
+#endif /* defined(__KERNEL__) */
+
+#endif /* !(__ARCH_SPARC_POSIX_TYPES_H) */
--- /dev/null
+#ifndef __ARCH_SPARC64_POSIX_TYPES_H
+#define __ARCH_SPARC64_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc. Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_pid_t;
+typedef int __kernel_ipc_pid_t;
+typedef unsigned int __kernel_uid_t;
+typedef unsigned int __kernel_gid_t;
+typedef unsigned long __kernel_ino_t;
+typedef unsigned int __kernel_mode_t;
+typedef unsigned short __kernel_umode_t;
+typedef unsigned int __kernel_nlink_t;
+typedef int __kernel_daddr_t;
+typedef long __kernel_off_t;
+typedef char * __kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef int __kernel_clockid_t;
+typedef int __kernel_timer_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+typedef __kernel_uid_t __kernel_uid32_t;
+typedef __kernel_gid_t __kernel_gid32_t;
+
+typedef unsigned int __kernel_old_dev_t;
+
+/* Note this piece of asymmetry from the v9 ABI. */
+typedef int __kernel_suseconds_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+ int val[2];
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__)
+
+#undef __FD_SET
+static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+ unsigned long _tmp = fd / __NFDBITS;
+ unsigned long _rem = fd % __NFDBITS;
+ fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static inline void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+ unsigned long _tmp = fd / __NFDBITS;
+ unsigned long _rem = fd % __NFDBITS;
+ fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static inline int __FD_ISSET(unsigned long fd, __const__ __kernel_fd_set *p)
+{
+ unsigned long _tmp = fd / __NFDBITS;
+ unsigned long _rem = fd % __NFDBITS;
+ return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant cases (8 or 32 longs,
+ * for 256 and 1024-bit fd_sets respectively)
+ */
+#undef __FD_ZERO
+static inline void __FD_ZERO(__kernel_fd_set *p)
+{
+ unsigned long *tmp = p->fds_bits;
+ int i;
+
+ if (__builtin_constant_p(__FDSET_LONGS)) {
+ switch (__FDSET_LONGS) {
+ case 32:
+ tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+ tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+ tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
+ tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
+ tmp[16] = 0; tmp[17] = 0; tmp[18] = 0; tmp[19] = 0;
+ tmp[20] = 0; tmp[21] = 0; tmp[22] = 0; tmp[23] = 0;
+ tmp[24] = 0; tmp[25] = 0; tmp[26] = 0; tmp[27] = 0;
+ tmp[28] = 0; tmp[29] = 0; tmp[30] = 0; tmp[31] = 0;
+ return;
+ case 16:
+ tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+ tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+ tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
+ tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
+ return;
+ case 8:
+ tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+ tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+ return;
+ case 4:
+ tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+ return;
+ }
+ }
+ i = __FDSET_LONGS;
+ while (i) {
+ i--;
+ *tmp = 0;
+ tmp++;
+ }
+}
+
+#endif /* defined(__KERNEL__) */
+
+#endif /* !(__ARCH_SPARC64_POSIX_TYPES_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_PROCESSOR_H
+#define ___ASM_SPARC_PROCESSOR_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/processor_64.h>
+#else
+#include <asm/processor_32.h>
+#endif
+#endif
--- /dev/null
+/* include/asm/processor.h
+ *
+ * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __ASM_SPARC_PROCESSOR_H
+#define __ASM_SPARC_PROCESSOR_H
+
+/*
+ * Sparc32 implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ void *pc; __asm__("sethi %%hi(1f), %0; or %0, %%lo(1f), %0;\n1:" : "=r" (pc)); pc; })
+
+#include <asm/psr.h>
+#include <asm/ptrace.h>
+#include <asm/head.h>
+#include <asm/signal.h>
+#include <asm/btfixup.h>
+#include <asm/page.h>
+
+/*
+ * The sparc has no problems with write protection
+ */
+#define wp_works_ok 1
+#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
+
+/* Whee, this is STACK_TOP + PAGE_SIZE and the lowest kernel address too...
+ * That one page is used to protect kernel from intruders, so that
+ * we can make our access_ok test faster
+ */
+#define TASK_SIZE PAGE_OFFSET
+#ifdef __KERNEL__
+#define STACK_TOP (PAGE_OFFSET - PAGE_SIZE)
+#define STACK_TOP_MAX STACK_TOP
+#endif /* __KERNEL__ */
+
+struct task_struct;
+
+#ifdef __KERNEL__
+struct fpq {
+ unsigned long *insn_addr;
+ unsigned long insn;
+};
+#endif
+
+typedef struct {
+ int seg;
+} mm_segment_t;
+
+/* The Sparc processor specific thread struct. */
+struct thread_struct {
+ struct pt_regs *kregs;
+ unsigned int _pad1;
+
+ /* Special child fork kpsr/kwim values. */
+ unsigned long fork_kpsr __attribute__ ((aligned (8)));
+ unsigned long fork_kwim;
+
+ /* Floating point regs */
+ unsigned long float_regs[32] __attribute__ ((aligned (8)));
+ unsigned long fsr;
+ unsigned long fpqdepth;
+ struct fpq fpqueue[16];
+ unsigned long flags;
+ mm_segment_t current_ds;
+};
+
+#define SPARC_FLAG_KTHREAD 0x1 /* task is a kernel thread */
+#define SPARC_FLAG_UNALIGNED 0x2 /* is allowed to do unaligned accesses */
+
+#define INIT_THREAD { \
+ .flags = SPARC_FLAG_KTHREAD, \
+ .current_ds = KERNEL_DS, \
+}
+
+/* Return saved PC of a blocked thread. */
+extern unsigned long thread_saved_pc(struct task_struct *t);
+
+/* Do necessary setup to start up a newly executed thread. */
+static inline void start_thread(struct pt_regs * regs, unsigned long pc,
+ unsigned long sp)
+{
+ register unsigned long zero asm("g1");
+
+ regs->psr = (regs->psr & (PSR_CWP)) | PSR_S;
+ regs->pc = ((pc & (~3)) - 4);
+ regs->npc = regs->pc + 4;
+ regs->y = 0;
+ zero = 0;
+ __asm__ __volatile__("std\t%%g0, [%0 + %3 + 0x00]\n\t"
+ "std\t%%g0, [%0 + %3 + 0x08]\n\t"
+ "std\t%%g0, [%0 + %3 + 0x10]\n\t"
+ "std\t%%g0, [%0 + %3 + 0x18]\n\t"
+ "std\t%%g0, [%0 + %3 + 0x20]\n\t"
+ "std\t%%g0, [%0 + %3 + 0x28]\n\t"
+ "std\t%%g0, [%0 + %3 + 0x30]\n\t"
+ "st\t%1, [%0 + %3 + 0x38]\n\t"
+ "st\t%%g0, [%0 + %3 + 0x3c]"
+ : /* no outputs */
+ : "r" (regs),
+ "r" (sp - sizeof(struct reg_window)),
+ "r" (zero),
+ "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))
+ : "memory");
+}
+
+/* Free all resources held by a thread. */
+#define release_thread(tsk) do { } while(0)
+extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk) do { } while (0)
+
+extern unsigned long get_wchan(struct task_struct *);
+
+#define task_pt_regs(tsk) ((tsk)->thread.kregs)
+#define KSTK_EIP(tsk) ((tsk)->thread.kregs->pc)
+#define KSTK_ESP(tsk) ((tsk)->thread.kregs->u_regs[UREG_FP])
+
+#ifdef __KERNEL__
+
+extern struct task_struct *last_task_used_math;
+
+#define cpu_relax() barrier()
+
+#endif
+
+#endif /* __ASM_SPARC_PROCESSOR_H */
--- /dev/null
+/*
+ * include/asm/processor.h
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __ASM_SPARC64_PROCESSOR_H
+#define __ASM_SPARC64_PROCESSOR_H
+
+/*
+ * Sparc64 implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; })
+
+#include <asm/asi.h>
+#include <asm/pstate.h>
+#include <asm/ptrace.h>
+#include <asm/page.h>
+
+/* The sparc has no problems with write protection */
+#define wp_works_ok 1
+#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
+
+/*
+ * User lives in his very own context, and cannot reference us. Note
+ * that TASK_SIZE is a misnomer, it really gives maximum user virtual
+ * address that the kernel will allocate out.
+ *
+ * XXX No longer using virtual page tables, kill this upper limit...
+ */
+#define VA_BITS 44
+#ifndef __ASSEMBLY__
+#define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
+#else
+#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
+#endif
+
+#define TASK_SIZE ((unsigned long)-VPTE_SIZE)
+#define TASK_SIZE_OF(tsk) \
+ (test_tsk_thread_flag(tsk,TIF_32BIT) ? \
+ (1UL << 32UL) : TASK_SIZE)
+#ifdef __KERNEL__
+
+#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
+#define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL))
+
+#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
+ STACK_TOP32 : STACK_TOP64)
+
+#define STACK_TOP_MAX STACK_TOP64
+
+#endif
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+ unsigned char seg;
+} mm_segment_t;
+
+/* The Sparc processor specific thread struct. */
+/* XXX This should die, everything can go into thread_info now. */
+struct thread_struct {
+#ifdef CONFIG_DEBUG_SPINLOCK
+ /* How many spinlocks held by this thread.
+ * Used with spin lock debugging to catch tasks
+ * sleeping illegally with locks held.
+ */
+ int smp_lock_count;
+ unsigned int smp_lock_pc;
+#else
+ int dummy; /* f'in gcc bug... */
+#endif
+};
+
+#endif /* !(__ASSEMBLY__) */
+
+#ifndef CONFIG_DEBUG_SPINLOCK
+#define INIT_THREAD { \
+ 0, \
+}
+#else /* CONFIG_DEBUG_SPINLOCK */
+#define INIT_THREAD { \
+/* smp_lock_count, smp_lock_pc, */ \
+ 0, 0, \
+}
+#endif /* !(CONFIG_DEBUG_SPINLOCK) */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+/* Return saved PC of a blocked thread. */
+struct task_struct;
+extern unsigned long thread_saved_pc(struct task_struct *);
+
+/* On Uniprocessor, even in RMO processes see TSO semantics */
+#ifdef CONFIG_SMP
+#define TSTATE_INITIAL_MM TSTATE_TSO
+#else
+#define TSTATE_INITIAL_MM TSTATE_RMO
+#endif
+
+/* Do necessary setup to start up a newly executed thread. */
+#define start_thread(regs, pc, sp) \
+do { \
+ unsigned long __asi = ASI_PNF; \
+ regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \
+ regs->tpc = ((pc & (~3)) - 4); \
+ regs->tnpc = regs->tpc + 4; \
+ regs->y = 0; \
+ set_thread_wstate(1 << 3); \
+ if (current_thread_info()->utraps) { \
+ if (*(current_thread_info()->utraps) < 2) \
+ kfree(current_thread_info()->utraps); \
+ else \
+ (*(current_thread_info()->utraps))--; \
+ current_thread_info()->utraps = NULL; \
+ } \
+ __asm__ __volatile__( \
+ "stx %%g0, [%0 + %2 + 0x00]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x08]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x10]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x18]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x20]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x28]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x30]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x38]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x40]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x48]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x50]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x58]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x60]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x68]\n\t" \
+ "stx %1, [%0 + %2 + 0x70]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x78]\n\t" \
+ "wrpr %%g0, (1 << 3), %%wstate\n\t" \
+ : \
+ : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
+ "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
+} while (0)
+
+#define start_thread32(regs, pc, sp) \
+do { \
+ unsigned long __asi = ASI_PNF; \
+ pc &= 0x00000000ffffffffUL; \
+ sp &= 0x00000000ffffffffUL; \
+ regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \
+ regs->tpc = ((pc & (~3)) - 4); \
+ regs->tnpc = regs->tpc + 4; \
+ regs->y = 0; \
+ set_thread_wstate(2 << 3); \
+ if (current_thread_info()->utraps) { \
+ if (*(current_thread_info()->utraps) < 2) \
+ kfree(current_thread_info()->utraps); \
+ else \
+ (*(current_thread_info()->utraps))--; \
+ current_thread_info()->utraps = NULL; \
+ } \
+ __asm__ __volatile__( \
+ "stx %%g0, [%0 + %2 + 0x00]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x08]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x10]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x18]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x20]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x28]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x30]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x38]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x40]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x48]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x50]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x58]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x60]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x68]\n\t" \
+ "stx %1, [%0 + %2 + 0x70]\n\t" \
+ "stx %%g0, [%0 + %2 + 0x78]\n\t" \
+ "wrpr %%g0, (2 << 3), %%wstate\n\t" \
+ : \
+ : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
+ "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
+} while (0)
+
+/* Free all resources held by a thread. */
+#define release_thread(tsk) do { } while (0)
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk) do { } while (0)
+
+extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+extern unsigned long get_wchan(struct task_struct *task);
+
+#define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
+#define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc)
+#define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP])
+
+#define cpu_relax() barrier()
+
+/* Prefetch support. This is tuned for UltraSPARC-III and later.
+ * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
+ * a shallower prefetch queue than later chips.
+ */
+#define ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCHW
+#define ARCH_HAS_SPINLOCK_PREFETCH
+
+static inline void prefetch(const void *x)
+{
+ /* We do not use the read prefetch mnemonic because that
+ * prefetches into the prefetch-cache which only is accessible
+ * by floating point operations in UltraSPARC-III and later.
+ * By contrast, "#one_write" prefetches into the L2 cache
+ * in shared state.
+ */
+ __asm__ __volatile__("prefetch [%0], #one_write"
+ : /* no outputs */
+ : "r" (x));
+}
+
+static inline void prefetchw(const void *x)
+{
+ /* The most optimal prefetch to use for writes is
+ * "#n_writes". This brings the cacheline into the
+ * L2 cache in "owned" state.
+ */
+ __asm__ __volatile__("prefetch [%0], #n_writes"
+ : /* no outputs */
+ : "r" (x));
+}
+
+#define spin_lock_prefetch(x) prefetchw(x)
+
+#define HAVE_ARCH_PICK_MMAP_LAYOUT
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
--- /dev/null
+#ifndef _SPARC_PROM_H
+#define _SPARC_PROM_H
+#ifdef __KERNEL__
+
+/*
+ * Definitions for talking to the Open Firmware PROM on
+ * Power Macintosh computers.
+ *
+ * Copyright (C) 1996-2005 Paul Mackerras.
+ *
+ * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp.
+ * Updates for SPARC by David S. Miller
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/types.h>
+#include <linux/proc_fs.h>
+#include <asm/atomic.h>
+
+#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 2
+#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1
+
+#define of_compat_cmp(s1, s2, l) strncmp((s1), (s2), (l))
+#define of_prop_cmp(s1, s2) strcasecmp((s1), (s2))
+#define of_node_cmp(s1, s2) strcmp((s1), (s2))
+
+typedef u32 phandle;
+typedef u32 ihandle;
+
+struct property {
+ char *name;
+ int length;
+ void *value;
+ struct property *next;
+ unsigned long _flags;
+ unsigned int unique_id;
+};
+
+struct of_irq_controller;
+struct device_node {
+ const char *name;
+ const char *type;
+ phandle node;
+ char *path_component_name;
+ char *full_name;
+
+ struct property *properties;
+ struct property *deadprops; /* removed properties */
+ struct device_node *parent;
+ struct device_node *child;
+ struct device_node *sibling;
+ struct device_node *next; /* next device of same type */
+ struct device_node *allnext; /* next in list of all nodes */
+ struct proc_dir_entry *pde; /* this node's proc directory */
+ struct kref kref;
+ unsigned long _flags;
+ void *data;
+ unsigned int unique_id;
+
+ struct of_irq_controller *irq_trans;
+};
+
+struct of_irq_controller {
+ unsigned int (*irq_build)(struct device_node *, unsigned int, void *);
+ void *data;
+};
+
+#define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags)
+#define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags)
+
+extern struct device_node *of_find_node_by_cpuid(int cpuid);
+extern int of_set_property(struct device_node *node, const char *name, void *val, int len);
+extern int of_getintprop_default(struct device_node *np,
+ const char *name,
+ int def);
+extern int of_find_in_proplist(const char *list, const char *match, int len);
+#ifdef CONFIG_NUMA
+extern int of_node_to_nid(struct device_node *dp);
+#else
+#define of_node_to_nid(dp) (-1)
+#endif
+
+extern void prom_build_devicetree(void);
+
+/* Dummy ref counting routines - to be implemented later */
+static inline struct device_node *of_node_get(struct device_node *node)
+{
+ return node;
+}
+static inline void of_node_put(struct device_node *node)
+{
+}
+
+/*
+ * NB: This is here while we transition from using asm/prom.h
+ * to linux/of.h
+ */
+#include <linux/of.h>
+
+extern struct device_node *of_console_device;
+extern char *of_console_path;
+extern char *of_console_options;
+
+#endif /* __KERNEL__ */
+#endif /* _SPARC_PROM_H */
--- /dev/null
+/*
+ * psr.h: This file holds the macros for masking off various parts of
+ * the processor status register on the Sparc. This is valid
+ * for Version 8. On the V9 this is renamed to the PSTATE
+ * register and its members are accessed as fields like
+ * PSTATE.PRIV for the current CPU privilege level.
+ *
+ * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __LINUX_SPARC_PSR_H
+#define __LINUX_SPARC_PSR_H
+
+/* The Sparc PSR fields are laid out as the following:
+ *
+ * ------------------------------------------------------------------------
+ * | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP |
+ * | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 |
+ * ------------------------------------------------------------------------
+ */
+#define PSR_CWP 0x0000001f /* current window pointer */
+#define PSR_ET 0x00000020 /* enable traps field */
+#define PSR_PS 0x00000040 /* previous privilege level */
+#define PSR_S 0x00000080 /* current privilege level */
+#define PSR_PIL 0x00000f00 /* processor interrupt level */
+#define PSR_EF 0x00001000 /* enable floating point */
+#define PSR_EC 0x00002000 /* enable co-processor */
+#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
+#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
+#define PSR_ICC 0x00f00000 /* integer condition codes */
+#define PSR_C 0x00100000 /* carry bit */
+#define PSR_V 0x00200000 /* overflow bit */
+#define PSR_Z 0x00400000 /* zero bit */
+#define PSR_N 0x00800000 /* negative bit */
+#define PSR_VERS 0x0f000000 /* cpu-version field */
+#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+/* Get the %psr register. */
+static inline unsigned int get_psr(void)
+{
+ unsigned int psr;
+ __asm__ __volatile__(
+ "rd %%psr, %0\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ : "=r" (psr)
+ : /* no inputs */
+ : "memory");
+
+ return psr;
+}
+
+static inline void put_psr(unsigned int new_psr)
+{
+ __asm__ __volatile__(
+ "wr %0, 0x0, %%psr\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ : /* no outputs */
+ : "r" (new_psr)
+ : "memory", "cc");
+}
+
+/* Get the %fsr register. Be careful, make sure the floating point
+ * enable bit is set in the %psr when you execute this or you will
+ * incur a trap.
+ */
+
+extern unsigned int fsr_storage;
+
+static inline unsigned int get_fsr(void)
+{
+ unsigned int fsr = 0;
+
+ __asm__ __volatile__(
+ "st %%fsr, %1\n\t"
+ "ld %1, %0\n\t"
+ : "=r" (fsr)
+ : "m" (fsr_storage));
+
+ return fsr;
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* (__KERNEL__) */
+
+#endif /* !(__LINUX_SPARC_PSR_H) */
--- /dev/null
+#ifndef _SPARC64_PSRCOMPAT_H
+#define _SPARC64_PSRCOMPAT_H
+
+#include <asm/pstate.h>
+
+/* Old 32-bit PSR fields for the compatibility conversion code. */
+#define PSR_CWP 0x0000001f /* current window pointer */
+#define PSR_ET 0x00000020 /* enable traps field */
+#define PSR_PS 0x00000040 /* previous privilege level */
+#define PSR_S 0x00000080 /* current privilege level */
+#define PSR_PIL 0x00000f00 /* processor interrupt level */
+#define PSR_EF 0x00001000 /* enable floating point */
+#define PSR_EC 0x00002000 /* enable co-processor */
+#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
+#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
+#define PSR_ICC 0x00f00000 /* integer condition codes */
+#define PSR_C 0x00100000 /* carry bit */
+#define PSR_V 0x00200000 /* overflow bit */
+#define PSR_Z 0x00400000 /* zero bit */
+#define PSR_N 0x00800000 /* negative bit */
+#define PSR_VERS 0x0f000000 /* cpu-version field */
+#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
+
+#define PSR_V8PLUS 0xff000000 /* fake impl/ver, meaning a 64bit CPU is present */
+#define PSR_XCC 0x000f0000 /* if PSR_V8PLUS, this is %xcc */
+
+static inline unsigned int tstate_to_psr(unsigned long tstate)
+{
+ return ((tstate & TSTATE_CWP) |
+ PSR_S |
+ ((tstate & TSTATE_ICC) >> 12) |
+ ((tstate & TSTATE_XCC) >> 20) |
+ ((tstate & TSTATE_SYSCALL) ? PSR_SYSCALL : 0) |
+ PSR_V8PLUS);
+}
+
+static inline unsigned long psr_to_tstate_icc(unsigned int psr)
+{
+ unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12;
+ if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS)
+ tstate |= ((unsigned long)(psr & PSR_XCC)) << 20;
+ return tstate;
+}
+
+#endif /* !(_SPARC64_PSRCOMPAT_H) */
--- /dev/null
+#ifndef _SPARC64_PSTATE_H
+#define _SPARC64_PSTATE_H
+
+#include <linux/const.h>
+
+/* The V9 PSTATE Register (with SpitFire extensions).
+ *
+ * -----------------------------------------------------------------------
+ * | Resv | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG |
+ * -----------------------------------------------------------------------
+ * 63 12 11 10 9 8 7 6 5 4 3 2 1 0
+ */
+#define PSTATE_IG _AC(0x0000000000000800,UL) /* Interrupt Globals. */
+#define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals. */
+#define PSTATE_CLE _AC(0x0000000000000200,UL) /* Current Little Endian.*/
+#define PSTATE_TLE _AC(0x0000000000000100,UL) /* Trap Little Endian. */
+#define PSTATE_MM _AC(0x00000000000000c0,UL) /* Memory Model. */
+#define PSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder */
+#define PSTATE_PSO _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder */
+#define PSTATE_RMO _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/
+#define PSTATE_RED _AC(0x0000000000000020,UL) /* Reset Error Debug. */
+#define PSTATE_PEF _AC(0x0000000000000010,UL) /* Floating Point Enable.*/
+#define PSTATE_AM _AC(0x0000000000000008,UL) /* Address Mask. */
+#define PSTATE_PRIV _AC(0x0000000000000004,UL) /* Privilege. */
+#define PSTATE_IE _AC(0x0000000000000002,UL) /* Interrupt Enable. */
+#define PSTATE_AG _AC(0x0000000000000001,UL) /* Alternate Globals. */
+
+/* The V9 TSTATE Register (with SpitFire and Linux extensions).
+ *
+ * ---------------------------------------------------------------------
+ * | Resv | GL | CCR | ASI | %pil | PSTATE | Resv | CWP |
+ * ---------------------------------------------------------------------
+ * 63 43 42 40 39 32 31 24 23 20 19 8 7 5 4 0
+ */
+#define TSTATE_GL _AC(0x0000070000000000,UL) /* Global reg level */
+#define TSTATE_CCR _AC(0x000000ff00000000,UL) /* Condition Codes. */
+#define TSTATE_XCC _AC(0x000000f000000000,UL) /* Condition Codes. */
+#define TSTATE_XNEG _AC(0x0000008000000000,UL) /* %xcc Negative. */
+#define TSTATE_XZERO _AC(0x0000004000000000,UL) /* %xcc Zero. */
+#define TSTATE_XOVFL _AC(0x0000002000000000,UL) /* %xcc Overflow. */
+#define TSTATE_XCARRY _AC(0x0000001000000000,UL) /* %xcc Carry. */
+#define TSTATE_ICC _AC(0x0000000f00000000,UL) /* Condition Codes. */
+#define TSTATE_INEG _AC(0x0000000800000000,UL) /* %icc Negative. */
+#define TSTATE_IZERO _AC(0x0000000400000000,UL) /* %icc Zero. */
+#define TSTATE_IOVFL _AC(0x0000000200000000,UL) /* %icc Overflow. */
+#define TSTATE_ICARRY _AC(0x0000000100000000,UL) /* %icc Carry. */
+#define TSTATE_ASI _AC(0x00000000ff000000,UL) /* AddrSpace ID. */
+#define TSTATE_PIL _AC(0x0000000000f00000,UL) /* %pil (Linux traps)*/
+#define TSTATE_PSTATE _AC(0x00000000000fff00,UL) /* PSTATE. */
+#define TSTATE_IG _AC(0x0000000000080000,UL) /* Interrupt Globals.*/
+#define TSTATE_MG _AC(0x0000000000040000,UL) /* MMU Globals. */
+#define TSTATE_CLE _AC(0x0000000000020000,UL) /* CurrLittleEndian. */
+#define TSTATE_TLE _AC(0x0000000000010000,UL) /* TrapLittleEndian. */
+#define TSTATE_MM _AC(0x000000000000c000,UL) /* Memory Model. */
+#define TSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TSO */
+#define TSTATE_PSO _AC(0x0000000000004000,UL) /* MM: PSO */
+#define TSTATE_RMO _AC(0x0000000000008000,UL) /* MM: RMO */
+#define TSTATE_RED _AC(0x0000000000002000,UL) /* Reset Error Debug.*/
+#define TSTATE_PEF _AC(0x0000000000001000,UL) /* FPU Enable. */
+#define TSTATE_AM _AC(0x0000000000000800,UL) /* Address Mask. */
+#define TSTATE_PRIV _AC(0x0000000000000400,UL) /* Privilege. */
+#define TSTATE_IE _AC(0x0000000000000200,UL) /* Interrupt Enable. */
+#define TSTATE_AG _AC(0x0000000000000100,UL) /* Alternate Globals.*/
+#define TSTATE_SYSCALL _AC(0x0000000000000020,UL) /* in syscall trap */
+#define TSTATE_CWP _AC(0x000000000000001f,UL) /* Curr Win-Pointer. */
+
+/* Floating-Point Registers State Register.
+ *
+ * --------------------------------
+ * | Resv | FEF | DU | DL |
+ * --------------------------------
+ * 63 3 2 1 0
+ */
+#define FPRS_FEF _AC(0x0000000000000004,UL) /* FPU Enable. */
+#define FPRS_DU _AC(0x0000000000000002,UL) /* Dirty Upper. */
+#define FPRS_DL _AC(0x0000000000000001,UL) /* Dirty Lower. */
+
+/* Version Register.
+ *
+ * ------------------------------------------------------
+ * | MANUF | IMPL | MASK | Resv | MAXTL | Resv | MAXWIN |
+ * ------------------------------------------------------
+ * 63 48 47 32 31 24 23 16 15 8 7 5 4 0
+ */
+#define VERS_MANUF _AC(0xffff000000000000,UL) /* Manufacturer. */
+#define VERS_IMPL _AC(0x0000ffff00000000,UL) /* Implementation. */
+#define VERS_MASK _AC(0x00000000ff000000,UL) /* Mask Set Revision.*/
+#define VERS_MAXTL _AC(0x000000000000ff00,UL) /* Max Trap Level. */
+#define VERS_MAXWIN _AC(0x000000000000001f,UL) /* Max RegWindow Idx.*/
+
+#endif /* !(_SPARC64_PSTATE_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_PTRACE_H
+#define ___ASM_SPARC_PTRACE_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/ptrace_64.h>
+#else
+#include <asm/ptrace_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _SPARC_PTRACE_H
+#define _SPARC_PTRACE_H
+
+#include <asm/psr.h>
+
+/* This struct defines the way the registers are stored on the
+ * stack during a system call and basically all traps.
+ */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+struct pt_regs {
+ unsigned long psr;
+ unsigned long pc;
+ unsigned long npc;
+ unsigned long y;
+ unsigned long u_regs[16]; /* globals and ins */
+};
+
+#define UREG_G0 0
+#define UREG_G1 1
+#define UREG_G2 2
+#define UREG_G3 3
+#define UREG_G4 4
+#define UREG_G5 5
+#define UREG_G6 6
+#define UREG_G7 7
+#define UREG_I0 8
+#define UREG_I1 9
+#define UREG_I2 10
+#define UREG_I3 11
+#define UREG_I4 12
+#define UREG_I5 13
+#define UREG_I6 14
+#define UREG_I7 15
+#define UREG_WIM UREG_G0
+#define UREG_FADDR UREG_G0
+#define UREG_FP UREG_I6
+#define UREG_RETPC UREG_I7
+
+static inline bool pt_regs_is_syscall(struct pt_regs *regs)
+{
+ return (regs->psr & PSR_SYSCALL);
+}
+
+static inline bool pt_regs_clear_syscall(struct pt_regs *regs)
+{
+ return (regs->psr &= ~PSR_SYSCALL);
+}
+
+/* A register window */
+struct reg_window {
+ unsigned long locals[8];
+ unsigned long ins[8];
+};
+
+/* A Sparc stack frame */
+struct sparc_stackf {
+ unsigned long locals[8];
+ unsigned long ins[6];
+ struct sparc_stackf *fp;
+ unsigned long callers_pc;
+ char *structptr;
+ unsigned long xargs[6];
+ unsigned long xxargs[1];
+};
+
+#define TRACEREG_SZ sizeof(struct pt_regs)
+#define STACKFRAME_SZ sizeof(struct sparc_stackf)
+
+#ifdef __KERNEL__
+
+#define user_mode(regs) (!((regs)->psr & PSR_PS))
+#define instruction_pointer(regs) ((regs)->pc)
+#define user_stack_pointer(regs) ((regs)->u_regs[UREG_FP])
+unsigned long profile_pc(struct pt_regs *);
+extern void show_regs(struct pt_regs *);
+#endif
+
+#else /* __ASSEMBLY__ */
+/* For assembly code. */
+#define TRACEREG_SZ 0x50
+#define STACKFRAME_SZ 0x60
+#endif
+
+/*
+ * The asm-offsets.h is a generated file, so we cannot include it.
+ * It may be OK for glibc headers, but it's utterly pointless for C code.
+ * The assembly code using those offsets has to include it explicitly.
+ */
+/* #include <asm/asm-offsets.h> */
+
+/* These are for pt_regs. */
+#define PT_PSR 0x0
+#define PT_PC 0x4
+#define PT_NPC 0x8
+#define PT_Y 0xc
+#define PT_G0 0x10
+#define PT_WIM PT_G0
+#define PT_G1 0x14
+#define PT_G2 0x18
+#define PT_G3 0x1c
+#define PT_G4 0x20
+#define PT_G5 0x24
+#define PT_G6 0x28
+#define PT_G7 0x2c
+#define PT_I0 0x30
+#define PT_I1 0x34
+#define PT_I2 0x38
+#define PT_I3 0x3c
+#define PT_I4 0x40
+#define PT_I5 0x44
+#define PT_I6 0x48
+#define PT_FP PT_I6
+#define PT_I7 0x4c
+
+/* Reg_window offsets */
+#define RW_L0 0x00
+#define RW_L1 0x04
+#define RW_L2 0x08
+#define RW_L3 0x0c
+#define RW_L4 0x10
+#define RW_L5 0x14
+#define RW_L6 0x18
+#define RW_L7 0x1c
+#define RW_I0 0x20
+#define RW_I1 0x24
+#define RW_I2 0x28
+#define RW_I3 0x2c
+#define RW_I4 0x30
+#define RW_I5 0x34
+#define RW_I6 0x38
+#define RW_I7 0x3c
+
+/* Stack_frame offsets */
+#define SF_L0 0x00
+#define SF_L1 0x04
+#define SF_L2 0x08
+#define SF_L3 0x0c
+#define SF_L4 0x10
+#define SF_L5 0x14
+#define SF_L6 0x18
+#define SF_L7 0x1c
+#define SF_I0 0x20
+#define SF_I1 0x24
+#define SF_I2 0x28
+#define SF_I3 0x2c
+#define SF_I4 0x30
+#define SF_I5 0x34
+#define SF_FP 0x38
+#define SF_PC 0x3c
+#define SF_RETP 0x40
+#define SF_XARG0 0x44
+#define SF_XARG1 0x48
+#define SF_XARG2 0x4c
+#define SF_XARG3 0x50
+#define SF_XARG4 0x54
+#define SF_XARG5 0x58
+#define SF_XXARG 0x5c
+
+/* Stuff for the ptrace system call */
+#define PTRACE_SPARC_DETACH 11
+#define PTRACE_GETREGS 12
+#define PTRACE_SETREGS 13
+#define PTRACE_GETFPREGS 14
+#define PTRACE_SETFPREGS 15
+#define PTRACE_READDATA 16
+#define PTRACE_WRITEDATA 17
+#define PTRACE_READTEXT 18
+#define PTRACE_WRITETEXT 19
+#define PTRACE_GETFPAREGS 20
+#define PTRACE_SETFPAREGS 21
+
+#endif /* !(_SPARC_PTRACE_H) */
--- /dev/null
+#ifndef _SPARC64_PTRACE_H
+#define _SPARC64_PTRACE_H
+
+#include <asm/pstate.h>
+
+/* This struct defines the way the registers are stored on the
+ * stack during a system call and basically all traps.
+ */
+
+/* This magic value must have the low 9 bits clear,
+ * as that is where we encode the %tt value, see below.
+ */
+#define PT_REGS_MAGIC 0x57ac6c00
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+struct pt_regs {
+ unsigned long u_regs[16]; /* globals and ins */
+ unsigned long tstate;
+ unsigned long tpc;
+ unsigned long tnpc;
+ unsigned int y;
+
+ /* We encode a magic number, PT_REGS_MAGIC, along
+ * with the %tt (trap type) register value at trap
+ * entry time. The magic number allows us to identify
+ * accurately a trap stack frame in the stack
+ * unwinder, and the %tt value allows us to test
+ * things like "in a system call" etc. for an arbitray
+ * process.
+ *
+ * The PT_REGS_MAGIC is choosen such that it can be
+ * loaded completely using just a sethi instruction.
+ */
+ unsigned int magic;
+};
+
+static inline int pt_regs_trap_type(struct pt_regs *regs)
+{
+ return regs->magic & 0x1ff;
+}
+
+static inline bool pt_regs_is_syscall(struct pt_regs *regs)
+{
+ return (regs->tstate & TSTATE_SYSCALL);
+}
+
+static inline bool pt_regs_clear_syscall(struct pt_regs *regs)
+{
+ return (regs->tstate &= ~TSTATE_SYSCALL);
+}
+
+struct pt_regs32 {
+ unsigned int psr;
+ unsigned int pc;
+ unsigned int npc;
+ unsigned int y;
+ unsigned int u_regs[16]; /* globals and ins */
+};
+
+#define UREG_G0 0
+#define UREG_G1 1
+#define UREG_G2 2
+#define UREG_G3 3
+#define UREG_G4 4
+#define UREG_G5 5
+#define UREG_G6 6
+#define UREG_G7 7
+#define UREG_I0 8
+#define UREG_I1 9
+#define UREG_I2 10
+#define UREG_I3 11
+#define UREG_I4 12
+#define UREG_I5 13
+#define UREG_I6 14
+#define UREG_I7 15
+#define UREG_FP UREG_I6
+#define UREG_RETPC UREG_I7
+
+/* A V9 register window */
+struct reg_window {
+ unsigned long locals[8];
+ unsigned long ins[8];
+};
+
+/* A 32-bit register window. */
+struct reg_window32 {
+ unsigned int locals[8];
+ unsigned int ins[8];
+};
+
+/* A V9 Sparc stack frame */
+struct sparc_stackf {
+ unsigned long locals[8];
+ unsigned long ins[6];
+ struct sparc_stackf *fp;
+ unsigned long callers_pc;
+ char *structptr;
+ unsigned long xargs[6];
+ unsigned long xxargs[1];
+};
+
+/* A 32-bit Sparc stack frame */
+struct sparc_stackf32 {
+ unsigned int locals[8];
+ unsigned int ins[6];
+ unsigned int fp;
+ unsigned int callers_pc;
+ unsigned int structptr;
+ unsigned int xargs[6];
+ unsigned int xxargs[1];
+};
+
+struct sparc_trapf {
+ unsigned long locals[8];
+ unsigned long ins[8];
+ unsigned long _unused;
+ struct pt_regs *regs;
+};
+
+#define TRACEREG_SZ sizeof(struct pt_regs)
+#define STACKFRAME_SZ sizeof(struct sparc_stackf)
+
+#define TRACEREG32_SZ sizeof(struct pt_regs32)
+#define STACKFRAME32_SZ sizeof(struct sparc_stackf32)
+
+#ifdef __KERNEL__
+
+struct global_reg_snapshot {
+ unsigned long tstate;
+ unsigned long tpc;
+ unsigned long tnpc;
+ unsigned long o7;
+ unsigned long i7;
+ struct thread_info *thread;
+ unsigned long pad1;
+ unsigned long pad2;
+};
+
+#define __ARCH_WANT_COMPAT_SYS_PTRACE
+
+#define force_successful_syscall_return() \
+do { current_thread_info()->syscall_noerror = 1; \
+} while (0)
+#define user_mode(regs) (!((regs)->tstate & TSTATE_PRIV))
+#define instruction_pointer(regs) ((regs)->tpc)
+#define user_stack_pointer(regs) ((regs)->u_regs[UREG_FP])
+#define regs_return_value(regs) ((regs)->u_regs[UREG_I0])
+#ifdef CONFIG_SMP
+extern unsigned long profile_pc(struct pt_regs *);
+#else
+#define profile_pc(regs) instruction_pointer(regs)
+#endif
+extern void show_regs(struct pt_regs *);
+extern void __show_regs(struct pt_regs *);
+#endif
+
+#else /* __ASSEMBLY__ */
+/* For assembly code. */
+#define TRACEREG_SZ 0xa0
+#define STACKFRAME_SZ 0xc0
+
+#define TRACEREG32_SZ 0x50
+#define STACKFRAME32_SZ 0x60
+#endif
+
+#ifdef __KERNEL__
+#define STACK_BIAS 2047
+#endif
+
+/* These are for pt_regs. */
+#define PT_V9_G0 0x00
+#define PT_V9_G1 0x08
+#define PT_V9_G2 0x10
+#define PT_V9_G3 0x18
+#define PT_V9_G4 0x20
+#define PT_V9_G5 0x28
+#define PT_V9_G6 0x30
+#define PT_V9_G7 0x38
+#define PT_V9_I0 0x40
+#define PT_V9_I1 0x48
+#define PT_V9_I2 0x50
+#define PT_V9_I3 0x58
+#define PT_V9_I4 0x60
+#define PT_V9_I5 0x68
+#define PT_V9_I6 0x70
+#define PT_V9_FP PT_V9_I6
+#define PT_V9_I7 0x78
+#define PT_V9_TSTATE 0x80
+#define PT_V9_TPC 0x88
+#define PT_V9_TNPC 0x90
+#define PT_V9_Y 0x98
+#define PT_V9_MAGIC 0x9c
+#define PT_TSTATE PT_V9_TSTATE
+#define PT_TPC PT_V9_TPC
+#define PT_TNPC PT_V9_TNPC
+
+/* These for pt_regs32. */
+#define PT_PSR 0x0
+#define PT_PC 0x4
+#define PT_NPC 0x8
+#define PT_Y 0xc
+#define PT_G0 0x10
+#define PT_WIM PT_G0
+#define PT_G1 0x14
+#define PT_G2 0x18
+#define PT_G3 0x1c
+#define PT_G4 0x20
+#define PT_G5 0x24
+#define PT_G6 0x28
+#define PT_G7 0x2c
+#define PT_I0 0x30
+#define PT_I1 0x34
+#define PT_I2 0x38
+#define PT_I3 0x3c
+#define PT_I4 0x40
+#define PT_I5 0x44
+#define PT_I6 0x48
+#define PT_FP PT_I6
+#define PT_I7 0x4c
+
+/* Reg_window offsets */
+#define RW_V9_L0 0x00
+#define RW_V9_L1 0x08
+#define RW_V9_L2 0x10
+#define RW_V9_L3 0x18
+#define RW_V9_L4 0x20
+#define RW_V9_L5 0x28
+#define RW_V9_L6 0x30
+#define RW_V9_L7 0x38
+#define RW_V9_I0 0x40
+#define RW_V9_I1 0x48
+#define RW_V9_I2 0x50
+#define RW_V9_I3 0x58
+#define RW_V9_I4 0x60
+#define RW_V9_I5 0x68
+#define RW_V9_I6 0x70
+#define RW_V9_I7 0x78
+
+#define RW_L0 0x00
+#define RW_L1 0x04
+#define RW_L2 0x08
+#define RW_L3 0x0c
+#define RW_L4 0x10
+#define RW_L5 0x14
+#define RW_L6 0x18
+#define RW_L7 0x1c
+#define RW_I0 0x20
+#define RW_I1 0x24
+#define RW_I2 0x28
+#define RW_I3 0x2c
+#define RW_I4 0x30
+#define RW_I5 0x34
+#define RW_I6 0x38
+#define RW_I7 0x3c
+
+/* Stack_frame offsets */
+#define SF_V9_L0 0x00
+#define SF_V9_L1 0x08
+#define SF_V9_L2 0x10
+#define SF_V9_L3 0x18
+#define SF_V9_L4 0x20
+#define SF_V9_L5 0x28
+#define SF_V9_L6 0x30
+#define SF_V9_L7 0x38
+#define SF_V9_I0 0x40
+#define SF_V9_I1 0x48
+#define SF_V9_I2 0x50
+#define SF_V9_I3 0x58
+#define SF_V9_I4 0x60
+#define SF_V9_I5 0x68
+#define SF_V9_FP 0x70
+#define SF_V9_PC 0x78
+#define SF_V9_RETP 0x80
+#define SF_V9_XARG0 0x88
+#define SF_V9_XARG1 0x90
+#define SF_V9_XARG2 0x98
+#define SF_V9_XARG3 0xa0
+#define SF_V9_XARG4 0xa8
+#define SF_V9_XARG5 0xb0
+#define SF_V9_XXARG 0xb8
+
+#define SF_L0 0x00
+#define SF_L1 0x04
+#define SF_L2 0x08
+#define SF_L3 0x0c
+#define SF_L4 0x10
+#define SF_L5 0x14
+#define SF_L6 0x18
+#define SF_L7 0x1c
+#define SF_I0 0x20
+#define SF_I1 0x24
+#define SF_I2 0x28
+#define SF_I3 0x2c
+#define SF_I4 0x30
+#define SF_I5 0x34
+#define SF_FP 0x38
+#define SF_PC 0x3c
+#define SF_RETP 0x40
+#define SF_XARG0 0x44
+#define SF_XARG1 0x48
+#define SF_XARG2 0x4c
+#define SF_XARG3 0x50
+#define SF_XARG4 0x54
+#define SF_XARG5 0x58
+#define SF_XXARG 0x5c
+
+#ifdef __KERNEL__
+
+/* global_reg_snapshot offsets */
+#define GR_SNAP_TSTATE 0x00
+#define GR_SNAP_TPC 0x08
+#define GR_SNAP_TNPC 0x10
+#define GR_SNAP_O7 0x18
+#define GR_SNAP_I7 0x20
+#define GR_SNAP_THREAD 0x28
+#define GR_SNAP_PAD1 0x30
+#define GR_SNAP_PAD2 0x38
+
+#endif /* __KERNEL__ */
+
+/* Stuff for the ptrace system call */
+#define PTRACE_SPARC_DETACH 11
+#define PTRACE_GETREGS 12
+#define PTRACE_SETREGS 13
+#define PTRACE_GETFPREGS 14
+#define PTRACE_SETFPREGS 15
+#define PTRACE_READDATA 16
+#define PTRACE_WRITEDATA 17
+#define PTRACE_READTEXT 18
+#define PTRACE_WRITETEXT 19
+#define PTRACE_GETFPAREGS 20
+#define PTRACE_SETFPAREGS 21
+
+/* There are for debugging 64-bit processes, either from a 32 or 64 bit
+ * parent. Thus their complements are for debugging 32-bit processes only.
+ */
+
+#define PTRACE_GETREGS64 22
+#define PTRACE_SETREGS64 23
+/* PTRACE_SYSCALL is 24 */
+#define PTRACE_GETFPREGS64 25
+#define PTRACE_SETFPREGS64 26
+
+#endif /* !(_SPARC64_PTRACE_H) */
--- /dev/null
+#ifndef _SPARC64_REBOOT_H
+#define _SPARC64_REBOOT_H
+
+extern void machine_alt_power_off(void);
+
+#endif /* _SPARC64_REBOOT_H */
--- /dev/null
+#ifndef ___ASM_SPARC_REG_H
+#define ___ASM_SPARC_REG_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/reg_64.h>
+#else
+#include <asm/reg_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * linux/include/asm/reg.h
+ * Layout of the registers as expected by gdb on the Sparc
+ * we should replace the user.h definitions with those in
+ * this file, we don't even use the other
+ * -miguel
+ *
+ * The names of the structures, constants and aliases in this file
+ * have the same names as the sunos ones, some programs rely on these
+ * names (gdb for example).
+ *
+ */
+
+#ifndef __SPARC_REG_H
+#define __SPARC_REG_H
+
+struct regs {
+ int r_psr;
+#define r_ps r_psr
+ int r_pc;
+ int r_npc;
+ int r_y;
+ int r_g1;
+ int r_g2;
+ int r_g3;
+ int r_g4;
+ int r_g5;
+ int r_g6;
+ int r_g7;
+ int r_o0;
+ int r_o1;
+ int r_o2;
+ int r_o3;
+ int r_o4;
+ int r_o5;
+ int r_o6;
+ int r_o7;
+};
+
+struct fpq {
+ unsigned long *addr;
+ unsigned long instr;
+};
+
+struct fq {
+ union {
+ double whole;
+ struct fpq fpq;
+ } FQu;
+};
+
+#define FPU_REGS_TYPE unsigned int
+#define FPU_FSR_TYPE unsigned
+
+struct fp_status {
+ union {
+ FPU_REGS_TYPE Fpu_regs[32];
+ double Fpu_dregs[16];
+ } fpu_fr;
+ FPU_FSR_TYPE Fpu_fsr;
+ unsigned Fpu_flags;
+ unsigned Fpu_extra;
+ unsigned Fpu_qcnt;
+ struct fq Fpu_q[16];
+};
+
+#define fpu_regs f_fpstatus.fpu_fr.Fpu_regs
+#define fpu_dregs f_fpstatus.fpu_fr.Fpu_dregs
+#define fpu_fsr f_fpstatus.Fpu_fsr
+#define fpu_flags f_fpstatus.Fpu_flags
+#define fpu_extra f_fpstatus.Fpu_extra
+#define fpu_q f_fpstatus.Fpu_q
+#define fpu_qcnt f_fpstatus.Fpu_qcnt
+
+struct fpu {
+ struct fp_status f_fpstatus;
+};
+
+#endif /* __SPARC_REG_H */
--- /dev/null
+/*
+ * linux/asm/reg.h
+ * Layout of the registers as expected by gdb on the Sparc
+ * we should replace the user.h definitions with those in
+ * this file, we don't even use the other
+ * -miguel
+ *
+ * The names of the structures, constants and aliases in this file
+ * have the same names as the sunos ones, some programs rely on these
+ * names (gdb for example).
+ *
+ */
+
+#ifndef __SPARC64_REG_H
+#define __SPARC64_REG_H
+
+struct regs {
+ unsigned long r_g1;
+ unsigned long r_g2;
+ unsigned long r_g3;
+ unsigned long r_g4;
+ unsigned long r_g5;
+ unsigned long r_g6;
+ unsigned long r_g7;
+ unsigned long r_o0;
+ unsigned long r_o1;
+ unsigned long r_o2;
+ unsigned long r_o3;
+ unsigned long r_o4;
+ unsigned long r_o5;
+ unsigned long r_o6;
+ unsigned long r_o7;
+ unsigned long __pad;
+ unsigned long r_tstate;
+ unsigned long r_tpc;
+ unsigned long r_tnpc;
+ unsigned int r_y;
+ unsigned int r_fprs;
+};
+
+#define FPU_REGS_TYPE unsigned int
+#define FPU_FSR_TYPE unsigned long
+
+struct fp_status {
+ unsigned long fpu_fr[32];
+ unsigned long Fpu_fsr;
+};
+
+struct fpu {
+ struct fp_status f_fpstatus;
+};
+
+#define fpu_regs f_fpstatus.fpu_fr
+#define fpu_fsr f_fpstatus.Fpu_fsr
+
+#endif /* __SPARC64_REG_H */
--- /dev/null
+/*
+ * resource.h: Resource definitions.
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_RESOURCE_H
+#define _SPARC_RESOURCE_H
+
+/*
+ * These two resource limit IDs have a Sparc/Linux-specific ordering,
+ * the rest comes from the generic header:
+ */
+#define RLIMIT_NOFILE 6 /* max number of open files */
+#define RLIMIT_NPROC 7 /* max number of processes */
+
+#if defined(__sparc__) && defined(__arch64__)
+/* Use generic version */
+#else
+/*
+ * SuS says limits have to be unsigned.
+ * We make this unsigned, but keep the
+ * old value for compatibility:
+ */
+#define RLIM_INFINITY 0x7fffffff
+#endif
+
+#include <asm-generic/resource.h>
+
+#endif /* !(_SPARC_RESOURCE_H) */
--- /dev/null
+/*
+ * ross.h: Ross module specific definitions and defines.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_ROSS_H
+#define _SPARC_ROSS_H
+
+#include <asm/asi.h>
+#include <asm/page.h>
+
+/* Ross made Hypersparcs have a %psr 'impl' field of '0001'. The 'vers'
+ * field has '1111'.
+ */
+
+/* The MMU control register fields on the HyperSparc.
+ *
+ * -----------------------------------------------------------------
+ * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
+ * -----------------------------------------------------------------
+ * 31 24 23-22 21 20 19 18-15 14 13 12 11 10 9 8 7-2 1 0
+ *
+ * Phew, lots of fields there ;-)
+ *
+ * CWR: Cache Wrapping Enabled, if one cache wrapping is on.
+ * SE: Snoop Enable, turns on bus snooping for cache activity if one.
+ * WBE: Write Buffer Enable, one turns it on.
+ * MID: The ModuleID of the chip for MBus transactions.
+ * BM: Boot-Mode. One indicates the MMU is in boot mode.
+ * C: Indicates whether accesses are cachable while the MMU is
+ * disabled.
+ * CS: Cache Size -- 0 = 128k, 1 = 256k
+ * MR: Memory Reflection, one indicates that the memory bus connected
+ * to the MBus supports memory reflection.
+ * CM: Cache Mode -- 0 = write-through, 1 = copy-back
+ * CE: Cache Enable -- 0 = no caching, 1 = cache is on
+ * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
+ * 1 = faults from supervisor mode do not generate traps
+ * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
+ */
+
+#define HYPERSPARC_CWENABLE 0x00200000
+#define HYPERSPARC_SBENABLE 0x00100000
+#define HYPERSPARC_WBENABLE 0x00080000
+#define HYPERSPARC_MIDMASK 0x00078000
+#define HYPERSPARC_BMODE 0x00004000
+#define HYPERSPARC_ACENABLE 0x00002000
+#define HYPERSPARC_CSIZE 0x00001000
+#define HYPERSPARC_MRFLCT 0x00000800
+#define HYPERSPARC_CMODE 0x00000400
+#define HYPERSPARC_CENABLE 0x00000100
+#define HYPERSPARC_NFAULT 0x00000002
+#define HYPERSPARC_MENABLE 0x00000001
+
+
+/* The ICCR instruction cache register on the HyperSparc.
+ *
+ * -----------------------------------------------
+ * | | FTD | ICE |
+ * -----------------------------------------------
+ * 31 1 0
+ *
+ * This register is accessed using the V8 'wrasr' and 'rdasr'
+ * opcodes, since not all assemblers understand them and those
+ * that do use different semantics I will just hard code the
+ * instruction with a '.word' statement.
+ *
+ * FTD: If set to one flush instructions executed during an
+ * instruction cache hit occurs, the corresponding line
+ * for said cache-hit is invalidated. If FTD is zero,
+ * an unimplemented 'flush' trap will occur when any
+ * flush is executed by the processor.
+ *
+ * ICE: If set to one, the instruction cache is enabled. If
+ * zero, the cache will not be used for instruction fetches.
+ *
+ * All other bits are read as zeros, and writes to them have no
+ * effect.
+ *
+ * Wheee, not many assemblers understand the %iccr register nor
+ * the generic asr r/w instructions.
+ *
+ * 1000 0011 0100 0111 1100 0000 0000 0000 ! rd %iccr, %g1
+ *
+ * 0x 8 3 4 7 c 0 0 0 ! 0x8347c000
+ *
+ * 1011 1111 1000 0000 0110 0000 0000 0000 ! wr %g1, 0x0, %iccr
+ *
+ * 0x b f 8 0 6 0 0 0 ! 0xbf806000
+ *
+ */
+
+#define HYPERSPARC_ICCR_FTD 0x00000002
+#define HYPERSPARC_ICCR_ICE 0x00000001
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned int get_ross_icr(void)
+{
+ unsigned int icreg;
+
+ __asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */
+ "mov %%g1, %0\n\t"
+ : "=r" (icreg)
+ : /* no inputs */
+ : "g1", "memory");
+
+ return icreg;
+}
+
+static inline void put_ross_icr(unsigned int icreg)
+{
+ __asm__ __volatile__("or %%g0, %0, %%g1\n\t"
+ ".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ : /* no outputs */
+ : "r" (icreg)
+ : "g1", "memory");
+
+ return;
+}
+
+/* HyperSparc specific cache flushing. */
+
+/* This is for the on-chip instruction cache. */
+static inline void hyper_flush_whole_icache(void)
+{
+ __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
+ : /* no outputs */
+ : "i" (ASI_M_FLUSH_IWHOLE)
+ : "memory");
+ return;
+}
+
+extern int vac_cache_size;
+extern int vac_line_size;
+
+static inline void hyper_clear_all_tags(void)
+{
+ unsigned long addr;
+
+ for(addr = 0; addr < vac_cache_size; addr += vac_line_size)
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" (addr), "i" (ASI_M_DATAC_TAG)
+ : "memory");
+}
+
+static inline void hyper_flush_unconditional_combined(void)
+{
+ unsigned long addr;
+
+ for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" (addr), "i" (ASI_M_FLUSH_CTX)
+ : "memory");
+}
+
+static inline void hyper_flush_cache_user(void)
+{
+ unsigned long addr;
+
+ for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" (addr), "i" (ASI_M_FLUSH_USER)
+ : "memory");
+}
+
+static inline void hyper_flush_cache_page(unsigned long page)
+{
+ unsigned long end;
+
+ page &= PAGE_MASK;
+ end = page + PAGE_SIZE;
+ while (page < end) {
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" (page), "i" (ASI_M_FLUSH_PAGE)
+ : "memory");
+ page += vac_line_size;
+ }
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC_ROSS_H) */
--- /dev/null
+/*
+ * rtc.h: Definitions for access to the Mostek real time clock
+ *
+ * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
+ */
+
+#ifndef _RTC_H
+#define _RTC_H
+
+#include <linux/ioctl.h>
+
+struct rtc_time
+{
+ int sec; /* Seconds (0-59) */
+ int min; /* Minutes (0-59) */
+ int hour; /* Hour (0-23) */
+ int dow; /* Day of the week (1-7) */
+ int dom; /* Day of the month (1-31) */
+ int month; /* Month of year (1-12) */
+ int year; /* Year (0-99) */
+};
+
+#define RTCGET _IOR('p', 20, struct rtc_time)
+#define RTCSET _IOW('p', 21, struct rtc_time)
+
+#endif
--- /dev/null
+/* rwsem-const.h: RW semaphore counter constants. */
+#ifndef _SPARC64_RWSEM_CONST_H
+#define _SPARC64_RWSEM_CONST_H
+
+#define RWSEM_UNLOCKED_VALUE 0x00000000
+#define RWSEM_ACTIVE_BIAS 0x00000001
+#define RWSEM_ACTIVE_MASK 0x0000ffff
+#define RWSEM_WAITING_BIAS 0xffff0000
+#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
+#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
+
+#endif /* _SPARC64_RWSEM_CONST_H */
--- /dev/null
+/*
+ * rwsem.h: R/W semaphores implemented using CAS
+ *
+ * Written by David S. Miller (davem@redhat.com), 2001.
+ * Derived from asm-i386/rwsem.h
+ */
+#ifndef _SPARC64_RWSEM_H
+#define _SPARC64_RWSEM_H
+
+#ifndef _LINUX_RWSEM_H
+#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
+#endif
+
+#ifdef __KERNEL__
+
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <asm/rwsem-const.h>
+
+struct rwsem_waiter;
+
+struct rw_semaphore {
+ signed int count;
+ spinlock_t wait_lock;
+ struct list_head wait_list;
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+ struct lockdep_map dep_map;
+#endif
+};
+
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
+#else
+# define __RWSEM_DEP_MAP_INIT(lockname)
+#endif
+
+#define __RWSEM_INITIALIZER(name) \
+{ RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) \
+ __RWSEM_DEP_MAP_INIT(name) }
+
+#define DECLARE_RWSEM(name) \
+ struct rw_semaphore name = __RWSEM_INITIALIZER(name)
+
+extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
+ struct lock_class_key *key);
+
+#define init_rwsem(sem) \
+do { \
+ static struct lock_class_key __key; \
+ \
+ __init_rwsem((sem), #sem, &__key); \
+} while (0)
+
+extern void __down_read(struct rw_semaphore *sem);
+extern int __down_read_trylock(struct rw_semaphore *sem);
+extern void __down_write(struct rw_semaphore *sem);
+extern int __down_write_trylock(struct rw_semaphore *sem);
+extern void __up_read(struct rw_semaphore *sem);
+extern void __up_write(struct rw_semaphore *sem);
+extern void __downgrade_write(struct rw_semaphore *sem);
+
+static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
+{
+ __down_write(sem);
+}
+
+static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
+{
+ return atomic_add_return(delta, (atomic_t *)(&sem->count));
+}
+
+static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
+{
+ atomic_add(delta, (atomic_t *)(&sem->count));
+}
+
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+ return (sem->count != 0);
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _SPARC64_RWSEM_H */
--- /dev/null
+/*
+ * sbi.h: SBI (Sbus Interface on sun4d) definitions
+ *
+ * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
+ */
+
+#ifndef _SPARC_SBI_H
+#define _SPARC_SBI_H
+
+#include <asm/obio.h>
+
+/* SBI */
+struct sbi_regs {
+/* 0x0000 */ u32 cid; /* Component ID */
+/* 0x0004 */ u32 ctl; /* Control */
+/* 0x0008 */ u32 status; /* Status */
+ u32 _unused1;
+
+/* 0x0010 */ u32 cfg0; /* Slot0 config reg */
+/* 0x0014 */ u32 cfg1; /* Slot1 config reg */
+/* 0x0018 */ u32 cfg2; /* Slot2 config reg */
+/* 0x001c */ u32 cfg3; /* Slot3 config reg */
+
+/* 0x0020 */ u32 stb0; /* Streaming buf control for slot 0 */
+/* 0x0024 */ u32 stb1; /* Streaming buf control for slot 1 */
+/* 0x0028 */ u32 stb2; /* Streaming buf control for slot 2 */
+/* 0x002c */ u32 stb3; /* Streaming buf control for slot 3 */
+
+/* 0x0030 */ u32 intr_state; /* Interrupt state */
+/* 0x0034 */ u32 intr_tid; /* Interrupt target ID */
+/* 0x0038 */ u32 intr_diag; /* Interrupt diagnostics */
+};
+
+#define SBI_CID 0x02800000
+#define SBI_CTL 0x02800004
+#define SBI_STATUS 0x02800008
+#define SBI_CFG0 0x02800010
+#define SBI_CFG1 0x02800014
+#define SBI_CFG2 0x02800018
+#define SBI_CFG3 0x0280001c
+#define SBI_STB0 0x02800020
+#define SBI_STB1 0x02800024
+#define SBI_STB2 0x02800028
+#define SBI_STB3 0x0280002c
+#define SBI_INTR_STATE 0x02800030
+#define SBI_INTR_TID 0x02800034
+#define SBI_INTR_DIAG 0x02800038
+
+/* Burst bits for 8, 16, 32, 64 are in cfgX registers at bits 2, 3, 4, 5 respectively */
+#define SBI_CFG_BURST_MASK 0x0000001e
+
+/* How to make devid from sbi no */
+#define SBI2DEVID(sbino) ((sbino<<4)|2)
+
+/* intr_state has 4 bits for slots 0 .. 3 and these bits are repeated for each sbus irq level
+ *
+ * +-------+-------+-------+-------+-------+-------+-------+-------+
+ * SBUS IRQ LEVEL | 7 | 6 | 5 | 4 | 3 | 2 | 1 | |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Reser |
+ * SLOT # |3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0| ved |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------+
+ * Bits 31 27 23 19 15 11 7 3 0
+ */
+
+
+#ifndef __ASSEMBLY__
+
+static inline int acquire_sbi(int devid, int mask)
+{
+ __asm__ __volatile__ ("swapa [%2] %3, %0" :
+ "=r" (mask) :
+ "0" (mask),
+ "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
+ "i" (ASI_M_CTL));
+ return mask;
+}
+
+static inline void release_sbi(int devid, int mask)
+{
+ __asm__ __volatile__ ("sta %0, [%1] %2" : :
+ "r" (mask),
+ "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
+ "i" (ASI_M_CTL));
+}
+
+static inline void set_sbi_tid(int devid, int targetid)
+{
+ __asm__ __volatile__ ("sta %0, [%1] %2" : :
+ "r" (targetid),
+ "r" (ECSR_DEV_BASE(devid) | SBI_INTR_TID),
+ "i" (ASI_M_CTL));
+}
+
+static inline int get_sbi_ctl(int devid, int cfgno)
+{
+ int cfg;
+
+ __asm__ __volatile__ ("lda [%1] %2, %0" :
+ "=r" (cfg) :
+ "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
+ "i" (ASI_M_CTL));
+ return cfg;
+}
+
+static inline void set_sbi_ctl(int devid, int cfgno, int cfg)
+{
+ __asm__ __volatile__ ("sta %0, [%1] %2" : :
+ "r" (cfg),
+ "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
+ "i" (ASI_M_CTL));
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* !(_SPARC_SBI_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_SBUS_H
+#define ___ASM_SPARC_SBUS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/sbus_64.h>
+#else
+#include <asm/sbus_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * sbus.h: Defines for the Sun SBus.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_SBUS_H
+#define _SPARC_SBUS_H
+
+#include <linux/dma-mapping.h>
+#include <linux/ioport.h>
+
+#include <asm/oplib.h>
+#include <asm/prom.h>
+#include <asm/of_device.h>
+#include <asm/scatterlist.h>
+
+/* We scan which devices are on the SBus using the PROM node device
+ * tree. SBus devices are described in two different ways. You can
+ * either get an absolute address at which to access the device, or
+ * you can get a SBus 'slot' number and an offset within that slot.
+ */
+
+/* The base address at which to calculate device OBIO addresses. */
+#define SUN_SBUS_BVADDR 0xf8000000
+#define SBUS_OFF_MASK 0x01ffffff
+
+/* These routines are used to calculate device address from slot
+ * numbers + offsets, and vice versa.
+ */
+
+static inline unsigned long sbus_devaddr(int slotnum, unsigned long offset)
+{
+ return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<25)+(offset));
+}
+
+static inline int sbus_dev_slot(unsigned long dev_addr)
+{
+ return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>25);
+}
+
+struct sbus_bus;
+
+/* Linux SBUS device tables */
+struct sbus_dev {
+ struct of_device ofdev;
+ struct sbus_bus *bus;
+ struct sbus_dev *next;
+ struct sbus_dev *child;
+ struct sbus_dev *parent;
+ int prom_node;
+ char prom_name[64];
+ int slot;
+
+ struct resource resource[PROMREG_MAX];
+
+ struct linux_prom_registers reg_addrs[PROMREG_MAX];
+ int num_registers;
+
+ struct linux_prom_ranges device_ranges[PROMREG_MAX];
+ int num_device_ranges;
+
+ unsigned int irqs[4];
+ int num_irqs;
+};
+#define to_sbus_device(d) container_of(d, struct sbus_dev, ofdev.dev)
+
+/* This struct describes the SBus(s) found on this machine. */
+struct sbus_bus {
+ struct of_device ofdev;
+ struct sbus_dev *devices; /* Link to devices on this SBus */
+ struct sbus_bus *next; /* next SBus, if more than one SBus */
+ int prom_node; /* PROM device tree node for this SBus */
+ char prom_name[64]; /* Usually "sbus" or "sbi" */
+ int clock_freq;
+
+ struct linux_prom_ranges sbus_ranges[PROMREG_MAX];
+ int num_sbus_ranges;
+
+ int devid;
+ int board;
+};
+#define to_sbus(d) container_of(d, struct sbus_bus, ofdev.dev)
+
+extern struct sbus_bus *sbus_root;
+
+static inline int
+sbus_is_slave(struct sbus_dev *dev)
+{
+ /* XXX Have to write this for sun4c's */
+ return 0;
+}
+
+/* Device probing routines could find these handy */
+#define for_each_sbus(bus) \
+ for((bus) = sbus_root; (bus); (bus)=(bus)->next)
+
+#define for_each_sbusdev(device, bus) \
+ for((device) = (bus)->devices; (device); (device)=(device)->next)
+
+#define for_all_sbusdev(device, bus) \
+ for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \
+ for ((device) = (bus)->devices; (device); (device) = (device)->next)
+
+/* Driver DVMA interfaces. */
+#define sbus_can_dma_64bit(sdev) (0) /* actually, sparc_cpu_model==sun4d */
+#define sbus_can_burst64(sdev) (0) /* actually, sparc_cpu_model==sun4d */
+extern void sbus_set_sbus64(struct sbus_dev *, int);
+extern void sbus_fill_device_irq(struct sbus_dev *);
+
+/* These yield IOMMU mappings in consistent mode. */
+extern void *sbus_alloc_consistent(struct sbus_dev *, long, u32 *dma_addrp);
+extern void sbus_free_consistent(struct sbus_dev *, long, void *, u32);
+void prom_adjust_ranges(struct linux_prom_ranges *, int,
+ struct linux_prom_ranges *, int);
+
+#define SBUS_DMA_BIDIRECTIONAL DMA_BIDIRECTIONAL
+#define SBUS_DMA_TODEVICE DMA_TO_DEVICE
+#define SBUS_DMA_FROMDEVICE DMA_FROM_DEVICE
+#define SBUS_DMA_NONE DMA_NONE
+
+/* All the rest use streaming mode mappings. */
+extern dma_addr_t sbus_map_single(struct sbus_dev *, void *, size_t, int);
+extern void sbus_unmap_single(struct sbus_dev *, dma_addr_t, size_t, int);
+extern int sbus_map_sg(struct sbus_dev *, struct scatterlist *, int, int);
+extern void sbus_unmap_sg(struct sbus_dev *, struct scatterlist *, int, int);
+
+/* Finally, allow explicit synchronization of streamable mappings. */
+extern void sbus_dma_sync_single_for_cpu(struct sbus_dev *, dma_addr_t, size_t, int);
+#define sbus_dma_sync_single sbus_dma_sync_single_for_cpu
+extern void sbus_dma_sync_single_for_device(struct sbus_dev *, dma_addr_t, size_t, int);
+extern void sbus_dma_sync_sg_for_cpu(struct sbus_dev *, struct scatterlist *, int, int);
+#define sbus_dma_sync_sg sbus_dma_sync_sg_for_cpu
+extern void sbus_dma_sync_sg_for_device(struct sbus_dev *, struct scatterlist *, int, int);
+
+/* Eric Brower (ebrower@usa.net)
+ * Translate SBus interrupt levels to ino values--
+ * this is used when converting sbus "interrupts" OBP
+ * node values to "intr" node values, and is platform
+ * dependent. If only we could call OBP with
+ * "sbus-intr>cpu (sbint -- ino)" from kernel...
+ * See .../drivers/sbus/sbus.c for details.
+ */
+BTFIXUPDEF_CALL(unsigned int, sbint_to_irq, struct sbus_dev *sdev, unsigned int)
+#define sbint_to_irq(sdev, sbint) BTFIXUP_CALL(sbint_to_irq)(sdev, sbint)
+
+extern void sbus_arch_bus_ranges_init(struct device_node *, struct sbus_bus *);
+extern void sbus_setup_iommu(struct sbus_bus *, struct device_node *);
+extern void sbus_setup_arch_props(struct sbus_bus *, struct device_node *);
+extern int sbus_arch_preinit(void);
+extern void sbus_arch_postinit(void);
+
+#endif /* !(_SPARC_SBUS_H) */
--- /dev/null
+/* sbus.h: Defines for the Sun SBus.
+ *
+ * Copyright (C) 1996, 1999, 2007 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC64_SBUS_H
+#define _SPARC64_SBUS_H
+
+#include <linux/dma-mapping.h>
+#include <linux/ioport.h>
+
+#include <asm/oplib.h>
+#include <asm/prom.h>
+#include <asm/of_device.h>
+#include <asm/iommu.h>
+#include <asm/scatterlist.h>
+
+/* We scan which devices are on the SBus using the PROM node device
+ * tree. SBus devices are described in two different ways. You can
+ * either get an absolute address at which to access the device, or
+ * you can get a SBus 'slot' number and an offset within that slot.
+ */
+
+/* The base address at which to calculate device OBIO addresses. */
+#define SUN_SBUS_BVADDR 0x00000000
+#define SBUS_OFF_MASK 0x0fffffff
+
+/* These routines are used to calculate device address from slot
+ * numbers + offsets, and vice versa.
+ */
+
+static inline unsigned long sbus_devaddr(int slotnum, unsigned long offset)
+{
+ return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<28)+(offset));
+}
+
+static inline int sbus_dev_slot(unsigned long dev_addr)
+{
+ return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>28);
+}
+
+struct sbus_bus;
+
+/* Linux SBUS device tables */
+struct sbus_dev {
+ struct of_device ofdev;
+ struct sbus_bus *bus;
+ struct sbus_dev *next;
+ struct sbus_dev *child;
+ struct sbus_dev *parent;
+ int prom_node;
+ char prom_name[64];
+ int slot;
+
+ struct resource resource[PROMREG_MAX];
+
+ struct linux_prom_registers reg_addrs[PROMREG_MAX];
+ int num_registers;
+
+ struct linux_prom_ranges device_ranges[PROMREG_MAX];
+ int num_device_ranges;
+
+ unsigned int irqs[4];
+ int num_irqs;
+};
+#define to_sbus_device(d) container_of(d, struct sbus_dev, ofdev.dev)
+
+/* This struct describes the SBus(s) found on this machine. */
+struct sbus_bus {
+ struct of_device ofdev;
+ struct sbus_dev *devices; /* Tree of SBUS devices */
+ struct sbus_bus *next; /* Next SBUS in system */
+ int prom_node; /* OBP node of SBUS */
+ char prom_name[64]; /* Usually "sbus" or "sbi" */
+ int clock_freq;
+
+ struct linux_prom_ranges sbus_ranges[PROMREG_MAX];
+ int num_sbus_ranges;
+
+ int portid;
+};
+#define to_sbus(d) container_of(d, struct sbus_bus, ofdev.dev)
+
+extern struct sbus_bus *sbus_root;
+
+/* Device probing routines could find these handy */
+#define for_each_sbus(bus) \
+ for((bus) = sbus_root; (bus); (bus)=(bus)->next)
+
+#define for_each_sbusdev(device, bus) \
+ for((device) = (bus)->devices; (device); (device)=(device)->next)
+
+#define for_all_sbusdev(device, bus) \
+ for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \
+ for ((device) = (bus)->devices; (device); (device) = (device)->next)
+
+/* Driver DVMA interfaces. */
+#define sbus_can_dma_64bit(sdev) (1)
+#define sbus_can_burst64(sdev) (1)
+extern void sbus_set_sbus64(struct sbus_dev *, int);
+extern void sbus_fill_device_irq(struct sbus_dev *);
+
+static inline void *sbus_alloc_consistent(struct sbus_dev *sdev , size_t size,
+ dma_addr_t *dma_handle)
+{
+ return dma_alloc_coherent(&sdev->ofdev.dev, size,
+ dma_handle, GFP_ATOMIC);
+}
+
+static inline void sbus_free_consistent(struct sbus_dev *sdev, size_t size,
+ void *vaddr, dma_addr_t dma_handle)
+{
+ return dma_free_coherent(&sdev->ofdev.dev, size, vaddr, dma_handle);
+}
+
+#define SBUS_DMA_BIDIRECTIONAL DMA_BIDIRECTIONAL
+#define SBUS_DMA_TODEVICE DMA_TO_DEVICE
+#define SBUS_DMA_FROMDEVICE DMA_FROM_DEVICE
+#define SBUS_DMA_NONE DMA_NONE
+
+/* All the rest use streaming mode mappings. */
+static inline dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr,
+ size_t size, int direction)
+{
+ return dma_map_single(&sdev->ofdev.dev, ptr, size,
+ (enum dma_data_direction) direction);
+}
+
+static inline void sbus_unmap_single(struct sbus_dev *sdev,
+ dma_addr_t dma_addr, size_t size,
+ int direction)
+{
+ dma_unmap_single(&sdev->ofdev.dev, dma_addr, size,
+ (enum dma_data_direction) direction);
+}
+
+static inline int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg,
+ int nents, int direction)
+{
+ return dma_map_sg(&sdev->ofdev.dev, sg, nents,
+ (enum dma_data_direction) direction);
+}
+
+static inline void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg,
+ int nents, int direction)
+{
+ dma_unmap_sg(&sdev->ofdev.dev, sg, nents,
+ (enum dma_data_direction) direction);
+}
+
+/* Finally, allow explicit synchronization of streamable mappings. */
+static inline void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev,
+ dma_addr_t dma_handle,
+ size_t size, int direction)
+{
+ dma_sync_single_for_cpu(&sdev->ofdev.dev, dma_handle, size,
+ (enum dma_data_direction) direction);
+}
+#define sbus_dma_sync_single sbus_dma_sync_single_for_cpu
+
+static inline void sbus_dma_sync_single_for_device(struct sbus_dev *sdev,
+ dma_addr_t dma_handle,
+ size_t size, int direction)
+{
+ /* No flushing needed to sync cpu writes to the device. */
+}
+
+static inline void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev,
+ struct scatterlist *sg,
+ int nents, int direction)
+{
+ dma_sync_sg_for_cpu(&sdev->ofdev.dev, sg, nents,
+ (enum dma_data_direction) direction);
+}
+#define sbus_dma_sync_sg sbus_dma_sync_sg_for_cpu
+
+static inline void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev,
+ struct scatterlist *sg,
+ int nents, int direction)
+{
+ /* No flushing needed to sync cpu writes to the device. */
+}
+
+extern void sbus_arch_bus_ranges_init(struct device_node *, struct sbus_bus *);
+extern void sbus_setup_iommu(struct sbus_bus *, struct device_node *);
+extern void sbus_setup_arch_props(struct sbus_bus *, struct device_node *);
+extern int sbus_arch_preinit(void);
+extern void sbus_arch_postinit(void);
+
+#endif /* !(_SPARC64_SBUS_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_SCATTERLIST_H
+#define ___ASM_SPARC_SCATTERLIST_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/scatterlist_64.h>
+#else
+#include <asm/scatterlist_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _SPARC_SCATTERLIST_H
+#define _SPARC_SCATTERLIST_H
+
+#include <linux/types.h>
+
+struct scatterlist {
+#ifdef CONFIG_DEBUG_SG
+ unsigned long sg_magic;
+#endif
+ unsigned long page_link;
+ unsigned int offset;
+
+ unsigned int length;
+
+ __u32 dvma_address; /* A place to hang host-specific addresses at. */
+ __u32 dvma_length;
+};
+
+#define sg_dma_address(sg) ((sg)->dvma_address)
+#define sg_dma_len(sg) ((sg)->dvma_length)
+
+#define ISA_DMA_THRESHOLD (~0UL)
+
+#define ARCH_HAS_SG_CHAIN
+
+#endif /* !(_SPARC_SCATTERLIST_H) */
--- /dev/null
+#ifndef _SPARC64_SCATTERLIST_H
+#define _SPARC64_SCATTERLIST_H
+
+#include <asm/page.h>
+#include <asm/types.h>
+
+struct scatterlist {
+#ifdef CONFIG_DEBUG_SG
+ unsigned long sg_magic;
+#endif
+ unsigned long page_link;
+ unsigned int offset;
+
+ unsigned int length;
+
+ dma_addr_t dma_address;
+ __u32 dma_length;
+};
+
+#define sg_dma_address(sg) ((sg)->dma_address)
+#define sg_dma_len(sg) ((sg)->dma_length)
+
+#define ISA_DMA_THRESHOLD (~0UL)
+
+#define ARCH_HAS_SG_CHAIN
+
+#endif /* !(_SPARC64_SCATTERLIST_H) */
--- /dev/null
+#ifndef _SPARC64_SCRATCHPAD_H
+#define _SPARC64_SCRATCHPAD_H
+
+/* Sun4v scratchpad registers, accessed via ASI_SCRATCHPAD. */
+
+#define SCRATCHPAD_MMU_MISS 0x00 /* Shared with OBP - set by OBP */
+#define SCRATCHPAD_CPUID 0x08 /* Shared with OBP - set by hypervisor */
+#define SCRATCHPAD_UTSBREG1 0x10
+#define SCRATCHPAD_UTSBREG2 0x18
+ /* 0x20 and 0x28, hypervisor only... */
+#define SCRATCHPAD_UNUSED1 0x30
+#define SCRATCHPAD_UNUSED2 0x38 /* Reserved for OBP */
+
+#endif /* !(_SPARC64_SCRATCHPAD_H) */
--- /dev/null
+#ifndef _ASM_SECCOMP_H
+
+#include <linux/thread_info.h> /* already defines TIF_32BIT */
+
+#ifndef TIF_32BIT
+#error "unexpected TIF_32BIT on sparc64"
+#endif
+
+#include <linux/unistd.h>
+
+#define __NR_seccomp_read __NR_read
+#define __NR_seccomp_write __NR_write
+#define __NR_seccomp_exit __NR_exit
+#define __NR_seccomp_sigreturn __NR_rt_sigreturn
+
+#define __NR_seccomp_read_32 __NR_read
+#define __NR_seccomp_write_32 __NR_write
+#define __NR_seccomp_exit_32 __NR_exit
+#define __NR_seccomp_sigreturn_32 __NR_sigreturn
+
+#endif /* _ASM_SECCOMP_H */
--- /dev/null
+#ifndef ___ASM_SPARC_SECTIONS_H
+#define ___ASM_SPARC_SECTIONS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/sections_64.h>
+#else
+#include <asm/sections_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _SPARC_SECTIONS_H
+#define _SPARC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
--- /dev/null
+#ifndef _SPARC64_SECTIONS_H
+#define _SPARC64_SECTIONS_H
+
+/* nothing to see, move along */
+#include <asm-generic/sections.h>
+
+extern char _start[];
+
+#endif
--- /dev/null
+#ifndef _SPARC_SEMBUF_H
+#define _SPARC_SEMBUF_H
+
+/*
+ * The semid64_ds structure for sparc architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+#if defined(__sparc__) && defined(__arch64__)
+# define PADDING(x)
+#else
+# define PADDING(x) unsigned int x;
+#endif
+
+struct semid64_ds {
+ struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
+ PADDING(__pad1)
+ __kernel_time_t sem_otime; /* last semop time */
+ PADDING(__pad2)
+ __kernel_time_t sem_ctime; /* last change time */
+ unsigned long sem_nsems; /* no. of semaphores in array */
+ unsigned long __unused1;
+ unsigned long __unused2;
+};
+#undef PADDING
+
+#endif /* _SPARC64_SEMBUF_H */
--- /dev/null
+/*
+ * Just a place holder.
+ */
+
+#ifndef _SPARC_SETUP_H
+#define _SPARC_SETUP_H
+
+#if defined(__sparc__) && defined(__arch64__)
+# define COMMAND_LINE_SIZE 2048
+#else
+# define COMMAND_LINE_SIZE 256
+#endif
+
+#endif /* _SPARC_SETUP_H */
--- /dev/null
+#ifndef _SPARC64_SFAFSR_H
+#define _SPARC64_SFAFSR_H
+
+#include <linux/const.h>
+
+/* Spitfire Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
+
+#define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT)
+#define SFAFSR_ME_SHIFT 32
+#define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT)
+#define SFAFSR_PRIV_SHIFT 31
+#define SFAFSR_ISAP (_AC(1,UL) << SFAFSR_ISAP_SHIFT)
+#define SFAFSR_ISAP_SHIFT 30
+#define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT)
+#define SFAFSR_ETP_SHIFT 29
+#define SFAFSR_IVUE (_AC(1,UL) << SFAFSR_IVUE_SHIFT)
+#define SFAFSR_IVUE_SHIFT 28
+#define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT)
+#define SFAFSR_TO_SHIFT 27
+#define SFAFSR_BERR (_AC(1,UL) << SFAFSR_BERR_SHIFT)
+#define SFAFSR_BERR_SHIFT 26
+#define SFAFSR_LDP (_AC(1,UL) << SFAFSR_LDP_SHIFT)
+#define SFAFSR_LDP_SHIFT 25
+#define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT)
+#define SFAFSR_CP_SHIFT 24
+#define SFAFSR_WP (_AC(1,UL) << SFAFSR_WP_SHIFT)
+#define SFAFSR_WP_SHIFT 23
+#define SFAFSR_EDP (_AC(1,UL) << SFAFSR_EDP_SHIFT)
+#define SFAFSR_EDP_SHIFT 22
+#define SFAFSR_UE (_AC(1,UL) << SFAFSR_UE_SHIFT)
+#define SFAFSR_UE_SHIFT 21
+#define SFAFSR_CE (_AC(1,UL) << SFAFSR_CE_SHIFT)
+#define SFAFSR_CE_SHIFT 20
+#define SFAFSR_ETS (_AC(0xf,UL) << SFAFSR_ETS_SHIFT)
+#define SFAFSR_ETS_SHIFT 16
+#define SFAFSR_PSYND (_AC(0xffff,UL) << SFAFSR_PSYND_SHIFT)
+#define SFAFSR_PSYND_SHIFT 0
+
+/* UDB Error Register, ASI=0x7f VA<63:0>=0x0(High),0x18(Low) for read
+ * ASI=0x77 VA<63:0>=0x0(High),0x18(Low) for write
+ */
+
+#define UDBE_UE (_AC(1,UL) << 9)
+#define UDBE_CE (_AC(1,UL) << 8)
+#define UDBE_E_SYNDR (_AC(0xff,UL) << 0)
+
+/* The trap handlers for asynchronous errors encode the AFSR and
+ * other pieces of information into a 64-bit argument for C code
+ * encoded as follows:
+ *
+ * -----------------------------------------------
+ * | UDB_H | UDB_L | TL>1 | TT | AFSR |
+ * -----------------------------------------------
+ * 63 54 53 44 42 41 33 32 0
+ *
+ * The AFAR is passed in unchanged.
+ */
+#define SFSTAT_UDBH_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
+#define SFSTAT_UDBH_SHIFT 54
+#define SFSTAT_UDBL_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
+#define SFSTAT_UDBL_SHIFT 44
+#define SFSTAT_TL_GT_ONE (_AC(1,UL) << SFSTAT_TL_GT_ONE_SHIFT)
+#define SFSTAT_TL_GT_ONE_SHIFT 42
+#define SFSTAT_TRAP_TYPE (_AC(0x1FF,UL) << SFSTAT_TRAP_TYPE_SHIFT)
+#define SFSTAT_TRAP_TYPE_SHIFT 33
+#define SFSTAT_AFSR_MASK (_AC(0x1ffffffff,UL) << SFSTAT_AFSR_SHIFT)
+#define SFSTAT_AFSR_SHIFT 0
+
+/* ESTATE Error Enable Register, ASI=0x4b VA<63:0>=0x0 */
+#define ESTATE_ERR_CE 0x1 /* Correctable errors */
+#define ESTATE_ERR_NCE 0x2 /* TO, BERR, LDP, ETP, EDP, WP, UE, IVUE */
+#define ESTATE_ERR_ISAP 0x4 /* System address parity error */
+#define ESTATE_ERR_ALL (ESTATE_ERR_CE | \
+ ESTATE_ERR_NCE | \
+ ESTATE_ERR_ISAP)
+
+/* The various trap types that report using the above state. */
+#define TRAP_TYPE_IAE 0x09 /* Instruction Access Error */
+#define TRAP_TYPE_DAE 0x32 /* Data Access Error */
+#define TRAP_TYPE_CEE 0x63 /* Correctable ECC Error */
+
+#endif /* _SPARC64_SFAFSR_H */
--- /dev/null
+#ifndef ___ASM_SPARC_SFP_MACHINE_H
+#define ___ASM_SPARC_SFP_MACHINE_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/sfp-machine_64.h>
+#else
+#include <asm/sfp-machine_32.h>
+#endif
+#endif
--- /dev/null
+/* Machine-dependent software floating-point definitions.
+ Sparc userland (_Q_*) version.
+ Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by Richard Henderson (rth@cygnus.com),
+ Jakub Jelinek (jj@ultra.linux.cz),
+ David S. Miller (davem@redhat.com) and
+ Peter Maydell (pmaydell@chiark.greenend.org.uk).
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Library General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Library General Public License for more details.
+
+ You should have received a copy of the GNU Library General Public
+ License along with the GNU C Library; see the file COPYING.LIB. If
+ not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef _SFP_MACHINE_H
+#define _SFP_MACHINE_H
+
+
+#define _FP_W_TYPE_SIZE 32
+#define _FP_W_TYPE unsigned long
+#define _FP_WS_TYPE signed long
+#define _FP_I_TYPE long
+
+#define _FP_MUL_MEAT_S(R,X,Y) \
+ _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_D(R,X,Y) \
+ _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_Q(R,X,Y) \
+ _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv(S,R,X,Y)
+#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
+#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
+#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
+#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
+#define _FP_NANSIGN_S 0
+#define _FP_NANSIGN_D 0
+#define _FP_NANSIGN_Q 0
+
+#define _FP_KEEPNANFRACP 1
+
+/* If one NaN is signaling and the other is not,
+ * we choose that one, otherwise we choose X.
+ */
+/* For _Qp_* and _Q_*, this should prefer X, for
+ * CPU instruction emulation this should prefer Y.
+ * (see SPAMv9 B.2.2 section).
+ */
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
+ do { \
+ if ((_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs) \
+ && !(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)) \
+ { \
+ R##_s = X##_s; \
+ _FP_FRAC_COPY_##wc(R,X); \
+ } \
+ else \
+ { \
+ R##_s = Y##_s; \
+ _FP_FRAC_COPY_##wc(R,Y); \
+ } \
+ R##_c = FP_CLS_NAN; \
+ } while (0)
+
+/* Some assembly to speed things up. */
+#define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
+ __asm__ ("addcc %r7,%8,%2\n\t" \
+ "addxcc %r5,%6,%1\n\t" \
+ "addx %r3,%4,%0\n" \
+ : "=r" ((USItype)(r2)), \
+ "=&r" ((USItype)(r1)), \
+ "=&r" ((USItype)(r0)) \
+ : "%rJ" ((USItype)(x2)), \
+ "rI" ((USItype)(y2)), \
+ "%rJ" ((USItype)(x1)), \
+ "rI" ((USItype)(y1)), \
+ "%rJ" ((USItype)(x0)), \
+ "rI" ((USItype)(y0)) \
+ : "cc")
+
+#define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
+ __asm__ ("subcc %r7,%8,%2\n\t" \
+ "subxcc %r5,%6,%1\n\t" \
+ "subx %r3,%4,%0\n" \
+ : "=r" ((USItype)(r2)), \
+ "=&r" ((USItype)(r1)), \
+ "=&r" ((USItype)(r0)) \
+ : "%rJ" ((USItype)(x2)), \
+ "rI" ((USItype)(y2)), \
+ "%rJ" ((USItype)(x1)), \
+ "rI" ((USItype)(y1)), \
+ "%rJ" ((USItype)(x0)), \
+ "rI" ((USItype)(y0)) \
+ : "cc")
+
+#define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
+ do { \
+ /* We need to fool gcc, as we need to pass more than 10 \
+ input/outputs. */ \
+ register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2"); \
+ __asm__ __volatile__ ( \
+ "addcc %r8,%9,%1\n\t" \
+ "addxcc %r6,%7,%0\n\t" \
+ "addxcc %r4,%5,%%g2\n\t" \
+ "addx %r2,%3,%%g1\n\t" \
+ : "=&r" ((USItype)(r1)), \
+ "=&r" ((USItype)(r0)) \
+ : "%rJ" ((USItype)(x3)), \
+ "rI" ((USItype)(y3)), \
+ "%rJ" ((USItype)(x2)), \
+ "rI" ((USItype)(y2)), \
+ "%rJ" ((USItype)(x1)), \
+ "rI" ((USItype)(y1)), \
+ "%rJ" ((USItype)(x0)), \
+ "rI" ((USItype)(y0)) \
+ : "cc", "g1", "g2"); \
+ __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2)); \
+ r3 = _t1; r2 = _t2; \
+ } while (0)
+
+#define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
+ do { \
+ /* We need to fool gcc, as we need to pass more than 10 \
+ input/outputs. */ \
+ register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2"); \
+ __asm__ __volatile__ ( \
+ "subcc %r8,%9,%1\n\t" \
+ "subxcc %r6,%7,%0\n\t" \
+ "subxcc %r4,%5,%%g2\n\t" \
+ "subx %r2,%3,%%g1\n\t" \
+ : "=&r" ((USItype)(r1)), \
+ "=&r" ((USItype)(r0)) \
+ : "%rJ" ((USItype)(x3)), \
+ "rI" ((USItype)(y3)), \
+ "%rJ" ((USItype)(x2)), \
+ "rI" ((USItype)(y2)), \
+ "%rJ" ((USItype)(x1)), \
+ "rI" ((USItype)(y1)), \
+ "%rJ" ((USItype)(x0)), \
+ "rI" ((USItype)(y0)) \
+ : "cc", "g1", "g2"); \
+ __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2)); \
+ r3 = _t1; r2 = _t2; \
+ } while (0)
+
+#define __FP_FRAC_DEC_3(x2,x1,x0,y2,y1,y0) __FP_FRAC_SUB_3(x2,x1,x0,x2,x1,x0,y2,y1,y0)
+
+#define __FP_FRAC_DEC_4(x3,x2,x1,x0,y3,y2,y1,y0) __FP_FRAC_SUB_4(x3,x2,x1,x0,x3,x2,x1,x0,y3,y2,y1,y0)
+
+#define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i) \
+ __asm__ ("addcc %3,%4,%3\n\t" \
+ "addxcc %2,%%g0,%2\n\t" \
+ "addxcc %1,%%g0,%1\n\t" \
+ "addx %0,%%g0,%0\n\t" \
+ : "=&r" ((USItype)(x3)), \
+ "=&r" ((USItype)(x2)), \
+ "=&r" ((USItype)(x1)), \
+ "=&r" ((USItype)(x0)) \
+ : "rI" ((USItype)(i)), \
+ "0" ((USItype)(x3)), \
+ "1" ((USItype)(x2)), \
+ "2" ((USItype)(x1)), \
+ "3" ((USItype)(x0)) \
+ : "cc")
+
+#ifndef CONFIG_SMP
+extern struct task_struct *last_task_used_math;
+#endif
+
+/* Obtain the current rounding mode. */
+#ifndef FP_ROUNDMODE
+#ifdef CONFIG_SMP
+#define FP_ROUNDMODE ((current->thread.fsr >> 30) & 0x3)
+#else
+#define FP_ROUNDMODE ((last_task_used_math->thread.fsr >> 30) & 0x3)
+#endif
+#endif
+
+/* Exception flags. */
+#define FP_EX_INVALID (1 << 4)
+#define FP_EX_OVERFLOW (1 << 3)
+#define FP_EX_UNDERFLOW (1 << 2)
+#define FP_EX_DIVZERO (1 << 1)
+#define FP_EX_INEXACT (1 << 0)
+
+#define FP_HANDLE_EXCEPTIONS return _fex
+
+#ifdef CONFIG_SMP
+#define FP_INHIBIT_RESULTS ((current->thread.fsr >> 23) & _fex)
+#else
+#define FP_INHIBIT_RESULTS ((last_task_used_math->thread.fsr >> 23) & _fex)
+#endif
+
+#ifdef CONFIG_SMP
+#define FP_TRAPPING_EXCEPTIONS ((current->thread.fsr >> 23) & 0x1f)
+#else
+#define FP_TRAPPING_EXCEPTIONS ((last_task_used_math->thread.fsr >> 23) & 0x1f)
+#endif
+
+#endif
--- /dev/null
+/* Machine-dependent software floating-point definitions.
+ Sparc64 kernel version.
+ Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by Richard Henderson (rth@cygnus.com),
+ Jakub Jelinek (jj@ultra.linux.cz) and
+ David S. Miller (davem@redhat.com).
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Library General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Library General Public License for more details.
+
+ You should have received a copy of the GNU Library General Public
+ License along with the GNU C Library; see the file COPYING.LIB. If
+ not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef _SFP_MACHINE_H
+#define _SFP_MACHINE_H
+
+#define _FP_W_TYPE_SIZE 64
+#define _FP_W_TYPE unsigned long
+#define _FP_WS_TYPE signed long
+#define _FP_I_TYPE long
+
+#define _FP_MUL_MEAT_S(R,X,Y) \
+ _FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y)
+#define _FP_MUL_MEAT_D(R,X,Y) \
+ _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_Q(R,X,Y) \
+ _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm)
+#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y)
+#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
+#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1)
+#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1
+#define _FP_NANSIGN_S 0
+#define _FP_NANSIGN_D 0
+#define _FP_NANSIGN_Q 0
+
+#define _FP_KEEPNANFRACP 1
+
+/* If one NaN is signaling and the other is not,
+ * we choose that one, otherwise we choose X.
+ */
+/* For _Qp_* and _Q_*, this should prefer X, for
+ * CPU instruction emulation this should prefer Y.
+ * (see SPAMv9 B.2.2 section).
+ */
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
+ do { \
+ if ((_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs) \
+ && !(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)) \
+ { \
+ R##_s = X##_s; \
+ _FP_FRAC_COPY_##wc(R,X); \
+ } \
+ else \
+ { \
+ R##_s = Y##_s; \
+ _FP_FRAC_COPY_##wc(R,Y); \
+ } \
+ R##_c = FP_CLS_NAN; \
+ } while (0)
+
+/* Obtain the current rounding mode. */
+#ifndef FP_ROUNDMODE
+#define FP_ROUNDMODE ((current_thread_info()->xfsr[0] >> 30) & 0x3)
+#endif
+
+/* Exception flags. */
+#define FP_EX_INVALID (1 << 4)
+#define FP_EX_OVERFLOW (1 << 3)
+#define FP_EX_UNDERFLOW (1 << 2)
+#define FP_EX_DIVZERO (1 << 1)
+#define FP_EX_INEXACT (1 << 0)
+
+#define FP_HANDLE_EXCEPTIONS return _fex
+
+#define FP_INHIBIT_RESULTS ((current_thread_info()->xfsr[0] >> 23) & _fex)
+
+#define FP_TRAPPING_EXCEPTIONS ((current_thread_info()->xfsr[0] >> 23) & 0x1f)
+
+#endif
--- /dev/null
+#ifndef _SPARC_SHMBUF_H
+#define _SPARC_SHMBUF_H
+
+/*
+ * The shmid64_ds structure for sparc architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+#if defined(__sparc__) && defined(__arch64__)
+# define PADDING(x)
+#else
+# define PADDING(x) unsigned int x;
+#endif
+
+struct shmid64_ds {
+ struct ipc64_perm shm_perm; /* operation perms */
+ PADDING(__pad1)
+ __kernel_time_t shm_atime; /* last attach time */
+ PADDING(__pad2)
+ __kernel_time_t shm_dtime; /* last detach time */
+ PADDING(__pad3)
+ __kernel_time_t shm_ctime; /* last change time */
+ size_t shm_segsz; /* size of segment (bytes) */
+ __kernel_pid_t shm_cpid; /* pid of creator */
+ __kernel_pid_t shm_lpid; /* pid of last operator */
+ unsigned long shm_nattch; /* no. of current attaches */
+ unsigned long __unused1;
+ unsigned long __unused2;
+};
+
+struct shminfo64 {
+ unsigned long shmmax;
+ unsigned long shmmin;
+ unsigned long shmmni;
+ unsigned long shmseg;
+ unsigned long shmall;
+ unsigned long __unused1;
+ unsigned long __unused2;
+ unsigned long __unused3;
+ unsigned long __unused4;
+};
+
+#undef PADDING
+
+#endif /* _SPARC_SHMBUF_H */
--- /dev/null
+#ifndef ___ASM_SPARC_SHMPARAM_H
+#define ___ASM_SPARC_SHMPARAM_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/shmparam_64.h>
+#else
+#include <asm/shmparam_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _ASMSPARC_SHMPARAM_H
+#define _ASMSPARC_SHMPARAM_H
+
+#define __ARCH_FORCE_SHMLBA 1
+
+extern int vac_cache_size;
+#define SHMLBA (vac_cache_size ? vac_cache_size : \
+ (sparc_cpu_model == sun4c ? (64 * 1024) : \
+ (sparc_cpu_model == sun4 ? (128 * 1024) : PAGE_SIZE)))
+
+#endif /* _ASMSPARC_SHMPARAM_H */
--- /dev/null
+#ifndef _ASMSPARC64_SHMPARAM_H
+#define _ASMSPARC64_SHMPARAM_H
+
+#include <asm/spitfire.h>
+
+#define __ARCH_FORCE_SHMLBA 1
+/* attach addr a multiple of this */
+#define SHMLBA ((PAGE_SIZE > L1DCACHE_SIZE) ? PAGE_SIZE : L1DCACHE_SIZE)
+
+#endif /* _ASMSPARC64_SHMPARAM_H */
--- /dev/null
+#ifndef ___ASM_SPARC_SIGCONTEXT_H
+#define ___ASM_SPARC_SIGCONTEXT_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/sigcontext_64.h>
+#else
+#include <asm/sigcontext_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef __SPARC_SIGCONTEXT_H
+#define __SPARC_SIGCONTEXT_H
+
+#ifdef __KERNEL__
+#include <asm/ptrace.h>
+
+#ifndef __ASSEMBLY__
+
+#define __SUNOS_MAXWIN 31
+
+/* This is what SunOS does, so shall I. */
+struct sigcontext {
+ int sigc_onstack; /* state to restore */
+ int sigc_mask; /* sigmask to restore */
+ int sigc_sp; /* stack pointer */
+ int sigc_pc; /* program counter */
+ int sigc_npc; /* next program counter */
+ int sigc_psr; /* for condition codes etc */
+ int sigc_g1; /* User uses these two registers */
+ int sigc_o0; /* within the trampoline code. */
+
+ /* Now comes information regarding the users window set
+ * at the time of the signal.
+ */
+ int sigc_oswins; /* outstanding windows */
+
+ /* stack ptrs for each regwin buf */
+ char *sigc_spbuf[__SUNOS_MAXWIN];
+
+ /* Windows to restore after signal */
+ struct {
+ unsigned long locals[8];
+ unsigned long ins[8];
+ } sigc_wbuf[__SUNOS_MAXWIN];
+};
+
+typedef struct {
+ struct {
+ unsigned long psr;
+ unsigned long pc;
+ unsigned long npc;
+ unsigned long y;
+ unsigned long u_regs[16]; /* globals and ins */
+ } si_regs;
+ int si_mask;
+} __siginfo_t;
+
+typedef struct {
+ unsigned long si_float_regs [32];
+ unsigned long si_fsr;
+ unsigned long si_fpqdepth;
+ struct {
+ unsigned long *insn_addr;
+ unsigned long insn;
+ } si_fpqueue [16];
+} __siginfo_fpu_t;
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* (__KERNEL__) */
+
+#endif /* !(__SPARC_SIGCONTEXT_H) */
--- /dev/null
+#ifndef __SPARC64_SIGCONTEXT_H
+#define __SPARC64_SIGCONTEXT_H
+
+#ifdef __KERNEL__
+#include <asm/ptrace.h>
+#endif
+
+#ifndef __ASSEMBLY__
+
+#ifdef __KERNEL__
+
+#define __SUNOS_MAXWIN 31
+
+/* This is what SunOS does, so shall I unless we use new 32bit signals or rt signals. */
+struct sigcontext32 {
+ int sigc_onstack; /* state to restore */
+ int sigc_mask; /* sigmask to restore */
+ int sigc_sp; /* stack pointer */
+ int sigc_pc; /* program counter */
+ int sigc_npc; /* next program counter */
+ int sigc_psr; /* for condition codes etc */
+ int sigc_g1; /* User uses these two registers */
+ int sigc_o0; /* within the trampoline code. */
+
+ /* Now comes information regarding the users window set
+ * at the time of the signal.
+ */
+ int sigc_oswins; /* outstanding windows */
+
+ /* stack ptrs for each regwin buf */
+ unsigned sigc_spbuf[__SUNOS_MAXWIN];
+
+ /* Windows to restore after signal */
+ struct reg_window32 sigc_wbuf[__SUNOS_MAXWIN];
+};
+
+#endif
+
+#ifdef __KERNEL__
+
+/* This is what we use for 32bit new non-rt signals. */
+
+typedef struct {
+ struct {
+ unsigned int psr;
+ unsigned int pc;
+ unsigned int npc;
+ unsigned int y;
+ unsigned int u_regs[16]; /* globals and ins */
+ } si_regs;
+ int si_mask;
+} __siginfo32_t;
+
+#endif
+
+typedef struct {
+ unsigned int si_float_regs [64];
+ unsigned long si_fsr;
+ unsigned long si_gsr;
+ unsigned long si_fprs;
+} __siginfo_fpu_t;
+
+/* This is what SunOS doesn't, so we have to write this alone
+ and do it properly. */
+struct sigcontext {
+ /* The size of this array has to match SI_MAX_SIZE from siginfo.h */
+ char sigc_info[128];
+ struct {
+ unsigned long u_regs[16]; /* globals and ins */
+ unsigned long tstate;
+ unsigned long tpc;
+ unsigned long tnpc;
+ unsigned int y;
+ unsigned int fprs;
+ } sigc_regs;
+ __siginfo_fpu_t * sigc_fpu_save;
+ struct {
+ void * ss_sp;
+ int ss_flags;
+ unsigned long ss_size;
+ } sigc_stack;
+ unsigned long sigc_mask;
+};
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__SPARC64_SIGCONTEXT_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_SIGINFO_H
+#define ___ASM_SPARC_SIGINFO_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/siginfo_64.h>
+#else
+#include <asm/siginfo_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _SPARC_SIGINFO_H
+#define _SPARC_SIGINFO_H
+
+#define __ARCH_SI_UID_T unsigned int
+#define __ARCH_SI_TRAPNO
+
+#include <asm-generic/siginfo.h>
+
+#define SI_NOINFO 32767 /* no information in siginfo_t */
+
+/*
+ * SIGEMT si_codes
+ */
+#define EMT_TAGOVF (__SI_FAULT|1) /* tag overflow */
+#define NSIGEMT 1
+
+#endif /* !(_SPARC_SIGINFO_H) */
--- /dev/null
+#ifndef _SPARC64_SIGINFO_H
+#define _SPARC64_SIGINFO_H
+
+#define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3)
+
+#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
+#define __ARCH_SI_TRAPNO
+#define __ARCH_SI_BAND_T int
+
+#include <asm-generic/siginfo.h>
+
+#ifdef __KERNEL__
+
+#include <linux/compat.h>
+
+#ifdef CONFIG_COMPAT
+
+struct compat_siginfo;
+
+#endif /* CONFIG_COMPAT */
+
+#endif /* __KERNEL__ */
+
+#define SI_NOINFO 32767 /* no information in siginfo_t */
+
+/*
+ * SIGEMT si_codes
+ */
+#define EMT_TAGOVF (__SI_FAULT|1) /* tag overflow */
+#define NSIGEMT 1
+
+#endif
--- /dev/null
+#ifndef ___ASM_SPARC_SIGNAL_H
+#define ___ASM_SPARC_SIGNAL_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/signal_64.h>
+#else
+#include <asm/signal_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _ASMSPARC_SIGNAL_H
+#define _ASMSPARC_SIGNAL_H
+
+#include <asm/sigcontext.h>
+#include <linux/compiler.h>
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+#include <linux/personality.h>
+#include <linux/types.h>
+#endif
+#endif
+
+/* On the Sparc the signal handlers get passed a 'sub-signal' code
+ * for certain signal types, which we document here.
+ */
+#define SIGHUP 1
+#define SIGINT 2
+#define SIGQUIT 3
+#define SIGILL 4
+#define SUBSIG_STACK 0
+#define SUBSIG_ILLINST 2
+#define SUBSIG_PRIVINST 3
+#define SUBSIG_BADTRAP(t) (0x80 + (t))
+
+#define SIGTRAP 5
+#define SIGABRT 6
+#define SIGIOT 6
+
+#define SIGEMT 7
+#define SUBSIG_TAG 10
+
+#define SIGFPE 8
+#define SUBSIG_FPDISABLED 0x400
+#define SUBSIG_FPERROR 0x404
+#define SUBSIG_FPINTOVFL 0x001
+#define SUBSIG_FPSTSIG 0x002
+#define SUBSIG_IDIVZERO 0x014
+#define SUBSIG_FPINEXACT 0x0c4
+#define SUBSIG_FPDIVZERO 0x0c8
+#define SUBSIG_FPUNFLOW 0x0cc
+#define SUBSIG_FPOPERROR 0x0d0
+#define SUBSIG_FPOVFLOW 0x0d4
+
+#define SIGKILL 9
+#define SIGBUS 10
+#define SUBSIG_BUSTIMEOUT 1
+#define SUBSIG_ALIGNMENT 2
+#define SUBSIG_MISCERROR 5
+
+#define SIGSEGV 11
+#define SUBSIG_NOMAPPING 3
+#define SUBSIG_PROTECTION 4
+#define SUBSIG_SEGERROR 5
+
+#define SIGSYS 12
+
+#define SIGPIPE 13
+#define SIGALRM 14
+#define SIGTERM 15
+#define SIGURG 16
+
+/* SunOS values which deviate from the Linux/i386 ones */
+#define SIGSTOP 17
+#define SIGTSTP 18
+#define SIGCONT 19
+#define SIGCHLD 20
+#define SIGTTIN 21
+#define SIGTTOU 22
+#define SIGIO 23
+#define SIGPOLL SIGIO /* SysV name for SIGIO */
+#define SIGXCPU 24
+#define SIGXFSZ 25
+#define SIGVTALRM 26
+#define SIGPROF 27
+#define SIGWINCH 28
+#define SIGLOST 29
+#define SIGPWR SIGLOST
+#define SIGUSR1 30
+#define SIGUSR2 31
+
+/* Most things should be clean enough to redefine this at will, if care
+ * is taken to make libc match.
+ */
+
+#define __OLD_NSIG 32
+#define __NEW_NSIG 64
+#define _NSIG_BPW 32
+#define _NSIG_WORDS (__NEW_NSIG / _NSIG_BPW)
+
+#define SIGRTMIN 32
+#define SIGRTMAX __NEW_NSIG
+
+#if defined(__KERNEL__) || defined(__WANT_POSIX1B_SIGNALS__)
+#define _NSIG __NEW_NSIG
+#define __new_sigset_t sigset_t
+#define __new_sigaction sigaction
+#define __old_sigset_t old_sigset_t
+#define __old_sigaction old_sigaction
+#else
+#define _NSIG __OLD_NSIG
+#define __old_sigset_t sigset_t
+#define __old_sigaction sigaction
+#endif
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned long __old_sigset_t;
+
+typedef struct {
+ unsigned long sig[_NSIG_WORDS];
+} __new_sigset_t;
+
+
+#ifdef __KERNEL__
+/* A SunOS sigstack */
+struct sigstack {
+ char *the_stack;
+ int cur_status;
+};
+#endif
+
+/* Sigvec flags */
+#define _SV_SSTACK 1u /* This signal handler should use sig-stack */
+#define _SV_INTR 2u /* Sig return should not restart system call */
+#define _SV_RESET 4u /* Set handler to SIG_DFL upon taken signal */
+#define _SV_IGNCHILD 8u /* Do not send SIGCHLD */
+
+/*
+ * sa_flags values: SA_STACK is not currently supported, but will allow the
+ * usage of signal stacks by using the (now obsolete) sa_restorer field in
+ * the sigaction structure as a stack pointer. This is now possible due to
+ * the changes in signal handling. LBT 010493.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ */
+#define SA_NOCLDSTOP _SV_IGNCHILD
+#define SA_STACK _SV_SSTACK
+#define SA_ONSTACK _SV_SSTACK
+#define SA_RESTART _SV_INTR
+#define SA_ONESHOT _SV_RESET
+#define SA_NOMASK 0x20u
+#define SA_NOCLDWAIT 0x100u
+#define SA_SIGINFO 0x200u
+
+#define SIG_BLOCK 0x01 /* for blocking signals */
+#define SIG_UNBLOCK 0x02 /* for unblocking signals */
+#define SIG_SETMASK 0x04 /* for setting the signal mask */
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK 1
+#define SS_DISABLE 2
+
+#define MINSIGSTKSZ 4096
+#define SIGSTKSZ 16384
+
+#ifdef __KERNEL__
+/*
+ * DJHR
+ * SA_STATIC_ALLOC is used for the SPARC system to indicate that this
+ * interrupt handler's irq structure should be statically allocated
+ * by the request_irq routine.
+ * The alternative is that arch/sparc/kernel/irq.c has carnal knowledge
+ * of interrupt usage and that sucks. Also without a flag like this
+ * it may be possible for the free_irq routine to attempt to free
+ * statically allocated data.. which is NOT GOOD.
+ *
+ */
+#define SA_STATIC_ALLOC 0x8000
+#endif
+
+#include <asm-generic/signal.h>
+
+#ifdef __KERNEL__
+struct __new_sigaction {
+ __sighandler_t sa_handler;
+ unsigned long sa_flags;
+ void (*sa_restorer)(void); /* Not used by Linux/SPARC */
+ __new_sigset_t sa_mask;
+};
+
+struct k_sigaction {
+ struct __new_sigaction sa;
+ void __user *ka_restorer;
+};
+
+struct __old_sigaction {
+ __sighandler_t sa_handler;
+ __old_sigset_t sa_mask;
+ unsigned long sa_flags;
+ void (*sa_restorer) (void); /* not used by Linux/SPARC */
+};
+
+typedef struct sigaltstack {
+ void __user *ss_sp;
+ int ss_flags;
+ size_t ss_size;
+} stack_t;
+
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif /* !(__KERNEL__) */
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_ASMSPARC_SIGNAL_H) */
--- /dev/null
+#ifndef _ASMSPARC64_SIGNAL_H
+#define _ASMSPARC64_SIGNAL_H
+
+#include <asm/sigcontext.h>
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+#include <linux/personality.h>
+#include <linux/types.h>
+#endif
+#endif
+
+/* On the Sparc the signal handlers get passed a 'sub-signal' code
+ * for certain signal types, which we document here.
+ */
+#define SIGHUP 1
+#define SIGINT 2
+#define SIGQUIT 3
+#define SIGILL 4
+#define SUBSIG_STACK 0
+#define SUBSIG_ILLINST 2
+#define SUBSIG_PRIVINST 3
+#define SUBSIG_BADTRAP(t) (0x80 + (t))
+
+#define SIGTRAP 5
+#define SIGABRT 6
+#define SIGIOT 6
+
+#define SIGEMT 7
+#define SUBSIG_TAG 10
+
+#define SIGFPE 8
+#define SUBSIG_FPDISABLED 0x400
+#define SUBSIG_FPERROR 0x404
+#define SUBSIG_FPINTOVFL 0x001
+#define SUBSIG_FPSTSIG 0x002
+#define SUBSIG_IDIVZERO 0x014
+#define SUBSIG_FPINEXACT 0x0c4
+#define SUBSIG_FPDIVZERO 0x0c8
+#define SUBSIG_FPUNFLOW 0x0cc
+#define SUBSIG_FPOPERROR 0x0d0
+#define SUBSIG_FPOVFLOW 0x0d4
+
+#define SIGKILL 9
+#define SIGBUS 10
+#define SUBSIG_BUSTIMEOUT 1
+#define SUBSIG_ALIGNMENT 2
+#define SUBSIG_MISCERROR 5
+
+#define SIGSEGV 11
+#define SUBSIG_NOMAPPING 3
+#define SUBSIG_PROTECTION 4
+#define SUBSIG_SEGERROR 5
+
+#define SIGSYS 12
+
+#define SIGPIPE 13
+#define SIGALRM 14
+#define SIGTERM 15
+#define SIGURG 16
+
+/* SunOS values which deviate from the Linux/i386 ones */
+#define SIGSTOP 17
+#define SIGTSTP 18
+#define SIGCONT 19
+#define SIGCHLD 20
+#define SIGTTIN 21
+#define SIGTTOU 22
+#define SIGIO 23
+#define SIGPOLL SIGIO /* SysV name for SIGIO */
+#define SIGXCPU 24
+#define SIGXFSZ 25
+#define SIGVTALRM 26
+#define SIGPROF 27
+#define SIGWINCH 28
+#define SIGLOST 29
+#define SIGPWR SIGLOST
+#define SIGUSR1 30
+#define SIGUSR2 31
+
+/* Most things should be clean enough to redefine this at will, if care
+ is taken to make libc match. */
+
+#define __OLD_NSIG 32
+#define __NEW_NSIG 64
+#define _NSIG_BPW 64
+#define _NSIG_WORDS (__NEW_NSIG / _NSIG_BPW)
+
+#define SIGRTMIN 32
+#define SIGRTMAX __NEW_NSIG
+
+#if defined(__KERNEL__) || defined(__WANT_POSIX1B_SIGNALS__)
+#define _NSIG __NEW_NSIG
+#define __new_sigset_t sigset_t
+#define __new_sigaction sigaction
+#define __new_sigaction32 sigaction32
+#define __old_sigset_t old_sigset_t
+#define __old_sigaction old_sigaction
+#define __old_sigaction32 old_sigaction32
+#else
+#define _NSIG __OLD_NSIG
+#define NSIG _NSIG
+#define __old_sigset_t sigset_t
+#define __old_sigaction sigaction
+#define __old_sigaction32 sigaction32
+#endif
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned long __old_sigset_t; /* at least 32 bits */
+
+typedef struct {
+ unsigned long sig[_NSIG_WORDS];
+} __new_sigset_t;
+
+/* A SunOS sigstack */
+struct sigstack {
+ /* XXX 32-bit pointers pinhead XXX */
+ char *the_stack;
+ int cur_status;
+};
+
+/* Sigvec flags */
+#define _SV_SSTACK 1u /* This signal handler should use sig-stack */
+#define _SV_INTR 2u /* Sig return should not restart system call */
+#define _SV_RESET 4u /* Set handler to SIG_DFL upon taken signal */
+#define _SV_IGNCHILD 8u /* Do not send SIGCHLD */
+
+/*
+ * sa_flags values: SA_STACK is not currently supported, but will allow the
+ * usage of signal stacks by using the (now obsolete) sa_restorer field in
+ * the sigaction structure as a stack pointer. This is now possible due to
+ * the changes in signal handling. LBT 010493.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ */
+#define SA_NOCLDSTOP _SV_IGNCHILD
+#define SA_STACK _SV_SSTACK
+#define SA_ONSTACK _SV_SSTACK
+#define SA_RESTART _SV_INTR
+#define SA_ONESHOT _SV_RESET
+#define SA_NOMASK 0x20u
+#define SA_NOCLDWAIT 0x100u
+#define SA_SIGINFO 0x200u
+
+
+#define SIG_BLOCK 0x01 /* for blocking signals */
+#define SIG_UNBLOCK 0x02 /* for unblocking signals */
+#define SIG_SETMASK 0x04 /* for setting the signal mask */
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK 1
+#define SS_DISABLE 2
+
+#define MINSIGSTKSZ 4096
+#define SIGSTKSZ 16384
+
+#include <asm-generic/signal.h>
+
+struct __new_sigaction {
+ __sighandler_t sa_handler;
+ unsigned long sa_flags;
+ __sigrestore_t sa_restorer; /* not used by Linux/SPARC yet */
+ __new_sigset_t sa_mask;
+};
+
+struct __old_sigaction {
+ __sighandler_t sa_handler;
+ __old_sigset_t sa_mask;
+ unsigned long sa_flags;
+ void (*sa_restorer)(void); /* not used by Linux/SPARC yet */
+};
+
+typedef struct sigaltstack {
+ void __user *ss_sp;
+ int ss_flags;
+ size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+
+struct k_sigaction {
+ struct __new_sigaction sa;
+ void __user *ka_restorer;
+};
+
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif /* !(__KERNEL__) */
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_ASMSPARC64_SIGNAL_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_SMP_H
+#define ___ASM_SPARC_SMP_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/smp_64.h>
+#else
+#include <asm/smp_32.h>
+#endif
+#endif
--- /dev/null
+/* smp.h: Sparc specific SMP stuff.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_SMP_H
+#define _SPARC_SMP_H
+
+#include <linux/threads.h>
+#include <asm/head.h>
+#include <asm/btfixup.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/cpumask.h>
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_SMP
+
+#ifndef __ASSEMBLY__
+
+#include <asm/ptrace.h>
+#include <asm/asi.h>
+#include <asm/atomic.h>
+
+/*
+ * Private routines/data
+ */
+
+extern unsigned char boot_cpu_id;
+extern cpumask_t phys_cpu_present_map;
+#define cpu_possible_map phys_cpu_present_map
+
+typedef void (*smpfunc_t)(unsigned long, unsigned long, unsigned long,
+ unsigned long, unsigned long);
+
+/*
+ * General functions that each host system must provide.
+ */
+
+void sun4m_init_smp(void);
+void sun4d_init_smp(void);
+
+void smp_callin(void);
+void smp_boot_cpus(void);
+void smp_store_cpu_info(int);
+
+struct seq_file;
+void smp_bogo(struct seq_file *);
+void smp_info(struct seq_file *);
+
+BTFIXUPDEF_CALL(void, smp_cross_call, smpfunc_t, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long)
+BTFIXUPDEF_CALL(int, __hard_smp_processor_id, void)
+BTFIXUPDEF_BLACKBOX(hard_smp_processor_id)
+BTFIXUPDEF_BLACKBOX(load_current)
+
+#define smp_cross_call(func,arg1,arg2,arg3,arg4,arg5) BTFIXUP_CALL(smp_cross_call)(func,arg1,arg2,arg3,arg4,arg5)
+
+static inline void xc0(smpfunc_t func) { smp_cross_call(func, 0, 0, 0, 0, 0); }
+static inline void xc1(smpfunc_t func, unsigned long arg1)
+{ smp_cross_call(func, arg1, 0, 0, 0, 0); }
+static inline void xc2(smpfunc_t func, unsigned long arg1, unsigned long arg2)
+{ smp_cross_call(func, arg1, arg2, 0, 0, 0); }
+static inline void xc3(smpfunc_t func, unsigned long arg1, unsigned long arg2,
+ unsigned long arg3)
+{ smp_cross_call(func, arg1, arg2, arg3, 0, 0); }
+static inline void xc4(smpfunc_t func, unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4)
+{ smp_cross_call(func, arg1, arg2, arg3, arg4, 0); }
+static inline void xc5(smpfunc_t func, unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4, unsigned long arg5)
+{ smp_cross_call(func, arg1, arg2, arg3, arg4, arg5); }
+
+static inline int smp_call_function(void (*func)(void *info), void *info, int wait)
+{
+ xc1((smpfunc_t)func, (unsigned long)info);
+ return 0;
+}
+
+static inline int cpu_logical_map(int cpu)
+{
+ return cpu;
+}
+
+static inline int hard_smp4m_processor_id(void)
+{
+ int cpuid;
+
+ __asm__ __volatile__("rd %%tbr, %0\n\t"
+ "srl %0, 12, %0\n\t"
+ "and %0, 3, %0\n\t" :
+ "=&r" (cpuid));
+ return cpuid;
+}
+
+static inline int hard_smp4d_processor_id(void)
+{
+ int cpuid;
+
+ __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
+ "=&r" (cpuid) : "i" (ASI_M_VIKING_TMP1));
+ return cpuid;
+}
+
+#ifndef MODULE
+static inline int hard_smp_processor_id(void)
+{
+ int cpuid;
+
+ /* Black box - sun4m
+ __asm__ __volatile__("rd %%tbr, %0\n\t"
+ "srl %0, 12, %0\n\t"
+ "and %0, 3, %0\n\t" :
+ "=&r" (cpuid));
+ - sun4d
+ __asm__ __volatile__("lda [%g0] ASI_M_VIKING_TMP1, %0\n\t"
+ "nop; nop" :
+ "=&r" (cpuid));
+ See btfixup.h and btfixupprep.c to understand how a blackbox works.
+ */
+ __asm__ __volatile__("sethi %%hi(___b_hard_smp_processor_id), %0\n\t"
+ "sethi %%hi(boot_cpu_id), %0\n\t"
+ "ldub [%0 + %%lo(boot_cpu_id)], %0\n\t" :
+ "=&r" (cpuid));
+ return cpuid;
+}
+#else
+static inline int hard_smp_processor_id(void)
+{
+ int cpuid;
+
+ __asm__ __volatile__("mov %%o7, %%g1\n\t"
+ "call ___f___hard_smp_processor_id\n\t"
+ " nop\n\t"
+ "mov %%g2, %0\n\t" : "=r"(cpuid) : : "g1", "g2");
+ return cpuid;
+}
+#endif
+
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+#define prof_multiplier(__cpu) cpu_data(__cpu).multiplier
+#define prof_counter(__cpu) cpu_data(__cpu).counter
+
+void smp_setup_cpu_possible_map(void);
+
+#endif /* !(__ASSEMBLY__) */
+
+/* Sparc specific messages. */
+#define MSG_CROSS_CALL 0x0005 /* run func on cpus */
+
+/* Empirical PROM processor mailbox constants. If the per-cpu mailbox
+ * contains something other than one of these then the ipi is from
+ * Linux's active_kernel_processor. This facility exists so that
+ * the boot monitor can capture all the other cpus when one catches
+ * a watchdog reset or the user enters the monitor using L1-A keys.
+ */
+#define MBOX_STOPCPU 0xFB
+#define MBOX_IDLECPU 0xFC
+#define MBOX_IDLECPU2 0xFD
+#define MBOX_STOPCPU2 0xFE
+
+#else /* SMP */
+
+#define hard_smp_processor_id() 0
+#define smp_setup_cpu_possible_map() do { } while (0)
+
+#endif /* !(SMP) */
+
+#define NO_PROC_ID 0xFF
+
+#endif /* !(_SPARC_SMP_H) */
--- /dev/null
+/* smp.h: Sparc64 specific SMP stuff.
+ *
+ * Copyright (C) 1996, 2008 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC64_SMP_H
+#define _SPARC64_SMP_H
+
+#include <linux/threads.h>
+#include <asm/asi.h>
+#include <asm/starfire.h>
+#include <asm/spitfire.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/cpumask.h>
+#include <linux/cache.h>
+
+#endif /* !(__ASSEMBLY__) */
+
+#ifdef CONFIG_SMP
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Private routines/data
+ */
+
+#include <linux/bitops.h>
+#include <asm/atomic.h>
+#include <asm/percpu.h>
+
+DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
+extern cpumask_t cpu_core_map[NR_CPUS];
+extern int sparc64_multi_core;
+
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
+/*
+ * General functions that each host system must provide.
+ */
+
+extern int hard_smp_processor_id(void);
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+extern void smp_fill_in_sib_core_maps(void);
+extern void cpu_play_dead(void);
+
+extern void smp_fetch_global_regs(void);
+
+#ifdef CONFIG_HOTPLUG_CPU
+extern int __cpu_disable(void);
+extern void __cpu_die(unsigned int cpu);
+#endif
+
+#endif /* !(__ASSEMBLY__) */
+
+#else
+
+#define hard_smp_processor_id() 0
+#define smp_fill_in_sib_core_maps() do { } while (0)
+#define smp_fetch_global_regs() do { } while (0)
+
+#endif /* !(CONFIG_SMP) */
+
+#endif /* !(_SPARC64_SMP_H) */
--- /dev/null
+/*
+ * smpprim.h: SMP locking primitives on the Sparc
+ *
+ * God knows we won't be actually using this code for some time
+ * but I thought I'd write it since I knew how.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __SPARC_SMPPRIM_H
+#define __SPARC_SMPPRIM_H
+
+/* Test and set the unsigned byte at ADDR to 1. Returns the previous
+ * value. On the Sparc we use the ldstub instruction since it is
+ * atomic.
+ */
+
+static inline __volatile__ char test_and_set(void *addr)
+{
+ char state = 0;
+
+ __asm__ __volatile__("ldstub [%0], %1 ! test_and_set\n\t"
+ "=r" (addr), "=r" (state) :
+ "0" (addr), "1" (state) : "memory");
+
+ return state;
+}
+
+/* Initialize a spin-lock. */
+static inline __volatile__ smp_initlock(void *spinlock)
+{
+ /* Unset the lock. */
+ *((unsigned char *) spinlock) = 0;
+
+ return;
+}
+
+/* This routine spins until it acquires the lock at ADDR. */
+static inline __volatile__ smp_lock(void *addr)
+{
+ while(test_and_set(addr) == 0xff)
+ ;
+
+ /* We now have the lock */
+ return;
+}
+
+/* This routine releases the lock at ADDR. */
+static inline __volatile__ smp_unlock(void *addr)
+{
+ *((unsigned char *) addr) = 0;
+}
+
+#endif /* !(__SPARC_SMPPRIM_H) */
--- /dev/null
+#ifndef _ASM_SOCKET_H
+#define _ASM_SOCKET_H
+
+#include <asm/sockios.h>
+
+/* For setsockopt(2) */
+#define SOL_SOCKET 0xffff
+
+#define SO_DEBUG 0x0001
+#define SO_PASSCRED 0x0002
+#define SO_REUSEADDR 0x0004
+#define SO_KEEPALIVE 0x0008
+#define SO_DONTROUTE 0x0010
+#define SO_BROADCAST 0x0020
+#define SO_PEERCRED 0x0040
+#define SO_LINGER 0x0080
+#define SO_OOBINLINE 0x0100
+/* To add :#define SO_REUSEPORT 0x0200 */
+#define SO_BSDCOMPAT 0x0400
+#define SO_RCVLOWAT 0x0800
+#define SO_SNDLOWAT 0x1000
+#define SO_RCVTIMEO 0x2000
+#define SO_SNDTIMEO 0x4000
+#define SO_ACCEPTCONN 0x8000
+
+#define SO_SNDBUF 0x1001
+#define SO_RCVBUF 0x1002
+#define SO_SNDBUFFORCE 0x100a
+#define SO_RCVBUFFORCE 0x100b
+#define SO_ERROR 0x1007
+#define SO_TYPE 0x1008
+
+/* Linux specific, keep the same. */
+#define SO_NO_CHECK 0x000b
+#define SO_PRIORITY 0x000c
+
+#define SO_BINDTODEVICE 0x000d
+
+#define SO_ATTACH_FILTER 0x001a
+#define SO_DETACH_FILTER 0x001b
+
+#define SO_PEERNAME 0x001c
+#define SO_TIMESTAMP 0x001d
+#define SCM_TIMESTAMP SO_TIMESTAMP
+
+#define SO_PEERSEC 0x001e
+#define SO_PASSSEC 0x001f
+#define SO_TIMESTAMPNS 0x0021
+#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
+
+#define SO_MARK 0x0022
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION 0x5001
+#define SO_SECURITY_ENCRYPTION_TRANSPORT 0x5002
+#define SO_SECURITY_ENCRYPTION_NETWORK 0x5004
+
+#endif /* _ASM_SOCKET_H */
--- /dev/null
+#ifndef _ASM_SPARC_SOCKIOS_H
+#define _ASM_SPARC_SOCKIOS_H
+
+/* Socket-level I/O control calls. */
+#define FIOSETOWN 0x8901
+#define SIOCSPGRP 0x8902
+#define FIOGETOWN 0x8903
+#define SIOCGPGRP 0x8904
+#define SIOCATMARK 0x8905
+#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
+#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
+
+#endif /* !(_ASM_SPARC_SOCKIOS_H) */
+
--- /dev/null
+#ifndef _SPARC64_SPARSEMEM_H
+#define _SPARC64_SPARSEMEM_H
+
+#ifdef __KERNEL__
+
+#define SECTION_SIZE_BITS 30
+#define MAX_PHYSADDR_BITS 42
+#define MAX_PHYSMEM_BITS 42
+
+#endif /* !(__KERNEL__) */
+
+#endif /* !(_SPARC64_SPARSEMEM_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_SPINLOCK_H
+#define ___ASM_SPARC_SPINLOCK_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/spinlock_64.h>
+#else
+#include <asm/spinlock_32.h>
+#endif
+#endif
--- /dev/null
+/* spinlock.h: 32-bit Sparc spinlock support.
+ *
+ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __SPARC_SPINLOCK_H
+#define __SPARC_SPINLOCK_H
+
+#include <linux/threads.h> /* For NR_CPUS */
+
+#ifndef __ASSEMBLY__
+
+#include <asm/psr.h>
+
+#define __raw_spin_is_locked(lock) (*((volatile unsigned char *)(lock)) != 0)
+
+#define __raw_spin_unlock_wait(lock) \
+ do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
+
+static inline void __raw_spin_lock(raw_spinlock_t *lock)
+{
+ __asm__ __volatile__(
+ "\n1:\n\t"
+ "ldstub [%0], %%g2\n\t"
+ "orcc %%g2, 0x0, %%g0\n\t"
+ "bne,a 2f\n\t"
+ " ldub [%0], %%g2\n\t"
+ ".subsection 2\n"
+ "2:\n\t"
+ "orcc %%g2, 0x0, %%g0\n\t"
+ "bne,a 2b\n\t"
+ " ldub [%0], %%g2\n\t"
+ "b,a 1b\n\t"
+ ".previous\n"
+ : /* no outputs */
+ : "r" (lock)
+ : "g2", "memory", "cc");
+}
+
+static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+{
+ unsigned int result;
+ __asm__ __volatile__("ldstub [%1], %0"
+ : "=r" (result)
+ : "r" (lock)
+ : "memory");
+ return (result == 0);
+}
+
+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+{
+ __asm__ __volatile__("stb %%g0, [%0]" : : "r" (lock) : "memory");
+}
+
+/* Read-write spinlocks, allowing multiple readers
+ * but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts
+ * but no interrupt writers. For those circumstances we
+ * can "mix" irq-safe locks - any writer needs to get a
+ * irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ *
+ * XXX This might create some problems with my dual spinlock
+ * XXX scheme, deadlocks etc. -DaveM
+ *
+ * Sort of like atomic_t's on Sparc, but even more clever.
+ *
+ * ------------------------------------
+ * | 24-bit counter | wlock | raw_rwlock_t
+ * ------------------------------------
+ * 31 8 7 0
+ *
+ * wlock signifies the one writer is in or somebody is updating
+ * counter. For a writer, if he successfully acquires the wlock,
+ * but counter is non-zero, he has to release the lock and wait,
+ * till both counter and wlock are zero.
+ *
+ * Unfortunately this scheme limits us to ~16,000,000 cpus.
+ */
+static inline void __read_lock(raw_rwlock_t *rw)
+{
+ register raw_rwlock_t *lp asm("g1");
+ lp = rw;
+ __asm__ __volatile__(
+ "mov %%o7, %%g4\n\t"
+ "call ___rw_read_enter\n\t"
+ " ldstub [%%g1 + 3], %%g2\n"
+ : /* no outputs */
+ : "r" (lp)
+ : "g2", "g4", "memory", "cc");
+}
+
+#define __raw_read_lock(lock) \
+do { unsigned long flags; \
+ local_irq_save(flags); \
+ __read_lock(lock); \
+ local_irq_restore(flags); \
+} while(0)
+
+static inline void __read_unlock(raw_rwlock_t *rw)
+{
+ register raw_rwlock_t *lp asm("g1");
+ lp = rw;
+ __asm__ __volatile__(
+ "mov %%o7, %%g4\n\t"
+ "call ___rw_read_exit\n\t"
+ " ldstub [%%g1 + 3], %%g2\n"
+ : /* no outputs */
+ : "r" (lp)
+ : "g2", "g4", "memory", "cc");
+}
+
+#define __raw_read_unlock(lock) \
+do { unsigned long flags; \
+ local_irq_save(flags); \
+ __read_unlock(lock); \
+ local_irq_restore(flags); \
+} while(0)
+
+static inline void __raw_write_lock(raw_rwlock_t *rw)
+{
+ register raw_rwlock_t *lp asm("g1");
+ lp = rw;
+ __asm__ __volatile__(
+ "mov %%o7, %%g4\n\t"
+ "call ___rw_write_enter\n\t"
+ " ldstub [%%g1 + 3], %%g2\n"
+ : /* no outputs */
+ : "r" (lp)
+ : "g2", "g4", "memory", "cc");
+ *(volatile __u32 *)&lp->lock = ~0U;
+}
+
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
+{
+ unsigned int val;
+
+ __asm__ __volatile__("ldstub [%1 + 3], %0"
+ : "=r" (val)
+ : "r" (&rw->lock)
+ : "memory");
+
+ if (val == 0) {
+ val = rw->lock & ~0xff;
+ if (val)
+ ((volatile u8*)&rw->lock)[3] = 0;
+ else
+ *(volatile u32*)&rw->lock = ~0U;
+ }
+
+ return (val == 0);
+}
+
+static inline int __read_trylock(raw_rwlock_t *rw)
+{
+ register raw_rwlock_t *lp asm("g1");
+ register int res asm("o0");
+ lp = rw;
+ __asm__ __volatile__(
+ "mov %%o7, %%g4\n\t"
+ "call ___rw_read_try\n\t"
+ " ldstub [%%g1 + 3], %%g2\n"
+ : "=r" (res)
+ : "r" (lp)
+ : "g2", "g4", "memory", "cc");
+ return res;
+}
+
+#define __raw_read_trylock(lock) \
+({ unsigned long flags; \
+ int res; \
+ local_irq_save(flags); \
+ res = __read_trylock(lock); \
+ local_irq_restore(flags); \
+ res; \
+})
+
+#define __raw_write_unlock(rw) do { (rw)->lock = 0; } while(0)
+
+#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+
+#define _raw_spin_relax(lock) cpu_relax()
+#define _raw_read_relax(lock) cpu_relax()
+#define _raw_write_relax(lock) cpu_relax()
+
+#define __raw_read_can_lock(rw) (!((rw)->lock & 0xff))
+#define __raw_write_can_lock(rw) (!(rw)->lock)
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* __SPARC_SPINLOCK_H */
--- /dev/null
+/* spinlock.h: 64-bit Sparc spinlock support.
+ *
+ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __SPARC64_SPINLOCK_H
+#define __SPARC64_SPINLOCK_H
+
+#include <linux/threads.h> /* For NR_CPUS */
+
+#ifndef __ASSEMBLY__
+
+/* To get debugging spinlocks which detect and catch
+ * deadlock situations, set CONFIG_DEBUG_SPINLOCK
+ * and rebuild your kernel.
+ */
+
+/* All of these locking primitives are expected to work properly
+ * even in an RMO memory model, which currently is what the kernel
+ * runs in.
+ *
+ * There is another issue. Because we play games to save cycles
+ * in the non-contention case, we need to be extra careful about
+ * branch targets into the "spinning" code. They live in their
+ * own section, but the newer V9 branches have a shorter range
+ * than the traditional 32-bit sparc branch variants. The rule
+ * is that the branches that go into and out of the spinner sections
+ * must be pre-V9 branches.
+ */
+
+#define __raw_spin_is_locked(lp) ((lp)->lock != 0)
+
+#define __raw_spin_unlock_wait(lp) \
+ do { rmb(); \
+ } while((lp)->lock)
+
+static inline void __raw_spin_lock(raw_spinlock_t *lock)
+{
+ unsigned long tmp;
+
+ __asm__ __volatile__(
+"1: ldstub [%1], %0\n"
+" membar #StoreLoad | #StoreStore\n"
+" brnz,pn %0, 2f\n"
+" nop\n"
+" .subsection 2\n"
+"2: ldub [%1], %0\n"
+" membar #LoadLoad\n"
+" brnz,pt %0, 2b\n"
+" nop\n"
+" ba,a,pt %%xcc, 1b\n"
+" .previous"
+ : "=&r" (tmp)
+ : "r" (lock)
+ : "memory");
+}
+
+static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+{
+ unsigned long result;
+
+ __asm__ __volatile__(
+" ldstub [%1], %0\n"
+" membar #StoreLoad | #StoreStore"
+ : "=r" (result)
+ : "r" (lock)
+ : "memory");
+
+ return (result == 0UL);
+}
+
+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+{
+ __asm__ __volatile__(
+" membar #StoreStore | #LoadStore\n"
+" stb %%g0, [%0]"
+ : /* No outputs */
+ : "r" (lock)
+ : "memory");
+}
+
+static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
+{
+ unsigned long tmp1, tmp2;
+
+ __asm__ __volatile__(
+"1: ldstub [%2], %0\n"
+" membar #StoreLoad | #StoreStore\n"
+" brnz,pn %0, 2f\n"
+" nop\n"
+" .subsection 2\n"
+"2: rdpr %%pil, %1\n"
+" wrpr %3, %%pil\n"
+"3: ldub [%2], %0\n"
+" membar #LoadLoad\n"
+" brnz,pt %0, 3b\n"
+" nop\n"
+" ba,pt %%xcc, 1b\n"
+" wrpr %1, %%pil\n"
+" .previous"
+ : "=&r" (tmp1), "=&r" (tmp2)
+ : "r"(lock), "r"(flags)
+ : "memory");
+}
+
+/* Multi-reader locks, these are much saner than the 32-bit Sparc ones... */
+
+static void inline __read_lock(raw_rwlock_t *lock)
+{
+ unsigned long tmp1, tmp2;
+
+ __asm__ __volatile__ (
+"1: ldsw [%2], %0\n"
+" brlz,pn %0, 2f\n"
+"4: add %0, 1, %1\n"
+" cas [%2], %0, %1\n"
+" cmp %0, %1\n"
+" membar #StoreLoad | #StoreStore\n"
+" bne,pn %%icc, 1b\n"
+" nop\n"
+" .subsection 2\n"
+"2: ldsw [%2], %0\n"
+" membar #LoadLoad\n"
+" brlz,pt %0, 2b\n"
+" nop\n"
+" ba,a,pt %%xcc, 4b\n"
+" .previous"
+ : "=&r" (tmp1), "=&r" (tmp2)
+ : "r" (lock)
+ : "memory");
+}
+
+static int inline __read_trylock(raw_rwlock_t *lock)
+{
+ int tmp1, tmp2;
+
+ __asm__ __volatile__ (
+"1: ldsw [%2], %0\n"
+" brlz,a,pn %0, 2f\n"
+" mov 0, %0\n"
+" add %0, 1, %1\n"
+" cas [%2], %0, %1\n"
+" cmp %0, %1\n"
+" membar #StoreLoad | #StoreStore\n"
+" bne,pn %%icc, 1b\n"
+" mov 1, %0\n"
+"2:"
+ : "=&r" (tmp1), "=&r" (tmp2)
+ : "r" (lock)
+ : "memory");
+
+ return tmp1;
+}
+
+static void inline __read_unlock(raw_rwlock_t *lock)
+{
+ unsigned long tmp1, tmp2;
+
+ __asm__ __volatile__(
+" membar #StoreLoad | #LoadLoad\n"
+"1: lduw [%2], %0\n"
+" sub %0, 1, %1\n"
+" cas [%2], %0, %1\n"
+" cmp %0, %1\n"
+" bne,pn %%xcc, 1b\n"
+" nop"
+ : "=&r" (tmp1), "=&r" (tmp2)
+ : "r" (lock)
+ : "memory");
+}
+
+static void inline __write_lock(raw_rwlock_t *lock)
+{
+ unsigned long mask, tmp1, tmp2;
+
+ mask = 0x80000000UL;
+
+ __asm__ __volatile__(
+"1: lduw [%2], %0\n"
+" brnz,pn %0, 2f\n"
+"4: or %0, %3, %1\n"
+" cas [%2], %0, %1\n"
+" cmp %0, %1\n"
+" membar #StoreLoad | #StoreStore\n"
+" bne,pn %%icc, 1b\n"
+" nop\n"
+" .subsection 2\n"
+"2: lduw [%2], %0\n"
+" membar #LoadLoad\n"
+" brnz,pt %0, 2b\n"
+" nop\n"
+" ba,a,pt %%xcc, 4b\n"
+" .previous"
+ : "=&r" (tmp1), "=&r" (tmp2)
+ : "r" (lock), "r" (mask)
+ : "memory");
+}
+
+static void inline __write_unlock(raw_rwlock_t *lock)
+{
+ __asm__ __volatile__(
+" membar #LoadStore | #StoreStore\n"
+" stw %%g0, [%0]"
+ : /* no outputs */
+ : "r" (lock)
+ : "memory");
+}
+
+static int inline __write_trylock(raw_rwlock_t *lock)
+{
+ unsigned long mask, tmp1, tmp2, result;
+
+ mask = 0x80000000UL;
+
+ __asm__ __volatile__(
+" mov 0, %2\n"
+"1: lduw [%3], %0\n"
+" brnz,pn %0, 2f\n"
+" or %0, %4, %1\n"
+" cas [%3], %0, %1\n"
+" cmp %0, %1\n"
+" membar #StoreLoad | #StoreStore\n"
+" bne,pn %%icc, 1b\n"
+" nop\n"
+" mov 1, %2\n"
+"2:"
+ : "=&r" (tmp1), "=&r" (tmp2), "=&r" (result)
+ : "r" (lock), "r" (mask)
+ : "memory");
+
+ return result;
+}
+
+#define __raw_read_lock(p) __read_lock(p)
+#define __raw_read_trylock(p) __read_trylock(p)
+#define __raw_read_unlock(p) __read_unlock(p)
+#define __raw_write_lock(p) __write_lock(p)
+#define __raw_write_unlock(p) __write_unlock(p)
+#define __raw_write_trylock(p) __write_trylock(p)
+
+#define __raw_read_can_lock(rw) (!((rw)->lock & 0x80000000UL))
+#define __raw_write_can_lock(rw) (!(rw)->lock)
+
+#define _raw_spin_relax(lock) cpu_relax()
+#define _raw_read_relax(lock) cpu_relax()
+#define _raw_write_relax(lock) cpu_relax()
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__SPARC64_SPINLOCK_H) */
--- /dev/null
+#ifndef __SPARC_SPINLOCK_TYPES_H
+#define __SPARC_SPINLOCK_TYPES_H
+
+#ifndef __LINUX_SPINLOCK_TYPES_H
+# error "please don't include this file directly"
+#endif
+
+typedef struct {
+ volatile unsigned char lock;
+} raw_spinlock_t;
+
+#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
+
+typedef struct {
+ volatile unsigned int lock;
+} raw_rwlock_t;
+
+#define __RAW_RW_LOCK_UNLOCKED { 0 }
+
+#endif
--- /dev/null
+/* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC64_SPITFIRE_H
+#define _SPARC64_SPITFIRE_H
+
+#include <asm/asi.h>
+
+/* The following register addresses are accessible via ASI_DMMU
+ * and ASI_IMMU, that is there is a distinct and unique copy of
+ * each these registers for each TLB.
+ */
+#define TSB_TAG_TARGET 0x0000000000000000 /* All chips */
+#define TLB_SFSR 0x0000000000000018 /* All chips */
+#define TSB_REG 0x0000000000000028 /* All chips */
+#define TLB_TAG_ACCESS 0x0000000000000030 /* All chips */
+#define VIRT_WATCHPOINT 0x0000000000000038 /* All chips */
+#define PHYS_WATCHPOINT 0x0000000000000040 /* All chips */
+#define TSB_EXTENSION_P 0x0000000000000048 /* Ultra-III and later */
+#define TSB_EXTENSION_S 0x0000000000000050 /* Ultra-III and later, D-TLB only */
+#define TSB_EXTENSION_N 0x0000000000000058 /* Ultra-III and later */
+#define TLB_TAG_ACCESS_EXT 0x0000000000000060 /* Ultra-III+ and later */
+
+/* These registers only exist as one entity, and are accessed
+ * via ASI_DMMU only.
+ */
+#define PRIMARY_CONTEXT 0x0000000000000008
+#define SECONDARY_CONTEXT 0x0000000000000010
+#define DMMU_SFAR 0x0000000000000020
+#define VIRT_WATCHPOINT 0x0000000000000038
+#define PHYS_WATCHPOINT 0x0000000000000040
+
+#define SPITFIRE_HIGHEST_LOCKED_TLBENT (64 - 1)
+#define CHEETAH_HIGHEST_LOCKED_TLBENT (16 - 1)
+
+#define L1DCACHE_SIZE 0x4000
+
+#define SUN4V_CHIP_INVALID 0x00
+#define SUN4V_CHIP_NIAGARA1 0x01
+#define SUN4V_CHIP_NIAGARA2 0x02
+#define SUN4V_CHIP_UNKNOWN 0xff
+
+#ifndef __ASSEMBLY__
+
+enum ultra_tlb_layout {
+ spitfire = 0,
+ cheetah = 1,
+ cheetah_plus = 2,
+ hypervisor = 3,
+};
+
+extern enum ultra_tlb_layout tlb_type;
+
+extern int sun4v_chip_type;
+
+extern int cheetah_pcache_forced_on;
+extern void cheetah_enable_pcache(void);
+
+#define sparc64_highest_locked_tlbent() \
+ (tlb_type == spitfire ? \
+ SPITFIRE_HIGHEST_LOCKED_TLBENT : \
+ CHEETAH_HIGHEST_LOCKED_TLBENT)
+
+extern int num_kernel_image_mappings;
+
+/* The data cache is write through, so this just invalidates the
+ * specified line.
+ */
+static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
+{
+ __asm__ __volatile__("stxa %0, [%1] %2\n\t"
+ "membar #Sync"
+ : /* No outputs */
+ : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
+}
+
+/* The instruction cache lines are flushed with this, but note that
+ * this does not flush the pipeline. It is possible for a line to
+ * get flushed but stale instructions to still be in the pipeline,
+ * a flush instruction (to any address) is sufficient to handle
+ * this issue after the line is invalidated.
+ */
+static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
+{
+ __asm__ __volatile__("stxa %0, [%1] %2\n\t"
+ "membar #Sync"
+ : /* No outputs */
+ : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
+}
+
+static inline unsigned long spitfire_get_dtlb_data(int entry)
+{
+ unsigned long data;
+
+ __asm__ __volatile__("ldxa [%1] %2, %0"
+ : "=r" (data)
+ : "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS));
+
+ /* Clear TTE diag bits. */
+ data &= ~0x0003fe0000000000UL;
+
+ return data;
+}
+
+static inline unsigned long spitfire_get_dtlb_tag(int entry)
+{
+ unsigned long tag;
+
+ __asm__ __volatile__("ldxa [%1] %2, %0"
+ : "=r" (tag)
+ : "r" (entry << 3), "i" (ASI_DTLB_TAG_READ));
+ return tag;
+}
+
+static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
+{
+ __asm__ __volatile__("stxa %0, [%1] %2\n\t"
+ "membar #Sync"
+ : /* No outputs */
+ : "r" (data), "r" (entry << 3),
+ "i" (ASI_DTLB_DATA_ACCESS));
+}
+
+static inline unsigned long spitfire_get_itlb_data(int entry)
+{
+ unsigned long data;
+
+ __asm__ __volatile__("ldxa [%1] %2, %0"
+ : "=r" (data)
+ : "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS));
+
+ /* Clear TTE diag bits. */
+ data &= ~0x0003fe0000000000UL;
+
+ return data;
+}
+
+static inline unsigned long spitfire_get_itlb_tag(int entry)
+{
+ unsigned long tag;
+
+ __asm__ __volatile__("ldxa [%1] %2, %0"
+ : "=r" (tag)
+ : "r" (entry << 3), "i" (ASI_ITLB_TAG_READ));
+ return tag;
+}
+
+static inline void spitfire_put_itlb_data(int entry, unsigned long data)
+{
+ __asm__ __volatile__("stxa %0, [%1] %2\n\t"
+ "membar #Sync"
+ : /* No outputs */
+ : "r" (data), "r" (entry << 3),
+ "i" (ASI_ITLB_DATA_ACCESS));
+}
+
+static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
+{
+ __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
+ "membar #Sync"
+ : /* No outputs */
+ : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
+}
+
+static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
+{
+ __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
+ "membar #Sync"
+ : /* No outputs */
+ : "r" (page | 0x20), "i" (ASI_IMMU_DEMAP));
+}
+
+/* Cheetah has "all non-locked" tlb flushes. */
+static inline void cheetah_flush_dtlb_all(void)
+{
+ __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
+ "membar #Sync"
+ : /* No outputs */
+ : "r" (0x80), "i" (ASI_DMMU_DEMAP));
+}
+
+static inline void cheetah_flush_itlb_all(void)
+{
+ __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
+ "membar #Sync"
+ : /* No outputs */
+ : "r" (0x80), "i" (ASI_IMMU_DEMAP));
+}
+
+/* Cheetah has a 4-tlb layout so direct access is a bit different.
+ * The first two TLBs are fully assosciative, hold 16 entries, and are
+ * used only for locked and >8K sized translations. One exists for
+ * data accesses and one for instruction accesses.
+ *
+ * The third TLB is for data accesses to 8K non-locked translations, is
+ * 2 way assosciative, and holds 512 entries. The fourth TLB is for
+ * instruction accesses to 8K non-locked translations, is 2 way
+ * assosciative, and holds 128 entries.
+ *
+ * Cheetah has some bug where bogus data can be returned from
+ * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
+ * the problem for me. -DaveM
+ */
+static inline unsigned long cheetah_get_ldtlb_data(int entry)
+{
+ unsigned long data;
+
+ __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
+ "ldxa [%1] %2, %0"
+ : "=r" (data)
+ : "r" ((0 << 16) | (entry << 3)),
+ "i" (ASI_DTLB_DATA_ACCESS));
+
+ return data;
+}
+
+static inline unsigned long cheetah_get_litlb_data(int entry)
+{
+ unsigned long data;
+
+ __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
+ "ldxa [%1] %2, %0"
+ : "=r" (data)
+ : "r" ((0 << 16) | (entry << 3)),
+ "i" (ASI_ITLB_DATA_ACCESS));
+
+ return data;
+}
+
+static inline unsigned long cheetah_get_ldtlb_tag(int entry)
+{
+ unsigned long tag;
+
+ __asm__ __volatile__("ldxa [%1] %2, %0"
+ : "=r" (tag)
+ : "r" ((0 << 16) | (entry << 3)),
+ "i" (ASI_DTLB_TAG_READ));
+
+ return tag;
+}
+
+static inline unsigned long cheetah_get_litlb_tag(int entry)
+{
+ unsigned long tag;
+
+ __asm__ __volatile__("ldxa [%1] %2, %0"
+ : "=r" (tag)
+ : "r" ((0 << 16) | (entry << 3)),
+ "i" (ASI_ITLB_TAG_READ));
+
+ return tag;
+}
+
+static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
+{
+ __asm__ __volatile__("stxa %0, [%1] %2\n\t"
+ "membar #Sync"
+ : /* No outputs */
+ : "r" (data),
+ "r" ((0 << 16) | (entry << 3)),
+ "i" (ASI_DTLB_DATA_ACCESS));
+}
+
+static inline void cheetah_put_litlb_data(int entry, unsigned long data)
+{
+ __asm__ __volatile__("stxa %0, [%1] %2\n\t"
+ "membar #Sync"
+ : /* No outputs */
+ : "r" (data),
+ "r" ((0 << 16) | (entry << 3)),
+ "i" (ASI_ITLB_DATA_ACCESS));
+}
+
+static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
+{
+ unsigned long data;
+
+ __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
+ "ldxa [%1] %2, %0"
+ : "=r" (data)
+ : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS));
+
+ return data;
+}
+
+static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
+{
+ unsigned long tag;
+
+ __asm__ __volatile__("ldxa [%1] %2, %0"
+ : "=r" (tag)
+ : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ));
+ return tag;
+}
+
+static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
+{
+ __asm__ __volatile__("stxa %0, [%1] %2\n\t"
+ "membar #Sync"
+ : /* No outputs */
+ : "r" (data),
+ "r" ((tlb << 16) | (entry << 3)),
+ "i" (ASI_DTLB_DATA_ACCESS));
+}
+
+static inline unsigned long cheetah_get_itlb_data(int entry)
+{
+ unsigned long data;
+
+ __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
+ "ldxa [%1] %2, %0"
+ : "=r" (data)
+ : "r" ((2 << 16) | (entry << 3)),
+ "i" (ASI_ITLB_DATA_ACCESS));
+
+ return data;
+}
+
+static inline unsigned long cheetah_get_itlb_tag(int entry)
+{
+ unsigned long tag;
+
+ __asm__ __volatile__("ldxa [%1] %2, %0"
+ : "=r" (tag)
+ : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ));
+ return tag;
+}
+
+static inline void cheetah_put_itlb_data(int entry, unsigned long data)
+{
+ __asm__ __volatile__("stxa %0, [%1] %2\n\t"
+ "membar #Sync"
+ : /* No outputs */
+ : "r" (data), "r" ((2 << 16) | (entry << 3)),
+ "i" (ASI_ITLB_DATA_ACCESS));
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC64_SPITFIRE_H) */
--- /dev/null
+#ifndef _SPARC64_SSTATE_H
+#define _SPARC64_SSTATE_H
+
+extern void sstate_booting(void);
+extern void sstate_running(void);
+extern void sstate_halt(void);
+extern void sstate_poweroff(void);
+extern void sstate_panic(void);
+extern void sstate_reboot(void);
+
+extern void sun4v_sstate_init(void);
+
+#endif /* _SPARC64_SSTATE_H */
--- /dev/null
+#ifndef _SPARC64_STACKTRACE_H
+#define _SPARC64_STACKTRACE_H
+
+extern void stack_trace_flush(void);
+
+#endif /* _SPARC64_STACKTRACE_H */
--- /dev/null
+/*
+ * starfire.h: Group all starfire specific code together.
+ *
+ * Copyright (C) 2000 Anton Blanchard (anton@samba.org)
+ */
+
+#ifndef _SPARC64_STARFIRE_H
+#define _SPARC64_STARFIRE_H
+
+#ifndef __ASSEMBLY__
+
+extern int this_is_starfire;
+
+extern void check_if_starfire(void);
+extern void starfire_cpu_setup(void);
+extern int starfire_hard_smp_processor_id(void);
+extern void starfire_hookup(int);
+extern unsigned int starfire_translate(unsigned long imap, unsigned int upaid);
+
+#endif
+#endif
--- /dev/null
+#ifndef ___ASM_SPARC_STAT_H
+#define ___ASM_SPARC_STAT_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/stat_64.h>
+#else
+#include <asm/stat_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _SPARC_STAT_H
+#define _SPARC_STAT_H
+
+#include <linux/types.h>
+
+struct __old_kernel_stat {
+ unsigned short st_dev;
+ unsigned short st_ino;
+ unsigned short st_mode;
+ unsigned short st_nlink;
+ unsigned short st_uid;
+ unsigned short st_gid;
+ unsigned short st_rdev;
+ unsigned long st_size;
+ unsigned long st_atime;
+ unsigned long st_mtime;
+ unsigned long st_ctime;
+};
+
+struct stat {
+ unsigned short st_dev;
+ unsigned long st_ino;
+ unsigned short st_mode;
+ short st_nlink;
+ unsigned short st_uid;
+ unsigned short st_gid;
+ unsigned short st_rdev;
+ long st_size;
+ long st_atime;
+ unsigned long st_atime_nsec;
+ long st_mtime;
+ unsigned long st_mtime_nsec;
+ long st_ctime;
+ unsigned long st_ctime_nsec;
+ long st_blksize;
+ long st_blocks;
+ unsigned long __unused4[2];
+};
+
+#define STAT_HAVE_NSEC 1
+
+struct stat64 {
+ unsigned long long st_dev;
+
+ unsigned long long st_ino;
+
+ unsigned int st_mode;
+ unsigned int st_nlink;
+
+ unsigned int st_uid;
+ unsigned int st_gid;
+
+ unsigned long long st_rdev;
+
+ unsigned char __pad3[8];
+
+ long long st_size;
+ unsigned int st_blksize;
+
+ unsigned char __pad4[8];
+ unsigned int st_blocks;
+
+ unsigned int st_atime;
+ unsigned int st_atime_nsec;
+
+ unsigned int st_mtime;
+ unsigned int st_mtime_nsec;
+
+ unsigned int st_ctime;
+ unsigned int st_ctime_nsec;
+
+ unsigned int __unused4;
+ unsigned int __unused5;
+};
+
+#endif
--- /dev/null
+#ifndef _SPARC64_STAT_H
+#define _SPARC64_STAT_H
+
+#include <linux/types.h>
+
+struct stat {
+ unsigned st_dev;
+ ino_t st_ino;
+ mode_t st_mode;
+ short st_nlink;
+ uid_t st_uid;
+ gid_t st_gid;
+ unsigned st_rdev;
+ off_t st_size;
+ time_t st_atime;
+ time_t st_mtime;
+ time_t st_ctime;
+ off_t st_blksize;
+ off_t st_blocks;
+ unsigned long __unused4[2];
+};
+
+struct stat64 {
+ unsigned long st_dev;
+ unsigned long st_ino;
+ unsigned long st_nlink;
+
+ unsigned int st_mode;
+ unsigned int st_uid;
+ unsigned int st_gid;
+ unsigned int __pad0;
+
+ unsigned long st_rdev;
+ long st_size;
+ long st_blksize;
+ long st_blocks;
+
+ unsigned long st_atime;
+ unsigned long st_atime_nsec;
+ unsigned long st_mtime;
+ unsigned long st_mtime_nsec;
+ unsigned long st_ctime;
+ unsigned long st_ctime_nsec;
+ long __unused[3];
+};
+
+#endif
--- /dev/null
+#ifndef ___ASM_SPARC_STATFS_H
+#define ___ASM_SPARC_STATFS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/statfs_64.h>
+#else
+#include <asm/statfs_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _SPARC_STATFS_H
+#define _SPARC_STATFS_H
+
+#include <asm-generic/statfs.h>
+
+#endif
--- /dev/null
+#ifndef _SPARC64_STATFS_H
+#define _SPARC64_STATFS_H
+
+#ifndef __KERNEL_STRICT_NAMES
+
+#include <linux/types.h>
+
+typedef __kernel_fsid_t fsid_t;
+
+#endif
+
+struct statfs {
+ long f_type;
+ long f_bsize;
+ long f_blocks;
+ long f_bfree;
+ long f_bavail;
+ long f_files;
+ long f_ffree;
+ __kernel_fsid_t f_fsid;
+ long f_namelen;
+ long f_frsize;
+ long f_spare[5];
+};
+
+struct statfs64 {
+ long f_type;
+ long f_bsize;
+ long f_blocks;
+ long f_bfree;
+ long f_bavail;
+ long f_files;
+ long f_ffree;
+ __kernel_fsid_t f_fsid;
+ long f_namelen;
+ long f_frsize;
+ long f_spare[5];
+};
+
+struct compat_statfs64 {
+ __u32 f_type;
+ __u32 f_bsize;
+ __u64 f_blocks;
+ __u64 f_bfree;
+ __u64 f_bavail;
+ __u64 f_files;
+ __u64 f_ffree;
+ __kernel_fsid_t f_fsid;
+ __u32 f_namelen;
+ __u32 f_frsize;
+ __u32 f_spare[5];
+};
+
+#endif
--- /dev/null
+#ifndef ___ASM_SPARC_STRING_H
+#define ___ASM_SPARC_STRING_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/string_64.h>
+#else
+#include <asm/string_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * string.h: External definitions for optimized assembly string
+ * routines for the Linux Kernel.
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+
+#ifndef __SPARC_STRING_H__
+#define __SPARC_STRING_H__
+
+#include <asm/page.h>
+
+/* Really, userland/ksyms should not see any of this stuff. */
+
+#ifdef __KERNEL__
+
+extern void __memmove(void *,const void *,__kernel_size_t);
+extern __kernel_size_t __memcpy(void *,const void *,__kernel_size_t);
+extern __kernel_size_t __memset(void *,int,__kernel_size_t);
+
+#ifndef EXPORT_SYMTAB_STROPS
+
+/* First the mem*() things. */
+#define __HAVE_ARCH_MEMMOVE
+#undef memmove
+#define memmove(_to, _from, _n) \
+({ \
+ void *_t = (_to); \
+ __memmove(_t, (_from), (_n)); \
+ _t; \
+})
+
+#define __HAVE_ARCH_MEMCPY
+
+static inline void *__constant_memcpy(void *to, const void *from, __kernel_size_t n)
+{
+ extern void __copy_1page(void *, const void *);
+
+ if(n <= 32) {
+ __builtin_memcpy(to, from, n);
+ } else if (((unsigned int) to & 7) != 0) {
+ /* Destination is not aligned on the double-word boundary */
+ __memcpy(to, from, n);
+ } else {
+ switch(n) {
+ case PAGE_SIZE:
+ __copy_1page(to, from);
+ break;
+ default:
+ __memcpy(to, from, n);
+ break;
+ }
+ }
+ return to;
+}
+
+static inline void *__nonconstant_memcpy(void *to, const void *from, __kernel_size_t n)
+{
+ __memcpy(to, from, n);
+ return to;
+}
+
+#undef memcpy
+#define memcpy(t, f, n) \
+(__builtin_constant_p(n) ? \
+ __constant_memcpy((t),(f),(n)) : \
+ __nonconstant_memcpy((t),(f),(n)))
+
+#define __HAVE_ARCH_MEMSET
+
+static inline void *__constant_c_and_count_memset(void *s, char c, __kernel_size_t count)
+{
+ extern void bzero_1page(void *);
+ extern __kernel_size_t __bzero(void *, __kernel_size_t);
+
+ if(!c) {
+ if(count == PAGE_SIZE)
+ bzero_1page(s);
+ else
+ __bzero(s, count);
+ } else {
+ __memset(s, c, count);
+ }
+ return s;
+}
+
+static inline void *__constant_c_memset(void *s, char c, __kernel_size_t count)
+{
+ extern __kernel_size_t __bzero(void *, __kernel_size_t);
+
+ if(!c)
+ __bzero(s, count);
+ else
+ __memset(s, c, count);
+ return s;
+}
+
+static inline void *__nonconstant_memset(void *s, char c, __kernel_size_t count)
+{
+ __memset(s, c, count);
+ return s;
+}
+
+#undef memset
+#define memset(s, c, count) \
+(__builtin_constant_p(c) ? (__builtin_constant_p(count) ? \
+ __constant_c_and_count_memset((s), (c), (count)) : \
+ __constant_c_memset((s), (c), (count))) \
+ : __nonconstant_memset((s), (c), (count)))
+
+#define __HAVE_ARCH_MEMSCAN
+
+#undef memscan
+#define memscan(__arg0, __char, __arg2) \
+({ \
+ extern void *__memscan_zero(void *, size_t); \
+ extern void *__memscan_generic(void *, int, size_t); \
+ void *__retval, *__addr = (__arg0); \
+ size_t __size = (__arg2); \
+ \
+ if(__builtin_constant_p(__char) && !(__char)) \
+ __retval = __memscan_zero(__addr, __size); \
+ else \
+ __retval = __memscan_generic(__addr, (__char), __size); \
+ \
+ __retval; \
+})
+
+#define __HAVE_ARCH_MEMCMP
+extern int memcmp(const void *,const void *,__kernel_size_t);
+
+/* Now the str*() stuff... */
+#define __HAVE_ARCH_STRLEN
+extern __kernel_size_t strlen(const char *);
+
+#define __HAVE_ARCH_STRNCMP
+
+extern int __strncmp(const char *, const char *, __kernel_size_t);
+
+static inline int __constant_strncmp(const char *src, const char *dest, __kernel_size_t count)
+{
+ register int retval;
+ switch(count) {
+ case 0: return 0;
+ case 1: return (src[0] - dest[0]);
+ case 2: retval = (src[0] - dest[0]);
+ if(!retval && src[0])
+ retval = (src[1] - dest[1]);
+ return retval;
+ case 3: retval = (src[0] - dest[0]);
+ if(!retval && src[0]) {
+ retval = (src[1] - dest[1]);
+ if(!retval && src[1])
+ retval = (src[2] - dest[2]);
+ }
+ return retval;
+ case 4: retval = (src[0] - dest[0]);
+ if(!retval && src[0]) {
+ retval = (src[1] - dest[1]);
+ if(!retval && src[1]) {
+ retval = (src[2] - dest[2]);
+ if (!retval && src[2])
+ retval = (src[3] - dest[3]);
+ }
+ }
+ return retval;
+ case 5: retval = (src[0] - dest[0]);
+ if(!retval && src[0]) {
+ retval = (src[1] - dest[1]);
+ if(!retval && src[1]) {
+ retval = (src[2] - dest[2]);
+ if (!retval && src[2]) {
+ retval = (src[3] - dest[3]);
+ if (!retval && src[3])
+ retval = (src[4] - dest[4]);
+ }
+ }
+ }
+ return retval;
+ default:
+ retval = (src[0] - dest[0]);
+ if(!retval && src[0]) {
+ retval = (src[1] - dest[1]);
+ if(!retval && src[1]) {
+ retval = (src[2] - dest[2]);
+ if(!retval && src[2])
+ retval = __strncmp(src+3,dest+3,count-3);
+ }
+ }
+ return retval;
+ }
+}
+
+#undef strncmp
+#define strncmp(__arg0, __arg1, __arg2) \
+(__builtin_constant_p(__arg2) ? \
+ __constant_strncmp(__arg0, __arg1, __arg2) : \
+ __strncmp(__arg0, __arg1, __arg2))
+
+#endif /* !EXPORT_SYMTAB_STROPS */
+
+#endif /* __KERNEL__ */
+
+#endif /* !(__SPARC_STRING_H__) */
--- /dev/null
+/*
+ * string.h: External definitions for optimized assembly string
+ * routines for the Linux Kernel.
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996,1997,1999 Jakub Jelinek (jakub@redhat.com)
+ */
+
+#ifndef __SPARC64_STRING_H__
+#define __SPARC64_STRING_H__
+
+/* Really, userland/ksyms should not see any of this stuff. */
+
+#ifdef __KERNEL__
+
+#include <asm/asi.h>
+
+extern void *__memset(void *,int,__kernel_size_t);
+
+#ifndef EXPORT_SYMTAB_STROPS
+
+/* First the mem*() things. */
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void *__builtin_memset(void *,int,__kernel_size_t);
+
+static inline void *__constant_memset(void *s, int c, __kernel_size_t count)
+{
+ extern __kernel_size_t __bzero(void *, __kernel_size_t);
+
+ if (!c) {
+ __bzero(s, count);
+ return s;
+ } else
+ return __memset(s, c, count);
+}
+
+#undef memset
+#define memset(s, c, count) \
+((__builtin_constant_p(count) && (count) <= 32) ? \
+ __builtin_memset((s), (c), (count)) : \
+ (__builtin_constant_p(c) ? \
+ __constant_memset((s), (c), (count)) : \
+ __memset((s), (c), (count))))
+
+#define __HAVE_ARCH_MEMSCAN
+
+#undef memscan
+#define memscan(__arg0, __char, __arg2) \
+({ \
+ extern void *__memscan_zero(void *, size_t); \
+ extern void *__memscan_generic(void *, int, size_t); \
+ void *__retval, *__addr = (__arg0); \
+ size_t __size = (__arg2); \
+ \
+ if(__builtin_constant_p(__char) && !(__char)) \
+ __retval = __memscan_zero(__addr, __size); \
+ else \
+ __retval = __memscan_generic(__addr, (__char), __size); \
+ \
+ __retval; \
+})
+
+#define __HAVE_ARCH_MEMCMP
+extern int memcmp(const void *,const void *,__kernel_size_t);
+
+/* Now the str*() stuff... */
+#define __HAVE_ARCH_STRLEN
+extern __kernel_size_t strlen(const char *);
+
+#define __HAVE_ARCH_STRNCMP
+extern int strncmp(const char *, const char *, __kernel_size_t);
+
+#endif /* !EXPORT_SYMTAB_STROPS */
+
+#endif /* __KERNEL__ */
+
+#endif /* !(__SPARC64_STRING_H__) */
--- /dev/null
+/*
+ * sun4paddr.h: Various physical addresses on sun4 machines
+ *
+ * Copyright (C) 1997 Anton Blanchard (anton@progsoc.uts.edu.au)
+ * Copyright (C) 1998 Chris Davis (cdavis@cois.on.ca)
+ *
+ * Now supports more sun4's
+ */
+
+#ifndef _SPARC_SUN4PADDR_H
+#define _SPARC_SUN4PADDR_H
+
+#define SUN4_IE_PHYSADDR 0xf5000000
+#define SUN4_UNUSED_PHYSADDR 0
+
+/* these work for me */
+#define SUN4_200_MEMREG_PHYSADDR 0xf4000000
+#define SUN4_200_CLOCK_PHYSADDR 0xf3000000
+#define SUN4_200_BWTWO_PHYSADDR 0xfd000000
+#define SUN4_200_ETH_PHYSADDR 0xf6000000
+#define SUN4_200_SI_PHYSADDR 0xff200000
+
+/* these were here before */
+#define SUN4_300_MEMREG_PHYSADDR 0xf4000000
+#define SUN4_300_CLOCK_PHYSADDR 0xf2000000
+#define SUN4_300_TIMER_PHYSADDR 0xef000000
+#define SUN4_300_ETH_PHYSADDR 0xf9000000
+#define SUN4_300_BWTWO_PHYSADDR 0xfb400000
+#define SUN4_300_DMA_PHYSADDR 0xfa001000
+#define SUN4_300_ESP_PHYSADDR 0xfa000000
+
+/* Are these right? */
+#define SUN4_400_MEMREG_PHYSADDR 0xf4000000
+#define SUN4_400_CLOCK_PHYSADDR 0xf2000000
+#define SUN4_400_TIMER_PHYSADDR 0xef000000
+#define SUN4_400_ETH_PHYSADDR 0xf9000000
+#define SUN4_400_BWTWO_PHYSADDR 0xfb400000
+#define SUN4_400_DMA_PHYSADDR 0xfa001000
+#define SUN4_400_ESP_PHYSADDR 0xfa000000
+
+/*
+ these are the actual values set and used in the code. Unused items set
+ to SUN_UNUSED_PHYSADDR
+ */
+
+extern int sun4_memreg_physaddr; /* memory register (ecc?) */
+extern int sun4_clock_physaddr; /* system clock */
+extern int sun4_timer_physaddr; /* timer, where applicable */
+extern int sun4_eth_physaddr; /* onboard ethernet (ie/le) */
+extern int sun4_si_physaddr; /* sun3 scsi adapter */
+extern int sun4_bwtwo_physaddr; /* onboard bw2 */
+extern int sun4_dma_physaddr; /* scsi dma */
+extern int sun4_esp_physaddr; /* esp scsi */
+extern int sun4_ie_physaddr; /* interrupt enable */
+
+#endif /* !(_SPARC_SUN4PADDR_H) */
--- /dev/null
+/*
+ * sun4prom.h -- interface to sun4 PROM monitor. We don't use most of this,
+ * so most of these are just placeholders.
+ */
+
+#ifndef _SUN4PROM_H_
+#define _SUN4PROM_H_
+
+/*
+ * Although this looks similar to an romvec for a OpenProm machine, it is
+ * actually closer to what was used in the Sun2 and Sun3.
+ *
+ * V2 entries exist only in version 2 PROMs and later, V3 in version 3 and later.
+ *
+ * Many of the function prototypes are guesses. Some are certainly wrong.
+ * Use with care.
+ */
+
+typedef struct {
+ char *initSP; /* Initial system stack ptr */
+ void (*startmon)(void); /* Initial PC for hardware */
+ int *diagberr; /* Bus err handler for diags */
+ struct linux_arguments_v0 **bootParam; /* Info for bootstrapped pgm */
+ unsigned int *memorysize; /* Usable memory in bytes */
+ unsigned char (*getchar)(void); /* Get char from input device */
+ void (*putchar)(char); /* Put char to output device */
+ int (*mayget)(void); /* Maybe get char, or -1 */
+ int (*mayput)(int); /* Maybe put char, or -1 */
+ unsigned char *echo; /* Should getchar echo? */
+ unsigned char *insource; /* Input source selector */
+ unsigned char *outsink; /* Output sink selector */
+ int (*getkey)(void); /* Get next key if one exists */
+ void (*initgetkey)(void); /* Initialize get key */
+ unsigned int *translation; /* Kbd translation selector */
+ unsigned char *keybid; /* Keyboard ID byte */
+ int *screen_x; /* V2: Screen x pos (r/o) */
+ int *screen_y; /* V2: Screen y pos (r/o) */
+ struct keybuf *keybuf; /* Up/down keycode buffer */
+ char *monid; /* Monitor version ID */
+ void (*fbwritechar)(char); /* Write a character to FB */
+ int *fbAddr; /* Address of frame buffer */
+ char **font; /* Font table for FB */
+ void (*fbwritestr)(char *); /* Write string to FB */
+ void (*reboot)(char *); /* e.g. reboot("sd()vmlinux") */
+ unsigned char *linebuf; /* The line input buffer */
+ unsigned char **lineptr; /* Cur pointer into linebuf */
+ int *linesize; /* length of line in linebuf */
+ void (*getline)(char *); /* Get line from user */
+ unsigned char (*getnextchar)(void); /* Get next char from linebuf */
+ unsigned char (*peeknextchar)(void); /* Peek at next char */
+ int *fbthere; /* =1 if frame buffer there */
+ int (*getnum)(void); /* Grab hex num from line */
+ int (*printf)(char *, ...); /* See prom_printf() instead */
+ void (*printhex)(int); /* Format N digits in hex */
+ unsigned char *leds; /* RAM copy of LED register */
+ void (*setLEDs)(unsigned char *); /* Sets LED's and RAM copy */
+ void (*NMIaddr)(void *); /* Addr for level 7 vector */
+ void (*abortentry)(void); /* Entry for keyboard abort */
+ int *nmiclock; /* Counts up in msec */
+ int *FBtype; /* Frame buffer type */
+ unsigned int romvecversion; /* Version number for this romvec */
+ struct globram *globram; /* monitor global variables ??? */
+ void * kbdaddr; /* Addr of keyboard in use */
+ int *keyrinit; /* ms before kbd repeat */
+ unsigned char *keyrtick; /* ms between repetitions */
+ unsigned int *memoryavail; /* V1: Main mem usable size */
+ long *resetaddr; /* where to jump on a reset */
+ long *resetmap; /* pgmap entry for resetaddr */
+ void (*exittomon)(void); /* Exit from user program */
+ unsigned char **memorybitmap; /* V1: &{0 or &bits} */
+ void (*setcxsegmap)(int ctxt, char *va, int pmeg); /* Set seg in any context */
+ void (**vector_cmd)(void *); /* V2: Handler for 'v' cmd */
+ unsigned long *expectedtrapsig; /* V3: Location of the expected trap signal */
+ unsigned long *trapvectorbasetable; /* V3: Address of the trap vector table */
+ int unused1;
+ int unused2;
+ int unused3;
+ int unused4;
+} linux_sun4_romvec;
+
+extern linux_sun4_romvec *sun4_romvec;
+
+#endif /* _SUN4PROM_H_ */
--- /dev/null
+/*
+ * include/asm/sunbpp.h
+ */
+
+#ifndef _ASM_SPARC_SUNBPP_H
+#define _ASM_SPARC_SUNBPP_H
+
+struct bpp_regs {
+ /* DMA registers */
+ __volatile__ __u32 p_csr; /* DMA Control/Status Register */
+ __volatile__ __u32 p_addr; /* Address Register */
+ __volatile__ __u32 p_bcnt; /* Byte Count Register */
+ __volatile__ __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */
+ /* Parallel Port registers */
+ __volatile__ __u16 p_hcr; /* Hardware Configuration Register */
+ __volatile__ __u16 p_ocr; /* Operation Configuration Register */
+ __volatile__ __u8 p_dr; /* Parallel Data Register */
+ __volatile__ __u8 p_tcr; /* Transfer Control Register */
+ __volatile__ __u8 p_or; /* Output Register */
+ __volatile__ __u8 p_ir; /* Input Register */
+ __volatile__ __u16 p_icr; /* Interrupt Control Register */
+};
+
+/* P_HCR. Time is in increments of SBus clock. */
+#define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
+#define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
+#define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
+
+/* P_OCR. */
+#define P_OCR_MEM_CLR 0x8000
+#define P_OCR_DATA_SRC 0x4000 /* ) */
+#define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
+#define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
+#define P_OCR_ACK_DSEL 0x0800 /* ) */
+#define P_OCR_EN_DIAG 0x0400
+#define P_OCR_BUSY_OP 0x0200 /* Busy operation */
+#define P_OCR_ACK_OP 0x0100 /* Ack operation */
+#define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
+#define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
+#define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
+#define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
+
+/* P_TCR */
+#define P_TCR_DIR 0x08
+#define P_TCR_BUSY 0x04
+#define P_TCR_ACK 0x02
+#define P_TCR_DS 0x01 /* Strobe */
+
+/* P_OR */
+#define P_OR_V3 0x20 /* ) */
+#define P_OR_V2 0x10 /* ) on Zebra only */
+#define P_OR_V1 0x08 /* ) */
+#define P_OR_INIT 0x04
+#define P_OR_AFXN 0x02 /* Auto Feed */
+#define P_OR_SLCT_IN 0x01
+
+/* P_IR */
+#define P_IR_PE 0x04
+#define P_IR_SLCT 0x02
+#define P_IR_ERR 0x01
+
+/* P_ICR */
+#define P_DS_IRQ 0x8000 /* RW1 */
+#define P_ACK_IRQ 0x4000 /* RW1 */
+#define P_BUSY_IRQ 0x2000 /* RW1 */
+#define P_PE_IRQ 0x1000 /* RW1 */
+#define P_SLCT_IRQ 0x0800 /* RW1 */
+#define P_ERR_IRQ 0x0400 /* RW1 */
+#define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
+#define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
+#define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
+#define P_BUSY_IRQ_EN 0x0040 /* RW */
+#define P_PE_IRP 0x0020 /* RW 1= rising edge */
+#define P_PE_IRQ_EN 0x0010 /* RW */
+#define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
+#define P_SLCT_IRQ_EN 0x0004 /* RW */
+#define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
+#define P_ERR_IRQ_EN 0x0001 /* RW */
+
+#endif /* !(_ASM_SPARC_SUNBPP_H) */
--- /dev/null
+/* swift.h: Specific definitions for the _broken_ Swift SRMMU
+ * MMU module.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_SWIFT_H
+#define _SPARC_SWIFT_H
+
+/* Swift is so brain damaged, here is the mmu control register. */
+#define SWIFT_ST 0x00800000 /* SW tablewalk enable */
+#define SWIFT_WP 0x00400000 /* Watchpoint enable */
+
+/* Branch folding (buggy, disable on production systems!) */
+#define SWIFT_BF 0x00200000
+#define SWIFT_PMC 0x00180000 /* Page mode control */
+#define SWIFT_PE 0x00040000 /* Parity enable */
+#define SWIFT_PC 0x00020000 /* Parity control */
+#define SWIFT_AP 0x00010000 /* Graphics page mode control (TCX/SX) */
+#define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
+#define SWIFT_BM 0x00004000 /* Boot mode */
+#define SWIFT_RC 0x00003c00 /* DRAM refresh control */
+#define SWIFT_IE 0x00000200 /* Instruction cache enable */
+#define SWIFT_DE 0x00000100 /* Data cache enable */
+#define SWIFT_SA 0x00000080 /* Store Allocate */
+#define SWIFT_NF 0x00000002 /* No fault mode */
+#define SWIFT_EN 0x00000001 /* MMU enable */
+
+/* Bits [13:5] select one of 512 instruction cache tags */
+static inline void swift_inv_insn_tag(unsigned long addr)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" (addr), "i" (ASI_M_TXTC_TAG)
+ : "memory");
+}
+
+/* Bits [12:4] select one of 512 data cache tags */
+static inline void swift_inv_data_tag(unsigned long addr)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" (addr), "i" (ASI_M_DATAC_TAG)
+ : "memory");
+}
+
+static inline void swift_flush_dcache(void)
+{
+ unsigned long addr;
+
+ for (addr = 0; addr < 0x2000; addr += 0x10)
+ swift_inv_data_tag(addr);
+}
+
+static inline void swift_flush_icache(void)
+{
+ unsigned long addr;
+
+ for (addr = 0; addr < 0x4000; addr += 0x20)
+ swift_inv_insn_tag(addr);
+}
+
+static inline void swift_idflash_clear(void)
+{
+ unsigned long addr;
+
+ for (addr = 0; addr < 0x2000; addr += 0x10) {
+ swift_inv_insn_tag(addr<<1);
+ swift_inv_data_tag(addr);
+ }
+}
+
+/* Swift is so broken, it isn't even safe to use the following. */
+static inline void swift_flush_page(unsigned long page)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" (page), "i" (ASI_M_FLUSH_PAGE)
+ : "memory");
+}
+
+static inline void swift_flush_segment(unsigned long addr)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" (addr), "i" (ASI_M_FLUSH_SEG)
+ : "memory");
+}
+
+static inline void swift_flush_region(unsigned long addr)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" (addr), "i" (ASI_M_FLUSH_REGION)
+ : "memory");
+}
+
+static inline void swift_flush_context(void)
+{
+ __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
+ : /* no outputs */
+ : "i" (ASI_M_FLUSH_CTX)
+ : "memory");
+}
+
+#endif /* !(_SPARC_SWIFT_H) */
--- /dev/null
+#ifndef __ASM_SPARC_SYSCALL_H
+#define __ASM_SPARC_SYSCALL_H
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <asm/ptrace.h>
+
+/* The system call number is given by the user in %g1 */
+static inline long syscall_get_nr(struct task_struct *task,
+ struct pt_regs *regs)
+{
+ int syscall_p = pt_regs_is_syscall(regs);
+
+ return (syscall_p ? regs->u_regs[UREG_G1] : -1L);
+}
+
+static inline void syscall_rollback(struct task_struct *task,
+ struct pt_regs *regs)
+{
+ /* XXX This needs some thought. On Sparc we don't
+ * XXX save away the original %o0 value somewhere.
+ * XXX Instead we hold it in register %l5 at the top
+ * XXX level trap frame and pass this down to the signal
+ * XXX dispatch code which is the only place that value
+ * XXX ever was needed.
+ */
+}
+
+#ifdef CONFIG_SPARC32
+static inline bool syscall_has_error(struct pt_regs *regs)
+{
+ return (regs->psr & PSR_C) ? true : false;
+}
+static inline void syscall_set_error(struct pt_regs *regs)
+{
+ regs->psr |= PSR_C;
+}
+static inline void syscall_clear_error(struct pt_regs *regs)
+{
+ regs->psr &= ~PSR_C;
+}
+#else
+static inline bool syscall_has_error(struct pt_regs *regs)
+{
+ return (regs->tstate & (TSTATE_XCARRY | TSTATE_ICARRY)) ? true : false;
+}
+static inline void syscall_set_error(struct pt_regs *regs)
+{
+ regs->tstate |= (TSTATE_XCARRY | TSTATE_ICARRY);
+}
+static inline void syscall_clear_error(struct pt_regs *regs)
+{
+ regs->tstate &= ~(TSTATE_XCARRY | TSTATE_ICARRY);
+}
+#endif
+
+static inline long syscall_get_error(struct task_struct *task,
+ struct pt_regs *regs)
+{
+ long val = regs->u_regs[UREG_I0];
+
+ return (syscall_has_error(regs) ? -val : 0);
+}
+
+static inline long syscall_get_return_value(struct task_struct *task,
+ struct pt_regs *regs)
+{
+ long val = regs->u_regs[UREG_I0];
+
+ return val;
+}
+
+static inline void syscall_set_return_value(struct task_struct *task,
+ struct pt_regs *regs,
+ int error, long val)
+{
+ if (error) {
+ syscall_set_error(regs);
+ regs->u_regs[UREG_I0] = -error;
+ } else {
+ syscall_clear_error(regs);
+ regs->u_regs[UREG_I0] = val;
+ }
+}
+
+static inline void syscall_get_arguments(struct task_struct *task,
+ struct pt_regs *regs,
+ unsigned int i, unsigned int n,
+ unsigned long *args)
+{
+ int zero_extend = 0;
+ unsigned int j;
+
+#ifdef CONFIG_SPARC64
+ if (test_tsk_thread_flag(task, TIF_32BIT))
+ zero_extend = 1;
+#endif
+
+ for (j = 0; j < n; j++) {
+ unsigned long val = regs->u_regs[UREG_I0 + i + j];
+
+ if (zero_extend)
+ args[j] = (u32) val;
+ else
+ args[j] = val;
+ }
+}
+
+static inline void syscall_set_arguments(struct task_struct *task,
+ struct pt_regs *regs,
+ unsigned int i, unsigned int n,
+ const unsigned long *args)
+{
+ unsigned int j;
+
+ for (j = 0; j < n; j++)
+ regs->u_regs[UREG_I0 + i + j] = args[j];
+}
+
+#endif /* __ASM_SPARC_SYSCALL_H */
--- /dev/null
+#ifndef _SPARC64_SYSCALLS_H
+#define _SPARC64_SYSCALLS_H
+
+struct pt_regs;
+
+extern asmlinkage long sparc_do_fork(unsigned long clone_flags,
+ unsigned long stack_start,
+ struct pt_regs *regs,
+ unsigned long stack_size);
+
+extern asmlinkage int sparc_execve(struct pt_regs *regs);
+
+#endif /* _SPARC64_SYSCALLS_H */
--- /dev/null
+/*
+ * sysen.h: Bit fields within the "System Enable" register accessed via
+ * the ASI_CONTROL address space at address AC_SYSENABLE.
+ *
+ * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_SYSEN_H
+#define _SPARC_SYSEN_H
+
+#define SENABLE_DVMA 0x20 /* enable dvma transfers */
+#define SENABLE_CACHE 0x10 /* enable VAC cache */
+#define SENABLE_RESET 0x04 /* reset whole machine, danger Will Robinson */
+
+#endif /* _SPARC_SYSEN_H */
--- /dev/null
+#ifndef ___ASM_SPARC_SYSTEM_H
+#define ___ASM_SPARC_SYSTEM_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/system_64.h>
+#else
+#include <asm/system_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef __SPARC_SYSTEM_H
+#define __SPARC_SYSTEM_H
+
+#include <linux/kernel.h>
+#include <linux/threads.h> /* NR_CPUS */
+#include <linux/thread_info.h>
+
+#include <asm/page.h>
+#include <asm/psr.h>
+#include <asm/ptrace.h>
+#include <asm/btfixup.h>
+#include <asm/smp.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/irqflags.h>
+
+/*
+ * Sparc (general) CPU types
+ */
+enum sparc_cpu {
+ sun4 = 0x00,
+ sun4c = 0x01,
+ sun4m = 0x02,
+ sun4d = 0x03,
+ sun4e = 0x04,
+ sun4u = 0x05, /* V8 ploos ploos */
+ sun_unknown = 0x06,
+ ap1000 = 0x07, /* almost a sun4m */
+};
+
+/* Really, userland should not be looking at any of this... */
+#ifdef __KERNEL__
+
+extern enum sparc_cpu sparc_cpu_model;
+
+#ifndef CONFIG_SUN4
+#define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
+#define ARCH_SUN4 0
+#else
+#define ARCH_SUN4C_SUN4 1
+#define ARCH_SUN4 1
+#endif
+
+#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
+
+extern char reboot_command[];
+
+extern struct thread_info *current_set[NR_CPUS];
+
+extern unsigned long empty_bad_page;
+extern unsigned long empty_bad_page_table;
+extern unsigned long empty_zero_page;
+
+extern void sun_do_break(void);
+extern int serial_console;
+extern int stop_a_enabled;
+
+static inline int con_is_present(void)
+{
+ return serial_console ? 0 : 1;
+}
+
+/* When a context switch happens we must flush all user windows so that
+ * the windows of the current process are flushed onto its stack. This
+ * way the windows are all clean for the next process and the stack
+ * frames are up to date.
+ */
+extern void flush_user_windows(void);
+extern void kill_user_windows(void);
+extern void synchronize_user_stack(void);
+extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
+ void *fpqueue, unsigned long *fpqdepth);
+
+#ifdef CONFIG_SMP
+#define SWITCH_ENTER(prv) \
+ do { \
+ if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
+ put_psr(get_psr() | PSR_EF); \
+ fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
+ &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
+ clear_tsk_thread_flag(prv, TIF_USEDFPU); \
+ (prv)->thread.kregs->psr &= ~PSR_EF; \
+ } \
+ } while(0)
+
+#define SWITCH_DO_LAZY_FPU(next) /* */
+#else
+#define SWITCH_ENTER(prv) /* */
+#define SWITCH_DO_LAZY_FPU(nxt) \
+ do { \
+ if (last_task_used_math != (nxt)) \
+ (nxt)->thread.kregs->psr&=~PSR_EF; \
+ } while(0)
+#endif
+
+extern void flushw_all(void);
+
+/*
+ * Flush windows so that the VM switch which follows
+ * would not pull the stack from under us.
+ *
+ * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
+ * XXX WTF is the above comment? Found in late teen 2.4.x.
+ */
+#define prepare_arch_switch(next) do { \
+ __asm__ __volatile__( \
+ ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
+ "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
+ "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
+ "save %sp, -0x40, %sp\n\t" \
+ "restore; restore; restore; restore; restore; restore; restore"); \
+} while(0)
+
+ /* Much care has gone into this code, do not touch it.
+ *
+ * We need to loadup regs l0/l1 for the newly forked child
+ * case because the trap return path relies on those registers
+ * holding certain values, gcc is told that they are clobbered.
+ * Gcc needs registers for 3 values in and 1 value out, so we
+ * clobber every non-fixed-usage register besides l2/l3/o4/o5. -DaveM
+ *
+ * Hey Dave, that do not touch sign is too much of an incentive
+ * - Anton & Pete
+ */
+#define switch_to(prev, next, last) do { \
+ SWITCH_ENTER(prev); \
+ SWITCH_DO_LAZY_FPU(next); \
+ cpu_set(smp_processor_id(), next->active_mm->cpu_vm_mask); \
+ __asm__ __volatile__( \
+ "sethi %%hi(here - 0x8), %%o7\n\t" \
+ "mov %%g6, %%g3\n\t" \
+ "or %%o7, %%lo(here - 0x8), %%o7\n\t" \
+ "rd %%psr, %%g4\n\t" \
+ "std %%sp, [%%g6 + %4]\n\t" \
+ "rd %%wim, %%g5\n\t" \
+ "wr %%g4, 0x20, %%psr\n\t" \
+ "nop\n\t" \
+ "std %%g4, [%%g6 + %3]\n\t" \
+ "ldd [%2 + %3], %%g4\n\t" \
+ "mov %2, %%g6\n\t" \
+ ".globl patchme_store_new_current\n" \
+"patchme_store_new_current:\n\t" \
+ "st %2, [%1]\n\t" \
+ "wr %%g4, 0x20, %%psr\n\t" \
+ "nop\n\t" \
+ "nop\n\t" \
+ "nop\n\t" /* LEON needs all 3 nops: load to %sp depends on CWP. */ \
+ "ldd [%%g6 + %4], %%sp\n\t" \
+ "wr %%g5, 0x0, %%wim\n\t" \
+ "ldd [%%sp + 0x00], %%l0\n\t" \
+ "ldd [%%sp + 0x38], %%i6\n\t" \
+ "wr %%g4, 0x0, %%psr\n\t" \
+ "nop\n\t" \
+ "nop\n\t" \
+ "jmpl %%o7 + 0x8, %%g0\n\t" \
+ " ld [%%g3 + %5], %0\n\t" \
+ "here:\n" \
+ : "=&r" (last) \
+ : "r" (&(current_set[hard_smp_processor_id()])), \
+ "r" (task_thread_info(next)), \
+ "i" (TI_KPSR), \
+ "i" (TI_KSP), \
+ "i" (TI_TASK) \
+ : "g1", "g2", "g3", "g4", "g5", "g7", \
+ "l0", "l1", "l3", "l4", "l5", "l6", "l7", \
+ "i0", "i1", "i2", "i3", "i4", "i5", \
+ "o0", "o1", "o2", "o3", "o7"); \
+ } while(0)
+
+/* XXX Change this if we ever use a PSO mode kernel. */
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+#define rmb() mb()
+#define wmb() mb()
+#define read_barrier_depends() do { } while(0)
+#define set_mb(__var, __value) do { __var = __value; mb(); } while(0)
+#define smp_mb() __asm__ __volatile__("":::"memory")
+#define smp_rmb() __asm__ __volatile__("":::"memory")
+#define smp_wmb() __asm__ __volatile__("":::"memory")
+#define smp_read_barrier_depends() do { } while(0)
+
+#define nop() __asm__ __volatile__ ("nop")
+
+/* This has special calling conventions */
+#ifndef CONFIG_SMP
+BTFIXUPDEF_CALL(void, ___xchg32, void)
+#endif
+
+static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
+{
+#ifdef CONFIG_SMP
+ __asm__ __volatile__("swap [%2], %0"
+ : "=&r" (val)
+ : "0" (val), "r" (m)
+ : "memory");
+ return val;
+#else
+ register unsigned long *ptr asm("g1");
+ register unsigned long ret asm("g2");
+
+ ptr = (unsigned long *) m;
+ ret = val;
+
+ /* Note: this is magic and the nop there is
+ really needed. */
+ __asm__ __volatile__(
+ "mov %%o7, %%g4\n\t"
+ "call ___f____xchg32\n\t"
+ " nop\n\t"
+ : "=&r" (ret)
+ : "0" (ret), "r" (ptr)
+ : "g3", "g4", "g7", "memory", "cc");
+
+ return ret;
+#endif
+}
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+extern void __xchg_called_with_bad_pointer(void);
+
+static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int size)
+{
+ switch (size) {
+ case 4:
+ return xchg_u32(ptr, x);
+ };
+ __xchg_called_with_bad_pointer();
+ return x;
+}
+
+/* Emulate cmpxchg() the same way we emulate atomics,
+ * by hashing the object address and indexing into an array
+ * of spinlocks to get a bit of performance...
+ *
+ * See arch/sparc/lib/atomic32.c for implementation.
+ *
+ * Cribbed from <asm-parisc/atomic.h>
+ */
+#define __HAVE_ARCH_CMPXCHG 1
+
+/* bug catcher for when unsupported size is used - won't link */
+extern void __cmpxchg_called_with_bad_pointer(void);
+/* we only need to support cmpxchg of a u32 on sparc */
+extern unsigned long __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_);
+
+/* don't worry...optimizer will get rid of most of this */
+static inline unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
+{
+ switch (size) {
+ case 4:
+ return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_);
+ default:
+ __cmpxchg_called_with_bad_pointer();
+ break;
+ }
+ return old;
+}
+
+#define cmpxchg(ptr, o, n) \
+({ \
+ __typeof__(*(ptr)) _o_ = (o); \
+ __typeof__(*(ptr)) _n_ = (n); \
+ (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
+ (unsigned long)_n_, sizeof(*(ptr))); \
+})
+
+#include <asm-generic/cmpxchg-local.h>
+
+/*
+ * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
+ * them available.
+ */
+#define cmpxchg_local(ptr, o, n) \
+ ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
+ (unsigned long)(n), sizeof(*(ptr))))
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+
+extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+#define arch_align_stack(x) (x)
+
+#endif /* !(__SPARC_SYSTEM_H) */
--- /dev/null
+#ifndef __SPARC64_SYSTEM_H
+#define __SPARC64_SYSTEM_H
+
+#include <asm/ptrace.h>
+#include <asm/processor.h>
+#include <asm/visasm.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/irqflags.h>
+#include <asm-generic/cmpxchg-local.h>
+
+/*
+ * Sparc (general) CPU types
+ */
+enum sparc_cpu {
+ sun4 = 0x00,
+ sun4c = 0x01,
+ sun4m = 0x02,
+ sun4d = 0x03,
+ sun4e = 0x04,
+ sun4u = 0x05, /* V8 ploos ploos */
+ sun_unknown = 0x06,
+ ap1000 = 0x07, /* almost a sun4m */
+};
+
+#define sparc_cpu_model sun4u
+
+/* This cannot ever be a sun4c nor sun4 :) That's just history. */
+#define ARCH_SUN4C_SUN4 0
+#define ARCH_SUN4 0
+
+extern char reboot_command[];
+
+/* These are here in an effort to more fully work around Spitfire Errata
+ * #51. Essentially, if a memory barrier occurs soon after a mispredicted
+ * branch, the chip can stop executing instructions until a trap occurs.
+ * Therefore, if interrupts are disabled, the chip can hang forever.
+ *
+ * It used to be believed that the memory barrier had to be right in the
+ * delay slot, but a case has been traced recently wherein the memory barrier
+ * was one instruction after the branch delay slot and the chip still hung.
+ * The offending sequence was the following in sym_wakeup_done() of the
+ * sym53c8xx_2 driver:
+ *
+ * call sym_ccb_from_dsa, 0
+ * movge %icc, 0, %l0
+ * brz,pn %o0, .LL1303
+ * mov %o0, %l2
+ * membar #LoadLoad
+ *
+ * The branch has to be mispredicted for the bug to occur. Therefore, we put
+ * the memory barrier explicitly into a "branch always, predicted taken"
+ * delay slot to avoid the problem case.
+ */
+#define membar_safe(type) \
+do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
+ " membar " type "\n" \
+ "1:\n" \
+ : : : "memory"); \
+} while (0)
+
+#define mb() \
+ membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
+#define rmb() \
+ membar_safe("#LoadLoad")
+#define wmb() \
+ membar_safe("#StoreStore")
+#define membar_storeload() \
+ membar_safe("#StoreLoad")
+#define membar_storeload_storestore() \
+ membar_safe("#StoreLoad | #StoreStore")
+#define membar_storeload_loadload() \
+ membar_safe("#StoreLoad | #LoadLoad")
+#define membar_storestore_loadstore() \
+ membar_safe("#StoreStore | #LoadStore")
+
+#endif
+
+#define nop() __asm__ __volatile__ ("nop")
+
+#define read_barrier_depends() do { } while(0)
+#define set_mb(__var, __value) \
+ do { __var = __value; membar_storeload_storestore(); } while(0)
+
+#ifdef CONFIG_SMP
+#define smp_mb() mb()
+#define smp_rmb() rmb()
+#define smp_wmb() wmb()
+#define smp_read_barrier_depends() read_barrier_depends()
+#else
+#define smp_mb() __asm__ __volatile__("":::"memory")
+#define smp_rmb() __asm__ __volatile__("":::"memory")
+#define smp_wmb() __asm__ __volatile__("":::"memory")
+#define smp_read_barrier_depends() do { } while(0)
+#endif
+
+#define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
+
+#define flushw_all() __asm__ __volatile__("flushw")
+
+/* Performance counter register access. */
+#define read_pcr(__p) __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
+#define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
+#define read_pic(__p) __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
+
+/* Blackbird errata workaround. See commentary in
+ * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
+ * for more information.
+ */
+#define reset_pic() \
+ __asm__ __volatile__("ba,pt %xcc, 99f\n\t" \
+ ".align 64\n" \
+ "99:wr %g0, 0x0, %pic\n\t" \
+ "rd %pic, %g0")
+
+#ifndef __ASSEMBLY__
+
+extern void sun_do_break(void);
+extern int stop_a_enabled;
+
+extern void fault_in_user_windows(void);
+extern void synchronize_user_stack(void);
+
+extern void __flushw_user(void);
+#define flushw_user() __flushw_user()
+
+#define flush_user_windows flushw_user
+#define flush_register_windows flushw_all
+
+/* Don't hold the runqueue lock over context switch */
+#define __ARCH_WANT_UNLOCKED_CTXSW
+#define prepare_arch_switch(next) \
+do { \
+ flushw_all(); \
+} while (0)
+
+ /* See what happens when you design the chip correctly?
+ *
+ * We tell gcc we clobber all non-fixed-usage registers except
+ * for l0/l1. It will use one for 'next' and the other to hold
+ * the output value of 'last'. 'next' is not referenced again
+ * past the invocation of switch_to in the scheduler, so we need
+ * not preserve it's value. Hairy, but it lets us remove 2 loads
+ * and 2 stores in this critical code path. -DaveM
+ */
+#define switch_to(prev, next, last) \
+do { if (test_thread_flag(TIF_PERFCTR)) { \
+ unsigned long __tmp; \
+ read_pcr(__tmp); \
+ current_thread_info()->pcr_reg = __tmp; \
+ read_pic(__tmp); \
+ current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
+ current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
+ } \
+ flush_tlb_pending(); \
+ save_and_clear_fpu(); \
+ /* If you are tempted to conditionalize the following */ \
+ /* so that ASI is only written if it changes, think again. */ \
+ __asm__ __volatile__("wr %%g0, %0, %%asi" \
+ : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
+ trap_block[current_thread_info()->cpu].thread = \
+ task_thread_info(next); \
+ __asm__ __volatile__( \
+ "mov %%g4, %%g7\n\t" \
+ "stx %%i6, [%%sp + 2047 + 0x70]\n\t" \
+ "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \
+ "rdpr %%wstate, %%o5\n\t" \
+ "stx %%o6, [%%g6 + %6]\n\t" \
+ "stb %%o5, [%%g6 + %5]\n\t" \
+ "rdpr %%cwp, %%o5\n\t" \
+ "stb %%o5, [%%g6 + %8]\n\t" \
+ "mov %4, %%g6\n\t" \
+ "ldub [%4 + %8], %%g1\n\t" \
+ "wrpr %%g1, %%cwp\n\t" \
+ "ldx [%%g6 + %6], %%o6\n\t" \
+ "ldub [%%g6 + %5], %%o5\n\t" \
+ "ldub [%%g6 + %7], %%o7\n\t" \
+ "wrpr %%o5, 0x0, %%wstate\n\t" \
+ "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \
+ "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \
+ "ldx [%%g6 + %9], %%g4\n\t" \
+ "brz,pt %%o7, switch_to_pc\n\t" \
+ " mov %%g7, %0\n\t" \
+ "sethi %%hi(ret_from_syscall), %%g1\n\t" \
+ "jmpl %%g1 + %%lo(ret_from_syscall), %%g0\n\t" \
+ " nop\n\t" \
+ ".globl switch_to_pc\n\t" \
+ "switch_to_pc:\n\t" \
+ : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \
+ "=r" (__local_per_cpu_offset) \
+ : "0" (task_thread_info(next)), \
+ "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \
+ "i" (TI_CWP), "i" (TI_TASK) \
+ : "cc", \
+ "g1", "g2", "g3", "g7", \
+ "l1", "l2", "l3", "l4", "l5", "l6", "l7", \
+ "i0", "i1", "i2", "i3", "i4", "i5", \
+ "o0", "o1", "o2", "o3", "o4", "o5", "o7"); \
+ /* If you fuck with this, update ret_from_syscall code too. */ \
+ if (test_thread_flag(TIF_PERFCTR)) { \
+ write_pcr(current_thread_info()->pcr_reg); \
+ reset_pic(); \
+ } \
+} while(0)
+
+static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
+{
+ unsigned long tmp1, tmp2;
+
+ __asm__ __volatile__(
+" membar #StoreLoad | #LoadLoad\n"
+" mov %0, %1\n"
+"1: lduw [%4], %2\n"
+" cas [%4], %2, %0\n"
+" cmp %2, %0\n"
+" bne,a,pn %%icc, 1b\n"
+" mov %1, %0\n"
+" membar #StoreLoad | #StoreStore\n"
+ : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
+ : "0" (val), "r" (m)
+ : "cc", "memory");
+ return val;
+}
+
+static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
+{
+ unsigned long tmp1, tmp2;
+
+ __asm__ __volatile__(
+" membar #StoreLoad | #LoadLoad\n"
+" mov %0, %1\n"
+"1: ldx [%4], %2\n"
+" casx [%4], %2, %0\n"
+" cmp %2, %0\n"
+" bne,a,pn %%xcc, 1b\n"
+" mov %1, %0\n"
+" membar #StoreLoad | #StoreStore\n"
+ : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
+ : "0" (val), "r" (m)
+ : "cc", "memory");
+ return val;
+}
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+extern void __xchg_called_with_bad_pointer(void);
+
+static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
+ int size)
+{
+ switch (size) {
+ case 4:
+ return xchg32(ptr, x);
+ case 8:
+ return xchg64(ptr, x);
+ };
+ __xchg_called_with_bad_pointer();
+ return x;
+}
+
+extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
+
+/*
+ * Atomic compare and exchange. Compare OLD with MEM, if identical,
+ * store NEW in MEM. Return the initial value in MEM. Success is
+ * indicated by comparing RETURN with OLD.
+ */
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+static inline unsigned long
+__cmpxchg_u32(volatile int *m, int old, int new)
+{
+ __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
+ "cas [%2], %3, %0\n\t"
+ "membar #StoreLoad | #StoreStore"
+ : "=&r" (new)
+ : "0" (new), "r" (m), "r" (old)
+ : "memory");
+
+ return new;
+}
+
+static inline unsigned long
+__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
+{
+ __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
+ "casx [%2], %3, %0\n\t"
+ "membar #StoreLoad | #StoreStore"
+ : "=&r" (new)
+ : "0" (new), "r" (m), "r" (old)
+ : "memory");
+
+ return new;
+}
+
+/* This function doesn't exist, so you'll get a linker error
+ if something tries to do an invalid cmpxchg(). */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+static inline unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
+{
+ switch (size) {
+ case 4:
+ return __cmpxchg_u32(ptr, old, new);
+ case 8:
+ return __cmpxchg_u64(ptr, old, new);
+ }
+ __cmpxchg_called_with_bad_pointer();
+ return old;
+}
+
+#define cmpxchg(ptr,o,n) \
+ ({ \
+ __typeof__(*(ptr)) _o_ = (o); \
+ __typeof__(*(ptr)) _n_ = (n); \
+ (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
+ (unsigned long)_n_, sizeof(*(ptr))); \
+ })
+
+/*
+ * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
+ * them available.
+ */
+
+static inline unsigned long __cmpxchg_local(volatile void *ptr,
+ unsigned long old,
+ unsigned long new, int size)
+{
+ switch (size) {
+ case 4:
+ case 8: return __cmpxchg(ptr, old, new, size);
+ default:
+ return __cmpxchg_local_generic(ptr, old, new, size);
+ }
+
+ return old;
+}
+
+#define cmpxchg_local(ptr, o, n) \
+ ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
+ (unsigned long)(n), sizeof(*(ptr))))
+#define cmpxchg64_local(ptr, o, n) \
+ ({ \
+ BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
+ cmpxchg_local((ptr), (o), (n)); \
+ })
+
+#endif /* !(__ASSEMBLY__) */
+
+#define arch_align_stack(x) (x)
+
+#endif /* !(__SPARC64_SYSTEM_H) */
--- /dev/null
+#ifndef _SPARC_TERMBITS_H
+#define _SPARC_TERMBITS_H
+
+#include <linux/posix_types.h>
+
+typedef unsigned char cc_t;
+typedef unsigned int speed_t;
+
+#if defined(__sparc__) && defined(__arch64__)
+typedef unsigned int tcflag_t;
+#else
+typedef unsigned long tcflag_t;
+#endif
+
+#define NCC 8
+struct termio {
+ unsigned short c_iflag; /* input mode flags */
+ unsigned short c_oflag; /* output mode flags */
+ unsigned short c_cflag; /* control mode flags */
+ unsigned short c_lflag; /* local mode flags */
+ unsigned char c_line; /* line discipline */
+ unsigned char c_cc[NCC]; /* control characters */
+};
+
+#define NCCS 17
+struct termios {
+ tcflag_t c_iflag; /* input mode flags */
+ tcflag_t c_oflag; /* output mode flags */
+ tcflag_t c_cflag; /* control mode flags */
+ tcflag_t c_lflag; /* local mode flags */
+ cc_t c_line; /* line discipline */
+ cc_t c_cc[NCCS]; /* control characters */
+#ifdef __KERNEL__
+#define SIZEOF_USER_TERMIOS sizeof (struct termios) - (2*sizeof (cc_t))
+ cc_t _x_cc[2]; /* We need them to hold vmin/vtime */
+#endif
+};
+
+struct termios2 {
+ tcflag_t c_iflag; /* input mode flags */
+ tcflag_t c_oflag; /* output mode flags */
+ tcflag_t c_cflag; /* control mode flags */
+ tcflag_t c_lflag; /* local mode flags */
+ cc_t c_line; /* line discipline */
+ cc_t c_cc[NCCS]; /* control characters */
+ cc_t _x_cc[2]; /* padding to match ktermios */
+ speed_t c_ispeed; /* input speed */
+ speed_t c_ospeed; /* output speed */
+};
+
+struct ktermios {
+ tcflag_t c_iflag; /* input mode flags */
+ tcflag_t c_oflag; /* output mode flags */
+ tcflag_t c_cflag; /* control mode flags */
+ tcflag_t c_lflag; /* local mode flags */
+ cc_t c_line; /* line discipline */
+ cc_t c_cc[NCCS]; /* control characters */
+ cc_t _x_cc[2]; /* We need them to hold vmin/vtime */
+ speed_t c_ispeed; /* input speed */
+ speed_t c_ospeed; /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR 0
+#define VQUIT 1
+#define VERASE 2
+#define VKILL 3
+#define VEOF 4
+#define VEOL 5
+#define VEOL2 6
+#define VSWTC 7
+#define VSTART 8
+#define VSTOP 9
+
+
+
+#define VSUSP 10
+#define VDSUSP 11 /* SunOS POSIX nicety I do believe... */
+#define VREPRINT 12
+#define VDISCARD 13
+#define VWERASE 14
+#define VLNEXT 15
+
+/* Kernel keeps vmin/vtime separated, user apps assume vmin/vtime is
+ * shared with eof/eol
+ */
+#ifdef __KERNEL__
+#define VMIN 16
+#define VTIME 17
+#else
+#define VMIN VEOF
+#define VTIME VEOL
+#endif
+
+/* c_iflag bits */
+#define IGNBRK 0x00000001
+#define BRKINT 0x00000002
+#define IGNPAR 0x00000004
+#define PARMRK 0x00000008
+#define INPCK 0x00000010
+#define ISTRIP 0x00000020
+#define INLCR 0x00000040
+#define IGNCR 0x00000080
+#define ICRNL 0x00000100
+#define IUCLC 0x00000200
+#define IXON 0x00000400
+#define IXANY 0x00000800
+#define IXOFF 0x00001000
+#define IMAXBEL 0x00002000
+#define IUTF8 0x00004000
+
+/* c_oflag bits */
+#define OPOST 0x00000001
+#define OLCUC 0x00000002
+#define ONLCR 0x00000004
+#define OCRNL 0x00000008
+#define ONOCR 0x00000010
+#define ONLRET 0x00000020
+#define OFILL 0x00000040
+#define OFDEL 0x00000080
+#define NLDLY 0x00000100
+#define NL0 0x00000000
+#define NL1 0x00000100
+#define CRDLY 0x00000600
+#define CR0 0x00000000
+#define CR1 0x00000200
+#define CR2 0x00000400
+#define CR3 0x00000600
+#define TABDLY 0x00001800
+#define TAB0 0x00000000
+#define TAB1 0x00000800
+#define TAB2 0x00001000
+#define TAB3 0x00001800
+#define XTABS 0x00001800
+#define BSDLY 0x00002000
+#define BS0 0x00000000
+#define BS1 0x00002000
+#define VTDLY 0x00004000
+#define VT0 0x00000000
+#define VT1 0x00004000
+#define FFDLY 0x00008000
+#define FF0 0x00000000
+#define FF1 0x00008000
+#define PAGEOUT 0x00010000 /* SUNOS specific */
+#define WRAP 0x00020000 /* SUNOS specific */
+
+/* c_cflag bit meaning */
+#define CBAUD 0x0000100f
+#define B0 0x00000000 /* hang up */
+#define B50 0x00000001
+#define B75 0x00000002
+#define B110 0x00000003
+#define B134 0x00000004
+#define B150 0x00000005
+#define B200 0x00000006
+#define B300 0x00000007
+#define B600 0x00000008
+#define B1200 0x00000009
+#define B1800 0x0000000a
+#define B2400 0x0000000b
+#define B4800 0x0000000c
+#define B9600 0x0000000d
+#define B19200 0x0000000e
+#define B38400 0x0000000f
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE 0x00000030
+#define CS5 0x00000000
+#define CS6 0x00000010
+#define CS7 0x00000020
+#define CS8 0x00000030
+#define CSTOPB 0x00000040
+#define CREAD 0x00000080
+#define PARENB 0x00000100
+#define PARODD 0x00000200
+#define HUPCL 0x00000400
+#define CLOCAL 0x00000800
+#define CBAUDEX 0x00001000
+/* We'll never see these speeds with the Zilogs, but for completeness... */
+#define BOTHER 0x00001000
+#define B57600 0x00001001
+#define B115200 0x00001002
+#define B230400 0x00001003
+#define B460800 0x00001004
+/* This is what we can do with the Zilogs. */
+#define B76800 0x00001005
+/* This is what we can do with the SAB82532. */
+#define B153600 0x00001006
+#define B307200 0x00001007
+#define B614400 0x00001008
+#define B921600 0x00001009
+/* And these are the rest... */
+#define B500000 0x0000100a
+#define B576000 0x0000100b
+#define B1000000 0x0000100c
+#define B1152000 0x0000100d
+#define B1500000 0x0000100e
+#define B2000000 0x0000100f
+/* These have totally bogus values and nobody uses them
+ so far. Later on we'd have to use say 0x10000x and
+ adjust CBAUD constant and drivers accordingly.
+#define B2500000 0x00001010
+#define B3000000 0x00001011
+#define B3500000 0x00001012
+#define B4000000 0x00001013 */
+#define CIBAUD 0x100f0000 /* input baud rate (not used) */
+#define CMSPAR 0x40000000 /* mark or space (stick) parity */
+#define CRTSCTS 0x80000000 /* flow control */
+
+#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
+
+/* c_lflag bits */
+#define ISIG 0x00000001
+#define ICANON 0x00000002
+#define XCASE 0x00000004
+#define ECHO 0x00000008
+#define ECHOE 0x00000010
+#define ECHOK 0x00000020
+#define ECHONL 0x00000040
+#define NOFLSH 0x00000080
+#define TOSTOP 0x00000100
+#define ECHOCTL 0x00000200
+#define ECHOPRT 0x00000400
+#define ECHOKE 0x00000800
+#define DEFECHO 0x00001000 /* SUNOS thing, what is it? */
+#define FLUSHO 0x00002000
+#define PENDIN 0x00004000
+#define IEXTEN 0x00008000
+
+/* modem lines */
+#define TIOCM_LE 0x001
+#define TIOCM_DTR 0x002
+#define TIOCM_RTS 0x004
+#define TIOCM_ST 0x008
+#define TIOCM_SR 0x010
+#define TIOCM_CTS 0x020
+#define TIOCM_CAR 0x040
+#define TIOCM_RNG 0x080
+#define TIOCM_DSR 0x100
+#define TIOCM_CD TIOCM_CAR
+#define TIOCM_RI TIOCM_RNG
+#define TIOCM_OUT1 0x2000
+#define TIOCM_OUT2 0x4000
+#define TIOCM_LOOP 0x8000
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
+
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF 0
+#define TCOON 1
+#define TCIOFF 2
+#define TCION 3
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH 0
+#define TCOFLUSH 1
+#define TCIOFLUSH 2
+
+/* tcsetattr uses these */
+#define TCSANOW 0
+#define TCSADRAIN 1
+#define TCSAFLUSH 2
+
+#endif /* !(_SPARC_TERMBITS_H) */
--- /dev/null
+#ifndef _SPARC_TERMIOS_H
+#define _SPARC_TERMIOS_H
+
+#include <asm/ioctls.h>
+#include <asm/termbits.h>
+
+#if defined(__KERNEL__) || defined(__DEFINE_BSD_TERMIOS)
+struct sgttyb {
+ char sg_ispeed;
+ char sg_ospeed;
+ char sg_erase;
+ char sg_kill;
+ short sg_flags;
+};
+
+struct tchars {
+ char t_intrc;
+ char t_quitc;
+ char t_startc;
+ char t_stopc;
+ char t_eofc;
+ char t_brkc;
+};
+
+struct ltchars {
+ char t_suspc;
+ char t_dsuspc;
+ char t_rprntc;
+ char t_flushc;
+ char t_werasc;
+ char t_lnextc;
+};
+#endif /* __KERNEL__ */
+
+struct winsize {
+ unsigned short ws_row;
+ unsigned short ws_col;
+ unsigned short ws_xpixel;
+ unsigned short ws_ypixel;
+};
+
+#ifdef __KERNEL__
+#include <linux/module.h>
+
+/*
+ * c_cc characters in the termio structure. Oh, how I love being
+ * backwardly compatible. Notice that character 4 and 5 are
+ * interpreted differently depending on whether ICANON is set in
+ * c_lflag. If it's set, they are used as _VEOF and _VEOL, otherwise
+ * as _VMIN and V_TIME. This is for compatibility with OSF/1 (which
+ * is compatible with sysV)...
+ */
+#define _VMIN 4
+#define _VTIME 5
+
+/* intr=^C quit=^\ erase=del kill=^U
+ eof=^D eol=\0 eol2=\0 sxtc=\0
+ start=^Q stop=^S susp=^Z dsusp=^Y
+ reprint=^R discard=^U werase=^W lnext=^V
+ vmin=\1 vtime=\0
+*/
+#define INIT_C_CC "\003\034\177\025\004\000\000\000\021\023\032\031\022\025\027\026\001"
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+#define user_termio_to_kernel_termios(termios, termio) \
+({ \
+ unsigned short tmp; \
+ int err; \
+ err = get_user(tmp, &(termio)->c_iflag); \
+ (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \
+ err |= get_user(tmp, &(termio)->c_oflag); \
+ (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \
+ err |= get_user(tmp, &(termio)->c_cflag); \
+ (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \
+ err |= get_user(tmp, &(termio)->c_lflag); \
+ (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \
+ err |= copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+ err; \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ *
+ * Note the "fun" _VMIN overloading.
+ */
+#define kernel_termios_to_user_termio(termio, termios) \
+({ \
+ int err; \
+ err = put_user((termios)->c_iflag, &(termio)->c_iflag); \
+ err |= put_user((termios)->c_oflag, &(termio)->c_oflag); \
+ err |= put_user((termios)->c_cflag, &(termio)->c_cflag); \
+ err |= put_user((termios)->c_lflag, &(termio)->c_lflag); \
+ err |= put_user((termios)->c_line, &(termio)->c_line); \
+ err |= copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+ if (!((termios)->c_lflag & ICANON)) { \
+ err |= put_user((termios)->c_cc[VMIN], &(termio)->c_cc[_VMIN]); \
+ err |= put_user((termios)->c_cc[VTIME], &(termio)->c_cc[_VTIME]); \
+ } \
+ err; \
+})
+
+#define user_termios_to_kernel_termios(k, u) \
+({ \
+ int err; \
+ err = get_user((k)->c_iflag, &(u)->c_iflag); \
+ err |= get_user((k)->c_oflag, &(u)->c_oflag); \
+ err |= get_user((k)->c_cflag, &(u)->c_cflag); \
+ err |= get_user((k)->c_lflag, &(u)->c_lflag); \
+ err |= get_user((k)->c_line, &(u)->c_line); \
+ err |= copy_from_user((k)->c_cc, (u)->c_cc, NCCS); \
+ if ((k)->c_lflag & ICANON) { \
+ err |= get_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
+ err |= get_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
+ } else { \
+ err |= get_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \
+ err |= get_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
+ } \
+ err |= get_user((k)->c_ispeed, &(u)->c_ispeed); \
+ err |= get_user((k)->c_ospeed, &(u)->c_ospeed); \
+ err; \
+})
+
+#define kernel_termios_to_user_termios(u, k) \
+({ \
+ int err; \
+ err = put_user((k)->c_iflag, &(u)->c_iflag); \
+ err |= put_user((k)->c_oflag, &(u)->c_oflag); \
+ err |= put_user((k)->c_cflag, &(u)->c_cflag); \
+ err |= put_user((k)->c_lflag, &(u)->c_lflag); \
+ err |= put_user((k)->c_line, &(u)->c_line); \
+ err |= copy_to_user((u)->c_cc, (k)->c_cc, NCCS); \
+ if (!((k)->c_lflag & ICANON)) { \
+ err |= put_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \
+ err |= put_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
+ } else { \
+ err |= put_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
+ err |= put_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
+ } \
+ err |= put_user((k)->c_ispeed, &(u)->c_ispeed); \
+ err |= put_user((k)->c_ospeed, &(u)->c_ospeed); \
+ err; \
+})
+
+#define user_termios_to_kernel_termios_1(k, u) \
+({ \
+ int err; \
+ err = get_user((k)->c_iflag, &(u)->c_iflag); \
+ err |= get_user((k)->c_oflag, &(u)->c_oflag); \
+ err |= get_user((k)->c_cflag, &(u)->c_cflag); \
+ err |= get_user((k)->c_lflag, &(u)->c_lflag); \
+ err |= get_user((k)->c_line, &(u)->c_line); \
+ err |= copy_from_user((k)->c_cc, (u)->c_cc, NCCS); \
+ if ((k)->c_lflag & ICANON) { \
+ err |= get_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
+ err |= get_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
+ } else { \
+ err |= get_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \
+ err |= get_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
+ } \
+ err; \
+})
+
+#define kernel_termios_to_user_termios_1(u, k) \
+({ \
+ int err; \
+ err = put_user((k)->c_iflag, &(u)->c_iflag); \
+ err |= put_user((k)->c_oflag, &(u)->c_oflag); \
+ err |= put_user((k)->c_cflag, &(u)->c_cflag); \
+ err |= put_user((k)->c_lflag, &(u)->c_lflag); \
+ err |= put_user((k)->c_line, &(u)->c_line); \
+ err |= copy_to_user((u)->c_cc, (k)->c_cc, NCCS); \
+ if (!((k)->c_lflag & ICANON)) { \
+ err |= put_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \
+ err |= put_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
+ } else { \
+ err |= put_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
+ err |= put_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
+ } \
+ err; \
+})
+
+#endif /* __KERNEL__ */
+
+#endif /* _SPARC_TERMIOS_H */
--- /dev/null
+#ifndef ___ASM_SPARC_THREAD_INFO_H
+#define ___ASM_SPARC_THREAD_INFO_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/thread_info_64.h>
+#else
+#include <asm/thread_info_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * thread_info.h: sparc low-level thread information
+ * adapted from the ppc version by Pete Zaitcev, which was
+ * adapted from the i386 version by Paul Mackerras
+ *
+ * Copyright (C) 2002 David Howells (dhowells@redhat.com)
+ * Copyright (c) 2002 Pete Zaitcev (zaitcev@yahoo.com)
+ * - Incorporating suggestions made by Linus Torvalds and Dave Miller
+ */
+
+#ifndef _ASM_THREAD_INFO_H
+#define _ASM_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+#include <asm/btfixup.h>
+#include <asm/ptrace.h>
+#include <asm/page.h>
+
+/*
+ * Low level task data.
+ *
+ * If you change this, change the TI_* offsets below to match.
+ */
+#define NSWINS 8
+struct thread_info {
+ unsigned long uwinmask;
+ struct task_struct *task; /* main task structure */
+ struct exec_domain *exec_domain; /* execution domain */
+ unsigned long flags; /* low level flags */
+ int cpu; /* cpu we're on */
+ int preempt_count; /* 0 => preemptable,
+ <0 => BUG */
+ int softirq_count;
+ int hardirq_count;
+
+ /* Context switch saved kernel state. */
+ unsigned long ksp; /* ... ksp __attribute__ ((aligned (8))); */
+ unsigned long kpc;
+ unsigned long kpsr;
+ unsigned long kwim;
+
+ /* A place to store user windows and stack pointers
+ * when the stack needs inspection.
+ */
+ struct reg_window reg_window[NSWINS]; /* align for ldd! */
+ unsigned long rwbuf_stkptrs[NSWINS];
+ unsigned long w_saved;
+
+ struct restart_block restart_block;
+};
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ *
+ * preempt_count needs to be 1 initially, until the scheduler is functional.
+ */
+#define INIT_THREAD_INFO(tsk) \
+{ \
+ .uwinmask = 0, \
+ .task = &tsk, \
+ .exec_domain = &default_exec_domain, \
+ .flags = 0, \
+ .cpu = 0, \
+ .preempt_count = 1, \
+ .restart_block = { \
+ .fn = do_no_restart_syscall, \
+ }, \
+}
+
+#define init_thread_info (init_thread_union.thread_info)
+#define init_stack (init_thread_union.stack)
+
+/* how to get the thread information struct from C */
+register struct thread_info *current_thread_info_reg asm("g6");
+#define current_thread_info() (current_thread_info_reg)
+
+/*
+ * thread information allocation
+ */
+#if PAGE_SHIFT == 13
+#define THREAD_INFO_ORDER 0
+#else /* PAGE_SHIFT */
+#define THREAD_INFO_ORDER 1
+#endif
+
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+
+BTFIXUPDEF_CALL(struct thread_info *, alloc_thread_info, void)
+#define alloc_thread_info(tsk) BTFIXUP_CALL(alloc_thread_info)()
+
+BTFIXUPDEF_CALL(void, free_thread_info, struct thread_info *)
+#define free_thread_info(ti) BTFIXUP_CALL(free_thread_info)(ti)
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Size of kernel stack for each process.
+ * Observe the order of get_free_pages() in alloc_thread_info().
+ * The sun4 has 8K stack too, because it's short on memory, and 16K is a waste.
+ */
+#define THREAD_SIZE 8192
+
+/*
+ * Offsets in thread_info structure, used in assembly code
+ * The "#define REGWIN_SZ 0x40" was abolished, so no multiplications.
+ */
+#define TI_UWINMASK 0x00 /* uwinmask */
+#define TI_TASK 0x04
+#define TI_EXECDOMAIN 0x08 /* exec_domain */
+#define TI_FLAGS 0x0c
+#define TI_CPU 0x10
+#define TI_PREEMPT 0x14 /* preempt_count */
+#define TI_SOFTIRQ 0x18 /* softirq_count */
+#define TI_HARDIRQ 0x1c /* hardirq_count */
+#define TI_KSP 0x20 /* ksp */
+#define TI_KPC 0x24 /* kpc (ldd'ed with kpc) */
+#define TI_KPSR 0x28 /* kpsr */
+#define TI_KWIM 0x2c /* kwim (ldd'ed with kpsr) */
+#define TI_REG_WINDOW 0x30
+#define TI_RWIN_SPTRS 0x230
+#define TI_W_SAVED 0x250
+/* #define TI_RESTART_BLOCK 0x25n */ /* Nobody cares */
+
+#define PREEMPT_ACTIVE 0x4000000
+
+/*
+ * thread information flag bit numbers
+ */
+#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
+#define TIF_NOTIFY_RESUME 1 /* callback before returning to user */
+#define TIF_SIGPENDING 2 /* signal pending */
+#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
+#define TIF_RESTORE_SIGMASK 4 /* restore signal mask in do_signal() */
+#define TIF_USEDFPU 8 /* FPU was used by this task
+ * this quantum (SMP) */
+#define TIF_POLLING_NRFLAG 9 /* true if poll_idle() is polling
+ * TIF_NEED_RESCHED */
+#define TIF_MEMDIE 10
+
+/* as above, but as bit values */
+#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
+#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
+#define _TIF_USEDFPU (1<<TIF_USEDFPU)
+#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
+
+#define _TIF_DO_NOTIFY_RESUME_MASK (_TIF_NOTIFY_RESUME | \
+ _TIF_SIGPENDING | \
+ _TIF_RESTORE_SIGMASK)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_THREAD_INFO_H */
--- /dev/null
+/* thread_info.h: sparc64 low-level thread information
+ *
+ * Copyright (C) 2002 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef _ASM_THREAD_INFO_H
+#define _ASM_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#define NSWINS 7
+
+#define TI_FLAG_BYTE_FAULT_CODE 0
+#define TI_FLAG_FAULT_CODE_SHIFT 56
+#define TI_FLAG_BYTE_WSTATE 1
+#define TI_FLAG_WSTATE_SHIFT 48
+#define TI_FLAG_BYTE_CWP 2
+#define TI_FLAG_CWP_SHIFT 40
+#define TI_FLAG_BYTE_CURRENT_DS 3
+#define TI_FLAG_CURRENT_DS_SHIFT 32
+#define TI_FLAG_BYTE_FPDEPTH 4
+#define TI_FLAG_FPDEPTH_SHIFT 24
+#define TI_FLAG_BYTE_WSAVED 5
+#define TI_FLAG_WSAVED_SHIFT 16
+
+#include <asm/page.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm/ptrace.h>
+#include <asm/types.h>
+
+struct task_struct;
+struct exec_domain;
+
+struct thread_info {
+ /* D$ line 1 */
+ struct task_struct *task;
+ unsigned long flags;
+ __u8 fpsaved[7];
+ __u8 status;
+ unsigned long ksp;
+
+ /* D$ line 2 */
+ unsigned long fault_address;
+ struct pt_regs *kregs;
+ struct exec_domain *exec_domain;
+ int preempt_count; /* 0 => preemptable, <0 => BUG */
+ __u8 new_child;
+ __u8 syscall_noerror;
+ __u16 cpu;
+
+ unsigned long *utraps;
+
+ struct reg_window reg_window[NSWINS];
+ unsigned long rwbuf_stkptrs[NSWINS];
+
+ unsigned long gsr[7];
+ unsigned long xfsr[7];
+
+ __u64 __user *user_cntd0;
+ __u64 __user *user_cntd1;
+ __u64 kernel_cntd0, kernel_cntd1;
+ __u64 pcr_reg;
+
+ struct restart_block restart_block;
+
+ struct pt_regs *kern_una_regs;
+ unsigned int kern_una_insn;
+
+ unsigned long fpregs[0] __attribute__ ((aligned(64)));
+};
+
+#endif /* !(__ASSEMBLY__) */
+
+/* offsets into the thread_info struct for assembly code access */
+#define TI_TASK 0x00000000
+#define TI_FLAGS 0x00000008
+#define TI_FAULT_CODE (TI_FLAGS + TI_FLAG_BYTE_FAULT_CODE)
+#define TI_WSTATE (TI_FLAGS + TI_FLAG_BYTE_WSTATE)
+#define TI_CWP (TI_FLAGS + TI_FLAG_BYTE_CWP)
+#define TI_CURRENT_DS (TI_FLAGS + TI_FLAG_BYTE_CURRENT_DS)
+#define TI_FPDEPTH (TI_FLAGS + TI_FLAG_BYTE_FPDEPTH)
+#define TI_WSAVED (TI_FLAGS + TI_FLAG_BYTE_WSAVED)
+#define TI_FPSAVED 0x00000010
+#define TI_KSP 0x00000018
+#define TI_FAULT_ADDR 0x00000020
+#define TI_KREGS 0x00000028
+#define TI_EXEC_DOMAIN 0x00000030
+#define TI_PRE_COUNT 0x00000038
+#define TI_NEW_CHILD 0x0000003c
+#define TI_SYS_NOERROR 0x0000003d
+#define TI_CPU 0x0000003e
+#define TI_UTRAPS 0x00000040
+#define TI_REG_WINDOW 0x00000048
+#define TI_RWIN_SPTRS 0x000003c8
+#define TI_GSR 0x00000400
+#define TI_XFSR 0x00000438
+#define TI_USER_CNTD0 0x00000470
+#define TI_USER_CNTD1 0x00000478
+#define TI_KERN_CNTD0 0x00000480
+#define TI_KERN_CNTD1 0x00000488
+#define TI_PCR 0x00000490
+#define TI_RESTART_BLOCK 0x00000498
+#define TI_KUNA_REGS 0x000004c0
+#define TI_KUNA_INSN 0x000004c8
+#define TI_FPREGS 0x00000500
+
+/* We embed this in the uppermost byte of thread_info->flags */
+#define FAULT_CODE_WRITE 0x01 /* Write access, implies D-TLB */
+#define FAULT_CODE_DTLB 0x02 /* Miss happened in D-TLB */
+#define FAULT_CODE_ITLB 0x04 /* Miss happened in I-TLB */
+#define FAULT_CODE_WINFIXUP 0x08 /* Miss happened during spill/fill */
+#define FAULT_CODE_BLKCOMMIT 0x10 /* Use blk-commit ASI in copy_page */
+
+#if PAGE_SHIFT == 13
+#define THREAD_SIZE (2*PAGE_SIZE)
+#define THREAD_SHIFT (PAGE_SHIFT + 1)
+#else /* PAGE_SHIFT == 13 */
+#define THREAD_SIZE PAGE_SIZE
+#define THREAD_SHIFT PAGE_SHIFT
+#endif /* PAGE_SHIFT == 13 */
+
+#define PREEMPT_ACTIVE 0x4000000
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ *
+ * preempt_count needs to be 1 initially, until the scheduler is functional.
+ */
+#ifndef __ASSEMBLY__
+
+#define INIT_THREAD_INFO(tsk) \
+{ \
+ .task = &tsk, \
+ .flags = ((unsigned long)ASI_P) << TI_FLAG_CURRENT_DS_SHIFT, \
+ .exec_domain = &default_exec_domain, \
+ .preempt_count = 1, \
+ .restart_block = { \
+ .fn = do_no_restart_syscall, \
+ }, \
+}
+
+#define init_thread_info (init_thread_union.thread_info)
+#define init_stack (init_thread_union.stack)
+
+/* how to get the thread information struct from C */
+register struct thread_info *current_thread_info_reg asm("g6");
+#define current_thread_info() (current_thread_info_reg)
+
+/* thread information allocation */
+#if PAGE_SHIFT == 13
+#define __THREAD_INFO_ORDER 1
+#else /* PAGE_SHIFT == 13 */
+#define __THREAD_INFO_ORDER 0
+#endif /* PAGE_SHIFT == 13 */
+
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+
+#ifdef CONFIG_DEBUG_STACK_USAGE
+#define alloc_thread_info(tsk) \
+({ \
+ struct thread_info *ret; \
+ \
+ ret = (struct thread_info *) \
+ __get_free_pages(GFP_KERNEL, __THREAD_INFO_ORDER); \
+ if (ret) \
+ memset(ret, 0, PAGE_SIZE<<__THREAD_INFO_ORDER); \
+ ret; \
+})
+#else
+#define alloc_thread_info(tsk) \
+ ((struct thread_info *)__get_free_pages(GFP_KERNEL, __THREAD_INFO_ORDER))
+#endif
+
+#define free_thread_info(ti) \
+ free_pages((unsigned long)(ti),__THREAD_INFO_ORDER)
+
+#define __thread_flag_byte_ptr(ti) \
+ ((unsigned char *)(&((ti)->flags)))
+#define __cur_thread_flag_byte_ptr __thread_flag_byte_ptr(current_thread_info())
+
+#define get_thread_fault_code() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FAULT_CODE])
+#define set_thread_fault_code(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FAULT_CODE] = (val))
+#define get_thread_wstate() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSTATE])
+#define set_thread_wstate(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSTATE] = (val))
+#define get_thread_cwp() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CWP])
+#define set_thread_cwp(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CWP] = (val))
+#define get_thread_current_ds() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CURRENT_DS])
+#define set_thread_current_ds(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CURRENT_DS] = (val))
+#define get_thread_fpdepth() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FPDEPTH])
+#define set_thread_fpdepth(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FPDEPTH] = (val))
+#define get_thread_wsaved() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSAVED])
+#define set_thread_wsaved(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSAVED] = (val))
+
+#endif /* !(__ASSEMBLY__) */
+
+/*
+ * Thread information flags, only 16 bits are available as we encode
+ * other values into the upper 6 bytes.
+ *
+ * On trap return we need to test several values:
+ *
+ * user: need_resched, notify_resume, sigpending, wsaved, perfctr
+ * kernel: fpdepth
+ *
+ * So to check for work in the kernel case we simply load the fpdepth
+ * byte out of the flags and test it. For the user case we encode the
+ * lower 3 bytes of flags as follows:
+ * ----------------------------------------
+ * | wsaved | flags byte 1 | flags byte 2 |
+ * ----------------------------------------
+ * This optimizes the user test into:
+ * ldx [%g6 + TI_FLAGS], REG1
+ * sethi %hi(_TIF_USER_WORK_MASK), REG2
+ * or REG2, %lo(_TIF_USER_WORK_MASK), REG2
+ * andcc REG1, REG2, %g0
+ * be,pt no_work_to_do
+ * nop
+ */
+#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
+#define TIF_NOTIFY_RESUME 1 /* callback before returning to user */
+#define TIF_SIGPENDING 2 /* signal pending */
+#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
+#define TIF_PERFCTR 4 /* performance counters active */
+#define TIF_UNALIGNED 5 /* allowed to do unaligned accesses */
+/* flag bit 6 is available */
+#define TIF_32BIT 7 /* 32-bit binary */
+/* flag bit 8 is available */
+#define TIF_SECCOMP 9 /* secure computing */
+#define TIF_SYSCALL_AUDIT 10 /* syscall auditing active */
+/* flag bit 11 is available */
+/* NOTE: Thread flags >= 12 should be ones we have no interest
+ * in using in assembly, else we can't use the mask as
+ * an immediate value in instructions such as andcc.
+ */
+#define TIF_ABI_PENDING 12
+#define TIF_MEMDIE 13
+#define TIF_POLLING_NRFLAG 14
+
+#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
+#define _TIF_PERFCTR (1<<TIF_PERFCTR)
+#define _TIF_UNALIGNED (1<<TIF_UNALIGNED)
+#define _TIF_32BIT (1<<TIF_32BIT)
+#define _TIF_SECCOMP (1<<TIF_SECCOMP)
+#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
+#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
+#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
+
+#define _TIF_USER_WORK_MASK ((0xff << TI_FLAG_WSAVED_SHIFT) | \
+ _TIF_DO_NOTIFY_RESUME_MASK | \
+ _TIF_NEED_RESCHED | _TIF_PERFCTR)
+#define _TIF_DO_NOTIFY_RESUME_MASK (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING)
+
+/*
+ * Thread-synchronous status.
+ *
+ * This is different from the flags in that nobody else
+ * ever touches our thread-synchronous status, so we don't
+ * have to worry about atomic accesses.
+ *
+ * Note that there are only 8 bits available.
+ */
+#define TS_RESTORE_SIGMASK 0x0001 /* restore signal mask in do_signal() */
+
+#ifndef __ASSEMBLY__
+#define HAVE_SET_RESTORE_SIGMASK 1
+static inline void set_restore_sigmask(void)
+{
+ struct thread_info *ti = current_thread_info();
+ ti->status |= TS_RESTORE_SIGMASK;
+ set_bit(TIF_SIGPENDING, &ti->flags);
+}
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_THREAD_INFO_H */
--- /dev/null
+#ifndef ___ASM_SPARC_TIMER_H
+#define ___ASM_SPARC_TIMER_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/timer_64.h>
+#else
+#include <asm/timer_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * timer.h: Definitions for the timer chips on the Sparc.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+
+#ifndef _SPARC_TIMER_H
+#define _SPARC_TIMER_H
+
+#include <asm/system.h> /* For SUN4M_NCPUS */
+#include <asm/sun4paddr.h>
+#include <asm/btfixup.h>
+
+/* Timer structures. The interrupt timer has two properties which
+ * are the counter (which is handled in do_timer in sched.c) and the limit.
+ * This limit is where the timer's counter 'wraps' around. Oddly enough,
+ * the sun4c timer when it hits the limit wraps back to 1 and not zero
+ * thus when calculating the value at which it will fire a microsecond you
+ * must adjust by one. Thanks SUN for designing such great hardware ;(
+ */
+
+/* Note that I am only going to use the timer that interrupts at
+ * Sparc IRQ 10. There is another one available that can fire at
+ * IRQ 14. Currently it is left untouched, we keep the PROM's limit
+ * register value and let the prom take these interrupts. This allows
+ * L1-A to work.
+ */
+
+struct sun4c_timer_info {
+ __volatile__ unsigned int cur_count10;
+ __volatile__ unsigned int timer_limit10;
+ __volatile__ unsigned int cur_count14;
+ __volatile__ unsigned int timer_limit14;
+};
+
+#define SUN4C_TIMER_PHYSADDR 0xf3000000
+#ifdef CONFIG_SUN4
+#define SUN_TIMER_PHYSADDR SUN4_300_TIMER_PHYSADDR
+#else
+#define SUN_TIMER_PHYSADDR SUN4C_TIMER_PHYSADDR
+#endif
+
+/* A sun4m has two blocks of registers which are probably of the same
+ * structure. LSI Logic's L64851 is told to _decrement_ from the limit
+ * value. Aurora behaves similarly but its limit value is compacted in
+ * other fashion (it's wider). Documented fields are defined here.
+ */
+
+/* As with the interrupt register, we have two classes of timer registers
+ * which are per-cpu and master. Per-cpu timers only hit that cpu and are
+ * only level 14 ticks, master timer hits all cpus and is level 10.
+ */
+
+#define SUN4M_PRM_CNT_L 0x80000000
+#define SUN4M_PRM_CNT_LVALUE 0x7FFFFC00
+
+struct sun4m_timer_percpu_info {
+ __volatile__ unsigned int l14_timer_limit; /* Initial value is 0x009c4000 */
+ __volatile__ unsigned int l14_cur_count;
+
+ /* This register appears to be write only and/or inaccessible
+ * on Uni-Processor sun4m machines.
+ */
+ __volatile__ unsigned int l14_limit_noclear; /* Data access error is here */
+
+ __volatile__ unsigned int cntrl; /* =1 after POST on Aurora */
+ __volatile__ unsigned char space[PAGE_SIZE - 16];
+};
+
+struct sun4m_timer_regs {
+ struct sun4m_timer_percpu_info cpu_timers[SUN4M_NCPUS];
+ volatile unsigned int l10_timer_limit;
+ volatile unsigned int l10_cur_count;
+
+ /* Again, this appears to be write only and/or inaccessible
+ * on uni-processor sun4m machines.
+ */
+ volatile unsigned int l10_limit_noclear;
+
+ /* This register too, it must be magic. */
+ volatile unsigned int foobar;
+
+ volatile unsigned int cfg; /* equals zero at boot time... */
+};
+
+#define SUN4D_PRM_CNT_L 0x80000000
+#define SUN4D_PRM_CNT_LVALUE 0x7FFFFC00
+
+struct sun4d_timer_regs {
+ volatile unsigned int l10_timer_limit;
+ volatile unsigned int l10_cur_countx;
+ volatile unsigned int l10_limit_noclear;
+ volatile unsigned int ctrl;
+ volatile unsigned int l10_cur_count;
+};
+
+extern struct sun4d_timer_regs *sun4d_timers;
+
+extern __volatile__ unsigned int *master_l10_counter;
+extern __volatile__ unsigned int *master_l10_limit;
+
+/* FIXME: Make do_[gs]ettimeofday btfixup calls */
+BTFIXUPDEF_CALL(int, bus_do_settimeofday, struct timespec *tv)
+#define bus_do_settimeofday(tv) BTFIXUP_CALL(bus_do_settimeofday)(tv)
+
+#endif /* !(_SPARC_TIMER_H) */
--- /dev/null
+/* timer.h: System timer definitions for sun5.
+ *
+ * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC64_TIMER_H
+#define _SPARC64_TIMER_H
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+struct sparc64_tick_ops {
+ unsigned long (*get_tick)(void);
+ int (*add_compare)(unsigned long);
+ unsigned long softint_mask;
+ void (*disable_irq)(void);
+
+ void (*init_tick)(void);
+ unsigned long (*add_tick)(unsigned long);
+
+ char *name;
+};
+
+extern struct sparc64_tick_ops *tick_ops;
+
+extern unsigned long sparc64_get_clock_tick(unsigned int cpu);
+extern void __devinit setup_sparc64_timer(void);
+extern void __init time_init(void);
+
+#endif /* _SPARC64_TIMER_H */
--- /dev/null
+#ifndef ___ASM_SPARC_TIMEX_H
+#define ___ASM_SPARC_TIMEX_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/timex_64.h>
+#else
+#include <asm/timex_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * linux/include/asm/timex.h
+ *
+ * sparc architecture timex specifications
+ */
+#ifndef _ASMsparc_TIMEX_H
+#define _ASMsparc_TIMEX_H
+
+#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
+
+/* XXX Maybe do something better at some point... -DaveM */
+typedef unsigned long cycles_t;
+#define get_cycles() (0)
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm/timex.h
+ *
+ * sparc64 architecture timex specifications
+ */
+#ifndef _ASMsparc64_TIMEX_H
+#define _ASMsparc64_TIMEX_H
+
+#include <asm/timer.h>
+
+#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
+
+/* Getting on the cycle counter on sparc64. */
+typedef unsigned long cycles_t;
+#define get_cycles() tick_ops->get_tick()
+
+#define ARCH_HAS_READ_CURRENT_TIMER
+
+#endif
--- /dev/null
+#ifndef ___ASM_SPARC_TLB_H
+#define ___ASM_SPARC_TLB_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/tlb_64.h>
+#else
+#include <asm/tlb_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _SPARC_TLB_H
+#define _SPARC_TLB_H
+
+#define tlb_start_vma(tlb, vma) \
+do { \
+ flush_cache_range(vma, vma->vm_start, vma->vm_end); \
+} while (0)
+
+#define tlb_end_vma(tlb, vma) \
+do { \
+ flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
+} while (0)
+
+#define __tlb_remove_tlb_entry(tlb, pte, address) \
+ do { } while (0)
+
+#define tlb_flush(tlb) \
+do { \
+ flush_tlb_mm((tlb)->mm); \
+} while (0)
+
+#include <asm-generic/tlb.h>
+
+#endif /* _SPARC_TLB_H */
--- /dev/null
+#ifndef _SPARC64_TLB_H
+#define _SPARC64_TLB_H
+
+#include <linux/swap.h>
+#include <linux/pagemap.h>
+#include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
+#include <asm/mmu_context.h>
+
+#define TLB_BATCH_NR 192
+
+/*
+ * For UP we don't need to worry about TLB flush
+ * and page free order so much..
+ */
+#ifdef CONFIG_SMP
+ #define FREE_PTE_NR 506
+ #define tlb_fast_mode(bp) ((bp)->pages_nr == ~0U)
+#else
+ #define FREE_PTE_NR 1
+ #define tlb_fast_mode(bp) 1
+#endif
+
+struct mmu_gather {
+ struct mm_struct *mm;
+ unsigned int pages_nr;
+ unsigned int need_flush;
+ unsigned int fullmm;
+ unsigned int tlb_nr;
+ unsigned long vaddrs[TLB_BATCH_NR];
+ struct page *pages[FREE_PTE_NR];
+};
+
+DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
+
+#ifdef CONFIG_SMP
+extern void smp_flush_tlb_pending(struct mm_struct *,
+ unsigned long, unsigned long *);
+#endif
+
+extern void __flush_tlb_pending(unsigned long, unsigned long, unsigned long *);
+extern void flush_tlb_pending(void);
+
+static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
+{
+ struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
+
+ BUG_ON(mp->tlb_nr);
+
+ mp->mm = mm;
+ mp->pages_nr = num_online_cpus() > 1 ? 0U : ~0U;
+ mp->fullmm = full_mm_flush;
+
+ return mp;
+}
+
+
+static inline void tlb_flush_mmu(struct mmu_gather *mp)
+{
+ if (mp->need_flush) {
+ free_pages_and_swap_cache(mp->pages, mp->pages_nr);
+ mp->pages_nr = 0;
+ mp->need_flush = 0;
+ }
+
+}
+
+#ifdef CONFIG_SMP
+extern void smp_flush_tlb_mm(struct mm_struct *mm);
+#define do_flush_tlb_mm(mm) smp_flush_tlb_mm(mm)
+#else
+#define do_flush_tlb_mm(mm) __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT)
+#endif
+
+static inline void tlb_finish_mmu(struct mmu_gather *mp, unsigned long start, unsigned long end)
+{
+ tlb_flush_mmu(mp);
+
+ if (mp->fullmm)
+ mp->fullmm = 0;
+ else
+ flush_tlb_pending();
+
+ /* keep the page table cache within bounds */
+ check_pgt_cache();
+
+ put_cpu_var(mmu_gathers);
+}
+
+static inline void tlb_remove_page(struct mmu_gather *mp, struct page *page)
+{
+ if (tlb_fast_mode(mp)) {
+ free_page_and_swap_cache(page);
+ return;
+ }
+ mp->need_flush = 1;
+ mp->pages[mp->pages_nr++] = page;
+ if (mp->pages_nr >= FREE_PTE_NR)
+ tlb_flush_mmu(mp);
+}
+
+#define tlb_remove_tlb_entry(mp,ptep,addr) do { } while (0)
+#define pte_free_tlb(mp, ptepage) pte_free((mp)->mm, ptepage)
+#define pmd_free_tlb(mp, pmdp) pmd_free((mp)->mm, pmdp)
+#define pud_free_tlb(tlb,pudp) __pud_free_tlb(tlb,pudp)
+
+#define tlb_migrate_finish(mm) do { } while (0)
+#define tlb_start_vma(tlb, vma) do { } while (0)
+#define tlb_end_vma(tlb, vma) do { } while (0)
+
+#endif /* _SPARC64_TLB_H */
--- /dev/null
+#ifndef ___ASM_SPARC_TLBFLUSH_H
+#define ___ASM_SPARC_TLBFLUSH_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/tlbflush_64.h>
+#else
+#include <asm/tlbflush_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _SPARC_TLBFLUSH_H
+#define _SPARC_TLBFLUSH_H
+
+#include <linux/mm.h>
+// #include <asm/processor.h>
+
+/*
+ * TLB flushing:
+ *
+ * - flush_tlb() flushes the current mm struct TLBs XXX Exists?
+ * - flush_tlb_all() flushes all processes TLBs
+ * - flush_tlb_mm(mm) flushes the specified mm context TLB's
+ * - flush_tlb_page(vma, vmaddr) flushes one page
+ * - flush_tlb_range(vma, start, end) flushes a range of pages
+ * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
+ */
+
+#ifdef CONFIG_SMP
+
+BTFIXUPDEF_CALL(void, local_flush_tlb_all, void)
+BTFIXUPDEF_CALL(void, local_flush_tlb_mm, struct mm_struct *)
+BTFIXUPDEF_CALL(void, local_flush_tlb_range, struct vm_area_struct *, unsigned long, unsigned long)
+BTFIXUPDEF_CALL(void, local_flush_tlb_page, struct vm_area_struct *, unsigned long)
+
+#define local_flush_tlb_all() BTFIXUP_CALL(local_flush_tlb_all)()
+#define local_flush_tlb_mm(mm) BTFIXUP_CALL(local_flush_tlb_mm)(mm)
+#define local_flush_tlb_range(vma,start,end) BTFIXUP_CALL(local_flush_tlb_range)(vma,start,end)
+#define local_flush_tlb_page(vma,addr) BTFIXUP_CALL(local_flush_tlb_page)(vma,addr)
+
+extern void smp_flush_tlb_all(void);
+extern void smp_flush_tlb_mm(struct mm_struct *mm);
+extern void smp_flush_tlb_range(struct vm_area_struct *vma,
+ unsigned long start,
+ unsigned long end);
+extern void smp_flush_tlb_page(struct vm_area_struct *mm, unsigned long page);
+
+#endif /* CONFIG_SMP */
+
+BTFIXUPDEF_CALL(void, flush_tlb_all, void)
+BTFIXUPDEF_CALL(void, flush_tlb_mm, struct mm_struct *)
+BTFIXUPDEF_CALL(void, flush_tlb_range, struct vm_area_struct *, unsigned long, unsigned long)
+BTFIXUPDEF_CALL(void, flush_tlb_page, struct vm_area_struct *, unsigned long)
+
+#define flush_tlb_all() BTFIXUP_CALL(flush_tlb_all)()
+#define flush_tlb_mm(mm) BTFIXUP_CALL(flush_tlb_mm)(mm)
+#define flush_tlb_range(vma,start,end) BTFIXUP_CALL(flush_tlb_range)(vma,start,end)
+#define flush_tlb_page(vma,addr) BTFIXUP_CALL(flush_tlb_page)(vma,addr)
+
+// #define flush_tlb() flush_tlb_mm(current->active_mm) /* XXX Sure? */
+
+/*
+ * This is a kludge, until I know better. --zaitcev XXX
+ */
+static inline void flush_tlb_kernel_range(unsigned long start,
+ unsigned long end)
+{
+ flush_tlb_all();
+}
+
+#endif /* _SPARC_TLBFLUSH_H */
--- /dev/null
+#ifndef _SPARC64_TLBFLUSH_H
+#define _SPARC64_TLBFLUSH_H
+
+#include <linux/mm.h>
+#include <asm/mmu_context.h>
+
+/* TSB flush operations. */
+struct mmu_gather;
+extern void flush_tsb_kernel_range(unsigned long start, unsigned long end);
+extern void flush_tsb_user(struct mmu_gather *mp);
+
+/* TLB flush operations. */
+
+extern void flush_tlb_pending(void);
+
+#define flush_tlb_range(vma,start,end) \
+ do { (void)(start); flush_tlb_pending(); } while (0)
+#define flush_tlb_page(vma,addr) flush_tlb_pending()
+#define flush_tlb_mm(mm) flush_tlb_pending()
+
+/* Local cpu only. */
+extern void __flush_tlb_all(void);
+
+extern void __flush_tlb_kernel_range(unsigned long start, unsigned long end);
+
+#ifndef CONFIG_SMP
+
+#define flush_tlb_kernel_range(start,end) \
+do { flush_tsb_kernel_range(start,end); \
+ __flush_tlb_kernel_range(start,end); \
+} while (0)
+
+#else /* CONFIG_SMP */
+
+extern void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end);
+
+#define flush_tlb_kernel_range(start, end) \
+do { flush_tsb_kernel_range(start,end); \
+ smp_flush_tlb_kernel_range(start, end); \
+} while (0)
+
+#endif /* ! CONFIG_SMP */
+
+#endif /* _SPARC64_TLBFLUSH_H */
--- /dev/null
+#ifndef ___ASM_SPARC_TOPOLOGY_H
+#define ___ASM_SPARC_TOPOLOGY_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/topology_64.h>
+#else
+#include <asm/topology_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _ASM_SPARC_TOPOLOGY_H
+#define _ASM_SPARC_TOPOLOGY_H
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_SPARC_TOPOLOGY_H */
--- /dev/null
+#ifndef _ASM_SPARC64_TOPOLOGY_H
+#define _ASM_SPARC64_TOPOLOGY_H
+
+#ifdef CONFIG_NUMA
+
+#include <asm/mmzone.h>
+
+static inline int cpu_to_node(int cpu)
+{
+ return numa_cpu_lookup_table[cpu];
+}
+
+#define parent_node(node) (node)
+
+static inline cpumask_t node_to_cpumask(int node)
+{
+ return numa_cpumask_lookup_table[node];
+}
+
+/* Returns a pointer to the cpumask of CPUs on Node 'node'. */
+#define node_to_cpumask_ptr(v, node) \
+ cpumask_t *v = &(numa_cpumask_lookup_table[node])
+
+#define node_to_cpumask_ptr_next(v, node) \
+ v = &(numa_cpumask_lookup_table[node])
+
+static inline int node_to_first_cpu(int node)
+{
+ cpumask_t tmp;
+ tmp = node_to_cpumask(node);
+ return first_cpu(tmp);
+}
+
+struct pci_bus;
+#ifdef CONFIG_PCI
+extern int pcibus_to_node(struct pci_bus *pbus);
+#else
+static inline int pcibus_to_node(struct pci_bus *pbus)
+{
+ return -1;
+}
+#endif
+
+#define pcibus_to_cpumask(bus) \
+ (pcibus_to_node(bus) == -1 ? \
+ CPU_MASK_ALL : \
+ node_to_cpumask(pcibus_to_node(bus)))
+
+#define SD_NODE_INIT (struct sched_domain) { \
+ .min_interval = 8, \
+ .max_interval = 32, \
+ .busy_factor = 32, \
+ .imbalance_pct = 125, \
+ .cache_nice_tries = 2, \
+ .busy_idx = 3, \
+ .idle_idx = 2, \
+ .newidle_idx = 0, \
+ .wake_idx = 1, \
+ .forkexec_idx = 1, \
+ .flags = SD_LOAD_BALANCE \
+ | SD_BALANCE_FORK \
+ | SD_BALANCE_EXEC \
+ | SD_SERIALIZE \
+ | SD_WAKE_BALANCE, \
+ .last_balance = jiffies, \
+ .balance_interval = 1, \
+}
+
+#else /* CONFIG_NUMA */
+
+#include <asm-generic/topology.h>
+
+#endif /* !(CONFIG_NUMA) */
+
+#ifdef CONFIG_SMP
+#define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id)
+#define topology_core_id(cpu) (cpu_data(cpu).core_id)
+#define topology_core_siblings(cpu) (cpu_core_map[cpu])
+#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu))
+#define mc_capable() (sparc64_multi_core)
+#define smt_capable() (sparc64_multi_core)
+#endif /* CONFIG_SMP */
+
+#define cpu_coregroup_map(cpu) (cpu_core_map[cpu])
+
+#endif /* _ASM_SPARC64_TOPOLOGY_H */
--- /dev/null
+/*
+ * traps.h: Format of entries for the Sparc trap table.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_TRAPS_H
+#define _SPARC_TRAPS_H
+
+#define NUM_SPARC_TRAPS 255
+
+#ifndef __ASSEMBLY__
+
+/* This is for V8 compliant Sparc CPUS */
+struct tt_entry {
+ unsigned long inst_one;
+ unsigned long inst_two;
+ unsigned long inst_three;
+ unsigned long inst_four;
+};
+
+/* We set this to _start in system setup. */
+extern struct tt_entry *sparc_ttable;
+
+static inline unsigned long get_tbr(void)
+{
+ unsigned long tbr;
+
+ __asm__ __volatile__("rd %%tbr, %0\n\t" : "=r" (tbr));
+ return tbr;
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+/* For patching the trap table at boot time, we need to know how to
+ * form various common Sparc instructions. Thus these macros...
+ */
+
+#define SPARC_MOV_CONST_L3(const) (0xa6102000 | (const&0xfff))
+
+/* The following assumes that the branch lies before the place we
+ * are branching to. This is the case for a trap vector...
+ * You have been warned.
+ */
+#define SPARC_BRANCH(dest_addr, inst_addr) \
+ (0x10800000 | (((dest_addr-inst_addr)>>2)&0x3fffff))
+
+#define SPARC_RD_PSR_L0 (0xa1480000)
+#define SPARC_RD_WIM_L3 (0xa7500000)
+#define SPARC_NOP (0x01000000)
+
+/* Various interesting trap levels. */
+/* First, hardware traps. */
+#define SP_TRAP_TFLT 0x1 /* Text fault */
+#define SP_TRAP_II 0x2 /* Illegal Instruction */
+#define SP_TRAP_PI 0x3 /* Privileged Instruction */
+#define SP_TRAP_FPD 0x4 /* Floating Point Disabled */
+#define SP_TRAP_WOVF 0x5 /* Window Overflow */
+#define SP_TRAP_WUNF 0x6 /* Window Underflow */
+#define SP_TRAP_MNA 0x7 /* Memory Address Unaligned */
+#define SP_TRAP_FPE 0x8 /* Floating Point Exception */
+#define SP_TRAP_DFLT 0x9 /* Data Fault */
+#define SP_TRAP_TOF 0xa /* Tag Overflow */
+#define SP_TRAP_WDOG 0xb /* Watchpoint Detected */
+#define SP_TRAP_IRQ1 0x11 /* IRQ level 1 */
+#define SP_TRAP_IRQ2 0x12 /* IRQ level 2 */
+#define SP_TRAP_IRQ3 0x13 /* IRQ level 3 */
+#define SP_TRAP_IRQ4 0x14 /* IRQ level 4 */
+#define SP_TRAP_IRQ5 0x15 /* IRQ level 5 */
+#define SP_TRAP_IRQ6 0x16 /* IRQ level 6 */
+#define SP_TRAP_IRQ7 0x17 /* IRQ level 7 */
+#define SP_TRAP_IRQ8 0x18 /* IRQ level 8 */
+#define SP_TRAP_IRQ9 0x19 /* IRQ level 9 */
+#define SP_TRAP_IRQ10 0x1a /* IRQ level 10 */
+#define SP_TRAP_IRQ11 0x1b /* IRQ level 11 */
+#define SP_TRAP_IRQ12 0x1c /* IRQ level 12 */
+#define SP_TRAP_IRQ13 0x1d /* IRQ level 13 */
+#define SP_TRAP_IRQ14 0x1e /* IRQ level 14 */
+#define SP_TRAP_IRQ15 0x1f /* IRQ level 15 Non-maskable */
+#define SP_TRAP_RACC 0x20 /* Register Access Error ??? */
+#define SP_TRAP_IACC 0x21 /* Instruction Access Error */
+#define SP_TRAP_CPDIS 0x24 /* Co-Processor Disabled */
+#define SP_TRAP_BADFL 0x25 /* Unimplemented Flush Instruction */
+#define SP_TRAP_CPEXP 0x28 /* Co-Processor Exception */
+#define SP_TRAP_DACC 0x29 /* Data Access Error */
+#define SP_TRAP_DIVZ 0x2a /* Divide By Zero */
+#define SP_TRAP_DSTORE 0x2b /* Data Store Error ??? */
+#define SP_TRAP_DMM 0x2c /* Data Access MMU Miss ??? */
+#define SP_TRAP_IMM 0x3c /* Instruction Access MMU Miss ??? */
+
+/* Now the Software Traps... */
+#define SP_TRAP_SUNOS 0x80 /* SunOS System Call */
+#define SP_TRAP_SBPT 0x81 /* Software Breakpoint */
+#define SP_TRAP_SDIVZ 0x82 /* Software Divide-by-Zero trap */
+#define SP_TRAP_FWIN 0x83 /* Flush Windows */
+#define SP_TRAP_CWIN 0x84 /* Clean Windows */
+#define SP_TRAP_RCHK 0x85 /* Range Check */
+#define SP_TRAP_FUNA 0x86 /* Fix Unaligned Access */
+#define SP_TRAP_IOWFL 0x87 /* Integer Overflow */
+#define SP_TRAP_SOLARIS 0x88 /* Solaris System Call */
+#define SP_TRAP_NETBSD 0x89 /* NetBSD System Call */
+#define SP_TRAP_LINUX 0x90 /* Linux System Call */
+
+/* Names used for compatibility with SunOS */
+#define ST_SYSCALL 0x00
+#define ST_BREAKPOINT 0x01
+#define ST_DIV0 0x02
+#define ST_FLUSH_WINDOWS 0x03
+#define ST_CLEAN_WINDOWS 0x04
+#define ST_RANGE_CHECK 0x05
+#define ST_FIX_ALIGN 0x06
+#define ST_INT_OVERFLOW 0x07
+
+/* Special traps... */
+#define SP_TRAP_KBPT1 0xfe /* KADB/PROM Breakpoint one */
+#define SP_TRAP_KBPT2 0xff /* KADB/PROM Breakpoint two */
+
+/* Handy Macros */
+/* Is this a trap we never expect to get? */
+#define BAD_TRAP_P(level) \
+ ((level > SP_TRAP_WDOG && level < SP_TRAP_IRQ1) || \
+ (level > SP_TRAP_IACC && level < SP_TRAP_CPDIS) || \
+ (level > SP_TRAP_BADFL && level < SP_TRAP_CPEXP) || \
+ (level > SP_TRAP_DMM && level < SP_TRAP_IMM) || \
+ (level > SP_TRAP_IMM && level < SP_TRAP_SUNOS) || \
+ (level > SP_TRAP_LINUX && level < SP_TRAP_KBPT1))
+
+/* Is this a Hardware trap? */
+#define HW_TRAP_P(level) ((level > 0) && (level < SP_TRAP_SUNOS))
+
+/* Is this a Software trap? */
+#define SW_TRAP_P(level) ((level >= SP_TRAP_SUNOS) && (level <= SP_TRAP_KBPT2))
+
+/* Is this a system call for some OS we know about? */
+#define SCALL_TRAP_P(level) ((level == SP_TRAP_SUNOS) || \
+ (level == SP_TRAP_SOLARIS) || \
+ (level == SP_TRAP_NETBSD) || \
+ (level == SP_TRAP_LINUX))
+
+#endif /* !(_SPARC_TRAPS_H) */
--- /dev/null
+#ifndef _SPARC64_TSB_H
+#define _SPARC64_TSB_H
+
+/* The sparc64 TSB is similar to the powerpc hashtables. It's a
+ * power-of-2 sized table of TAG/PTE pairs. The cpu precomputes
+ * pointers into this table for 8K and 64K page sizes, and also a
+ * comparison TAG based upon the virtual address and context which
+ * faults.
+ *
+ * TLB miss trap handler software does the actual lookup via something
+ * of the form:
+ *
+ * ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
+ * ldxa [%g0] ASI_{D,I}MMU, %g6
+ * sllx %g6, 22, %g6
+ * srlx %g6, 22, %g6
+ * ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4
+ * cmp %g4, %g6
+ * bne,pn %xcc, tsb_miss_{d,i}tlb
+ * mov FAULT_CODE_{D,I}TLB, %g3
+ * stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN
+ * retry
+ *
+ *
+ * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
+ * PTE. The TAG is of the same layout as the TLB TAG TARGET mmu
+ * register which is:
+ *
+ * -------------------------------------------------
+ * | - | CONTEXT | - | VADDR bits 63:22 |
+ * -------------------------------------------------
+ * 63 61 60 48 47 42 41 0
+ *
+ * But actually, since we use per-mm TSB's, we zero out the CONTEXT
+ * field.
+ *
+ * Like the powerpc hashtables we need to use locking in order to
+ * synchronize while we update the entries. PTE updates need locking
+ * as well.
+ *
+ * We need to carefully choose a lock bits for the TSB entry. We
+ * choose to use bit 47 in the tag. Also, since we never map anything
+ * at page zero in context zero, we use zero as an invalid tag entry.
+ * When the lock bit is set, this forces a tag comparison failure.
+ */
+
+#define TSB_TAG_LOCK_BIT 47
+#define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32))
+
+#define TSB_TAG_INVALID_BIT 46
+#define TSB_TAG_INVALID_HIGH (1 << (TSB_TAG_INVALID_BIT - 32))
+
+#define TSB_MEMBAR membar #StoreStore
+
+/* Some cpus support physical address quad loads. We want to use
+ * those if possible so we don't need to hard-lock the TSB mapping
+ * into the TLB. We encode some instruction patching in order to
+ * support this.
+ *
+ * The kernel TSB is locked into the TLB by virtue of being in the
+ * kernel image, so we don't play these games for swapper_tsb access.
+ */
+#ifndef __ASSEMBLY__
+struct tsb_ldquad_phys_patch_entry {
+ unsigned int addr;
+ unsigned int sun4u_insn;
+ unsigned int sun4v_insn;
+};
+extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
+ __tsb_ldquad_phys_patch_end;
+
+struct tsb_phys_patch_entry {
+ unsigned int addr;
+ unsigned int insn;
+};
+extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
+#endif
+#define TSB_LOAD_QUAD(TSB, REG) \
+661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
+ .section .tsb_ldquad_phys_patch, "ax"; \
+ .word 661b; \
+ ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
+ ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
+ .previous
+
+#define TSB_LOAD_TAG_HIGH(TSB, REG) \
+661: lduwa [TSB] ASI_N, REG; \
+ .section .tsb_phys_patch, "ax"; \
+ .word 661b; \
+ lduwa [TSB] ASI_PHYS_USE_EC, REG; \
+ .previous
+
+#define TSB_LOAD_TAG(TSB, REG) \
+661: ldxa [TSB] ASI_N, REG; \
+ .section .tsb_phys_patch, "ax"; \
+ .word 661b; \
+ ldxa [TSB] ASI_PHYS_USE_EC, REG; \
+ .previous
+
+#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
+661: casa [TSB] ASI_N, REG1, REG2; \
+ .section .tsb_phys_patch, "ax"; \
+ .word 661b; \
+ casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
+ .previous
+
+#define TSB_CAS_TAG(TSB, REG1, REG2) \
+661: casxa [TSB] ASI_N, REG1, REG2; \
+ .section .tsb_phys_patch, "ax"; \
+ .word 661b; \
+ casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
+ .previous
+
+#define TSB_STORE(ADDR, VAL) \
+661: stxa VAL, [ADDR] ASI_N; \
+ .section .tsb_phys_patch, "ax"; \
+ .word 661b; \
+ stxa VAL, [ADDR] ASI_PHYS_USE_EC; \
+ .previous
+
+#define TSB_LOCK_TAG(TSB, REG1, REG2) \
+99: TSB_LOAD_TAG_HIGH(TSB, REG1); \
+ sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
+ andcc REG1, REG2, %g0; \
+ bne,pn %icc, 99b; \
+ nop; \
+ TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
+ cmp REG1, REG2; \
+ bne,pn %icc, 99b; \
+ nop; \
+ TSB_MEMBAR
+
+#define TSB_WRITE(TSB, TTE, TAG) \
+ add TSB, 0x8, TSB; \
+ TSB_STORE(TSB, TTE); \
+ sub TSB, 0x8, TSB; \
+ TSB_MEMBAR; \
+ TSB_STORE(TSB, TAG);
+
+#define KTSB_LOAD_QUAD(TSB, REG) \
+ ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG;
+
+#define KTSB_STORE(ADDR, VAL) \
+ stxa VAL, [ADDR] ASI_N;
+
+#define KTSB_LOCK_TAG(TSB, REG1, REG2) \
+99: lduwa [TSB] ASI_N, REG1; \
+ sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
+ andcc REG1, REG2, %g0; \
+ bne,pn %icc, 99b; \
+ nop; \
+ casa [TSB] ASI_N, REG1, REG2;\
+ cmp REG1, REG2; \
+ bne,pn %icc, 99b; \
+ nop; \
+ TSB_MEMBAR
+
+#define KTSB_WRITE(TSB, TTE, TAG) \
+ add TSB, 0x8, TSB; \
+ stxa TTE, [TSB] ASI_N; \
+ sub TSB, 0x8, TSB; \
+ TSB_MEMBAR; \
+ stxa TAG, [TSB] ASI_N;
+
+ /* Do a kernel page table walk. Leaves physical PTE pointer in
+ * REG1. Jumps to FAIL_LABEL on early page table walk termination.
+ * VADDR will not be clobbered, but REG2 will.
+ */
+#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \
+ sethi %hi(swapper_pg_dir), REG1; \
+ or REG1, %lo(swapper_pg_dir), REG1; \
+ sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
+ srlx REG2, 64 - PAGE_SHIFT, REG2; \
+ andn REG2, 0x3, REG2; \
+ lduw [REG1 + REG2], REG1; \
+ brz,pn REG1, FAIL_LABEL; \
+ sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
+ srlx REG2, 64 - PAGE_SHIFT, REG2; \
+ sllx REG1, 11, REG1; \
+ andn REG2, 0x3, REG2; \
+ lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
+ brz,pn REG1, FAIL_LABEL; \
+ sllx VADDR, 64 - PMD_SHIFT, REG2; \
+ srlx REG2, 64 - PAGE_SHIFT, REG2; \
+ sllx REG1, 11, REG1; \
+ andn REG2, 0x7, REG2; \
+ add REG1, REG2, REG1;
+
+ /* Do a user page table walk in MMU globals. Leaves physical PTE
+ * pointer in REG1. Jumps to FAIL_LABEL on early page table walk
+ * termination. Physical base of page tables is in PHYS_PGD which
+ * will not be modified.
+ *
+ * VADDR will not be clobbered, but REG1 and REG2 will.
+ */
+#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \
+ sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
+ srlx REG2, 64 - PAGE_SHIFT, REG2; \
+ andn REG2, 0x3, REG2; \
+ lduwa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
+ brz,pn REG1, FAIL_LABEL; \
+ sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
+ srlx REG2, 64 - PAGE_SHIFT, REG2; \
+ sllx REG1, 11, REG1; \
+ andn REG2, 0x3, REG2; \
+ lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
+ brz,pn REG1, FAIL_LABEL; \
+ sllx VADDR, 64 - PMD_SHIFT, REG2; \
+ srlx REG2, 64 - PAGE_SHIFT, REG2; \
+ sllx REG1, 11, REG1; \
+ andn REG2, 0x7, REG2; \
+ add REG1, REG2, REG1;
+
+/* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0.
+ * If no entry is found, FAIL_LABEL will be branched to. On success
+ * the resulting PTE value will be left in REG1. VADDR is preserved
+ * by this routine.
+ */
+#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
+ sethi %hi(prom_trans), REG1; \
+ or REG1, %lo(prom_trans), REG1; \
+97: ldx [REG1 + 0x00], REG2; \
+ brz,pn REG2, FAIL_LABEL; \
+ nop; \
+ ldx [REG1 + 0x08], REG3; \
+ add REG2, REG3, REG3; \
+ cmp REG2, VADDR; \
+ bgu,pt %xcc, 98f; \
+ cmp VADDR, REG3; \
+ bgeu,pt %xcc, 98f; \
+ ldx [REG1 + 0x10], REG3; \
+ sub VADDR, REG2, REG2; \
+ ba,pt %xcc, 99f; \
+ add REG3, REG2, REG1; \
+98: ba,pt %xcc, 97b; \
+ add REG1, (3 * 8), REG1; \
+99:
+
+ /* We use a 32K TSB for the whole kernel, this allows to
+ * handle about 16MB of modules and vmalloc mappings without
+ * incurring many hash conflicts.
+ */
+#define KERNEL_TSB_SIZE_BYTES (32 * 1024)
+#define KERNEL_TSB_NENTRIES \
+ (KERNEL_TSB_SIZE_BYTES / 16)
+#define KERNEL_TSB4M_NENTRIES 4096
+
+ /* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL
+ * on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries
+ * and the found TTE will be left in REG1. REG3 and REG4 must
+ * be an even/odd pair of registers.
+ *
+ * VADDR and TAG will be preserved and not clobbered by this macro.
+ */
+#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
+ sethi %hi(swapper_tsb), REG1; \
+ or REG1, %lo(swapper_tsb), REG1; \
+ srlx VADDR, PAGE_SHIFT, REG2; \
+ and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
+ sllx REG2, 4, REG2; \
+ add REG1, REG2, REG2; \
+ KTSB_LOAD_QUAD(REG2, REG3); \
+ cmp REG3, TAG; \
+ be,a,pt %xcc, OK_LABEL; \
+ mov REG4, REG1;
+
+#ifndef CONFIG_DEBUG_PAGEALLOC
+ /* This version uses a trick, the TAG is already (VADDR >> 22) so
+ * we can make use of that for the index computation.
+ */
+#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
+ sethi %hi(swapper_4m_tsb), REG1; \
+ or REG1, %lo(swapper_4m_tsb), REG1; \
+ and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
+ sllx REG2, 4, REG2; \
+ add REG1, REG2, REG2; \
+ KTSB_LOAD_QUAD(REG2, REG3); \
+ cmp REG3, TAG; \
+ be,a,pt %xcc, OK_LABEL; \
+ mov REG4, REG1;
+#endif
+
+#endif /* !(_SPARC64_TSB_H) */
--- /dev/null
+/*
+ * tsunami.h: Module specific definitions for Tsunami V8 Sparcs
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_TSUNAMI_H
+#define _SPARC_TSUNAMI_H
+
+#include <asm/asi.h>
+
+/* The MMU control register on the Tsunami:
+ *
+ * -----------------------------------------------------------------------
+ * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME|
+ * -----------------------------------------------------------------------
+ * 31 24 23 22 21 20 19-18 17 16 14 13-12 11 10-9 8 7 6-2 1 0
+ *
+ * SW: Enable Software Table Walks 0=off 1=on
+ * AV: Address View bit
+ * DV: Data View bit
+ * MV: Memory View bit
+ * PC: Parity Control
+ * ITD: ITBR disable
+ * ALC: Alternate Cacheable
+ * PE: Parity Enable 0=off 1=on
+ * RC: Refresh Control
+ * IE: Instruction cache Enable 0=off 1=on
+ * DE: Data cache Enable 0=off 1=on
+ * NF: No Fault, same as all other SRMMUs
+ * ME: MMU Enable, same as all other SRMMUs
+ */
+
+#define TSUNAMI_SW 0x00800000
+#define TSUNAMI_AV 0x00400000
+#define TSUNAMI_DV 0x00200000
+#define TSUNAMI_MV 0x00100000
+#define TSUNAMI_PC 0x00020000
+#define TSUNAMI_ITD 0x00010000
+#define TSUNAMI_ALC 0x00008000
+#define TSUNAMI_PE 0x00001000
+#define TSUNAMI_RCMASK 0x00000C00
+#define TSUNAMI_IENAB 0x00000200
+#define TSUNAMI_DENAB 0x00000100
+#define TSUNAMI_NF 0x00000002
+#define TSUNAMI_ME 0x00000001
+
+static inline void tsunami_flush_icache(void)
+{
+ __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
+ : /* no outputs */
+ : "i" (ASI_M_IC_FLCLEAR)
+ : "memory");
+}
+
+static inline void tsunami_flush_dcache(void)
+{
+ __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
+ : /* no outputs */
+ : "i" (ASI_M_DC_FLCLEAR)
+ : "memory");
+}
+
+#endif /* !(_SPARC_TSUNAMI_H) */
--- /dev/null
+#ifndef _SPARC64_TTABLE_H
+#define _SPARC64_TTABLE_H
+
+#include <asm/utrap.h>
+
+#ifdef __ASSEMBLY__
+#include <asm/thread_info.h>
+#endif
+
+#define BOOT_KERNEL b sparc64_boot; nop; nop; nop; nop; nop; nop; nop;
+
+/* We need a "cleaned" instruction... */
+#define CLEAN_WINDOW \
+ rdpr %cleanwin, %l0; add %l0, 1, %l0; \
+ wrpr %l0, 0x0, %cleanwin; \
+ clr %o0; clr %o1; clr %o2; clr %o3; \
+ clr %o4; clr %o5; clr %o6; clr %o7; \
+ clr %l0; clr %l1; clr %l2; clr %l3; \
+ clr %l4; clr %l5; clr %l6; clr %l7; \
+ retry; \
+ nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
+
+#define TRAP(routine) \
+ sethi %hi(109f), %g7; \
+ ba,pt %xcc, etrap; \
+109: or %g7, %lo(109b), %g7; \
+ call routine; \
+ add %sp, PTREGS_OFF, %o0; \
+ ba,pt %xcc, rtrap; \
+ nop; \
+ nop;
+
+#define TRAP_7INSNS(routine) \
+ sethi %hi(109f), %g7; \
+ ba,pt %xcc, etrap; \
+109: or %g7, %lo(109b), %g7; \
+ call routine; \
+ add %sp, PTREGS_OFF, %o0; \
+ ba,pt %xcc, rtrap; \
+ nop;
+
+#define TRAP_SAVEFPU(routine) \
+ sethi %hi(109f), %g7; \
+ ba,pt %xcc, do_fptrap; \
+109: or %g7, %lo(109b), %g7; \
+ call routine; \
+ add %sp, PTREGS_OFF, %o0; \
+ ba,pt %xcc, rtrap; \
+ nop; \
+ nop;
+
+#define TRAP_NOSAVE(routine) \
+ ba,pt %xcc, routine; \
+ nop; \
+ nop; nop; nop; nop; nop; nop;
+
+#define TRAP_NOSAVE_7INSNS(routine) \
+ ba,pt %xcc, routine; \
+ nop; \
+ nop; nop; nop; nop; nop;
+
+#define TRAPTL1(routine) \
+ sethi %hi(109f), %g7; \
+ ba,pt %xcc, etraptl1; \
+109: or %g7, %lo(109b), %g7; \
+ call routine; \
+ add %sp, PTREGS_OFF, %o0; \
+ ba,pt %xcc, rtrap; \
+ nop; \
+ nop;
+
+#define TRAP_ARG(routine, arg) \
+ sethi %hi(109f), %g7; \
+ ba,pt %xcc, etrap; \
+109: or %g7, %lo(109b), %g7; \
+ add %sp, PTREGS_OFF, %o0; \
+ call routine; \
+ mov arg, %o1; \
+ ba,pt %xcc, rtrap; \
+ nop;
+
+#define TRAPTL1_ARG(routine, arg) \
+ sethi %hi(109f), %g7; \
+ ba,pt %xcc, etraptl1; \
+109: or %g7, %lo(109b), %g7; \
+ add %sp, PTREGS_OFF, %o0; \
+ call routine; \
+ mov arg, %o1; \
+ ba,pt %xcc, rtrap; \
+ nop;
+
+#define SYSCALL_TRAP(routine, systbl) \
+ rdpr %pil, %g2; \
+ mov TSTATE_SYSCALL, %g3; \
+ sethi %hi(109f), %g7; \
+ ba,pt %xcc, etrap_syscall; \
+109: or %g7, %lo(109b), %g7; \
+ sethi %hi(systbl), %l7; \
+ ba,pt %xcc, routine; \
+ or %l7, %lo(systbl), %l7;
+
+#define TRAP_UTRAP(handler,lvl) \
+ mov handler, %g3; \
+ ba,pt %xcc, utrap_trap; \
+ mov lvl, %g4; \
+ nop; \
+ nop; \
+ nop; \
+ nop; \
+ nop;
+
+#ifdef CONFIG_COMPAT
+#define LINUX_32BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall32, sys_call_table32)
+#else
+#define LINUX_32BIT_SYSCALL_TRAP BTRAP(0x110)
+#endif
+#define LINUX_64BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall, sys_call_table64)
+#define GETCC_TRAP TRAP(getcc)
+#define SETCC_TRAP TRAP(setcc)
+#define BREAKPOINT_TRAP TRAP(breakpoint_trap)
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+
+#define TRAP_IRQ(routine, level) \
+ rdpr %pil, %g2; \
+ wrpr %g0, 15, %pil; \
+ sethi %hi(1f-4), %g7; \
+ ba,pt %xcc, etrap_irq; \
+ or %g7, %lo(1f-4), %g7; \
+ nop; \
+ nop; \
+ nop; \
+ .subsection 2; \
+1: call trace_hardirqs_off; \
+ nop; \
+ mov level, %o0; \
+ call routine; \
+ add %sp, PTREGS_OFF, %o1; \
+ ba,a,pt %xcc, rtrap_irq; \
+ .previous;
+
+#else
+
+#define TRAP_IRQ(routine, level) \
+ rdpr %pil, %g2; \
+ wrpr %g0, 15, %pil; \
+ ba,pt %xcc, etrap_irq; \
+ rd %pc, %g7; \
+ mov level, %o0; \
+ call routine; \
+ add %sp, PTREGS_OFF, %o1; \
+ ba,a,pt %xcc, rtrap_irq;
+
+#endif
+
+#define TRAP_IVEC TRAP_NOSAVE(do_ivec)
+
+#define BTRAP(lvl) TRAP_ARG(bad_trap, lvl)
+
+#define BTRAPTL1(lvl) TRAPTL1_ARG(bad_trap_tl1, lvl)
+
+#define FLUSH_WINDOW_TRAP \
+ ba,pt %xcc, etrap; \
+ rd %pc, %g7; \
+ flushw; \
+ ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1; \
+ add %l1, 4, %l2; \
+ stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]; \
+ ba,pt %xcc, rtrap; \
+ stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC];
+
+#ifdef CONFIG_KPROBES
+#define KPROBES_TRAP(lvl) TRAP_IRQ(kprobe_trap, lvl)
+#else
+#define KPROBES_TRAP(lvl) TRAP_ARG(bad_trap, lvl)
+#endif
+
+#ifdef CONFIG_KGDB
+#define KGDB_TRAP(lvl) TRAP_IRQ(kgdb_trap, lvl)
+#else
+#define KGDB_TRAP(lvl) TRAP_ARG(bad_trap, lvl)
+#endif
+
+#define SUN4V_ITSB_MISS \
+ ldxa [%g0] ASI_SCRATCHPAD, %g2; \
+ ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4; \
+ ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5; \
+ srlx %g4, 22, %g6; \
+ ba,pt %xcc, sun4v_itsb_miss; \
+ nop; \
+ nop; \
+ nop;
+
+#define SUN4V_DTSB_MISS \
+ ldxa [%g0] ASI_SCRATCHPAD, %g2; \
+ ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4; \
+ ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5; \
+ srlx %g4, 22, %g6; \
+ ba,pt %xcc, sun4v_dtsb_miss; \
+ nop; \
+ nop; \
+ nop;
+
+/* Before touching these macros, you owe it to yourself to go and
+ * see how arch/sparc64/kernel/winfixup.S works... -DaveM
+ *
+ * For the user cases we used to use the %asi register, but
+ * it turns out that the "wr xxx, %asi" costs ~5 cycles, so
+ * now we use immediate ASI loads and stores instead. Kudos
+ * to Greg Onufer for pointing out this performance anomaly.
+ *
+ * Further note that we cannot use the g2, g4, g5, and g7 alternate
+ * globals in the spill routines, check out the save instruction in
+ * arch/sparc64/kernel/etrap.S to see what I mean about g2, and
+ * g4/g5 are the globals which are preserved by etrap processing
+ * for the caller of it. The g7 register is the return pc for
+ * etrap. Finally, g6 is the current thread register so we cannot
+ * us it in the spill handlers either. Most of these rules do not
+ * apply to fill processing, only g6 is not usable.
+ */
+
+/* Normal kernel spill */
+#define SPILL_0_NORMAL \
+ stx %l0, [%sp + STACK_BIAS + 0x00]; \
+ stx %l1, [%sp + STACK_BIAS + 0x08]; \
+ stx %l2, [%sp + STACK_BIAS + 0x10]; \
+ stx %l3, [%sp + STACK_BIAS + 0x18]; \
+ stx %l4, [%sp + STACK_BIAS + 0x20]; \
+ stx %l5, [%sp + STACK_BIAS + 0x28]; \
+ stx %l6, [%sp + STACK_BIAS + 0x30]; \
+ stx %l7, [%sp + STACK_BIAS + 0x38]; \
+ stx %i0, [%sp + STACK_BIAS + 0x40]; \
+ stx %i1, [%sp + STACK_BIAS + 0x48]; \
+ stx %i2, [%sp + STACK_BIAS + 0x50]; \
+ stx %i3, [%sp + STACK_BIAS + 0x58]; \
+ stx %i4, [%sp + STACK_BIAS + 0x60]; \
+ stx %i5, [%sp + STACK_BIAS + 0x68]; \
+ stx %i6, [%sp + STACK_BIAS + 0x70]; \
+ stx %i7, [%sp + STACK_BIAS + 0x78]; \
+ saved; retry; nop; nop; nop; nop; nop; nop; \
+ nop; nop; nop; nop; nop; nop; nop; nop;
+
+#define SPILL_0_NORMAL_ETRAP \
+etrap_kernel_spill: \
+ stx %l0, [%sp + STACK_BIAS + 0x00]; \
+ stx %l1, [%sp + STACK_BIAS + 0x08]; \
+ stx %l2, [%sp + STACK_BIAS + 0x10]; \
+ stx %l3, [%sp + STACK_BIAS + 0x18]; \
+ stx %l4, [%sp + STACK_BIAS + 0x20]; \
+ stx %l5, [%sp + STACK_BIAS + 0x28]; \
+ stx %l6, [%sp + STACK_BIAS + 0x30]; \
+ stx %l7, [%sp + STACK_BIAS + 0x38]; \
+ stx %i0, [%sp + STACK_BIAS + 0x40]; \
+ stx %i1, [%sp + STACK_BIAS + 0x48]; \
+ stx %i2, [%sp + STACK_BIAS + 0x50]; \
+ stx %i3, [%sp + STACK_BIAS + 0x58]; \
+ stx %i4, [%sp + STACK_BIAS + 0x60]; \
+ stx %i5, [%sp + STACK_BIAS + 0x68]; \
+ stx %i6, [%sp + STACK_BIAS + 0x70]; \
+ stx %i7, [%sp + STACK_BIAS + 0x78]; \
+ saved; \
+ sub %g1, 2, %g1; \
+ ba,pt %xcc, etrap_save; \
+ wrpr %g1, %cwp; \
+ nop; nop; nop; nop; nop; nop; nop; nop; \
+ nop; nop; nop; nop;
+
+/* Normal 64bit spill */
+#define SPILL_1_GENERIC(ASI) \
+ add %sp, STACK_BIAS + 0x00, %g1; \
+ stxa %l0, [%g1 + %g0] ASI; \
+ mov 0x08, %g3; \
+ stxa %l1, [%g1 + %g3] ASI; \
+ add %g1, 0x10, %g1; \
+ stxa %l2, [%g1 + %g0] ASI; \
+ stxa %l3, [%g1 + %g3] ASI; \
+ add %g1, 0x10, %g1; \
+ stxa %l4, [%g1 + %g0] ASI; \
+ stxa %l5, [%g1 + %g3] ASI; \
+ add %g1, 0x10, %g1; \
+ stxa %l6, [%g1 + %g0] ASI; \
+ stxa %l7, [%g1 + %g3] ASI; \
+ add %g1, 0x10, %g1; \
+ stxa %i0, [%g1 + %g0] ASI; \
+ stxa %i1, [%g1 + %g3] ASI; \
+ add %g1, 0x10, %g1; \
+ stxa %i2, [%g1 + %g0] ASI; \
+ stxa %i3, [%g1 + %g3] ASI; \
+ add %g1, 0x10, %g1; \
+ stxa %i4, [%g1 + %g0] ASI; \
+ stxa %i5, [%g1 + %g3] ASI; \
+ add %g1, 0x10, %g1; \
+ stxa %i6, [%g1 + %g0] ASI; \
+ stxa %i7, [%g1 + %g3] ASI; \
+ saved; \
+ retry; nop; nop; \
+ b,a,pt %xcc, spill_fixup_dax; \
+ b,a,pt %xcc, spill_fixup_mna; \
+ b,a,pt %xcc, spill_fixup;
+
+#define SPILL_1_GENERIC_ETRAP \
+etrap_user_spill_64bit: \
+ stxa %l0, [%sp + STACK_BIAS + 0x00] %asi; \
+ stxa %l1, [%sp + STACK_BIAS + 0x08] %asi; \
+ stxa %l2, [%sp + STACK_BIAS + 0x10] %asi; \
+ stxa %l3, [%sp + STACK_BIAS + 0x18] %asi; \
+ stxa %l4, [%sp + STACK_BIAS + 0x20] %asi; \
+ stxa %l5, [%sp + STACK_BIAS + 0x28] %asi; \
+ stxa %l6, [%sp + STACK_BIAS + 0x30] %asi; \
+ stxa %l7, [%sp + STACK_BIAS + 0x38] %asi; \
+ stxa %i0, [%sp + STACK_BIAS + 0x40] %asi; \
+ stxa %i1, [%sp + STACK_BIAS + 0x48] %asi; \
+ stxa %i2, [%sp + STACK_BIAS + 0x50] %asi; \
+ stxa %i3, [%sp + STACK_BIAS + 0x58] %asi; \
+ stxa %i4, [%sp + STACK_BIAS + 0x60] %asi; \
+ stxa %i5, [%sp + STACK_BIAS + 0x68] %asi; \
+ stxa %i6, [%sp + STACK_BIAS + 0x70] %asi; \
+ stxa %i7, [%sp + STACK_BIAS + 0x78] %asi; \
+ saved; \
+ sub %g1, 2, %g1; \
+ ba,pt %xcc, etrap_save; \
+ wrpr %g1, %cwp; \
+ nop; nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ ba,a,pt %xcc, etrap_spill_fixup_64bit; \
+ ba,a,pt %xcc, etrap_spill_fixup_64bit; \
+ ba,a,pt %xcc, etrap_spill_fixup_64bit;
+
+#define SPILL_1_GENERIC_ETRAP_FIXUP \
+etrap_spill_fixup_64bit: \
+ ldub [%g6 + TI_WSAVED], %g1; \
+ sll %g1, 3, %g3; \
+ add %g6, %g3, %g3; \
+ stx %sp, [%g3 + TI_RWIN_SPTRS]; \
+ sll %g1, 7, %g3; \
+ add %g6, %g3, %g3; \
+ stx %l0, [%g3 + TI_REG_WINDOW + 0x00]; \
+ stx %l1, [%g3 + TI_REG_WINDOW + 0x08]; \
+ stx %l2, [%g3 + TI_REG_WINDOW + 0x10]; \
+ stx %l3, [%g3 + TI_REG_WINDOW + 0x18]; \
+ stx %l4, [%g3 + TI_REG_WINDOW + 0x20]; \
+ stx %l5, [%g3 + TI_REG_WINDOW + 0x28]; \
+ stx %l6, [%g3 + TI_REG_WINDOW + 0x30]; \
+ stx %l7, [%g3 + TI_REG_WINDOW + 0x38]; \
+ stx %i0, [%g3 + TI_REG_WINDOW + 0x40]; \
+ stx %i1, [%g3 + TI_REG_WINDOW + 0x48]; \
+ stx %i2, [%g3 + TI_REG_WINDOW + 0x50]; \
+ stx %i3, [%g3 + TI_REG_WINDOW + 0x58]; \
+ stx %i4, [%g3 + TI_REG_WINDOW + 0x60]; \
+ stx %i5, [%g3 + TI_REG_WINDOW + 0x68]; \
+ stx %i6, [%g3 + TI_REG_WINDOW + 0x70]; \
+ stx %i7, [%g3 + TI_REG_WINDOW + 0x78]; \
+ add %g1, 1, %g1; \
+ stb %g1, [%g6 + TI_WSAVED]; \
+ saved; \
+ rdpr %cwp, %g1; \
+ sub %g1, 2, %g1; \
+ ba,pt %xcc, etrap_save; \
+ wrpr %g1, %cwp; \
+ nop; nop; nop
+
+/* Normal 32bit spill */
+#define SPILL_2_GENERIC(ASI) \
+ srl %sp, 0, %sp; \
+ stwa %l0, [%sp + %g0] ASI; \
+ mov 0x04, %g3; \
+ stwa %l1, [%sp + %g3] ASI; \
+ add %sp, 0x08, %g1; \
+ stwa %l2, [%g1 + %g0] ASI; \
+ stwa %l3, [%g1 + %g3] ASI; \
+ add %g1, 0x08, %g1; \
+ stwa %l4, [%g1 + %g0] ASI; \
+ stwa %l5, [%g1 + %g3] ASI; \
+ add %g1, 0x08, %g1; \
+ stwa %l6, [%g1 + %g0] ASI; \
+ stwa %l7, [%g1 + %g3] ASI; \
+ add %g1, 0x08, %g1; \
+ stwa %i0, [%g1 + %g0] ASI; \
+ stwa %i1, [%g1 + %g3] ASI; \
+ add %g1, 0x08, %g1; \
+ stwa %i2, [%g1 + %g0] ASI; \
+ stwa %i3, [%g1 + %g3] ASI; \
+ add %g1, 0x08, %g1; \
+ stwa %i4, [%g1 + %g0] ASI; \
+ stwa %i5, [%g1 + %g3] ASI; \
+ add %g1, 0x08, %g1; \
+ stwa %i6, [%g1 + %g0] ASI; \
+ stwa %i7, [%g1 + %g3] ASI; \
+ saved; \
+ retry; nop; nop; \
+ b,a,pt %xcc, spill_fixup_dax; \
+ b,a,pt %xcc, spill_fixup_mna; \
+ b,a,pt %xcc, spill_fixup;
+
+#define SPILL_2_GENERIC_ETRAP \
+etrap_user_spill_32bit: \
+ srl %sp, 0, %sp; \
+ stwa %l0, [%sp + 0x00] %asi; \
+ stwa %l1, [%sp + 0x04] %asi; \
+ stwa %l2, [%sp + 0x08] %asi; \
+ stwa %l3, [%sp + 0x0c] %asi; \
+ stwa %l4, [%sp + 0x10] %asi; \
+ stwa %l5, [%sp + 0x14] %asi; \
+ stwa %l6, [%sp + 0x18] %asi; \
+ stwa %l7, [%sp + 0x1c] %asi; \
+ stwa %i0, [%sp + 0x20] %asi; \
+ stwa %i1, [%sp + 0x24] %asi; \
+ stwa %i2, [%sp + 0x28] %asi; \
+ stwa %i3, [%sp + 0x2c] %asi; \
+ stwa %i4, [%sp + 0x30] %asi; \
+ stwa %i5, [%sp + 0x34] %asi; \
+ stwa %i6, [%sp + 0x38] %asi; \
+ stwa %i7, [%sp + 0x3c] %asi; \
+ saved; \
+ sub %g1, 2, %g1; \
+ ba,pt %xcc, etrap_save; \
+ wrpr %g1, %cwp; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ ba,a,pt %xcc, etrap_spill_fixup_32bit; \
+ ba,a,pt %xcc, etrap_spill_fixup_32bit; \
+ ba,a,pt %xcc, etrap_spill_fixup_32bit;
+
+#define SPILL_2_GENERIC_ETRAP_FIXUP \
+etrap_spill_fixup_32bit: \
+ ldub [%g6 + TI_WSAVED], %g1; \
+ sll %g1, 3, %g3; \
+ add %g6, %g3, %g3; \
+ stx %sp, [%g3 + TI_RWIN_SPTRS]; \
+ sll %g1, 7, %g3; \
+ add %g6, %g3, %g3; \
+ stw %l0, [%g3 + TI_REG_WINDOW + 0x00]; \
+ stw %l1, [%g3 + TI_REG_WINDOW + 0x04]; \
+ stw %l2, [%g3 + TI_REG_WINDOW + 0x08]; \
+ stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]; \
+ stw %l4, [%g3 + TI_REG_WINDOW + 0x10]; \
+ stw %l5, [%g3 + TI_REG_WINDOW + 0x14]; \
+ stw %l6, [%g3 + TI_REG_WINDOW + 0x18]; \
+ stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]; \
+ stw %i0, [%g3 + TI_REG_WINDOW + 0x20]; \
+ stw %i1, [%g3 + TI_REG_WINDOW + 0x24]; \
+ stw %i2, [%g3 + TI_REG_WINDOW + 0x28]; \
+ stw %i3, [%g3 + TI_REG_WINDOW + 0x2c]; \
+ stw %i4, [%g3 + TI_REG_WINDOW + 0x30]; \
+ stw %i5, [%g3 + TI_REG_WINDOW + 0x34]; \
+ stw %i6, [%g3 + TI_REG_WINDOW + 0x38]; \
+ stw %i7, [%g3 + TI_REG_WINDOW + 0x3c]; \
+ add %g1, 1, %g1; \
+ stb %g1, [%g6 + TI_WSAVED]; \
+ saved; \
+ rdpr %cwp, %g1; \
+ sub %g1, 2, %g1; \
+ ba,pt %xcc, etrap_save; \
+ wrpr %g1, %cwp; \
+ nop; nop; nop
+
+#define SPILL_1_NORMAL SPILL_1_GENERIC(ASI_AIUP)
+#define SPILL_2_NORMAL SPILL_2_GENERIC(ASI_AIUP)
+#define SPILL_3_NORMAL SPILL_0_NORMAL
+#define SPILL_4_NORMAL SPILL_0_NORMAL
+#define SPILL_5_NORMAL SPILL_0_NORMAL
+#define SPILL_6_NORMAL SPILL_0_NORMAL
+#define SPILL_7_NORMAL SPILL_0_NORMAL
+
+#define SPILL_0_OTHER SPILL_0_NORMAL
+#define SPILL_1_OTHER SPILL_1_GENERIC(ASI_AIUS)
+#define SPILL_2_OTHER SPILL_2_GENERIC(ASI_AIUS)
+#define SPILL_3_OTHER SPILL_3_NORMAL
+#define SPILL_4_OTHER SPILL_4_NORMAL
+#define SPILL_5_OTHER SPILL_5_NORMAL
+#define SPILL_6_OTHER SPILL_6_NORMAL
+#define SPILL_7_OTHER SPILL_7_NORMAL
+
+/* Normal kernel fill */
+#define FILL_0_NORMAL \
+ ldx [%sp + STACK_BIAS + 0x00], %l0; \
+ ldx [%sp + STACK_BIAS + 0x08], %l1; \
+ ldx [%sp + STACK_BIAS + 0x10], %l2; \
+ ldx [%sp + STACK_BIAS + 0x18], %l3; \
+ ldx [%sp + STACK_BIAS + 0x20], %l4; \
+ ldx [%sp + STACK_BIAS + 0x28], %l5; \
+ ldx [%sp + STACK_BIAS + 0x30], %l6; \
+ ldx [%sp + STACK_BIAS + 0x38], %l7; \
+ ldx [%sp + STACK_BIAS + 0x40], %i0; \
+ ldx [%sp + STACK_BIAS + 0x48], %i1; \
+ ldx [%sp + STACK_BIAS + 0x50], %i2; \
+ ldx [%sp + STACK_BIAS + 0x58], %i3; \
+ ldx [%sp + STACK_BIAS + 0x60], %i4; \
+ ldx [%sp + STACK_BIAS + 0x68], %i5; \
+ ldx [%sp + STACK_BIAS + 0x70], %i6; \
+ ldx [%sp + STACK_BIAS + 0x78], %i7; \
+ restored; retry; nop; nop; nop; nop; nop; nop; \
+ nop; nop; nop; nop; nop; nop; nop; nop;
+
+#define FILL_0_NORMAL_RTRAP \
+kern_rtt_fill: \
+ rdpr %cwp, %g1; \
+ sub %g1, 1, %g1; \
+ wrpr %g1, %cwp; \
+ ldx [%sp + STACK_BIAS + 0x00], %l0; \
+ ldx [%sp + STACK_BIAS + 0x08], %l1; \
+ ldx [%sp + STACK_BIAS + 0x10], %l2; \
+ ldx [%sp + STACK_BIAS + 0x18], %l3; \
+ ldx [%sp + STACK_BIAS + 0x20], %l4; \
+ ldx [%sp + STACK_BIAS + 0x28], %l5; \
+ ldx [%sp + STACK_BIAS + 0x30], %l6; \
+ ldx [%sp + STACK_BIAS + 0x38], %l7; \
+ ldx [%sp + STACK_BIAS + 0x40], %i0; \
+ ldx [%sp + STACK_BIAS + 0x48], %i1; \
+ ldx [%sp + STACK_BIAS + 0x50], %i2; \
+ ldx [%sp + STACK_BIAS + 0x58], %i3; \
+ ldx [%sp + STACK_BIAS + 0x60], %i4; \
+ ldx [%sp + STACK_BIAS + 0x68], %i5; \
+ ldx [%sp + STACK_BIAS + 0x70], %i6; \
+ ldx [%sp + STACK_BIAS + 0x78], %i7; \
+ restored; \
+ add %g1, 1, %g1; \
+ ba,pt %xcc, kern_rtt_restore; \
+ wrpr %g1, %cwp; \
+ nop; nop; nop; nop; nop; \
+ nop; nop; nop; nop;
+
+
+/* Normal 64bit fill */
+#define FILL_1_GENERIC(ASI) \
+ add %sp, STACK_BIAS + 0x00, %g1; \
+ ldxa [%g1 + %g0] ASI, %l0; \
+ mov 0x08, %g2; \
+ mov 0x10, %g3; \
+ ldxa [%g1 + %g2] ASI, %l1; \
+ mov 0x18, %g5; \
+ ldxa [%g1 + %g3] ASI, %l2; \
+ ldxa [%g1 + %g5] ASI, %l3; \
+ add %g1, 0x20, %g1; \
+ ldxa [%g1 + %g0] ASI, %l4; \
+ ldxa [%g1 + %g2] ASI, %l5; \
+ ldxa [%g1 + %g3] ASI, %l6; \
+ ldxa [%g1 + %g5] ASI, %l7; \
+ add %g1, 0x20, %g1; \
+ ldxa [%g1 + %g0] ASI, %i0; \
+ ldxa [%g1 + %g2] ASI, %i1; \
+ ldxa [%g1 + %g3] ASI, %i2; \
+ ldxa [%g1 + %g5] ASI, %i3; \
+ add %g1, 0x20, %g1; \
+ ldxa [%g1 + %g0] ASI, %i4; \
+ ldxa [%g1 + %g2] ASI, %i5; \
+ ldxa [%g1 + %g3] ASI, %i6; \
+ ldxa [%g1 + %g5] ASI, %i7; \
+ restored; \
+ retry; nop; nop; nop; nop; \
+ b,a,pt %xcc, fill_fixup_dax; \
+ b,a,pt %xcc, fill_fixup_mna; \
+ b,a,pt %xcc, fill_fixup;
+
+#define FILL_1_GENERIC_RTRAP \
+user_rtt_fill_64bit: \
+ ldxa [%sp + STACK_BIAS + 0x00] %asi, %l0; \
+ ldxa [%sp + STACK_BIAS + 0x08] %asi, %l1; \
+ ldxa [%sp + STACK_BIAS + 0x10] %asi, %l2; \
+ ldxa [%sp + STACK_BIAS + 0x18] %asi, %l3; \
+ ldxa [%sp + STACK_BIAS + 0x20] %asi, %l4; \
+ ldxa [%sp + STACK_BIAS + 0x28] %asi, %l5; \
+ ldxa [%sp + STACK_BIAS + 0x30] %asi, %l6; \
+ ldxa [%sp + STACK_BIAS + 0x38] %asi, %l7; \
+ ldxa [%sp + STACK_BIAS + 0x40] %asi, %i0; \
+ ldxa [%sp + STACK_BIAS + 0x48] %asi, %i1; \
+ ldxa [%sp + STACK_BIAS + 0x50] %asi, %i2; \
+ ldxa [%sp + STACK_BIAS + 0x58] %asi, %i3; \
+ ldxa [%sp + STACK_BIAS + 0x60] %asi, %i4; \
+ ldxa [%sp + STACK_BIAS + 0x68] %asi, %i5; \
+ ldxa [%sp + STACK_BIAS + 0x70] %asi, %i6; \
+ ldxa [%sp + STACK_BIAS + 0x78] %asi, %i7; \
+ ba,pt %xcc, user_rtt_pre_restore; \
+ restored; \
+ nop; nop; nop; nop; nop; nop; \
+ nop; nop; nop; nop; nop; \
+ ba,a,pt %xcc, user_rtt_fill_fixup; \
+ ba,a,pt %xcc, user_rtt_fill_fixup; \
+ ba,a,pt %xcc, user_rtt_fill_fixup;
+
+
+/* Normal 32bit fill */
+#define FILL_2_GENERIC(ASI) \
+ srl %sp, 0, %sp; \
+ lduwa [%sp + %g0] ASI, %l0; \
+ mov 0x04, %g2; \
+ mov 0x08, %g3; \
+ lduwa [%sp + %g2] ASI, %l1; \
+ mov 0x0c, %g5; \
+ lduwa [%sp + %g3] ASI, %l2; \
+ lduwa [%sp + %g5] ASI, %l3; \
+ add %sp, 0x10, %g1; \
+ lduwa [%g1 + %g0] ASI, %l4; \
+ lduwa [%g1 + %g2] ASI, %l5; \
+ lduwa [%g1 + %g3] ASI, %l6; \
+ lduwa [%g1 + %g5] ASI, %l7; \
+ add %g1, 0x10, %g1; \
+ lduwa [%g1 + %g0] ASI, %i0; \
+ lduwa [%g1 + %g2] ASI, %i1; \
+ lduwa [%g1 + %g3] ASI, %i2; \
+ lduwa [%g1 + %g5] ASI, %i3; \
+ add %g1, 0x10, %g1; \
+ lduwa [%g1 + %g0] ASI, %i4; \
+ lduwa [%g1 + %g2] ASI, %i5; \
+ lduwa [%g1 + %g3] ASI, %i6; \
+ lduwa [%g1 + %g5] ASI, %i7; \
+ restored; \
+ retry; nop; nop; nop; nop; \
+ b,a,pt %xcc, fill_fixup_dax; \
+ b,a,pt %xcc, fill_fixup_mna; \
+ b,a,pt %xcc, fill_fixup;
+
+#define FILL_2_GENERIC_RTRAP \
+user_rtt_fill_32bit: \
+ srl %sp, 0, %sp; \
+ lduwa [%sp + 0x00] %asi, %l0; \
+ lduwa [%sp + 0x04] %asi, %l1; \
+ lduwa [%sp + 0x08] %asi, %l2; \
+ lduwa [%sp + 0x0c] %asi, %l3; \
+ lduwa [%sp + 0x10] %asi, %l4; \
+ lduwa [%sp + 0x14] %asi, %l5; \
+ lduwa [%sp + 0x18] %asi, %l6; \
+ lduwa [%sp + 0x1c] %asi, %l7; \
+ lduwa [%sp + 0x20] %asi, %i0; \
+ lduwa [%sp + 0x24] %asi, %i1; \
+ lduwa [%sp + 0x28] %asi, %i2; \
+ lduwa [%sp + 0x2c] %asi, %i3; \
+ lduwa [%sp + 0x30] %asi, %i4; \
+ lduwa [%sp + 0x34] %asi, %i5; \
+ lduwa [%sp + 0x38] %asi, %i6; \
+ lduwa [%sp + 0x3c] %asi, %i7; \
+ ba,pt %xcc, user_rtt_pre_restore; \
+ restored; \
+ nop; nop; nop; nop; nop; \
+ nop; nop; nop; nop; nop; \
+ ba,a,pt %xcc, user_rtt_fill_fixup; \
+ ba,a,pt %xcc, user_rtt_fill_fixup; \
+ ba,a,pt %xcc, user_rtt_fill_fixup;
+
+
+#define FILL_1_NORMAL FILL_1_GENERIC(ASI_AIUP)
+#define FILL_2_NORMAL FILL_2_GENERIC(ASI_AIUP)
+#define FILL_3_NORMAL FILL_0_NORMAL
+#define FILL_4_NORMAL FILL_0_NORMAL
+#define FILL_5_NORMAL FILL_0_NORMAL
+#define FILL_6_NORMAL FILL_0_NORMAL
+#define FILL_7_NORMAL FILL_0_NORMAL
+
+#define FILL_0_OTHER FILL_0_NORMAL
+#define FILL_1_OTHER FILL_1_GENERIC(ASI_AIUS)
+#define FILL_2_OTHER FILL_2_GENERIC(ASI_AIUS)
+#define FILL_3_OTHER FILL_3_NORMAL
+#define FILL_4_OTHER FILL_4_NORMAL
+#define FILL_5_OTHER FILL_5_NORMAL
+#define FILL_6_OTHER FILL_6_NORMAL
+#define FILL_7_OTHER FILL_7_NORMAL
+
+#endif /* !(_SPARC64_TTABLE_H) */
--- /dev/null
+/*
+ * turbosparc.h: Defines specific to the TurboSparc module.
+ * This is SRMMU stuff.
+ *
+ * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+#ifndef _SPARC_TURBOSPARC_H
+#define _SPARC_TURBOSPARC_H
+
+#include <asm/asi.h>
+#include <asm/pgtsrmmu.h>
+
+/* Bits in the SRMMU control register for TurboSparc modules.
+ *
+ * -------------------------------------------------------------------
+ * |impl-vers| RSV| PMC |PE|PC| RSV |BM| RFR |IC|DC|PSO|RSV|ICS|NF|ME|
+ * -------------------------------------------------------------------
+ * 31 24 23-21 20-19 18 17 16-15 14 13-10 9 8 7 6-3 2 1 0
+ *
+ * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
+ *
+ * This indicates whether the TurboSparc is in boot-mode or not.
+ *
+ * IC: Instruction Cache -- 0 = off, 1 = on
+ * DC: Data Cache -- 0 = off, 1 = 0n
+ *
+ * These bits enable the on-cpu TurboSparc split I/D caches.
+ *
+ * ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache
+ * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
+ * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
+ *
+ */
+
+#define TURBOSPARC_MMUENABLE 0x00000001
+#define TURBOSPARC_NOFAULT 0x00000002
+#define TURBOSPARC_ICSNOOP 0x00000004
+#define TURBOSPARC_PSO 0x00000080
+#define TURBOSPARC_DCENABLE 0x00000100 /* Enable data cache */
+#define TURBOSPARC_ICENABLE 0x00000200 /* Enable instruction cache */
+#define TURBOSPARC_BMODE 0x00004000
+#define TURBOSPARC_PARITYODD 0x00020000 /* Parity odd, if enabled */
+#define TURBOSPARC_PCENABLE 0x00040000 /* Enable parity checking */
+
+/* Bits in the CPU configuration register for TurboSparc modules.
+ *
+ * -------------------------------------------------------
+ * |IOClk|SNP|AXClk| RAH | WS | RSV |SBC|WT|uS2|SE|SCC|
+ * -------------------------------------------------------
+ * 31 30 29-28 27-26 25-23 22-8 7-6 5 4 3 2-0
+ *
+ */
+
+#define TURBOSPARC_SCENABLE 0x00000008 /* Secondary cache enable */
+#define TURBOSPARC_uS2 0x00000010 /* Swift compatibility mode */
+#define TURBOSPARC_WTENABLE 0x00000020 /* Write thru for dcache */
+#define TURBOSPARC_SNENABLE 0x40000000 /* DVMA snoop enable */
+
+#ifndef __ASSEMBLY__
+
+/* Bits [13:5] select one of 512 instruction cache tags */
+static inline void turbosparc_inv_insn_tag(unsigned long addr)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" (addr), "i" (ASI_M_TXTC_TAG)
+ : "memory");
+}
+
+/* Bits [13:5] select one of 512 data cache tags */
+static inline void turbosparc_inv_data_tag(unsigned long addr)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" (addr), "i" (ASI_M_DATAC_TAG)
+ : "memory");
+}
+
+static inline void turbosparc_flush_icache(void)
+{
+ unsigned long addr;
+
+ for (addr = 0; addr < 0x4000; addr += 0x20)
+ turbosparc_inv_insn_tag(addr);
+}
+
+static inline void turbosparc_flush_dcache(void)
+{
+ unsigned long addr;
+
+ for (addr = 0; addr < 0x4000; addr += 0x20)
+ turbosparc_inv_data_tag(addr);
+}
+
+static inline void turbosparc_idflash_clear(void)
+{
+ unsigned long addr;
+
+ for (addr = 0; addr < 0x4000; addr += 0x20) {
+ turbosparc_inv_insn_tag(addr);
+ turbosparc_inv_data_tag(addr);
+ }
+}
+
+static inline void turbosparc_set_ccreg(unsigned long regval)
+{
+ __asm__ __volatile__("sta %0, [%1] %2\n\t"
+ : /* no outputs */
+ : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS)
+ : "memory");
+}
+
+static inline unsigned long turbosparc_get_ccreg(void)
+{
+ unsigned long regval;
+
+ __asm__ __volatile__("lda [%1] %2, %0\n\t"
+ : "=r" (regval)
+ : "r" (0x600), "i" (ASI_M_MMUREGS));
+ return regval;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* !(_SPARC_TURBOSPARC_H) */
--- /dev/null
+#ifndef _SPARC_TYPES_H
+#define _SPARC_TYPES_H
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue. However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+
+#if defined(__sparc__) && defined(__arch64__)
+
+/*** SPARC 64 bit ***/
+#include <asm-generic/int-l64.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 64
+
+#ifndef __ASSEMBLY__
+
+/* Dma addresses come in generic and 64-bit flavours. */
+
+typedef u32 dma_addr_t;
+typedef u64 dma64_addr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+#else
+
+/*** SPARC 32 bit ***/
+#include <asm-generic/int-ll64.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+typedef u32 dma_addr_t;
+typedef u32 dma64_addr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* defined(__sparc__) && defined(__arch64__) */
+
+#endif /* defined(_SPARC_TYPES_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_UACCESS_H
+#define ___ASM_SPARC_UACCESS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/uaccess_64.h>
+#else
+#include <asm/uaccess_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * uaccess.h: User space memore access functions.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+#ifndef _ASM_UACCESS_H
+#define _ASM_UACCESS_H
+
+#ifdef __KERNEL__
+#include <linux/compiler.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <asm/vac-ops.h>
+#endif
+
+#ifndef __ASSEMBLY__
+
+/* Sparc is not segmented, however we need to be able to fool access_ok()
+ * when doing system calls from kernel mode legitimately.
+ *
+ * "For historical reasons, these macros are grossly misnamed." -Linus
+ */
+
+#define KERNEL_DS ((mm_segment_t) { 0 })
+#define USER_DS ((mm_segment_t) { -1 })
+
+#define VERIFY_READ 0
+#define VERIFY_WRITE 1
+
+#define get_ds() (KERNEL_DS)
+#define get_fs() (current->thread.current_ds)
+#define set_fs(val) ((current->thread.current_ds) = (val))
+
+#define segment_eq(a,b) ((a).seg == (b).seg)
+
+/* We have there a nice not-mapped page at PAGE_OFFSET - PAGE_SIZE, so that this test
+ * can be fairly lightweight.
+ * No one can read/write anything from userland in the kernel space by setting
+ * large size and address near to PAGE_OFFSET - a fault will break his intentions.
+ */
+#define __user_ok(addr, size) ({ (void)(size); (addr) < STACK_TOP; })
+#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS))
+#define __access_ok(addr,size) (__user_ok((addr) & get_fs().seg,(size)))
+#define access_ok(type, addr, size) \
+ ({ (void)(type); __access_ok((unsigned long)(addr), size); })
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue. No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path. This means when everything is well,
+ * we don't even have to jump over them. Further, they do not intrude
+ * on our cache or tlb entries.
+ *
+ * There is a special way how to put a range of potentially faulting
+ * insns (like twenty ldd/std's with now intervening other instructions)
+ * You specify address of first in insn and 0 in fixup and in the next
+ * exception_table_entry you specify last potentially faulting insn + 1
+ * and in fixup the routine which should handle the fault.
+ * That fixup code will get
+ * (faulting_insn_address - first_insn_in_the_range_address)/4
+ * in %g2 (ie. index of the faulting instruction in the range).
+ */
+
+struct exception_table_entry
+{
+ unsigned long insn, fixup;
+};
+
+/* Returns 0 if exception not found and fixup otherwise. */
+extern unsigned long search_extables_range(unsigned long addr, unsigned long *g2);
+
+extern void __ret_efault(void);
+
+/* Uh, these should become the main single-value transfer routines..
+ * They automatically use the right size if we just have the right
+ * pointer type..
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ */
+#define put_user(x,ptr) ({ \
+unsigned long __pu_addr = (unsigned long)(ptr); \
+__chk_user_ptr(ptr); \
+__put_user_check((__typeof__(*(ptr)))(x),__pu_addr,sizeof(*(ptr))); })
+
+#define get_user(x,ptr) ({ \
+unsigned long __gu_addr = (unsigned long)(ptr); \
+__chk_user_ptr(ptr); \
+__get_user_check((x),__gu_addr,sizeof(*(ptr)),__typeof__(*(ptr))); })
+
+/*
+ * The "__xxx" versions do not do address space checking, useful when
+ * doing multiple accesses to the same area (the user has to do the
+ * checks by hand with "access_ok()")
+ */
+#define __put_user(x,ptr) __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
+#define __get_user(x,ptr) __get_user_nocheck((x),(ptr),sizeof(*(ptr)),__typeof__(*(ptr)))
+
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) ((struct __large_struct __user *)(x))
+
+#define __put_user_check(x,addr,size) ({ \
+register int __pu_ret; \
+if (__access_ok(addr,size)) { \
+switch (size) { \
+case 1: __put_user_asm(x,b,addr,__pu_ret); break; \
+case 2: __put_user_asm(x,h,addr,__pu_ret); break; \
+case 4: __put_user_asm(x,,addr,__pu_ret); break; \
+case 8: __put_user_asm(x,d,addr,__pu_ret); break; \
+default: __pu_ret = __put_user_bad(); break; \
+} } else { __pu_ret = -EFAULT; } __pu_ret; })
+
+#define __put_user_nocheck(x,addr,size) ({ \
+register int __pu_ret; \
+switch (size) { \
+case 1: __put_user_asm(x,b,addr,__pu_ret); break; \
+case 2: __put_user_asm(x,h,addr,__pu_ret); break; \
+case 4: __put_user_asm(x,,addr,__pu_ret); break; \
+case 8: __put_user_asm(x,d,addr,__pu_ret); break; \
+default: __pu_ret = __put_user_bad(); break; \
+} __pu_ret; })
+
+#define __put_user_asm(x,size,addr,ret) \
+__asm__ __volatile__( \
+ "/* Put user asm, inline. */\n" \
+"1:\t" "st"#size " %1, %2\n\t" \
+ "clr %0\n" \
+"2:\n\n\t" \
+ ".section .fixup,#alloc,#execinstr\n\t" \
+ ".align 4\n" \
+"3:\n\t" \
+ "b 2b\n\t" \
+ " mov %3, %0\n\t" \
+ ".previous\n\n\t" \
+ ".section __ex_table,#alloc\n\t" \
+ ".align 4\n\t" \
+ ".word 1b, 3b\n\t" \
+ ".previous\n\n\t" \
+ : "=&r" (ret) : "r" (x), "m" (*__m(addr)), \
+ "i" (-EFAULT))
+
+extern int __put_user_bad(void);
+
+#define __get_user_check(x,addr,size,type) ({ \
+register int __gu_ret; \
+register unsigned long __gu_val; \
+if (__access_ok(addr,size)) { \
+switch (size) { \
+case 1: __get_user_asm(__gu_val,ub,addr,__gu_ret); break; \
+case 2: __get_user_asm(__gu_val,uh,addr,__gu_ret); break; \
+case 4: __get_user_asm(__gu_val,,addr,__gu_ret); break; \
+case 8: __get_user_asm(__gu_val,d,addr,__gu_ret); break; \
+default: __gu_val = 0; __gu_ret = __get_user_bad(); break; \
+} } else { __gu_val = 0; __gu_ret = -EFAULT; } x = (type) __gu_val; __gu_ret; })
+
+#define __get_user_check_ret(x,addr,size,type,retval) ({ \
+register unsigned long __gu_val __asm__ ("l1"); \
+if (__access_ok(addr,size)) { \
+switch (size) { \
+case 1: __get_user_asm_ret(__gu_val,ub,addr,retval); break; \
+case 2: __get_user_asm_ret(__gu_val,uh,addr,retval); break; \
+case 4: __get_user_asm_ret(__gu_val,,addr,retval); break; \
+case 8: __get_user_asm_ret(__gu_val,d,addr,retval); break; \
+default: if (__get_user_bad()) return retval; \
+} x = (type) __gu_val; } else return retval; })
+
+#define __get_user_nocheck(x,addr,size,type) ({ \
+register int __gu_ret; \
+register unsigned long __gu_val; \
+switch (size) { \
+case 1: __get_user_asm(__gu_val,ub,addr,__gu_ret); break; \
+case 2: __get_user_asm(__gu_val,uh,addr,__gu_ret); break; \
+case 4: __get_user_asm(__gu_val,,addr,__gu_ret); break; \
+case 8: __get_user_asm(__gu_val,d,addr,__gu_ret); break; \
+default: __gu_val = 0; __gu_ret = __get_user_bad(); break; \
+} x = (type) __gu_val; __gu_ret; })
+
+#define __get_user_nocheck_ret(x,addr,size,type,retval) ({ \
+register unsigned long __gu_val __asm__ ("l1"); \
+switch (size) { \
+case 1: __get_user_asm_ret(__gu_val,ub,addr,retval); break; \
+case 2: __get_user_asm_ret(__gu_val,uh,addr,retval); break; \
+case 4: __get_user_asm_ret(__gu_val,,addr,retval); break; \
+case 8: __get_user_asm_ret(__gu_val,d,addr,retval); break; \
+default: if (__get_user_bad()) return retval; \
+} x = (type) __gu_val; })
+
+#define __get_user_asm(x,size,addr,ret) \
+__asm__ __volatile__( \
+ "/* Get user asm, inline. */\n" \
+"1:\t" "ld"#size " %2, %1\n\t" \
+ "clr %0\n" \
+"2:\n\n\t" \
+ ".section .fixup,#alloc,#execinstr\n\t" \
+ ".align 4\n" \
+"3:\n\t" \
+ "clr %1\n\t" \
+ "b 2b\n\t" \
+ " mov %3, %0\n\n\t" \
+ ".previous\n\t" \
+ ".section __ex_table,#alloc\n\t" \
+ ".align 4\n\t" \
+ ".word 1b, 3b\n\n\t" \
+ ".previous\n\t" \
+ : "=&r" (ret), "=&r" (x) : "m" (*__m(addr)), \
+ "i" (-EFAULT))
+
+#define __get_user_asm_ret(x,size,addr,retval) \
+if (__builtin_constant_p(retval) && retval == -EFAULT) \
+__asm__ __volatile__( \
+ "/* Get user asm ret, inline. */\n" \
+"1:\t" "ld"#size " %1, %0\n\n\t" \
+ ".section __ex_table,#alloc\n\t" \
+ ".align 4\n\t" \
+ ".word 1b,__ret_efault\n\n\t" \
+ ".previous\n\t" \
+ : "=&r" (x) : "m" (*__m(addr))); \
+else \
+__asm__ __volatile__( \
+ "/* Get user asm ret, inline. */\n" \
+"1:\t" "ld"#size " %1, %0\n\n\t" \
+ ".section .fixup,#alloc,#execinstr\n\t" \
+ ".align 4\n" \
+"3:\n\t" \
+ "ret\n\t" \
+ " restore %%g0, %2, %%o0\n\n\t" \
+ ".previous\n\t" \
+ ".section __ex_table,#alloc\n\t" \
+ ".align 4\n\t" \
+ ".word 1b, 3b\n\n\t" \
+ ".previous\n\t" \
+ : "=&r" (x) : "m" (*__m(addr)), "i" (retval))
+
+extern int __get_user_bad(void);
+
+extern unsigned long __copy_user(void __user *to, const void __user *from, unsigned long size);
+
+static inline unsigned long copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+ if (n && __access_ok((unsigned long) to, n))
+ return __copy_user(to, (__force void __user *) from, n);
+ else
+ return n;
+}
+
+static inline unsigned long __copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+ return __copy_user(to, (__force void __user *) from, n);
+}
+
+static inline unsigned long copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+ if (n && __access_ok((unsigned long) from, n))
+ return __copy_user((__force void __user *) to, from, n);
+ else
+ return n;
+}
+
+static inline unsigned long __copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+ return __copy_user((__force void __user *) to, from, n);
+}
+
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+static inline unsigned long __clear_user(void __user *addr, unsigned long size)
+{
+ unsigned long ret;
+
+ __asm__ __volatile__ (
+ ".section __ex_table,#alloc\n\t"
+ ".align 4\n\t"
+ ".word 1f,3\n\t"
+ ".previous\n\t"
+ "mov %2, %%o1\n"
+ "1:\n\t"
+ "call __bzero\n\t"
+ " mov %1, %%o0\n\t"
+ "mov %%o0, %0\n"
+ : "=r" (ret) : "r" (addr), "r" (size) :
+ "o0", "o1", "o2", "o3", "o4", "o5", "o7",
+ "g1", "g2", "g3", "g4", "g5", "g7", "cc");
+
+ return ret;
+}
+
+static inline unsigned long clear_user(void __user *addr, unsigned long n)
+{
+ if (n && __access_ok((unsigned long) addr, n))
+ return __clear_user(addr, n);
+ else
+ return n;
+}
+
+extern long __strncpy_from_user(char *dest, const char __user *src, long count);
+
+static inline long strncpy_from_user(char *dest, const char __user *src, long count)
+{
+ if (__access_ok((unsigned long) src, count))
+ return __strncpy_from_user(dest, src, count);
+ else
+ return -EFAULT;
+}
+
+extern long __strlen_user(const char __user *);
+extern long __strnlen_user(const char __user *, long len);
+
+static inline long strlen_user(const char __user *str)
+{
+ if (!access_ok(VERIFY_READ, str, 0))
+ return 0;
+ else
+ return __strlen_user(str);
+}
+
+static inline long strnlen_user(const char __user *str, long len)
+{
+ if (!access_ok(VERIFY_READ, str, 0))
+ return 0;
+ else
+ return __strnlen_user(str, len);
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_UACCESS_H */
--- /dev/null
+#ifndef _ASM_UACCESS_H
+#define _ASM_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+
+#ifdef __KERNEL__
+#include <linux/compiler.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <asm/asi.h>
+#include <asm/system.h>
+#include <asm/spitfire.h>
+#include <asm-generic/uaccess.h>
+#endif
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Sparc64 is segmented, though more like the M68K than the I386.
+ * We use the secondary ASI to address user memory, which references a
+ * completely different VM map, thus there is zero chance of the user
+ * doing something queer and tricking us into poking kernel memory.
+ *
+ * What is left here is basically what is needed for the other parts of
+ * the kernel that expect to be able to manipulate, erum, "segments".
+ * Or perhaps more properly, permissions.
+ *
+ * "For historical reasons, these macros are grossly misnamed." -Linus
+ */
+
+#define KERNEL_DS ((mm_segment_t) { ASI_P })
+#define USER_DS ((mm_segment_t) { ASI_AIUS }) /* har har har */
+
+#define VERIFY_READ 0
+#define VERIFY_WRITE 1
+
+#define get_fs() ((mm_segment_t) { get_thread_current_ds() })
+#define get_ds() (KERNEL_DS)
+
+#define segment_eq(a,b) ((a).seg == (b).seg)
+
+#define set_fs(val) \
+do { \
+ set_thread_current_ds((val).seg); \
+ __asm__ __volatile__ ("wr %%g0, %0, %%asi" : : "r" ((val).seg)); \
+} while(0)
+
+static inline int __access_ok(const void __user * addr, unsigned long size)
+{
+ return 1;
+}
+
+static inline int access_ok(int type, const void __user * addr, unsigned long size)
+{
+ return 1;
+}
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue. No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path. This means when everything is well,
+ * we don't even have to jump over them. Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry {
+ unsigned int insn, fixup;
+};
+
+extern void __ret_efault(void);
+extern void __retl_efault(void);
+
+/* Uh, these should become the main single-value transfer routines..
+ * They automatically use the right size if we just have the right
+ * pointer type..
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ */
+#define put_user(x,ptr) ({ \
+unsigned long __pu_addr = (unsigned long)(ptr); \
+__chk_user_ptr(ptr); \
+__put_user_nocheck((__typeof__(*(ptr)))(x),__pu_addr,sizeof(*(ptr))); })
+
+#define get_user(x,ptr) ({ \
+unsigned long __gu_addr = (unsigned long)(ptr); \
+__chk_user_ptr(ptr); \
+__get_user_nocheck((x),__gu_addr,sizeof(*(ptr)),__typeof__(*(ptr))); })
+
+#define __put_user(x,ptr) put_user(x,ptr)
+#define __get_user(x,ptr) get_user(x,ptr)
+
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) ((struct __large_struct *)(x))
+
+#define __put_user_nocheck(data,addr,size) ({ \
+register int __pu_ret; \
+switch (size) { \
+case 1: __put_user_asm(data,b,addr,__pu_ret); break; \
+case 2: __put_user_asm(data,h,addr,__pu_ret); break; \
+case 4: __put_user_asm(data,w,addr,__pu_ret); break; \
+case 8: __put_user_asm(data,x,addr,__pu_ret); break; \
+default: __pu_ret = __put_user_bad(); break; \
+} __pu_ret; })
+
+#define __put_user_asm(x,size,addr,ret) \
+__asm__ __volatile__( \
+ "/* Put user asm, inline. */\n" \
+"1:\t" "st"#size "a %1, [%2] %%asi\n\t" \
+ "clr %0\n" \
+"2:\n\n\t" \
+ ".section .fixup,#alloc,#execinstr\n\t" \
+ ".align 4\n" \
+"3:\n\t" \
+ "sethi %%hi(2b), %0\n\t" \
+ "jmpl %0 + %%lo(2b), %%g0\n\t" \
+ " mov %3, %0\n\n\t" \
+ ".previous\n\t" \
+ ".section __ex_table,\"a\"\n\t" \
+ ".align 4\n\t" \
+ ".word 1b, 3b\n\t" \
+ ".previous\n\n\t" \
+ : "=r" (ret) : "r" (x), "r" (__m(addr)), \
+ "i" (-EFAULT))
+
+extern int __put_user_bad(void);
+
+#define __get_user_nocheck(data,addr,size,type) ({ \
+register int __gu_ret; \
+register unsigned long __gu_val; \
+switch (size) { \
+case 1: __get_user_asm(__gu_val,ub,addr,__gu_ret); break; \
+case 2: __get_user_asm(__gu_val,uh,addr,__gu_ret); break; \
+case 4: __get_user_asm(__gu_val,uw,addr,__gu_ret); break; \
+case 8: __get_user_asm(__gu_val,x,addr,__gu_ret); break; \
+default: __gu_val = 0; __gu_ret = __get_user_bad(); break; \
+} data = (type) __gu_val; __gu_ret; })
+
+#define __get_user_nocheck_ret(data,addr,size,type,retval) ({ \
+register unsigned long __gu_val __asm__ ("l1"); \
+switch (size) { \
+case 1: __get_user_asm_ret(__gu_val,ub,addr,retval); break; \
+case 2: __get_user_asm_ret(__gu_val,uh,addr,retval); break; \
+case 4: __get_user_asm_ret(__gu_val,uw,addr,retval); break; \
+case 8: __get_user_asm_ret(__gu_val,x,addr,retval); break; \
+default: if (__get_user_bad()) return retval; \
+} data = (type) __gu_val; })
+
+#define __get_user_asm(x,size,addr,ret) \
+__asm__ __volatile__( \
+ "/* Get user asm, inline. */\n" \
+"1:\t" "ld"#size "a [%2] %%asi, %1\n\t" \
+ "clr %0\n" \
+"2:\n\n\t" \
+ ".section .fixup,#alloc,#execinstr\n\t" \
+ ".align 4\n" \
+"3:\n\t" \
+ "sethi %%hi(2b), %0\n\t" \
+ "clr %1\n\t" \
+ "jmpl %0 + %%lo(2b), %%g0\n\t" \
+ " mov %3, %0\n\n\t" \
+ ".previous\n\t" \
+ ".section __ex_table,\"a\"\n\t" \
+ ".align 4\n\t" \
+ ".word 1b, 3b\n\n\t" \
+ ".previous\n\t" \
+ : "=r" (ret), "=r" (x) : "r" (__m(addr)), \
+ "i" (-EFAULT))
+
+#define __get_user_asm_ret(x,size,addr,retval) \
+if (__builtin_constant_p(retval) && retval == -EFAULT) \
+__asm__ __volatile__( \
+ "/* Get user asm ret, inline. */\n" \
+"1:\t" "ld"#size "a [%1] %%asi, %0\n\n\t" \
+ ".section __ex_table,\"a\"\n\t" \
+ ".align 4\n\t" \
+ ".word 1b,__ret_efault\n\n\t" \
+ ".previous\n\t" \
+ : "=r" (x) : "r" (__m(addr))); \
+else \
+__asm__ __volatile__( \
+ "/* Get user asm ret, inline. */\n" \
+"1:\t" "ld"#size "a [%1] %%asi, %0\n\n\t" \
+ ".section .fixup,#alloc,#execinstr\n\t" \
+ ".align 4\n" \
+"3:\n\t" \
+ "ret\n\t" \
+ " restore %%g0, %2, %%o0\n\n\t" \
+ ".previous\n\t" \
+ ".section __ex_table,\"a\"\n\t" \
+ ".align 4\n\t" \
+ ".word 1b, 3b\n\n\t" \
+ ".previous\n\t" \
+ : "=r" (x) : "r" (__m(addr)), "i" (retval))
+
+extern int __get_user_bad(void);
+
+extern unsigned long __must_check ___copy_from_user(void *to,
+ const void __user *from,
+ unsigned long size);
+extern unsigned long copy_from_user_fixup(void *to, const void __user *from,
+ unsigned long size);
+static inline unsigned long __must_check
+copy_from_user(void *to, const void __user *from, unsigned long size)
+{
+ unsigned long ret = ___copy_from_user(to, from, size);
+
+ if (unlikely(ret))
+ ret = copy_from_user_fixup(to, from, size);
+ return ret;
+}
+#define __copy_from_user copy_from_user
+
+extern unsigned long __must_check ___copy_to_user(void __user *to,
+ const void *from,
+ unsigned long size);
+extern unsigned long copy_to_user_fixup(void __user *to, const void *from,
+ unsigned long size);
+static inline unsigned long __must_check
+copy_to_user(void __user *to, const void *from, unsigned long size)
+{
+ unsigned long ret = ___copy_to_user(to, from, size);
+
+ if (unlikely(ret))
+ ret = copy_to_user_fixup(to, from, size);
+ return ret;
+}
+#define __copy_to_user copy_to_user
+
+extern unsigned long __must_check ___copy_in_user(void __user *to,
+ const void __user *from,
+ unsigned long size);
+extern unsigned long copy_in_user_fixup(void __user *to, void __user *from,
+ unsigned long size);
+static inline unsigned long __must_check
+copy_in_user(void __user *to, void __user *from, unsigned long size)
+{
+ unsigned long ret = ___copy_in_user(to, from, size);
+
+ if (unlikely(ret))
+ ret = copy_in_user_fixup(to, from, size);
+ return ret;
+}
+#define __copy_in_user copy_in_user
+
+extern unsigned long __must_check __clear_user(void __user *, unsigned long);
+
+#define clear_user __clear_user
+
+extern long __must_check __strncpy_from_user(char *dest, const char __user *src, long count);
+
+#define strncpy_from_user __strncpy_from_user
+
+extern long __strlen_user(const char __user *);
+extern long __strnlen_user(const char __user *, long len);
+
+#define strlen_user __strlen_user
+#define strnlen_user __strnlen_user
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_UACCESS_H */
--- /dev/null
+/*
+ * uctx.h: Sparc64 {set,get}context() register state layouts.
+ *
+ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __SPARC64_UCTX_H
+#define __SPARC64_UCTX_H
+
+#define MC_TSTATE 0
+#define MC_PC 1
+#define MC_NPC 2
+#define MC_Y 3
+#define MC_G1 4
+#define MC_G2 5
+#define MC_G3 6
+#define MC_G4 7
+#define MC_G5 8
+#define MC_G6 9
+#define MC_G7 10
+#define MC_O0 11
+#define MC_O1 12
+#define MC_O2 13
+#define MC_O3 14
+#define MC_O4 15
+#define MC_O5 16
+#define MC_O6 17
+#define MC_O7 18
+#define MC_NGREG 19
+
+typedef unsigned long mc_greg_t;
+typedef mc_greg_t mc_gregset_t[MC_NGREG];
+
+#define MC_MAXFPQ 16
+struct mc_fq {
+ unsigned long *mcfq_addr;
+ unsigned int mcfq_insn;
+};
+
+struct mc_fpu {
+ union {
+ unsigned int sregs[32];
+ unsigned long dregs[32];
+ long double qregs[16];
+ } mcfpu_fregs;
+ unsigned long mcfpu_fsr;
+ unsigned long mcfpu_fprs;
+ unsigned long mcfpu_gsr;
+ struct mc_fq *mcfpu_fq;
+ unsigned char mcfpu_qcnt;
+ unsigned char mcfpu_qentsz;
+ unsigned char mcfpu_enab;
+};
+typedef struct mc_fpu mc_fpu_t;
+
+typedef struct {
+ mc_gregset_t mc_gregs;
+ mc_greg_t mc_fp;
+ mc_greg_t mc_i7;
+ mc_fpu_t mc_fpregs;
+} mcontext_t;
+
+struct ucontext {
+ struct ucontext *uc_link;
+ unsigned long uc_flags;
+ sigset_t uc_sigmask;
+ mcontext_t uc_mcontext;
+};
+typedef struct ucontext ucontext_t;
+
+#endif /* __SPARC64_UCTX_H */
--- /dev/null
+#ifndef _ASM_SPARC_UNALIGNED_H
+#define _ASM_SPARC_UNALIGNED_H
+
+#include <linux/unaligned/be_struct.h>
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/generic.h>
+#define get_unaligned __get_unaligned_be
+#define put_unaligned __put_unaligned_be
+
+#endif /* _ASM_SPARC_UNALIGNED_H */
--- /dev/null
+#ifndef ___ASM_SPARC_UNISTD_H
+#define ___ASM_SPARC_UNISTD_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/unistd_64.h>
+#else
+#include <asm/unistd_32.h>
+#endif
+#endif
--- /dev/null
+#ifndef _SPARC_UNISTD_H
+#define _SPARC_UNISTD_H
+
+/*
+ * System calls under the Sparc.
+ *
+ * Don't be scared by the ugly clobbers, it is the only way I can
+ * think of right now to force the arguments into fixed registers
+ * before the trap into the system call with gcc 'asm' statements.
+ *
+ * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
+ *
+ * SunOS compatibility based upon preliminary work which is:
+ *
+ * Copyright (C) 1995 Adrian M. Rodriguez (adrian@remus.rutgers.edu)
+ */
+
+#define __NR_restart_syscall 0 /* Linux Specific */
+#define __NR_exit 1 /* Common */
+#define __NR_fork 2 /* Common */
+#define __NR_read 3 /* Common */
+#define __NR_write 4 /* Common */
+#define __NR_open 5 /* Common */
+#define __NR_close 6 /* Common */
+#define __NR_wait4 7 /* Common */
+#define __NR_creat 8 /* Common */
+#define __NR_link 9 /* Common */
+#define __NR_unlink 10 /* Common */
+#define __NR_execv 11 /* SunOS Specific */
+#define __NR_chdir 12 /* Common */
+#define __NR_chown 13 /* Common */
+#define __NR_mknod 14 /* Common */
+#define __NR_chmod 15 /* Common */
+#define __NR_lchown 16 /* Common */
+#define __NR_brk 17 /* Common */
+#define __NR_perfctr 18 /* Performance counter operations */
+#define __NR_lseek 19 /* Common */
+#define __NR_getpid 20 /* Common */
+#define __NR_capget 21 /* Linux Specific */
+#define __NR_capset 22 /* Linux Specific */
+#define __NR_setuid 23 /* Implemented via setreuid in SunOS */
+#define __NR_getuid 24 /* Common */
+#define __NR_vmsplice 25 /* ENOSYS under SunOS */
+#define __NR_ptrace 26 /* Common */
+#define __NR_alarm 27 /* Implemented via setitimer in SunOS */
+#define __NR_sigaltstack 28 /* Common */
+#define __NR_pause 29 /* Is sigblock(0)->sigpause() in SunOS */
+#define __NR_utime 30 /* Implemented via utimes() under SunOS */
+#define __NR_lchown32 31 /* Linux sparc32 specific */
+#define __NR_fchown32 32 /* Linux sparc32 specific */
+#define __NR_access 33 /* Common */
+#define __NR_nice 34 /* Implemented via get/setpriority() in SunOS */
+#define __NR_chown32 35 /* Linux sparc32 specific */
+#define __NR_sync 36 /* Common */
+#define __NR_kill 37 /* Common */
+#define __NR_stat 38 /* Common */
+#define __NR_sendfile 39 /* Linux Specific */
+#define __NR_lstat 40 /* Common */
+#define __NR_dup 41 /* Common */
+#define __NR_pipe 42 /* Common */
+#define __NR_times 43 /* Implemented via getrusage() in SunOS */
+#define __NR_getuid32 44 /* Linux sparc32 specific */
+#define __NR_umount2 45 /* Linux Specific */
+#define __NR_setgid 46 /* Implemented via setregid() in SunOS */
+#define __NR_getgid 47 /* Common */
+#define __NR_signal 48 /* Implemented via sigvec() in SunOS */
+#define __NR_geteuid 49 /* SunOS calls getuid() */
+#define __NR_getegid 50 /* SunOS calls getgid() */
+#define __NR_acct 51 /* Common */
+/* #define __NR_memory_ordering 52 Linux sparc64 specific */
+#define __NR_getgid32 53 /* Linux sparc32 specific */
+#define __NR_ioctl 54 /* Common */
+#define __NR_reboot 55 /* Common */
+#define __NR_mmap2 56 /* Linux sparc32 Specific */
+#define __NR_symlink 57 /* Common */
+#define __NR_readlink 58 /* Common */
+#define __NR_execve 59 /* Common */
+#define __NR_umask 60 /* Common */
+#define __NR_chroot 61 /* Common */
+#define __NR_fstat 62 /* Common */
+#define __NR_fstat64 63 /* Linux Specific */
+#define __NR_getpagesize 64 /* Common */
+#define __NR_msync 65 /* Common in newer 1.3.x revs... */
+#define __NR_vfork 66 /* Common */
+#define __NR_pread64 67 /* Linux Specific */
+#define __NR_pwrite64 68 /* Linux Specific */
+#define __NR_geteuid32 69 /* Linux sparc32, sbrk under SunOS */
+#define __NR_getegid32 70 /* Linux sparc32, sstk under SunOS */
+#define __NR_mmap 71 /* Common */
+#define __NR_setreuid32 72 /* Linux sparc32, vadvise under SunOS */
+#define __NR_munmap 73 /* Common */
+#define __NR_mprotect 74 /* Common */
+#define __NR_madvise 75 /* Common */
+#define __NR_vhangup 76 /* Common */
+#define __NR_truncate64 77 /* Linux sparc32 Specific */
+#define __NR_mincore 78 /* Common */
+#define __NR_getgroups 79 /* Common */
+#define __NR_setgroups 80 /* Common */
+#define __NR_getpgrp 81 /* Common */
+#define __NR_setgroups32 82 /* Linux sparc32, setpgrp under SunOS */
+#define __NR_setitimer 83 /* Common */
+#define __NR_ftruncate64 84 /* Linux sparc32 Specific */
+#define __NR_swapon 85 /* Common */
+#define __NR_getitimer 86 /* Common */
+#define __NR_setuid32 87 /* Linux sparc32, gethostname under SunOS */
+#define __NR_sethostname 88 /* Common */
+#define __NR_setgid32 89 /* Linux sparc32, getdtablesize under SunOS */
+#define __NR_dup2 90 /* Common */
+#define __NR_setfsuid32 91 /* Linux sparc32, getdopt under SunOS */
+#define __NR_fcntl 92 /* Common */
+#define __NR_select 93 /* Common */
+#define __NR_setfsgid32 94 /* Linux sparc32, setdopt under SunOS */
+#define __NR_fsync 95 /* Common */
+#define __NR_setpriority 96 /* Common */
+#define __NR_socket 97 /* Common */
+#define __NR_connect 98 /* Common */
+#define __NR_accept 99 /* Common */
+#define __NR_getpriority 100 /* Common */
+#define __NR_rt_sigreturn 101 /* Linux Specific */
+#define __NR_rt_sigaction 102 /* Linux Specific */
+#define __NR_rt_sigprocmask 103 /* Linux Specific */
+#define __NR_rt_sigpending 104 /* Linux Specific */
+#define __NR_rt_sigtimedwait 105 /* Linux Specific */
+#define __NR_rt_sigqueueinfo 106 /* Linux Specific */
+#define __NR_rt_sigsuspend 107 /* Linux Specific */
+#define __NR_setresuid32 108 /* Linux Specific, sigvec under SunOS */
+#define __NR_getresuid32 109 /* Linux Specific, sigblock under SunOS */
+#define __NR_setresgid32 110 /* Linux Specific, sigsetmask under SunOS */
+#define __NR_getresgid32 111 /* Linux Specific, sigpause under SunOS */
+#define __NR_setregid32 112 /* Linux sparc32, sigstack under SunOS */
+#define __NR_recvmsg 113 /* Common */
+#define __NR_sendmsg 114 /* Common */
+#define __NR_getgroups32 115 /* Linux sparc32, vtrace under SunOS */
+#define __NR_gettimeofday 116 /* Common */
+#define __NR_getrusage 117 /* Common */
+#define __NR_getsockopt 118 /* Common */
+#define __NR_getcwd 119 /* Linux Specific */
+#define __NR_readv 120 /* Common */
+#define __NR_writev 121 /* Common */
+#define __NR_settimeofday 122 /* Common */
+#define __NR_fchown 123 /* Common */
+#define __NR_fchmod 124 /* Common */
+#define __NR_recvfrom 125 /* Common */
+#define __NR_setreuid 126 /* Common */
+#define __NR_setregid 127 /* Common */
+#define __NR_rename 128 /* Common */
+#define __NR_truncate 129 /* Common */
+#define __NR_ftruncate 130 /* Common */
+#define __NR_flock 131 /* Common */
+#define __NR_lstat64 132 /* Linux Specific */
+#define __NR_sendto 133 /* Common */
+#define __NR_shutdown 134 /* Common */
+#define __NR_socketpair 135 /* Common */
+#define __NR_mkdir 136 /* Common */
+#define __NR_rmdir 137 /* Common */
+#define __NR_utimes 138 /* SunOS Specific */
+#define __NR_stat64 139 /* Linux Specific */
+#define __NR_sendfile64 140 /* adjtime under SunOS */
+#define __NR_getpeername 141 /* Common */
+#define __NR_futex 142 /* gethostid under SunOS */
+#define __NR_gettid 143 /* ENOSYS under SunOS */
+#define __NR_getrlimit 144 /* Common */
+#define __NR_setrlimit 145 /* Common */
+#define __NR_pivot_root 146 /* Linux Specific, killpg under SunOS */
+#define __NR_prctl 147 /* ENOSYS under SunOS */
+#define __NR_pciconfig_read 148 /* ENOSYS under SunOS */
+#define __NR_pciconfig_write 149 /* ENOSYS under SunOS */
+#define __NR_getsockname 150 /* Common */
+#define __NR_inotify_init 151 /* Linux specific */
+#define __NR_inotify_add_watch 152 /* Linux specific */
+#define __NR_poll 153 /* Common */
+#define __NR_getdents64 154 /* Linux specific */
+#define __NR_fcntl64 155 /* Linux sparc32 Specific */
+#define __NR_inotify_rm_watch 156 /* Linux specific */
+#define __NR_statfs 157 /* Common */
+#define __NR_fstatfs 158 /* Common */
+#define __NR_umount 159 /* Common */
+#define __NR_sched_set_affinity 160 /* Linux specific, async_daemon under SunOS */
+#define __NR_sched_get_affinity 161 /* Linux specific, getfh under SunOS */
+#define __NR_getdomainname 162 /* SunOS Specific */
+#define __NR_setdomainname 163 /* Common */
+/* #define __NR_utrap_install 164 Linux sparc64 specific */
+#define __NR_quotactl 165 /* Common */
+#define __NR_set_tid_address 166 /* Linux specific, exportfs under SunOS */
+#define __NR_mount 167 /* Common */
+#define __NR_ustat 168 /* Common */
+#define __NR_setxattr 169 /* SunOS: semsys */
+#define __NR_lsetxattr 170 /* SunOS: msgsys */
+#define __NR_fsetxattr 171 /* SunOS: shmsys */
+#define __NR_getxattr 172 /* SunOS: auditsys */
+#define __NR_lgetxattr 173 /* SunOS: rfssys */
+#define __NR_getdents 174 /* Common */
+#define __NR_setsid 175 /* Common */
+#define __NR_fchdir 176 /* Common */
+#define __NR_fgetxattr 177 /* SunOS: fchroot */
+#define __NR_listxattr 178 /* SunOS: vpixsys */
+#define __NR_llistxattr 179 /* SunOS: aioread */
+#define __NR_flistxattr 180 /* SunOS: aiowrite */
+#define __NR_removexattr 181 /* SunOS: aiowait */
+#define __NR_lremovexattr 182 /* SunOS: aiocancel */
+#define __NR_sigpending 183 /* Common */
+#define __NR_query_module 184 /* Linux Specific */
+#define __NR_setpgid 185 /* Common */
+#define __NR_fremovexattr 186 /* SunOS: pathconf */
+#define __NR_tkill 187 /* SunOS: fpathconf */
+#define __NR_exit_group 188 /* Linux specific, sysconf undef SunOS */
+#define __NR_uname 189 /* Linux Specific */
+#define __NR_init_module 190 /* Linux Specific */
+#define __NR_personality 191 /* Linux Specific */
+#define __NR_remap_file_pages 192 /* Linux Specific */
+#define __NR_epoll_create 193 /* Linux Specific */
+#define __NR_epoll_ctl 194 /* Linux Specific */
+#define __NR_epoll_wait 195 /* Linux Specific */
+#define __NR_ioprio_set 196 /* Linux Specific */
+#define __NR_getppid 197 /* Linux Specific */
+#define __NR_sigaction 198 /* Linux Specific */
+#define __NR_sgetmask 199 /* Linux Specific */
+#define __NR_ssetmask 200 /* Linux Specific */
+#define __NR_sigsuspend 201 /* Linux Specific */
+#define __NR_oldlstat 202 /* Linux Specific */
+#define __NR_uselib 203 /* Linux Specific */
+#define __NR_readdir 204 /* Linux Specific */
+#define __NR_readahead 205 /* Linux Specific */
+#define __NR_socketcall 206 /* Linux Specific */
+#define __NR_syslog 207 /* Linux Specific */
+#define __NR_lookup_dcookie 208 /* Linux Specific */
+#define __NR_fadvise64 209 /* Linux Specific */
+#define __NR_fadvise64_64 210 /* Linux Specific */
+#define __NR_tgkill 211 /* Linux Specific */
+#define __NR_waitpid 212 /* Linux Specific */
+#define __NR_swapoff 213 /* Linux Specific */
+#define __NR_sysinfo 214 /* Linux Specific */
+#define __NR_ipc 215 /* Linux Specific */
+#define __NR_sigreturn 216 /* Linux Specific */
+#define __NR_clone 217 /* Linux Specific */
+#define __NR_ioprio_get 218 /* Linux Specific */
+#define __NR_adjtimex 219 /* Linux Specific */
+#define __NR_sigprocmask 220 /* Linux Specific */
+#define __NR_create_module 221 /* Linux Specific */
+#define __NR_delete_module 222 /* Linux Specific */
+#define __NR_get_kernel_syms 223 /* Linux Specific */
+#define __NR_getpgid 224 /* Linux Specific */
+#define __NR_bdflush 225 /* Linux Specific */
+#define __NR_sysfs 226 /* Linux Specific */
+#define __NR_afs_syscall 227 /* Linux Specific */
+#define __NR_setfsuid 228 /* Linux Specific */
+#define __NR_setfsgid 229 /* Linux Specific */
+#define __NR__newselect 230 /* Linux Specific */
+#define __NR_time 231 /* Linux Specific */
+#define __NR_splice 232 /* Linux Specific */
+#define __NR_stime 233 /* Linux Specific */
+#define __NR_statfs64 234 /* Linux Specific */
+#define __NR_fstatfs64 235 /* Linux Specific */
+#define __NR__llseek 236 /* Linux Specific */
+#define __NR_mlock 237
+#define __NR_munlock 238
+#define __NR_mlockall 239
+#define __NR_munlockall 240
+#define __NR_sched_setparam 241
+#define __NR_sched_getparam 242
+#define __NR_sched_setscheduler 243
+#define __NR_sched_getscheduler 244
+#define __NR_sched_yield 245
+#define __NR_sched_get_priority_max 246
+#define __NR_sched_get_priority_min 247
+#define __NR_sched_rr_get_interval 248
+#define __NR_nanosleep 249
+#define __NR_mremap 250
+#define __NR__sysctl 251
+#define __NR_getsid 252
+#define __NR_fdatasync 253
+#define __NR_nfsservctl 254
+#define __NR_sync_file_range 255
+#define __NR_clock_settime 256
+#define __NR_clock_gettime 257
+#define __NR_clock_getres 258
+#define __NR_clock_nanosleep 259
+#define __NR_sched_getaffinity 260
+#define __NR_sched_setaffinity 261
+#define __NR_timer_settime 262
+#define __NR_timer_gettime 263
+#define __NR_timer_getoverrun 264
+#define __NR_timer_delete 265
+#define __NR_timer_create 266
+/* #define __NR_vserver 267 Reserved for VSERVER */
+#define __NR_io_setup 268
+#define __NR_io_destroy 269
+#define __NR_io_submit 270
+#define __NR_io_cancel 271
+#define __NR_io_getevents 272
+#define __NR_mq_open 273
+#define __NR_mq_unlink 274
+#define __NR_mq_timedsend 275
+#define __NR_mq_timedreceive 276
+#define __NR_mq_notify 277
+#define __NR_mq_getsetattr 278
+#define __NR_waitid 279
+#define __NR_tee 280
+#define __NR_add_key 281
+#define __NR_request_key 282
+#define __NR_keyctl 283
+#define __NR_openat 284
+#define __NR_mkdirat 285
+#define __NR_mknodat 286
+#define __NR_fchownat 287
+#define __NR_futimesat 288
+#define __NR_fstatat64 289
+#define __NR_unlinkat 290
+#define __NR_renameat 291
+#define __NR_linkat 292
+#define __NR_symlinkat 293
+#define __NR_readlinkat 294
+#define __NR_fchmodat 295
+#define __NR_faccessat 296
+#define __NR_pselect6 297
+#define __NR_ppoll 298
+#define __NR_unshare 299
+#define __NR_set_robust_list 300
+#define __NR_get_robust_list 301
+#define __NR_migrate_pages 302
+#define __NR_mbind 303
+#define __NR_get_mempolicy 304
+#define __NR_set_mempolicy 305
+#define __NR_kexec_load 306
+#define __NR_move_pages 307
+#define __NR_getcpu 308
+#define __NR_epoll_pwait 309
+#define __NR_utimensat 310
+#define __NR_signalfd 311
+#define __NR_timerfd_create 312
+#define __NR_eventfd 313
+#define __NR_fallocate 314
+#define __NR_timerfd_settime 315
+#define __NR_timerfd_gettime 316
+#define __NR_signalfd4 317
+#define __NR_eventfd2 318
+#define __NR_epoll_create1 319
+#define __NR_dup3 320
+#define __NR_pipe2 321
+#define __NR_inotify_init1 322
+
+#define NR_SYSCALLS 323
+
+/* Sparc 32-bit only has the "setresuid32", "getresuid32" variants,
+ * it never had the plain ones and there is no value to adding those
+ * old versions into the syscall table.
+ */
+#define __IGNORE_setresuid
+#define __IGNORE_getresuid
+#define __IGNORE_setresgid
+#define __IGNORE_getresgid
+
+#ifdef __KERNEL__
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+
+#endif /* __KERNEL__ */
+#endif /* _SPARC_UNISTD_H */
--- /dev/null
+#ifndef _SPARC64_UNISTD_H
+#define _SPARC64_UNISTD_H
+
+/*
+ * System calls under the Sparc.
+ *
+ * Don't be scared by the ugly clobbers, it is the only way I can
+ * think of right now to force the arguments into fixed registers
+ * before the trap into the system call with gcc 'asm' statements.
+ *
+ * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
+ *
+ * SunOS compatibility based upon preliminary work which is:
+ *
+ * Copyright (C) 1995 Adrian M. Rodriguez (adrian@remus.rutgers.edu)
+ */
+
+#define __NR_restart_syscall 0 /* Linux Specific */
+#define __NR_exit 1 /* Common */
+#define __NR_fork 2 /* Common */
+#define __NR_read 3 /* Common */
+#define __NR_write 4 /* Common */
+#define __NR_open 5 /* Common */
+#define __NR_close 6 /* Common */
+#define __NR_wait4 7 /* Common */
+#define __NR_creat 8 /* Common */
+#define __NR_link 9 /* Common */
+#define __NR_unlink 10 /* Common */
+#define __NR_execv 11 /* SunOS Specific */
+#define __NR_chdir 12 /* Common */
+#define __NR_chown 13 /* Common */
+#define __NR_mknod 14 /* Common */
+#define __NR_chmod 15 /* Common */
+#define __NR_lchown 16 /* Common */
+#define __NR_brk 17 /* Common */
+#define __NR_perfctr 18 /* Performance counter operations */
+#define __NR_lseek 19 /* Common */
+#define __NR_getpid 20 /* Common */
+#define __NR_capget 21 /* Linux Specific */
+#define __NR_capset 22 /* Linux Specific */
+#define __NR_setuid 23 /* Implemented via setreuid in SunOS */
+#define __NR_getuid 24 /* Common */
+#define __NR_vmsplice 25 /* ENOSYS under SunOS */
+#define __NR_ptrace 26 /* Common */
+#define __NR_alarm 27 /* Implemented via setitimer in SunOS */
+#define __NR_sigaltstack 28 /* Common */
+#define __NR_pause 29 /* Is sigblock(0)->sigpause() in SunOS */
+#define __NR_utime 30 /* Implemented via utimes() under SunOS */
+/* #define __NR_lchown32 31 Linux sparc32 specific */
+/* #define __NR_fchown32 32 Linux sparc32 specific */
+#define __NR_access 33 /* Common */
+#define __NR_nice 34 /* Implemented via get/setpriority() in SunOS */
+/* #define __NR_chown32 35 Linux sparc32 specific */
+#define __NR_sync 36 /* Common */
+#define __NR_kill 37 /* Common */
+#define __NR_stat 38 /* Common */
+#define __NR_sendfile 39 /* Linux Specific */
+#define __NR_lstat 40 /* Common */
+#define __NR_dup 41 /* Common */
+#define __NR_pipe 42 /* Common */
+#define __NR_times 43 /* Implemented via getrusage() in SunOS */
+/* #define __NR_getuid32 44 Linux sparc32 specific */
+#define __NR_umount2 45 /* Linux Specific */
+#define __NR_setgid 46 /* Implemented via setregid() in SunOS */
+#define __NR_getgid 47 /* Common */
+#define __NR_signal 48 /* Implemented via sigvec() in SunOS */
+#define __NR_geteuid 49 /* SunOS calls getuid() */
+#define __NR_getegid 50 /* SunOS calls getgid() */
+#define __NR_acct 51 /* Common */
+#define __NR_memory_ordering 52 /* Linux Specific */
+/* #define __NR_getgid32 53 Linux sparc32 specific */
+#define __NR_ioctl 54 /* Common */
+#define __NR_reboot 55 /* Common */
+/* #define __NR_mmap2 56 Linux sparc32 Specific */
+#define __NR_symlink 57 /* Common */
+#define __NR_readlink 58 /* Common */
+#define __NR_execve 59 /* Common */
+#define __NR_umask 60 /* Common */
+#define __NR_chroot 61 /* Common */
+#define __NR_fstat 62 /* Common */
+#define __NR_fstat64 63 /* Linux Specific */
+#define __NR_getpagesize 64 /* Common */
+#define __NR_msync 65 /* Common in newer 1.3.x revs... */
+#define __NR_vfork 66 /* Common */
+#define __NR_pread64 67 /* Linux Specific */
+#define __NR_pwrite64 68 /* Linux Specific */
+/* #define __NR_geteuid32 69 Linux sparc32, sbrk under SunOS */
+/* #define __NR_getegid32 70 Linux sparc32, sstk under SunOS */
+#define __NR_mmap 71 /* Common */
+/* #define __NR_setreuid32 72 Linux sparc32, vadvise under SunOS */
+#define __NR_munmap 73 /* Common */
+#define __NR_mprotect 74 /* Common */
+#define __NR_madvise 75 /* Common */
+#define __NR_vhangup 76 /* Common */
+/* #define __NR_truncate64 77 Linux sparc32 Specific */
+#define __NR_mincore 78 /* Common */
+#define __NR_getgroups 79 /* Common */
+#define __NR_setgroups 80 /* Common */
+#define __NR_getpgrp 81 /* Common */
+/* #define __NR_setgroups32 82 Linux sparc32, setpgrp under SunOS */
+#define __NR_setitimer 83 /* Common */
+/* #define __NR_ftruncate64 84 Linux sparc32 Specific */
+#define __NR_swapon 85 /* Common */
+#define __NR_getitimer 86 /* Common */
+/* #define __NR_setuid32 87 Linux sparc32, gethostname under SunOS */
+#define __NR_sethostname 88 /* Common */
+/* #define __NR_setgid32 89 Linux sparc32, getdtablesize under SunOS */
+#define __NR_dup2 90 /* Common */
+/* #define __NR_setfsuid32 91 Linux sparc32, getdopt under SunOS */
+#define __NR_fcntl 92 /* Common */
+#define __NR_select 93 /* Common */
+/* #define __NR_setfsgid32 94 Linux sparc32, setdopt under SunOS */
+#define __NR_fsync 95 /* Common */
+#define __NR_setpriority 96 /* Common */
+#define __NR_socket 97 /* Common */
+#define __NR_connect 98 /* Common */
+#define __NR_accept 99 /* Common */
+#define __NR_getpriority 100 /* Common */
+#define __NR_rt_sigreturn 101 /* Linux Specific */
+#define __NR_rt_sigaction 102 /* Linux Specific */
+#define __NR_rt_sigprocmask 103 /* Linux Specific */
+#define __NR_rt_sigpending 104 /* Linux Specific */
+#define __NR_rt_sigtimedwait 105 /* Linux Specific */
+#define __NR_rt_sigqueueinfo 106 /* Linux Specific */
+#define __NR_rt_sigsuspend 107 /* Linux Specific */
+#define __NR_setresuid 108 /* Linux Specific, sigvec under SunOS */
+#define __NR_getresuid 109 /* Linux Specific, sigblock under SunOS */
+#define __NR_setresgid 110 /* Linux Specific, sigsetmask under SunOS */
+#define __NR_getresgid 111 /* Linux Specific, sigpause under SunOS */
+/* #define __NR_setregid32 75 Linux sparc32, sigstack under SunOS */
+#define __NR_recvmsg 113 /* Common */
+#define __NR_sendmsg 114 /* Common */
+/* #define __NR_getgroups32 115 Linux sparc32, vtrace under SunOS */
+#define __NR_gettimeofday 116 /* Common */
+#define __NR_getrusage 117 /* Common */
+#define __NR_getsockopt 118 /* Common */
+#define __NR_getcwd 119 /* Linux Specific */
+#define __NR_readv 120 /* Common */
+#define __NR_writev 121 /* Common */
+#define __NR_settimeofday 122 /* Common */
+#define __NR_fchown 123 /* Common */
+#define __NR_fchmod 124 /* Common */
+#define __NR_recvfrom 125 /* Common */
+#define __NR_setreuid 126 /* Common */
+#define __NR_setregid 127 /* Common */
+#define __NR_rename 128 /* Common */
+#define __NR_truncate 129 /* Common */
+#define __NR_ftruncate 130 /* Common */
+#define __NR_flock 131 /* Common */
+#define __NR_lstat64 132 /* Linux Specific */
+#define __NR_sendto 133 /* Common */
+#define __NR_shutdown 134 /* Common */
+#define __NR_socketpair 135 /* Common */
+#define __NR_mkdir 136 /* Common */
+#define __NR_rmdir 137 /* Common */
+#define __NR_utimes 138 /* SunOS Specific */
+#define __NR_stat64 139 /* Linux Specific */
+#define __NR_sendfile64 140 /* adjtime under SunOS */
+#define __NR_getpeername 141 /* Common */
+#define __NR_futex 142 /* gethostid under SunOS */
+#define __NR_gettid 143 /* ENOSYS under SunOS */
+#define __NR_getrlimit 144 /* Common */
+#define __NR_setrlimit 145 /* Common */
+#define __NR_pivot_root 146 /* Linux Specific, killpg under SunOS */
+#define __NR_prctl 147 /* ENOSYS under SunOS */
+#define __NR_pciconfig_read 148 /* ENOSYS under SunOS */
+#define __NR_pciconfig_write 149 /* ENOSYS under SunOS */
+#define __NR_getsockname 150 /* Common */
+#define __NR_inotify_init 151 /* Linux specific */
+#define __NR_inotify_add_watch 152 /* Linux specific */
+#define __NR_poll 153 /* Common */
+#define __NR_getdents64 154 /* Linux specific */
+/* #define __NR_fcntl64 155 Linux sparc32 Specific */
+#define __NR_inotify_rm_watch 156 /* Linux specific */
+#define __NR_statfs 157 /* Common */
+#define __NR_fstatfs 158 /* Common */
+#define __NR_umount 159 /* Common */
+#define __NR_sched_set_affinity 160 /* Linux specific, async_daemon under SunOS */
+#define __NR_sched_get_affinity 161 /* Linux specific, getfh under SunOS */
+#define __NR_getdomainname 162 /* SunOS Specific */
+#define __NR_setdomainname 163 /* Common */
+#define __NR_utrap_install 164 /* SYSV ABI/v9 required */
+#define __NR_quotactl 165 /* Common */
+#define __NR_set_tid_address 166 /* Linux specific, exportfs under SunOS */
+#define __NR_mount 167 /* Common */
+#define __NR_ustat 168 /* Common */
+#define __NR_setxattr 169 /* SunOS: semsys */
+#define __NR_lsetxattr 170 /* SunOS: msgsys */
+#define __NR_fsetxattr 171 /* SunOS: shmsys */
+#define __NR_getxattr 172 /* SunOS: auditsys */
+#define __NR_lgetxattr 173 /* SunOS: rfssys */
+#define __NR_getdents 174 /* Common */
+#define __NR_setsid 175 /* Common */
+#define __NR_fchdir 176 /* Common */
+#define __NR_fgetxattr 177 /* SunOS: fchroot */
+#define __NR_listxattr 178 /* SunOS: vpixsys */
+#define __NR_llistxattr 179 /* SunOS: aioread */
+#define __NR_flistxattr 180 /* SunOS: aiowrite */
+#define __NR_removexattr 181 /* SunOS: aiowait */
+#define __NR_lremovexattr 182 /* SunOS: aiocancel */
+#define __NR_sigpending 183 /* Common */
+#define __NR_query_module 184 /* Linux Specific */
+#define __NR_setpgid 185 /* Common */
+#define __NR_fremovexattr 186 /* SunOS: pathconf */
+#define __NR_tkill 187 /* SunOS: fpathconf */
+#define __NR_exit_group 188 /* Linux specific, sysconf undef SunOS */
+#define __NR_uname 189 /* Linux Specific */
+#define __NR_init_module 190 /* Linux Specific */
+#define __NR_personality 191 /* Linux Specific */
+#define __NR_remap_file_pages 192 /* Linux Specific */
+#define __NR_epoll_create 193 /* Linux Specific */
+#define __NR_epoll_ctl 194 /* Linux Specific */
+#define __NR_epoll_wait 195 /* Linux Specific */
+#define __NR_ioprio_set 196 /* Linux Specific */
+#define __NR_getppid 197 /* Linux Specific */
+#define __NR_sigaction 198 /* Linux Specific */
+#define __NR_sgetmask 199 /* Linux Specific */
+#define __NR_ssetmask 200 /* Linux Specific */
+#define __NR_sigsuspend 201 /* Linux Specific */
+#define __NR_oldlstat 202 /* Linux Specific */
+#define __NR_uselib 203 /* Linux Specific */
+#define __NR_readdir 204 /* Linux Specific */
+#define __NR_readahead 205 /* Linux Specific */
+#define __NR_socketcall 206 /* Linux Specific */
+#define __NR_syslog 207 /* Linux Specific */
+#define __NR_lookup_dcookie 208 /* Linux Specific */
+#define __NR_fadvise64 209 /* Linux Specific */
+#define __NR_fadvise64_64 210 /* Linux Specific */
+#define __NR_tgkill 211 /* Linux Specific */
+#define __NR_waitpid 212 /* Linux Specific */
+#define __NR_swapoff 213 /* Linux Specific */
+#define __NR_sysinfo 214 /* Linux Specific */
+#define __NR_ipc 215 /* Linux Specific */
+#define __NR_sigreturn 216 /* Linux Specific */
+#define __NR_clone 217 /* Linux Specific */
+#define __NR_ioprio_get 218 /* Linux Specific */
+#define __NR_adjtimex 219 /* Linux Specific */
+#define __NR_sigprocmask 220 /* Linux Specific */
+#define __NR_create_module 221 /* Linux Specific */
+#define __NR_delete_module 222 /* Linux Specific */
+#define __NR_get_kernel_syms 223 /* Linux Specific */
+#define __NR_getpgid 224 /* Linux Specific */
+#define __NR_bdflush 225 /* Linux Specific */
+#define __NR_sysfs 226 /* Linux Specific */
+#define __NR_afs_syscall 227 /* Linux Specific */
+#define __NR_setfsuid 228 /* Linux Specific */
+#define __NR_setfsgid 229 /* Linux Specific */
+#define __NR__newselect 230 /* Linux Specific */
+#ifdef __KERNEL__
+#define __NR_time 231 /* Linux sparc32 */
+#endif
+#define __NR_splice 232 /* Linux Specific */
+#define __NR_stime 233 /* Linux Specific */
+#define __NR_statfs64 234 /* Linux Specific */
+#define __NR_fstatfs64 235 /* Linux Specific */
+#define __NR__llseek 236 /* Linux Specific */
+#define __NR_mlock 237
+#define __NR_munlock 238
+#define __NR_mlockall 239
+#define __NR_munlockall 240
+#define __NR_sched_setparam 241
+#define __NR_sched_getparam 242
+#define __NR_sched_setscheduler 243
+#define __NR_sched_getscheduler 244
+#define __NR_sched_yield 245
+#define __NR_sched_get_priority_max 246
+#define __NR_sched_get_priority_min 247
+#define __NR_sched_rr_get_interval 248
+#define __NR_nanosleep 249
+#define __NR_mremap 250
+#define __NR__sysctl 251
+#define __NR_getsid 252
+#define __NR_fdatasync 253
+#define __NR_nfsservctl 254
+#define __NR_sync_file_range 255
+#define __NR_clock_settime 256
+#define __NR_clock_gettime 257
+#define __NR_clock_getres 258
+#define __NR_clock_nanosleep 259
+#define __NR_sched_getaffinity 260
+#define __NR_sched_setaffinity 261
+#define __NR_timer_settime 262
+#define __NR_timer_gettime 263
+#define __NR_timer_getoverrun 264
+#define __NR_timer_delete 265
+#define __NR_timer_create 266
+/* #define __NR_vserver 267 Reserved for VSERVER */
+#define __NR_io_setup 268
+#define __NR_io_destroy 269
+#define __NR_io_submit 270
+#define __NR_io_cancel 271
+#define __NR_io_getevents 272
+#define __NR_mq_open 273
+#define __NR_mq_unlink 274
+#define __NR_mq_timedsend 275
+#define __NR_mq_timedreceive 276
+#define __NR_mq_notify 277
+#define __NR_mq_getsetattr 278
+#define __NR_waitid 279
+#define __NR_tee 280
+#define __NR_add_key 281
+#define __NR_request_key 282
+#define __NR_keyctl 283
+#define __NR_openat 284
+#define __NR_mkdirat 285
+#define __NR_mknodat 286
+#define __NR_fchownat 287
+#define __NR_futimesat 288
+#define __NR_fstatat64 289
+#define __NR_unlinkat 290
+#define __NR_renameat 291
+#define __NR_linkat 292
+#define __NR_symlinkat 293
+#define __NR_readlinkat 294
+#define __NR_fchmodat 295
+#define __NR_faccessat 296
+#define __NR_pselect6 297
+#define __NR_ppoll 298
+#define __NR_unshare 299
+#define __NR_set_robust_list 300
+#define __NR_get_robust_list 301
+#define __NR_migrate_pages 302
+#define __NR_mbind 303
+#define __NR_get_mempolicy 304
+#define __NR_set_mempolicy 305
+#define __NR_kexec_load 306
+#define __NR_move_pages 307
+#define __NR_getcpu 308
+#define __NR_epoll_pwait 309
+#define __NR_utimensat 310
+#define __NR_signalfd 311
+#define __NR_timerfd_create 312
+#define __NR_eventfd 313
+#define __NR_fallocate 314
+#define __NR_timerfd_settime 315
+#define __NR_timerfd_gettime 316
+#define __NR_signalfd4 317
+#define __NR_eventfd2 318
+#define __NR_epoll_create1 319
+#define __NR_dup3 320
+#define __NR_pipe2 321
+#define __NR_inotify_init1 322
+
+#define NR_SYSCALLS 323
+
+#ifdef __KERNEL__
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_COMPAT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
+#define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+
+#endif /* __KERNEL__ */
+#endif /* _SPARC64_UNISTD_H */
--- /dev/null
+#ifndef _SPARC64_UPA_H
+#define _SPARC64_UPA_H
+
+#include <asm/asi.h>
+
+/* UPA level registers and defines. */
+
+/* UPA Config Register */
+#define UPA_CONFIG_RESV 0xffffffffc0000000 /* Reserved. */
+#define UPA_CONFIG_PCON 0x000000003fc00000 /* Depth of various sys queues. */
+#define UPA_CONFIG_MID 0x00000000003e0000 /* Module ID. */
+#define UPA_CONFIG_PCAP 0x000000000001ffff /* Port Capabilities. */
+
+/* UPA Port ID Register */
+#define UPA_PORTID_FNP 0xff00000000000000 /* Hardcoded to 0xfc on ultra. */
+#define UPA_PORTID_RESV 0x00fffff800000000 /* Reserved. */
+#define UPA_PORTID_ECCVALID 0x0000000400000000 /* Zero if mod can generate ECC */
+#define UPA_PORTID_ONEREAD 0x0000000200000000 /* Set if mod generates P_RASB */
+#define UPA_PORTID_PINTRDQ 0x0000000180000000 /* # outstanding P_INT_REQ's */
+#define UPA_PORTID_PREQDQ 0x000000007e000000 /* slave-wr's to mod supported */
+#define UPA_PORTID_PREQRD 0x0000000001e00000 /* # incoming P_REQ's supported */
+#define UPA_PORTID_UPACAP 0x00000000001f0000 /* UPA capabilities of mod */
+#define UPA_PORTID_ID 0x000000000000ffff /* Module Identification bits */
+
+/* UPA I/O space accessors */
+#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+static inline unsigned char _upa_readb(unsigned long addr)
+{
+ unsigned char ret;
+
+ __asm__ __volatile__("lduba\t[%1] %2, %0\t/* upa_readb */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+ return ret;
+}
+
+static inline unsigned short _upa_readw(unsigned long addr)
+{
+ unsigned short ret;
+
+ __asm__ __volatile__("lduha\t[%1] %2, %0\t/* upa_readw */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+ return ret;
+}
+
+static inline unsigned int _upa_readl(unsigned long addr)
+{
+ unsigned int ret;
+
+ __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* upa_readl */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+ return ret;
+}
+
+static inline unsigned long _upa_readq(unsigned long addr)
+{
+ unsigned long ret;
+
+ __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* upa_readq */"
+ : "=r" (ret)
+ : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+ return ret;
+}
+
+static inline void _upa_writeb(unsigned char b, unsigned long addr)
+{
+ __asm__ __volatile__("stba\t%0, [%1] %2\t/* upa_writeb */"
+ : /* no outputs */
+ : "r" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+static inline void _upa_writew(unsigned short w, unsigned long addr)
+{
+ __asm__ __volatile__("stha\t%0, [%1] %2\t/* upa_writew */"
+ : /* no outputs */
+ : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+static inline void _upa_writel(unsigned int l, unsigned long addr)
+{
+ __asm__ __volatile__("stwa\t%0, [%1] %2\t/* upa_writel */"
+ : /* no outputs */
+ : "r" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+static inline void _upa_writeq(unsigned long q, unsigned long addr)
+{
+ __asm__ __volatile__("stxa\t%0, [%1] %2\t/* upa_writeq */"
+ : /* no outputs */
+ : "r" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+#define upa_readb(__addr) (_upa_readb((unsigned long)(__addr)))
+#define upa_readw(__addr) (_upa_readw((unsigned long)(__addr)))
+#define upa_readl(__addr) (_upa_readl((unsigned long)(__addr)))
+#define upa_readq(__addr) (_upa_readq((unsigned long)(__addr)))
+#define upa_writeb(__b, __addr) (_upa_writeb((__b), (unsigned long)(__addr)))
+#define upa_writew(__w, __addr) (_upa_writew((__w), (unsigned long)(__addr)))
+#define upa_writel(__l, __addr) (_upa_writel((__l), (unsigned long)(__addr)))
+#define upa_writeq(__q, __addr) (_upa_writeq((__q), (unsigned long)(__addr)))
+#endif /* __KERNEL__ && !__ASSEMBLY__ */
+
+#endif /* !(_SPARC64_UPA_H) */
--- /dev/null
+#ifndef _SPARC_USER_H
+#define _SPARC_USER_H
+
+/* Nothing to define. */
+
+#endif /* !(_SPARC_USER_H) */
--- /dev/null
+/*
+ * include/asm/utrap.h
+ *
+ * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+
+#ifndef __ASM_SPARC64_UTRAP_H
+#define __ASM_SPARC64_UTRAP_H
+
+#define UT_INSTRUCTION_EXCEPTION 1
+#define UT_INSTRUCTION_ERROR 2
+#define UT_INSTRUCTION_PROTECTION 3
+#define UT_ILLTRAP_INSTRUCTION 4
+#define UT_ILLEGAL_INSTRUCTION 5
+#define UT_PRIVILEGED_OPCODE 6
+#define UT_FP_DISABLED 7
+#define UT_FP_EXCEPTION_IEEE_754 8
+#define UT_FP_EXCEPTION_OTHER 9
+#define UT_TAG_OVERVIEW 10
+#define UT_DIVISION_BY_ZERO 11
+#define UT_DATA_EXCEPTION 12
+#define UT_DATA_ERROR 13
+#define UT_DATA_PROTECTION 14
+#define UT_MEM_ADDRESS_NOT_ALIGNED 15
+#define UT_PRIVILEGED_ACTION 16
+#define UT_ASYNC_DATA_ERROR 17
+#define UT_TRAP_INSTRUCTION_16 18
+#define UT_TRAP_INSTRUCTION_17 19
+#define UT_TRAP_INSTRUCTION_18 20
+#define UT_TRAP_INSTRUCTION_19 21
+#define UT_TRAP_INSTRUCTION_20 22
+#define UT_TRAP_INSTRUCTION_21 23
+#define UT_TRAP_INSTRUCTION_22 24
+#define UT_TRAP_INSTRUCTION_23 25
+#define UT_TRAP_INSTRUCTION_24 26
+#define UT_TRAP_INSTRUCTION_25 27
+#define UT_TRAP_INSTRUCTION_26 28
+#define UT_TRAP_INSTRUCTION_27 29
+#define UT_TRAP_INSTRUCTION_28 30
+#define UT_TRAP_INSTRUCTION_29 31
+#define UT_TRAP_INSTRUCTION_30 32
+#define UT_TRAP_INSTRUCTION_31 33
+
+#define UTH_NOCHANGE (-1)
+
+#ifndef __ASSEMBLY__
+typedef int utrap_entry_t;
+typedef void *utrap_handler_t;
+#endif /* __ASSEMBLY__ */
+
+#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
--- /dev/null
+#ifndef _SPARC_VAC_OPS_H
+#define _SPARC_VAC_OPS_H
+
+/* vac-ops.h: Inline assembly routines to do operations on the Sparc
+ * VAC (virtual address cache) for the sun4c.
+ *
+ * Copyright (C) 1994, David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#include <asm/sysen.h>
+#include <asm/contregs.h>
+#include <asm/asi.h>
+
+/* The SUN4C models have a virtually addressed write-through
+ * cache.
+ *
+ * The cache tags are directly accessible through an ASI and
+ * each have the form:
+ *
+ * ------------------------------------------------------------
+ * | MBZ | CONTEXT | WRITE | PRIV | VALID | MBZ | TagID | MBZ |
+ * ------------------------------------------------------------
+ * 31 25 24 22 21 20 19 18 16 15 2 1 0
+ *
+ * MBZ: These bits are either unused and/or reserved and should
+ * be written as zeroes.
+ *
+ * CONTEXT: Records the context to which this cache line belongs.
+ *
+ * WRITE: A copy of the writable bit from the mmu pte access bits.
+ *
+ * PRIV: A copy of the privileged bit from the pte access bits.
+ *
+ * VALID: If set, this line is valid, else invalid.
+ *
+ * TagID: Fourteen bits of tag ID.
+ *
+ * Every virtual address is seen by the cache like this:
+ *
+ * ----------------------------------------
+ * | RESV | TagID | LINE | BYTE-in-LINE |
+ * ----------------------------------------
+ * 31 30 29 16 15 4 3 0
+ *
+ * RESV: Unused/reserved.
+ *
+ * TagID: Used to match the Tag-ID in that vac tags.
+ *
+ * LINE: Which line within the cache
+ *
+ * BYTE-in-LINE: Which byte within the cache line.
+ */
+
+/* Sun4c VAC Tags */
+#define S4CVACTAG_CID 0x01c00000
+#define S4CVACTAG_W 0x00200000
+#define S4CVACTAG_P 0x00100000
+#define S4CVACTAG_V 0x00080000
+#define S4CVACTAG_TID 0x0000fffc
+
+/* Sun4c VAC Virtual Address */
+/* These aren't used, why bother? (Anton) */
+#if 0
+#define S4CVACVA_TID 0x3fff0000
+#define S4CVACVA_LINE 0x0000fff0
+#define S4CVACVA_BIL 0x0000000f
+#endif
+
+/* The indexing of cache lines creates a problem. Because the line
+ * field of a virtual address extends past the page offset within
+ * the virtual address it is possible to have what are called
+ * 'bad aliases' which will create inconsistencies. So we must make
+ * sure that within a context that if a physical page is mapped
+ * more than once, that 'extra' line bits are the same. If this is
+ * not the case, and thus is a 'bad alias' we must turn off the
+ * cacheable bit in the pte's of all such pages.
+ */
+
+#ifdef CONFIG_SUN4
+#define S4CVAC_BADBITS 0x0001e000
+#else
+#define S4CVAC_BADBITS 0x0000f000
+#endif
+
+/* The following is true if vaddr1 and vaddr2 would cause
+ * a 'bad alias'.
+ */
+#define S4CVAC_BADALIAS(vaddr1, vaddr2) \
+ ((((unsigned long) (vaddr1)) ^ ((unsigned long) (vaddr2))) & \
+ (S4CVAC_BADBITS))
+
+/* The following structure describes the characteristics of a sun4c
+ * VAC as probed from the prom during boot time.
+ */
+struct sun4c_vac_props {
+ unsigned int num_bytes; /* Size of the cache */
+ unsigned int num_lines; /* Number of cache lines */
+ unsigned int do_hwflushes; /* Hardware flushing available? */
+ enum { VAC_NONE, VAC_WRITE_THROUGH,
+ VAC_WRITE_BACK } type; /* What type of VAC? */
+ unsigned int linesize; /* Size of each line in bytes */
+ unsigned int log2lsize; /* log2(linesize) */
+ unsigned int on; /* VAC is enabled */
+};
+
+extern struct sun4c_vac_props sun4c_vacinfo;
+
+/* sun4c_enable_vac() enables the sun4c virtual address cache. */
+static inline void sun4c_enable_vac(void)
+{
+ __asm__ __volatile__("lduba [%0] %1, %%g1\n\t"
+ "or %%g1, %2, %%g1\n\t"
+ "stba %%g1, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" ((unsigned int) AC_SENABLE),
+ "i" (ASI_CONTROL), "i" (SENABLE_CACHE)
+ : "g1", "memory");
+ sun4c_vacinfo.on = 1;
+}
+
+/* sun4c_disable_vac() disables the virtual address cache. */
+static inline void sun4c_disable_vac(void)
+{
+ __asm__ __volatile__("lduba [%0] %1, %%g1\n\t"
+ "andn %%g1, %2, %%g1\n\t"
+ "stba %%g1, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" ((unsigned int) AC_SENABLE),
+ "i" (ASI_CONTROL), "i" (SENABLE_CACHE)
+ : "g1", "memory");
+ sun4c_vacinfo.on = 0;
+}
+
+#endif /* !(_SPARC_VAC_OPS_H) */
--- /dev/null
+#ifndef _SPARC_VADDRS_H
+#define _SPARC_VADDRS_H
+
+#include <asm/head.h>
+
+/*
+ * asm/vaddrs.h: Here we define the virtual addresses at
+ * which important things will be mapped.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 2000 Anton Blanchard (anton@samba.org)
+ */
+
+#define SRMMU_MAXMEM 0x0c000000
+
+#define SRMMU_NOCACHE_VADDR (KERNBASE + SRMMU_MAXMEM)
+ /* = 0x0fc000000 */
+/* XXX Empiricals - this needs to go away - KMW */
+#define SRMMU_MIN_NOCACHE_PAGES (550)
+#define SRMMU_MAX_NOCACHE_PAGES (1280)
+
+/* The following constant is used in mm/srmmu.c::srmmu_nocache_calcsize()
+ * to determine the amount of memory that will be reserved as nocache:
+ *
+ * 256 pages will be taken as nocache per each
+ * SRMMU_NOCACHE_ALCRATIO MB of system memory.
+ *
+ * limits enforced: nocache minimum = 256 pages
+ * nocache maximum = 1280 pages
+ */
+#define SRMMU_NOCACHE_ALCRATIO 64 /* 256 pages per 64MB of system RAM */
+
+#define SUN4M_IOBASE_VADDR 0xfd000000 /* Base for mapping pages */
+#define IOBASE_VADDR 0xfe000000
+#define IOBASE_END 0xfe600000
+
+/*
+ * On the sun4/4c we need a place
+ * to reliably map locked down kernel data. This includes the
+ * task_struct and kernel stack pages of each process plus the
+ * scsi buffers during dvma IO transfers, also the floppy buffers
+ * during pseudo dma which runs with traps off (no faults allowed).
+ * Some quick calculations yield:
+ * NR_TASKS <512> * (3 * PAGE_SIZE) == 0x600000
+ * Subtract this from 0xc00000 and you get 0x927C0 of vm left
+ * over to map SCSI dvma + floppy pseudo-dma buffers. So be
+ * careful if you change NR_TASKS or else there won't be enough
+ * room for it all.
+ */
+#define SUN4C_LOCK_VADDR 0xff000000
+#define SUN4C_LOCK_END 0xffc00000
+
+#define KADB_DEBUGGER_BEGVM 0xffc00000 /* Where kern debugger is in virt-mem */
+#define KADB_DEBUGGER_ENDVM 0xffd00000
+#define DEBUG_FIRSTVADDR KADB_DEBUGGER_BEGVM
+#define DEBUG_LASTVADDR KADB_DEBUGGER_ENDVM
+
+#define LINUX_OPPROM_BEGVM 0xffd00000
+#define LINUX_OPPROM_ENDVM 0xfff00000
+
+#define DVMA_VADDR 0xfff00000 /* Base area of the DVMA on suns */
+#define DVMA_END 0xfffc0000
+
+#endif /* !(_SPARC_VADDRS_H) */
--- /dev/null
+/* Copyright (c) 1996 by Manish Vachharajani */
+
+#ifndef _LINUX_VFC_IOCTLS_H_
+#define _LINUX_VFC_IOCTLS_H_
+
+ /* IOCTLs */
+#define VFC_IOCTL(a) (('j' << 8) | a)
+#define VFCGCTRL (VFC_IOCTL (0)) /* get vfc attributes */
+#define VFCSCTRL (VFC_IOCTL (1)) /* set vfc attributes */
+#define VFCGVID (VFC_IOCTL (2)) /* get video decoder attributes */
+#define VFCSVID (VFC_IOCTL (3)) /* set video decoder attributes */
+#define VFCHUE (VFC_IOCTL (4)) /* set hue */
+#define VFCPORTCHG (VFC_IOCTL (5)) /* change port */
+#define VFCRDINFO (VFC_IOCTL (6)) /* read info */
+
+ /* Options for setting the vfc attributes and status */
+#define MEMPRST 0x1 /* reset FIFO ptr. */
+#define CAPTRCMD 0x2 /* start capture and wait */
+#define DIAGMODE 0x3 /* diag mode */
+#define NORMMODE 0x4 /* normal mode */
+#define CAPTRSTR 0x5 /* start capture */
+#define CAPTRWAIT 0x6 /* wait for capture to finish */
+
+
+ /* Options for the decoder */
+#define STD_NTSC 0x1 /* NTSC mode */
+#define STD_PAL 0x2 /* PAL mode */
+#define COLOR_ON 0x3 /* force color ON */
+#define MONO 0x4 /* force color OFF */
+
+ /* Values returned by ioctl 2 */
+
+#define NO_LOCK 1
+#define NTSC_COLOR 2
+#define NTSC_NOCOLOR 3
+#define PAL_COLOR 4
+#define PAL_NOCOLOR 5
+
+/* Not too sure what this does yet */
+ /* Options for setting Field number */
+#define ODD_FIELD 0x1
+#define EVEN_FIELD 0x0
+#define ACTIVE_ONLY 0x2
+#define NON_ACTIVE 0x0
+
+/* Debug options */
+#define VFC_I2C_SEND 0
+#define VFC_I2C_RECV 1
+
+struct vfc_debug_inout
+{
+ unsigned long addr;
+ unsigned long ret;
+ unsigned long len;
+ unsigned char __user *buffer;
+};
+
+#endif /* _LINUX_VFC_IOCTLS_H_ */
--- /dev/null
+/*
+ * Access to VGA videoram
+ *
+ * (c) 1998 Martin Mares <mj@ucw.cz>
+ */
+
+#ifndef _LINUX_ASM_VGA_H_
+#define _LINUX_ASM_VGA_H_
+
+#include <asm/types.h>
+
+#define VT_BUF_HAVE_RW
+
+#undef scr_writew
+#undef scr_readw
+
+static inline void scr_writew(u16 val, u16 *addr)
+{
+ BUG_ON((long) addr >= 0);
+
+ *addr = val;
+}
+
+static inline u16 scr_readw(const u16 *addr)
+{
+ BUG_ON((long) addr >= 0);
+
+ return *addr;
+}
+
+#define VGA_MAP_MEM(x,s) (x)
+
+#endif
--- /dev/null
+/*
+ * viking.h: Defines specific to the GNU/Viking MBUS module.
+ * This is SRMMU stuff.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_VIKING_H
+#define _SPARC_VIKING_H
+
+#include <asm/asi.h>
+#include <asm/mxcc.h>
+#include <asm/pgtsrmmu.h>
+
+/* Bits in the SRMMU control register for GNU/Viking modules.
+ *
+ * -----------------------------------------------------------
+ * |impl-vers| RSV |TC|AC|SP|BM|PC|MBM|SB|IC|DC|PSO|RSV|NF|ME|
+ * -----------------------------------------------------------
+ * 31 24 23-17 16 15 14 13 12 11 10 9 8 7 6-2 1 0
+ *
+ * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache
+ * 1 = Twalks are cacheable in E-cache
+ *
+ * GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present
+ * and never caches them internally (or so states the docs). Therefore
+ * for machines lacking an E-cache (ie. in MBUS mode) this bit must
+ * remain cleared.
+ *
+ * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable
+ * 1 = Passthru physical accesses cacheable
+ *
+ * This indicates whether accesses are cacheable when no cachable bit
+ * is present in the pte when the processor is in boot-mode or the
+ * access does not need pte's for translation (ie. pass-thru ASI's).
+ * "Cachable" is only referring to E-cache (if present) and not the
+ * on chip split I/D caches of the GNU/Viking.
+ *
+ * SP: SnooP Enable -- 0 = bus snooping off, 1 = bus snooping on
+ *
+ * This enables snooping on the GNU/Viking bus. This must be on
+ * for the hardware cache consistency mechanisms of the GNU/Viking
+ * to work at all. On non-mxcc GNU/Viking modules the split I/D
+ * caches will snoop regardless of whether they are enabled, this
+ * takes care of the case where the I or D or both caches are turned
+ * off yet still contain valid data. Note also that this bit does
+ * not affect GNU/Viking store-buffer snoops, those happen if the
+ * store-buffer is enabled no matter what.
+ *
+ * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
+ *
+ * This indicates whether the GNU/Viking is in boot-mode or not,
+ * if it is then all instruction fetch physical addresses are
+ * computed as 0xff0000000 + low 28 bits of requested address.
+ * GNU/Viking boot-mode does not affect data accesses. Also,
+ * in boot mode instruction accesses bypass the split on chip I/D
+ * caches, they may be cached by the GNU/MXCC if present and enabled.
+ *
+ * MBM: MBus Mode -- 0 = not in MBus mode, 1 = in MBus mode
+ *
+ * This indicated the GNU/Viking configuration present. If in
+ * MBUS mode, the GNU/Viking lacks a GNU/MXCC E-cache. If it is
+ * not then the GNU/Viking is on a module VBUS connected directly
+ * to a GNU/MXCC cache controller. The GNU/MXCC can be thus connected
+ * to either an GNU/MBUS (sun4m) or the packet-switched GNU/XBus (sun4d).
+ *
+ * SB: StoreBuffer enable -- 0 = store buffer off, 1 = store buffer on
+ *
+ * The GNU/Viking store buffer allows the chip to continue execution
+ * after a store even if the data cannot be placed in one of the
+ * caches during that cycle. If disabled, all stores operations
+ * occur synchronously.
+ *
+ * IC: Instruction Cache -- 0 = off, 1 = on
+ * DC: Data Cache -- 0 = off, 1 = 0n
+ *
+ * These bits enable the on-cpu GNU/Viking split I/D caches. Note,
+ * as mentioned above, these caches will snoop the bus in GNU/MBUS
+ * configurations even when disabled to avoid data corruption.
+ *
+ * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
+ * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
+ *
+ */
+
+#define VIKING_MMUENABLE 0x00000001
+#define VIKING_NOFAULT 0x00000002
+#define VIKING_PSO 0x00000080
+#define VIKING_DCENABLE 0x00000100 /* Enable data cache */
+#define VIKING_ICENABLE 0x00000200 /* Enable instruction cache */
+#define VIKING_SBENABLE 0x00000400 /* Enable store buffer */
+#define VIKING_MMODE 0x00000800 /* MBUS mode */
+#define VIKING_PCENABLE 0x00001000 /* Enable parity checking */
+#define VIKING_BMODE 0x00002000
+#define VIKING_SPENABLE 0x00004000 /* Enable bus cache snooping */
+#define VIKING_ACENABLE 0x00008000 /* Enable alternate caching */
+#define VIKING_TCENABLE 0x00010000 /* Enable table-walks to be cached */
+#define VIKING_DPENABLE 0x00040000 /* Enable the data prefetcher */
+
+/*
+ * GNU/Viking Breakpoint Action Register fields.
+ */
+#define VIKING_ACTION_MIX 0x00001000 /* Enable multiple instructions */
+
+/*
+ * GNU/Viking Cache Tags.
+ */
+#define VIKING_PTAG_VALID 0x01000000 /* Cache block is valid */
+#define VIKING_PTAG_DIRTY 0x00010000 /* Block has been modified */
+#define VIKING_PTAG_SHARED 0x00000100 /* Shared with some other cache */
+
+#ifndef __ASSEMBLY__
+
+static inline void viking_flush_icache(void)
+{
+ __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
+ : /* no outputs */
+ : "i" (ASI_M_IC_FLCLEAR)
+ : "memory");
+}
+
+static inline void viking_flush_dcache(void)
+{
+ __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
+ : /* no outputs */
+ : "i" (ASI_M_DC_FLCLEAR)
+ : "memory");
+}
+
+static inline void viking_unlock_icache(void)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" (0x80000000), "i" (ASI_M_IC_FLCLEAR)
+ : "memory");
+}
+
+static inline void viking_unlock_dcache(void)
+{
+ __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+ : /* no outputs */
+ : "r" (0x80000000), "i" (ASI_M_DC_FLCLEAR)
+ : "memory");
+}
+
+static inline void viking_set_bpreg(unsigned long regval)
+{
+ __asm__ __volatile__("sta %0, [%%g0] %1\n\t"
+ : /* no outputs */
+ : "r" (regval), "i" (ASI_M_ACTION)
+ : "memory");
+}
+
+static inline unsigned long viking_get_bpreg(void)
+{
+ unsigned long regval;
+
+ __asm__ __volatile__("lda [%%g0] %1, %0\n\t"
+ : "=r" (regval)
+ : "i" (ASI_M_ACTION));
+ return regval;
+}
+
+static inline void viking_get_dcache_ptag(int set, int block,
+ unsigned long *data)
+{
+ unsigned long ptag = ((set & 0x7f) << 5) | ((block & 0x3) << 26) |
+ 0x80000000;
+ unsigned long info, page;
+
+ __asm__ __volatile__ ("ldda [%2] %3, %%g2\n\t"
+ "or %%g0, %%g2, %0\n\t"
+ "or %%g0, %%g3, %1\n\t"
+ : "=r" (info), "=r" (page)
+ : "r" (ptag), "i" (ASI_M_DATAC_TAG)
+ : "g2", "g3");
+ data[0] = info;
+ data[1] = page;
+}
+
+static inline void viking_mxcc_turn_off_parity(unsigned long *mregp,
+ unsigned long *mxcc_cregp)
+{
+ unsigned long mreg = *mregp;
+ unsigned long mxcc_creg = *mxcc_cregp;
+
+ mreg &= ~(VIKING_PCENABLE);
+ mxcc_creg &= ~(MXCC_CTL_PARE);
+
+ __asm__ __volatile__ ("set 1f, %%g2\n\t"
+ "andcc %%g2, 4, %%g0\n\t"
+ "bne 2f\n\t"
+ " nop\n"
+ "1:\n\t"
+ "sta %0, [%%g0] %3\n\t"
+ "sta %1, [%2] %4\n\t"
+ "b 1f\n\t"
+ " nop\n\t"
+ "nop\n"
+ "2:\n\t"
+ "sta %0, [%%g0] %3\n\t"
+ "sta %1, [%2] %4\n"
+ "1:\n\t"
+ : /* no output */
+ : "r" (mreg), "r" (mxcc_creg),
+ "r" (MXCC_CREG), "i" (ASI_M_MMUREGS),
+ "i" (ASI_M_MXCC)
+ : "g2", "memory", "cc");
+ *mregp = mreg;
+ *mxcc_cregp = mxcc_creg;
+}
+
+static inline unsigned long viking_hwprobe(unsigned long vaddr)
+{
+ unsigned long val;
+
+ vaddr &= PAGE_MASK;
+ /* Probe all MMU entries. */
+ __asm__ __volatile__("lda [%1] %2, %0\n\t"
+ : "=r" (val)
+ : "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
+ if (!val)
+ return 0;
+
+ /* Probe region. */
+ __asm__ __volatile__("lda [%1] %2, %0\n\t"
+ : "=r" (val)
+ : "r" (vaddr | 0x200), "i" (ASI_M_FLUSH_PROBE));
+ if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
+ vaddr &= ~SRMMU_PGDIR_MASK;
+ vaddr >>= PAGE_SHIFT;
+ return val | (vaddr << 8);
+ }
+
+ /* Probe segment. */
+ __asm__ __volatile__("lda [%1] %2, %0\n\t"
+ : "=r" (val)
+ : "r" (vaddr | 0x100), "i" (ASI_M_FLUSH_PROBE));
+ if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
+ vaddr &= ~SRMMU_REAL_PMD_MASK;
+ vaddr >>= PAGE_SHIFT;
+ return val | (vaddr << 8);
+ }
+
+ /* Probe page. */
+ __asm__ __volatile__("lda [%1] %2, %0\n\t"
+ : "=r" (val)
+ : "r" (vaddr), "i" (ASI_M_FLUSH_PROBE));
+ return val;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* !(_SPARC_VIKING_H) */
--- /dev/null
+#ifndef _SPARC64_VIO_H
+#define _SPARC64_VIO_H
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/completion.h>
+#include <linux/list.h>
+#include <linux/log2.h>
+
+#include <asm/ldc.h>
+#include <asm/mdesc.h>
+
+struct vio_msg_tag {
+ u8 type;
+#define VIO_TYPE_CTRL 0x01
+#define VIO_TYPE_DATA 0x02
+#define VIO_TYPE_ERR 0x04
+
+ u8 stype;
+#define VIO_SUBTYPE_INFO 0x01
+#define VIO_SUBTYPE_ACK 0x02
+#define VIO_SUBTYPE_NACK 0x04
+
+ u16 stype_env;
+#define VIO_VER_INFO 0x0001
+#define VIO_ATTR_INFO 0x0002
+#define VIO_DRING_REG 0x0003
+#define VIO_DRING_UNREG 0x0004
+#define VIO_RDX 0x0005
+#define VIO_PKT_DATA 0x0040
+#define VIO_DESC_DATA 0x0041
+#define VIO_DRING_DATA 0x0042
+#define VNET_MCAST_INFO 0x0101
+
+ u32 sid;
+};
+
+struct vio_rdx {
+ struct vio_msg_tag tag;
+ u64 resv[6];
+};
+
+struct vio_ver_info {
+ struct vio_msg_tag tag;
+ u16 major;
+ u16 minor;
+ u8 dev_class;
+#define VDEV_NETWORK 0x01
+#define VDEV_NETWORK_SWITCH 0x02
+#define VDEV_DISK 0x03
+#define VDEV_DISK_SERVER 0x04
+
+ u8 resv1[3];
+ u64 resv2[5];
+};
+
+struct vio_dring_register {
+ struct vio_msg_tag tag;
+ u64 dring_ident;
+ u32 num_descr;
+ u32 descr_size;
+ u16 options;
+#define VIO_TX_DRING 0x0001
+#define VIO_RX_DRING 0x0002
+ u16 resv;
+ u32 num_cookies;
+ struct ldc_trans_cookie cookies[0];
+};
+
+struct vio_dring_unregister {
+ struct vio_msg_tag tag;
+ u64 dring_ident;
+ u64 resv[5];
+};
+
+/* Data transfer modes */
+#define VIO_PKT_MODE 0x01 /* Packet based transfer */
+#define VIO_DESC_MODE 0x02 /* In-band descriptors */
+#define VIO_DRING_MODE 0x03 /* Descriptor rings */
+
+struct vio_dring_data {
+ struct vio_msg_tag tag;
+ u64 seq;
+ u64 dring_ident;
+ u32 start_idx;
+ u32 end_idx;
+ u8 state;
+#define VIO_DRING_ACTIVE 0x01
+#define VIO_DRING_STOPPED 0x02
+
+ u8 __pad1;
+ u16 __pad2;
+ u32 __pad3;
+ u64 __par4[2];
+};
+
+struct vio_dring_hdr {
+ u8 state;
+#define VIO_DESC_FREE 0x01
+#define VIO_DESC_READY 0x02
+#define VIO_DESC_ACCEPTED 0x03
+#define VIO_DESC_DONE 0x04
+ u8 ack;
+#define VIO_ACK_ENABLE 0x01
+#define VIO_ACK_DISABLE 0x00
+
+ u16 __pad1;
+ u32 __pad2;
+};
+
+/* VIO disk specific structures and defines */
+struct vio_disk_attr_info {
+ struct vio_msg_tag tag;
+ u8 xfer_mode;
+ u8 vdisk_type;
+#define VD_DISK_TYPE_SLICE 0x01 /* Slice in block device */
+#define VD_DISK_TYPE_DISK 0x02 /* Entire block device */
+ u16 resv1;
+ u32 vdisk_block_size;
+ u64 operations;
+ u64 vdisk_size;
+ u64 max_xfer_size;
+ u64 resv2[2];
+};
+
+struct vio_disk_desc {
+ struct vio_dring_hdr hdr;
+ u64 req_id;
+ u8 operation;
+#define VD_OP_BREAD 0x01 /* Block read */
+#define VD_OP_BWRITE 0x02 /* Block write */
+#define VD_OP_FLUSH 0x03 /* Flush disk contents */
+#define VD_OP_GET_WCE 0x04 /* Get write-cache status */
+#define VD_OP_SET_WCE 0x05 /* Enable/disable write-cache */
+#define VD_OP_GET_VTOC 0x06 /* Get VTOC */
+#define VD_OP_SET_VTOC 0x07 /* Set VTOC */
+#define VD_OP_GET_DISKGEOM 0x08 /* Get disk geometry */
+#define VD_OP_SET_DISKGEOM 0x09 /* Set disk geometry */
+#define VD_OP_SCSICMD 0x0a /* SCSI control command */
+#define VD_OP_GET_DEVID 0x0b /* Get device ID */
+#define VD_OP_GET_EFI 0x0c /* Get EFI */
+#define VD_OP_SET_EFI 0x0d /* Set EFI */
+ u8 slice;
+ u16 resv1;
+ u32 status;
+ u64 offset;
+ u64 size;
+ u32 ncookies;
+ u32 resv2;
+ struct ldc_trans_cookie cookies[0];
+};
+
+#define VIO_DISK_VNAME_LEN 8
+#define VIO_DISK_ALABEL_LEN 128
+#define VIO_DISK_NUM_PART 8
+
+struct vio_disk_vtoc {
+ u8 volume_name[VIO_DISK_VNAME_LEN];
+ u16 sector_size;
+ u16 num_partitions;
+ u8 ascii_label[VIO_DISK_ALABEL_LEN];
+ struct {
+ u16 id;
+ u16 perm_flags;
+ u32 resv;
+ u64 start_block;
+ u64 num_blocks;
+ } partitions[VIO_DISK_NUM_PART];
+};
+
+struct vio_disk_geom {
+ u16 num_cyl; /* Num data cylinders */
+ u16 alt_cyl; /* Num alternate cylinders */
+ u16 beg_cyl; /* Cyl off of fixed head area */
+ u16 num_hd; /* Num heads */
+ u16 num_sec; /* Num sectors */
+ u16 ifact; /* Interleave factor */
+ u16 apc; /* Alts per cylinder (SCSI) */
+ u16 rpm; /* Revolutions per minute */
+ u16 phy_cyl; /* Num physical cylinders */
+ u16 wr_skip; /* Num sects to skip, writes */
+ u16 rd_skip; /* Num sects to skip, writes */
+};
+
+struct vio_disk_devid {
+ u16 resv;
+ u16 type;
+ u32 len;
+ char id[0];
+};
+
+struct vio_disk_efi {
+ u64 lba;
+ u64 len;
+ char data[0];
+};
+
+/* VIO net specific structures and defines */
+struct vio_net_attr_info {
+ struct vio_msg_tag tag;
+ u8 xfer_mode;
+ u8 addr_type;
+#define VNET_ADDR_ETHERMAC 0x01
+ u16 ack_freq;
+ u32 resv1;
+ u64 addr;
+ u64 mtu;
+ u64 resv2[3];
+};
+
+#define VNET_NUM_MCAST 7
+
+struct vio_net_mcast_info {
+ struct vio_msg_tag tag;
+ u8 set;
+ u8 count;
+ u8 mcast_addr[VNET_NUM_MCAST * 6];
+ u32 resv;
+};
+
+struct vio_net_desc {
+ struct vio_dring_hdr hdr;
+ u32 size;
+ u32 ncookies;
+ struct ldc_trans_cookie cookies[0];
+};
+
+#define VIO_MAX_RING_COOKIES 24
+
+struct vio_dring_state {
+ u64 ident;
+ void *base;
+ u64 snd_nxt;
+ u64 rcv_nxt;
+ u32 entry_size;
+ u32 num_entries;
+ u32 prod;
+ u32 cons;
+ u32 pending;
+ int ncookies;
+ struct ldc_trans_cookie cookies[VIO_MAX_RING_COOKIES];
+};
+
+static inline void *vio_dring_cur(struct vio_dring_state *dr)
+{
+ return dr->base + (dr->entry_size * dr->prod);
+}
+
+static inline void *vio_dring_entry(struct vio_dring_state *dr,
+ unsigned int index)
+{
+ return dr->base + (dr->entry_size * index);
+}
+
+static inline u32 vio_dring_avail(struct vio_dring_state *dr,
+ unsigned int ring_size)
+{
+ BUILD_BUG_ON(!is_power_of_2(ring_size));
+
+ return (dr->pending -
+ ((dr->prod - dr->cons) & (ring_size - 1)));
+}
+
+#define VIO_MAX_TYPE_LEN 32
+#define VIO_MAX_COMPAT_LEN 64
+
+struct vio_dev {
+ u64 mp;
+ struct device_node *dp;
+
+ char type[VIO_MAX_TYPE_LEN];
+ char compat[VIO_MAX_COMPAT_LEN];
+ int compat_len;
+
+ u64 dev_no;
+
+ unsigned long channel_id;
+
+ unsigned int tx_irq;
+ unsigned int rx_irq;
+
+ struct device dev;
+};
+
+struct vio_driver {
+ struct list_head node;
+ const struct vio_device_id *id_table;
+ int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
+ int (*remove)(struct vio_dev *dev);
+ void (*shutdown)(struct vio_dev *dev);
+ unsigned long driver_data;
+ struct device_driver driver;
+};
+
+struct vio_version {
+ u16 major;
+ u16 minor;
+};
+
+struct vio_driver_state;
+struct vio_driver_ops {
+ int (*send_attr)(struct vio_driver_state *vio);
+ int (*handle_attr)(struct vio_driver_state *vio, void *pkt);
+ void (*handshake_complete)(struct vio_driver_state *vio);
+};
+
+struct vio_completion {
+ struct completion com;
+ int err;
+ int waiting_for;
+};
+
+struct vio_driver_state {
+ /* Protects VIO handshake and, optionally, driver private state. */
+ spinlock_t lock;
+
+ struct ldc_channel *lp;
+
+ u32 _peer_sid;
+ u32 _local_sid;
+ struct vio_dring_state drings[2];
+#define VIO_DRIVER_TX_RING 0
+#define VIO_DRIVER_RX_RING 1
+
+ u8 hs_state;
+#define VIO_HS_INVALID 0x00
+#define VIO_HS_GOTVERS 0x01
+#define VIO_HS_GOT_ATTR 0x04
+#define VIO_HS_SENT_DREG 0x08
+#define VIO_HS_SENT_RDX 0x10
+#define VIO_HS_GOT_RDX_ACK 0x20
+#define VIO_HS_GOT_RDX 0x40
+#define VIO_HS_SENT_RDX_ACK 0x80
+#define VIO_HS_COMPLETE (VIO_HS_GOT_RDX_ACK | VIO_HS_SENT_RDX_ACK)
+
+ u8 dev_class;
+
+ u8 dr_state;
+#define VIO_DR_STATE_TXREG 0x01
+#define VIO_DR_STATE_RXREG 0x02
+#define VIO_DR_STATE_TXREQ 0x10
+#define VIO_DR_STATE_RXREQ 0x20
+
+ u8 debug;
+#define VIO_DEBUG_HS 0x01
+#define VIO_DEBUG_DATA 0x02
+
+ void *desc_buf;
+ unsigned int desc_buf_len;
+
+ struct vio_completion *cmp;
+
+ struct vio_dev *vdev;
+
+ struct timer_list timer;
+
+ struct vio_version ver;
+
+ struct vio_version *ver_table;
+ int ver_table_entries;
+
+ char *name;
+
+ struct vio_driver_ops *ops;
+};
+
+#define viodbg(TYPE, f, a...) \
+do { if (vio->debug & VIO_DEBUG_##TYPE) \
+ printk(KERN_INFO "vio: ID[%lu] " f, \
+ vio->vdev->channel_id, ## a); \
+} while (0)
+
+extern int vio_register_driver(struct vio_driver *drv);
+extern void vio_unregister_driver(struct vio_driver *drv);
+
+static inline struct vio_driver *to_vio_driver(struct device_driver *drv)
+{
+ return container_of(drv, struct vio_driver, driver);
+}
+
+static inline struct vio_dev *to_vio_dev(struct device *dev)
+{
+ return container_of(dev, struct vio_dev, dev);
+}
+
+extern int vio_ldc_send(struct vio_driver_state *vio, void *data, int len);
+extern void vio_link_state_change(struct vio_driver_state *vio, int event);
+extern void vio_conn_reset(struct vio_driver_state *vio);
+extern int vio_control_pkt_engine(struct vio_driver_state *vio, void *pkt);
+extern int vio_validate_sid(struct vio_driver_state *vio,
+ struct vio_msg_tag *tp);
+extern u32 vio_send_sid(struct vio_driver_state *vio);
+extern int vio_ldc_alloc(struct vio_driver_state *vio,
+ struct ldc_channel_config *base_cfg, void *event_arg);
+extern void vio_ldc_free(struct vio_driver_state *vio);
+extern int vio_driver_init(struct vio_driver_state *vio, struct vio_dev *vdev,
+ u8 dev_class, struct vio_version *ver_table,
+ int ver_table_size, struct vio_driver_ops *ops,
+ char *name);
+
+extern void vio_port_up(struct vio_driver_state *vio);
+
+#endif /* _SPARC64_VIO_H */
--- /dev/null
+#ifndef _SPARC64_VISASM_H
+#define _SPARC64_VISASM_H
+
+/* visasm.h: FPU saving macros for VIS routines
+ *
+ * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
+ */
+
+#include <asm/pstate.h>
+#include <asm/ptrace.h>
+
+/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
+
+#define VISEntry \
+ rd %fprs, %o5; \
+ andcc %o5, (FPRS_FEF|FPRS_DU), %g0; \
+ be,pt %icc, 297f; \
+ sethi %hi(297f), %g7; \
+ sethi %hi(VISenter), %g1; \
+ jmpl %g1 + %lo(VISenter), %g0; \
+ or %g7, %lo(297f), %g7; \
+297: wr %g0, FPRS_FEF, %fprs; \
+
+#define VISExit \
+ wr %g0, 0, %fprs;
+
+/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc.
+ * Must preserve %o5 between VISEntryHalf and VISExitHalf */
+
+#define VISEntryHalf \
+ rd %fprs, %o5; \
+ andcc %o5, FPRS_FEF, %g0; \
+ be,pt %icc, 297f; \
+ sethi %hi(298f), %g7; \
+ sethi %hi(VISenterhalf), %g1; \
+ jmpl %g1 + %lo(VISenterhalf), %g0; \
+ or %g7, %lo(298f), %g7; \
+ clr %o5; \
+297: wr %o5, FPRS_FEF, %fprs; \
+298:
+
+#define VISExitHalf \
+ wr %o5, 0, %fprs;
+
+#ifndef __ASSEMBLY__
+static inline void save_and_clear_fpu(void) {
+ __asm__ __volatile__ (
+" rd %%fprs, %%o5\n"
+" andcc %%o5, %0, %%g0\n"
+" be,pt %%icc, 299f\n"
+" sethi %%hi(298f), %%g7\n"
+" sethi %%hi(VISenter), %%g1\n"
+" jmpl %%g1 + %%lo(VISenter), %%g0\n"
+" or %%g7, %%lo(298f), %%g7\n"
+" 298: wr %%g0, 0, %%fprs\n"
+" 299:\n"
+" " : : "i" (FPRS_FEF|FPRS_DU) :
+ "o5", "g1", "g2", "g3", "g7", "cc");
+}
+#endif
+
+#endif /* _SPARC64_ASI_H */
--- /dev/null
+/*
+ *
+ * watchdog - Driver interface for the hardware watchdog timers
+ * present on Sun Microsystems boardsets
+ *
+ * Copyright (c) 2000 Eric Brower <ebrower@usa.net>
+ *
+ */
+
+#ifndef _SPARC64_WATCHDOG_H
+#define _SPARC64_WATCHDOG_H
+
+#include <linux/watchdog.h>
+
+/* Solaris compatibility ioctls--
+ * Ref. <linux/watchdog.h> for standard linux watchdog ioctls
+ */
+#define WIOCSTART _IO (WATCHDOG_IOCTL_BASE, 10) /* Start Timer */
+#define WIOCSTOP _IO (WATCHDOG_IOCTL_BASE, 11) /* Stop Timer */
+#define WIOCGSTAT _IOR(WATCHDOG_IOCTL_BASE, 12, int)/* Get Timer Status */
+
+/* Status flags from WIOCGSTAT ioctl
+ */
+#define WD_FREERUN 0x01 /* timer is running, interrupts disabled */
+#define WD_EXPIRED 0x02 /* timer has expired */
+#define WD_RUNNING 0x04 /* timer is running, interrupts enabled */
+#define WD_STOPPED 0x08 /* timer has not been started */
+#define WD_SERVICED 0x10 /* timer interrupt was serviced */
+
+#endif /* ifndef _SPARC64_WATCHDOG_H */
+
--- /dev/null
+/*
+ * winmacro.h: Window loading-unloading macros.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_WINMACRO_H
+#define _SPARC_WINMACRO_H
+
+#include <asm/ptrace.h>
+
+/* Store the register window onto the 8-byte aligned area starting
+ * at %reg. It might be %sp, it might not, we don't care.
+ */
+#define STORE_WINDOW(reg) \
+ std %l0, [%reg + RW_L0]; \
+ std %l2, [%reg + RW_L2]; \
+ std %l4, [%reg + RW_L4]; \
+ std %l6, [%reg + RW_L6]; \
+ std %i0, [%reg + RW_I0]; \
+ std %i2, [%reg + RW_I2]; \
+ std %i4, [%reg + RW_I4]; \
+ std %i6, [%reg + RW_I6];
+
+/* Load a register window from the area beginning at %reg. */
+#define LOAD_WINDOW(reg) \
+ ldd [%reg + RW_L0], %l0; \
+ ldd [%reg + RW_L2], %l2; \
+ ldd [%reg + RW_L4], %l4; \
+ ldd [%reg + RW_L6], %l6; \
+ ldd [%reg + RW_I0], %i0; \
+ ldd [%reg + RW_I2], %i2; \
+ ldd [%reg + RW_I4], %i4; \
+ ldd [%reg + RW_I6], %i6;
+
+/* Loading and storing struct pt_reg trap frames. */
+#define LOAD_PT_INS(base_reg) \
+ ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
+ ldd [%base_reg + STACKFRAME_SZ + PT_I2], %i2; \
+ ldd [%base_reg + STACKFRAME_SZ + PT_I4], %i4; \
+ ldd [%base_reg + STACKFRAME_SZ + PT_I6], %i6;
+
+#define LOAD_PT_GLOBALS(base_reg) \
+ ld [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \
+ ldd [%base_reg + STACKFRAME_SZ + PT_G2], %g2; \
+ ldd [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \
+ ldd [%base_reg + STACKFRAME_SZ + PT_G6], %g6;
+
+#define LOAD_PT_YREG(base_reg, scratch) \
+ ld [%base_reg + STACKFRAME_SZ + PT_Y], %scratch; \
+ wr %scratch, 0x0, %y;
+
+#define LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
+ ld [%base_reg + STACKFRAME_SZ + PT_PSR], %pt_psr; \
+ ld [%base_reg + STACKFRAME_SZ + PT_PC], %pt_pc; \
+ ld [%base_reg + STACKFRAME_SZ + PT_NPC], %pt_npc;
+
+#define LOAD_PT_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \
+ LOAD_PT_YREG(base_reg, scratch) \
+ LOAD_PT_INS(base_reg) \
+ LOAD_PT_GLOBALS(base_reg) \
+ LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc)
+
+#define STORE_PT_INS(base_reg) \
+ std %i0, [%base_reg + STACKFRAME_SZ + PT_I0]; \
+ std %i2, [%base_reg + STACKFRAME_SZ + PT_I2]; \
+ std %i4, [%base_reg + STACKFRAME_SZ + PT_I4]; \
+ std %i6, [%base_reg + STACKFRAME_SZ + PT_I6];
+
+#define STORE_PT_GLOBALS(base_reg) \
+ st %g1, [%base_reg + STACKFRAME_SZ + PT_G1]; \
+ std %g2, [%base_reg + STACKFRAME_SZ + PT_G2]; \
+ std %g4, [%base_reg + STACKFRAME_SZ + PT_G4]; \
+ std %g6, [%base_reg + STACKFRAME_SZ + PT_G6];
+
+#define STORE_PT_YREG(base_reg, scratch) \
+ rd %y, %scratch; \
+ st %scratch, [%base_reg + STACKFRAME_SZ + PT_Y];
+
+#define STORE_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
+ st %pt_psr, [%base_reg + STACKFRAME_SZ + PT_PSR]; \
+ st %pt_pc, [%base_reg + STACKFRAME_SZ + PT_PC]; \
+ st %pt_npc, [%base_reg + STACKFRAME_SZ + PT_NPC];
+
+#define STORE_PT_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \
+ STORE_PT_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \
+ STORE_PT_GLOBALS(base_reg) \
+ STORE_PT_YREG(base_reg, g_scratch) \
+ STORE_PT_INS(base_reg)
+
+#define SAVE_BOLIXED_USER_STACK(cur_reg, scratch) \
+ ld [%cur_reg + TI_W_SAVED], %scratch; \
+ sll %scratch, 2, %scratch; \
+ add %scratch, %cur_reg, %scratch; \
+ st %sp, [%scratch + TI_RWIN_SPTRS]; \
+ sub %scratch, %cur_reg, %scratch; \
+ sll %scratch, 4, %scratch; \
+ add %scratch, %cur_reg, %scratch; \
+ STORE_WINDOW(scratch + TI_REG_WINDOW); \
+ sub %scratch, %cur_reg, %scratch; \
+ srl %scratch, 6, %scratch; \
+ add %scratch, 1, %scratch; \
+ st %scratch, [%cur_reg + TI_W_SAVED];
+
+#ifdef CONFIG_SMP
+#define LOAD_CURRENT4M(dest_reg, idreg) \
+ rd %tbr, %idreg; \
+ sethi %hi(current_set), %dest_reg; \
+ srl %idreg, 10, %idreg; \
+ or %dest_reg, %lo(current_set), %dest_reg; \
+ and %idreg, 0xc, %idreg; \
+ ld [%idreg + %dest_reg], %dest_reg;
+
+#define LOAD_CURRENT4D(dest_reg, idreg) \
+ lda [%g0] ASI_M_VIKING_TMP1, %idreg; \
+ sethi %hi(C_LABEL(current_set)), %dest_reg; \
+ sll %idreg, 2, %idreg; \
+ or %dest_reg, %lo(C_LABEL(current_set)), %dest_reg; \
+ ld [%idreg + %dest_reg], %dest_reg;
+
+/* Blackbox - take care with this... - check smp4m and smp4d before changing this. */
+#define LOAD_CURRENT(dest_reg, idreg) \
+ sethi %hi(___b_load_current), %idreg; \
+ sethi %hi(current_set), %dest_reg; \
+ sethi %hi(boot_cpu_id4), %idreg; \
+ or %dest_reg, %lo(current_set), %dest_reg; \
+ ldub [%idreg + %lo(boot_cpu_id4)], %idreg; \
+ ld [%idreg + %dest_reg], %dest_reg;
+#else
+#define LOAD_CURRENT(dest_reg, idreg) \
+ sethi %hi(current_set), %idreg; \
+ ld [%idreg + %lo(current_set)], %dest_reg;
+#endif
+
+#endif /* !(_SPARC_WINMACRO_H) */
--- /dev/null
+#ifndef ___ASM_SPARC_XOR_H
+#define ___ASM_SPARC_XOR_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/xor_64.h>
+#else
+#include <asm/xor_32.h>
+#endif
+#endif
--- /dev/null
+/*
+ * include/asm/xor.h
+ *
+ * Optimized RAID-5 checksumming functions for 32-bit Sparc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * (for example /usr/src/linux/COPYING); if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * High speed xor_block operation for RAID4/5 utilizing the
+ * ldd/std SPARC instructions.
+ *
+ * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
+ */
+
+static void
+sparc_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
+{
+ int lines = bytes / (sizeof (long)) / 8;
+
+ do {
+ __asm__ __volatile__(
+ "ldd [%0 + 0x00], %%g2\n\t"
+ "ldd [%0 + 0x08], %%g4\n\t"
+ "ldd [%0 + 0x10], %%o0\n\t"
+ "ldd [%0 + 0x18], %%o2\n\t"
+ "ldd [%1 + 0x00], %%o4\n\t"
+ "ldd [%1 + 0x08], %%l0\n\t"
+ "ldd [%1 + 0x10], %%l2\n\t"
+ "ldd [%1 + 0x18], %%l4\n\t"
+ "xor %%g2, %%o4, %%g2\n\t"
+ "xor %%g3, %%o5, %%g3\n\t"
+ "xor %%g4, %%l0, %%g4\n\t"
+ "xor %%g5, %%l1, %%g5\n\t"
+ "xor %%o0, %%l2, %%o0\n\t"
+ "xor %%o1, %%l3, %%o1\n\t"
+ "xor %%o2, %%l4, %%o2\n\t"
+ "xor %%o3, %%l5, %%o3\n\t"
+ "std %%g2, [%0 + 0x00]\n\t"
+ "std %%g4, [%0 + 0x08]\n\t"
+ "std %%o0, [%0 + 0x10]\n\t"
+ "std %%o2, [%0 + 0x18]\n"
+ :
+ : "r" (p1), "r" (p2)
+ : "g2", "g3", "g4", "g5",
+ "o0", "o1", "o2", "o3", "o4", "o5",
+ "l0", "l1", "l2", "l3", "l4", "l5");
+ p1 += 8;
+ p2 += 8;
+ } while (--lines > 0);
+}
+
+static void
+sparc_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+ unsigned long *p3)
+{
+ int lines = bytes / (sizeof (long)) / 8;
+
+ do {
+ __asm__ __volatile__(
+ "ldd [%0 + 0x00], %%g2\n\t"
+ "ldd [%0 + 0x08], %%g4\n\t"
+ "ldd [%0 + 0x10], %%o0\n\t"
+ "ldd [%0 + 0x18], %%o2\n\t"
+ "ldd [%1 + 0x00], %%o4\n\t"
+ "ldd [%1 + 0x08], %%l0\n\t"
+ "ldd [%1 + 0x10], %%l2\n\t"
+ "ldd [%1 + 0x18], %%l4\n\t"
+ "xor %%g2, %%o4, %%g2\n\t"
+ "xor %%g3, %%o5, %%g3\n\t"
+ "ldd [%2 + 0x00], %%o4\n\t"
+ "xor %%g4, %%l0, %%g4\n\t"
+ "xor %%g5, %%l1, %%g5\n\t"
+ "ldd [%2 + 0x08], %%l0\n\t"
+ "xor %%o0, %%l2, %%o0\n\t"
+ "xor %%o1, %%l3, %%o1\n\t"
+ "ldd [%2 + 0x10], %%l2\n\t"
+ "xor %%o2, %%l4, %%o2\n\t"
+ "xor %%o3, %%l5, %%o3\n\t"
+ "ldd [%2 + 0x18], %%l4\n\t"
+ "xor %%g2, %%o4, %%g2\n\t"
+ "xor %%g3, %%o5, %%g3\n\t"
+ "xor %%g4, %%l0, %%g4\n\t"
+ "xor %%g5, %%l1, %%g5\n\t"
+ "xor %%o0, %%l2, %%o0\n\t"
+ "xor %%o1, %%l3, %%o1\n\t"
+ "xor %%o2, %%l4, %%o2\n\t"
+ "xor %%o3, %%l5, %%o3\n\t"
+ "std %%g2, [%0 + 0x00]\n\t"
+ "std %%g4, [%0 + 0x08]\n\t"
+ "std %%o0, [%0 + 0x10]\n\t"
+ "std %%o2, [%0 + 0x18]\n"
+ :
+ : "r" (p1), "r" (p2), "r" (p3)
+ : "g2", "g3", "g4", "g5",
+ "o0", "o1", "o2", "o3", "o4", "o5",
+ "l0", "l1", "l2", "l3", "l4", "l5");
+ p1 += 8;
+ p2 += 8;
+ p3 += 8;
+ } while (--lines > 0);
+}
+
+static void
+sparc_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+ unsigned long *p3, unsigned long *p4)
+{
+ int lines = bytes / (sizeof (long)) / 8;
+
+ do {
+ __asm__ __volatile__(
+ "ldd [%0 + 0x00], %%g2\n\t"
+ "ldd [%0 + 0x08], %%g4\n\t"
+ "ldd [%0 + 0x10], %%o0\n\t"
+ "ldd [%0 + 0x18], %%o2\n\t"
+ "ldd [%1 + 0x00], %%o4\n\t"
+ "ldd [%1 + 0x08], %%l0\n\t"
+ "ldd [%1 + 0x10], %%l2\n\t"
+ "ldd [%1 + 0x18], %%l4\n\t"
+ "xor %%g2, %%o4, %%g2\n\t"
+ "xor %%g3, %%o5, %%g3\n\t"
+ "ldd [%2 + 0x00], %%o4\n\t"
+ "xor %%g4, %%l0, %%g4\n\t"
+ "xor %%g5, %%l1, %%g5\n\t"
+ "ldd [%2 + 0x08], %%l0\n\t"
+ "xor %%o0, %%l2, %%o0\n\t"
+ "xor %%o1, %%l3, %%o1\n\t"
+ "ldd [%2 + 0x10], %%l2\n\t"
+ "xor %%o2, %%l4, %%o2\n\t"
+ "xor %%o3, %%l5, %%o3\n\t"
+ "ldd [%2 + 0x18], %%l4\n\t"
+ "xor %%g2, %%o4, %%g2\n\t"
+ "xor %%g3, %%o5, %%g3\n\t"
+ "ldd [%3 + 0x00], %%o4\n\t"
+ "xor %%g4, %%l0, %%g4\n\t"
+ "xor %%g5, %%l1, %%g5\n\t"
+ "ldd [%3 + 0x08], %%l0\n\t"
+ "xor %%o0, %%l2, %%o0\n\t"
+ "xor %%o1, %%l3, %%o1\n\t"
+ "ldd [%3 + 0x10], %%l2\n\t"
+ "xor %%o2, %%l4, %%o2\n\t"
+ "xor %%o3, %%l5, %%o3\n\t"
+ "ldd [%3 + 0x18], %%l4\n\t"
+ "xor %%g2, %%o4, %%g2\n\t"
+ "xor %%g3, %%o5, %%g3\n\t"
+ "xor %%g4, %%l0, %%g4\n\t"
+ "xor %%g5, %%l1, %%g5\n\t"
+ "xor %%o0, %%l2, %%o0\n\t"
+ "xor %%o1, %%l3, %%o1\n\t"
+ "xor %%o2, %%l4, %%o2\n\t"
+ "xor %%o3, %%l5, %%o3\n\t"
+ "std %%g2, [%0 + 0x00]\n\t"
+ "std %%g4, [%0 + 0x08]\n\t"
+ "std %%o0, [%0 + 0x10]\n\t"
+ "std %%o2, [%0 + 0x18]\n"
+ :
+ : "r" (p1), "r" (p2), "r" (p3), "r" (p4)
+ : "g2", "g3", "g4", "g5",
+ "o0", "o1", "o2", "o3", "o4", "o5",
+ "l0", "l1", "l2", "l3", "l4", "l5");
+ p1 += 8;
+ p2 += 8;
+ p3 += 8;
+ p4 += 8;
+ } while (--lines > 0);
+}
+
+static void
+sparc_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+ unsigned long *p3, unsigned long *p4, unsigned long *p5)
+{
+ int lines = bytes / (sizeof (long)) / 8;
+
+ do {
+ __asm__ __volatile__(
+ "ldd [%0 + 0x00], %%g2\n\t"
+ "ldd [%0 + 0x08], %%g4\n\t"
+ "ldd [%0 + 0x10], %%o0\n\t"
+ "ldd [%0 + 0x18], %%o2\n\t"
+ "ldd [%1 + 0x00], %%o4\n\t"
+ "ldd [%1 + 0x08], %%l0\n\t"
+ "ldd [%1 + 0x10], %%l2\n\t"
+ "ldd [%1 + 0x18], %%l4\n\t"
+ "xor %%g2, %%o4, %%g2\n\t"
+ "xor %%g3, %%o5, %%g3\n\t"
+ "ldd [%2 + 0x00], %%o4\n\t"
+ "xor %%g4, %%l0, %%g4\n\t"
+ "xor %%g5, %%l1, %%g5\n\t"
+ "ldd [%2 + 0x08], %%l0\n\t"
+ "xor %%o0, %%l2, %%o0\n\t"
+ "xor %%o1, %%l3, %%o1\n\t"
+ "ldd [%2 + 0x10], %%l2\n\t"
+ "xor %%o2, %%l4, %%o2\n\t"
+ "xor %%o3, %%l5, %%o3\n\t"
+ "ldd [%2 + 0x18], %%l4\n\t"
+ "xor %%g2, %%o4, %%g2\n\t"
+ "xor %%g3, %%o5, %%g3\n\t"
+ "ldd [%3 + 0x00], %%o4\n\t"
+ "xor %%g4, %%l0, %%g4\n\t"
+ "xor %%g5, %%l1, %%g5\n\t"
+ "ldd [%3 + 0x08], %%l0\n\t"
+ "xor %%o0, %%l2, %%o0\n\t"
+ "xor %%o1, %%l3, %%o1\n\t"
+ "ldd [%3 + 0x10], %%l2\n\t"
+ "xor %%o2, %%l4, %%o2\n\t"
+ "xor %%o3, %%l5, %%o3\n\t"
+ "ldd [%3 + 0x18], %%l4\n\t"
+ "xor %%g2, %%o4, %%g2\n\t"
+ "xor %%g3, %%o5, %%g3\n\t"
+ "ldd [%4 + 0x00], %%o4\n\t"
+ "xor %%g4, %%l0, %%g4\n\t"
+ "xor %%g5, %%l1, %%g5\n\t"
+ "ldd [%4 + 0x08], %%l0\n\t"
+ "xor %%o0, %%l2, %%o0\n\t"
+ "xor %%o1, %%l3, %%o1\n\t"
+ "ldd [%4 + 0x10], %%l2\n\t"
+ "xor %%o2, %%l4, %%o2\n\t"
+ "xor %%o3, %%l5, %%o3\n\t"
+ "ldd [%4 + 0x18], %%l4\n\t"
+ "xor %%g2, %%o4, %%g2\n\t"
+ "xor %%g3, %%o5, %%g3\n\t"
+ "xor %%g4, %%l0, %%g4\n\t"
+ "xor %%g5, %%l1, %%g5\n\t"
+ "xor %%o0, %%l2, %%o0\n\t"
+ "xor %%o1, %%l3, %%o1\n\t"
+ "xor %%o2, %%l4, %%o2\n\t"
+ "xor %%o3, %%l5, %%o3\n\t"
+ "std %%g2, [%0 + 0x00]\n\t"
+ "std %%g4, [%0 + 0x08]\n\t"
+ "std %%o0, [%0 + 0x10]\n\t"
+ "std %%o2, [%0 + 0x18]\n"
+ :
+ : "r" (p1), "r" (p2), "r" (p3), "r" (p4), "r" (p5)
+ : "g2", "g3", "g4", "g5",
+ "o0", "o1", "o2", "o3", "o4", "o5",
+ "l0", "l1", "l2", "l3", "l4", "l5");
+ p1 += 8;
+ p2 += 8;
+ p3 += 8;
+ p4 += 8;
+ p5 += 8;
+ } while (--lines > 0);
+}
+
+static struct xor_block_template xor_block_SPARC = {
+ .name = "SPARC",
+ .do_2 = sparc_2,
+ .do_3 = sparc_3,
+ .do_4 = sparc_4,
+ .do_5 = sparc_5,
+};
+
+/* For grins, also test the generic routines. */
+#include <asm-generic/xor.h>
+
+#undef XOR_TRY_TEMPLATES
+#define XOR_TRY_TEMPLATES \
+ do { \
+ xor_speed(&xor_block_8regs); \
+ xor_speed(&xor_block_32regs); \
+ xor_speed(&xor_block_SPARC); \
+ } while (0)
--- /dev/null
+/*
+ * include/asm/xor.h
+ *
+ * High speed xor_block operation for RAID4/5 utilizing the
+ * UltraSparc Visual Instruction Set and Niagara block-init
+ * twin-load instructions.
+ *
+ * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
+ * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * (for example /usr/src/linux/COPYING); if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/spitfire.h>
+
+extern void xor_vis_2(unsigned long, unsigned long *, unsigned long *);
+extern void xor_vis_3(unsigned long, unsigned long *, unsigned long *,
+ unsigned long *);
+extern void xor_vis_4(unsigned long, unsigned long *, unsigned long *,
+ unsigned long *, unsigned long *);
+extern void xor_vis_5(unsigned long, unsigned long *, unsigned long *,
+ unsigned long *, unsigned long *, unsigned long *);
+
+/* XXX Ugh, write cheetah versions... -DaveM */
+
+static struct xor_block_template xor_block_VIS = {
+ .name = "VIS",
+ .do_2 = xor_vis_2,
+ .do_3 = xor_vis_3,
+ .do_4 = xor_vis_4,
+ .do_5 = xor_vis_5,
+};
+
+extern void xor_niagara_2(unsigned long, unsigned long *, unsigned long *);
+extern void xor_niagara_3(unsigned long, unsigned long *, unsigned long *,
+ unsigned long *);
+extern void xor_niagara_4(unsigned long, unsigned long *, unsigned long *,
+ unsigned long *, unsigned long *);
+extern void xor_niagara_5(unsigned long, unsigned long *, unsigned long *,
+ unsigned long *, unsigned long *, unsigned long *);
+
+static struct xor_block_template xor_block_niagara = {
+ .name = "Niagara",
+ .do_2 = xor_niagara_2,
+ .do_3 = xor_niagara_3,
+ .do_4 = xor_niagara_4,
+ .do_5 = xor_niagara_5,
+};
+
+#undef XOR_TRY_TEMPLATES
+#define XOR_TRY_TEMPLATES \
+ do { \
+ xor_speed(&xor_block_VIS); \
+ xor_speed(&xor_block_niagara); \
+ } while (0)
+
+/* For VIS for everything except Niagara. */
+#define XOR_SELECT_TEMPLATE(FASTEST) \
+ ((tlb_type == hypervisor && \
+ (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
+ sun4v_chip_type == SUN4V_CHIP_NIAGARA2)) ? \
+ &xor_block_niagara : \
+ &xor_block_VIS)
be 1f
nop
+ add %sp, STACKFRAME_SZ, %o0
call syscall_trace
- nop
+ mov 1, %o1
1:
/* We are returning to a signal handler. */
mov %i3, %o3
linux_syscall_trace:
+ add %sp, STACKFRAME_SZ, %o0
call syscall_trace
- nop
+ mov 0, %o1
+ cmp %o0, 0
+ bne 3f
+ mov -ENOSYS, %o0
mov %i0, %o0
mov %i1, %o1
mov %i2, %o2
call %l7
mov %i5, %o5
+3:
st %o0, [%sp + STACKFRAME_SZ + PT_I0]
ret_sys_call:
st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
linux_syscall_trace2:
+ add %sp, STACKFRAME_SZ, %o0
+ mov 1, %o1
call syscall_trace
add %l1, 0x4, %l2 /* npc = npc+4 */
st %l1, [%sp + STACKFRAME_SZ + PT_PC]
#include <linux/signal.h>
#include <linux/regset.h>
#include <linux/elf.h>
+#include <linux/tracehook.h>
#include <asm/pgtable.h>
#include <asm/system.h>
return ret;
}
-asmlinkage void syscall_trace(void)
+asmlinkage int syscall_trace(struct pt_regs *regs, int syscall_exit_p)
{
- if (!test_thread_flag(TIF_SYSCALL_TRACE))
- return;
- if (!(current->ptrace & PT_PTRACED))
- return;
- ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
- ? 0x80 : 0));
- /*
- * this isn't the same as continuing with a signal, but it will do
- * for normal use. strace only continues with a signal if the
- * stopping signal is not SIGTRAP. -brl
- */
- if (current->exit_code) {
- send_sig (current->exit_code, current, 1);
- current->exit_code = 0;
+ int ret = 0;
+
+ if (test_thread_flag(TIF_SYSCALL_TRACE)) {
+ if (syscall_exit_p)
+ tracehook_report_syscall_exit(regs, 0);
+ else
+ ret = tracehook_report_syscall_entry(regs);
}
+
+ return ret;
}
ld [%curptr + TI_FLAGS], %g2
signal_p:
- andcc %g2, (_TIF_SIGPENDING|_TIF_RESTORE_SIGMASK), %g0
+ andcc %g2, _TIF_DO_NOTIFY_RESUME_MASK, %g0
bz,a ret_trap_continue
ld [%sp + STACKFRAME_SZ + PT_PSR], %t_psr
+ mov %g2, %o2
mov %l5, %o1
- call do_signal
+ call do_notify_resume
add %sp, STACKFRAME_SZ, %o0 ! pt_regs ptr
/* Fall through. */
#include <linux/smp.h>
#include <linux/binfmts.h> /* do_coredum */
#include <linux/bitops.h>
+#include <linux/tracehook.h>
#include <asm/uaccess.h>
#include <asm/ptrace.h>
* want to handle. Thus you cannot kill init even with a SIGKILL even by
* mistake.
*/
-asmlinkage void do_signal(struct pt_regs * regs, unsigned long orig_i0)
+static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
{
struct k_sigaction ka;
int restart_syscall;
*/
if (test_thread_flag(TIF_RESTORE_SIGMASK))
clear_thread_flag(TIF_RESTORE_SIGMASK);
+
+ tracehook_signal_handler(signr, &info, &ka, regs, 0);
return;
}
if (restart_syscall &&
}
}
+void do_notify_resume(struct pt_regs *regs, unsigned long orig_i0,
+ unsigned long thread_info_flags)
+{
+ if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK))
+ do_signal(regs, orig_i0);
+ if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+ clear_thread_flag(TIF_NOTIFY_RESUME);
+ tracehook_notify_resume(regs);
+ }
+}
+
asmlinkage int
do_sys_sigstack(struct sigstack __user *ssptr, struct sigstack __user *ossptr,
unsigned long sp)
select HAVE_LMB
select HAVE_ARCH_KGDB
select USE_GENERIC_SMP_HELPERS if SMP
+ select HAVE_ARCH_TRACEHOOK
config GENERIC_TIME
bool
-#include <asm-sparc/unistd.h>
+#include <asm/unistd_32.h>
unsigned sparc32_dir_class[] = {
#include <asm-generic/audit_dir_write.h>
unsigned long orig_i0,
unsigned long thread_info_flags);
-extern asmlinkage void syscall_trace(struct pt_regs *regs,
- int syscall_exit_p);
+extern asmlinkage int syscall_trace(struct pt_regs *regs, int syscall_exit_p);
extern void bad_trap_tl1(struct pt_regs *regs, long lvl);
#include <linux/audit.h>
#include <linux/signal.h>
#include <linux/regset.h>
+#include <linux/tracehook.h>
#include <linux/compat.h>
#include <linux/elf.h>
return ret;
}
-asmlinkage void syscall_trace(struct pt_regs *regs, int syscall_exit_p)
+asmlinkage int syscall_trace(struct pt_regs *regs, int syscall_exit_p)
{
+ int ret = 0;
+
/* do the secure computing check first */
secure_computing(regs->u_regs[UREG_G1]);
audit_syscall_exit(result, regs->u_regs[UREG_I0]);
}
- if (!(current->ptrace & PT_PTRACED))
- goto out;
-
- if (!test_thread_flag(TIF_SYSCALL_TRACE))
- goto out;
-
- ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
- ? 0x80 : 0));
-
- /*
- * this isn't the same as continuing with a signal, but it will do
- * for normal use. strace only continues with a signal if the
- * stopping signal is not SIGTRAP. -brl
- */
- if (current->exit_code) {
- send_sig(current->exit_code, current, 1);
- current->exit_code = 0;
+ if (test_thread_flag(TIF_SYSCALL_TRACE)) {
+ if (syscall_exit_p)
+ tracehook_report_syscall_exit(regs, 0);
+ else
+ ret = tracehook_report_syscall_entry(regs);
}
-out:
- if (unlikely(current->audit_context) && !syscall_exit_p)
+ if (unlikely(current->audit_context) && !syscall_exit_p && !ret)
audit_syscall_entry((test_thread_flag(TIF_32BIT) ?
AUDIT_ARCH_SPARC :
AUDIT_ARCH_SPARC64),
regs->u_regs[UREG_I1],
regs->u_regs[UREG_I2],
regs->u_regs[UREG_I3]);
+
+ return ret;
}
wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
ldx [%g6 + TI_FLAGS], %l0
-1: andcc %l0, _TIF_SIGPENDING, %g0
+1: andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
be,pt %xcc, __handle_user_windows_continue
nop
mov %l5, %o1
wrpr %g0, RTRAP_PSTATE, %pstate
wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
ldx [%g6 + TI_FLAGS], %l0
-1: andcc %l0, _TIF_SIGPENDING, %g0
+1: andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
be,pt %xcc, __handle_perfctrs_continue
sethi %hi(TSTATE_PEF), %o0
andcc %l1, %o0, %g0
andcc %l0, _TIF_NEED_RESCHED, %g0
bne,pn %xcc, __handle_preemption
- andcc %l0, _TIF_SIGPENDING, %g0
+ andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
bne,pn %xcc, __handle_signal
__handle_signal_continue:
ldub [%g6 + TI_WSAVED], %o2
#include <linux/errno.h>
#include <linux/wait.h>
#include <linux/ptrace.h>
+#include <linux/tracehook.h>
#include <linux/unistd.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/binfmts.h>
#include <linux/bitops.h>
+#include <linux/tracehook.h>
#include <asm/uaccess.h>
#include <asm/ptrace.h>
* clear the TS_RESTORE_SIGMASK flag.
*/
current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
+
+ tracehook_signal_handler(signr, &info, &ka, regs, 0);
return;
}
if (restart_syscall &&
{
if (thread_info_flags & _TIF_SIGPENDING)
do_signal(regs, orig_i0);
+ if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+ clear_thread_flag(TIF_NOTIFY_RESUME);
+ tracehook_notify_resume(regs);
+ }
}
#include <linux/binfmts.h>
#include <linux/compat.h>
#include <linux/bitops.h>
+#include <linux/tracehook.h>
#include <asm/uaccess.h>
#include <asm/ptrace.h>
* clear the TS_RESTORE_SIGMASK flag.
*/
current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
+
+ tracehook_signal_handler(signr, &info, &ka, regs, 0);
return;
}
if (restart_syscall &&
add %sp, PTREGS_OFF, %o0
call syscall_trace
clr %o1
+ brnz,pn %o0, 3f
+ mov -ENOSYS, %o0
srl %i0, 0, %o0
srl %i4, 0, %o4
srl %i1, 0, %o1
add %sp, PTREGS_OFF, %o0
call syscall_trace
clr %o1
+ brnz,pn %o0, 3f
+ mov -ENOSYS, %o0
mov %i0, %o0
mov %i1, %o1
mov %i2, %o2
1:
#endif /* CONFIG_SMP */
jmp *(initial_code)
-.align 4
-ENTRY(initial_code)
- .long i386_start_kernel
/*
* We depend on ET to be correct. This checks for 287/387.
#endif
iret
+.section .cpuinit.data,"wa"
+.align 4
+ENTRY(initial_code)
+ .long i386_start_kernel
+
.section .text
/*
* Real beginning of normal "text" segment
if (!pr->flags.power_setup_done)
return -ENODEV;
- /* Fall back to the default idle loop */
- pm_idle = pm_idle_save;
- synchronize_sched(); /* Relies on interrupts forcing exit from idle. */
+ /*
+ * Fall back to the default idle loop, when pm_idle_save had
+ * been initialized.
+ */
+ if (pm_idle_save) {
+ pm_idle = pm_idle_save;
+ /* Relies on interrupts forcing exit from idle. */
+ synchronize_sched();
+ }
pr->flags.power = 0;
result = acpi_processor_get_power_info(pr);
/* Unregister the idle handler when processor #0 is removed. */
if (pr->id == 0) {
- pm_idle = pm_idle_save;
+ if (pm_idle_save)
+ pm_idle = pm_idle_save;
/*
* We are about to unload the current idle thread pm callback
irq = platform_get_irq(pdev, 0);
if (irq)
- set_irq_type(irq, IRQT_RISING);
+ set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
/* Setup expansion bus chip selects */
*data->cs0_cfg = data->cs0_bits;
/*
* Show whether the section of memory is likely to be hot-removable
*/
-static ssize_t show_mem_removable(struct sys_device *dev, char *buf)
+static ssize_t show_mem_removable(struct sys_device *dev,
+ struct sysdev_attribute *attr, char *buf)
{
unsigned long start_pfn;
int ret;
ssize_t ret;
if (flashdebug)
- printk(KERN_DEBUG "flash_read: flash_read: offset=0x%lX, "
- "buffer=%p, count=0x%X.\n", p, buf, count);
+ printk(KERN_DEBUG "flash_read: flash_read: offset=0x%llx, "
+ "buffer=%p, count=0x%zx.\n", *ppos, buf, size);
/*
* We now lock against reads and writes. --rmk
*/
if (mutex_lock_interruptible(&nwflash_mutex))
return -ERESTARTSYS;
- ret = simple_read_from_buffer(buf, size, ppos, FLASH_BASE, gbFlashSize);
+ ret = simple_read_from_buffer(buf, size, ppos, (void *)FLASH_BASE, gbFlashSize);
mutex_unlock(&nwflash_mutex);
return ret;
static void ipw_send_setup_packet(struct ipw_hardware *hw);
static void handle_received_SETUP_packet(struct ipw_hardware *ipw,
unsigned int address,
- unsigned char *data, int len,
+ const unsigned char *data, int len,
int is_last);
static void ipwireless_setup_timer(unsigned long data);
static void handle_received_CTRL_packet(struct ipw_hardware *hw,
- unsigned int channel_idx, unsigned char *data, int len);
+ unsigned int channel_idx, const unsigned char *data, int len);
/*#define TIMING_DIAGNOSTICS*/
timing_stats.last_report_time = jiffies;
if (!first)
printk(KERN_INFO IPWIRELESS_PCCARD_NAME
- ": %u us elapsed - read %lu bytes in %u us, "
- "wrote %lu bytes in %u us\n",
+ ": %u us elapsed - read %lu bytes in %u us, wrote %lu bytes in %u us\n",
jiffies_to_usecs(since),
timing_stats.read_bytes,
jiffies_to_usecs(timing_stats.read_time),
#define NL_FOLLOWING_PACKET_HEADER_SIZE 1
struct nl_first_packet_header {
-#if defined(__BIG_ENDIAN_BITFIELD)
- unsigned char packet_rank:2;
- unsigned char address:3;
- unsigned char protocol:3;
-#else
unsigned char protocol:3;
unsigned char address:3;
unsigned char packet_rank:2;
-#endif
unsigned char length_lsb;
unsigned char length_msb;
};
struct nl_packet_header {
-#if defined(__BIG_ENDIAN_BITFIELD)
- unsigned char packet_rank:2;
- unsigned char address:3;
- unsigned char protocol:3;
-#else
unsigned char protocol:3;
unsigned char address:3;
unsigned char packet_rank:2;
-#endif
};
/* Value of 'packet_rank' above */
unsigned short memreg_tx_new; /* TX2 (new) Register (R/W) */
};
-#define IODMADPR 0x00 /* DMA Data Port Register (R/W) */
-
#define CARD_PRESENT_VALUE (0xBEEFCAFEUL)
#define MEMTX_TX 0x0001
#define MEMRX_RX 0x0001
#define MEMRX_RX_DONE 0x0001
#define MEMRX_PCINTACKK 0x0001
-#define MEMRX_MEMSPURIOUSINT 0x0001
#define NL_NUM_OF_PRIORITIES 3
#define NL_NUM_OF_PROTOCOLS 3
unsigned int base_port;
short hw_version;
unsigned short ll_mtu;
- spinlock_t spinlock;
+ spinlock_t lock;
int initializing;
int init_loops;
length < DUMP_MAX_BYTES ? length : DUMP_MAX_BYTES);
}
-static int do_send_fragment(struct ipw_hardware *hw, const unsigned char *data,
+static void swap_packet_bitfield_to_le(unsigned char *data)
+{
+#ifdef __BIG_ENDIAN_BITFIELD
+ unsigned char tmp = *data, ret = 0;
+
+ /*
+ * transform bits from aa.bbb.ccc to ccc.bbb.aa
+ */
+ ret |= tmp & 0xc0 >> 6;
+ ret |= tmp & 0x38 >> 1;
+ ret |= tmp & 0x07 << 5;
+ *data = ret & 0xff;
+#endif
+}
+
+static void swap_packet_bitfield_from_le(unsigned char *data)
+{
+#ifdef __BIG_ENDIAN_BITFIELD
+ unsigned char tmp = *data, ret = 0;
+
+ /*
+ * transform bits from ccc.bbb.aa to aa.bbb.ccc
+ */
+ ret |= tmp & 0xe0 >> 5;
+ ret |= tmp & 0x1c << 1;
+ ret |= tmp & 0x03 << 6;
+ *data = ret & 0xff;
+#endif
+}
+
+static void do_send_fragment(struct ipw_hardware *hw, unsigned char *data,
unsigned length)
{
- int i;
+ unsigned i;
unsigned long flags;
start_timing();
-
- if (length == 0)
- return 0;
-
- if (length > hw->ll_mtu)
- return -1;
+ BUG_ON(length > hw->ll_mtu);
if (ipwireless_debug)
dump_data_bytes("send", data, length);
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
hw->tx_ready = 0;
+ swap_packet_bitfield_to_le(data);
if (hw->hw_version == HW_VERSION_1) {
outw((unsigned short) length, hw->base_port + IODWR);
unsigned short d = data[i];
__le16 raw_data;
- if (likely(i + 1 < length))
+ if (i + 1 < length)
d |= data[i + 1] << 8;
raw_data = cpu_to_le16(d);
outw(raw_data, hw->base_port + IODWR);
outw(DCR_TXDONE, hw->base_port + IODCR);
} else if (hw->hw_version == HW_VERSION_2) {
- outw((unsigned short) length, hw->base_port + IODMADPR);
+ outw((unsigned short) length, hw->base_port);
for (i = 0; i < length; i += 2) {
unsigned short d = data[i];
__le16 raw_data;
- if ((i + 1 < length))
+ if (i + 1 < length)
d |= data[i + 1] << 8;
raw_data = cpu_to_le16(d);
- outw(raw_data, hw->base_port + IODMADPR);
+ outw(raw_data, hw->base_port);
}
while ((i & 3) != 2) {
- outw((unsigned short) 0xDEAD, hw->base_port + IODMADPR);
+ outw((unsigned short) 0xDEAD, hw->base_port);
i += 2;
}
writew(MEMRX_RX, &hw->memory_info_regs->memreg_rx);
}
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
end_write_timing(length);
-
- return 0;
}
-static int do_send_packet(struct ipw_hardware *hw, struct ipw_tx_packet *packet)
+static void do_send_packet(struct ipw_hardware *hw, struct ipw_tx_packet *packet)
{
unsigned short fragment_data_len;
unsigned short data_left = packet->length - packet->offset;
if (data_left < fragment_data_len)
fragment_data_len = data_left;
+ /*
+ * hdr_first is now in machine bitfield order, which will be swapped
+ * to le just before it goes to hw
+ */
pkt.hdr_first.protocol = packet->protocol;
pkt.hdr_first.address = packet->dest_addr;
pkt.hdr_first.packet_rank = 0;
*/
unsigned long flags;
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
list_add(&packet->queue, &hw->tx_queue[0]);
hw->tx_queued++;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
} else {
if (packet->packet_callback)
packet->packet_callback(packet->callback_data,
packet->length);
kfree(packet);
}
-
- return 0;
}
static void ipw_setup_hardware(struct ipw_hardware *hw)
{
unsigned long flags;
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
if (hw->hw_version == HW_VERSION_1) {
/* Reset RX FIFO */
outw(DCR_RXRESET, hw->base_port + IODCR);
csr |= 1;
writew(csr, &hw->memregs_CCR->reg_config_and_status);
}
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
}
/*
if (!packet) {
unsigned long flags;
- /*
- * If this is the first fragment, then we will need to fetch a
- * packet to put it in.
- */
- spin_lock_irqsave(&hw->spinlock, flags);
- /* If we have one in our pool, then pull it out. */
+ spin_lock_irqsave(&hw->lock, flags);
if (!list_empty(&hw->rx_pool)) {
packet = list_first_entry(&hw->rx_pool,
struct ipw_rx_packet, queue);
- list_del(&packet->queue);
hw->rx_pool_size--;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
+ list_del(&packet->queue);
} else {
- /* Otherwise allocate a new one. */
- static int min_capacity = 256;
+ const int min_capacity =
+ ipwireless_ppp_mru(hw->network + 2);
int new_capacity;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
new_capacity =
- minimum_free_space > min_capacity
- ? minimum_free_space
- : min_capacity;
+ (minimum_free_space > min_capacity
+ ? minimum_free_space
+ : min_capacity);
packet = kmalloc(sizeof(struct ipw_rx_packet)
+ new_capacity, GFP_ATOMIC);
if (!packet)
packet->length = 0;
}
- /*
- * If this packet does not have sufficient capacity for the data we
- * want to add, then make it bigger.
- */
if (packet->length + minimum_free_space > packet->capacity) {
struct ipw_rx_packet *old_packet = packet;
kfree(packet);
else {
hw->rx_pool_size++;
- list_add_tail(&packet->queue, &hw->rx_pool);
+ list_add(&packet->queue, &hw->rx_pool);
}
}
static void queue_received_packet(struct ipw_hardware *hw,
- unsigned int protocol, unsigned int address,
- unsigned char *data, int length, int is_last)
+ unsigned int protocol,
+ unsigned int address,
+ const unsigned char *data, int length,
+ int is_last)
{
unsigned int channel_idx = address - 1;
struct ipw_rx_packet *packet = NULL;
packet = *assem;
*assem = NULL;
/* Count queued DATA bytes only */
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
hw->rx_bytes_queued += packet->length;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
}
} else {
/* If it's a CTRL packet, don't assemble, just queue it. */
* network layer.
*/
if (packet) {
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
list_add_tail(&packet->queue, &hw->rx_queue);
/* Block reception of incoming packets if queue is full. */
hw->blocking_rx =
- hw->rx_bytes_queued >= IPWIRELESS_RX_QUEUE_SIZE;
+ (hw->rx_bytes_queued >= IPWIRELESS_RX_QUEUE_SIZE);
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
schedule_work(&hw->work_rx);
}
}
container_of(work_rx, struct ipw_hardware, work_rx);
unsigned long flags;
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
while (!list_empty(&hw->rx_queue)) {
struct ipw_rx_packet *packet =
list_first_entry(&hw->rx_queue,
if (packet->protocol == TL_PROTOCOLID_COM_DATA) {
if (hw->network != NULL) {
/* If the network hasn't been disconnected. */
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
/*
* This must run unlocked due to tty processing
* and mutex locking
(unsigned char *)packet
+ sizeof(struct ipw_rx_packet),
packet->length);
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
}
/* Count queued DATA bytes only */
hw->rx_bytes_queued -= packet->length;
if (hw->shutting_down)
break;
}
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
}
static void handle_received_CTRL_packet(struct ipw_hardware *hw,
unsigned int channel_idx,
- unsigned char *data, int len)
+ const unsigned char *data, int len)
{
- struct ipw_control_packet_body *body =
- (struct ipw_control_packet_body *) data;
+ const struct ipw_control_packet_body *body =
+ (const struct ipw_control_packet_body *) data;
unsigned int changed_mask;
if (len != sizeof(struct ipw_control_packet_body)) {
}
static void handle_received_packet(struct ipw_hardware *hw,
- union nl_packet *packet,
+ const union nl_packet *packet,
unsigned short len)
{
unsigned int protocol = packet->hdr.protocol;
unsigned int address = packet->hdr.address;
unsigned int header_length;
- unsigned char *data;
+ const unsigned char *data;
unsigned int data_len;
int is_last = packet->hdr.packet_rank & NL_LAST_PACKET;
static void do_receive_packet(struct ipw_hardware *hw)
{
unsigned len;
- unsigned int i;
+ unsigned i;
unsigned char pkt[LL_MTU_MAX];
start_timing();
len = inw(hw->base_port + IODRR);
if (len > hw->ll_mtu) {
printk(KERN_INFO IPWIRELESS_PCCARD_NAME
- ": received a packet of %u bytes - "
- "longer than the MTU!\n", len);
+ ": received a packet of %u bytes - longer than the MTU!\n", len);
outw(DCR_RXDONE | DCR_RXRESET, hw->base_port + IODCR);
return;
}
pkt[i + 1] = (unsigned char) (data >> 8);
}
} else {
- len = inw(hw->base_port + IODMADPR);
+ len = inw(hw->base_port);
if (len > hw->ll_mtu) {
printk(KERN_INFO IPWIRELESS_PCCARD_NAME
- ": received a packet of %u bytes - "
- "longer than the MTU!\n", len);
+ ": received a packet of %u bytes - longer than the MTU!\n", len);
writew(MEMRX_PCINTACKK,
&hw->memory_info_regs->memreg_pc_interrupt_ack);
return;
}
for (i = 0; i < len; i += 2) {
- __le16 raw_data = inw(hw->base_port + IODMADPR);
+ __le16 raw_data = inw(hw->base_port);
unsigned short data = le16_to_cpu(raw_data);
pkt[i] = (unsigned char) data;
}
while ((i & 3) != 2) {
- inw(hw->base_port + IODMADPR);
+ inw(hw->base_port);
i += 2;
}
}
acknowledge_data_read(hw);
+ swap_packet_bitfield_from_le(pkt);
+
if (ipwireless_debug)
dump_data_bytes("recv", pkt, len);
* until setup is complete.
*/
return (hw->to_setup || hw->initializing
- ? PRIO_SETUP + 1 :
- NL_NUM_OF_PRIORITIES);
+ ? PRIO_SETUP + 1 : NL_NUM_OF_PRIORITIES);
}
/*
int received = 0;
unsigned long flags;
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
while (hw->rx_ready && !hw->blocking_rx) {
received = 1;
hw->rx_ready--;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
do_receive_packet(hw);
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
}
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
return received;
}
int more_to_send = 0;
unsigned long flags;
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
if (hw->tx_queued && hw->tx_ready) {
int priority;
struct ipw_tx_packet *packet = NULL;
}
if (!packet) {
hw->tx_queued = 0;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
return 0;
}
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
/* Send */
do_send_packet(hw, packet);
/* Check if more to send */
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
for (priority = 0; priority < priority_limit; priority++)
if (!list_empty(&hw->tx_queue[priority])) {
more_to_send = 1;
if (!more_to_send)
hw->tx_queued = 0;
}
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
return more_to_send;
}
struct ipw_hardware *hw = (struct ipw_hardware *) hw_;
unsigned long flags;
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
if (hw->shutting_down) {
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
return;
}
* Initial setup data sent to hardware
*/
hw->to_setup = 2;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
ipw_setup_hardware(hw);
ipw_send_setup_packet(hw);
int priority_limit = get_current_packet_priority(hw);
int again;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
do {
again = send_pending_packet(hw, priority_limit);
/* Transmit complete. */
if (irqn & IR_TXINTR) {
ack |= IR_TXINTR;
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
hw->tx_ready = 1;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
}
/* Received data */
if (irqn & IR_RXINTR) {
ack |= IR_RXINTR;
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
hw->rx_ready++;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
}
if (ack != 0) {
outw(ack, hw->base_port + IOIR);
} else {
return IRQ_NONE;
}
- } else {
+ } else
return IRQ_NONE;
- }
}
/*
if (hw->serial_number_detected) {
if (memtx_serial != hw->last_memtx_serial) {
hw->last_memtx_serial = memtx_serial;
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
hw->rx_ready++;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
rx = 1;
} else
/* Ignore 'Timer Recovery' duplicates. */
printk(KERN_DEBUG IPWIRELESS_PCCARD_NAME
": memreg_tx serial num detected\n");
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
hw->rx_ready++;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
}
rx = 1;
}
}
if (memrxdone & MEMRX_RX_DONE) {
writew(0, &hw->memory_info_regs->memreg_rx_done);
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
hw->tx_ready = 1;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
tx = 1;
}
if (tx)
": spurious interrupt - new_tx mode\n");
else {
printk(KERN_WARNING IPWIRELESS_PCCARD_NAME
- ": no valid memreg_tx value - "
- "switching to the old memreg_tx\n");
+ ": no valid memreg_tx value - switching to the old memreg_tx\n");
hw->memreg_tx =
&hw->memory_info_regs->memreg_tx_old;
try_mem_tx_old = 1;
return IRQ_HANDLED;
}
-irqreturn_t ipwireless_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+irqreturn_t ipwireless_interrupt(int irq, void *dev_id)
{
struct ipw_hardware *hw = dev_id;
int priority_limit;
unsigned long flags;
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
priority_limit = get_current_packet_priority(hw);
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
while (send_pending_packet(hw, priority_limit));
}
{
unsigned long flags;
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
list_add_tail(&packet->queue, &hw->tx_queue[priority]);
hw->tx_queued++;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
flush_packets_to_hw(hw);
}
}
int ipwireless_send_packet(struct ipw_hardware *hw, unsigned int channel_idx,
- unsigned char *data, unsigned int length,
+ const unsigned char *data, unsigned int length,
void (*callback) (void *cb, unsigned int length),
void *callback_data)
{
struct ipw_tx_packet *packet;
- packet = alloc_data_packet(length,
- (unsigned char) (channel_idx + 1),
- TL_PROTOCOLID_COM_DATA);
+ packet = alloc_data_packet(length, (channel_idx + 1),
+ TL_PROTOCOLID_COM_DATA);
if (!packet)
return -ENOMEM;
packet->packet_callback = callback;
packet->callback_data = callback_data;
- memcpy((unsigned char *) packet +
- sizeof(struct ipw_tx_packet), data, length);
+ memcpy((unsigned char *) packet + sizeof(struct ipw_tx_packet), data,
+ length);
send_packet(hw, PRIO_DATA, packet);
return 0;
protocolid = TL_PROTOCOLID_SETUP;
packet = alloc_ctrl_packet(sizeof(struct ipw_control_packet),
- (unsigned char) (channel_idx + 1),
- protocolid, line);
+ (channel_idx + 1), protocolid, line);
if (!packet)
return -ENOMEM;
packet->header.length = sizeof(struct ipw_control_packet_body);
- packet->body.value = (unsigned char) (state == 0 ? 0 : 1);
+ packet->body.value = (state == 0 ? 0 : 1);
send_packet(hw, prio, &packet->header);
return 0;
}
if (vers_no == TL_SETUP_VERSION)
__handle_setup_get_version_rsp(hw);
else
- printk(KERN_ERR
- IPWIRELESS_PCCARD_NAME
+ printk(KERN_ERR IPWIRELESS_PCCARD_NAME
": invalid hardware version no %u\n",
(unsigned int) vers_no);
}
static void handle_received_SETUP_packet(struct ipw_hardware *hw,
unsigned int address,
- unsigned char *data, int len,
+ const unsigned char *data, int len,
int is_last)
{
- union ipw_setup_rx_msg *rx_msg = (union ipw_setup_rx_msg *) data;
+ const union ipw_setup_rx_msg *rx_msg = (const union ipw_setup_rx_msg *) data;
if (address != ADDR_SETUP_PROT) {
printk(KERN_INFO IPWIRELESS_PCCARD_NAME
INIT_LIST_HEAD(&hw->rx_queue);
INIT_LIST_HEAD(&hw->rx_pool);
- spin_lock_init(&hw->spinlock);
+ spin_lock_init(&hw->lock);
tasklet_init(&hw->tasklet, ipwireless_do_tasklet, (unsigned long) hw);
INIT_WORK(&hw->work_rx, ipw_receive_data_work);
setup_timer(&hw->setup_timer, ipwireless_setup_timer,
enable_irq(hw->irq);
}
hw->base_port = base_port;
- hw->hw_version = is_v2_card ? HW_VERSION_2 : HW_VERSION_1;
- hw->ll_mtu = hw->hw_version == HW_VERSION_1 ? LL_MTU_V1 : LL_MTU_V2;
+ hw->hw_version = (is_v2_card ? HW_VERSION_2 : HW_VERSION_1);
+ hw->ll_mtu = (hw->hw_version == HW_VERSION_1 ? LL_MTU_V1 : LL_MTU_V2);
hw->memregs_CCR = (struct MEMCCR __iomem *)
((unsigned short __iomem *) attr_memory + 0x200);
hw->memory_info_regs = (struct MEMINFREG __iomem *) common_memory;
if (is_card_present(hw)) {
unsigned long flags;
- spin_lock_irqsave(&hw->spinlock, flags);
+ spin_lock_irqsave(&hw->lock, flags);
hw->to_setup = 1;
hw->tx_ready = 1;
- spin_unlock_irqrestore(&hw->spinlock, flags);
+ spin_unlock_irqrestore(&hw->lock, flags);
tasklet_schedule(&hw->tasklet);
}
struct ipw_hardware *ipwireless_hardware_create(void);
void ipwireless_hardware_free(struct ipw_hardware *hw);
-irqreturn_t ipwireless_interrupt(int irq, void *dev_id, struct pt_regs *regs);
+irqreturn_t ipwireless_interrupt(int irq, void *dev_id);
int ipwireless_set_DTR(struct ipw_hardware *hw, unsigned int channel_idx,
int state);
int ipwireless_set_RTS(struct ipw_hardware *hw, unsigned int channel_idx,
int state);
int ipwireless_send_packet(struct ipw_hardware *hw,
unsigned int channel_idx,
- unsigned char *data,
+ const unsigned char *data,
unsigned int length,
void (*packet_sent_callback) (void *cb,
unsigned int length),
/* Debug mode: more verbose, print sent/recv bytes */
int ipwireless_debug;
int ipwireless_loopback;
-int ipwireless_out_queue = 1;
+int ipwireless_out_queue = 10;
module_param_named(debug, ipwireless_debug, int, 0);
module_param_named(loopback, ipwireless_loopback, int, 0);
MODULE_PARM_DESC(debug, "switch on debug messages [0]");
MODULE_PARM_DESC(loopback,
"debug: enable ras_raw channel [0]");
-MODULE_PARM_DESC(out_queue, "debug: set size of outgoing queue [1]");
+MODULE_PARM_DESC(out_queue, "debug: set size of outgoing PPP queue [10]");
/* Executes in process context. */
static void signalled_reboot_work(struct work_struct *work_reboot)
unsigned short buf[64];
cisparse_t parse;
unsigned short cor_value;
- win_req_t request_attr_memory;
- win_req_t request_common_memory;
memreq_t memreq_attr_memory;
memreq_t memreq_common_memory;
goto exit0;
}
+ request_region(link->io.BasePort1, link->io.NumPorts1,
+ IPWIRELESS_PCCARD_NAME);
+
/* memory settings */
tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
}
if (parse.cftable_entry.mem.nwin > 0) {
- request_common_memory.Attributes =
+ ipw->request_common_memory.Attributes =
WIN_DATA_WIDTH_16 | WIN_MEMORY_TYPE_CM | WIN_ENABLE;
- request_common_memory.Base =
+ ipw->request_common_memory.Base =
parse.cftable_entry.mem.win[0].host_addr;
- request_common_memory.Size = parse.cftable_entry.mem.win[0].len;
- if (request_common_memory.Size < 0x1000)
- request_common_memory.Size = 0x1000;
- request_common_memory.AccessSpeed = 0;
+ ipw->request_common_memory.Size = parse.cftable_entry.mem.win[0].len;
+ if (ipw->request_common_memory.Size < 0x1000)
+ ipw->request_common_memory.Size = 0x1000;
+ ipw->request_common_memory.AccessSpeed = 0;
- ret = pcmcia_request_window(&link, &request_common_memory,
+ ret = pcmcia_request_window(&link, &ipw->request_common_memory,
&ipw->handle_common_memory);
if (ret != CS_SUCCESS) {
ipw->is_v2_card =
parse.cftable_entry.mem.win[0].len == 0x100;
- ipw->common_memory = ioremap(request_common_memory.Base,
- request_common_memory.Size);
+ ipw->common_memory = ioremap(ipw->request_common_memory.Base,
+ ipw->request_common_memory.Size);
+ request_mem_region(ipw->request_common_memory.Base,
+ ipw->request_common_memory.Size, IPWIRELESS_PCCARD_NAME);
- request_attr_memory.Attributes =
+ ipw->request_attr_memory.Attributes =
WIN_DATA_WIDTH_16 | WIN_MEMORY_TYPE_AM | WIN_ENABLE;
- request_attr_memory.Base = 0;
- request_attr_memory.Size = 0; /* this used to be 0x1000 */
- request_attr_memory.AccessSpeed = 0;
+ ipw->request_attr_memory.Base = 0;
+ ipw->request_attr_memory.Size = 0; /* this used to be 0x1000 */
+ ipw->request_attr_memory.AccessSpeed = 0;
- ret = pcmcia_request_window(&link, &request_attr_memory,
+ ret = pcmcia_request_window(&link, &ipw->request_attr_memory,
&ipw->handle_attr_memory);
if (ret != CS_SUCCESS) {
goto exit2;
}
- ipw->attr_memory = ioremap(request_attr_memory.Base,
- request_attr_memory.Size);
+ ipw->attr_memory = ioremap(ipw->request_attr_memory.Base,
+ ipw->request_attr_memory.Size);
+ request_mem_region(ipw->request_attr_memory.Base, ipw->request_attr_memory.Size,
+ IPWIRELESS_PCCARD_NAME);
}
INIT_WORK(&ipw->work_reboot, signalled_reboot_work);
(unsigned int) link->irq.AssignedIRQ);
if (ipw->attr_memory && ipw->common_memory)
printk(KERN_INFO IPWIRELESS_PCCARD_NAME
- ": attr memory 0x%08lx-0x%08lx, "
- "common memory 0x%08lx-0x%08lx\n",
- request_attr_memory.Base,
- request_attr_memory.Base
- + request_attr_memory.Size - 1,
- request_common_memory.Base,
- request_common_memory.Base
- + request_common_memory.Size - 1);
+ ": attr memory 0x%08lx-0x%08lx, common memory 0x%08lx-0x%08lx\n",
+ ipw->request_attr_memory.Base,
+ ipw->request_attr_memory.Base
+ + ipw->request_attr_memory.Size - 1,
+ ipw->request_common_memory.Base,
+ ipw->request_common_memory.Base
+ + ipw->request_common_memory.Size - 1);
ipw->network = ipwireless_network_create(ipw->hardware);
if (!ipw->network)
pcmcia_disable_device(link);
exit3:
if (ipw->attr_memory) {
+ release_mem_region(ipw->request_attr_memory.Base,
+ ipw->request_attr_memory.Size);
iounmap(ipw->attr_memory);
pcmcia_release_window(ipw->handle_attr_memory);
pcmcia_disable_device(link);
}
exit2:
if (ipw->common_memory) {
+ release_mem_region(ipw->request_common_memory.Base,
+ ipw->request_common_memory.Size);
iounmap(ipw->common_memory);
pcmcia_release_window(ipw->handle_common_memory);
}
static void release_ipwireless(struct ipw_dev *ipw)
{
- struct pcmcia_device *link = ipw->link;
-
- pcmcia_disable_device(link);
+ pcmcia_disable_device(ipw->link);
- if (ipw->common_memory)
+ if (ipw->common_memory) {
+ release_mem_region(ipw->request_common_memory.Base,
+ ipw->request_common_memory.Size);
iounmap(ipw->common_memory);
- if (ipw->attr_memory)
+ }
+ if (ipw->attr_memory) {
+ release_mem_region(ipw->request_attr_memory.Base,
+ ipw->request_attr_memory.Size);
iounmap(ipw->attr_memory);
+ }
if (ipw->common_memory)
pcmcia_release_window(ipw->handle_common_memory);
if (ipw->attr_memory)
pcmcia_release_window(ipw->handle_attr_memory);
- pcmcia_disable_device(link);
+
+ /* Break the link with Card Services */
+ pcmcia_disable_device(ipw->link);
}
/*
release_ipwireless(ipw);
- /* Break the link with Card Services */
- if (link)
- pcmcia_disable_device(link);
-
if (ipw->tty != NULL)
ipwireless_tty_free(ipw->tty);
if (ipw->network != NULL)
struct ipw_dev {
struct pcmcia_device *link;
int is_v2_card;
+
window_handle_t handle_attr_memory;
void __iomem *attr_memory;
+ win_req_t request_attr_memory;
+
window_handle_t handle_common_memory;
void __iomem *common_memory;
+ win_req_t request_common_memory;
+
dev_node_t nodes[2];
/* Reference to attribute memory, containing CIS data */
void *attribute_memory;
#include "main.h"
#include "tty.h"
-#define MAX_OUTGOING_PACKETS_QUEUED ipwireless_out_queue
#define MAX_ASSOCIATED_TTYS 2
#define SC_RCV_BITS (SC_RCV_B7_1|SC_RCV_B7_0|SC_RCV_ODDP|SC_RCV_EVNP)
/* Number of packets queued up in hardware module. */
int outgoing_packets_queued;
/* Spinlock to avoid interrupts during shutdown */
- spinlock_t spinlock;
+ spinlock_t lock;
struct mutex close_lock;
/* PPP ioctl data, not actually used anywere */
struct ipw_network *network = callback_data;
unsigned long flags;
- spin_lock_irqsave(&network->spinlock, flags);
+ spin_lock_irqsave(&network->lock, flags);
network->outgoing_packets_queued--;
if (network->ppp_channel != NULL) {
if (network->ppp_blocked) {
network->ppp_blocked = 0;
- spin_unlock_irqrestore(&network->spinlock, flags);
+ spin_unlock_irqrestore(&network->lock, flags);
ppp_output_wakeup(network->ppp_channel);
if (ipwireless_debug)
- printk(KERN_INFO IPWIRELESS_PCCARD_NAME
+ printk(KERN_DEBUG IPWIRELESS_PCCARD_NAME
": ppp unblocked\n");
} else
- spin_unlock_irqrestore(&network->spinlock, flags);
+ spin_unlock_irqrestore(&network->lock, flags);
} else
- spin_unlock_irqrestore(&network->spinlock, flags);
+ spin_unlock_irqrestore(&network->lock, flags);
}
/*
struct ipw_network *network = ppp_channel->private;
unsigned long flags;
- spin_lock_irqsave(&network->spinlock, flags);
- if (network->outgoing_packets_queued < MAX_OUTGOING_PACKETS_QUEUED) {
+ spin_lock_irqsave(&network->lock, flags);
+ if (network->outgoing_packets_queued < ipwireless_out_queue) {
unsigned char *buf;
static unsigned char header[] = {
PPP_ALLSTATIONS, /* 0xff */
int ret;
network->outgoing_packets_queued++;
- spin_unlock_irqrestore(&network->spinlock, flags);
+ spin_unlock_irqrestore(&network->lock, flags);
/*
* If we have the requested amount of headroom in the skb we
* needs to be unblocked once we are ready to send.
*/
network->ppp_blocked = 1;
- spin_unlock_irqrestore(&network->spinlock, flags);
+ spin_unlock_irqrestore(&network->lock, flags);
+ if (ipwireless_debug)
+ printk(KERN_DEBUG IPWIRELESS_PCCARD_NAME ": ppp blocked\n");
return 0;
}
}
work_go_online);
unsigned long flags;
- spin_lock_irqsave(&network->spinlock, flags);
+ spin_lock_irqsave(&network->lock, flags);
if (!network->ppp_channel) {
struct ppp_channel *channel;
- spin_unlock_irqrestore(&network->spinlock, flags);
+ spin_unlock_irqrestore(&network->lock, flags);
channel = kzalloc(sizeof(struct ppp_channel), GFP_KERNEL);
if (!channel) {
printk(KERN_ERR IPWIRELESS_PCCARD_NAME
network->xaccm[3] = 0x60000000U;
network->raccm = ~0U;
ppp_register_channel(channel);
- spin_lock_irqsave(&network->spinlock, flags);
+ spin_lock_irqsave(&network->lock, flags);
network->ppp_channel = channel;
}
- spin_unlock_irqrestore(&network->spinlock, flags);
+ spin_unlock_irqrestore(&network->lock, flags);
}
static void do_go_offline(struct work_struct *work_go_offline)
unsigned long flags;
mutex_lock(&network->close_lock);
- spin_lock_irqsave(&network->spinlock, flags);
+ spin_lock_irqsave(&network->lock, flags);
if (network->ppp_channel != NULL) {
struct ppp_channel *channel = network->ppp_channel;
network->ppp_channel = NULL;
- spin_unlock_irqrestore(&network->spinlock, flags);
+ spin_unlock_irqrestore(&network->lock, flags);
mutex_unlock(&network->close_lock);
ppp_unregister_channel(channel);
} else {
- spin_unlock_irqrestore(&network->spinlock, flags);
+ spin_unlock_irqrestore(&network->lock, flags);
mutex_unlock(&network->close_lock);
}
}
* the PPP layer.
*/
mutex_lock(&network->close_lock);
- spin_lock_irqsave(&network->spinlock, flags);
+ spin_lock_irqsave(&network->lock, flags);
if (network->ppp_channel != NULL) {
struct sk_buff *skb;
- spin_unlock_irqrestore(&network->spinlock,
+ spin_unlock_irqrestore(&network->lock,
flags);
/* Send the data to the ppp_generic module. */
skb = ipw_packet_received_skb(data, length);
ppp_input(network->ppp_channel, skb);
} else
- spin_unlock_irqrestore(&network->spinlock,
+ spin_unlock_irqrestore(&network->lock,
flags);
mutex_unlock(&network->close_lock);
}
if (!network)
return NULL;
- spin_lock_init(&network->spinlock);
+ spin_lock_init(&network->lock);
mutex_init(&network->close_lock);
network->hardware = hw;
int ret = -1;
unsigned long flags;
- spin_lock_irqsave(&network->spinlock, flags);
+ spin_lock_irqsave(&network->lock, flags);
if (network->ppp_channel != NULL)
ret = ppp_channel_index(network->ppp_channel);
- spin_unlock_irqrestore(&network->spinlock, flags);
+ spin_unlock_irqrestore(&network->lock, flags);
return ret;
}
int ret = -1;
unsigned long flags;
- spin_lock_irqsave(&network->spinlock, flags);
+ spin_lock_irqsave(&network->lock, flags);
if (network->ppp_channel != NULL)
ret = ppp_unit_number(network->ppp_channel);
- spin_unlock_irqrestore(&network->spinlock, flags);
+ spin_unlock_irqrestore(&network->lock, flags);
return ret;
}
+
+int ipwireless_ppp_mru(const struct ipw_network *network)
+{
+ return network->mru;
+}
void ipwireless_ppp_close(struct ipw_network *net);
int ipwireless_ppp_channel_index(struct ipw_network *net);
int ipwireless_ppp_unit_number(struct ipw_network *net);
+int ipwireless_ppp_mru(const struct ipw_network *net);
#endif
}
ret = ipwireless_send_packet(tty->hardware, IPW_CHANNEL_RAS,
- (unsigned char *) buf, count,
+ buf, count,
ipw_write_packet_sent_callback, tty);
if (ret == -1) {
mutex_unlock(&tty->ipw_tty_mutex);
*/
void cpuidle_uninstall_idle_handler(void)
{
- if (enabled_devices && (pm_idle != pm_idle_old)) {
+ if (enabled_devices && pm_idle_old && (pm_idle != pm_idle_old)) {
pm_idle = pm_idle_old;
cpuidle_kick_cpus();
}
struct i2c_msg *pmsg;
int msg_num;
int cur_msg;
+ u16 saved_clkdiv;
+ u16 saved_control;
void __iomem *regs_base;
};
I2C_FUNC_I2C;
}
-
static struct i2c_algorithm bfin_twi_algorithm = {
.master_xfer = bfin_twi_master_xfer,
.smbus_xfer = bfin_twi_smbus_xfer,
.functionality = bfin_twi_functionality,
};
-
-static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state)
+static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
{
- struct bfin_twi_iface *iface = platform_get_drvdata(dev);
+ struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
+
+ iface->saved_clkdiv = read_CLKDIV(iface);
+ iface->saved_control = read_CONTROL(iface);
+
+ free_irq(iface->irq, iface);
/* Disable TWI */
- write_CONTROL(iface, read_CONTROL(iface) & ~TWI_ENA);
- SSYNC();
+ write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
return 0;
}
-static int i2c_bfin_twi_resume(struct platform_device *dev)
+static int i2c_bfin_twi_resume(struct platform_device *pdev)
{
- struct bfin_twi_iface *iface = platform_get_drvdata(dev);
+ struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
- /* Enable TWI */
- write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
- SSYNC();
+ int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
+ IRQF_DISABLED, pdev->name, iface);
+ if (rc) {
+ dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
+ return -ENODEV;
+ }
+
+ /* Resume TWI interface clock as specified */
+ write_CLKDIV(iface, iface->saved_clkdiv);
+
+ /* Resume TWI */
+ write_CONTROL(iface, iface->saved_control);
return 0;
}
return gpio_get_value(pdata->scl_pin);
}
-static int __init i2c_gpio_probe(struct platform_device *pdev)
+static int __devinit i2c_gpio_probe(struct platform_device *pdev)
{
struct i2c_gpio_platform_data *pdata;
struct i2c_algo_bit_data *bit_data;
return ret;
}
-static int __exit i2c_gpio_remove(struct platform_device *pdev)
+static int __devexit i2c_gpio_remove(struct platform_device *pdev)
{
struct i2c_gpio_platform_data *pdata;
struct i2c_adapter *adap;
.name = "i2c-gpio",
.owner = THIS_MODULE,
},
- .remove = __exit_p(i2c_gpio_remove),
+ .probe = i2c_gpio_probe,
+ .remove = __devexit_p(i2c_gpio_remove),
};
static int __init i2c_gpio_init(void)
{
int ret;
- ret = platform_driver_probe(&i2c_gpio_driver, i2c_gpio_probe);
+ ret = platform_driver_register(&i2c_gpio_driver);
if (ret)
printk(KERN_ERR "i2c-gpio: probe failed: %d\n", ret);
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
+#include <linux/cpufreq.h>
#include <asm/hardware.h>
#include <asm/irq.h>
unsigned int tx_setup;
enum s3c24xx_i2c_state state;
+ unsigned long clkrate;
void __iomem *regs;
struct clk *clk;
struct resource *irq;
struct resource *ioarea;
struct i2c_adapter adap;
+
+#ifdef CONFIG_CPU_FREQ
+ struct notifier_block freq_transition;
+#endif
};
/* default platform data to use if not supplied in the platform_device
unsigned long timeout;
int ret;
+ if (!readl(i2c->regs + S3C2410_IICCON) & S3C2410_IICCON_IRQEN)
+ return -EIO;
+
ret = s3c24xx_i2c_set_master(i2c);
if (ret != 0) {
dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
return (diff >= -2 && diff <= 2);
}
-/* s3c24xx_i2c_getdivisor
+/* s3c24xx_i2c_clockrate
*
* work out a divisor for the user requested frequency setting,
* either by the requested frequency, or scanning the acceptable
* range of frequencies until something is found
*/
-static int s3c24xx_i2c_getdivisor(struct s3c24xx_i2c *i2c,
- struct s3c2410_platform_i2c *pdata,
- unsigned long *iicon,
- unsigned int *got)
+static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
{
+ struct s3c2410_platform_i2c *pdata;
unsigned long clkin = clk_get_rate(i2c->clk);
-
unsigned int divs, div1;
+ u32 iiccon;
int freq;
int start, end;
+ i2c->clkrate = clkin;
+
+ pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
clkin /= 1000; /* clkin now in KHz */
- dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
+ dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
if (pdata->bus_freq != 0) {
found:
*got = freq;
- *iicon |= (divs-1);
- *iicon |= (div1 == 512) ? S3C2410_IICCON_TXDIV_512 : 0;
+
+ iiccon = readl(i2c->regs + S3C2410_IICCON);
+ iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
+ iiccon |= (divs-1);
+
+ if (div1 == 512)
+ iiccon |= S3C2410_IICCON_TXDIV_512;
+
+ writel(iiccon, i2c->regs + S3C2410_IICCON);
+
+ return 0;
+}
+
+#ifdef CONFIG_CPU_FREQ
+
+#define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
+
+static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
+ unsigned long val, void *data)
+{
+ struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
+ unsigned long flags;
+ unsigned int got;
+ int delta_f;
+ int ret;
+
+ delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
+
+ /* if we're post-change and the input clock has slowed down
+ * or at pre-change and the clock is about to speed up, then
+ * adjust our clock rate. <0 is slow, >0 speedup.
+ */
+
+ if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
+ (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
+ spin_lock_irqsave(&i2c->lock, flags);
+ ret = s3c24xx_i2c_clockrate(i2c, &got);
+ spin_unlock_irqrestore(&i2c->lock, flags);
+
+ if (ret < 0)
+ dev_err(i2c->dev, "cannot find frequency\n");
+ else
+ dev_info(i2c->dev, "setting freq %d\n", got);
+ }
+
+ return 0;
+}
+
+static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
+{
+ i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
+
+ return cpufreq_register_notifier(&i2c->freq_transition,
+ CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
+{
+ cpufreq_unregister_notifier(&i2c->freq_transition,
+ CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+#else
+static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
+{
return 0;
}
+static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
+{
+}
+#endif
+
/* s3c24xx_i2c_init
*
* initialise the controller, set the IO lines and frequency
dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
+ writel(iicon, i2c->regs + S3C2410_IICCON);
+
/* we need to work out the divisors for the clock... */
- if (s3c24xx_i2c_getdivisor(i2c, pdata, &iicon, &freq) != 0) {
+ if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
+ writel(0, i2c->regs + S3C2410_IICCON);
dev_err(i2c->dev, "cannot meet bus frequency required\n");
return -EINVAL;
}
dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
-
- writel(iicon, i2c->regs + S3C2410_IICCON);
/* check for s3c2440 i2c controller */
static int s3c24xx_i2c_probe(struct platform_device *pdev)
{
struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
+ struct s3c2410_platform_i2c *pdata;
struct resource *res;
int ret;
+ pdata = s3c24xx_i2c_get_platformdata(&pdev->dev);
+
/* find the clock and enable it */
i2c->dev = &pdev->dev;
dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res,
(unsigned long)res->start);
- ret = i2c_add_adapter(&i2c->adap);
+ ret = s3c24xx_i2c_register_cpufreq(i2c);
if (ret < 0) {
- dev_err(&pdev->dev, "failed to add bus to i2c core\n");
+ dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
goto err_irq;
}
+ /* Note, previous versions of the driver used i2c_add_adapter()
+ * to add the bus at any number. We now pass the bus number via
+ * the platform data, so if unset it will now default to always
+ * being bus 0.
+ */
+
+ i2c->adap.nr = pdata->bus_num;
+
+ ret = i2c_add_numbered_adapter(&i2c->adap);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to add bus to i2c core\n");
+ goto err_cpufreq;
+ }
+
platform_set_drvdata(pdev, i2c);
dev_info(&pdev->dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id);
return 0;
+ err_cpufreq:
+ s3c24xx_i2c_deregister_cpufreq(i2c);
+
err_irq:
free_irq(i2c->irq->start, i2c);
{
struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
+ s3c24xx_i2c_deregister_cpufreq(i2c);
+
i2c_del_adapter(&i2c->adap);
free_irq(i2c->irq->start, i2c);
{
if ((GPLR(IRQ_TO_GPIO(corgi_ts->irq_gpio)) & GPIO_bit(IRQ_TO_GPIO(corgi_ts->irq_gpio))) == 0) {
/* Disable Interrupt */
- set_irq_type(corgi_ts->irq_gpio, IRQT_NOEDGE);
+ set_irq_type(corgi_ts->irq_gpio, IRQ_TYPE_NONE);
if (read_xydata(corgi_ts)) {
corgi_ts->pendown = 1;
new_data(corgi_ts);
}
/* Enable Falling Edge */
- set_irq_type(corgi_ts->irq_gpio, IRQT_FALLING);
+ set_irq_type(corgi_ts->irq_gpio, IRQ_TYPE_EDGE_FALLING);
corgi_ts->pendown = 0;
}
}
corgi_ssp_ads7846_putget((4u << ADSCTRL_ADR_SH) | ADSCTRL_STS);
/* Enable Falling Edge */
- set_irq_type(corgi_ts->irq_gpio, IRQT_FALLING);
+ set_irq_type(corgi_ts->irq_gpio, IRQ_TYPE_EDGE_FALLING);
corgi_ts->power_mode = PWR_MODE_ACTIVE;
return 0;
corgi_ts->power_mode = PWR_MODE_ACTIVE;
/* Enable Falling Edge */
- set_irq_type(corgi_ts->irq_gpio, IRQT_FALLING);
+ set_irq_type(corgi_ts->irq_gpio, IRQ_TYPE_EDGE_FALLING);
return 0;
switch (wm->id) {
case WM9705_ID2:
wm->pen_irq = IRQ_GPIO(4);
- set_irq_type(IRQ_GPIO(4), IRQT_BOTHEDGE);
+ set_irq_type(IRQ_GPIO(4), IRQ_TYPE_EDGE_BOTH);
break;
case WM9712_ID2:
case WM9713_ID2:
DEB_EE(("dev:%p\n",dev));
- if( VFL_TYPE_GRABBER == (*vid)->type ) {
+ if ((*vid)->vfl_type == VFL_TYPE_GRABBER) {
vv->video_minor = -1;
} else {
vv->vbi_minor = -1;
/* if we have a user buffer, the first page may not be
aligned to a page boundary. */
- pt1->offset = list->offset;
+ pt1->offset = dma->sglist->offset;
pt2->offset = pt1->offset+o1;
pt3->offset = pt1->offset+o2;
case VIDIOC_ENUM_FMT:
{
struct v4l2_fmtdesc *f = arg;
- int index;
switch (f->type) {
case V4L2_BUF_TYPE_VIDEO_CAPTURE:
- case V4L2_BUF_TYPE_VIDEO_OVERLAY: {
- index = f->index;
- if (index < 0 || index >= NUM_FORMATS) {
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ if (f->index >= NUM_FORMATS)
return -EINVAL;
- }
- memset(f,0,sizeof(*f));
- f->index = index;
- strlcpy((char *)f->description,formats[index].name,sizeof(f->description));
- f->pixelformat = formats[index].pixelformat;
+ strlcpy((char *)f->description, formats[f->index].name,
+ sizeof(f->description));
+ f->pixelformat = formats[f->index].pixelformat;
+ f->flags = 0;
+ memset(f->reserved, 0, sizeof(f->reserved));
break;
- }
default:
return -EINVAL;
}
tristate
default VIDEO_MEDIA && I2C
depends on VIDEO_MEDIA && I2C
- select FW_LOADER if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG
- select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG
- select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG
+ select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE
+ select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE
select MEDIA_TUNER_MT20XX if !MEDIA_TUNER_CUSTOMIZE
select MEDIA_TUNER_TDA8290 if !MEDIA_TUNER_CUSTOMIZE
select MEDIA_TUNER_TEA5761 if !MEDIA_TUNER_CUSTOMIZE
config MEDIA_TUNER_XC2028
tristate "XCeive xc2028/xc3028 tuners"
depends on VIDEO_MEDIA && I2C
- depends on HOTPLUG
- select FW_LOADER
default m if MEDIA_TUNER_CUSTOMIZE
help
Say Y here to include support for the xc2028/xc3028 tuners.
config MEDIA_TUNER_XC5000
tristate "Xceive XC5000 silicon tuner"
depends on VIDEO_MEDIA && I2C
- depends on HOTPLUG
- select FW_LOADER
default m if DVB_FE_CUSTOMISE
help
A driver for the silicon tuner XC5000 from Xceive.
help
A driver for the silicon tuner MXL5005S from MaxLinear.
+config MEDIA_TUNER_MXL5007T
+ tristate "MaxLinear MxL5007T silicon tuner"
+ depends on VIDEO_MEDIA && I2C
+ default m if DVB_FE_CUSTOMISE
+ help
+ A driver for the silicon tuner MxL5007T from MaxLinear.
+
endif # MEDIA_TUNER_CUSTOMIZE
obj-$(CONFIG_MEDIA_TUNER_QT1010) += qt1010.o
obj-$(CONFIG_MEDIA_TUNER_MT2131) += mt2131.o
obj-$(CONFIG_MEDIA_TUNER_MXL5005S) += mxl5005s.o
+obj-$(CONFIG_MEDIA_TUNER_MXL5007T) += mxl5007t.o
EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core
EXTRA_CFLAGS += -Idrivers/media/dvb/frontends
tuner_dbg("mt2032: rfin=%d lo2=%d lo2n=%d lo2a=%d num=%d lo2freq=%d\n",
rfin,lo2,lo2n,lo2a,lo2num,lo2freq);
- if(lo1a<0 || lo1a>7 || lo1n<17 ||lo1n>48 || lo2a<0 ||lo2a >7 ||lo2n<17 || lo2n>30) {
+ if (lo1a > 7 || lo1n < 17 || lo1n > 48 || lo2a > 7 || lo2n < 17 ||
+ lo2n > 30) {
tuner_info("mt2032: frequency parameters out of range: %d %d %d %d\n",
lo1a, lo1n, lo2a,lo2n);
return(-1);
--- /dev/null
+/*
+ * mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner
+ *
+ * Copyright (C) 2008 Michael Krufky <mkrufky@linuxtv.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/i2c.h>
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include "tuner-i2c.h"
+#include "mxl5007t.h"
+
+static DEFINE_MUTEX(mxl5007t_list_mutex);
+static LIST_HEAD(hybrid_tuner_instance_list);
+
+static int mxl5007t_debug;
+module_param_named(debug, mxl5007t_debug, int, 0644);
+MODULE_PARM_DESC(debug, "set debug level");
+
+/* ------------------------------------------------------------------------- */
+
+#define mxl_printk(kern, fmt, arg...) \
+ printk(kern "%s: " fmt "\n", __func__, ##arg)
+
+#define mxl_err(fmt, arg...) \
+ mxl_printk(KERN_ERR, "%d: " fmt, __LINE__, ##arg)
+
+#define mxl_warn(fmt, arg...) \
+ mxl_printk(KERN_WARNING, fmt, ##arg)
+
+#define mxl_info(fmt, arg...) \
+ mxl_printk(KERN_INFO, fmt, ##arg)
+
+#define mxl_debug(fmt, arg...) \
+({ \
+ if (mxl5007t_debug) \
+ mxl_printk(KERN_DEBUG, fmt, ##arg); \
+})
+
+#define mxl_fail(ret) \
+({ \
+ int __ret; \
+ __ret = (ret < 0); \
+ if (__ret) \
+ mxl_printk(KERN_ERR, "error %d on line %d", \
+ ret, __LINE__); \
+ __ret; \
+})
+
+/* ------------------------------------------------------------------------- */
+
+#define MHz 1000000
+
+enum mxl5007t_mode {
+ MxL_MODE_OTA_DVBT_ATSC = 0,
+ MxL_MODE_OTA_NTSC_PAL_GH = 1,
+ MxL_MODE_OTA_PAL_IB = 2,
+ MxL_MODE_OTA_PAL_D_SECAM_KL = 3,
+ MxL_MODE_OTA_ISDBT = 4,
+ MxL_MODE_CABLE_DIGITAL = 0x10,
+ MxL_MODE_CABLE_NTSC_PAL_GH = 0x11,
+ MxL_MODE_CABLE_PAL_IB = 0x12,
+ MxL_MODE_CABLE_PAL_D_SECAM_KL = 0x13,
+ MxL_MODE_CABLE_SCTE40 = 0x14,
+};
+
+enum mxl5007t_chip_version {
+ MxL_UNKNOWN_ID = 0x00,
+ MxL_5007_V1_F1 = 0x11,
+ MxL_5007_V1_F2 = 0x12,
+ MxL_5007_V2_100_F1 = 0x21,
+ MxL_5007_V2_100_F2 = 0x22,
+ MxL_5007_V2_200_F1 = 0x23,
+ MxL_5007_V2_200_F2 = 0x24,
+};
+
+struct reg_pair_t {
+ u8 reg;
+ u8 val;
+};
+
+/* ------------------------------------------------------------------------- */
+
+static struct reg_pair_t init_tab[] = {
+ { 0x0b, 0x44 }, /* XTAL */
+ { 0x0c, 0x60 }, /* IF */
+ { 0x10, 0x00 }, /* MISC */
+ { 0x12, 0xca }, /* IDAC */
+ { 0x16, 0x90 }, /* MODE */
+ { 0x32, 0x38 }, /* MODE Analog/Digital */
+ { 0xd8, 0x18 }, /* CLK_OUT_ENABLE */
+ { 0x2c, 0x34 }, /* OVERRIDE */
+ { 0x4d, 0x40 }, /* OVERRIDE */
+ { 0x7f, 0x02 }, /* OVERRIDE */
+ { 0x9a, 0x52 }, /* OVERRIDE */
+ { 0x48, 0x5a }, /* OVERRIDE */
+ { 0x76, 0x1a }, /* OVERRIDE */
+ { 0x6a, 0x48 }, /* OVERRIDE */
+ { 0x64, 0x28 }, /* OVERRIDE */
+ { 0x66, 0xe6 }, /* OVERRIDE */
+ { 0x35, 0x0e }, /* OVERRIDE */
+ { 0x7e, 0x01 }, /* OVERRIDE */
+ { 0x83, 0x00 }, /* OVERRIDE */
+ { 0x04, 0x0b }, /* OVERRIDE */
+ { 0x05, 0x01 }, /* TOP_MASTER_ENABLE */
+ { 0, 0 }
+};
+
+static struct reg_pair_t init_tab_cable[] = {
+ { 0x0b, 0x44 }, /* XTAL */
+ { 0x0c, 0x60 }, /* IF */
+ { 0x10, 0x00 }, /* MISC */
+ { 0x12, 0xca }, /* IDAC */
+ { 0x16, 0x90 }, /* MODE */
+ { 0x32, 0x38 }, /* MODE A/D */
+ { 0x71, 0x3f }, /* TOP1 */
+ { 0x72, 0x3f }, /* TOP2 */
+ { 0x74, 0x3f }, /* TOP3 */
+ { 0xd8, 0x18 }, /* CLK_OUT_ENABLE */
+ { 0x2c, 0x34 }, /* OVERRIDE */
+ { 0x4d, 0x40 }, /* OVERRIDE */
+ { 0x7f, 0x02 }, /* OVERRIDE */
+ { 0x9a, 0x52 }, /* OVERRIDE */
+ { 0x48, 0x5a }, /* OVERRIDE */
+ { 0x76, 0x1a }, /* OVERRIDE */
+ { 0x6a, 0x48 }, /* OVERRIDE */
+ { 0x64, 0x28 }, /* OVERRIDE */
+ { 0x66, 0xe6 }, /* OVERRIDE */
+ { 0x35, 0x0e }, /* OVERRIDE */
+ { 0x7e, 0x01 }, /* OVERRIDE */
+ { 0x04, 0x0b }, /* OVERRIDE */
+ { 0x68, 0xb4 }, /* OVERRIDE */
+ { 0x36, 0x00 }, /* OVERRIDE */
+ { 0x05, 0x01 }, /* TOP_MASTER_ENABLE */
+ { 0, 0 }
+};
+
+/* ------------------------------------------------------------------------- */
+
+static struct reg_pair_t reg_pair_rftune[] = {
+ { 0x11, 0x00 }, /* abort tune */
+ { 0x13, 0x15 },
+ { 0x14, 0x40 },
+ { 0x15, 0x0e },
+ { 0x11, 0x02 }, /* start tune */
+ { 0, 0 }
+};
+
+/* ------------------------------------------------------------------------- */
+
+struct mxl5007t_state {
+ struct list_head hybrid_tuner_instance_list;
+ struct tuner_i2c_props i2c_props;
+
+ struct mutex lock;
+
+ struct mxl5007t_config *config;
+
+ enum mxl5007t_chip_version chip_id;
+
+ struct reg_pair_t tab_init[ARRAY_SIZE(init_tab)];
+ struct reg_pair_t tab_init_cable[ARRAY_SIZE(init_tab_cable)];
+ struct reg_pair_t tab_rftune[ARRAY_SIZE(reg_pair_rftune)];
+
+ u32 frequency;
+ u32 bandwidth;
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* called by _init and _rftun to manipulate the register arrays */
+
+static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val)
+{
+ unsigned int i = 0;
+
+ while (reg_pair[i].reg || reg_pair[i].val) {
+ if (reg_pair[i].reg == reg) {
+ reg_pair[i].val &= ~mask;
+ reg_pair[i].val |= val;
+ }
+ i++;
+
+ }
+ return;
+}
+
+static void copy_reg_bits(struct reg_pair_t *reg_pair1,
+ struct reg_pair_t *reg_pair2)
+{
+ unsigned int i, j;
+
+ i = j = 0;
+
+ while (reg_pair1[i].reg || reg_pair1[i].val) {
+ while (reg_pair2[j].reg || reg_pair2[j].reg) {
+ if (reg_pair1[i].reg != reg_pair2[j].reg) {
+ j++;
+ continue;
+ }
+ reg_pair2[j].val = reg_pair1[i].val;
+ break;
+ }
+ i++;
+ }
+ return;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void mxl5007t_set_mode_bits(struct mxl5007t_state *state,
+ enum mxl5007t_mode mode,
+ s32 if_diff_out_level)
+{
+ switch (mode) {
+ case MxL_MODE_OTA_DVBT_ATSC:
+ set_reg_bits(state->tab_init, 0x32, 0x0f, 0x06);
+ set_reg_bits(state->tab_init, 0x35, 0xff, 0x0e);
+ break;
+ case MxL_MODE_OTA_ISDBT:
+ set_reg_bits(state->tab_init, 0x32, 0x0f, 0x06);
+ set_reg_bits(state->tab_init, 0x35, 0xff, 0x12);
+ break;
+ case MxL_MODE_OTA_NTSC_PAL_GH:
+ set_reg_bits(state->tab_init, 0x16, 0x70, 0x00);
+ set_reg_bits(state->tab_init, 0x32, 0xff, 0x85);
+ break;
+ case MxL_MODE_OTA_PAL_IB:
+ set_reg_bits(state->tab_init, 0x16, 0x70, 0x10);
+ set_reg_bits(state->tab_init, 0x32, 0xff, 0x85);
+ break;
+ case MxL_MODE_OTA_PAL_D_SECAM_KL:
+ set_reg_bits(state->tab_init, 0x16, 0x70, 0x20);
+ set_reg_bits(state->tab_init, 0x32, 0xff, 0x85);
+ break;
+ case MxL_MODE_CABLE_DIGITAL:
+ set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01);
+ set_reg_bits(state->tab_init_cable, 0x72, 0xff,
+ 8 - if_diff_out_level);
+ set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17);
+ break;
+ case MxL_MODE_CABLE_NTSC_PAL_GH:
+ set_reg_bits(state->tab_init, 0x16, 0x70, 0x00);
+ set_reg_bits(state->tab_init, 0x32, 0xff, 0x85);
+ set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01);
+ set_reg_bits(state->tab_init_cable, 0x72, 0xff,
+ 8 - if_diff_out_level);
+ set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17);
+ break;
+ case MxL_MODE_CABLE_PAL_IB:
+ set_reg_bits(state->tab_init, 0x16, 0x70, 0x10);
+ set_reg_bits(state->tab_init, 0x32, 0xff, 0x85);
+ set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01);
+ set_reg_bits(state->tab_init_cable, 0x72, 0xff,
+ 8 - if_diff_out_level);
+ set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17);
+ break;
+ case MxL_MODE_CABLE_PAL_D_SECAM_KL:
+ set_reg_bits(state->tab_init, 0x16, 0x70, 0x20);
+ set_reg_bits(state->tab_init, 0x32, 0xff, 0x85);
+ set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01);
+ set_reg_bits(state->tab_init_cable, 0x72, 0xff,
+ 8 - if_diff_out_level);
+ set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17);
+ break;
+ case MxL_MODE_CABLE_SCTE40:
+ set_reg_bits(state->tab_init_cable, 0x36, 0xff, 0x08);
+ set_reg_bits(state->tab_init_cable, 0x68, 0xff, 0xbc);
+ set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01);
+ set_reg_bits(state->tab_init_cable, 0x72, 0xff,
+ 8 - if_diff_out_level);
+ set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17);
+ break;
+ default:
+ mxl_fail(-EINVAL);
+ }
+ return;
+}
+
+static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state,
+ enum mxl5007t_if_freq if_freq,
+ int invert_if)
+{
+ u8 val;
+
+ switch (if_freq) {
+ case MxL_IF_4_MHZ:
+ val = 0x00;
+ break;
+ case MxL_IF_4_5_MHZ:
+ val = 0x20;
+ break;
+ case MxL_IF_4_57_MHZ:
+ val = 0x30;
+ break;
+ case MxL_IF_5_MHZ:
+ val = 0x40;
+ break;
+ case MxL_IF_5_38_MHZ:
+ val = 0x50;
+ break;
+ case MxL_IF_6_MHZ:
+ val = 0x60;
+ break;
+ case MxL_IF_6_28_MHZ:
+ val = 0x70;
+ break;
+ case MxL_IF_9_1915_MHZ:
+ val = 0x80;
+ break;
+ case MxL_IF_35_25_MHZ:
+ val = 0x90;
+ break;
+ case MxL_IF_36_15_MHZ:
+ val = 0xa0;
+ break;
+ case MxL_IF_44_MHZ:
+ val = 0xb0;
+ break;
+ default:
+ mxl_fail(-EINVAL);
+ return;
+ }
+ set_reg_bits(state->tab_init, 0x0c, 0xf0, val);
+
+ /* set inverted IF or normal IF */
+ set_reg_bits(state->tab_init, 0x0c, 0x08, invert_if ? 0x08 : 0x00);
+
+ return;
+}
+
+static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state,
+ enum mxl5007t_xtal_freq xtal_freq)
+{
+ u8 val;
+
+ switch (xtal_freq) {
+ case MxL_XTAL_16_MHZ:
+ val = 0x00; /* select xtal freq & Ref Freq */
+ break;
+ case MxL_XTAL_20_MHZ:
+ val = 0x11;
+ break;
+ case MxL_XTAL_20_25_MHZ:
+ val = 0x22;
+ break;
+ case MxL_XTAL_20_48_MHZ:
+ val = 0x33;
+ break;
+ case MxL_XTAL_24_MHZ:
+ val = 0x44;
+ break;
+ case MxL_XTAL_25_MHZ:
+ val = 0x55;
+ break;
+ case MxL_XTAL_25_14_MHZ:
+ val = 0x66;
+ break;
+ case MxL_XTAL_27_MHZ:
+ val = 0x77;
+ break;
+ case MxL_XTAL_28_8_MHZ:
+ val = 0x88;
+ break;
+ case MxL_XTAL_32_MHZ:
+ val = 0x99;
+ break;
+ case MxL_XTAL_40_MHZ:
+ val = 0xaa;
+ break;
+ case MxL_XTAL_44_MHZ:
+ val = 0xbb;
+ break;
+ case MxL_XTAL_48_MHZ:
+ val = 0xcc;
+ break;
+ case MxL_XTAL_49_3811_MHZ:
+ val = 0xdd;
+ break;
+ default:
+ mxl_fail(-EINVAL);
+ return;
+ }
+ set_reg_bits(state->tab_init, 0x0b, 0xff, val);
+
+ return;
+}
+
+static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state,
+ enum mxl5007t_mode mode)
+{
+ struct mxl5007t_config *cfg = state->config;
+
+ memcpy(&state->tab_init, &init_tab, sizeof(init_tab));
+ memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable));
+
+ mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level);
+ mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if);
+ mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz);
+
+ set_reg_bits(state->tab_init, 0x10, 0x40, cfg->loop_thru_enable << 6);
+
+ set_reg_bits(state->tab_init, 0xd8, 0x08, cfg->clk_out_enable << 3);
+
+ set_reg_bits(state->tab_init, 0x10, 0x07, cfg->clk_out_amp);
+
+ /* set IDAC to automatic mode control by AGC */
+ set_reg_bits(state->tab_init, 0x12, 0x80, 0x00);
+
+ if (mode >= MxL_MODE_CABLE_DIGITAL) {
+ copy_reg_bits(state->tab_init, state->tab_init_cable);
+ return state->tab_init_cable;
+ } else
+ return state->tab_init;
+}
+
+/* ------------------------------------------------------------------------- */
+
+enum mxl5007t_bw_mhz {
+ MxL_BW_6MHz = 6,
+ MxL_BW_7MHz = 7,
+ MxL_BW_8MHz = 8,
+};
+
+static void mxl5007t_set_bw_bits(struct mxl5007t_state *state,
+ enum mxl5007t_bw_mhz bw)
+{
+ u8 val;
+
+ switch (bw) {
+ case MxL_BW_6MHz:
+ val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A,
+ * and DIG_MODEINDEX_CSF */
+ break;
+ case MxL_BW_7MHz:
+ val = 0x21;
+ break;
+ case MxL_BW_8MHz:
+ val = 0x3f;
+ break;
+ default:
+ mxl_fail(-EINVAL);
+ return;
+ }
+ set_reg_bits(state->tab_rftune, 0x13, 0x3f, val);
+
+ return;
+}
+
+static struct
+reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state,
+ u32 rf_freq, enum mxl5007t_bw_mhz bw)
+{
+ u32 dig_rf_freq = 0;
+ u32 temp;
+ u32 frac_divider = 1000000;
+ unsigned int i;
+
+ memcpy(&state->tab_rftune, ®_pair_rftune, sizeof(reg_pair_rftune));
+
+ mxl5007t_set_bw_bits(state, bw);
+
+ /* Convert RF frequency into 16 bits =>
+ * 10 bit integer (MHz) + 6 bit fraction */
+ dig_rf_freq = rf_freq / MHz;
+
+ temp = rf_freq % MHz;
+
+ for (i = 0; i < 6; i++) {
+ dig_rf_freq <<= 1;
+ frac_divider /= 2;
+ if (temp > frac_divider) {
+ temp -= frac_divider;
+ dig_rf_freq++;
+ }
+ }
+
+ /* add to have shift center point by 7.8124 kHz */
+ if (temp > 7812)
+ dig_rf_freq++;
+
+ set_reg_bits(state->tab_rftune, 0x14, 0xff, (u8)dig_rf_freq);
+ set_reg_bits(state->tab_rftune, 0x15, 0xff, (u8)(dig_rf_freq >> 8));
+
+ return state->tab_rftune;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val)
+{
+ u8 buf[] = { reg, val };
+ struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0,
+ .buf = buf, .len = 2 };
+ int ret;
+
+ ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
+ if (ret != 1) {
+ mxl_err("failed!");
+ return -EREMOTEIO;
+ }
+ return 0;
+}
+
+static int mxl5007t_write_regs(struct mxl5007t_state *state,
+ struct reg_pair_t *reg_pair)
+{
+ unsigned int i = 0;
+ int ret = 0;
+
+ while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) {
+ ret = mxl5007t_write_reg(state,
+ reg_pair[i].reg, reg_pair[i].val);
+ i++;
+ }
+ return ret;
+}
+
+static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val)
+{
+ struct i2c_msg msg[] = {
+ { .addr = state->i2c_props.addr, .flags = 0,
+ .buf = ®, .len = 1 },
+ { .addr = state->i2c_props.addr, .flags = I2C_M_RD,
+ .buf = val, .len = 1 },
+ };
+ int ret;
+
+ ret = i2c_transfer(state->i2c_props.adap, msg, 2);
+ if (ret != 2) {
+ mxl_err("failed!");
+ return -EREMOTEIO;
+ }
+ return 0;
+}
+
+static int mxl5007t_soft_reset(struct mxl5007t_state *state)
+{
+ u8 d = 0xff;
+ struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0,
+ .buf = &d, .len = 1 };
+
+ int ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
+
+ if (ret != 1) {
+ mxl_err("failed!");
+ return -EREMOTEIO;
+ }
+ return 0;
+}
+
+static int mxl5007t_tuner_init(struct mxl5007t_state *state,
+ enum mxl5007t_mode mode)
+{
+ struct reg_pair_t *init_regs;
+ int ret;
+
+ ret = mxl5007t_soft_reset(state);
+ if (mxl_fail(ret))
+ goto fail;
+
+ /* calculate initialization reg array */
+ init_regs = mxl5007t_calc_init_regs(state, mode);
+
+ ret = mxl5007t_write_regs(state, init_regs);
+ if (mxl_fail(ret))
+ goto fail;
+ mdelay(1);
+
+ ret = mxl5007t_write_reg(state, 0x2c, 0x35);
+ mxl_fail(ret);
+fail:
+ return ret;
+}
+
+static int mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz,
+ enum mxl5007t_bw_mhz bw)
+{
+ struct reg_pair_t *rf_tune_regs;
+ int ret;
+
+ /* calculate channel change reg array */
+ rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw);
+
+ ret = mxl5007t_write_regs(state, rf_tune_regs);
+ if (mxl_fail(ret))
+ goto fail;
+ msleep(3);
+fail:
+ return ret;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static int mxl5007t_synth_lock_status(struct mxl5007t_state *state,
+ int *rf_locked, int *ref_locked)
+{
+ u8 d;
+ int ret;
+
+ *rf_locked = 0;
+ *ref_locked = 0;
+
+ ret = mxl5007t_read_reg(state, 0xcf, &d);
+ if (mxl_fail(ret))
+ goto fail;
+
+ if ((d & 0x0c) == 0x0c)
+ *rf_locked = 1;
+
+ if ((d & 0x03) == 0x03)
+ *ref_locked = 1;
+fail:
+ return ret;
+}
+
+static int mxl5007t_check_rf_input_power(struct mxl5007t_state *state,
+ s32 *rf_input_level)
+{
+ u8 d1, d2;
+ int ret;
+
+ ret = mxl5007t_read_reg(state, 0xb7, &d1);
+ if (mxl_fail(ret))
+ goto fail;
+
+ ret = mxl5007t_read_reg(state, 0xbf, &d2);
+ if (mxl_fail(ret))
+ goto fail;
+
+ d2 = d2 >> 4;
+ if (d2 > 7)
+ d2 += 0xf0;
+
+ *rf_input_level = (s32)(d1 + d2 - 113);
+fail:
+ return ret;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static int mxl5007t_get_status(struct dvb_frontend *fe, u32 *status)
+{
+ struct mxl5007t_state *state = fe->tuner_priv;
+ int rf_locked, ref_locked;
+ s32 rf_input_level;
+ int ret;
+
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+
+ ret = mxl5007t_synth_lock_status(state, &rf_locked, &ref_locked);
+ if (mxl_fail(ret))
+ goto fail;
+ mxl_debug("%s%s", rf_locked ? "rf locked " : "",
+ ref_locked ? "ref locked" : "");
+
+ ret = mxl5007t_check_rf_input_power(state, &rf_input_level);
+ if (mxl_fail(ret))
+ goto fail;
+ mxl_debug("rf input power: %d", rf_input_level);
+fail:
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0);
+
+ return ret;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static int mxl5007t_set_params(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *params)
+{
+ struct mxl5007t_state *state = fe->tuner_priv;
+ enum mxl5007t_bw_mhz bw;
+ enum mxl5007t_mode mode;
+ int ret;
+ u32 freq = params->frequency;
+
+ if (fe->ops.info.type == FE_ATSC) {
+ switch (params->u.vsb.modulation) {
+ case VSB_8:
+ case VSB_16:
+ mode = MxL_MODE_OTA_DVBT_ATSC;
+ break;
+ case QAM_64:
+ case QAM_256:
+ mode = MxL_MODE_CABLE_DIGITAL;
+ break;
+ default:
+ mxl_err("modulation not set!");
+ return -EINVAL;
+ }
+ bw = MxL_BW_6MHz;
+ } else if (fe->ops.info.type == FE_OFDM) {
+ switch (params->u.ofdm.bandwidth) {
+ case BANDWIDTH_6_MHZ:
+ bw = MxL_BW_6MHz;
+ break;
+ case BANDWIDTH_7_MHZ:
+ bw = MxL_BW_7MHz;
+ break;
+ case BANDWIDTH_8_MHZ:
+ bw = MxL_BW_8MHz;
+ break;
+ default:
+ mxl_err("bandwidth not set!");
+ return -EINVAL;
+ }
+ mode = MxL_MODE_OTA_DVBT_ATSC;
+ } else {
+ mxl_err("modulation type not supported!");
+ return -EINVAL;
+ }
+
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+
+ mutex_lock(&state->lock);
+
+ ret = mxl5007t_tuner_init(state, mode);
+ if (mxl_fail(ret))
+ goto fail;
+
+ ret = mxl5007t_tuner_rf_tune(state, freq, bw);
+ if (mxl_fail(ret))
+ goto fail;
+
+ state->frequency = freq;
+ state->bandwidth = (fe->ops.info.type == FE_OFDM) ?
+ params->u.ofdm.bandwidth : 0;
+fail:
+ mutex_unlock(&state->lock);
+
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0);
+
+ return ret;
+}
+
+static int mxl5007t_set_analog_params(struct dvb_frontend *fe,
+ struct analog_parameters *params)
+{
+ struct mxl5007t_state *state = fe->tuner_priv;
+ enum mxl5007t_bw_mhz bw = 0; /* FIXME */
+ enum mxl5007t_mode cbl_mode;
+ enum mxl5007t_mode ota_mode;
+ char *mode_name;
+ int ret;
+ u32 freq = params->frequency * 62500;
+
+#define cable 1
+ if (params->std & V4L2_STD_MN) {
+ cbl_mode = MxL_MODE_CABLE_NTSC_PAL_GH;
+ ota_mode = MxL_MODE_OTA_NTSC_PAL_GH;
+ mode_name = "MN";
+ } else if (params->std & V4L2_STD_B) {
+ cbl_mode = MxL_MODE_CABLE_PAL_IB;
+ ota_mode = MxL_MODE_OTA_PAL_IB;
+ mode_name = "B";
+ } else if (params->std & V4L2_STD_GH) {
+ cbl_mode = MxL_MODE_CABLE_NTSC_PAL_GH;
+ ota_mode = MxL_MODE_OTA_NTSC_PAL_GH;
+ mode_name = "GH";
+ } else if (params->std & V4L2_STD_PAL_I) {
+ cbl_mode = MxL_MODE_CABLE_PAL_IB;
+ ota_mode = MxL_MODE_OTA_PAL_IB;
+ mode_name = "I";
+ } else if (params->std & V4L2_STD_DK) {
+ cbl_mode = MxL_MODE_CABLE_PAL_D_SECAM_KL;
+ ota_mode = MxL_MODE_OTA_PAL_D_SECAM_KL;
+ mode_name = "DK";
+ } else if (params->std & V4L2_STD_SECAM_L) {
+ cbl_mode = MxL_MODE_CABLE_PAL_D_SECAM_KL;
+ ota_mode = MxL_MODE_OTA_PAL_D_SECAM_KL;
+ mode_name = "L";
+ } else if (params->std & V4L2_STD_SECAM_LC) {
+ cbl_mode = MxL_MODE_CABLE_PAL_D_SECAM_KL;
+ ota_mode = MxL_MODE_OTA_PAL_D_SECAM_KL;
+ mode_name = "L'";
+ } else {
+ mode_name = "xx";
+ /* FIXME */
+ cbl_mode = MxL_MODE_CABLE_NTSC_PAL_GH;
+ ota_mode = MxL_MODE_OTA_NTSC_PAL_GH;
+ }
+ mxl_debug("setting mxl5007 to system %s", mode_name);
+
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+
+ mutex_lock(&state->lock);
+
+ ret = mxl5007t_tuner_init(state, cable ? cbl_mode : ota_mode);
+ if (mxl_fail(ret))
+ goto fail;
+
+ ret = mxl5007t_tuner_rf_tune(state, freq, bw);
+ if (mxl_fail(ret))
+ goto fail;
+
+ state->frequency = freq;
+ state->bandwidth = 0;
+fail:
+ mutex_unlock(&state->lock);
+
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0);
+
+ return ret;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static int mxl5007t_init(struct dvb_frontend *fe)
+{
+ struct mxl5007t_state *state = fe->tuner_priv;
+ int ret;
+ u8 d;
+
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+
+ ret = mxl5007t_read_reg(state, 0x05, &d);
+ if (mxl_fail(ret))
+ goto fail;
+
+ ret = mxl5007t_write_reg(state, 0x05, d | 0x01);
+ mxl_fail(ret);
+fail:
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0);
+
+ return ret;
+}
+
+static int mxl5007t_sleep(struct dvb_frontend *fe)
+{
+ struct mxl5007t_state *state = fe->tuner_priv;
+ int ret;
+ u8 d;
+
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+
+ ret = mxl5007t_read_reg(state, 0x05, &d);
+ if (mxl_fail(ret))
+ goto fail;
+
+ ret = mxl5007t_write_reg(state, 0x05, d & ~0x01);
+ mxl_fail(ret);
+fail:
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0);
+
+ return ret;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static int mxl5007t_get_frequency(struct dvb_frontend *fe, u32 *frequency)
+{
+ struct mxl5007t_state *state = fe->tuner_priv;
+ *frequency = state->frequency;
+ return 0;
+}
+
+static int mxl5007t_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
+{
+ struct mxl5007t_state *state = fe->tuner_priv;
+ *bandwidth = state->bandwidth;
+ return 0;
+}
+
+static int mxl5007t_release(struct dvb_frontend *fe)
+{
+ struct mxl5007t_state *state = fe->tuner_priv;
+
+ mutex_lock(&mxl5007t_list_mutex);
+
+ if (state)
+ hybrid_tuner_release_state(state);
+
+ mutex_unlock(&mxl5007t_list_mutex);
+
+ fe->tuner_priv = NULL;
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static struct dvb_tuner_ops mxl5007t_tuner_ops = {
+ .info = {
+ .name = "MaxLinear MxL5007T",
+ },
+ .init = mxl5007t_init,
+ .sleep = mxl5007t_sleep,
+ .set_params = mxl5007t_set_params,
+ .set_analog_params = mxl5007t_set_analog_params,
+ .get_status = mxl5007t_get_status,
+ .get_frequency = mxl5007t_get_frequency,
+ .get_bandwidth = mxl5007t_get_bandwidth,
+ .release = mxl5007t_release,
+};
+
+static int mxl5007t_get_chip_id(struct mxl5007t_state *state)
+{
+ char *name;
+ int ret;
+ u8 id;
+
+ ret = mxl5007t_read_reg(state, 0xd3, &id);
+ if (mxl_fail(ret))
+ goto fail;
+
+ switch (id) {
+ case MxL_5007_V1_F1:
+ name = "MxL5007.v1.f1";
+ break;
+ case MxL_5007_V1_F2:
+ name = "MxL5007.v1.f2";
+ break;
+ case MxL_5007_V2_100_F1:
+ name = "MxL5007.v2.100.f1";
+ break;
+ case MxL_5007_V2_100_F2:
+ name = "MxL5007.v2.100.f2";
+ break;
+ case MxL_5007_V2_200_F1:
+ name = "MxL5007.v2.200.f1";
+ break;
+ case MxL_5007_V2_200_F2:
+ name = "MxL5007.v2.200.f2";
+ break;
+ default:
+ name = "MxL5007T";
+ id = MxL_UNKNOWN_ID;
+ }
+ state->chip_id = id;
+ mxl_info("%s detected @ %d-%04x", name,
+ i2c_adapter_id(state->i2c_props.adap),
+ state->i2c_props.addr);
+ return 0;
+fail:
+ mxl_warn("unable to identify device @ %d-%04x",
+ i2c_adapter_id(state->i2c_props.adap),
+ state->i2c_props.addr);
+
+ state->chip_id = MxL_UNKNOWN_ID;
+ return ret;
+}
+
+struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
+ struct i2c_adapter *i2c, u8 addr,
+ struct mxl5007t_config *cfg)
+{
+ struct mxl5007t_state *state = NULL;
+ int instance, ret;
+
+ mutex_lock(&mxl5007t_list_mutex);
+ instance = hybrid_tuner_request_state(struct mxl5007t_state, state,
+ hybrid_tuner_instance_list,
+ i2c, addr, "mxl5007");
+ switch (instance) {
+ case 0:
+ goto fail;
+ break;
+ case 1:
+ /* new tuner instance */
+ state->config = cfg;
+
+ mutex_init(&state->lock);
+
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+
+ ret = mxl5007t_get_chip_id(state);
+
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0);
+
+ /* check return value of mxl5007t_get_chip_id */
+ if (mxl_fail(ret))
+ goto fail;
+ break;
+ default:
+ /* existing tuner instance */
+ break;
+ }
+ fe->tuner_priv = state;
+ mutex_unlock(&mxl5007t_list_mutex);
+
+ memcpy(&fe->ops.tuner_ops, &mxl5007t_tuner_ops,
+ sizeof(struct dvb_tuner_ops));
+
+ return fe;
+fail:
+ mutex_unlock(&mxl5007t_list_mutex);
+
+ mxl5007t_release(fe);
+ return NULL;
+}
+EXPORT_SYMBOL_GPL(mxl5007t_attach);
+MODULE_DESCRIPTION("MaxLinear MxL5007T Silicon IC tuner driver");
+MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
+MODULE_LICENSE("GPL");
+MODULE_VERSION("0.1");
+
+/*
+ * Overrides for Emacs so that we follow Linus's tabbing style.
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
--- /dev/null
+/*
+ * mxl5007t.h - driver for the MaxLinear MxL5007T silicon tuner
+ *
+ * Copyright (C) 2008 Michael Krufky <mkrufky@linuxtv.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MXL5007T_H__
+#define __MXL5007T_H__
+
+#include "dvb_frontend.h"
+
+/* ------------------------------------------------------------------------- */
+
+enum mxl5007t_if_freq {
+ MxL_IF_4_MHZ, /* 4000000 */
+ MxL_IF_4_5_MHZ, /* 4500000 */
+ MxL_IF_4_57_MHZ, /* 4570000 */
+ MxL_IF_5_MHZ, /* 5000000 */
+ MxL_IF_5_38_MHZ, /* 5380000 */
+ MxL_IF_6_MHZ, /* 6000000 */
+ MxL_IF_6_28_MHZ, /* 6280000 */
+ MxL_IF_9_1915_MHZ, /* 9191500 */
+ MxL_IF_35_25_MHZ, /* 35250000 */
+ MxL_IF_36_15_MHZ, /* 36150000 */
+ MxL_IF_44_MHZ, /* 44000000 */
+};
+
+enum mxl5007t_xtal_freq {
+ MxL_XTAL_16_MHZ, /* 16000000 */
+ MxL_XTAL_20_MHZ, /* 20000000 */
+ MxL_XTAL_20_25_MHZ, /* 20250000 */
+ MxL_XTAL_20_48_MHZ, /* 20480000 */
+ MxL_XTAL_24_MHZ, /* 24000000 */
+ MxL_XTAL_25_MHZ, /* 25000000 */
+ MxL_XTAL_25_14_MHZ, /* 25140000 */
+ MxL_XTAL_27_MHZ, /* 27000000 */
+ MxL_XTAL_28_8_MHZ, /* 28800000 */
+ MxL_XTAL_32_MHZ, /* 32000000 */
+ MxL_XTAL_40_MHZ, /* 40000000 */
+ MxL_XTAL_44_MHZ, /* 44000000 */
+ MxL_XTAL_48_MHZ, /* 48000000 */
+ MxL_XTAL_49_3811_MHZ, /* 49381100 */
+};
+
+enum mxl5007t_clkout_amp {
+ MxL_CLKOUT_AMP_0_94V = 0,
+ MxL_CLKOUT_AMP_0_53V = 1,
+ MxL_CLKOUT_AMP_0_37V = 2,
+ MxL_CLKOUT_AMP_0_28V = 3,
+ MxL_CLKOUT_AMP_0_23V = 4,
+ MxL_CLKOUT_AMP_0_20V = 5,
+ MxL_CLKOUT_AMP_0_17V = 6,
+ MxL_CLKOUT_AMP_0_15V = 7,
+};
+
+struct mxl5007t_config {
+ s32 if_diff_out_level;
+ enum mxl5007t_clkout_amp clk_out_amp;
+ enum mxl5007t_xtal_freq xtal_freq_hz;
+ enum mxl5007t_if_freq if_freq_hz;
+ unsigned int invert_if:1;
+ unsigned int loop_thru_enable:1;
+ unsigned int clk_out_enable:1;
+};
+
+#if defined(CONFIG_MEDIA_TUNER_MXL5007T) || (defined(CONFIG_MEDIA_TUNER_MXL5007T_MODULE) && defined(MODULE))
+extern struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
+ struct i2c_adapter *i2c, u8 addr,
+ struct mxl5007t_config *cfg);
+#else
+static inline struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
+ struct i2c_adapter *i2c,
+ u8 addr,
+ struct mxl5007t_config *cfg)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+#endif
+
+#endif /* __MXL5007T_H__ */
+
+/*
+ * Overrides for Emacs so that we follow Linus's tabbing style.
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
+
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/delay.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <media/tuner.h>
#include "tuner-i2c.h"
*/
#include <linux/delay.h>
#include <linux/i2c.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <media/tuner.h>
#include <media/v4l2-common.h>
#include <media/tuner-types.h>
config DVB_BT8XX
tristate "BT8xx based PCI cards"
depends on DVB_CORE && PCI && I2C && VIDEO_BT848
- depends on HOTPLUG # due to FW_LOADER
select DVB_MT352 if !DVB_FE_CUSTOMISE
select DVB_SP887X if !DVB_FE_CUSTOMISE
select DVB_NXT6000 if !DVB_FE_CUSTOMISE
select DVB_LGDT330X if !DVB_FE_CUSTOMISE
select DVB_ZL10353 if !DVB_FE_CUSTOMISE
select MEDIA_TUNER_SIMPLE if !DVB_FE_CUSTOMISE
- select FW_LOADER
help
Support for PCI cards based on the Bt8xx PCI bridge. Examples are
the Nebula cards, the Pinnacle PCTV cards, the Twinhan DST cards,
config DVB_USB
tristate "Support for various USB DVB devices"
depends on DVB_CORE && USB && I2C && INPUT
- depends on HOTPLUG # due to FW_LOADER
- select FW_LOADER
help
By enabling this you will be able to choose the various supported
USB1.1 and USB2.0 DVB devices.
Say Y here to support the default remote control decoding for the
Afatech AF9005 based receiver.
+config DVB_USB_DW2102
+ tristate "DvbWorld 2102 DVB-S USB2.0 receiver"
+ depends on DVB_USB
+ select DVB_STV0299 if !DVB_FE_CUSTOMISE
+ select DVB_PLL if !DVB_FE_CUSTOMISE
+ help
+ Say Y here to support the DvbWorld 2102 DVB-S USB2.0 receiver.
+
config DVB_USB_ANYSEE
tristate "Anysee DVB-T/C USB2.0 support"
depends on DVB_USB
dvb-usb-anysee-objs = anysee.o
obj-$(CONFIG_DVB_USB_ANYSEE) += dvb-usb-anysee.o
+dvb-usb-dw2102-objs = dw2102.o
+obj-$(CONFIG_DVB_USB_DW2102) += dvb-usb-dw2102.o
+
EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends/
# due to tuner-xc3028
EXTRA_CFLAGS += -Idrivers/media/common/tuners
MODULE_PARM_DESC(debug, "set debugging level" DVB_USB_DEBUG_STATUS);
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
-struct mutex anysee_usb_mutex;
+static struct mutex anysee_usb_mutex;
static int anysee_ctrl_msg(struct dvb_usb_device *d, u8 *sbuf, u8 slen,
u8 *rbuf, u8 rlen)
#define USB_PID_ASUS_U3000 0x171f
#define USB_PID_ASUS_U3100 0x173f
#define USB_PID_YUAN_EC372S 0x1edc
+#define USB_PID_DW2102 0x2102
#endif
--- /dev/null
+/* DVB USB framework compliant Linux driver for the DVBWorld DVB-S 2102 Card
+*
+* Copyright (C) 2008 Igor M. Liplianin (liplianin@me.by)
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation, version 2.
+*
+* see Documentation/dvb/README.dvb-usb for more information
+*/
+#include <linux/version.h>
+#include "dw2102.h"
+#include "stv0299.h"
+#include "z0194a.h"
+
+#ifndef USB_PID_DW2102
+#define USB_PID_DW2102 0x2102
+#endif
+
+#define DW2102_READ_MSG 0
+#define DW2102_WRITE_MSG 1
+
+#define REG_1F_SYMBOLRATE_BYTE0 0x1f
+#define REG_20_SYMBOLRATE_BYTE1 0x20
+#define REG_21_SYMBOLRATE_BYTE2 0x21
+
+#define DW2102_VOLTAGE_CTRL (0x1800)
+#define DW2102_RC_QUERY (0x1a00)
+
+struct dw2102_state {
+ u32 last_key_pressed;
+};
+struct dw2102_rc_keys {
+ u32 keycode;
+ u32 event;
+};
+
+DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
+
+static int dw2102_op_rw(struct usb_device *dev, u8 request, u16 value,
+ u8 *data, u16 len, int flags)
+{
+ int ret;
+ u8 u8buf[len];
+
+ unsigned int pipe = (flags == DW2102_READ_MSG) ?
+ usb_rcvctrlpipe(dev, 0) : usb_sndctrlpipe(dev, 0);
+ u8 request_type = (flags == DW2102_READ_MSG) ? USB_DIR_IN : USB_DIR_OUT;
+
+ if (flags == DW2102_WRITE_MSG)
+ memcpy(u8buf, data, len);
+ ret = usb_control_msg(dev, pipe, request,
+ request_type | USB_TYPE_VENDOR, value, 0 , u8buf, len, 2000);
+
+ if (flags == DW2102_READ_MSG)
+ memcpy(data, u8buf, len);
+ return ret;
+}
+
+/* I2C */
+
+static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[],
+ int num)
+{
+struct dvb_usb_device *d = i2c_get_adapdata(adap);
+ int i = 0, ret = 0;
+ u8 buf6[] = {0x2c, 0x05, 0xc0, 0, 0, 0, 0};
+ u8 request;
+ u16 value;
+
+ if (!d)
+ return -ENODEV;
+ if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
+ return -EAGAIN;
+
+ switch (num) {
+ case 2:
+ /* read stv0299 register */
+ request = 0xb5;
+ value = msg[0].buf[0];/* register */
+ for (i = 0; i < msg[1].len; i++) {
+ value = value + i;
+ ret = dw2102_op_rw(d->udev, 0xb5,
+ value, buf6, 2, DW2102_READ_MSG);
+ msg[1].buf[i] = buf6[0];
+
+ }
+ break;
+ case 1:
+ switch (msg[0].addr) {
+ case 0x68:
+ /* write to stv0299 register */
+ buf6[0] = 0x2a;
+ buf6[1] = msg[0].buf[0];
+ buf6[2] = msg[0].buf[1];
+ ret = dw2102_op_rw(d->udev, 0xb2,
+ 0, buf6, 3, DW2102_WRITE_MSG);
+ break;
+ case 0x60:
+ if (msg[0].flags == 0) {
+ /* write to tuner pll */
+ buf6[0] = 0x2c;
+ buf6[1] = 5;
+ buf6[2] = 0xc0;
+ buf6[3] = msg[0].buf[0];
+ buf6[4] = msg[0].buf[1];
+ buf6[5] = msg[0].buf[2];
+ buf6[6] = msg[0].buf[3];
+ ret = dw2102_op_rw(d->udev, 0xb2,
+ 0, buf6, 7, DW2102_WRITE_MSG);
+ } else {
+ /* write to tuner pll */
+ ret = dw2102_op_rw(d->udev, 0xb5,
+ 0, buf6, 1, DW2102_READ_MSG);
+ msg[0].buf[0] = buf6[0];
+ }
+ break;
+ case (DW2102_RC_QUERY):
+ ret = dw2102_op_rw(d->udev, 0xb8,
+ 0, buf6, 2, DW2102_READ_MSG);
+ msg[0].buf[0] = buf6[0];
+ msg[0].buf[1] = buf6[1];
+ break;
+ case (DW2102_VOLTAGE_CTRL):
+ buf6[0] = 0x30;
+ buf6[1] = msg[0].buf[0];
+ ret = dw2102_op_rw(d->udev, 0xb2,
+ 0, buf6, 2, DW2102_WRITE_MSG);
+ break;
+ }
+
+ break;
+ }
+
+ mutex_unlock(&d->i2c_mutex);
+ return num;
+}
+
+static u32 dw2102_i2c_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C;
+}
+
+static struct i2c_algorithm dw2102_i2c_algo = {
+ .master_xfer = dw2102_i2c_transfer,
+ .functionality = dw2102_i2c_func,
+};
+
+static int dw2102_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
+{
+ static u8 command_13v[1] = {0x00};
+ static u8 command_18v[1] = {0x01};
+ struct i2c_msg msg[] = {
+ {.addr = DW2102_VOLTAGE_CTRL, .flags = 0,
+ .buf = command_13v, .len = 1},
+ };
+
+ struct dvb_usb_adapter *udev_adap =
+ (struct dvb_usb_adapter *)(fe->dvb->priv);
+ if (voltage == SEC_VOLTAGE_18)
+ msg[0].buf = command_18v;
+ i2c_transfer(&udev_adap->dev->i2c_adap, msg, 1);
+ return 0;
+}
+
+static int dw2102_frontend_attach(struct dvb_usb_adapter *d)
+{
+ d->fe = dvb_attach(stv0299_attach, &sharp_z0194a_config,
+ &d->dev->i2c_adap);
+ if (d->fe != NULL) {
+ d->fe->ops.set_voltage = dw2102_set_voltage;
+ info("Attached stv0299!\n");
+ return 0;
+ }
+ return -EIO;
+}
+
+static int dw2102_tuner_attach(struct dvb_usb_adapter *adap)
+{
+ dvb_attach(dvb_pll_attach, adap->fe, 0x60,
+ &adap->dev->i2c_adap, DVB_PLL_OPERA1);
+ return 0;
+}
+
+static struct dvb_usb_rc_key dw2102_rc_keys[] = {
+ { 0xf8, 0x0a, KEY_Q }, /*power*/
+ { 0xf8, 0x0c, KEY_M }, /*mute*/
+ { 0xf8, 0x11, KEY_1 },
+ { 0xf8, 0x12, KEY_2 },
+ { 0xf8, 0x13, KEY_3 },
+ { 0xf8, 0x14, KEY_4 },
+ { 0xf8, 0x15, KEY_5 },
+ { 0xf8, 0x16, KEY_6 },
+ { 0xf8, 0x17, KEY_7 },
+ { 0xf8, 0x18, KEY_8 },
+ { 0xf8, 0x19, KEY_9 },
+ { 0xf8, 0x10, KEY_0 },
+ { 0xf8, 0x1c, KEY_PAGEUP }, /*ch+*/
+ { 0xf8, 0x0f, KEY_PAGEDOWN }, /*ch-*/
+ { 0xf8, 0x1a, KEY_O }, /*vol+*/
+ { 0xf8, 0x0e, KEY_Z }, /*vol-*/
+ { 0xf8, 0x04, KEY_R }, /*rec*/
+ { 0xf8, 0x09, KEY_D }, /*fav*/
+ { 0xf8, 0x08, KEY_BACKSPACE }, /*rewind*/
+ { 0xf8, 0x07, KEY_A }, /*fast*/
+ { 0xf8, 0x0b, KEY_P }, /*pause*/
+ { 0xf8, 0x02, KEY_ESC }, /*cancel*/
+ { 0xf8, 0x03, KEY_G }, /*tab*/
+ { 0xf8, 0x00, KEY_UP }, /*up*/
+ { 0xf8, 0x1f, KEY_ENTER }, /*ok*/
+ { 0xf8, 0x01, KEY_DOWN }, /*down*/
+ { 0xf8, 0x05, KEY_C }, /*cap*/
+ { 0xf8, 0x06, KEY_S }, /*stop*/
+ { 0xf8, 0x40, KEY_F }, /*full*/
+ { 0xf8, 0x1e, KEY_W }, /*tvmode*/
+ { 0xf8, 0x1b, KEY_B }, /*recall*/
+
+};
+
+
+
+static int dw2102_rc_query(struct dvb_usb_device *d, u32 *event, int *state)
+{
+ struct dw2102_state *st = d->priv;
+ u8 key[2];
+ struct i2c_msg msg[] = {
+ {.addr = DW2102_RC_QUERY, .flags = I2C_M_RD, .buf = key,
+ .len = 2},
+ };
+ int i;
+
+ *state = REMOTE_NO_KEY_PRESSED;
+ if (dw2102_i2c_transfer(&d->i2c_adap, msg, 1) == 1) {
+ for (i = 0; i < ARRAY_SIZE(dw2102_rc_keys); i++) {
+ if (dw2102_rc_keys[i].data == msg[0].buf[0]) {
+ *state = REMOTE_KEY_PRESSED;
+ *event = dw2102_rc_keys[i].event;
+ st->last_key_pressed =
+ dw2102_rc_keys[i].event;
+ break;
+ }
+ st->last_key_pressed = 0;
+ }
+ }
+ /* info("key: %x %x\n",key[0],key[1]); */
+ return 0;
+}
+
+static struct usb_device_id dw2102_table[] = {
+ {USB_DEVICE(USB_VID_CYPRESS, USB_PID_DW2102)},
+ {USB_DEVICE(USB_VID_CYPRESS, 0x2101)},
+ { }
+};
+
+MODULE_DEVICE_TABLE(usb, dw2102_table);
+
+static int dw2102_load_firmware(struct usb_device *dev,
+ const struct firmware *frmwr)
+{
+ u8 *b, *p;
+ int ret = 0, i;
+ u8 reset;
+ u8 reset16 [] = {0, 0, 0, 0, 0, 0, 0};
+ const struct firmware *fw;
+ const char *filename = "dvb-usb-dw2101.fw";
+ switch (dev->descriptor.idProduct) {
+ case 0x2101:
+ ret = request_firmware(&fw, filename, &dev->dev);
+ if (ret != 0) {
+ err("did not find the firmware file. (%s) "
+ "Please see linux/Documentation/dvb/ for more details "
+ "on firmware-problems.", filename);
+ return ret;
+ }
+ break;
+ case USB_PID_DW2102:
+ fw = frmwr;
+ break;
+ }
+ info("start downloading DW2102 firmware");
+ p = kmalloc(fw->size, GFP_KERNEL);
+ reset = 1;
+ /*stop the CPU*/
+ dw2102_op_rw(dev, 0xa0, 0x7f92, &reset, 1, DW2102_WRITE_MSG);
+ dw2102_op_rw(dev, 0xa0, 0xe600, &reset, 1, DW2102_WRITE_MSG);
+
+ if (p != NULL) {
+ memcpy(p, fw->data, fw->size);
+ for (i = 0; i < fw->size; i += 0x40) {
+ b = (u8 *) p + i;
+ if (dw2102_op_rw
+ (dev, 0xa0, i, b , 0x40,
+ DW2102_WRITE_MSG) != 0x40
+ ) {
+ err("error while transferring firmware");
+ ret = -EINVAL;
+ break;
+ }
+ }
+ /* restart the CPU */
+ reset = 0;
+ if (ret || dw2102_op_rw
+ (dev, 0xa0, 0x7f92, &reset, 1,
+ DW2102_WRITE_MSG) != 1) {
+ err("could not restart the USB controller CPU.");
+ ret = -EINVAL;
+ }
+ if (ret || dw2102_op_rw
+ (dev, 0xa0, 0xe600, &reset, 1,
+ DW2102_WRITE_MSG) != 1) {
+ err("could not restart the USB controller CPU.");
+ ret = -EINVAL;
+ }
+ /* init registers */
+ switch (dev->descriptor.idProduct) {
+ case USB_PID_DW2102:
+ dw2102_op_rw
+ (dev, 0xbf, 0x0040, &reset, 0,
+ DW2102_WRITE_MSG);
+ dw2102_op_rw
+ (dev, 0xb9, 0x0000, &reset16[0], 2,
+ DW2102_READ_MSG);
+ break;
+ case 0x2101:
+ dw2102_op_rw
+ (dev, 0xbc, 0x0030, &reset16[0], 2,
+ DW2102_READ_MSG);
+ dw2102_op_rw
+ (dev, 0xba, 0x0000, &reset16[0], 7,
+ DW2102_READ_MSG);
+ dw2102_op_rw
+ (dev, 0xba, 0x0000, &reset16[0], 7,
+ DW2102_READ_MSG);
+ dw2102_op_rw
+ (dev, 0xb9, 0x0000, &reset16[0], 2,
+ DW2102_READ_MSG);
+ break;
+ }
+ kfree(p);
+ }
+ return ret;
+}
+
+static struct dvb_usb_device_properties dw2102_properties = {
+ .caps = DVB_USB_IS_AN_I2C_ADAPTER,
+ .usb_ctrl = DEVICE_SPECIFIC,
+ .firmware = "dvb-usb-dw2102.fw",
+ .size_of_priv = sizeof(struct dw2102_state),
+ .no_reconnect = 1,
+
+ .i2c_algo = &dw2102_i2c_algo,
+ .rc_key_map = dw2102_rc_keys,
+ .rc_key_map_size = ARRAY_SIZE(dw2102_rc_keys),
+ .rc_interval = 150,
+ .rc_query = dw2102_rc_query,
+
+ .generic_bulk_ctrl_endpoint = 0x81,
+ /* parameter for the MPEG2-data transfer */
+ .num_adapters = 1,
+ .download_firmware = dw2102_load_firmware,
+ .adapter = {
+ {
+ .frontend_attach = dw2102_frontend_attach,
+ .streaming_ctrl = NULL,
+ .tuner_attach = dw2102_tuner_attach,
+ .stream = {
+ .type = USB_BULK,
+ .count = 8,
+ .endpoint = 0x82,
+ .u = {
+ .bulk = {
+ .buffersize = 4096,
+ }
+ }
+ },
+ }
+ },
+ .num_device_descs = 2,
+ .devices = {
+ {"DVBWorld DVB-S 2102 USB2.0",
+ {&dw2102_table[0], NULL},
+ {NULL},
+ },
+ {"DVBWorld DVB-S 2101 USB2.0",
+ {&dw2102_table[1], NULL},
+ {NULL},
+ },
+ }
+};
+
+static int dw2102_probe(struct usb_interface *intf,
+ const struct usb_device_id *id)
+{
+ return dvb_usb_device_init(intf, &dw2102_properties,
+ THIS_MODULE, NULL, adapter_nr);
+}
+
+static struct usb_driver dw2102_driver = {
+ .name = "dw2102",
+ .probe = dw2102_probe,
+ .disconnect = dvb_usb_device_exit,
+ .id_table = dw2102_table,
+};
+
+static int __init dw2102_module_init(void)
+{
+ int ret = usb_register(&dw2102_driver);
+ if (ret)
+ err("usb_register failed. Error number %d", ret);
+
+ return ret;
+}
+
+static void __exit dw2102_module_exit(void)
+{
+ usb_deregister(&dw2102_driver);
+}
+
+module_init(dw2102_module_init);
+module_exit(dw2102_module_exit);
+
+MODULE_AUTHOR("Igor M. Liplianin (c) liplianin@me.by");
+MODULE_DESCRIPTION("Driver for DVBWorld DVB-S 2101 2102 USB2.0 device");
+MODULE_VERSION("0.1");
+MODULE_LICENSE("GPL");
--- /dev/null
+#ifndef _DW2102_H_
+#define _DW2102_H_
+
+#define DVB_USB_LOG_PREFIX "dw2102"
+#include "dvb-usb.h"
+
+extern int dvb_usb_dw2102_debug;
+#define deb_xfer(args...) dprintk(dvb_usb_dw2102_debug, 0x02, args)
+#endif
config DVB_SP8870
tristate "Spase sp8870 based"
- depends on DVB_CORE && I2C && HOTPLUG
+ depends on DVB_CORE && I2C
default m if DVB_FE_CUSTOMISE
- select FW_LOADER
help
A DVB-T tuner module. Say Y when you want to support this frontend.
config DVB_SP887X
tristate "Spase sp887x based"
- depends on DVB_CORE && I2C && HOTPLUG
+ depends on DVB_CORE && I2C
default m if DVB_FE_CUSTOMISE
- select FW_LOADER
help
A DVB-T tuner module. Say Y when you want to support this frontend.
help
A DVB-T tuner module. Say Y when you want to support this frontend.
+config DVB_DRX397XD
+ tristate "Micronas DRX3975D/DRX3977D based"
+ depends on DVB_CORE && I2C && HOTPLUG
+ default m if DVB_FE_CUSTOMISE
+ select FW_LOADER
+ help
+ A DVB-T tuner module. Say Y when you want to support this frontend.
+
+ TODO:
+ This driver needs external firmware. Please use the command
+ "<kerneldir>/Documentation/dvb/get_dvb_firmware drx397xD" to
+ download/extract them, and then copy them to /usr/lib/hotplug/firmware
+ or /lib/firmware (depending on configuration of firmware hotplug).
+
config DVB_L64781
tristate "LSI L64781"
depends on DVB_CORE && I2C
config DVB_TDA1004X
tristate "Philips TDA10045H/TDA10046H based"
- depends on DVB_CORE && I2C && HOTPLUG
+ depends on DVB_CORE && I2C
default m if DVB_FE_CUSTOMISE
- select FW_LOADER
help
A DVB-T tuner module. Say Y when you want to support this frontend.
config DVB_TDA10048
tristate "Philips TDA10048HN based"
- depends on DVB_CORE && I2C && HOTPLUG
+ depends on DVB_CORE && I2C
default m if DVB_FE_CUSTOMISE
- select FW_LOADER
help
A DVB-T tuner module. Say Y when you want to support this frontend.
config DVB_NXT200X
tristate "NxtWave Communications NXT2002/NXT2004 based"
- depends on DVB_CORE && I2C && HOTPLUG
+ depends on DVB_CORE && I2C
default m if DVB_FE_CUSTOMISE
- select FW_LOADER
help
An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
to support this frontend.
config DVB_OR51211
tristate "Oren OR51211 based"
- depends on DVB_CORE && I2C && HOTPLUG
+ depends on DVB_CORE && I2C
default m if DVB_FE_CUSTOMISE
- select FW_LOADER
help
An ATSC 8VSB tuner module. Say Y when you want to support this frontend.
config DVB_OR51132
tristate "Oren OR51132 based"
- depends on DVB_CORE && I2C && HOTPLUG
+ depends on DVB_CORE && I2C
default m if DVB_FE_CUSTOMISE
- select FW_LOADER
help
An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
to support this frontend.
config DVB_BCM3510
tristate "Broadcom BCM3510"
- depends on DVB_CORE && I2C && HOTPLUG
+ depends on DVB_CORE && I2C
default m if DVB_FE_CUSTOMISE
- select FW_LOADER
help
An ATSC 8VSB/16VSB and QAM64/256 tuner module. Say Y when you want to
support this frontend.
obj-$(CONFIG_DVB_MT352) += mt352.o
obj-$(CONFIG_DVB_ZL10353) += zl10353.o
obj-$(CONFIG_DVB_CX22702) += cx22702.o
+obj-$(CONFIG_DVB_DRX397XD) += drx397xD.o
obj-$(CONFIG_DVB_TDA10021) += tda10021.o
obj-$(CONFIG_DVB_TDA10023) += tda10023.o
obj-$(CONFIG_DVB_STV0297) += stv0297.o
--- /dev/null
+/*
+ * Driver for Micronas drx397xD demodulator
+ *
+ * Copyright (C) 2007 Henk Vergonet <Henk.Vergonet@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define DEBUG /* uncomment if you want debugging output */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/firmware.h>
+#include <asm/div64.h>
+
+#include "dvb_frontend.h"
+#include "drx397xD.h"
+
+static const char mod_name[] = "drx397xD";
+
+#define MAX_CLOCK_DRIFT 200 /* maximal 200 PPM allowed */
+
+#define F_SET_0D0h 1
+#define F_SET_0D4h 2
+
+typedef enum fw_ix {
+#define _FW_ENTRY(a, b) b
+#include "drx397xD_fw.h"
+} fw_ix_t;
+
+/* chip specifics */
+struct drx397xD_state {
+ struct i2c_adapter *i2c;
+ struct dvb_frontend frontend;
+ struct drx397xD_config config;
+ fw_ix_t chip_rev;
+ int flags;
+ u32 bandwidth_parm; /* internal bandwidth conversions */
+ u32 f_osc; /* w90: actual osc frequency [Hz] */
+};
+
+/*******************************************************************************
+ * Firmware
+ ******************************************************************************/
+
+static const char *blob_name[] = {
+#define _BLOB_ENTRY(a, b) a
+#include "drx397xD_fw.h"
+};
+
+typedef enum blob_ix {
+#define _BLOB_ENTRY(a, b) b
+#include "drx397xD_fw.h"
+} blob_ix_t;
+
+static struct {
+ const char *name;
+ const struct firmware *file;
+ rwlock_t lock;
+ int refcnt;
+ const u8 *data[ARRAY_SIZE(blob_name)];
+} fw[] = {
+#define _FW_ENTRY(a, b) { \
+ .name = a, \
+ .file = 0, \
+ .lock = RW_LOCK_UNLOCKED, \
+ .refcnt = 0, \
+ .data = { } }
+#include "drx397xD_fw.h"
+};
+
+/* use only with writer lock aquired */
+static void _drx_release_fw(struct drx397xD_state *s, fw_ix_t ix)
+{
+ memset(&fw[ix].data[0], 0, sizeof(fw[0].data));
+ if (fw[ix].file)
+ release_firmware(fw[ix].file);
+}
+
+static void drx_release_fw(struct drx397xD_state *s)
+{
+ fw_ix_t ix = s->chip_rev;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ write_lock(&fw[ix].lock);
+ if (fw[ix].refcnt) {
+ fw[ix].refcnt--;
+ if (fw[ix].refcnt == 0)
+ _drx_release_fw(s, ix);
+ }
+ write_unlock(&fw[ix].lock);
+}
+
+static int drx_load_fw(struct drx397xD_state *s, fw_ix_t ix)
+{
+ const u8 *data;
+ size_t size, len;
+ int i = 0, j, rc = -EINVAL;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ if (ix < 0 || ix >= ARRAY_SIZE(fw))
+ return -EINVAL;
+ s->chip_rev = ix;
+
+ write_lock(&fw[ix].lock);
+ if (fw[ix].file) {
+ rc = 0;
+ goto exit_ok;
+ }
+ memset(&fw[ix].data[0], 0, sizeof(fw[0].data));
+
+ if (request_firmware(&fw[ix].file, fw[ix].name, &s->i2c->dev) != 0) {
+ printk(KERN_ERR "%s: Firmware \"%s\" not available\n",
+ mod_name, fw[ix].name);
+ rc = -ENOENT;
+ goto exit_err;
+ }
+
+ if (!fw[ix].file->data || fw[ix].file->size < 10)
+ goto exit_corrupt;
+
+ data = fw[ix].file->data;
+ size = fw[ix].file->size;
+
+ if (data[i++] != 2) /* check firmware version */
+ goto exit_corrupt;
+
+ do {
+ switch (data[i++]) {
+ case 0x00: /* bytecode */
+ if (i >= size)
+ break;
+ i += data[i];
+ case 0x01: /* reset */
+ case 0x02: /* sleep */
+ i++;
+ break;
+ case 0xfe: /* name */
+ len = strnlen(&data[i], size - i);
+ if (i + len + 1 >= size)
+ goto exit_corrupt;
+ if (data[i + len + 1] != 0)
+ goto exit_corrupt;
+ for (j = 0; j < ARRAY_SIZE(blob_name); j++) {
+ if (strcmp(blob_name[j], &data[i]) == 0) {
+ fw[ix].data[j] = &data[i + len + 1];
+ pr_debug("Loading %s\n", blob_name[j]);
+ }
+ }
+ i += len + 1;
+ break;
+ case 0xff: /* file terminator */
+ if (i == size) {
+ rc = 0;
+ goto exit_ok;
+ }
+ default:
+ goto exit_corrupt;
+ }
+ } while (i < size);
+ exit_corrupt:
+ printk(KERN_ERR "%s: Firmware is corrupt\n", mod_name);
+ exit_err:
+ _drx_release_fw(s, ix);
+ fw[ix].refcnt--;
+ exit_ok:
+ fw[ix].refcnt++;
+ write_unlock(&fw[ix].lock);
+ return rc;
+}
+
+/*******************************************************************************
+ * i2c bus IO
+ ******************************************************************************/
+
+static int write_fw(struct drx397xD_state *s, blob_ix_t ix)
+{
+ struct i2c_msg msg = {.addr = s->config.demod_address,.flags = 0 };
+ const u8 *data;
+ int len, rc = 0, i = 0;
+
+ if (ix < 0 || ix >= ARRAY_SIZE(blob_name)) {
+ pr_debug("%s drx_fw_ix_t out of range\n", __FUNCTION__);
+ return -EINVAL;
+ }
+ pr_debug("%s %s\n", __FUNCTION__, blob_name[ix]);
+
+ read_lock(&fw[s->chip_rev].lock);
+ data = fw[s->chip_rev].data[ix];
+ if (!data) {
+ rc = -EINVAL;
+ goto exit_rc;
+ }
+
+ for (;;) {
+ switch (data[i++]) {
+ case 0: /* bytecode */
+ len = data[i++];
+ msg.len = len;
+ msg.buf = (__u8 *) &data[i];
+ if (i2c_transfer(s->i2c, &msg, 1) != 1) {
+ rc = -EIO;
+ goto exit_rc;
+ }
+ i += len;
+ break;
+ case 1: /* reset */
+ case 2: /* sleep */
+ i++;
+ break;
+ default:
+ goto exit_rc;
+ }
+ }
+ exit_rc:
+ read_unlock(&fw[s->chip_rev].lock);
+ return 0;
+}
+
+/* Function is not endian safe, use the RD16 wrapper below */
+static int _read16(struct drx397xD_state *s, u32 i2c_adr)
+{
+ int rc;
+ u8 a[4];
+ u16 v;
+ struct i2c_msg msg[2] = {
+ {
+ .addr = s->config.demod_address,
+ .flags = 0,
+ .buf = a,
+ .len = sizeof(a)
+ }
+ , {
+ .addr = s->config.demod_address,
+ .flags = I2C_M_RD,
+ .buf = (u8 *) & v,
+ .len = sizeof(v)
+ }
+ };
+
+ *(u32 *) a = i2c_adr;
+
+ rc = i2c_transfer(s->i2c, msg, 2);
+ if (rc != 2)
+ return -EIO;
+
+ return le16_to_cpu(v);
+}
+
+/* Function is not endian safe, use the WR16.. wrappers below */
+static int _write16(struct drx397xD_state *s, u32 i2c_adr, u16 val)
+{
+ u8 a[6];
+ int rc;
+ struct i2c_msg msg = {
+ .addr = s->config.demod_address,
+ .flags = 0,
+ .buf = a,
+ .len = sizeof(a)
+ };
+
+ *(u32 *) a = i2c_adr;
+ *(u16 *) & a[4] = val;
+
+ rc = i2c_transfer(s->i2c, &msg, 1);
+ if (rc != 1)
+ return -EIO;
+ return 0;
+}
+
+#define WR16(ss,adr, val) \
+ _write16(ss, I2C_ADR_C0(adr), cpu_to_le16(val))
+#define WR16_E0(ss,adr, val) \
+ _write16(ss, I2C_ADR_E0(adr), cpu_to_le16(val))
+#define RD16(ss,adr) \
+ _read16(ss, I2C_ADR_C0(adr))
+
+#define EXIT_RC( cmd ) if ( (rc = (cmd)) < 0) goto exit_rc
+
+/*******************************************************************************
+ * Tuner callback
+ ******************************************************************************/
+
+static int PLL_Set(struct drx397xD_state *s,
+ struct dvb_frontend_parameters *fep, int *df_tuner)
+{
+ struct dvb_frontend *fe = &s->frontend;
+ u32 f_tuner, f = fep->frequency;
+ int rc;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ if ((f > s->frontend.ops.tuner_ops.info.frequency_max) ||
+ (f < s->frontend.ops.tuner_ops.info.frequency_min))
+ return -EINVAL;
+
+ *df_tuner = 0;
+ if (!s->frontend.ops.tuner_ops.set_params ||
+ !s->frontend.ops.tuner_ops.get_frequency)
+ return -ENOSYS;
+
+ rc = s->frontend.ops.tuner_ops.set_params(fe, fep);
+ if (rc < 0)
+ return rc;
+
+ rc = s->frontend.ops.tuner_ops.get_frequency(fe, &f_tuner);
+ if (rc < 0)
+ return rc;
+
+ *df_tuner = f_tuner - f;
+ pr_debug("%s requested %d [Hz] tuner %d [Hz]\n", __FUNCTION__, f,
+ f_tuner);
+
+ return 0;
+}
+
+/*******************************************************************************
+ * Demodulator helper functions
+ ******************************************************************************/
+
+static int SC_WaitForReady(struct drx397xD_state *s)
+{
+ int cnt = 1000;
+ int rc;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ while (cnt--) {
+ rc = RD16(s, 0x820043);
+ if (rc == 0)
+ return 0;
+ }
+ return -1;
+}
+
+static int SC_SendCommand(struct drx397xD_state *s, int cmd)
+{
+ int rc;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ WR16(s, 0x820043, cmd);
+ SC_WaitForReady(s);
+ rc = RD16(s, 0x820042);
+ if ((rc & 0xffff) == 0xffff)
+ return -1;
+ return 0;
+}
+
+static int HI_Command(struct drx397xD_state *s, u16 cmd)
+{
+ int rc, cnt = 1000;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ rc = WR16(s, 0x420032, cmd);
+ if (rc < 0)
+ return rc;
+
+ do {
+ rc = RD16(s, 0x420032);
+ if (rc == 0) {
+ rc = RD16(s, 0x420031);
+ return rc;
+ }
+ if (rc < 0)
+ return rc;
+ } while (--cnt);
+ return rc;
+}
+
+static int HI_CfgCommand(struct drx397xD_state *s)
+{
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ WR16(s, 0x420033, 0x3973);
+ WR16(s, 0x420034, s->config.w50); // code 4, log 4
+ WR16(s, 0x420035, s->config.w52); // code 15, log 9
+ WR16(s, 0x420036, s->config.demod_address << 1);
+ WR16(s, 0x420037, s->config.w56); // code (set_i2c ?? initX 1 ), log 1
+// WR16(s, 0x420033, 0x3973);
+ if ((s->config.w56 & 8) == 0)
+ return HI_Command(s, 3);
+ return WR16(s, 0x420032, 0x3);
+}
+
+static const u8 fastIncrDecLUT_15273[] = {
+ 0x0e, 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x12, 0x13, 0x14,
+ 0x15, 0x16, 0x17, 0x18, 0x1a, 0x1b, 0x1c, 0x1d, 0x1f
+};
+
+static const u8 slowIncrDecLUT_15272[] = {
+ 3, 4, 4, 5, 6
+};
+
+static int SetCfgIfAgc(struct drx397xD_state *s, struct drx397xD_CfgIfAgc *agc)
+{
+ u16 w06 = agc->w06;
+ u16 w08 = agc->w08;
+ u16 w0A = agc->w0A;
+ u16 w0C = agc->w0C;
+ int quot, rem, i, rc = -EINVAL;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ if (agc->w04 > 0x3ff)
+ goto exit_rc;
+
+ if (agc->d00 == 1) {
+ EXIT_RC(RD16(s, 0x0c20010));
+ rc &= ~0x10;
+ EXIT_RC(WR16(s, 0x0c20010, rc));
+ return WR16(s, 0x0c20030, agc->w04 & 0x7ff);
+ }
+
+ if (agc->d00 != 0)
+ goto exit_rc;
+ if (w0A < w08)
+ goto exit_rc;
+ if (w0A > 0x3ff)
+ goto exit_rc;
+ if (w0C > 0x3ff)
+ goto exit_rc;
+ if (w06 > 0x3ff)
+ goto exit_rc;
+
+ EXIT_RC(RD16(s, 0x0c20010));
+ rc |= 0x10;
+ EXIT_RC(WR16(s, 0x0c20010, rc));
+
+ EXIT_RC(WR16(s, 0x0c20025, (w06 >> 1) & 0x1ff));
+ EXIT_RC(WR16(s, 0x0c20031, (w0A - w08) >> 1));
+ EXIT_RC(WR16(s, 0x0c20032, ((w0A + w08) >> 1) - 0x1ff));
+
+ quot = w0C / 113;
+ rem = w0C % 113;
+ if (quot <= 8) {
+ quot = 8 - quot;
+ } else {
+ quot = 0;
+ rem += 113;
+ }
+
+ EXIT_RC(WR16(s, 0x0c20024, quot));
+
+ i = fastIncrDecLUT_15273[rem / 8];
+ EXIT_RC(WR16(s, 0x0c2002d, i));
+ EXIT_RC(WR16(s, 0x0c2002e, i));
+
+ i = slowIncrDecLUT_15272[rem / 28];
+ EXIT_RC(WR16(s, 0x0c2002b, i));
+ rc = WR16(s, 0x0c2002c, i);
+ exit_rc:
+ return rc;
+}
+
+static int SetCfgRfAgc(struct drx397xD_state *s, struct drx397xD_CfgRfAgc *agc)
+{
+ u16 w04 = agc->w04;
+ u16 w06 = agc->w06;
+ int rc = -1;
+
+ pr_debug("%s %d 0x%x 0x%x\n", __FUNCTION__, agc->d00, w04, w06);
+
+ if (w04 > 0x3ff)
+ goto exit_rc;
+
+ switch (agc->d00) {
+ case 1:
+ if (w04 == 0x3ff)
+ w04 = 0x400;
+
+ EXIT_RC(WR16(s, 0x0c20036, w04));
+ s->config.w9C &= ~2;
+ EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
+ EXIT_RC(RD16(s, 0x0c20010));
+ rc &= 0xbfdf;
+ EXIT_RC(WR16(s, 0x0c20010, rc));
+ EXIT_RC(RD16(s, 0x0c20013));
+ rc &= ~2;
+ break;
+ case 0:
+ // loc_8000659
+ s->config.w9C &= ~2;
+ EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
+ EXIT_RC(RD16(s, 0x0c20010));
+ rc &= 0xbfdf;
+ rc |= 0x4000;
+ EXIT_RC(WR16(s, 0x0c20010, rc));
+ EXIT_RC(WR16(s, 0x0c20051, (w06 >> 4) & 0x3f));
+ EXIT_RC(RD16(s, 0x0c20013));
+ rc &= ~2;
+ break;
+ default:
+ s->config.w9C |= 2;
+ EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
+ EXIT_RC(RD16(s, 0x0c20010));
+ rc &= 0xbfdf;
+ EXIT_RC(WR16(s, 0x0c20010, rc));
+
+ EXIT_RC(WR16(s, 0x0c20036, 0));
+
+ EXIT_RC(RD16(s, 0x0c20013));
+ rc |= 2;
+ }
+ rc = WR16(s, 0x0c20013, rc);
+ exit_rc:
+ return rc;
+}
+
+static int GetLockStatus(struct drx397xD_state *s, int *lockstat)
+{
+ int rc;
+
+ *lockstat = 0;
+
+ rc = RD16(s, 0x082004b);
+ if (rc < 0)
+ return rc;
+
+ if (s->config.d60 != 2)
+ return 0;
+
+ if ((rc & 7) == 7)
+ *lockstat |= 1;
+ if ((rc & 3) == 3)
+ *lockstat |= 2;
+ if (rc & 1)
+ *lockstat |= 4;
+ return 0;
+}
+
+static int CorrectSysClockDeviation(struct drx397xD_state *s)
+{
+ int rc = -EINVAL;
+ int lockstat;
+ u32 clk, clk_limit;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ if (s->config.d5C == 0) {
+ EXIT_RC(WR16(s, 0x08200e8, 0x010));
+ EXIT_RC(WR16(s, 0x08200e9, 0x113));
+ s->config.d5C = 1;
+ return rc;
+ }
+ if (s->config.d5C != 1)
+ goto exit_rc;
+
+ rc = RD16(s, 0x0820048);
+
+ rc = GetLockStatus(s, &lockstat);
+ if (rc < 0)
+ goto exit_rc;
+ if ((lockstat & 1) == 0)
+ goto exit_rc;
+
+ EXIT_RC(WR16(s, 0x0420033, 0x200));
+ EXIT_RC(WR16(s, 0x0420034, 0xc5));
+ EXIT_RC(WR16(s, 0x0420035, 0x10));
+ EXIT_RC(WR16(s, 0x0420036, 0x1));
+ EXIT_RC(WR16(s, 0x0420037, 0xa));
+ EXIT_RC(HI_Command(s, 6));
+ EXIT_RC(RD16(s, 0x0420040));
+ clk = rc;
+ EXIT_RC(RD16(s, 0x0420041));
+ clk |= rc << 16;
+
+ if (clk <= 0x26ffff)
+ goto exit_rc;
+ if (clk > 0x610000)
+ goto exit_rc;
+
+ if (!s->bandwidth_parm)
+ return -EINVAL;
+
+ /* round & convert to Hz */
+ clk = ((u64) (clk + 0x800000) * s->bandwidth_parm + (1 << 20)) >> 21;
+ clk_limit = s->config.f_osc * MAX_CLOCK_DRIFT / 1000;
+
+ if (clk - s->config.f_osc * 1000 + clk_limit <= 2 * clk_limit) {
+ s->f_osc = clk;
+ pr_debug("%s: osc %d %d [Hz]\n", __FUNCTION__,
+ s->config.f_osc * 1000, clk - s->config.f_osc * 1000);
+ }
+ rc = WR16(s, 0x08200e8, 0);
+ exit_rc:
+ return rc;
+}
+
+static int ConfigureMPEGOutput(struct drx397xD_state *s, int type)
+{
+ int rc, si, bp;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ si = s->config.wA0;
+ if (s->config.w98 == 0) {
+ si |= 1;
+ bp = 0;
+ } else {
+ si &= ~1;
+ bp = 0x200;
+ }
+ if (s->config.w9A == 0) {
+ si |= 0x80;
+ } else {
+ si &= ~0x80;
+ }
+
+ EXIT_RC(WR16(s, 0x2150045, 0));
+ EXIT_RC(WR16(s, 0x2150010, si));
+ EXIT_RC(WR16(s, 0x2150011, bp));
+ rc = WR16(s, 0x2150012, (type == 0 ? 0xfff : 0));
+ exit_rc:
+ return rc;
+}
+
+static int drx_tune(struct drx397xD_state *s,
+ struct dvb_frontend_parameters *fep)
+{
+ u16 v22 = 0;
+ u16 v1C = 0;
+ u16 v1A = 0;
+ u16 v18 = 0;
+ u32 edi = 0, ebx = 0, ebp = 0, edx = 0;
+ u16 v20 = 0, v1E = 0, v16 = 0, v14 = 0, v12 = 0, v10 = 0, v0E = 0;
+
+ int rc, df_tuner;
+ int a, b, c, d;
+ pr_debug("%s %d\n", __FUNCTION__, s->config.d60);
+
+ if (s->config.d60 != 2)
+ goto set_tuner;
+ rc = CorrectSysClockDeviation(s);
+ if (rc < 0)
+ goto set_tuner;
+
+ s->config.d60 = 1;
+ rc = ConfigureMPEGOutput(s, 0);
+ if (rc < 0)
+ goto set_tuner;
+ set_tuner:
+
+ rc = PLL_Set(s, fep, &df_tuner);
+ if (rc < 0) {
+ printk(KERN_ERR "Error in pll_set\n");
+ goto exit_rc;
+ }
+ msleep(200);
+
+ a = rc = RD16(s, 0x2150016);
+ if (rc < 0)
+ goto exit_rc;
+ b = rc = RD16(s, 0x2150010);
+ if (rc < 0)
+ goto exit_rc;
+ c = rc = RD16(s, 0x2150034);
+ if (rc < 0)
+ goto exit_rc;
+ d = rc = RD16(s, 0x2150035);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x2150014, c);
+ rc = WR16(s, 0x2150015, d);
+ rc = WR16(s, 0x2150010, 0);
+ rc = WR16(s, 0x2150000, 2);
+ rc = WR16(s, 0x2150036, 0x0fff);
+ rc = WR16(s, 0x2150016, a);
+
+ rc = WR16(s, 0x2150010, 2);
+ rc = WR16(s, 0x2150007, 0);
+ rc = WR16(s, 0x2150000, 1);
+ rc = WR16(s, 0x2110000, 0);
+ rc = WR16(s, 0x0800000, 0);
+ rc = WR16(s, 0x2800000, 0);
+ rc = WR16(s, 0x2110010, 0x664);
+
+ rc = write_fw(s, DRXD_ResetECRAM);
+ rc = WR16(s, 0x2110000, 1);
+
+ rc = write_fw(s, DRXD_InitSC);
+ if (rc < 0)
+ goto exit_rc;
+
+ rc = SetCfgIfAgc(s, &s->config.ifagc);
+ if (rc < 0)
+ goto exit_rc;
+
+ rc = SetCfgRfAgc(s, &s->config.rfagc);
+ if (rc < 0)
+ goto exit_rc;
+
+ if (fep->u.ofdm.transmission_mode != TRANSMISSION_MODE_2K)
+ v22 = 1;
+ switch (fep->u.ofdm.transmission_mode) {
+ case TRANSMISSION_MODE_8K:
+ edi = 1;
+ if (s->chip_rev == DRXD_FW_B1)
+ break;
+
+ rc = WR16(s, 0x2010010, 0);
+ if (rc < 0)
+ break;
+ v1C = 0x63;
+ v1A = 0x53;
+ v18 = 0x43;
+ break;
+ default:
+ edi = 0;
+ if (s->chip_rev == DRXD_FW_B1)
+ break;
+
+ rc = WR16(s, 0x2010010, 1);
+ if (rc < 0)
+ break;
+
+ v1C = 0x61;
+ v1A = 0x47;
+ v18 = 0x41;
+ }
+
+ switch (fep->u.ofdm.guard_interval) {
+ case GUARD_INTERVAL_1_4:
+ edi |= 0x0c;
+ break;
+ case GUARD_INTERVAL_1_8:
+ edi |= 0x08;
+ break;
+ case GUARD_INTERVAL_1_16:
+ edi |= 0x04;
+ break;
+ case GUARD_INTERVAL_1_32:
+ break;
+ default:
+ v22 |= 2;
+ }
+
+ ebx = 0;
+ ebp = 0;
+ v20 = 0;
+ v1E = 0;
+ v16 = 0;
+ v14 = 0;
+ v12 = 0;
+ v10 = 0;
+ v0E = 0;
+
+ switch (fep->u.ofdm.hierarchy_information) {
+ case HIERARCHY_1:
+ edi |= 0x40;
+ if (s->chip_rev == DRXD_FW_B1)
+ break;
+ rc = WR16(s, 0x1c10047, 1);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x2010012, 1);
+ if (rc < 0)
+ goto exit_rc;
+ ebx = 0x19f;
+ ebp = 0x1fb;
+ v20 = 0x0c0;
+ v1E = 0x195;
+ v16 = 0x1d6;
+ v14 = 0x1ef;
+ v12 = 4;
+ v10 = 5;
+ v0E = 5;
+ break;
+ case HIERARCHY_2:
+ edi |= 0x80;
+ if (s->chip_rev == DRXD_FW_B1)
+ break;
+ rc = WR16(s, 0x1c10047, 2);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x2010012, 2);
+ if (rc < 0)
+ goto exit_rc;
+ ebx = 0x08f;
+ ebp = 0x12f;
+ v20 = 0x0c0;
+ v1E = 0x11e;
+ v16 = 0x1d6;
+ v14 = 0x15e;
+ v12 = 4;
+ v10 = 5;
+ v0E = 5;
+ break;
+ case HIERARCHY_4:
+ edi |= 0xc0;
+ if (s->chip_rev == DRXD_FW_B1)
+ break;
+ rc = WR16(s, 0x1c10047, 3);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x2010012, 3);
+ if (rc < 0)
+ goto exit_rc;
+ ebx = 0x14d;
+ ebp = 0x197;
+ v20 = 0x0c0;
+ v1E = 0x1ce;
+ v16 = 0x1d6;
+ v14 = 0x11a;
+ v12 = 4;
+ v10 = 6;
+ v0E = 5;
+ break;
+ default:
+ v22 |= 8;
+ if (s->chip_rev == DRXD_FW_B1)
+ break;
+ rc = WR16(s, 0x1c10047, 0);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x2010012, 0);
+ if (rc < 0)
+ goto exit_rc;
+ // QPSK QAM16 QAM64
+ ebx = 0x19f; // 62
+ ebp = 0x1fb; // 15
+ v20 = 0x16a; // 62
+ v1E = 0x195; // 62
+ v16 = 0x1bb; // 15
+ v14 = 0x1ef; // 15
+ v12 = 5; // 16
+ v10 = 5; // 16
+ v0E = 5; // 16
+ }
+
+ switch (fep->u.ofdm.constellation) {
+ default:
+ v22 |= 4;
+ case QPSK:
+ if (s->chip_rev == DRXD_FW_B1)
+ break;
+
+ rc = WR16(s, 0x1c10046, 0);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x2010011, 0);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x201001a, 0x10);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x201001b, 0);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x201001c, 0);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x1c10062, v20);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x1c1002a, v1C);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x1c10015, v16);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x1c10016, v12);
+ if (rc < 0)
+ goto exit_rc;
+ break;
+ case QAM_16:
+ edi |= 0x10;
+ if (s->chip_rev == DRXD_FW_B1)
+ break;
+
+ rc = WR16(s, 0x1c10046, 1);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x2010011, 1);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x201001a, 0x10);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x201001b, 4);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x201001c, 0);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x1c10062, v1E);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x1c1002a, v1A);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x1c10015, v14);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x1c10016, v10);
+ if (rc < 0)
+ goto exit_rc;
+ break;
+ case QAM_64:
+ edi |= 0x20;
+ rc = WR16(s, 0x1c10046, 2);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x2010011, 2);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x201001a, 0x20);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x201001b, 8);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x201001c, 2);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x1c10062, ebx);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x1c1002a, v18);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x1c10015, ebp);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x1c10016, v0E);
+ if (rc < 0)
+ goto exit_rc;
+ break;
+ }
+
+ if (s->config.s20d24 == 1) {
+ rc = WR16(s, 0x2010013, 0);
+ } else {
+ rc = WR16(s, 0x2010013, 1);
+ edi |= 0x1000;
+ }
+
+ switch (fep->u.ofdm.code_rate_HP) {
+ default:
+ v22 |= 0x10;
+ case FEC_1_2:
+ if (s->chip_rev == DRXD_FW_B1)
+ break;
+ rc = WR16(s, 0x2090011, 0);
+ break;
+ case FEC_2_3:
+ edi |= 0x200;
+ if (s->chip_rev == DRXD_FW_B1)
+ break;
+ rc = WR16(s, 0x2090011, 1);
+ break;
+ case FEC_3_4:
+ edi |= 0x400;
+ if (s->chip_rev == DRXD_FW_B1)
+ break;
+ rc = WR16(s, 0x2090011, 2);
+ break;
+ case FEC_5_6: /* 5 */
+ edi |= 0x600;
+ if (s->chip_rev == DRXD_FW_B1)
+ break;
+ rc = WR16(s, 0x2090011, 3);
+ break;
+ case FEC_7_8: /* 7 */
+ edi |= 0x800;
+ if (s->chip_rev == DRXD_FW_B1)
+ break;
+ rc = WR16(s, 0x2090011, 4);
+ break;
+ };
+ if (rc < 0)
+ goto exit_rc;
+
+ switch (fep->u.ofdm.bandwidth) {
+ default:
+ rc = -EINVAL;
+ goto exit_rc;
+ case BANDWIDTH_8_MHZ: /* 0 */
+ case BANDWIDTH_AUTO:
+ rc = WR16(s, 0x0c2003f, 0x32);
+ s->bandwidth_parm = ebx = 0x8b8249; // 9142857
+ edx = 0;
+ break;
+ case BANDWIDTH_7_MHZ:
+ rc = WR16(s, 0x0c2003f, 0x3b);
+ s->bandwidth_parm = ebx = 0x7a1200; // 8000000
+ edx = 0x4807;
+ break;
+ case BANDWIDTH_6_MHZ:
+ rc = WR16(s, 0x0c2003f, 0x47);
+ s->bandwidth_parm = ebx = 0x68a1b6; // 6857142
+ edx = 0x0f07;
+ break;
+ };
+
+ if (rc < 0)
+ goto exit_rc;
+
+ rc = WR16(s, 0x08200ec, edx);
+ if (rc < 0)
+ goto exit_rc;
+
+ rc = RD16(s, 0x0820050);
+ if (rc < 0)
+ goto exit_rc;
+ rc = WR16(s, 0x0820050, rc);
+
+ {
+ /* Configure bandwidth specific factor */
+ ebx = div64_u64(((u64) (s->f_osc) << 21) + (ebx >> 1),
+ (u64)ebx) - 0x800000;
+ EXIT_RC(WR16(s, 0x0c50010, ebx & 0xffff));
+ EXIT_RC(WR16(s, 0x0c50011, ebx >> 16));
+
+ /* drx397xD oscillator calibration */
+ ebx = div64_u64(((u64) (s->config.f_if + df_tuner) << 28) +
+ (s->f_osc >> 1), (u64)s->f_osc);
+ }
+ ebx &= 0xfffffff;
+ if (fep->inversion == INVERSION_ON)
+ ebx = 0x10000000 - ebx;
+
+ EXIT_RC(WR16(s, 0x0c30010, ebx & 0xffff));
+ EXIT_RC(WR16(s, 0x0c30011, ebx >> 16));
+
+ EXIT_RC(WR16(s, 0x0800000, 1));
+ EXIT_RC(RD16(s, 0x0800000));
+
+
+ EXIT_RC(SC_WaitForReady(s));
+ EXIT_RC(WR16(s, 0x0820042, 0));
+ EXIT_RC(WR16(s, 0x0820041, v22));
+ EXIT_RC(WR16(s, 0x0820040, edi));
+ EXIT_RC(SC_SendCommand(s, 3));
+
+ rc = RD16(s, 0x0800000);
+
+ SC_WaitForReady(s);
+ WR16(s, 0x0820042, 0);
+ WR16(s, 0x0820041, 1);
+ WR16(s, 0x0820040, 1);
+ SC_SendCommand(s, 1);
+
+// rc = WR16(s, 0x2150000, 1);
+// if (rc < 0) goto exit_rc;
+
+ rc = WR16(s, 0x2150000, 2);
+ rc = WR16(s, 0x2150016, a);
+ rc = WR16(s, 0x2150010, 4);
+ rc = WR16(s, 0x2150036, 0);
+ rc = WR16(s, 0x2150000, 1);
+ s->config.d60 = 2;
+ exit_rc:
+ return rc;
+}
+
+/*******************************************************************************
+ * DVB interface
+ ******************************************************************************/
+
+static int drx397x_init(struct dvb_frontend *fe)
+{
+ struct drx397xD_state *s = fe->demodulator_priv;
+ int rc;
+
+ pr_debug("%s\n", __FUNCTION__);
+
+ s->config.rfagc.d00 = 2; /* 0x7c */
+ s->config.rfagc.w04 = 0;
+ s->config.rfagc.w06 = 0x3ff;
+
+ s->config.ifagc.d00 = 0; /* 0x68 */
+ s->config.ifagc.w04 = 0;
+ s->config.ifagc.w06 = 140;
+ s->config.ifagc.w08 = 0;
+ s->config.ifagc.w0A = 0x3ff;
+ s->config.ifagc.w0C = 0x388;
+
+ /* for signal strenght calculations */
+ s->config.ss76 = 820;
+ s->config.ss78 = 2200;
+ s->config.ss7A = 150;
+
+ /* HI_CfgCommand */
+ s->config.w50 = 4;
+ s->config.w52 = 9; // 0xf;
+
+ s->config.f_if = 42800000; /* d14: intermediate frequency [Hz] */
+ s->config.f_osc = 48000; /* s66 : oscillator frequency [kHz] */
+ s->config.w92 = 12000; // 20000;
+
+ s->config.w9C = 0x000e;
+ s->config.w9E = 0x0000;
+
+ /* ConfigureMPEGOutput params */
+ s->config.wA0 = 4;
+ s->config.w98 = 1; // 0;
+ s->config.w9A = 1;
+
+ /* get chip revision */
+ rc = RD16(s, 0x2410019);
+ if (rc < 0)
+ return -ENODEV;
+
+ if (rc == 0) {
+ printk(KERN_INFO "%s: chip revision A2\n", mod_name);
+ rc = drx_load_fw(s, DRXD_FW_A2);
+ } else {
+
+ rc = (rc >> 12) - 3;
+ switch (rc) {
+ case 1:
+ s->flags |= F_SET_0D4h;
+ case 0:
+ case 4:
+ s->flags |= F_SET_0D0h;
+ break;
+ case 2:
+ case 5:
+ break;
+ case 3:
+ s->flags |= F_SET_0D4h;
+ break;
+ default:
+ return -ENODEV;
+ };
+ printk(KERN_INFO "%s: chip revision B1.%d\n", mod_name, rc);
+ rc = drx_load_fw(s, DRXD_FW_B1);
+ }
+ if (rc < 0)
+ goto error;
+
+ rc = WR16(s, 0x0420033, 0x3973);
+ if (rc < 0)
+ goto error;
+
+ rc = HI_Command(s, 2);
+
+ msleep(1);
+
+ if (s->chip_rev == DRXD_FW_A2) {
+ rc = WR16(s, 0x043012d, 0x47F);
+ if (rc < 0)
+ goto error;
+ }
+ rc = WR16_E0(s, 0x0400000, 0);
+ if (rc < 0)
+ goto error;
+
+ if (s->config.w92 > 20000 || s->config.w92 % 4000) {
+ printk(KERN_ERR "%s: invalid osc frequency\n", mod_name);
+ rc = -1;
+ goto error;
+ }
+
+ rc = WR16(s, 0x2410010, 1);
+ if (rc < 0)
+ goto error;
+ rc = WR16(s, 0x2410011, 0x15);
+ if (rc < 0)
+ goto error;
+ rc = WR16(s, 0x2410012, s->config.w92 / 4000);
+ if (rc < 0)
+ goto error;
+#ifdef ORIG_FW
+ rc = WR16(s, 0x2410015, 2);
+ if (rc < 0)
+ goto error;
+#endif
+ rc = WR16(s, 0x2410017, 0x3973);
+ if (rc < 0)
+ goto error;
+
+ s->f_osc = s->config.f_osc * 1000; /* initial estimator */
+
+ s->config.w56 = 1;
+
+ rc = HI_CfgCommand(s);
+ if (rc < 0)
+ goto error;
+
+ rc = write_fw(s, DRXD_InitAtomicRead);
+ if (rc < 0)
+ goto error;
+
+ if (s->chip_rev == DRXD_FW_A2) {
+ rc = WR16(s, 0x2150013, 0);
+ if (rc < 0)
+ goto error;
+ }
+
+ rc = WR16_E0(s, 0x0400002, 0);
+ if (rc < 0)
+ goto error;
+ rc = WR16(s, 0x0400002, 0);
+ if (rc < 0)
+ goto error;
+
+ if (s->chip_rev == DRXD_FW_A2) {
+ rc = write_fw(s, DRXD_ResetCEFR);
+ if (rc < 0)
+ goto error;
+ }
+ rc = write_fw(s, DRXD_microcode);
+ if (rc < 0)
+ goto error;
+
+ s->config.w9C = 0x0e;
+ if (s->flags & F_SET_0D0h) {
+ s->config.w9C = 0;
+ rc = RD16(s, 0x0c20010);
+ if (rc < 0)
+ goto write_DRXD_InitFE_1;
+
+ rc &= ~0x1000;
+ rc = WR16(s, 0x0c20010, rc);
+ if (rc < 0)
+ goto write_DRXD_InitFE_1;
+
+ rc = RD16(s, 0x0c20011);
+ if (rc < 0)
+ goto write_DRXD_InitFE_1;
+
+ rc &= ~0x8;
+ rc = WR16(s, 0x0c20011, rc);
+ if (rc < 0)
+ goto write_DRXD_InitFE_1;
+
+ rc = WR16(s, 0x0c20012, 1);
+ }
+
+ write_DRXD_InitFE_1:
+
+ rc = write_fw(s, DRXD_InitFE_1);
+ if (rc < 0)
+ goto error;
+
+ rc = 1;
+ if (s->chip_rev == DRXD_FW_B1) {
+ if (s->flags & F_SET_0D0h)
+ rc = 0;
+ } else {
+ if (s->flags & F_SET_0D0h)
+ rc = 4;
+ }
+
+ rc = WR16(s, 0x0C20012, rc);
+ if (rc < 0)
+ goto error;
+
+ rc = WR16(s, 0x0C20013, s->config.w9E);
+ if (rc < 0)
+ goto error;
+ rc = WR16(s, 0x0C20015, s->config.w9C);
+ if (rc < 0)
+ goto error;
+
+ rc = write_fw(s, DRXD_InitFE_2);
+ if (rc < 0)
+ goto error;
+ rc = write_fw(s, DRXD_InitFT);
+ if (rc < 0)
+ goto error;
+ rc = write_fw(s, DRXD_InitCP);
+ if (rc < 0)
+ goto error;
+ rc = write_fw(s, DRXD_InitCE);
+ if (rc < 0)
+ goto error;
+ rc = write_fw(s, DRXD_InitEQ);
+ if (rc < 0)
+ goto error;
+ rc = write_fw(s, DRXD_InitEC);
+ if (rc < 0)
+ goto error;
+ rc = write_fw(s, DRXD_InitSC);
+ if (rc < 0)
+ goto error;
+
+ rc = SetCfgIfAgc(s, &s->config.ifagc);
+ if (rc < 0)
+ goto error;
+
+ rc = SetCfgRfAgc(s, &s->config.rfagc);
+ if (rc < 0)
+ goto error;
+
+ rc = ConfigureMPEGOutput(s, 1);
+ rc = WR16(s, 0x08201fe, 0x0017);
+ rc = WR16(s, 0x08201ff, 0x0101);
+
+ s->config.d5C = 0;
+ s->config.d60 = 1;
+ s->config.d48 = 1;
+ error:
+ return rc;
+}
+
+static int drx397x_get_frontend(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *params)
+{
+ return 0;
+}
+
+static int drx397x_set_frontend(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *params)
+{
+ struct drx397xD_state *s = fe->demodulator_priv;
+
+ s->config.s20d24 = 1; // 0;
+ return drx_tune(s, params);
+}
+
+static int drx397x_get_tune_settings(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings
+ *fe_tune_settings)
+{
+ fe_tune_settings->min_delay_ms = 10000;
+ fe_tune_settings->step_size = 0;
+ fe_tune_settings->max_drift = 0;
+ return 0;
+}
+
+static int drx397x_read_status(struct dvb_frontend *fe, fe_status_t * status)
+{
+ struct drx397xD_state *s = fe->demodulator_priv;
+ int lockstat;
+
+ GetLockStatus(s, &lockstat);
+ /* TODO */
+// if (lockstat & 1)
+// CorrectSysClockDeviation(s);
+
+ *status = 0;
+ if (lockstat & 2) {
+ CorrectSysClockDeviation(s);
+ ConfigureMPEGOutput(s, 1);
+ *status = FE_HAS_LOCK | FE_HAS_SYNC | FE_HAS_VITERBI;
+ }
+ if (lockstat & 4) {
+ *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
+ }
+
+ return 0;
+}
+
+static int drx397x_read_ber(struct dvb_frontend *fe, unsigned int *ber)
+{
+ *ber = 0;
+ return 0;
+}
+
+static int drx397x_read_snr(struct dvb_frontend *fe, u16 * snr)
+{
+ *snr = 0;
+ return 0;
+}
+
+static int drx397x_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
+{
+ struct drx397xD_state *s = fe->demodulator_priv;
+ int rc;
+
+ if (s->config.ifagc.d00 == 2) {
+ *strength = 0xffff;
+ return 0;
+ }
+ rc = RD16(s, 0x0c20035);
+ if (rc < 0) {
+ *strength = 0;
+ return 0;
+ }
+ rc &= 0x3ff;
+ /* Signal strength is calculated using the following formula:
+ *
+ * a = 2200 * 150 / (2200 + 150);
+ * a = a * 3300 / (a + 820);
+ * b = 2200 * 3300 / (2200 + 820);
+ * c = (((b-a) * rc) >> 10 + a) << 4;
+ * strength = ~c & 0xffff;
+ *
+ * The following does the same but with less rounding errors:
+ */
+ *strength = ~(7720 + (rc * 30744 >> 10));
+ return 0;
+}
+
+static int drx397x_read_ucblocks(struct dvb_frontend *fe,
+ unsigned int *ucblocks)
+{
+ *ucblocks = 0;
+ return 0;
+}
+
+static int drx397x_sleep(struct dvb_frontend *fe)
+{
+ return 0;
+}
+
+static void drx397x_release(struct dvb_frontend *fe)
+{
+ struct drx397xD_state *s = fe->demodulator_priv;
+ printk(KERN_INFO "%s: release demodulator\n", mod_name);
+ if (s) {
+ drx_release_fw(s);
+ kfree(s);
+ }
+
+}
+
+static struct dvb_frontend_ops drx397x_ops = {
+
+ .info = {
+ .name = "Micronas DRX397xD DVB-T Frontend",
+ .type = FE_OFDM,
+ .frequency_min = 47125000,
+ .frequency_max = 855250000,
+ .frequency_stepsize = 166667,
+ .frequency_tolerance = 0,
+ .caps = /* 0x0C01B2EAE */
+ FE_CAN_FEC_1_2 | // = 0x2,
+ FE_CAN_FEC_2_3 | // = 0x4,
+ FE_CAN_FEC_3_4 | // = 0x8,
+ FE_CAN_FEC_5_6 | // = 0x20,
+ FE_CAN_FEC_7_8 | // = 0x80,
+ FE_CAN_FEC_AUTO | // = 0x200,
+ FE_CAN_QPSK | // = 0x400,
+ FE_CAN_QAM_16 | // = 0x800,
+ FE_CAN_QAM_64 | // = 0x2000,
+ FE_CAN_QAM_AUTO | // = 0x10000,
+ FE_CAN_TRANSMISSION_MODE_AUTO | // = 0x20000,
+ FE_CAN_GUARD_INTERVAL_AUTO | // = 0x80000,
+ FE_CAN_HIERARCHY_AUTO | // = 0x100000,
+ FE_CAN_RECOVER | // = 0x40000000,
+ FE_CAN_MUTE_TS // = 0x80000000
+ },
+
+ .release = drx397x_release,
+ .init = drx397x_init,
+ .sleep = drx397x_sleep,
+
+ .set_frontend = drx397x_set_frontend,
+ .get_tune_settings = drx397x_get_tune_settings,
+ .get_frontend = drx397x_get_frontend,
+
+ .read_status = drx397x_read_status,
+ .read_snr = drx397x_read_snr,
+ .read_signal_strength = drx397x_read_signal_strength,
+ .read_ber = drx397x_read_ber,
+ .read_ucblocks = drx397x_read_ucblocks,
+};
+
+struct dvb_frontend *drx397xD_attach(const struct drx397xD_config *config,
+ struct i2c_adapter *i2c)
+{
+ struct drx397xD_state *s = NULL;
+
+ /* allocate memory for the internal state */
+ s = kzalloc(sizeof(struct drx397xD_state), GFP_KERNEL);
+ if (s == NULL)
+ goto error;
+
+ /* setup the state */
+ s->i2c = i2c;
+ memcpy(&s->config, config, sizeof(struct drx397xD_config));
+
+ /* check if the demod is there */
+ if (RD16(s, 0x2410019) < 0)
+ goto error;
+
+ /* create dvb_frontend */
+ memcpy(&s->frontend.ops, &drx397x_ops, sizeof(struct dvb_frontend_ops));
+ s->frontend.demodulator_priv = s;
+
+ return &s->frontend;
+ error:
+ kfree(s);
+ return NULL;
+}
+
+MODULE_DESCRIPTION("Micronas DRX397xD DVB-T Frontend");
+MODULE_AUTHOR("Henk Vergonet");
+MODULE_LICENSE("GPL");
+
+EXPORT_SYMBOL(drx397xD_attach);
--- /dev/null
+/*
+ * Driver for Micronas DVB-T drx397xD demodulator
+ *
+ * Copyright (C) 2007 Henk vergonet <Henk.Vergonet@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
+ */
+
+#ifndef _DRX397XD_H_INCLUDED
+#define _DRX397XD_H_INCLUDED
+
+#include <linux/dvb/frontend.h>
+
+#define DRX_F_STEPSIZE 166667
+#define DRX_F_OFFSET 36000000
+
+#define I2C_ADR_C0(x) \
+( (u32)cpu_to_le32( \
+ (u32)( \
+ (((u32)(x) & (u32)0x000000ffUL) ) | \
+ (((u32)(x) & (u32)0x0000ff00UL) << 16) | \
+ (((u32)(x) & (u32)0x0fff0000UL) >> 8) | \
+ ( (u32)0x00c00000UL) \
+ )) \
+)
+
+#define I2C_ADR_E0(x) \
+( (u32)cpu_to_le32( \
+ (u32)( \
+ (((u32)(x) & (u32)0x000000ffUL) ) | \
+ (((u32)(x) & (u32)0x0000ff00UL) << 16) | \
+ (((u32)(x) & (u32)0x0fff0000UL) >> 8) | \
+ ( (u32)0x00e00000UL) \
+ )) \
+)
+
+struct drx397xD_CfgRfAgc /* 0x7c */
+{
+ int d00; /* 2 */
+ u16 w04;
+ u16 w06;
+};
+
+struct drx397xD_CfgIfAgc /* 0x68 */
+{
+ int d00; /* 0 */
+ u16 w04; /* 0 */
+ u16 w06;
+ u16 w08;
+ u16 w0A;
+ u16 w0C;
+};
+
+struct drx397xD_s20 {
+ int d04;
+ u32 d18;
+ u32 d1C;
+ u32 d20;
+ u32 d14;
+ u32 d24;
+ u32 d0C;
+ u32 d08;
+};
+
+struct drx397xD_config
+{
+ /* demodulator's I2C address */
+ u8 demod_address; /* 0x0f */
+
+ struct drx397xD_CfgIfAgc ifagc; /* 0x68 */
+ struct drx397xD_CfgRfAgc rfagc; /* 0x7c */
+ u32 s20d24;
+
+ /* HI_CfgCommand parameters */
+ u16 w50, w52, /* w54, */ w56;
+
+ int d5C;
+ int d60;
+ int d48;
+ int d28;
+
+ u32 f_if; /* d14: intermediate frequency [Hz] */
+ /* 36000000 on Cinergy 2400i DT */
+ /* 42800000 on Pinnacle Hybrid PRO 330e */
+
+ u16 f_osc; /* s66: 48000 oscillator frequency [kHz] */
+
+ u16 w92; /* 20000 */
+
+ u16 wA0;
+ u16 w98;
+ u16 w9A;
+
+ u16 w9C; /* 0xe0 */
+ u16 w9E; /* 0x00 */
+
+ /* used for signal strength calculations in
+ drx397x_read_signal_strength
+ */
+ u16 ss78; // 2200
+ u16 ss7A; // 150
+ u16 ss76; // 820
+};
+
+#if defined(CONFIG_DVB_DRX397XD) || (defined(CONFIG_DVB_DRX397XD_MODULE) && defined(MODULE))
+extern struct dvb_frontend* drx397xD_attach(const struct drx397xD_config *config,
+ struct i2c_adapter *i2c);
+#else
+static inline struct dvb_frontend* drx397xD_attach(const struct drx397xD_config *config,
+ struct i2c_adapter *i2c)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __FUNCTION__);
+ return NULL;
+}
+#endif /* CONFIG_DVB_DRX397XD */
+
+#endif /* _DRX397XD_H_INCLUDED */
--- /dev/null
+/*
+ * Firmware definitions for Micronas drx397xD
+ *
+ * Copyright (C) 2007 Henk Vergonet <Henk.Vergonet@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef _FW_ENTRY
+ _FW_ENTRY("drx397xD.A2.fw", DRXD_FW_A2 = 0 ),
+ _FW_ENTRY("drx397xD.B1.fw", DRXD_FW_B1 ),
+#undef _FW_ENTRY
+#endif /* _FW_ENTRY */
+
+#ifdef _BLOB_ENTRY
+ _BLOB_ENTRY("InitAtomicRead", DRXD_InitAtomicRead = 0 ),
+ _BLOB_ENTRY("InitCE", DRXD_InitCE ),
+ _BLOB_ENTRY("InitCP", DRXD_InitCP ),
+ _BLOB_ENTRY("InitEC", DRXD_InitEC ),
+ _BLOB_ENTRY("InitEQ", DRXD_InitEQ ),
+ _BLOB_ENTRY("InitFE_1", DRXD_InitFE_1 ),
+ _BLOB_ENTRY("InitFE_2", DRXD_InitFE_2 ),
+ _BLOB_ENTRY("InitFT", DRXD_InitFT ),
+ _BLOB_ENTRY("InitSC", DRXD_InitSC ),
+ _BLOB_ENTRY("ResetCEFR", DRXD_ResetCEFR ),
+ _BLOB_ENTRY("ResetECRAM", DRXD_ResetECRAM ),
+ _BLOB_ENTRY("microcode", DRXD_microcode ),
+#undef _BLOB_ENTRY
+#endif /* _BLOB_ENTRY */
--- /dev/null
+/* z0194a.h Sharp z0194a tuner support
+*
+* Copyright (C) 2008 Igor M. Liplianin (liplianin@me.by)
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation, version 2.
+*
+* see Documentation/dvb/README.dvb-usb for more information
+*/
+
+#ifndef Z0194A
+#define Z0194A
+
+static int sharp_z0194a__set_symbol_rate(struct dvb_frontend *fe,
+ u32 srate, u32 ratio)
+{
+ u8 aclk = 0;
+ u8 bclk = 0;
+
+ if (srate < 1500000) {
+ aclk = 0xb7; bclk = 0x47; }
+ else if (srate < 3000000) {
+ aclk = 0xb7; bclk = 0x4b; }
+ else if (srate < 7000000) {
+ aclk = 0xb7; bclk = 0x4f; }
+ else if (srate < 14000000) {
+ aclk = 0xb7; bclk = 0x53; }
+ else if (srate < 30000000) {
+ aclk = 0xb6; bclk = 0x53; }
+ else if (srate < 45000000) {
+ aclk = 0xb4; bclk = 0x51; }
+
+ stv0299_writereg(fe, 0x13, aclk);
+ stv0299_writereg(fe, 0x14, bclk);
+ stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
+ stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
+ stv0299_writereg(fe, 0x21, (ratio) & 0xf0);
+
+ return 0;
+}
+
+static u8 sharp_z0194a__inittab[] = {
+ 0x01, 0x15,
+ 0x02, 0x00,
+ 0x03, 0x00,
+ 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
+ 0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
+ 0x06, 0x40, /* DAC not used, set to high impendance mode */
+ 0x07, 0x00, /* DAC LSB */
+ 0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
+ 0x09, 0x00, /* FIFO */
+ 0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
+ 0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */
+ 0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */
+ 0x10, 0x3f, /* AGC2 0x3d */
+ 0x11, 0x84,
+ 0x12, 0xb9,
+ 0x15, 0xc9, /* lock detector threshold */
+ 0x16, 0x00,
+ 0x17, 0x00,
+ 0x18, 0x00,
+ 0x19, 0x00,
+ 0x1a, 0x00,
+ 0x1f, 0x50,
+ 0x20, 0x00,
+ 0x21, 0x00,
+ 0x22, 0x00,
+ 0x23, 0x00,
+ 0x28, 0x00, /* out imp: normal out type: parallel FEC mode:0 */
+ 0x29, 0x1e, /* 1/2 threshold */
+ 0x2a, 0x14, /* 2/3 threshold */
+ 0x2b, 0x0f, /* 3/4 threshold */
+ 0x2c, 0x09, /* 5/6 threshold */
+ 0x2d, 0x05, /* 7/8 threshold */
+ 0x2e, 0x01,
+ 0x31, 0x1f, /* test all FECs */
+ 0x32, 0x19, /* viterbi and synchro search */
+ 0x33, 0xfc, /* rs control */
+ 0x34, 0x93, /* error control */
+ 0x0f, 0x52,
+ 0xff, 0xff
+};
+
+static struct stv0299_config sharp_z0194a_config = {
+ .demod_address = 0x68,
+ .inittab = sharp_z0194a__inittab,
+ .mclk = 88000000UL,
+ .invert = 1,
+ .skip_reinit = 0,
+ .lock_output = STV0299_LOCKOUTPUT_1,
+ .volt13_op0_op1 = STV0299_VOLT13_OP1,
+ .min_delay_ms = 100,
+ .set_symbol_rate = sharp_z0194a__set_symbol_rate,
+};
+
+#endif
enum sms_device_type_st type;
};
-struct list_head g_smscore_notifyees;
-struct list_head g_smscore_devices;
-struct mutex g_smscore_deviceslock;
+static struct list_head g_smscore_notifyees;
+static struct list_head g_smscore_devices;
+static struct mutex g_smscore_deviceslock;
-struct list_head g_smscore_registry;
-struct mutex g_smscore_registrylock;
+static struct list_head g_smscore_registry;
+static struct mutex g_smscore_registrylock;
static int default_mode = 4;
}
-int smscore_module_init(void)
+static int __init smscore_module_init(void)
{
int rc = 0;
return rc;
}
-void smscore_module_exit(void)
+static void __exit smscore_module_exit(void)
{
kmutex_lock(&g_smscore_deviceslock);
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
-struct list_head g_smsdvb_clients;
-struct mutex g_smsdvb_clientslock;
+static struct list_head g_smsdvb_clients;
+static struct mutex g_smsdvb_clientslock;
static int smsdvb_onresponse(void *context, struct smscore_buffer_t *cb)
{
config DVB_AV7110
tristate "AV7110 cards"
depends on DVB_CORE && PCI && I2C
- depends on HOTPLUG
- select FW_LOADER if !DVB_AV7110_FIRMWARE
select TTPCI_EEPROM
select VIDEO_SAA7146_VV
depends on VIDEO_DEV # dependencies of VIDEO_SAA7146_VV
depends on DVB_BUDGET_CORE && I2C
select VIDEO_SAA7146_VV
depends on VIDEO_DEV # dependencies of VIDEO_SAA7146_VV
- depends on HOTPLUG # dependency of FW_LOADER
select DVB_PLL if !DVB_FE_CUSTOMISE
select DVB_STV0299 if !DVB_FE_CUSTOMISE
select DVB_TDA1004X if !DVB_FE_CUSTOMISE
select DVB_TDA10021 if !DVB_FE_CUSTOMISE
select DVB_TDA10023 if !DVB_FE_CUSTOMISE
select DVB_TUA6100 if !DVB_FE_CUSTOMISE
- select FW_LOADER
help
Support for simple SAA7146 based DVB cards
(so called Budget- or Nova-PCI cards) without onboard
config DVB_TTUSB_DEC
tristate "Technotrend/Hauppauge USB DEC devices"
depends on DVB_CORE && USB && INPUT
- depends on HOTPLUG # due to FW_LOADER
- select FW_LOADER
select CRC32
help
Support for external USB adapters designed by Technotrend and
#include <linux/input.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/usb.h>
/*
.llseek = no_llseek,
};
-/* V4L2 interface */
-static struct video_device dsbr100_videodev_template =
-{
- .owner = THIS_MODULE,
- .name = "D-Link DSB-R 100",
- .type = VID_TYPE_TUNER,
- .fops = &usb_dsbr100_fops,
- .release = video_device_release,
+static const struct v4l2_ioctl_ops usb_dsbr100_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_input = vidioc_s_input,
};
+/* V4L2 interface */
+static struct video_device dsbr100_videodev_template = {
+ .name = "D-Link DSB-R 100",
+ .fops = &usb_dsbr100_fops,
+ .ioctl_ops = &usb_dsbr100_ioctl_ops,
+ .release = video_device_release,
+};
+
/* check if the device is present and register with v4l and
usb if it is */
static int usb_dsbr100_probe(struct usb_interface *intf,
#include <linux/init.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include "oss/aci.h"
#include "miropcm20-rds-core.h"
};
static struct video_device pcm20_radio = {
- .owner = THIS_MODULE,
.name = "Miro PCM 20 radio",
- .type = VID_TYPE_TUNER,
.fops = &pcm20_fops,
.priv = &pcm20_unit
};
#include <asm/uaccess.h> /* copy to/from user */
#include <linux/videodev2.h> /* kernel radio structs */
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/version.h> /* for KERNEL_VERSION MACRO */
#define RADIO_VERSION KERNEL_VERSION(0,0,2)
.llseek = no_llseek,
};
-static struct video_device rtrack_radio=
-{
- .owner = THIS_MODULE,
- .name = "RadioTrack radio",
- .type = VID_TYPE_TUNER,
- .fops = &rtrack_fops,
+static const struct v4l2_ioctl_ops rtrack_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_ctrl = vidioc_s_ctrl,
};
+static struct video_device rtrack_radio = {
+ .name = "RadioTrack radio",
+ .fops = &rtrack_fops,
+ .ioctl_ops = &rtrack_ioctl_ops,
+};
+
static int __init rtrack_init(void)
{
if(io==-1)
#include <asm/uaccess.h> /* copy to/from user */
#include <linux/videodev2.h> /* kernel radio structs */
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/version.h> /* for KERNEL_VERSION MACRO */
#define RADIO_VERSION KERNEL_VERSION(0,0,2)
.llseek = no_llseek,
};
-static struct video_device aztech_radio=
-{
- .owner = THIS_MODULE,
- .name = "Aztech radio",
- .type = VID_TYPE_TUNER,
- .fops = &aztech_fops,
+static const struct v4l2_ioctl_ops aztech_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_ctrl = vidioc_s_ctrl,
};
+static struct video_device aztech_radio = {
+ .name = "Aztech radio",
+ .fops = &aztech_fops,
+ .ioctl_ops = &aztech_ioctl_ops,
+};
+
module_param_named(debug,aztech_radio.debug, int, 0644);
MODULE_PARM_DESC(debug,"activates debug info");
#include <asm/uaccess.h> /* copy to/from user */
#include <linux/videodev2.h> /* V4L2 API defs */
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/param.h>
#include <linux/pnp.h>
.llseek = no_llseek,
};
-static struct video_device cadet_radio=
-{
- .owner = THIS_MODULE,
- .name = "Cadet radio",
- .type = VID_TYPE_TUNER,
- .fops = &cadet_fops,
+static const struct v4l2_ioctl_ops cadet_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_input = vidioc_s_input,
};
+static struct video_device cadet_radio = {
+ .name = "Cadet radio",
+ .fops = &cadet_fops,
+ .ioctl_ops = &cadet_ioctl_ops,
+};
+
#ifdef CONFIG_PNP
static struct pnp_device_id cadet_pnp_devices[] = {
#include <linux/pci.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/errno.h>
#include <linux/version.h> /* for KERNEL_VERSION MACRO */
.llseek = no_llseek,
};
-static struct video_device vdev_template = {
- .owner = THIS_MODULE,
- .name = "Gemtek PCI Radio",
- .type = VID_TYPE_TUNER,
- .fops = &gemtek_pci_fops,
+static const struct v4l2_ioctl_ops gemtek_pci_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_ctrl = vidioc_s_ctrl,
};
+static struct video_device vdev_template = {
+ .name = "Gemtek PCI Radio",
+ .fops = &gemtek_pci_fops,
+ .ioctl_ops = &gemtek_pci_ioctl_ops,
+};
+
static int __devinit gemtek_pci_probe( struct pci_dev *pci_dev, const struct pci_device_id *pci_id )
{
struct gemtek_pci_card *card;
#include <asm/io.h> /* outb, outb_p */
#include <asm/uaccess.h> /* copy to/from user */
#include <linux/videodev2.h> /* kernel radio structs */
+#include <media/v4l2-ioctl.h>
#include <media/v4l2-common.h>
#include <linux/spinlock.h>
return 0;
}
-static struct video_device gemtek_radio = {
- .owner = THIS_MODULE,
- .name = "GemTek Radio card",
- .type = VID_TYPE_TUNER,
- .fops = &gemtek_fops,
+static const struct v4l2_ioctl_ops gemtek_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_ctrl = vidioc_s_ctrl
};
+static struct video_device gemtek_radio = {
+ .name = "GemTek Radio card",
+ .fops = &gemtek_fops,
+ .ioctl_ops = &gemtek_ioctl_ops,
+};
+
/*
* Initialization / cleanup related stuff.
*/
#include <linux/pci.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/version.h> /* for KERNEL_VERSION MACRO */
#define RADIO_VERSION KERNEL_VERSION(0,0,6)
return (ofreq == radio_bits_get(dev));
}
-static struct video_device maestro_radio = {
- .name = "Maestro radio",
- .type = VID_TYPE_TUNER,
- .fops = &maestro_fops,
+static const struct v4l2_ioctl_ops maestro_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_ctrl = vidioc_s_ctrl,
};
+static struct video_device maestro_radio = {
+ .name = "Maestro radio",
+ .fops = &maestro_fops,
+ .ioctl_ops = &maestro_ioctl_ops,
+};
+
static int __devinit maestro_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
#include <linux/pci.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#define DRIVER_VERSION "0.77"
return -EINVAL;
}
-static struct video_device maxiradio_radio =
-{
- .owner = THIS_MODULE,
- .name = "Maxi Radio FM2000 radio",
- .type = VID_TYPE_TUNER,
- .fops = &maxiradio_fops,
-
+static const struct v4l2_ioctl_ops maxiradio_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_ctrl = vidioc_s_ctrl,
};
+static struct video_device maxiradio_radio = {
+ .name = "Maxi Radio FM2000 radio",
+ .fops = &maxiradio_fops,
+ .ioctl_ops = &maxiradio_ioctl_ops,
+};
+
static int __devinit maxiradio_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
if(!request_region(pci_resource_start(pdev, 0),
#include <asm/uaccess.h> /* copy to/from user */
#include <linux/videodev2.h> /* kernel radio structs */
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/spinlock.h>
#include <linux/version.h> /* for KERNEL_VERSION MACRO */
.llseek = no_llseek,
};
-static struct video_device rtrack2_radio=
-{
- .owner = THIS_MODULE,
- .name = "RadioTrack II radio",
- .type = VID_TYPE_TUNER,
- .fops = &rtrack2_fops,
+static const struct v4l2_ioctl_ops rtrack2_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_input = vidioc_s_input,
};
+static struct video_device rtrack2_radio = {
+ .name = "RadioTrack II radio",
+ .fops = &rtrack2_fops,
+ .ioctl_ops = &rtrack2_ioctl_ops,
+};
+
static int __init rtrack2_init(void)
{
if(io==-1)
#include <linux/delay.h> /* udelay */
#include <linux/videodev2.h> /* kernel radio structs */
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/isapnp.h>
#include <asm/io.h> /* outb, outb_p */
#include <asm/uaccess.h> /* copy to/from user */
.llseek = no_llseek,
};
-static struct video_device fmi_radio=
-{
- .owner = THIS_MODULE,
- .name = "SF16FMx radio",
- .type = VID_TYPE_TUNER,
- .fops = &fmi_fops,
+static const struct v4l2_ioctl_ops fmi_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_ctrl = vidioc_s_ctrl,
};
+static struct video_device fmi_radio = {
+ .name = "SF16FMx radio",
+ .fops = &fmi_fops,
+ .ioctl_ops = &fmi_ioctl_ops,
+};
+
/* ladis: this is my card. does any other types exist? */
static struct isapnp_device_id id_table[] __devinitdata = {
{ ISAPNP_ANY_ID, ISAPNP_ANY_ID,
#include <asm/uaccess.h> /* copy to/from user */
#include <linux/videodev2.h> /* kernel radio structs */
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/mutex.h>
static struct mutex lock;
.llseek = no_llseek,
};
-static struct video_device fmr2_radio=
-{
- .owner = THIS_MODULE,
- .name = "SF16FMR2 radio",
- . type = VID_TYPE_TUNER,
- .fops = &fmr2_fops,
+static const struct v4l2_ioctl_ops fmr2_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_ctrl = vidioc_s_ctrl,
};
+static struct video_device fmr2_radio = {
+ .name = "SF16FMR2 radio",
+ .fops = &fmr2_fops,
+ .ioctl_ops = &fmr2_ioctl_ops,
+};
+
static int __init fmr2_init(void)
{
fmr2_unit.port = io;
#include <linux/videodev2.h>
#include <linux/mutex.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/rds.h>
#include <asm/unaligned.h>
return retval;
}
-
-/*
- * si470x_viddev_tamples - video device interface
- */
-static struct video_device si470x_viddev_template = {
- .fops = &si470x_fops,
- .name = DRIVER_NAME,
- .type = VID_TYPE_TUNER,
- .release = video_device_release,
+static const struct v4l2_ioctl_ops si470x_ioctl_ops = {
.vidioc_querycap = si470x_vidioc_querycap,
.vidioc_g_input = si470x_vidioc_g_input,
.vidioc_s_input = si470x_vidioc_s_input,
.vidioc_g_frequency = si470x_vidioc_g_frequency,
.vidioc_s_frequency = si470x_vidioc_s_frequency,
.vidioc_s_hw_freq_seek = si470x_vidioc_s_hw_freq_seek,
- .owner = THIS_MODULE,
+};
+
+/*
+ * si470x_viddev_tamples - video device interface
+ */
+static struct video_device si470x_viddev_template = {
+ .fops = &si470x_fops,
+ .ioctl_ops = &si470x_ioctl_ops,
+ .name = DRIVER_NAME,
+ .release = video_device_release,
};
#include <asm/uaccess.h> /* copy to/from user */
#include <linux/videodev2.h> /* kernel radio structs */
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/spinlock.h>
#include <linux/version.h> /* for KERNEL_VERSION MACRO */
.llseek = no_llseek,
};
-static struct video_device terratec_radio=
-{
- .owner = THIS_MODULE,
- .name = "TerraTec ActiveRadio",
- .type = VID_TYPE_TUNER,
- .fops = &terratec_fops,
+static const struct v4l2_ioctl_ops terratec_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_input = vidioc_s_input,
};
+static struct video_device terratec_radio = {
+ .name = "TerraTec ActiveRadio",
+ .fops = &terratec_fops,
+ .ioctl_ops = &terratec_ioctl_ops,
+};
+
static int __init terratec_init(void)
{
if(io==-1)
#include <asm/uaccess.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/version.h> /* for KERNEL_VERSION MACRO */
#define RADIO_VERSION KERNEL_VERSION(0,0,2)
.llseek = no_llseek,
};
-static struct video_device trust_radio=
-{
- .owner = THIS_MODULE,
- .name = "Trust FM Radio",
- .type = VID_TYPE_TUNER,
- .fops = &trust_fops,
+static const struct v4l2_ioctl_ops trust_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_input = vidioc_s_input,
};
+static struct video_device trust_radio = {
+ .name = "Trust FM Radio",
+ .fops = &trust_fops,
+ .ioctl_ops = &trust_ioctl_ops,
+};
+
static int __init trust_init(void)
{
if(io == -1) {
#include <asm/uaccess.h> /* copy to/from user */
#include <linux/videodev2.h> /* kernel radio structs */
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/version.h> /* for KERNEL_VERSION MACRO */
#define RADIO_VERSION KERNEL_VERSION(0,1,1)
.llseek = no_llseek,
};
-static struct video_device typhoon_radio =
-{
- .owner = THIS_MODULE,
- .name = "Typhoon Radio",
- .type = VID_TYPE_TUNER,
- .fops = &typhoon_fops,
+static const struct v4l2_ioctl_ops typhoon_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_ctrl = vidioc_s_ctrl,
};
+static struct video_device typhoon_radio = {
+ .name = "Typhoon Radio",
+ .fops = &typhoon_fops,
+ .ioctl_ops = &typhoon_ioctl_ops,
+};
+
#ifdef CONFIG_RADIO_TYPHOON_PROC_FS
static int typhoon_proc_show(struct seq_file *m, void *v)
#include <asm/uaccess.h> /* copy to/from user */
#include <linux/videodev2.h> /* kernel radio structs */
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/version.h> /* for KERNEL_VERSION MACRO */
#define RADIO_VERSION KERNEL_VERSION(0,0,2)
.llseek = no_llseek,
};
-static struct video_device zoltrix_radio =
-{
- .owner = THIS_MODULE,
- .name = "Zoltrix Radio Plus",
- .type = VID_TYPE_TUNER,
- .fops = &zoltrix_fops,
+static const struct v4l2_ioctl_ops zoltrix_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_ctrl = vidioc_s_ctrl,
};
+static struct video_device zoltrix_radio = {
+ .name = "Zoltrix Radio Plus",
+ .fops = &zoltrix_fops,
+ .ioctl_ops = &zoltrix_ioctl_ops,
+};
+
static int __init zoltrix_init(void)
{
if (io == -1) {
To compile this driver as a module, choose M here: the
module will be called pms.
-config VIDEO_PLANB
- tristate "PlanB Video-In on PowerMac"
- depends on PPC_PMAC && VIDEO_V4L1 && BROKEN
- help
- PlanB is the V4L driver for the PowerMac 7x00/8x00 series video
- input hardware. If you want to experiment with this, say Y.
- Otherwise, or if you don't understand a word, say N. See
- <http://www.cpu.lu/~mlan/linux/dev/planb.html> for more info.
-
- Saying M will compile this driver as a module (planb).
-
config VIDEO_BWQCAM
tristate "Quickcam BW Video For Linux"
depends on PARPORT && VIDEO_V4L1
if V4L_USB_DRIVERS && USB
-config USB_VIDEO_CLASS
- tristate "USB Video Class (UVC)"
- ---help---
- Support for the USB Video Class (UVC). Currently only video
- input devices, such as webcams, are supported.
-
- For more information see: <http://linux-uvc.berlios.de/>
+source "drivers/media/video/uvc/Kconfig"
source "drivers/media/video/gspca/Kconfig"
stkwebcam-objs := stk-webcam.o stk-sensor.o
+videodev-objs := v4l2-dev.o v4l2-ioctl.o
+
obj-$(CONFIG_VIDEO_DEV) += videodev.o compat_ioctl32.o v4l2-int-device.o
obj-$(CONFIG_VIDEO_V4L2_COMMON) += v4l2-common.o
obj-$(CONFIG_VIDEO_ZORAN_ZR36060) += zr36060.o
obj-$(CONFIG_VIDEO_PMS) += pms.o
-obj-$(CONFIG_VIDEO_PLANB) += planb.o
obj-$(CONFIG_VIDEO_VINO) += vino.o indycam.o
obj-$(CONFIG_VIDEO_STRADIS) += stradis.o
obj-$(CONFIG_VIDEO_CPIA) += cpia.o
};
static struct video_device ar_template = {
- .owner = THIS_MODULE,
.name = "Colour AR VGA",
.type = VID_TYPE_CAPTURE,
.fops = &ar_fops,
select VIDEO_TVEEPROM
select DVB_AU8522 if !DVB_FE_CUSTOMIZE
select MEDIA_TUNER_XC5000 if !DVB_FE_CUSTOMIZE
+ select MEDIA_TUNER_MXL5007T if !DVB_FE_CUSTOMIZE
---help---
This is a video4linux driver for Auvitek's USB device.
[AU0828_BOARD_HAUPPAUGE_HVR950Q] = {
.name = "Hauppauge HVR950Q",
},
+ [AU0828_BOARD_HAUPPAUGE_HVR950Q_MXL] = {
+ .name = "Hauppauge HVR950Q rev xxF8",
+ },
[AU0828_BOARD_DVICO_FUSIONHDTV7] = {
.name = "DViCO FusionHDTV USB",
},
switch (dev->board) {
case AU0828_BOARD_HAUPPAUGE_HVR850:
case AU0828_BOARD_HAUPPAUGE_HVR950Q:
+ case AU0828_BOARD_HAUPPAUGE_HVR950Q_MXL:
case AU0828_BOARD_DVICO_FUSIONHDTV7:
if (command == 0) {
/* Tuner Reset Command from xc5000 */
switch (dev->board) {
case AU0828_BOARD_HAUPPAUGE_HVR850:
case AU0828_BOARD_HAUPPAUGE_HVR950Q:
+ case AU0828_BOARD_HAUPPAUGE_HVR950Q_MXL:
if (dev->i2c_rc == 0)
hauppauge_eeprom(dev, eeprom+0xa0);
break;
switch (dev->board) {
case AU0828_BOARD_HAUPPAUGE_HVR850:
case AU0828_BOARD_HAUPPAUGE_HVR950Q:
+ case AU0828_BOARD_HAUPPAUGE_HVR950Q_MXL:
/* GPIO's
* 4 - CS5340
* 5 - AU8522 Demodulator
.driver_info = AU0828_BOARD_HAUPPAUGE_HVR950Q },
{ USB_DEVICE(0x0fd9, 0x0008),
.driver_info = AU0828_BOARD_HAUPPAUGE_HVR950Q },
+ { USB_DEVICE(0x2040, 0x7201),
+ .driver_info = AU0828_BOARD_HAUPPAUGE_HVR950Q_MXL },
+ { USB_DEVICE(0x2040, 0x7211),
+ .driver_info = AU0828_BOARD_HAUPPAUGE_HVR950Q_MXL },
+ { USB_DEVICE(0x2040, 0x7281),
+ .driver_info = AU0828_BOARD_HAUPPAUGE_HVR950Q_MXL },
{ },
};
#define AU0828_BOARD_HAUPPAUGE_HVR950Q 1
#define AU0828_BOARD_HAUPPAUGE_HVR850 2
#define AU0828_BOARD_DVICO_FUSIONHDTV7 3
+#define AU0828_BOARD_HAUPPAUGE_HVR950Q_MXL 4
#include "au0828.h"
#include "au8522.h"
#include "xc5000.h"
+#include "mxl5007t.h"
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
.tuner_callback = au0828_tuner_callback
};
+static struct mxl5007t_config mxl5007t_hvr950q_config = {
+ .xtal_freq_hz = MxL_XTAL_24_MHZ,
+ .if_freq_hz = MxL_IF_6_MHZ,
+};
+
/*-------------------------------------------------------------------*/
static void urb_completion(struct urb *purb)
{
&dev->i2c_adap,
&hauppauge_hvr950q_tunerconfig, dev);
break;
+ case AU0828_BOARD_HAUPPAUGE_HVR950Q_MXL:
+ dvb->frontend = dvb_attach(au8522_attach,
+ &hauppauge_hvr950q_config,
+ &dev->i2c_adap);
+ if (dvb->frontend != NULL)
+ dvb_attach(mxl5007t_attach, dvb->frontend,
+ &dev->i2c_adap, 0x60,
+ &mxl5007t_hvr950q_config);
+ break;
default:
printk(KERN_WARNING "The frontend of your DVB/ATSC card "
"isn't supported yet\n");
config VIDEO_BT848
tristate "BT848 Video For Linux"
depends on VIDEO_DEV && PCI && I2C && VIDEO_V4L2 && INPUT
- depends on HOTPLUG # due to FW_LOADER
select I2C_ALGOBIT
- select FW_LOADER
select VIDEO_BTCX
select VIDEOBUF_DMA_SG
select VIDEO_IR
#include <linux/kdev_t.h>
#include "bttvp.h"
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/tvaudio.h>
#include <media/msp3400.h>
static ssize_t show_card(struct device *cd,
struct device_attribute *attr, char *buf)
{
- struct video_device *vfd = container_of(cd, struct video_device, class_dev);
- struct bttv *btv = dev_get_drvdata(vfd->dev);
+ struct video_device *vfd = container_of(cd, struct video_device, dev);
+ struct bttv *btv = dev_get_drvdata(vfd->parent);
return sprintf(buf, "%d\n", btv ? btv->c.type : UNSET);
}
static DEVICE_ATTR(card, S_IRUGO, show_card, NULL);
.poll = bttv_poll,
};
-static struct video_device bttv_video_template =
-{
- .fops = &bttv_fops,
- .minor = -1,
+static const struct v4l2_ioctl_ops bttv_ioctl_ops = {
.vidioc_querycap = bttv_querycap,
.vidioc_enum_fmt_vid_cap = bttv_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = bttv_g_fmt_vid_cap,
.vidioc_g_register = bttv_g_register,
.vidioc_s_register = bttv_s_register,
#endif
- .tvnorms = BTTV_NORMS,
- .current_norm = V4L2_STD_PAL,
+};
+
+static struct video_device bttv_video_template = {
+ .fops = &bttv_fops,
+ .minor = -1,
+ .ioctl_ops = &bttv_ioctl_ops,
+ .tvnorms = BTTV_NORMS,
+ .current_norm = V4L2_STD_PAL,
};
/* ----------------------------------------------------------------------- */
.poll = radio_poll,
};
-static struct video_device radio_template =
-{
- .fops = &radio_fops,
- .minor = -1,
+static const struct v4l2_ioctl_ops radio_ioctl_ops = {
.vidioc_querycap = radio_querycap,
.vidioc_g_tuner = radio_g_tuner,
.vidioc_enum_input = radio_enum_input,
.vidioc_s_frequency = bttv_s_frequency,
};
+static struct video_device radio_template = {
+ .fops = &radio_fops,
+ .minor = -1,
+ .ioctl_ops = &radio_ioctl_ops,
+};
+
/* ----------------------------------------------------------------------- */
/* some debug code */
static struct video_device *vdev_init(struct bttv *btv,
const struct video_device *template,
- const char *type_name,
- const int type)
+ const char *type_name)
{
struct video_device *vfd;
return NULL;
*vfd = *template;
vfd->minor = -1;
- vfd->dev = &btv->c.pci->dev;
+ vfd->parent = &btv->c.pci->dev;
vfd->release = video_device_release;
- vfd->type = type;
vfd->debug = bttv_debug;
snprintf(vfd->name, sizeof(vfd->name), "BT%d%s %s (%s)",
btv->id, (btv->id==848 && btv->revision==0x12) ? "A" : "",
/* register video4linux devices */
static int __devinit bttv_register_video(struct bttv *btv)
{
- int video_type = VID_TYPE_CAPTURE |
- VID_TYPE_TUNER |
- VID_TYPE_CLIPPING|
- VID_TYPE_SCALES;
-
- if (no_overlay <= 0) {
- bttv_video_template.type |= VID_TYPE_OVERLAY;
- } else {
+ if (no_overlay > 0)
printk("bttv: Overlay support disabled.\n");
- }
/* video */
- btv->video_dev = vdev_init(btv, &bttv_video_template,
- "video", video_type);
+ btv->video_dev = vdev_init(btv, &bttv_video_template, "video");
if (NULL == btv->video_dev)
goto err;
goto err;
printk(KERN_INFO "bttv%d: registered device video%d\n",
btv->c.nr,btv->video_dev->minor & 0x1f);
- if (device_create_file(&btv->video_dev->class_dev,
+ if (device_create_file(&btv->video_dev->dev,
&dev_attr_card)<0) {
printk(KERN_ERR "bttv%d: device_create_file 'card' "
"failed\n", btv->c.nr);
}
/* vbi */
- btv->vbi_dev = vdev_init(btv, &bttv_video_template,
- "vbi", VID_TYPE_TUNER | VID_TYPE_TELETEXT);
+ btv->vbi_dev = vdev_init(btv, &bttv_video_template, "vbi");
if (NULL == btv->vbi_dev)
goto err;
if (!btv->has_radio)
return 0;
/* radio */
- btv->radio_dev = vdev_init(btv, &radio_template,
- "radio", VID_TYPE_TUNER);
+ btv->radio_dev = vdev_init(btv, &radio_template, "radio");
if (NULL == btv->radio_dev)
goto err;
if (video_register_device(btv->radio_dev, VFL_TYPE_RADIO,radio_nr)<0)
#include <linux/interrupt.h>
#include <asm/page.h>
#include <asm/pgtable.h>
+#include <media/v4l2-ioctl.h>
#include "bttvp.h"
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/kdev_t.h>
+#include <media/v4l2-ioctl.h>
#include <asm/io.h>
#include "bttvp.h"
#include <linux/sched.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/mutex.h>
#include <asm/uaccess.h>
};
static struct video_device qcam_template=
{
- .owner = THIS_MODULE,
.name = "Connectix Quickcam",
- .type = VID_TYPE_CAPTURE,
.fops = &qcam_fops,
};
#include <linux/sched.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/mutex.h>
#include <linux/jiffies.h>
static struct video_device qcam_template=
{
- .owner = THIS_MODULE,
.name = "Colour QuickCam",
- .type = VID_TYPE_CAPTURE,
.fops = &qcam_fops,
};
#include <linux/spinlock.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/v4l2-chip-ident.h>
#include <linux/device.h>
#include <linux/wait.h>
.llseek = no_llseek,
};
-static struct video_device cafe_v4l_template = {
- .name = "cafe",
- .type = VFL_TYPE_GRABBER,
- .type2 = VID_TYPE_CAPTURE,
- .minor = -1, /* Get one dynamically */
- .tvnorms = V4L2_STD_NTSC_M,
- .current_norm = V4L2_STD_NTSC_M, /* make mplayer happy */
-
- .fops = &cafe_v4l_fops,
- .release = cafe_v4l_dev_release,
-
+static const struct v4l2_ioctl_ops cafe_v4l_ioctl_ops = {
.vidioc_querycap = cafe_vidioc_querycap,
.vidioc_enum_fmt_vid_cap = cafe_vidioc_enum_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = cafe_vidioc_try_fmt_vid_cap,
.vidioc_s_parm = cafe_vidioc_s_parm,
};
+static struct video_device cafe_v4l_template = {
+ .name = "cafe",
+ .minor = -1, /* Get one dynamically */
+ .tvnorms = V4L2_STD_NTSC_M,
+ .current_norm = V4L2_STD_NTSC_M, /* make mplayer happy */
+
+ .fops = &cafe_v4l_fops,
+ .ioctl_ops = &cafe_v4l_ioctl_ops,
+ .release = cafe_v4l_dev_release,
+};
+
cam->v4ldev = cafe_v4l_template;
cam->v4ldev.debug = 0;
// cam->v4ldev.debug = V4L2_DEBUG_IOCTL_ARG;
- cam->v4ldev.dev = &pdev->dev;
+ cam->v4ldev.parent = &pdev->dev;
ret = video_register_device(&cam->v4ldev, VFL_TYPE_GRABBER, -1);
if (ret)
goto out_smbus;
#include <linux/videodev2.h>
#include <linux/module.h>
#include <linux/smp_lock.h>
-#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#ifdef CONFIG_COMPAT
};
static struct video_device cpia_template = {
- .owner = THIS_MODULE,
.name = "CPiA Camera",
- .type = VID_TYPE_CAPTURE,
.fops = &cpia_fops,
};
#include <asm/uaccess.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include "cpia2.h"
#include <linux/slab.h>
+#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/firmware.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/init.h>
+#include <media/v4l2-ioctl.h>
#include "cpia2.h"
#include "cpia2dev.h"
static struct video_device cpia2_template = {
/* I could not find any place for the old .initialize initializer?? */
- .owner= THIS_MODULE,
.name= "CPiA2 Camera",
- .type= VID_TYPE_CAPTURE,
- .type2 = V4L2_CAP_VIDEO_CAPTURE |
- V4L2_CAP_STREAMING,
.minor= -1,
.fops= &fops_template,
.release= video_device_release,
if (cmd == VIDIOC_DBG_G_REGISTER)
reg->val = cs5345_read(client, reg->reg & 0x1f);
else
- cs5345_write(client, reg->reg & 0x1f, reg->val & 0x1f);
+ cs5345_write(client, reg->reg & 0x1f, reg->val & 0xff);
break;
}
#endif
#include <asm/uaccess.h>
#include <linux/i2c.h>
#include <linux/i2c-id.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <media/v4l2-chip-ident.h>
#include <media/v4l2-i2c-drv-legacy.h>
tristate "Conexant cx23418 MPEG encoder support"
depends on VIDEO_V4L2 && DVB_CORE && PCI && I2C && EXPERIMENTAL
depends on INPUT # due to VIDEO_IR
- depends on HOTPLUG # due to FW_LOADER
select I2C_ALGOBIT
- select FW_LOADER
select VIDEO_IR
select VIDEO_TUNER
select VIDEO_TVEEPROM
if (freq != 32000 && freq != 44100 && freq != 48000)
return -EINVAL;
- /* common for all inputs and rates */
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x10 */
cx18_av_write(cx, 0x127, 0x50);
switch (freq) {
case 32000:
/* VID_PLL and AUX_PLL */
- cx18_av_write4(cx, 0x108, 0x1006040f);
+ cx18_av_write4(cx, 0x108, 0x1408040f);
/* AUX_PLL_FRAC */
- cx18_av_write4(cx, 0x110, 0x01bb39ee);
+ /* 0x8.9504318a * 28,636,363.636 / 0x14 = 32000 * 384 */
+ cx18_av_write4(cx, 0x110, 0x012a0863);
- /* src3/4/6_ctl = 0x0801f77f */
+ /* src3/4/6_ctl */
+ /* 0x1.f77f = (4 * 15734.26) / 32000 */
cx18_av_write4(cx, 0x900, 0x0801f77f);
cx18_av_write4(cx, 0x904, 0x0801f77f);
cx18_av_write4(cx, 0x90c, 0x0801f77f);
+
+ /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x14 */
+ cx18_av_write(cx, 0x127, 0x54);
+
+ /* AUD_COUNT = 0x2fff = 8 samples * 4 * 384 - 1 */
+ cx18_av_write4(cx, 0x12c, 0x11202fff);
+
+ /*
+ * EN_AV_LOCK = 1
+ * VID_COUNT = 0x0d2ef8 = 107999.000 * 8 =
+ * ((8 samples/32,000) * (13,500,000 * 8) * 4 - 1) * 8
+ */
+ cx18_av_write4(cx, 0x128, 0xa10d2ef8);
break;
case 44100:
cx18_av_write4(cx, 0x108, 0x1009040f);
/* AUX_PLL_FRAC */
- cx18_av_write4(cx, 0x110, 0x00ec6bd6);
+ /* 0x9.7635e7 * 28,636,363.63 / 0x10 = 44100 * 384 */
+ cx18_av_write4(cx, 0x110, 0x00ec6bce);
- /* src3/4/6_ctl = 0x08016d59 */
+ /* src3/4/6_ctl */
+ /* 0x1.6d59 = (4 * 15734.26) / 44100 */
cx18_av_write4(cx, 0x900, 0x08016d59);
cx18_av_write4(cx, 0x904, 0x08016d59);
cx18_av_write4(cx, 0x90c, 0x08016d59);
+
+ /* AUD_COUNT = 0x92ff = 49 samples * 2 * 384 - 1 */
+ cx18_av_write4(cx, 0x12c, 0x112092ff);
+
+ /*
+ * EN_AV_LOCK = 1
+ * VID_COUNT = 0x1d4bf8 = 239999.000 * 8 =
+ * ((49 samples/44,100) * (13,500,000 * 8) * 2 - 1) * 8
+ */
+ cx18_av_write4(cx, 0x128, 0xa11d4bf8);
break;
case 48000:
cx18_av_write4(cx, 0x108, 0x100a040f);
/* AUX_PLL_FRAC */
- cx18_av_write4(cx, 0x110, 0x0098d6e5);
+ /* 0xa.4c6b6ea * 28,636,363.63 / 0x10 = 48000 * 384 */
+ cx18_av_write4(cx, 0x110, 0x0098d6dd);
- /* src3/4/6_ctl = 0x08014faa */
+ /* src3/4/6_ctl */
+ /* 0x1.4faa = (4 * 15734.26) / 48000 */
cx18_av_write4(cx, 0x900, 0x08014faa);
cx18_av_write4(cx, 0x904, 0x08014faa);
cx18_av_write4(cx, 0x90c, 0x08014faa);
+
+ /* AUD_COUNT = 0x5fff = 4 samples * 16 * 384 - 1 */
+ cx18_av_write4(cx, 0x12c, 0x11205fff);
+
+ /*
+ * EN_AV_LOCK = 1
+ * VID_COUNT = 0x1193f8 = 143999.000 * 8 =
+ * ((4 samples/48,000) * (13,500,000 * 8) * 16 - 1) * 8
+ */
+ cx18_av_write4(cx, 0x128, 0xa11193f8);
break;
}
} else {
cx18_av_write4(cx, 0x108, 0x1e08040f);
/* AUX_PLL_FRAC */
- cx18_av_write4(cx, 0x110, 0x012a0869);
+ /* 0x8.9504318 * 28,636,363.63 / 0x1e = 32000 * 256 */
+ cx18_av_write4(cx, 0x110, 0x012a0863);
- /* src1_ctl = 0x08010000 */
+ /* src1_ctl */
+ /* 0x1.0000 = 32000/32000 */
cx18_av_write4(cx, 0x8f8, 0x08010000);
- /* src3/4/6_ctl = 0x08020000 */
+ /* src3/4/6_ctl */
+ /* 0x2.0000 = 2 * (32000/32000) */
cx18_av_write4(cx, 0x900, 0x08020000);
cx18_av_write4(cx, 0x904, 0x08020000);
cx18_av_write4(cx, 0x90c, 0x08020000);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x14 */
cx18_av_write(cx, 0x127, 0x54);
+
+ /* AUD_COUNT = 0x1fff = 8 samples * 4 * 256 - 1 */
+ cx18_av_write4(cx, 0x12c, 0x11201fff);
+
+ /*
+ * EN_AV_LOCK = 1
+ * VID_COUNT = 0x0d2ef8 = 107999.000 * 8 =
+ * ((8 samples/32,000) * (13,500,000 * 8) * 4 - 1) * 8
+ */
+ cx18_av_write4(cx, 0x128, 0xa10d2ef8);
break;
case 44100:
cx18_av_write4(cx, 0x108, 0x1809040f);
/* AUX_PLL_FRAC */
- cx18_av_write4(cx, 0x110, 0x00ec6bd6);
+ /* 0x9.7635e74 * 28,636,363.63 / 0x18 = 44100 * 256 */
+ cx18_av_write4(cx, 0x110, 0x00ec6bce);
- /* src1_ctl = 0x08010000 */
+ /* src1_ctl */
+ /* 0x1.60cd = 44100/32000 */
cx18_av_write4(cx, 0x8f8, 0x080160cd);
- /* src3/4/6_ctl = 0x08020000 */
+ /* src3/4/6_ctl */
+ /* 0x1.7385 = 2 * (32000/44100) */
cx18_av_write4(cx, 0x900, 0x08017385);
cx18_av_write4(cx, 0x904, 0x08017385);
cx18_av_write4(cx, 0x90c, 0x08017385);
+
+ /* AUD_COUNT = 0x61ff = 49 samples * 2 * 256 - 1 */
+ cx18_av_write4(cx, 0x12c, 0x112061ff);
+
+ /*
+ * EN_AV_LOCK = 1
+ * VID_COUNT = 0x1d4bf8 = 239999.000 * 8 =
+ * ((49 samples/44,100) * (13,500,000 * 8) * 2 - 1) * 8
+ */
+ cx18_av_write4(cx, 0x128, 0xa11d4bf8);
break;
case 48000:
cx18_av_write4(cx, 0x108, 0x180a040f);
/* AUX_PLL_FRAC */
- cx18_av_write4(cx, 0x110, 0x0098d6e5);
+ /* 0xa.4c6b6ea * 28,636,363.63 / 0x18 = 48000 * 256 */
+ cx18_av_write4(cx, 0x110, 0x0098d6dd);
- /* src1_ctl = 0x08010000 */
+ /* src1_ctl */
+ /* 0x1.8000 = 48000/32000 */
cx18_av_write4(cx, 0x8f8, 0x08018000);
- /* src3/4/6_ctl = 0x08020000 */
+ /* src3/4/6_ctl */
+ /* 0x1.5555 = 2 * (32000/48000) */
cx18_av_write4(cx, 0x900, 0x08015555);
cx18_av_write4(cx, 0x904, 0x08015555);
cx18_av_write4(cx, 0x90c, 0x08015555);
+
+ /* AUD_COUNT = 0x3fff = 4 samples * 16 * 256 - 1 */
+ cx18_av_write4(cx, 0x12c, 0x11203fff);
+
+ /*
+ * EN_AV_LOCK = 1
+ * VID_COUNT = 0x1193f8 = 143999.000 * 8 =
+ * ((4 samples/48,000) * (13,500,000 * 8) * 16 - 1) * 8
+ */
+ cx18_av_write4(cx, 0x128, 0xa11193f8);
break;
}
}
#include <linux/dvb/video.h>
#include <linux/dvb/audio.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/tuner.h>
#include "cx18-mailbox.h"
#include "cx18-av-core.h"
#define CX18_DSP0_INTERRUPT_MASK 0xd0004C
-/* Encoder/decoder firmware sizes */
-#define CX18_FW_CPU_SIZE (158332)
-#define CX18_FW_APU_SIZE (141200)
-
#define APU_ROM_SYNC1 0x6D676553 /* "mgeS" */
#define APU_ROM_SYNC2 0x72646548 /* "rdeH" */
u32 size;
};
-static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx, long size)
+static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx)
{
const struct firmware *fw = NULL;
- int retries = 3;
int i, j;
+ unsigned size;
u32 __iomem *dst = (u32 __iomem *)mem;
const u32 *src;
-retry:
- if (!retries || request_firmware(&fw, fn, &cx->dev->dev)) {
- CX18_ERR("Unable to open firmware %s (must be %ld bytes)\n",
- fn, size);
+ if (request_firmware(&fw, fn, &cx->dev->dev)) {
+ CX18_ERR("Unable to open firmware %s\n", fn);
CX18_ERR("Did you put the firmware in the hotplug firmware directory?\n");
return -ENOMEM;
}
src = (const u32 *)fw->data;
- if (fw->size != size) {
- /* Due to race conditions in firmware loading (esp. with
- udev <0.95) the wrong file was sometimes loaded. So we check
- filesizes to see if at least the right-sized file was
- loaded. If not, then we retry. */
- CX18_INFO("retry: file loaded was not %s (expected size %ld, got %zd)\n",
- fn, size, fw->size);
- release_firmware(fw);
- retries--;
- goto retry;
- }
for (i = 0; i < fw->size; i += 4096) {
setup_page(i);
for (j = i; j < fw->size && j < i + 4096; j += 4) {
}
if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
CX18_INFO("loaded %s firmware (%zd bytes)\n", fn, fw->size);
+ size = fw->size;
release_firmware(fw);
return size;
}
-static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx, long size)
+static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx)
{
const struct firmware *fw = NULL;
- int retries = 3;
int i, j;
+ unsigned size;
const u32 *src;
struct cx18_apu_rom_seghdr seghdr;
const u8 *vers;
u32 apu_version = 0;
int sz;
-retry:
- if (!retries || request_firmware(&fw, fn, &cx->dev->dev)) {
- CX18_ERR("unable to open firmware %s (must be %ld bytes)\n",
- fn, size);
+ if (request_firmware(&fw, fn, &cx->dev->dev)) {
+ CX18_ERR("unable to open firmware %s\n", fn);
CX18_ERR("did you put the firmware in the hotplug firmware directory?\n");
return -ENOMEM;
}
vers = fw->data + sizeof(seghdr);
sz = fw->size;
- if (fw->size != size) {
- /* Due to race conditions in firmware loading (esp. with
- udev <0.95) the wrong file was sometimes loaded. So we check
- filesizes to see if at least the right-sized file was
- loaded. If not, then we retry. */
- CX18_INFO("retry: file loaded was not %s (expected size %ld, got %zd)\n",
- fn, size, fw->size);
- release_firmware(fw);
- retries--;
- goto retry;
- }
apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];
- while (offset + sizeof(seghdr) < size) {
+ while (offset + sizeof(seghdr) < fw->size) {
/* TODO: byteswapping */
memcpy(&seghdr, src + offset / 4, sizeof(seghdr));
offset += sizeof(seghdr);
if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
CX18_INFO("loaded %s firmware V%08x (%zd bytes)\n",
fn, apu_version, fw->size);
+ size = fw->size;
release_firmware(fw);
/* Clear bit0 for APU to start from 0 */
write_reg(read_reg(0xc72030) & ~1, 0xc72030);
/* Only if the processor is not running */
if (read_reg(CX18_PROC_SOFT_RESET) & 8) {
int sz = load_apu_fw_direct("v4l-cx23418-apu.fw",
- cx->enc_mem, cx, CX18_FW_APU_SIZE);
+ cx->enc_mem, cx);
write_enc(0xE51FF004, 0);
write_enc(0xa00000, 4); /* todo: not hardcoded */
cx18_msleep_timeout(500, 0);
sz = sz <= 0 ? sz : load_cpu_fw_direct("v4l-cx23418-cpu.fw",
- cx->enc_mem, cx, CX18_FW_CPU_SIZE);
+ cx->enc_mem, cx);
if (sz > 0) {
int retries = 0;
return res;
}
-void cx18_set_funcs(struct video_device *vdev)
-{
- vdev->vidioc_querycap = cx18_querycap;
- vdev->vidioc_g_priority = cx18_g_priority;
- vdev->vidioc_s_priority = cx18_s_priority;
- vdev->vidioc_s_audio = cx18_s_audio;
- vdev->vidioc_g_audio = cx18_g_audio;
- vdev->vidioc_enumaudio = cx18_enumaudio;
- vdev->vidioc_enum_input = cx18_enum_input;
- vdev->vidioc_cropcap = cx18_cropcap;
- vdev->vidioc_s_crop = cx18_s_crop;
- vdev->vidioc_g_crop = cx18_g_crop;
- vdev->vidioc_g_input = cx18_g_input;
- vdev->vidioc_s_input = cx18_s_input;
- vdev->vidioc_g_frequency = cx18_g_frequency;
- vdev->vidioc_s_frequency = cx18_s_frequency;
- vdev->vidioc_s_tuner = cx18_s_tuner;
- vdev->vidioc_g_tuner = cx18_g_tuner;
- vdev->vidioc_g_enc_index = cx18_g_enc_index;
- vdev->vidioc_g_std = cx18_g_std;
- vdev->vidioc_s_std = cx18_s_std;
- vdev->vidioc_log_status = cx18_log_status;
- vdev->vidioc_enum_fmt_vid_cap = cx18_enum_fmt_vid_cap;
- vdev->vidioc_encoder_cmd = cx18_encoder_cmd;
- vdev->vidioc_try_encoder_cmd = cx18_try_encoder_cmd;
- vdev->vidioc_g_fmt_vid_cap = cx18_g_fmt_vid_cap;
- vdev->vidioc_g_fmt_vbi_cap = cx18_g_fmt_vbi_cap;
- vdev->vidioc_g_fmt_sliced_vbi_cap = cx18_g_fmt_sliced_vbi_cap;
- vdev->vidioc_s_fmt_vid_cap = cx18_s_fmt_vid_cap;
- vdev->vidioc_s_fmt_vbi_cap = cx18_s_fmt_vbi_cap;
- vdev->vidioc_s_fmt_sliced_vbi_cap = cx18_s_fmt_sliced_vbi_cap;
- vdev->vidioc_try_fmt_vid_cap = cx18_try_fmt_vid_cap;
- vdev->vidioc_try_fmt_vbi_cap = cx18_try_fmt_vbi_cap;
- vdev->vidioc_try_fmt_sliced_vbi_cap = cx18_try_fmt_sliced_vbi_cap;
- vdev->vidioc_g_sliced_vbi_cap = cx18_g_sliced_vbi_cap;
- vdev->vidioc_g_chip_ident = cx18_g_chip_ident;
+static const struct v4l2_ioctl_ops cx18_ioctl_ops = {
+ .vidioc_querycap = cx18_querycap,
+ .vidioc_g_priority = cx18_g_priority,
+ .vidioc_s_priority = cx18_s_priority,
+ .vidioc_s_audio = cx18_s_audio,
+ .vidioc_g_audio = cx18_g_audio,
+ .vidioc_enumaudio = cx18_enumaudio,
+ .vidioc_enum_input = cx18_enum_input,
+ .vidioc_cropcap = cx18_cropcap,
+ .vidioc_s_crop = cx18_s_crop,
+ .vidioc_g_crop = cx18_g_crop,
+ .vidioc_g_input = cx18_g_input,
+ .vidioc_s_input = cx18_s_input,
+ .vidioc_g_frequency = cx18_g_frequency,
+ .vidioc_s_frequency = cx18_s_frequency,
+ .vidioc_s_tuner = cx18_s_tuner,
+ .vidioc_g_tuner = cx18_g_tuner,
+ .vidioc_g_enc_index = cx18_g_enc_index,
+ .vidioc_g_std = cx18_g_std,
+ .vidioc_s_std = cx18_s_std,
+ .vidioc_log_status = cx18_log_status,
+ .vidioc_enum_fmt_vid_cap = cx18_enum_fmt_vid_cap,
+ .vidioc_encoder_cmd = cx18_encoder_cmd,
+ .vidioc_try_encoder_cmd = cx18_try_encoder_cmd,
+ .vidioc_g_fmt_vid_cap = cx18_g_fmt_vid_cap,
+ .vidioc_g_fmt_vbi_cap = cx18_g_fmt_vbi_cap,
+ .vidioc_g_fmt_sliced_vbi_cap = cx18_g_fmt_sliced_vbi_cap,
+ .vidioc_s_fmt_vid_cap = cx18_s_fmt_vid_cap,
+ .vidioc_s_fmt_vbi_cap = cx18_s_fmt_vbi_cap,
+ .vidioc_s_fmt_sliced_vbi_cap = cx18_s_fmt_sliced_vbi_cap,
+ .vidioc_try_fmt_vid_cap = cx18_try_fmt_vid_cap,
+ .vidioc_try_fmt_vbi_cap = cx18_try_fmt_vbi_cap,
+ .vidioc_try_fmt_sliced_vbi_cap = cx18_try_fmt_sliced_vbi_cap,
+ .vidioc_g_sliced_vbi_cap = cx18_g_sliced_vbi_cap,
+ .vidioc_g_chip_ident = cx18_g_chip_ident,
#ifdef CONFIG_VIDEO_ADV_DEBUG
- vdev->vidioc_g_register = cx18_g_register;
- vdev->vidioc_s_register = cx18_s_register;
+ .vidioc_g_register = cx18_g_register,
+ .vidioc_s_register = cx18_s_register,
#endif
- vdev->vidioc_default = cx18_default;
- vdev->vidioc_queryctrl = cx18_queryctrl;
- vdev->vidioc_querymenu = cx18_querymenu;
- vdev->vidioc_g_ext_ctrls = cx18_g_ext_ctrls;
- vdev->vidioc_s_ext_ctrls = cx18_s_ext_ctrls;
- vdev->vidioc_try_ext_ctrls = cx18_try_ext_ctrls;
+ .vidioc_default = cx18_default,
+ .vidioc_queryctrl = cx18_queryctrl,
+ .vidioc_querymenu = cx18_querymenu,
+ .vidioc_g_ext_ctrls = cx18_g_ext_ctrls,
+ .vidioc_s_ext_ctrls = cx18_s_ext_ctrls,
+ .vidioc_try_ext_ctrls = cx18_try_ext_ctrls,
+};
+
+void cx18_set_funcs(struct video_device *vdev)
+{
+ vdev->ioctl_ops = &cx18_ioctl_ops;
}
return -ENOMEM;
}
- s->v4l2dev->type =
- VID_TYPE_CAPTURE | VID_TYPE_TUNER | VID_TYPE_TELETEXT |
- VID_TYPE_CLIPPING | VID_TYPE_SCALES | VID_TYPE_MPEG_ENCODER;
snprintf(s->v4l2dev->name, sizeof(s->v4l2dev->name), "cx18-%d",
cx->num);
s->v4l2dev->minor = minor;
- s->v4l2dev->dev = &cx->dev->dev;
+ s->v4l2dev->parent = &cx->dev->dev;
s->v4l2dev->fops = cx18_stream_info[type].fops;
s->v4l2dev->release = video_device_release;
s->v4l2dev->tvnorms = V4L2_STD_ALL;
config VIDEO_CX23885
tristate "Conexant cx23885 (2388x successor) support"
depends on DVB_CORE && VIDEO_DEV && PCI && I2C && INPUT
- depends on HOTPLUG # due to FW_LOADER
select I2C_ALGOBIT
- select FW_LOADER
select VIDEO_BTCX
select VIDEO_TUNER
select VIDEO_TVEEPROM
#include <linux/device.h>
#include <linux/firmware.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/cx2341x.h>
#include "cx23885.h"
.llseek = no_llseek,
};
-static struct video_device cx23885_mpeg_template = {
- .name = "cx23885",
- .type = VID_TYPE_CAPTURE |
- VID_TYPE_TUNER |
- VID_TYPE_SCALES |
- VID_TYPE_MPEG_ENCODER,
- .fops = &mpeg_fops,
- .minor = -1,
+static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
.vidioc_s_std = vidioc_s_std,
.vidioc_enum_input = vidioc_enum_input,
.vidioc_g_input = vidioc_g_input,
.vidioc_queryctrl = vidioc_queryctrl,
};
+static struct video_device cx23885_mpeg_template = {
+ .name = "cx23885",
+ .fops = &mpeg_fops,
+ .ioctl_ops = &mpeg_ioctl_ops,
+ .minor = -1,
+};
+
void cx23885_417_unregister(struct cx23885_dev *dev)
{
dprintk(1, "%s()\n", __func__);
vfd->minor = -1;
snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
type, cx23885_boards[tsport->dev->board].name);
- vfd->dev = &pci->dev;
+ vfd->parent = &pci->dev;
vfd->release = video_device_release;
return vfd;
}
},
[CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
.name = "DViCO FusionHDTV7 Dual Express",
+ .portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
},
};
{
struct cx23885_i2c *bus = priv;
struct cx23885_dev *dev = bus->dev;
+ u32 bitmask = 0;
+
+ if (command != 0) {
+ printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
+ __func__, command);
+ return -EINVAL;
+ }
switch(dev->board) {
case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
- if(command == 0) { /* Tuner Reset Command from xc5000 */
- /* Drive the tuner into reset and out */
- cx_clear(GP0_IO, 0x00000004);
- mdelay(200);
- cx_set(GP0_IO, 0x00000004);
- return 0;
- }
- else {
- printk(KERN_ERR
- "%s(): Unknow command.\n", __func__);
- return -EINVAL;
+ /* Tuner Reset Command from xc5000 */
+ if (command == 0)
+ bitmask = 0x04;
+ break;
+ case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
+ if (command == 0) {
+
+ /* Two identical tuners on two different i2c buses,
+ * we need to reset the correct gpio. */
+ if (bus->nr == 0)
+ bitmask = 0x01;
+ else if (bus->nr == 1)
+ bitmask = 0x04;
}
break;
}
- return 0; /* Should never be here */
+ if (bitmask) {
+ /* Drive the tuner into reset and back out */
+ cx_clear(GP0_IO, bitmask);
+ mdelay(200);
+ cx_set(GP0_IO, bitmask);
+ }
+
+ return 0;
}
void cx23885_gpio_setup(struct cx23885_dev *dev)
mdelay(20);
cx_set(GP0_IO, 0x00050005);
break;
+ case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
+ /* GPIO-0 xc5000 tuner reset i2c bus 0 */
+ /* GPIO-1 s5h1409 demod reset i2c bus 0 */
+ /* GPIO-2 xc5000 tuner reset i2c bus 1 */
+ /* GPIO-3 s5h1409 demod reset i2c bus 0 */
+
+ /* Put the parts into reset and back */
+ cx_set(GP0_IO, 0x000f0000);
+ mdelay(20);
+ cx_clear(GP0_IO, 0x0000000f);
+ mdelay(20);
+ cx_set(GP0_IO, 0x000f000f);
+ break;
}
}
* 0x00010ea0 0x00010xxx Free
*/
+static struct sram_channel cx23885_sram_channels[] = {
+ [SRAM_CH01] = {
+ .name = "VID A",
+ .cmds_start = 0x10000,
+ .ctrl_start = 0x10380,
+ .cdt = 0x104c0,
+ .fifo_start = 0x40,
+ .fifo_size = 0x2800,
+ .ptr1_reg = DMA1_PTR1,
+ .ptr2_reg = DMA1_PTR2,
+ .cnt1_reg = DMA1_CNT1,
+ .cnt2_reg = DMA1_CNT2,
+ },
+ [SRAM_CH02] = {
+ .name = "ch2",
+ .cmds_start = 0x0,
+ .ctrl_start = 0x0,
+ .cdt = 0x0,
+ .fifo_start = 0x0,
+ .fifo_size = 0x0,
+ .ptr1_reg = DMA2_PTR1,
+ .ptr2_reg = DMA2_PTR2,
+ .cnt1_reg = DMA2_CNT1,
+ .cnt2_reg = DMA2_CNT2,
+ },
+ [SRAM_CH03] = {
+ .name = "TS1 B",
+ .cmds_start = 0x100A0,
+ .ctrl_start = 0x10400,
+ .cdt = 0x10580,
+ .fifo_start = 0x5000,
+ .fifo_size = 0x1000,
+ .ptr1_reg = DMA3_PTR1,
+ .ptr2_reg = DMA3_PTR2,
+ .cnt1_reg = DMA3_CNT1,
+ .cnt2_reg = DMA3_CNT2,
+ },
+ [SRAM_CH04] = {
+ .name = "ch4",
+ .cmds_start = 0x0,
+ .ctrl_start = 0x0,
+ .cdt = 0x0,
+ .fifo_start = 0x0,
+ .fifo_size = 0x0,
+ .ptr1_reg = DMA4_PTR1,
+ .ptr2_reg = DMA4_PTR2,
+ .cnt1_reg = DMA4_CNT1,
+ .cnt2_reg = DMA4_CNT2,
+ },
+ [SRAM_CH05] = {
+ .name = "ch5",
+ .cmds_start = 0x0,
+ .ctrl_start = 0x0,
+ .cdt = 0x0,
+ .fifo_start = 0x0,
+ .fifo_size = 0x0,
+ .ptr1_reg = DMA5_PTR1,
+ .ptr2_reg = DMA5_PTR2,
+ .cnt1_reg = DMA5_CNT1,
+ .cnt2_reg = DMA5_CNT2,
+ },
+ [SRAM_CH06] = {
+ .name = "TS2 C",
+ .cmds_start = 0x10140,
+ .ctrl_start = 0x10440,
+ .cdt = 0x105e0,
+ .fifo_start = 0x6000,
+ .fifo_size = 0x1000,
+ .ptr1_reg = DMA5_PTR1,
+ .ptr2_reg = DMA5_PTR2,
+ .cnt1_reg = DMA5_CNT1,
+ .cnt2_reg = DMA5_CNT2,
+ },
+ [SRAM_CH07] = {
+ .name = "ch7",
+ .cmds_start = 0x0,
+ .ctrl_start = 0x0,
+ .cdt = 0x0,
+ .fifo_start = 0x0,
+ .fifo_size = 0x0,
+ .ptr1_reg = DMA6_PTR1,
+ .ptr2_reg = DMA6_PTR2,
+ .cnt1_reg = DMA6_CNT1,
+ .cnt2_reg = DMA6_CNT2,
+ },
+ [SRAM_CH08] = {
+ .name = "ch8",
+ .cmds_start = 0x0,
+ .ctrl_start = 0x0,
+ .cdt = 0x0,
+ .fifo_start = 0x0,
+ .fifo_size = 0x0,
+ .ptr1_reg = DMA7_PTR1,
+ .ptr2_reg = DMA7_PTR2,
+ .cnt1_reg = DMA7_CNT1,
+ .cnt2_reg = DMA7_CNT2,
+ },
+ [SRAM_CH09] = {
+ .name = "ch9",
+ .cmds_start = 0x0,
+ .ctrl_start = 0x0,
+ .cdt = 0x0,
+ .fifo_start = 0x0,
+ .fifo_size = 0x0,
+ .ptr1_reg = DMA8_PTR1,
+ .ptr2_reg = DMA8_PTR2,
+ .cnt1_reg = DMA8_CNT1,
+ .cnt2_reg = DMA8_CNT2,
+ },
+};
+
static struct sram_channel cx23887_sram_channels[] = {
[SRAM_CH01] = {
.name = "VID A",
[SRAM_CH03] = {
.name = "TS1 B",
.cmds_start = 0x100A0,
- .ctrl_start = 0x10780,
- .cdt = 0x10400,
+ .ctrl_start = 0x10630,
+ .cdt = 0x10870,
.fifo_start = 0x5000,
.fifo_size = 0x1000,
.ptr1_reg = DMA3_PTR1,
[SRAM_CH06] = {
.name = "TS2 C",
.cmds_start = 0x10140,
- .ctrl_start = 0x10680,
+ .ctrl_start = 0x10670,
.cdt = 0x108d0,
.fifo_start = 0x6000,
.fifo_size = 0x1000,
cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
+ cx_write(PAD_CTRL, 0x00500300);
mdelay(100);
atomic_inc(&dev->refcount);
dev->nr = cx23885_devcount++;
- dev->sram_channels = cx23887_sram_channels;
sprintf(dev->name, "cx23885[%d]", dev->nr);
mutex_lock(&devlist);
dev->bridge = CX23885_BRIDGE_887;
/* Apply a sensible clock frequency for the PCIe bridge */
dev->clk_freq = 25000000;
+ dev->sram_channels = cx23887_sram_channels;
} else
if(dev->pci->device == 0x8852) {
dev->bridge = CX23885_BRIDGE_885;
/* Apply a sensible clock frequency for the PCIe bridge */
dev->clk_freq = 28000000;
+ dev->sram_channels = cx23885_sram_channels;
} else
BUG();
port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__,
port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
- dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
- port->reg_src_sel, cx_read(port->reg_src_sel));
+ if (port->reg_src_sel)
+ dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
+ port->reg_src_sel, cx_read(port->reg_src_sel));
dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__,
port->reg_lngth, cx_read(port->reg_lngth));
dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__,
dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
buf->vb.width, buf->vb.height, buf->vb.field);
+ /* Stop the fifo and risc engine for this port */
+ cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
+
/* setup fifo + format */
cx23885_sram_channel_setup(dev,
&dev->sram_channels[ port->sram_chno ],
cx_write(port->reg_gpcnt_ctl, 3);
q->count = 1;
- if (cx23885_boards[dev->board].portb & CX23885_MPEG_ENCODER) {
+ /* Set VIDB pins to input */
+ if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
+ reg = cx_read(PAD_CTRL);
+ reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
+ cx_write(PAD_CTRL, reg);
+ }
+
+ /* Set VIDC pins to input */
+ if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
+ reg = cx_read(PAD_CTRL);
+ reg &= ~0x4; /* Clear TS2_SOP_OE */
+ cx_write(PAD_CTRL, reg);
+ }
+
+ if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
reg = cx_read(PAD_CTRL);
reg = reg & ~0x1; /* Clear TS1_OE */
cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
- if (cx23885_boards[dev->board].portb & CX23885_MPEG_ENCODER) {
+ if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
reg = cx_read(PAD_CTRL);
#include "cx23885.h"
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#ifdef CONFIG_VIDEO_V4L1_COMPAT
/* Include V4L1 specific functions. Should be removed soon */
return NULL;
*vfd = *template;
vfd->minor = -1;
- vfd->dev = &pci->dev;
+ vfd->parent = &pci->dev;
vfd->release = video_device_release;
snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)",
dev->name, type, cx23885_boards[dev->board].name);
.llseek = no_llseek,
};
-static struct video_device cx23885_vbi_template;
-static struct video_device cx23885_video_template = {
- .name = "cx23885-video",
- .type = VID_TYPE_CAPTURE|VID_TYPE_TUNER|VID_TYPE_SCALES,
- .fops = &video_fops,
- .minor = -1,
+static const struct v4l2_ioctl_ops video_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
.vidioc_g_register = vidioc_g_register,
.vidioc_s_register = vidioc_s_register,
#endif
+};
+
+static struct video_device cx23885_vbi_template;
+static struct video_device cx23885_video_template = {
+ .name = "cx23885-video",
+ .fops = &video_fops,
+ .minor = -1,
+ .ioctl_ops = &video_ioctl_ops,
.tvnorms = CX23885_NORMS,
.current_norm = V4L2_STD_NTSC_M,
};
memcpy(&cx23885_vbi_template, &cx23885_video_template,
sizeof(cx23885_vbi_template));
strcpy(cx23885_vbi_template.name, "cx23885-vbi");
- cx23885_vbi_template.type = VID_TYPE_TELETEXT|VID_TYPE_TUNER;
dev->tvnorm = cx23885_video_template.current_norm;
config VIDEO_CX25840
tristate "Conexant CX2584x audio/video decoders"
depends on VIDEO_V4L2 && I2C && EXPERIMENTAL
- depends on HOTPLUG # due to FW_LOADER
- select FW_LOADER
---help---
Support for the Conexant CX2584x audio/video decoders.
static unsigned short normal_i2c[] = { 0x88 >> 1, I2C_CLIENT_END };
-int cx25840_debug;
+static int cx25840_debug;
module_param_named(debug,cx25840_debug, int, 0644);
#include <linux/videodev2.h>
#include <linux/i2c.h>
-extern int cx25840_debug;
-
/* ENABLE_PVR150_WORKAROUND activates a workaround for a hardware bug that is
present in Hauppauge PVR-150 (and possibly PVR-500) cards that have
certain NTSC tuners (tveeprom tuner model numbers 85, 99 and 112). The
config VIDEO_CX88_BLACKBIRD
tristate "Blackbird MPEG encoder support (cx2388x + cx23416)"
- depends on VIDEO_CX88 && HOTPLUG
+ depends on VIDEO_CX88
select VIDEO_CX2341X
- select FW_LOADER
---help---
This adds support for MPEG encoder cards based on the
Blackbird reference design, using the Conexant 2388x
#include <linux/device.h>
#include <linux/firmware.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/cx2341x.h>
#include "cx88.h"
.llseek = no_llseek,
};
-static struct video_device cx8802_mpeg_template =
-{
- .name = "cx8802",
- .type = VID_TYPE_CAPTURE|VID_TYPE_TUNER|VID_TYPE_SCALES|VID_TYPE_MPEG_ENCODER,
- .fops = &mpeg_fops,
- .minor = -1,
+static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
.vidioc_querymenu = vidioc_querymenu,
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_s_std = vidioc_s_std,
+};
+
+static struct video_device cx8802_mpeg_template = {
+ .name = "cx8802",
+ .fops = &mpeg_fops,
+ .ioctl_ops = &mpeg_ioctl_ops,
+ .minor = -1,
.tvnorms = CX88_NORMS,
.current_norm = V4L2_STD_NTSC_M,
};
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
- .audio_chip = AUDIO_CHIP_WM8775,
+ .audio_chip = V4L2_IDENT_WM8775,
.input = {{
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
#include "cx88.h"
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards");
MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
return NULL;
*vfd = *template;
vfd->minor = -1;
- vfd->dev = &pci->dev;
+ vfd->parent = &pci->dev;
vfd->release = video_device_release;
snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)",
core->name, type, core->board.name);
#include "cx88.h"
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#ifdef CONFIG_VIDEO_V4L1_COMPAT
/* Include V4L1 specific functions. Should be removed soon */
the initialization. Some boards may use different
routes for different inputs. HVR-1300 surely does */
if (core->board.audio_chip &&
- core->board.audio_chip == AUDIO_CHIP_WM8775) {
+ core->board.audio_chip == V4L2_IDENT_WM8775) {
struct v4l2_routing route;
route.input = INPUT(input).audioroute;
.llseek = no_llseek,
};
-static struct video_device cx8800_vbi_template;
-static struct video_device cx8800_video_template =
-{
- .name = "cx8800-video",
- .type = VID_TYPE_CAPTURE|VID_TYPE_TUNER|VID_TYPE_SCALES,
- .fops = &video_fops,
- .minor = -1,
+static const struct v4l2_ioctl_ops video_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
.vidioc_g_register = vidioc_g_register,
.vidioc_s_register = vidioc_s_register,
#endif
+};
+
+static struct video_device cx8800_vbi_template;
+
+static struct video_device cx8800_video_template = {
+ .name = "cx8800-video",
+ .fops = &video_fops,
+ .minor = -1,
+ .ioctl_ops = &video_ioctl_ops,
.tvnorms = CX88_NORMS,
.current_norm = V4L2_STD_NTSC_M,
};
.llseek = no_llseek,
};
-static struct video_device cx8800_radio_template =
-{
- .name = "cx8800-radio",
- .type = VID_TYPE_TUNER,
- .fops = &radio_fops,
- .minor = -1,
+static const struct v4l2_ioctl_ops radio_ioctl_ops = {
.vidioc_querycap = radio_querycap,
.vidioc_g_tuner = radio_g_tuner,
.vidioc_enum_input = radio_enum_input,
#endif
};
+static struct video_device cx8800_radio_template = {
+ .name = "cx8800-radio",
+ .fops = &radio_fops,
+ .minor = -1,
+ .ioctl_ops = &radio_ioctl_ops,
+};
+
/* ----------------------------------------------------------- */
static void cx8800_unregister_video(struct cx8800_dev *dev)
memcpy( &cx8800_vbi_template, &cx8800_video_template,
sizeof(cx8800_vbi_template) );
strcpy(cx8800_vbi_template.name,"cx8800-vbi");
- cx8800_vbi_template.type = VID_TYPE_TELETEXT|VID_TYPE_TUNER;
/* initialize driver struct */
spin_lock_init(&dev->slock);
/* load and configure helper modules */
- if (core->board.audio_chip == AUDIO_CHIP_WM8775)
+ if (core->board.audio_chip == V4L2_IDENT_WM8775)
request_module("wm8775");
switch (core->boardnr) {
#include <media/tuner.h>
#include <media/tveeprom.h>
#include <media/videobuf-dma-sg.h>
+#include <media/v4l2-chip-ident.h>
#include <media/cx2341x.h>
-#include <media/audiochip.h>
#if defined(CONFIG_VIDEO_CX88_DVB) || defined(CONFIG_VIDEO_CX88_DVB_MODULE)
#include <media/videobuf-dvb.h>
#endif
struct cx88_input input[MAX_CX88_INPUT];
struct cx88_input radio;
enum cx88_board_type mpeg;
- enum audiochip audio_chip;
+ unsigned int audio_chip;
};
struct cx88_subid {
#include <media/saa7115.h>
#include <media/tvp5150.h>
#include <media/tveeprom.h>
-#include <media/audiochip.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-chip-ident.h>
#include "em28xx.h"
};
struct em28xx_board em28xx_boards[] = {
+ [EM2750_BOARD_UNKNOWN] = {
+ .name = "Unknown EM2750/EM2751 webcam grabber",
+ .vchannels = 1,
+ .input = { {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = 0,
+ .amux = 0,
+ } },
+ },
[EM2800_BOARD_UNKNOWN] = {
.name = "Unknown EM2800 video grabber",
.is_em2800 = 1,
.is_em2800 = 0,
.tuner_type = TUNER_ABSENT,
},
+ [EM2750_BOARD_DLCW_130] = {
+ /* Beijing Huaqi Information Digital Technology Co., Ltd */
+ .name = "Huaqi DLCW-130",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 1,
+ .input = { {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = 0,
+ .amux = 0,
+ } },
+ },
+ [EM2800_BOARD_KWORLD_USB2800] = {
+ .name = "Kworld USB2800",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .is_em2800 = 1,
+ .vchannels = 3,
+ .tuner_type = TUNER_PHILIPS_FCV1236D,
+ .tda9887_conf = TDA9887_PRESENT,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE2,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
[EM2820_BOARD_KWORLD_PVRTV2800RF] = {
.name = "Kworld PVR TV 2800 RF",
.is_em2800 = 0,
MSP_DSP_IN_SCART, MSP_DSP_IN_SCART),
} },
},
- [EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900] = {
- .name = "Hauppauge WinTV HVR 900",
+ [EM2820_BOARD_DLINK_USB_TV] = {
+ .name = "D-Link DUB-T210 TV Tuner",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 3,
+ .is_em2800 = 0,
+ .tuner_type = TUNER_LG_PAL_NEW_TAPC,
+ .tda9887_conf = TDA9887_PRESENT,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE2,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2820_BOARD_HERCULES_SMART_TV_USB2] = {
+ .name = "Hercules Smart TV USB 2.0",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 3,
+ .tuner_type = TUNER_LG_PAL_NEW_TAPC,
+ .tda9887_conf = TDA9887_PRESENT,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE2,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2820_BOARD_PINNACLE_USB_2_FM1216ME] = {
+ .name = "Pinnacle PCTV USB 2 (Philips FM1216ME)",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 3,
+ .is_em2800 = 0,
+ .tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
+ .tda9887_conf = TDA9887_PRESENT,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE2,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2820_BOARD_GADMEI_UTV310] = {
+ .name = "Gadmei UTV310",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 3,
+ .tuner_type = TUNER_TNF_5335MF,
+ .tda9887_conf = TDA9887_PRESENT,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE1,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2820_BOARD_LEADTEK_WINFAST_USBII_DELUXE] = {
+ .name = "Leadtek Winfast USB II Deluxe",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 3,
+ .tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
+ .tda9887_conf = TDA9887_PRESENT,
+ .decoder = EM28XX_SAA7114,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = 2,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = 0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = 9,
+ .amux = 1,
+ } },
+ },
+ [EM2820_BOARD_PINNACLE_DVC_100] = {
+ .name = "Pinnacle Dazzle DVC 100",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 3,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2820_BOARD_VIDEOLOGY_20K14XUSB] = {
+ .name = "Videology 20K14XUSB USB2.0",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 1,
+ .input = { {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = 0,
+ .amux = 0,
+ } },
+ },
+ [EM2821_BOARD_PROLINK_PLAYTV_USB2] = {
+ .name = "SIIG AVTuner-PVR/Prolink PlayTV USB 2.0",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 3,
+ .is_em2800 = 0,
+ .tuner_type = TUNER_LG_PAL_NEW_TAPC, /* unknown? */
+ .tda9887_conf = TDA9887_PRESENT, /* unknown? */
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE2,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2821_BOARD_SUPERCOMP_USB_2] = {
+ .name = "Supercomp USB 2.0 TV",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 3,
+ .is_em2800 = 0,
+ .tuner_type = TUNER_PHILIPS_FM1236_MK3,
+ .tda9887_conf = TDA9887_PRESENT |
+ TDA9887_PORT1_ACTIVE |
+ TDA9887_PORT2_ACTIVE,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE2,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2821_BOARD_USBGEAR_VD204] = {
+ .name = "Usbgear VD204v9",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 2,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2860_BOARD_NETGMBH_CAM] = {
+ /* Beijing Huaqi Information Digital Technology Co., Ltd */
+ .name = "NetGMBH Cam",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 1,
+ .input = { {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = 0,
+ .amux = 0,
+ } },
+ },
+ [EM2860_BOARD_TYPHOON_DVD_MAKER] = {
+ .name = "Typhoon DVD Maker",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 2,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2860_BOARD_GADMEI_UTV330] = {
+ .name = "Gadmei UTV330",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
.vchannels = 3,
+ .tuner_type = TUNER_TNF_5335MF,
.tda9887_conf = TDA9887_PRESENT,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE2,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2860_BOARD_TERRATEC_HYBRID_XS] = {
+ .name = "Terratec Cinergy A Hybrid XS",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 3,
.tuner_type = TUNER_XC2028,
- .mts_firmware = 1,
- .has_dvb = 1,
.decoder = EM28XX_TVP5150,
.input = { {
.type = EM28XX_VMUX_TELEVISION,
.amux = 1,
} },
},
- [EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2] = {
- .name = "Hauppauge WinTV HVR 900 (R2)",
+ [EM2861_BOARD_KWORLD_PVRTV_300U] = {
+ .name = "KWorld PVRTV 300U",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 3,
+ .tuner_type = TUNER_XC2028,
+ .decoder = EM28XX_TVP5150,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = TVP5150_COMPOSITE0,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = TVP5150_COMPOSITE1,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = TVP5150_SVIDEO,
+ .amux = 1,
+ } },
+ },
+ [EM2861_BOARD_YAKUMO_MOVIE_MIXER] = {
+ .name = "Yakumo MovieMixer",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 1,
+ .decoder = EM28XX_TVP5150,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = TVP5150_COMPOSITE0,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = TVP5150_COMPOSITE1,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = TVP5150_SVIDEO,
+ .amux = 1,
+ } },
+ },
+ [EM2861_BOARD_PLEXTOR_PX_TV100U] = {
+ .name = "Plextor ConvertX PX-TV100U",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
.vchannels = 3,
+ .tuner_type = TUNER_TNF_5335MF,
.tda9887_conf = TDA9887_PRESENT,
+ .decoder = EM28XX_TVP5150,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = TVP5150_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = TVP5150_COMPOSITE1,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = TVP5150_SVIDEO,
+ .amux = 1,
+ } },
+ },
+ [EM2870_BOARD_TERRATEC_XS] = {
+ .name = "Terratec Cinergy T XS",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .tuner_type = TUNER_XC2028,
+ },
+ [EM2870_BOARD_TERRATEC_XS_MT2060] = {
+ .name = "Terratec Cinergy T XS (MT2060)",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .tuner_type = TUNER_ABSENT, /* MT2060 */
+ },
+ [EM2870_BOARD_KWORLD_350U] = {
+ .name = "Kworld 350 U DVB-T",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .tuner_type = TUNER_XC2028,
+ },
+ [EM2870_BOARD_KWORLD_355U] = {
+ .name = "Kworld 355 U DVB-T",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ },
+ [EM2870_BOARD_PINNACLE_PCTV_DVB] = {
+ .name = "Pinnacle PCTV DVB-T",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .tuner_type = TUNER_ABSENT, /* MT2060 */
+ },
+ [EM2870_BOARD_COMPRO_VIDEOMATE] = {
+ .name = "Compro, VideoMate U3",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .tuner_type = TUNER_ABSENT, /* MT2060 */
+ },
+ [EM2880_BOARD_TERRATEC_HYBRID_XS_FR] = {
+ .name = "Terratec Hybrid XS Secam",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 3,
+ .has_msp34xx = 1,
.tuner_type = TUNER_XC2028,
- .mts_firmware = 1,
.decoder = EM28XX_TVP5150,
.input = { {
.type = EM28XX_VMUX_TELEVISION,
.amux = 1,
} },
},
- [EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950] = {
- .name = "Hauppauge WinTV HVR 950",
+ [EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900] = {
+ .name = "Hauppauge WinTV HVR 900",
+ .vchannels = 3,
+ .tda9887_conf = TDA9887_PRESENT,
+ .tuner_type = TUNER_XC2028,
+ .mts_firmware = 1,
+ .has_dvb = 1,
+ .decoder = EM28XX_TVP5150,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = TVP5150_COMPOSITE0,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = TVP5150_COMPOSITE1,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = TVP5150_SVIDEO,
+ .amux = 1,
+ } },
+ },
+ [EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2] = {
+ .name = "Hauppauge WinTV HVR 900 (R2)",
+ .vchannels = 3,
+ .tda9887_conf = TDA9887_PRESENT,
+ .tuner_type = TUNER_XC2028,
+ .mts_firmware = 1,
+ .decoder = EM28XX_TVP5150,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = TVP5150_COMPOSITE0,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = TVP5150_COMPOSITE1,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = TVP5150_SVIDEO,
+ .amux = 1,
+ } },
+ },
+ [EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950] = {
+ .name = "Hauppauge WinTV HVR 950",
+ .vchannels = 3,
+ .tda9887_conf = TDA9887_PRESENT,
+ .tuner_type = TUNER_XC2028,
+ .mts_firmware = 1,
+ .has_12mhz_i2s = 1,
+ .has_dvb = 1,
+ .decoder = EM28XX_TVP5150,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = TVP5150_COMPOSITE0,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = TVP5150_COMPOSITE1,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = TVP5150_SVIDEO,
+ .amux = 1,
+ } },
+ },
+ [EM2880_BOARD_PINNACLE_PCTV_HD_PRO] = {
+ .name = "Pinnacle PCTV HD Pro Stick",
+ .vchannels = 3,
+ .tda9887_conf = TDA9887_PRESENT,
+ .tuner_type = TUNER_XC2028,
+ .mts_firmware = 1,
+ .has_12mhz_i2s = 1,
+ .has_dvb = 1,
+ .decoder = EM28XX_TVP5150,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = TVP5150_COMPOSITE0,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = TVP5150_COMPOSITE1,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = TVP5150_SVIDEO,
+ .amux = 1,
+ } },
+ },
+ [EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600] = {
+ .name = "AMD ATI TV Wonder HD 600",
.vchannels = 3,
.tda9887_conf = TDA9887_PRESENT,
.tuner_type = TUNER_XC2028,
.amux = 1,
} },
},
- [EM2880_BOARD_PINNACLE_PCTV_HD_PRO] = {
- .name = "Pinnacle PCTV HD Pro Stick",
- .vchannels = 3,
- .tda9887_conf = TDA9887_PRESENT,
- .tuner_type = TUNER_XC2028,
- .mts_firmware = 1,
- .has_12mhz_i2s = 1,
- .has_dvb = 1,
- .decoder = EM28XX_TVP5150,
+ [EM2880_BOARD_TERRATEC_HYBRID_XS] = {
+ .name = "Terratec Hybrid XS",
+ .vchannels = 3,
+ .tda9887_conf = TDA9887_PRESENT,
+ .tuner_type = TUNER_XC2028,
+ .decoder = EM28XX_TVP5150,
+ .has_dvb = 1,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = TVP5150_COMPOSITE0,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = TVP5150_COMPOSITE1,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = TVP5150_SVIDEO,
+ .amux = 1,
+ } },
+ },
+ /* maybe there's a reason behind it why Terratec sells the Hybrid XS
+ as Prodigy XS with a different PID, let's keep it separated for now
+ maybe we'll need it lateron */
+ [EM2880_BOARD_TERRATEC_PRODIGY_XS] = {
+ .name = "Terratec Prodigy XS",
+ .vchannels = 3,
+ .tda9887_conf = TDA9887_PRESENT,
+ .tuner_type = TUNER_XC2028,
+ .decoder = EM28XX_TVP5150,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = TVP5150_COMPOSITE0,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = TVP5150_COMPOSITE1,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = TVP5150_SVIDEO,
+ .amux = 1,
+ } },
+ },
+ [EM2820_BOARD_MSI_VOX_USB_2] = {
+ .name = "MSI VOX USB 2.0",
+ .vchannels = 3,
+ .tuner_type = TUNER_LG_PAL_NEW_TAPC,
+ .tda9887_conf = TDA9887_PRESENT |
+ TDA9887_PORT1_ACTIVE |
+ TDA9887_PORT2_ACTIVE,
+ .max_range_640_480 = 1,
+
+ .decoder = EM28XX_SAA7114,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE4,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2800_BOARD_TERRATEC_CINERGY_200] = {
+ .name = "Terratec Cinergy 200 USB",
+ .is_em2800 = 1,
+ .vchannels = 3,
+ .tuner_type = TUNER_LG_PAL_NEW_TAPC,
+ .tda9887_conf = TDA9887_PRESENT,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE2,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2800_BOARD_GRABBEEX_USB2800] = {
+ .name = "eMPIA Technology, Inc. GrabBeeX+ Video Encoder",
+ .is_em2800 = 1,
+ .vchannels = 2,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2800_BOARD_LEADTEK_WINFAST_USBII] = {
+ .name = "Leadtek Winfast USB II",
+ .is_em2800 = 1,
+ .vchannels = 3,
+ .tuner_type = TUNER_LG_PAL_NEW_TAPC,
+ .tda9887_conf = TDA9887_PRESENT,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE2,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2800_BOARD_KWORLD_USB2800] = {
+ .name = "Kworld USB2800",
+ .is_em2800 = 1,
+ .vchannels = 3,
+ .tuner_type = TUNER_PHILIPS_FCV1236D,
+ .tda9887_conf = TDA9887_PRESENT,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE2,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2820_BOARD_PINNACLE_DVC_90] = {
+ .name = "Pinnacle Dazzle DVC 90/DVC 100",
+ .vchannels = 3,
+ .tuner_type = TUNER_ABSENT,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2800_BOARD_VGEAR_POCKETTV] = {
+ .name = "V-Gear PocketTV",
+ .is_em2800 = 1,
+ .vchannels = 3,
+ .tuner_type = TUNER_LG_PAL_NEW_TAPC,
+ .tda9887_conf = TDA9887_PRESENT,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE2,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 1,
+ } },
+ },
+ [EM2820_BOARD_PROLINK_PLAYTV_USB2] = {
+ .name = "Pixelview Prolink PlayTV USB 2.0",
+ .vchannels = 3,
+ .tda9887_conf = TDA9887_PRESENT,
+ .tuner_type = TUNER_YMEC_TVF_5533MF,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = SAA7115_COMPOSITE2,
+ .amux = EM28XX_AMUX_LINE_IN,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = SAA7115_COMPOSITE0,
+ .amux = EM28XX_AMUX_LINE_IN,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = EM28XX_AMUX_LINE_IN,
+ } },
+ },
+ [EM2860_BOARD_POINTNIX_INTRAORAL_CAMERA] = {
+ .name = "PointNix Intra-Oral Camera",
+ .has_snapshot_button = 1,
+ .vchannels = 1,
+ .tda9887_conf = TDA9887_PRESENT,
+ .tuner_type = TUNER_ABSENT,
+ .decoder = EM28XX_SAA7113,
+ .input = { {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = SAA7115_SVIDEO3,
+ .amux = 0,
+ } },
+ },
+ [EM2880_BOARD_MSI_DIGIVOX_AD] = {
+ .name = "MSI DigiVox A/D",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 3,
+ .tuner_type = TUNER_XC2028,
+ .decoder = EM28XX_TVP5150,
+ .input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = TVP5150_COMPOSITE0,
+ .amux = 0,
+ }, {
+ .type = EM28XX_VMUX_COMPOSITE1,
+ .vmux = TVP5150_COMPOSITE1,
+ .amux = 1,
+ }, {
+ .type = EM28XX_VMUX_SVIDEO,
+ .vmux = TVP5150_SVIDEO,
+ .amux = 1,
+ } },
+ },
+ [EM2880_BOARD_MSI_DIGIVOX_AD_II] = {
+ .name = "MSI DigiVox A/D II",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
+ .vchannels = 3,
+ .tuner_type = TUNER_XC2028,
+ .decoder = EM28XX_TVP5150,
.input = { {
.type = EM28XX_VMUX_TELEVISION,
.vmux = TVP5150_COMPOSITE0,
.amux = 1,
} },
},
- [EM2880_BOARD_TERRATEC_HYBRID_XS] = {
- .name = "Terratec Hybrid XS",
+ [EM2880_BOARD_KWORLD_DVB_305U] = {
+ .name = "KWorld DVB-T 305U",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
.vchannels = 3,
- .tda9887_conf = TDA9887_PRESENT,
.tuner_type = TUNER_XC2028,
.decoder = EM28XX_TVP5150,
.input = { {
.amux = 1,
} },
},
- /* maybe there's a reason behind it why Terratec sells the Hybrid XS
- as Prodigy XS with a different PID, let's keep it separated for now
- maybe we'll need it lateron */
- [EM2880_BOARD_TERRATEC_PRODIGY_XS] = {
- .name = "Terratec Prodigy XS",
+ [EM2880_BOARD_KWORLD_DVB_310U] = {
+ .name = "KWorld DVB-T 310U",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
.vchannels = 3,
- .tda9887_conf = TDA9887_PRESENT,
.tuner_type = TUNER_XC2028,
.decoder = EM28XX_TVP5150,
.input = { {
.amux = 1,
} },
},
- [EM2820_BOARD_MSI_VOX_USB_2] = {
- .name = "MSI VOX USB 2.0",
- .vchannels = 3,
- .tuner_type = TUNER_LG_PAL_NEW_TAPC,
- .tda9887_conf = TDA9887_PRESENT |
- TDA9887_PORT1_ACTIVE |
- TDA9887_PORT2_ACTIVE,
- .max_range_640_480 = 1,
-
- .decoder = EM28XX_SAA7114,
- .input = { {
- .type = EM28XX_VMUX_TELEVISION,
- .vmux = SAA7115_COMPOSITE4,
- .amux = 0,
- }, {
- .type = EM28XX_VMUX_COMPOSITE1,
- .vmux = SAA7115_COMPOSITE0,
- .amux = 1,
- }, {
- .type = EM28XX_VMUX_SVIDEO,
- .vmux = SAA7115_SVIDEO3,
- .amux = 1,
- } },
- },
- [EM2800_BOARD_TERRATEC_CINERGY_200] = {
- .name = "Terratec Cinergy 200 USB",
- .is_em2800 = 1,
+ [EM2881_BOARD_DNT_DA2_HYBRID] = {
+ .name = "DNT DA2 Hybrid",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
.vchannels = 3,
- .tuner_type = TUNER_LG_PAL_NEW_TAPC,
- .tda9887_conf = TDA9887_PRESENT,
- .decoder = EM28XX_SAA7113,
+ .tuner_type = TUNER_XC2028,
+ .decoder = EM28XX_TVP5150,
.input = { {
.type = EM28XX_VMUX_TELEVISION,
- .vmux = SAA7115_COMPOSITE2,
+ .vmux = TVP5150_COMPOSITE0,
.amux = 0,
}, {
.type = EM28XX_VMUX_COMPOSITE1,
- .vmux = SAA7115_COMPOSITE0,
+ .vmux = TVP5150_COMPOSITE1,
.amux = 1,
}, {
.type = EM28XX_VMUX_SVIDEO,
- .vmux = SAA7115_SVIDEO3,
+ .vmux = TVP5150_SVIDEO,
.amux = 1,
} },
},
- [EM2800_BOARD_LEADTEK_WINFAST_USBII] = {
- .name = "Leadtek Winfast USB II",
- .is_em2800 = 1,
+ [EM2881_BOARD_PINNACLE_HYBRID_PRO] = {
+ .name = "Pinnacle Hybrid Pro",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
.vchannels = 3,
- .tuner_type = TUNER_LG_PAL_NEW_TAPC,
- .tda9887_conf = TDA9887_PRESENT,
- .decoder = EM28XX_SAA7113,
+ .tuner_type = TUNER_XC2028,
+ .decoder = EM28XX_TVP5150,
.input = { {
.type = EM28XX_VMUX_TELEVISION,
- .vmux = SAA7115_COMPOSITE2,
+ .vmux = TVP5150_COMPOSITE0,
.amux = 0,
}, {
.type = EM28XX_VMUX_COMPOSITE1,
- .vmux = SAA7115_COMPOSITE0,
+ .vmux = TVP5150_COMPOSITE1,
.amux = 1,
}, {
.type = EM28XX_VMUX_SVIDEO,
- .vmux = SAA7115_SVIDEO3,
+ .vmux = TVP5150_SVIDEO,
.amux = 1,
} },
},
- [EM2800_BOARD_KWORLD_USB2800] = {
- .name = "Kworld USB2800",
- .is_em2800 = 1,
+ [EM2882_BOARD_PINNACLE_HYBRID_PRO] = {
+ .name = "Pinnacle Hybrid Pro (2)",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
.vchannels = 3,
- .tuner_type = TUNER_PHILIPS_FCV1236D,
- .tda9887_conf = TDA9887_PRESENT,
- .decoder = EM28XX_SAA7113,
+ .tuner_type = TUNER_XC2028,
+ .decoder = EM28XX_TVP5150,
.input = { {
.type = EM28XX_VMUX_TELEVISION,
- .vmux = SAA7115_COMPOSITE2,
+ .vmux = TVP5150_COMPOSITE0,
.amux = 0,
}, {
.type = EM28XX_VMUX_COMPOSITE1,
- .vmux = SAA7115_COMPOSITE0,
+ .vmux = TVP5150_COMPOSITE1,
.amux = 1,
}, {
.type = EM28XX_VMUX_SVIDEO,
- .vmux = SAA7115_SVIDEO3,
+ .vmux = TVP5150_SVIDEO,
.amux = 1,
} },
},
- [EM2820_BOARD_PINNACLE_DVC_90] = {
- .name = "Pinnacle Dazzle DVC 90/DVC 100",
+ [EM2882_BOARD_KWORLD_VS_DVBT] = {
+ .name = "Kworld VS-DVB-T 323UR",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
.vchannels = 3,
- .tuner_type = TUNER_ABSENT,
- .decoder = EM28XX_SAA7113,
+ .tuner_type = TUNER_XC2028,
+ .decoder = EM28XX_TVP5150,
.input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = TVP5150_COMPOSITE0,
+ .amux = 0,
+ }, {
.type = EM28XX_VMUX_COMPOSITE1,
- .vmux = SAA7115_COMPOSITE0,
+ .vmux = TVP5150_COMPOSITE1,
.amux = 1,
}, {
.type = EM28XX_VMUX_SVIDEO,
- .vmux = SAA7115_SVIDEO3,
+ .vmux = TVP5150_SVIDEO,
.amux = 1,
} },
},
- [EM2800_BOARD_VGEAR_POCKETTV] = {
- .name = "V-Gear PocketTV",
- .is_em2800 = 1,
+ [EM2882_BOARD_TERRATEC_HYBRID_XS] = {
+ .name = "Terratec Hybrid XS (em2882)",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
.vchannels = 3,
- .tuner_type = TUNER_LG_PAL_NEW_TAPC,
- .tda9887_conf = TDA9887_PRESENT,
- .decoder = EM28XX_SAA7113,
+ .tuner_type = TUNER_XC2028,
+ .decoder = EM28XX_TVP5150,
.input = { {
.type = EM28XX_VMUX_TELEVISION,
- .vmux = SAA7115_COMPOSITE2,
+ .vmux = TVP5150_COMPOSITE0,
.amux = 0,
}, {
.type = EM28XX_VMUX_COMPOSITE1,
- .vmux = SAA7115_COMPOSITE0,
+ .vmux = TVP5150_COMPOSITE1,
.amux = 1,
}, {
.type = EM28XX_VMUX_SVIDEO,
- .vmux = SAA7115_SVIDEO3,
+ .vmux = TVP5150_SVIDEO,
.amux = 1,
} },
},
- [EM2820_BOARD_PROLINK_PLAYTV_USB2] = {
- .name = "Pixelview Prolink PlayTV USB 2.0",
+ [EM2883_BOARD_KWORLD_HYBRID_A316] = {
+ .name = "Kworld PlusTV HD Hybrid 330",
+ .valid = EM28XX_BOARD_NOT_VALIDATED,
.vchannels = 3,
- .tda9887_conf = TDA9887_PRESENT,
- .tuner_type = TUNER_YMEC_TVF_5533MF,
- .decoder = EM28XX_SAA7113,
+ .is_em2800 = 0,
+ .tuner_type = TUNER_XC2028,
+ .decoder = EM28XX_TVP5150,
.input = { {
.type = EM28XX_VMUX_TELEVISION,
- .vmux = SAA7115_COMPOSITE2,
- .amux = EM28XX_AMUX_LINE_IN,
+ .vmux = TVP5150_COMPOSITE0,
+ .amux = 0,
}, {
.type = EM28XX_VMUX_COMPOSITE1,
- .vmux = SAA7115_COMPOSITE0,
- .amux = EM28XX_AMUX_LINE_IN,
+ .vmux = TVP5150_COMPOSITE1,
+ .amux = 1,
}, {
.type = EM28XX_VMUX_SVIDEO,
- .vmux = SAA7115_SVIDEO3,
- .amux = EM28XX_AMUX_LINE_IN,
+ .vmux = TVP5150_SVIDEO,
+ .amux = 1,
} },
},
- [EM2860_BOARD_POINTNIX_INTRAORAL_CAMERA] = {
- .name = "PointNix Intra-Oral Camera",
- .has_snapshot_button = 1,
- .vchannels = 1,
+ [EM2820_BOARD_COMPRO_VIDEOMATE_FORYOU] = {
+ .name = "Compro VideoMate ForYou/Stereo",
+ .vchannels = 2,
+ .tuner_type = TUNER_LG_PAL_NEW_TAPC,
.tda9887_conf = TDA9887_PRESENT,
- .tuner_type = TUNER_ABSENT,
- .decoder = EM28XX_SAA7113,
+ .decoder = EM28XX_TVP5150,
.input = { {
+ .type = EM28XX_VMUX_TELEVISION,
+ .vmux = TVP5150_COMPOSITE0,
+ .amux = EM28XX_AMUX_LINE_IN,
+ }, {
.type = EM28XX_VMUX_SVIDEO,
- .vmux = SAA7115_SVIDEO3,
- .amux = 0,
+ .vmux = TVP5150_SVIDEO,
+ .amux = EM28XX_AMUX_LINE_IN,
} },
},
};
/* table of devices that work with this driver */
struct usb_device_id em28xx_id_table [] = {
{ USB_DEVICE(0xeb1a, 0x2750),
- .driver_info = EM2820_BOARD_UNKNOWN },
+ .driver_info = EM2750_BOARD_UNKNOWN },
+ { USB_DEVICE(0xeb1a, 0x2751),
+ .driver_info = EM2750_BOARD_UNKNOWN },
{ USB_DEVICE(0xeb1a, 0x2800),
.driver_info = EM2800_BOARD_UNKNOWN },
{ USB_DEVICE(0xeb1a, 0x2820),
.driver_info = EM2820_BOARD_UNKNOWN },
{ USB_DEVICE(0xeb1a, 0x2883),
.driver_info = EM2820_BOARD_UNKNOWN },
+ { USB_DEVICE(0xeb1a, 0xe300),
+ .driver_info = EM2861_BOARD_KWORLD_PVRTV_300U },
+ { USB_DEVICE(0xeb1a, 0xe305),
+ .driver_info = EM2880_BOARD_KWORLD_DVB_305U },
+ { USB_DEVICE(0xeb1a, 0xe310),
+ .driver_info = EM2880_BOARD_MSI_DIGIVOX_AD },
+ { USB_DEVICE(0xeb1a, 0xa316),
+ .driver_info = EM2883_BOARD_KWORLD_HYBRID_A316 },
+ { USB_DEVICE(0xeb1a, 0xe320),
+ .driver_info = EM2880_BOARD_MSI_DIGIVOX_AD_II },
+ { USB_DEVICE(0xeb1a, 0xe323),
+ .driver_info = EM2882_BOARD_KWORLD_VS_DVBT },
+ { USB_DEVICE(0xeb1a, 0xe350),
+ .driver_info = EM2870_BOARD_KWORLD_350U },
+ { USB_DEVICE(0xeb1a, 0xe355),
+ .driver_info = EM2870_BOARD_KWORLD_355U },
+ { USB_DEVICE(0xeb1a, 0x2801),
+ .driver_info = EM2800_BOARD_GRABBEEX_USB2800 },
+ { USB_DEVICE(0xeb1a, 0xe357),
+ .driver_info = EM2870_BOARD_KWORLD_355U },
{ USB_DEVICE(0x0ccd, 0x0036),
.driver_info = EM2820_BOARD_TERRATEC_CINERGY_250 },
- { USB_DEVICE(0x2304, 0x0208),
- .driver_info = EM2820_BOARD_PINNACLE_USB_2 },
+ { USB_DEVICE(0x0ccd, 0x004c),
+ .driver_info = EM2880_BOARD_TERRATEC_HYBRID_XS_FR },
+ { USB_DEVICE(0x0ccd, 0x004f),
+ .driver_info = EM2860_BOARD_TERRATEC_HYBRID_XS },
+ { USB_DEVICE(0x0ccd, 0x005e),
+ .driver_info = EM2882_BOARD_TERRATEC_HYBRID_XS },
+ { USB_DEVICE(0x0ccd, 0x0042),
+ .driver_info = EM2880_BOARD_TERRATEC_HYBRID_XS },
+ { USB_DEVICE(0x0ccd, 0x0043),
+ .driver_info = EM2870_BOARD_TERRATEC_XS },
+ { USB_DEVICE(0x0ccd, 0x0047),
+ .driver_info = EM2880_BOARD_TERRATEC_PRODIGY_XS },
+ { USB_DEVICE(0x185b, 0x2870),
+ .driver_info = EM2870_BOARD_COMPRO_VIDEOMATE },
+ { USB_DEVICE(0x185b, 0x2041),
+ .driver_info = EM2820_BOARD_COMPRO_VIDEOMATE_FORYOU },
{ USB_DEVICE(0x2040, 0x4200),
.driver_info = EM2820_BOARD_HAUPPAUGE_WINTV_USB_2 },
{ USB_DEVICE(0x2040, 0x4201),
.driver_info = EM2820_BOARD_HAUPPAUGE_WINTV_USB_2 },
- { USB_DEVICE(0x2304, 0x0207),
- .driver_info = EM2820_BOARD_PINNACLE_DVC_90 },
- { USB_DEVICE(0x2304, 0x021a),
- .driver_info = EM2820_BOARD_PINNACLE_DVC_90 },
- { USB_DEVICE(0x2304, 0x0227),
- .driver_info = EM2880_BOARD_PINNACLE_PCTV_HD_PRO },
{ USB_DEVICE(0x2040, 0x6500),
.driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900 },
{ USB_DEVICE(0x2040, 0x6502),
.driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2 },
{ USB_DEVICE(0x2040, 0x6513), /* HCW HVR-980 */
- .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 },
+ .driver_info = EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950 },
{ USB_DEVICE(0x2040, 0x6517), /* HP HVR-950 */
- .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 },
+ .driver_info = EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950 },
{ USB_DEVICE(0x2040, 0x651b), /* RP HVR-950 */
- .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 },
+ .driver_info = EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950 },
{ USB_DEVICE(0x2040, 0x651f), /* HCW HVR-850 */
- .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 },
- { USB_DEVICE(0x0ccd, 0x0042),
- .driver_info = EM2880_BOARD_TERRATEC_HYBRID_XS },
- { USB_DEVICE(0x0ccd, 0x0047),
- .driver_info = EM2880_BOARD_TERRATEC_PRODIGY_XS },
+ .driver_info = EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950 },
+ { USB_DEVICE(0x0438, 0xb002),
+ .driver_info = EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600 },
+ { USB_DEVICE(0x2001, 0xf112),
+ .driver_info = EM2820_BOARD_DLINK_USB_TV },
+ { USB_DEVICE(0x2304, 0x0207),
+ .driver_info = EM2820_BOARD_PINNACLE_DVC_90 },
+ { USB_DEVICE(0x2304, 0x0208),
+ .driver_info = EM2820_BOARD_PINNACLE_USB_2 },
+ { USB_DEVICE(0x2304, 0x021a),
+ .driver_info = EM2820_BOARD_PINNACLE_DVC_90 },
+ { USB_DEVICE(0x2304, 0x0226),
+ .driver_info = EM2882_BOARD_PINNACLE_HYBRID_PRO },
+ { USB_DEVICE(0x2304, 0x0227),
+ .driver_info = EM2880_BOARD_PINNACLE_PCTV_HD_PRO },
+ { USB_DEVICE(0x0413, 0x6023),
+ .driver_info = EM2800_BOARD_LEADTEK_WINFAST_USBII },
+ { USB_DEVICE(0x093b, 0xa005),
+ .driver_info = EM2861_BOARD_PLEXTOR_PX_TV100U },
{ },
};
MODULE_DEVICE_TABLE(usb, em28xx_id_table);
* Reset sequences for analog/digital modes
*/
+/* Reset for the most [analog] boards */
+static struct em28xx_reg_seq default_analog[] = {
+ {EM28XX_R08_GPIO, 0x6d, ~EM_GPIO_4, 10},
+ { -1, -1, -1, -1},
+};
+
+/* Reset for the most [digital] boards */
+static struct em28xx_reg_seq default_digital[] = {
+ {EM28XX_R08_GPIO, 0x6e, ~EM_GPIO_4, 10},
+ { -1, -1, -1, -1},
+};
+
/* Board Hauppauge WinTV HVR 900 analog */
static struct em28xx_reg_seq hauppauge_wintv_hvr_900_analog[] = {
{EM28XX_R08_GPIO, 0x2d, ~EM_GPIO_4, 10},
{ -1, -1, -1, -1},
};
-/* Board Hauppauge WinTV HVR 900 tuner_callback */
-static struct em28xx_reg_seq hauppauge_wintv_hvr_900_tuner_callback[] = {
+/* Boards - EM2880 MSI DIGIVOX AD and EM2880_BOARD_MSI_DIGIVOX_AD_II */
+static struct em28xx_reg_seq em2880_msi_digivox_ad_analog[] = {
+ {EM28XX_R08_GPIO, 0x69, ~EM_GPIO_4, 10},
+ { -1, -1, -1, -1},
+};
+
+/* Boards - EM2880 MSI DIGIVOX AD and EM2880_BOARD_MSI_DIGIVOX_AD_II */
+static struct em28xx_reg_seq em2880_msi_digivox_ad_digital[] = {
+ {EM28XX_R08_GPIO, 0x6a, ~EM_GPIO_4, 10},
+ { -1, -1, -1, -1},
+};
+
+/* Board - EM2870 Kworld 355u
+ Analog - No input analog */
+static struct em28xx_reg_seq em2870_kworld_355u_digital[] = {
+ {EM2880_R04_GPO, 0x01, 0xff, 10},
+ { -1, -1, -1, -1},
+};
+
+/* Callback for the most boards */
+static struct em28xx_reg_seq default_callback[] = {
{EM28XX_R08_GPIO, EM_GPIO_4, EM_GPIO_4, 10},
{EM28XX_R08_GPIO, 0, EM_GPIO_4, 10},
{EM28XX_R08_GPIO, EM_GPIO_4, EM_GPIO_4, 10},
{ -1, -1, -1, -1},
};
+/* Callback for EM2882 TERRATEC HYBRID XS */
+static struct em28xx_reg_seq em2882_terratec_hybrid_xs_digital[] = {
+ {EM28XX_R08_GPIO, 0x2e, 0xff, 6},
+ {EM28XX_R08_GPIO, 0x3e, ~EM_GPIO_4, 6},
+ {EM2880_R04_GPO, 0x04, 0xff, 10},
+ {EM2880_R04_GPO, 0x0c, 0xff, 10},
+ { -1, -1, -1, -1},
+};
+
/*
* EEPROM hash table for devices with generic USB IDs
*/
dev->max_range_640_480 = em28xx_boards[dev->model].max_range_640_480;
dev->has_dvb = em28xx_boards[dev->model].has_dvb;
dev->has_snapshot_button = em28xx_boards[dev->model].has_snapshot_button;
+ dev->valid = em28xx_boards[dev->model].valid;
}
/* Since em28xx_pre_card_setup() requires a proper dev->model,
case EM2880_BOARD_TERRATEC_PRODIGY_XS:
case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900:
case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2:
- case EM2880_BOARD_TERRATEC_HYBRID_XS:
- case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950:
+ case EM2860_BOARD_TERRATEC_HYBRID_XS:
+ case EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950:
case EM2880_BOARD_PINNACLE_PCTV_HD_PRO:
+ case EM2882_BOARD_PINNACLE_HYBRID_PRO:
+ case EM2883_BOARD_KWORLD_HYBRID_A316:
+ case EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600:
+ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
+ em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
+ msleep(50);
+
+ /* Sets GPO/GPIO sequences for this device */
+ dev->analog_gpio = hauppauge_wintv_hvr_900_analog;
+ dev->digital_gpio = hauppauge_wintv_hvr_900_digital;
+ dev->tun_analog_gpio = default_callback;
+ dev->tun_digital_gpio = default_callback;
+ break;
+
+ case EM2882_BOARD_TERRATEC_HYBRID_XS:
em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
msleep(50);
+ /* should be added ir_codes here */
+
/* Sets GPO/GPIO sequences for this device */
dev->analog_gpio = hauppauge_wintv_hvr_900_analog;
dev->digital_gpio = hauppauge_wintv_hvr_900_digital;
- dev->tun_analog_gpio = hauppauge_wintv_hvr_900_tuner_callback;
- dev->tun_digital_gpio = hauppauge_wintv_hvr_900_tuner_callback;
+ dev->tun_analog_gpio = default_callback;
+ dev->tun_digital_gpio = em2882_terratec_hybrid_xs_digital;
+ break;
+
+ case EM2880_BOARD_TERRATEC_HYBRID_XS_FR:
+ case EM2880_BOARD_TERRATEC_HYBRID_XS:
+ case EM2870_BOARD_TERRATEC_XS:
+ case EM2881_BOARD_PINNACLE_HYBRID_PRO:
+ case EM2880_BOARD_KWORLD_DVB_310U:
+ case EM2870_BOARD_KWORLD_350U:
+ case EM2881_BOARD_DNT_DA2_HYBRID:
+ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
+ em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
+ msleep(50);
+
+ /* NOTE: EM2881_DNT_DA2_HYBRID spend 140 msleep for digital
+ and analog commands. If this commands doesn't work,
+ add this timer. */
+
+ /* Sets GPO/GPIO sequences for this device */
+ dev->analog_gpio = default_analog;
+ dev->digital_gpio = default_digital;
+ dev->tun_analog_gpio = default_callback;
+ dev->tun_digital_gpio = default_callback;
+ break;
+
+ case EM2880_BOARD_MSI_DIGIVOX_AD:
+ case EM2880_BOARD_MSI_DIGIVOX_AD_II:
+ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
+ em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
+ msleep(50);
+
+ /* Sets GPO/GPIO sequences for this device */
+ dev->analog_gpio = em2880_msi_digivox_ad_analog;
+ dev->digital_gpio = em2880_msi_digivox_ad_digital;
+ dev->tun_analog_gpio = default_callback;
+ dev->tun_digital_gpio = default_callback;
+ break;
+
+ case EM2750_BOARD_UNKNOWN:
+ case EM2750_BOARD_DLCW_130:
+ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x0a", 1);
+ break;
+
+ case EM2861_BOARD_PLEXTOR_PX_TV100U:
+ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
+ em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
+ /* FIXME guess */
+ /* Turn on analog audio output */
+ em28xx_write_regs_req(dev, 0x00, 0x08, "\xfd", 1);
+ break;
+
+ case EM2861_BOARD_KWORLD_PVRTV_300U:
+ case EM2880_BOARD_KWORLD_DVB_305U:
+ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
+ em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x4c", 1);
+ msleep(10);
+ em28xx_write_regs(dev, 0x08, "\x6d", 1);
+ msleep(10);
+ em28xx_write_regs(dev, 0x08, "\x7d", 1);
+ msleep(10);
+ break;
+
+ case EM2870_BOARD_KWORLD_355U:
+ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
+ em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
+ msleep(50);
+
+ /* Sets GPO/GPIO sequences for this device */
+ dev->digital_gpio = em2870_kworld_355u_digital;
+ break;
+
+ case EM2870_BOARD_COMPRO_VIDEOMATE:
+ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
+ em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
+ /* TODO: someone can do some cleanup here...
+ not everything's needed */
+ em28xx_write_regs(dev, 0x04, "\x00", 1);
+ msleep(10);
+ em28xx_write_regs(dev, 0x04, "\x01", 1);
+ msleep(10);
+ em28xx_write_regs(dev, 0x08, "\xfd", 1);
+ mdelay(70);
+ em28xx_write_regs(dev, 0x08, "\xfc", 1);
+ mdelay(70);
+ em28xx_write_regs(dev, 0x08, "\xdc", 1);
+ mdelay(70);
+ em28xx_write_regs(dev, 0x08, "\xfc", 1);
+ mdelay(70);
+ break;
+
+ case EM2870_BOARD_TERRATEC_XS_MT2060:
+ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
+ em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
+ /* this device needs some gpio writes to get the DVB-T
+ demod work */
+ em28xx_write_regs(dev, 0x08, "\xfe", 1);
+ mdelay(70);
+ em28xx_write_regs(dev, 0x08, "\xde", 1);
+ mdelay(70);
+ dev->em28xx_write_regs(dev, 0x08, "\xfe", 1);
+ mdelay(70);
+ break;
+
+ case EM2870_BOARD_PINNACLE_PCTV_DVB:
+ em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
+ /* this device needs some gpio writes to get the
+ DVB-T demod work */
+ em28xx_write_regs(dev, 0x08, "\xfe", 1);
+ mdelay(70);
+ em28xx_write_regs(dev, 0x08, "\xde", 1);
+ mdelay(70);
+ em28xx_write_regs(dev, 0x08, "\xfe", 1);
+ mdelay(70);
+ /* switch em2880 rc protocol */
+ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x22", 1);
+ /* should be added ir_codes here */
+ break;
+
+ case EM2820_BOARD_GADMEI_UTV310:
+ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
+ em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
+ /* Turn on analog audio output */
+ em28xx_write_regs_req(dev, 0x00, 0x08, "\xfd", 1);
+ break;
+
+ case EM2860_BOARD_GADMEI_UTV330:
+ /* Turn on IR */
+ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x07", 1);
+ em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
+ /* should be added ir_codes here */
+ break;
+ case EM2820_BOARD_MSI_VOX_USB_2:
+ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
+ em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
+ /* enables audio for that device */
+ em28xx_write_regs_req(dev, 0x00, 0x08, "\xfd", 1);
break;
}
case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900:
ctl->demod = XC3028_FE_ZARLINK456;
break;
+ case EM2880_BOARD_TERRATEC_HYBRID_XS:
+ ctl->demod = XC3028_FE_ZARLINK456;
+ break;
case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2:
/* djh - Not sure which demod we need here */
ctl->demod = XC3028_FE_DEFAULT;
break;
- case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950:
+ case EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950:
case EM2880_BOARD_PINNACLE_PCTV_HD_PRO:
+ case EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600:
/* FIXME: Better to specify the needed IF */
ctl->demod = XC3028_FE_DEFAULT;
break;
break;
case (EM2800_BOARD_KWORLD_USB2800):
break;
+ case (EM2800_BOARD_GRABBEEX_USB2800):
+ break;
}
}
case EM2820_BOARD_HAUPPAUGE_WINTV_USB_2:
case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900:
case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2:
- case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950:
+ case EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950:
{
struct tveeprom tv;
#ifdef CONFIG_MODULES
dev->tuner_type = tv.tuner_type;
- if (tv.audio_processor == AUDIO_CHIP_MSP34XX) {
+ if (tv.audio_processor == V4L2_IDENT_MSPX4XX) {
dev->i2s_speed = 2048000;
dev->has_msp34xx = 1;
}
case EM2800_BOARD_UNKNOWN:
if (!em28xx_hint_board(dev))
em28xx_set_model(dev);
+ break;
}
if (dev->has_snapshot_button)
em28xx_register_snapshot_button(dev);
+ if (dev->valid == EM28XX_BOARD_NOT_VALIDATED) {
+ em28xx_errdev("\n\n");
+ em28xx_errdev("The support for this board weren't "
+ "valid yet.\n");
+ em28xx_errdev("Please send a report of having this working\n");
+ em28xx_errdev("not to V4L mailing list (and/or to other "
+ "addresses)\n\n");
+ }
+
/* Allow override tuner type by a module parameter */
if (tuner >= 0)
dev->tuner_type = tuner;
(c) 2008 Devin Heitmueller <devin.heitmueller@gmail.com>
- Fixes for the driver to properly work with HVR-950
- Fixes for the driver to properly work with Pinnacle PCTV HD Pro Stick
+ - Fixes for the driver to properly work with AMD ATI TV Wonder HD 600
(c) 2008 Aidan Thornton <makosoft@googlemail.com>
em28xx_set_mode(dev, EM28XX_DIGITAL_MODE);
/* init frontend */
switch (dev->model) {
- case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950:
+ case EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950:
case EM2880_BOARD_PINNACLE_PCTV_HD_PRO:
+ case EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600:
dvb->frontend = dvb_attach(lgdt330x_attach,
&em2880_lgdt3303_dev,
&dev->i2c_adap);
}
break;
#endif
+ case EM2880_BOARD_TERRATEC_HYBRID_XS:
+ dvb->frontend = dvb_attach(zl10353_attach,
+ &em28xx_zl10353_with_xc3028,
+ &dev->i2c_adap);
+ if (attach_xc3028(0x61, dev) < 0) {
+ result = -EINVAL;
+ goto out_free;
+ }
+ break;
default:
printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card"
" isn't supported yet\n",
#include "em28xx.h"
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/msp3400.h>
#include <media/tuner.h>
.compat_ioctl = v4l_compat_ioctl32,
};
-static const struct file_operations radio_fops = {
- .owner = THIS_MODULE,
- .open = em28xx_v4l2_open,
- .release = em28xx_v4l2_close,
- .ioctl = video_ioctl2,
- .compat_ioctl = v4l_compat_ioctl32,
- .llseek = no_llseek,
-};
-
-static const struct video_device em28xx_video_template = {
- .fops = &em28xx_v4l_fops,
- .release = video_device_release,
-
- .minor = -1,
+static const struct v4l2_ioctl_ops video_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
#ifdef CONFIG_VIDEO_V4L1_COMPAT
.vidiocgmbuf = vidiocgmbuf,
#endif
+};
+
+static const struct video_device em28xx_video_template = {
+ .fops = &em28xx_v4l_fops,
+ .release = video_device_release,
+ .ioctl_ops = &video_ioctl_ops,
+
+ .minor = -1,
.tvnorms = V4L2_STD_ALL,
.current_norm = V4L2_STD_PAL,
};
-static struct video_device em28xx_radio_template = {
- .name = "em28xx-radio",
- .type = VID_TYPE_TUNER,
- .fops = &radio_fops,
- .minor = -1,
+static const struct file_operations radio_fops = {
+ .owner = THIS_MODULE,
+ .open = em28xx_v4l2_open,
+ .release = em28xx_v4l2_close,
+ .ioctl = video_ioctl2,
+ .compat_ioctl = v4l_compat_ioctl32,
+ .llseek = no_llseek,
+};
+
+static const struct v4l2_ioctl_ops radio_ioctl_ops = {
.vidioc_querycap = radio_querycap,
.vidioc_g_tuner = radio_g_tuner,
.vidioc_enum_input = radio_enum_input,
#endif
};
+static struct video_device em28xx_radio_template = {
+ .name = "em28xx-radio",
+ .fops = &radio_fops,
+ .ioctl_ops = &radio_ioctl_ops,
+ .minor = -1,
+};
+
/******************************** usb interface ******************************/
static struct video_device *em28xx_vdev_init(struct em28xx *dev,
const struct video_device *template,
- const int type,
const char *type_name)
{
struct video_device *vfd;
return NULL;
*vfd = *template;
vfd->minor = -1;
- vfd->dev = &dev->udev->dev;
+ vfd->parent = &dev->udev->dev;
vfd->release = video_device_release;
- vfd->type = type;
vfd->debug = video_debug;
snprintf(vfd->name, sizeof(vfd->name), "%s %s",
list_add_tail(&dev->devlist, &em28xx_devlist);
/* allocate and fill video video_device struct */
- dev->vdev = em28xx_vdev_init(dev, &em28xx_video_template,
- VID_TYPE_CAPTURE, "video");
+ dev->vdev = em28xx_vdev_init(dev, &em28xx_video_template, "video");
if (NULL == dev->vdev) {
em28xx_errdev("cannot allocate video_device.\n");
goto fail_unreg;
}
- if (dev->tuner_type != TUNER_ABSENT)
- dev->vdev->type |= VID_TYPE_TUNER;
/* register v4l2 video video_device */
retval = video_register_device(dev->vdev, VFL_TYPE_GRABBER,
}
/* Allocate and fill vbi video_device struct */
- dev->vbi_dev = em28xx_vdev_init(dev, &em28xx_video_template,
- VFL_TYPE_VBI, "vbi");
+ dev->vbi_dev = em28xx_vdev_init(dev, &em28xx_video_template, "vbi");
/* register v4l2 vbi video_device */
if (video_register_device(dev->vbi_dev, VFL_TYPE_VBI,
vbi_nr[dev->devno]) < 0) {
}
if (em28xx_boards[dev->model].radio.type == EM28XX_RADIO) {
- dev->radio_dev = em28xx_vdev_init(dev, &em28xx_radio_template,
- VFL_TYPE_RADIO, "radio");
+ dev->radio_dev = em28xx_vdev_init(dev, &em28xx_radio_template, "radio");
if (NULL == dev->radio_dev) {
em28xx_errdev("cannot allocate video_device.\n");
goto fail_unreg;
#define EM2880_BOARD_TERRATEC_PRODIGY_XS 13
#define EM2820_BOARD_PROLINK_PLAYTV_USB2 14
#define EM2800_BOARD_VGEAR_POCKETTV 15
-#define EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 16
+#define EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950 16
#define EM2880_BOARD_PINNACLE_PCTV_HD_PRO 17
#define EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2 18
#define EM2860_BOARD_POINTNIX_INTRAORAL_CAMERA 19
+#define EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600 20
+#define EM2800_BOARD_GRABBEEX_USB2800 21
+#define EM2750_BOARD_UNKNOWN 22
+#define EM2750_BOARD_DLCW_130 23
+#define EM2820_BOARD_DLINK_USB_TV 24
+#define EM2820_BOARD_GADMEI_UTV310 25
+#define EM2820_BOARD_HERCULES_SMART_TV_USB2 26
+#define EM2820_BOARD_PINNACLE_USB_2_FM1216ME 27
+#define EM2820_BOARD_LEADTEK_WINFAST_USBII_DELUXE 28
+#define EM2820_BOARD_PINNACLE_DVC_100 29
+#define EM2820_BOARD_VIDEOLOGY_20K14XUSB 30
+#define EM2821_BOARD_USBGEAR_VD204 31
+#define EM2821_BOARD_SUPERCOMP_USB_2 32
+#define EM2821_BOARD_PROLINK_PLAYTV_USB2 33
+#define EM2860_BOARD_TERRATEC_HYBRID_XS 34
+#define EM2860_BOARD_TYPHOON_DVD_MAKER 35
+#define EM2860_BOARD_NETGMBH_CAM 36
+#define EM2860_BOARD_GADMEI_UTV330 37
+#define EM2861_BOARD_YAKUMO_MOVIE_MIXER 38
+#define EM2861_BOARD_KWORLD_PVRTV_300U 39
+#define EM2861_BOARD_PLEXTOR_PX_TV100U 40
+#define EM2870_BOARD_KWORLD_350U 41
+#define EM2870_BOARD_KWORLD_355U 42
+#define EM2870_BOARD_TERRATEC_XS 43
+#define EM2870_BOARD_TERRATEC_XS_MT2060 44
+#define EM2870_BOARD_PINNACLE_PCTV_DVB 45
+#define EM2870_BOARD_COMPRO_VIDEOMATE 46
+#define EM2880_BOARD_KWORLD_DVB_305U 47
+#define EM2880_BOARD_KWORLD_DVB_310U 48
+#define EM2880_BOARD_MSI_DIGIVOX_AD 49
+#define EM2880_BOARD_MSI_DIGIVOX_AD_II 50
+#define EM2880_BOARD_TERRATEC_HYBRID_XS_FR 51
+#define EM2881_BOARD_DNT_DA2_HYBRID 52
+#define EM2881_BOARD_PINNACLE_HYBRID_PRO 53
+#define EM2882_BOARD_KWORLD_VS_DVBT 54
+#define EM2882_BOARD_TERRATEC_HYBRID_XS 55
+#define EM2882_BOARD_PINNACLE_HYBRID_PRO 56
+#define EM2883_BOARD_KWORLD_HYBRID_A316 57
+#define EM2820_BOARD_COMPRO_VIDEOMATE_FORYOU 58
/* Limits minimum and default number of buffers */
#define EM28XX_MIN_BUF 4
#define EM28XX_DEF_BUF 8
+/* Params for validated field */
+#define EM28XX_BOARD_NOT_VALIDATED 1
+#define EM28XX_BOARD_VALIDATED 0
+
/* maximum number of em28xx boards */
#define EM28XX_MAXBOARDS 4 /*FIXME: should be bigger */
unsigned int max_range_640_480:1;
unsigned int has_dvb:1;
unsigned int has_snapshot_button:1;
+ unsigned int valid:1;
enum em28xx_decoder decoder;
unsigned int max_range_640_480:1;
unsigned int has_dvb:1;
unsigned int has_snapshot_button:1;
+ unsigned int valid:1; /* report for validated boards */
/* Some older em28xx chips needs a waiting time after writing */
unsigned int wait_after_write;
v4l2_std_id norm; /* selected tv norm */
int ctl_freq; /* selected frequency */
unsigned int ctl_input; /* selected input */
- unsigned int ctl_ainput; /* slected audio input */
+ unsigned int ctl_ainput;/* selected audio input */
int mute;
int volume;
/* frame properties */
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/page-flags.h>
+#include <media/v4l2-ioctl.h>
#include <asm/byteorder.h>
#include <asm/page.h>
#include <asm/uaccess.h>
static int et61x251_create_sysfs(struct et61x251_device* cam)
{
- struct device *classdev = &(cam->v4ldev->class_dev);
+ struct device *classdev = &(cam->v4ldev->dev);
int err = 0;
if ((err = device_create_file(classdev, &dev_attr_reg)))
}
strcpy(cam->v4ldev->name, "ET61X[12]51 PC Camera");
- cam->v4ldev->owner = THIS_MODULE;
- cam->v4ldev->type = VID_TYPE_CAPTURE | VID_TYPE_SCALES;
cam->v4ldev->fops = &et61x251_fops;
cam->v4ldev->minor = video_nr[dev_nr];
cam->v4ldev->release = video_device_release;
#define CONEX_CAM 1 /* special JPEG header */
#include "jpeg.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("GSPCA USB Conexant Camera Driver");
MODULE_LICENSE("GPL");
struct cam *cam;
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x01;
cam->cam_mode = vga_mode;
cam->nmodes = sizeof vga_mode / sizeof vga_mode[0];
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x0572, 0x0041), DVNM("Creative Notebook cx11646")},
+ {USB_DEVICE(0x0572, 0x0041)},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("Etoms USB Camera Driver");
MODULE_LICENSE("GPL");
{
struct sd *sd = (struct sd *) gspca_dev;
struct cam *cam;
- __u16 vendor;
- __u16 product;
-
- vendor = id->idVendor;
- product = id->idProduct;
-/* switch (vendor) { */
-/* case 0x102c: * Etoms */
- switch (product) {
- case 0x6151:
- sd->sensor = SENSOR_PAS106; /* Etoms61x151 */
- break;
- case 0x6251:
- sd->sensor = SENSOR_TAS5130CXX; /* Etoms61x251 */
- break;
-/* } */
-/* break; */
- }
+
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 1;
+ sd->sensor = id->driver_info;
if (sd->sensor == SENSOR_PAS106) {
cam->cam_mode = sif_mode;
cam->nmodes = sizeof sif_mode / sizeof sif_mode[0];
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static __devinitdata struct usb_device_id device_table[] = {
#ifndef CONFIG_USB_ET61X251
- {USB_DEVICE(0x102c, 0x6151), DVNM("Qcam Sangha CIF")},
+ {USB_DEVICE(0x102c, 0x6151), .driver_info = SENSOR_PAS106},
#endif
- {USB_DEVICE(0x102c, 0x6251), DVNM("Qcam xxxxxx VGA")},
+ {USB_DEVICE(0x102c, 0x6251), .driver_info = SENSOR_TAS5130CXX},
{}
};
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
#include <asm/page.h>
#include <linux/uaccess.h>
#include <linux/jiffies.h>
+#include <media/v4l2-ioctl.h>
#include "gspca.h"
MODULE_DESCRIPTION("GSPCA USB Camera Driver");
MODULE_LICENSE("GPL");
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
+#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 2, 0)
static int video_nr = -1;
&frame->v4l2_buf.timestamp);
frame->v4l2_buf.sequence = ++gspca_dev->sequence;
} else if (gspca_dev->last_packet_type == DISCARD_PACKET) {
+ if (packet_type == LAST_PACKET)
+ gspca_dev->last_packet_type = packet_type;
return frame;
}
* This routine may be called many times when the bandwidth is too small
* (the bandwidth is checked on urb submit).
*/
-struct usb_host_endpoint *get_isoc_ep(struct gspca_dev *gspca_dev)
+static struct usb_host_endpoint *get_isoc_ep(struct gspca_dev *gspca_dev)
{
struct usb_interface *intf;
struct usb_host_endpoint *ep;
memset(cap, 0, sizeof *cap);
strncpy(cap->driver, gspca_dev->sd_desc->name, sizeof cap->driver);
- strncpy(cap->card, gspca_dev->cam.dev_name, sizeof cap->card);
+/* strncpy(cap->card, gspca_dev->cam.dev_name, sizeof cap->card); */
+ if (gspca_dev->dev->product != NULL) {
+ strncpy(cap->card, gspca_dev->dev->product,
+ sizeof cap->card);
+ } else {
+ snprintf(cap->card, sizeof cap->card,
+ "USB Camera (%04x:%04x)",
+ le16_to_cpu(gspca_dev->dev->descriptor.idVendor),
+ le16_to_cpu(gspca_dev->dev->descriptor.idProduct));
+ }
strncpy(cap->bus_info, gspca_dev->dev->bus->bus_name,
sizeof cap->bus_info);
cap->version = DRIVER_VERSION_NUMBER;
.poll = dev_poll,
};
-static struct video_device gspca_template = {
- .name = "gspca main driver",
- .type = VID_TYPE_CAPTURE,
- .fops = &dev_fops,
- .release = dev_release, /* mandatory */
- .minor = -1,
+static const struct v4l2_ioctl_ops dev_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_dqbuf = vidioc_dqbuf,
.vidioc_qbuf = vidioc_qbuf,
#endif
};
+static struct video_device gspca_template = {
+ .name = "gspca main driver",
+ .fops = &dev_fops,
+ .ioctl_ops = &dev_ioctl_ops,
+ .release = dev_release, /* mandatory */
+ .minor = -1,
+};
+
/*
* probe and create a new gspca device
*
/* init video stuff */
memcpy(&gspca_dev->vdev, &gspca_template, sizeof gspca_template);
- gspca_dev->vdev.dev = &dev->dev;
+ gspca_dev->vdev.parent = &dev->dev;
memcpy(&gspca_dev->fops, &dev_fops, sizeof gspca_dev->fops);
gspca_dev->vdev.fops = &gspca_dev->fops;
gspca_dev->fops.owner = module; /* module protection */
+ gspca_dev->present = 1;
ret = video_register_device(&gspca_dev->vdev,
VFL_TYPE_GRABBER,
video_nr);
goto out;
}
- gspca_dev->present = 1;
usb_set_intfdata(intf, gspca_dev);
PDEBUG(D_PROBE, "probe ok");
return 0;
/* -- module insert / remove -- */
static int __init gspca_init(void)
{
- info("main v%s registered", version);
+ info("main v%d.%d.%d registered",
+ (DRIVER_VERSION_NUMBER >> 16) & 0xff,
+ (DRIVER_VERSION_NUMBER >> 8) & 0xff,
+ DRIVER_VERSION_NUMBER & 0xff);
return 0;
}
static void __exit gspca_exit(void)
#include "gspca.h"
#include "jpeg.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("GSPCA/Mars USB Camera Driver");
MODULE_LICENSE("GPL");
struct cam *cam;
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x01;
cam->cam_mode = vga_mode;
cam->nmodes = sizeof vga_mode / sizeof vga_mode[0];
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x093a, 0x050f), DVNM("Mars-Semi Pc-Camera")},
+ {USB_DEVICE(0x093a, 0x050f)},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Jean-Francois Moine <http://moinejf.free.fr>");
MODULE_DESCRIPTION("OV519 USB Camera Driver");
MODULE_LICENSE("GPL");
cam->cam_mode = sif_mode;
cam->nmodes = sizeof sif_mode / sizeof sif_mode[0];
}
- cam->dev_name = (char *) id->driver_info;
sd->brightness = sd_ctrls[SD_BRIGHTNESS].qctrl.default_value;
sd->contrast = sd_ctrls[SD_CONTRAST].qctrl.default_value;
sd->colors = sd_ctrls[SD_COLOR].qctrl.default_value;
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x041e, 0x4052), DVNM("Creative Live! VISTA IM")},
- {USB_DEVICE(0x041e, 0x405f), DVNM("Creative Live! VISTA VF0330")},
- {USB_DEVICE(0x041e, 0x4060), DVNM("Creative Live! VISTA VF0350")},
- {USB_DEVICE(0x041e, 0x4061), DVNM("Creative Live! VISTA VF0400")},
- {USB_DEVICE(0x041e, 0x4064), DVNM("Creative Live! VISTA VF0420")},
- {USB_DEVICE(0x041e, 0x4068), DVNM("Creative Live! VISTA VF0470")},
- {USB_DEVICE(0x045e, 0x028c), DVNM("Microsoft xbox cam")},
- {USB_DEVICE(0x054c, 0x0154), DVNM("Sonny toy4")},
- {USB_DEVICE(0x054c, 0x0155), DVNM("Sonny toy5")},
- {USB_DEVICE(0x05a9, 0x0519), DVNM("OmniVision")},
- {USB_DEVICE(0x05a9, 0x0530), DVNM("OmniVision")},
- {USB_DEVICE(0x05a9, 0x4519), DVNM("OmniVision")},
- {USB_DEVICE(0x05a9, 0x8519), DVNM("OmniVision")},
+ {USB_DEVICE(0x041e, 0x4052)},
+ {USB_DEVICE(0x041e, 0x405f)},
+ {USB_DEVICE(0x041e, 0x4060)},
+ {USB_DEVICE(0x041e, 0x4061)},
+ {USB_DEVICE(0x041e, 0x4064)},
+ {USB_DEVICE(0x041e, 0x4068)},
+ {USB_DEVICE(0x045e, 0x028c)},
+ {USB_DEVICE(0x054c, 0x0154)},
+ {USB_DEVICE(0x054c, 0x0155)},
+ {USB_DEVICE(0x05a9, 0x0519)},
+ {USB_DEVICE(0x05a9, 0x0530)},
+ {USB_DEVICE(0x05a9, 0x4519)},
+ {USB_DEVICE(0x05a9, 0x8519)},
{}
};
#undef DVNAME
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Hans de Goede <j.w.r.degoede@hhs.nl>");
MODULE_DESCRIPTION("Pixart PAC207");
MODULE_LICENSE("GPL");
}
-int pac207_write_reg(struct gspca_dev *gspca_dev, u16 index, u16 value)
+static int pac207_write_reg(struct gspca_dev *gspca_dev, u16 index, u16 value)
{
struct usb_device *udev = gspca_dev->dev;
int err;
return err;
}
-
-int pac207_read_reg(struct gspca_dev *gspca_dev, u16 index)
+static int pac207_read_reg(struct gspca_dev *gspca_dev, u16 index)
{
struct usb_device *udev = gspca_dev->dev;
int res;
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x041e, 0x4028), DVNM("Creative Webcam Vista Plus")},
- {USB_DEVICE(0x093a, 0x2460), DVNM("Q-Tec Webcam 100")},
- {USB_DEVICE(0x093a, 0x2463), DVNM("Philips spc200nc pac207")},
- {USB_DEVICE(0x093a, 0x2464), DVNM("Labtec Webcam 1200")},
- {USB_DEVICE(0x093a, 0x2468), DVNM("PAC207")},
- {USB_DEVICE(0x093a, 0x2470), DVNM("Genius GF112")},
- {USB_DEVICE(0x093a, 0x2471), DVNM("Genius VideoCam GE111")},
- {USB_DEVICE(0x093a, 0x2472), DVNM("Genius VideoCam GE110")},
- {USB_DEVICE(0x2001, 0xf115), DVNM("D-Link DSB-C120")},
+ {USB_DEVICE(0x041e, 0x4028)},
+ {USB_DEVICE(0x093a, 0x2460)},
+ {USB_DEVICE(0x093a, 0x2463)},
+ {USB_DEVICE(0x093a, 0x2464)},
+ {USB_DEVICE(0x093a, 0x2468)},
+ {USB_DEVICE(0x093a, 0x2470)},
+ {USB_DEVICE(0x093a, 0x2471)},
+ {USB_DEVICE(0x093a, 0x2472)},
+ {USB_DEVICE(0x2001, 0xf115)},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Thomas Kaiser thomas@kaiser-linux.li");
MODULE_DESCRIPTION("Pixart PAC7311");
MODULE_LICENSE("GPL");
reg_w(gspca_dev, 0x3e, 0x20);
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x05;
cam->cam_mode = vga_mode;
cam->nmodes = ARRAY_SIZE(vga_mode);
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x093a, 0x2600), DVNM("Typhoon")},
- {USB_DEVICE(0x093a, 0x2601), DVNM("Philips SPC610NC")},
- {USB_DEVICE(0x093a, 0x2603), DVNM("PAC7312")},
- {USB_DEVICE(0x093a, 0x2608), DVNM("Trust WB-3300p")},
- {USB_DEVICE(0x093a, 0x260e), DVNM("Gigaware VGA PC Camera")},
- /* and also ', Trust WB-3350p, SIGMA cam 2350' */
- {USB_DEVICE(0x093a, 0x260f), DVNM("SnakeCam")},
- {USB_DEVICE(0x093a, 0x2621), DVNM("PAC731x")},
+ {USB_DEVICE(0x093a, 0x2600)},
+ {USB_DEVICE(0x093a, 0x2601)},
+ {USB_DEVICE(0x093a, 0x2603)},
+ {USB_DEVICE(0x093a, 0x2608)},
+ {USB_DEVICE(0x093a, 0x260e)},
+ {USB_DEVICE(0x093a, 0x260f)},
+ {USB_DEVICE(0x093a, 0x2621)},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 8)
-static const char version[] = "2.1.8";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("GSPCA/SN9C102 USB Camera Driver");
MODULE_LICENSE("GPL");
unsigned char brightness;
unsigned char autogain;
unsigned char autogain_ignore_frames;
+ unsigned char frames_to_drop;
unsigned char freq; /* light freq filter setting */
- unsigned char saturation;
- unsigned char hue;
- unsigned char contrast;
unsigned char fr_h_sz; /* size of frame header */
char sensor; /* Type of image sensor chip */
#define SENSOR_HV7131R 0
#define SENSOR_OV6650 1
#define SENSOR_OV7630 2
-#define SENSOR_OV7630_3 3
-#define SENSOR_PAS106 4
-#define SENSOR_PAS202 5
-#define SENSOR_TAS5110 6
-#define SENSOR_TAS5130CXX 7
+#define SENSOR_PAS106 3
+#define SENSOR_PAS202 4
+#define SENSOR_TAS5110 5
+#define SENSOR_TAS5130CXX 6
char sensor_has_gain;
__u8 sensor_addr;
+ __u8 reg11;
};
+/* flags used in the device id table */
+#define F_GAIN 0x01 /* has gain */
+#define F_AUTO 0x02 /* has autogain */
+#define F_SIF 0x04 /* sif or vga */
+#define F_H18 0x08 /* long (18 b) or short (12 b) frame header */
+
#define COMP2 0x8f
#define COMP 0xc7 /* 0x87 //0x07 */
#define COMP1 0xc9 /* 0x89 //0x09 */
static int sd_getautogain(struct gspca_dev *gspca_dev, __s32 *val);
static int sd_setfreq(struct gspca_dev *gspca_dev, __s32 val);
static int sd_getfreq(struct gspca_dev *gspca_dev, __s32 *val);
-static int sd_setsaturation(struct gspca_dev *gspca_dev, __s32 val);
-static int sd_getsaturation(struct gspca_dev *gspca_dev, __s32 *val);
-static int sd_sethue(struct gspca_dev *gspca_dev, __s32 val);
-static int sd_gethue(struct gspca_dev *gspca_dev, __s32 *val);
-static int sd_setcontrast(struct gspca_dev *gspca_dev, __s32 val);
-static int sd_getcontrast(struct gspca_dev *gspca_dev, __s32 *val);
static struct ctrl sd_ctrls[] = {
{
.set = sd_setfreq,
.get = sd_getfreq,
},
- {
- {
- .id = V4L2_CID_SATURATION,
- .type = V4L2_CTRL_TYPE_INTEGER,
- .name = "Saturation",
- .minimum = 0,
- .maximum = 255,
- .step = 1,
-#define SATURATION_DEF 127
- .default_value = SATURATION_DEF,
- },
- .set = sd_setsaturation,
- .get = sd_getsaturation,
- },
- {
- {
- .id = V4L2_CID_HUE,
- .type = V4L2_CTRL_TYPE_INTEGER,
- .name = "Hue",
- .minimum = 0,
- .maximum = 255,
- .step = 1,
-#define HUE_DEF 127
- .default_value = HUE_DEF,
- },
- .set = sd_sethue,
- .get = sd_gethue,
- },
- {
- {
- .id = V4L2_CID_CONTRAST,
- .type = V4L2_CTRL_TYPE_INTEGER,
- .name = "Contrast",
- .minimum = 0,
- .maximum = 255,
- .step = 1,
-#define CONTRAST_DEF 127
- .default_value = CONTRAST_DEF,
- },
- .set = sd_setcontrast,
- .get = sd_getcontrast,
- },
};
static struct v4l2_pix_format vga_mode[] = {
.priv = 0},
};
-static const __u8 probe_ov7630[] = {0x08, 0x44};
-
static const __u8 initHv7131[] = {
0x46, 0x77, 0x00, 0x04, 0x00, 0x00, 0x00, 0x80, 0x11, 0x00, 0x00, 0x00,
0x00, 0x00,
0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, /* r21 .. r28 */
0x90, 0xa0, 0xb0, 0xc0, 0xd0, 0xe0, 0xf0, 0xff /* r29 .. r30 */
};
-static const __u8 ov7630_sensor_init_com[][8] = {
+static const __u8 ov7630_sensor_init[][8] = {
{0xa0, 0x21, 0x12, 0x80, 0x00, 0x00, 0x00, 0x10},
{0xb0, 0x21, 0x01, 0x77, 0x3a, 0x00, 0x00, 0x10},
/* {0xd0, 0x21, 0x12, 0x7c, 0x01, 0x80, 0x34, 0x10}, jfm */
{0xa0, 0x21, 0x7d, 0xf7, 0x8e, 0x00, 0x30, 0x10},
{0xd0, 0x21, 0x17, 0x1c, 0xbd, 0x06, 0xf6, 0x10},
};
-static const __u8 ov7630_sensor_init[][8] = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /* delay 200ms */
- {0xa0, 0x21, 0x11, 0x01, 0xbd, 0x06, 0xf6, 0x10}, /* jfm */
- {0xa0, 0x21, 0x10, 0x57, 0xbd, 0x06, 0xf6, 0x16},
- {0xa0, 0x21, 0x76, 0x02, 0xbd, 0x06, 0xf6, 0x16},
- {0xa0, 0x21, 0x00, 0x10, 0xbd, 0x06, 0xf6, 0x15}, /* gain */
-};
-static const __u8 ov7630_sensor_init_3[][8] = {
- {0xa0, 0x21, 0x2a, 0xa0, 0x00, 0x00, 0x00, 0x10},
- {0xa0, 0x21, 0x2a, 0x80, 0x00, 0x00, 0x00, 0x10},
-};
static const __u8 initPas106[] = {
0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x40, 0x00, 0x00, 0x00,
switch (sd->sensor) {
case SENSOR_OV6650:
- case SENSOR_OV7630_3:
case SENSOR_OV7630: {
__u8 i2cOV[] =
{0xa0, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x10};
case SENSOR_OV6650:
gain >>= 1;
/* fall thru */
- case SENSOR_OV7630_3: {
+ case SENSOR_OV7630: {
__u8 i2c[] = {0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10};
i2c[1] = sd->sensor_addr;
break;
}
case SENSOR_OV6650:
- case SENSOR_OV7630_3: {
+ case SENSOR_OV7630: {
/* The ov6650 / ov7630 have 2 registers which both influence
exposure, register 11, whose low nibble sets the nr off fps
according to: fps = 30 / (low_nibble + 1)
The code maps our 0 - 510 ms exposure ctrl to these 2
registers, trying to keep fps as high as possible.
*/
- __u8 i2c[] = {0xb0, 0x00, 0x10, 0x00, 0xc0, 0x00, 0x00, 0x10};
- int reg10, reg11;
+ __u8 i2c[] = {0xb0, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x10};
+ int reg10, reg11, reg10_max;
+
/* ov6645 datasheet says reg10_max is 9a, but that uses
tline * 2 * reg10 as formula for calculating texpo, the
ov6650 probably uses the same formula as the 7730 which uses
tline * 4 * reg10, which explains why the reg10max we've
found experimentally for the ov6650 is exactly half that of
the ov6645. The ov7630 datasheet says the max is 0x41. */
- const int reg10_max = (sd->sensor == SENSOR_OV6650)
- ? 0x4d : 0x41;
+ if (sd->sensor == SENSOR_OV6650) {
+ reg10_max = 0x4d;
+ i2c[4] = 0xc0; /* OV6650 needs non default vsync pol */
+ } else
+ reg10_max = 0x41;
reg11 = (60 * sd->exposure + 999) / 1000;
if (reg11 < 1)
else if (reg10 > reg10_max)
reg10 = reg10_max;
+ /* In 640x480, if the reg11 has less than 3, the image is
+ unstable (not enough bandwidth). */
+ if (gspca_dev->width == 640 && reg11 < 3)
+ reg11 = 3;
+
/* Write reg 10 and reg11 low nibble */
i2c[1] = sd->sensor_addr;
i2c[3] = reg10;
i2c[4] |= reg11 - 1;
- if (sd->sensor == SENSOR_OV7630_3) {
- __u8 reg76 = reg10 & 0x03;
- __u8 i2c_reg76[] = {0xa0, 0x21, 0x76, 0x00,
- 0x00, 0x00, 0x00, 0x10};
- reg10 >>= 2;
- i2c_reg76[3] = reg76;
- if (i2c_w(gspca_dev, i2c_reg76) < 0)
- PDEBUG(D_ERR, "i2c error exposure");
- }
- if (i2c_w(gspca_dev, i2c) < 0)
+
+ /* If register 11 didn't change, don't change it */
+ if (sd->reg11 == reg11 )
+ i2c[0] = 0xa0;
+
+ if (i2c_w(gspca_dev, i2c) == 0)
+ sd->reg11 = reg11;
+ else
PDEBUG(D_ERR, "i2c error exposure");
break;
}
switch (sd->sensor) {
case SENSOR_OV6650:
- case SENSOR_OV7630_3: {
+ case SENSOR_OV7630: {
/* Framerate adjust register for artificial light 50 hz flicker
- compensation, identical to ov6630 0x2b register, see ov6630
- datasheet.
- 0x4f -> (30 fps -> 25 fps), 0x00 -> no adjustment */
+ compensation, for the ov6650 this is identical to ov6630
+ 0x2b register, see ov6630 datasheet.
+ 0x4f / 0x8a -> (30 fps -> 25 fps), 0x00 -> no adjustment */
__u8 i2c[] = {0xa0, 0x00, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x10};
switch (sd->freq) {
default:
}
}
-static void setsaturation(struct gspca_dev *gspca_dev)
-{
- struct sd *sd = (struct sd *) gspca_dev;
-
- switch (sd->sensor) {
-/* case SENSOR_OV6650: */
- case SENSOR_OV7630_3:
- case SENSOR_OV7630: {
- __u8 i2c[] = {0xa0, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10};
- i2c[1] = sd->sensor_addr;
- i2c[3] = sd->saturation & 0xf0;
- if (i2c_w(gspca_dev, i2c) < 0)
- PDEBUG(D_ERR, "i2c error setsaturation");
- else
- PDEBUG(D_CONF, "saturation set to: %d",
- (int)sd->saturation);
- break;
- }
- }
-}
-
-static void sethue(struct gspca_dev *gspca_dev)
-{
- struct sd *sd = (struct sd *) gspca_dev;
-
- switch (sd->sensor) {
-/* case SENSOR_OV6650: */
- case SENSOR_OV7630_3:
- case SENSOR_OV7630: {
- __u8 i2c[] = {0xa0, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x10};
- i2c[1] = sd->sensor_addr;
- i2c[3] = 0x20 | (sd->hue >> 3);
- if (i2c_w(gspca_dev, i2c) < 0)
- PDEBUG(D_ERR, "i2c error setsaturation");
- else
- PDEBUG(D_CONF, "hue set to: %d", (int)sd->hue);
- break;
- }
- }
-}
-
-static void setcontrast(struct gspca_dev *gspca_dev)
-{
- struct sd *sd = (struct sd *) gspca_dev;
-
- switch (sd->sensor) {
-/* case SENSOR_OV6650: */
- case SENSOR_OV7630_3:
- case SENSOR_OV7630: {
- __u8 i2c[] = {0xa0, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x10};
- i2c[1] = sd->sensor_addr;
- i2c[3] = 0x20 | (sd->contrast >> 3);
- if (i2c_w(gspca_dev, i2c) < 0)
- PDEBUG(D_ERR, "i2c error setcontrast");
- else
- PDEBUG(D_CONF, "contrast set to: %d",
- (int)sd->contrast);
- break;
- }
- }
-}
-
-
static void do_autogain(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
{
struct sd *sd = (struct sd *) gspca_dev;
struct cam *cam;
- __u16 product;
int sif = 0;
/* nctrls depends upon the sensor, so we use a per cam copy */
memcpy(&sd->sd_desc, gspca_dev->sd_desc, sizeof(struct sd_desc));
gspca_dev->sd_desc = &sd->sd_desc;
- sd->fr_h_sz = 12; /* default size of the frame header */
- sd->sd_desc.nctrls = 2; /* default nb of ctrls */
- sd->autogain = AUTOGAIN_DEF; /* default is autogain active */
-
- product = id->idProduct;
-/* switch (id->idVendor) { */
-/* case 0x0c45: * Sonix */
- switch (product) {
- case 0x6001: /* SN9C102 */
- case 0x6005: /* SN9C101 */
- case 0x6007: /* SN9C101 */
- sd->sensor = SENSOR_TAS5110;
- sd->sensor_has_gain = 1;
- sd->sd_desc.nctrls = 4;
- sd->sd_desc.dq_callback = do_autogain;
- sif = 1;
- break;
- case 0x6009: /* SN9C101 */
- case 0x600d: /* SN9C101 */
- case 0x6029: /* SN9C101 */
- sd->sensor = SENSOR_PAS106;
- sif = 1;
- break;
- case 0x6011: /* SN9C101 - SN9C101G */
- sd->sensor = SENSOR_OV6650;
- sd->sensor_has_gain = 1;
- sd->sensor_addr = 0x60;
- sd->sd_desc.nctrls = 5;
- sd->sd_desc.dq_callback = do_autogain;
- sif = 1;
- break;
- case 0x6019: /* SN9C101 */
- case 0x602c: /* SN9C102 */
- case 0x602e: /* SN9C102 */
- sd->sensor = SENSOR_OV7630;
- sd->sensor_addr = 0x21;
- break;
- case 0x60b0: /* SN9C103 */
- sd->sensor = SENSOR_OV7630_3;
- sd->sensor_addr = 0x21;
- sd->fr_h_sz = 18; /* size of frame header */
- sd->sensor_has_gain = 1;
- sd->sd_desc.nctrls = 8;
- sd->sd_desc.dq_callback = do_autogain;
- sd->autogain = 0;
- break;
- case 0x6024: /* SN9C102 */
- case 0x6025: /* SN9C102 */
- sd->sensor = SENSOR_TAS5130CXX;
- break;
- case 0x6028: /* SN9C102 */
- sd->sensor = SENSOR_PAS202;
- break;
- case 0x602d: /* SN9C102 */
- sd->sensor = SENSOR_HV7131R;
- break;
- case 0x60af: /* SN9C103 */
- sd->sensor = SENSOR_PAS202;
- sd->fr_h_sz = 18; /* size of frame header (?) */
- break;
- }
-/* break; */
-/* } */
+ /* copy the webcam info from the device id */
+ sd->sensor = (id->driver_info >> 24) & 0xff;
+ if (id->driver_info & (F_GAIN << 16))
+ sd->sensor_has_gain = 1;
+ if (id->driver_info & (F_AUTO << 16))
+ sd->sd_desc.dq_callback = do_autogain;
+ if (id->driver_info & (F_SIF << 16))
+ sif = 1;
+ if (id->driver_info & (F_H18 << 16))
+ sd->fr_h_sz = 18; /* size of frame header */
+ else
+ sd->fr_h_sz = 12;
+ sd->sd_desc.nctrls = (id->driver_info >> 8) & 0xff;
+ sd->sensor_addr = id->driver_info & 0xff;
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x01;
if (!sif) {
cam->cam_mode = vga_mode;
cam->nmodes = ARRAY_SIZE(vga_mode);
- if (sd->sensor == SENSOR_OV7630_3) {
- /* We only have 320x240 & 640x480 */
- cam->cam_mode++;
- cam->nmodes--;
- }
} else {
cam->cam_mode = sif_mode;
cam->nmodes = ARRAY_SIZE(sif_mode);
sd->brightness = BRIGHTNESS_DEF;
sd->gain = GAIN_DEF;
sd->exposure = EXPOSURE_DEF;
+ sd->autogain = AUTOGAIN_DEF;
sd->freq = FREQ_DEF;
- sd->contrast = CONTRAST_DEF;
- sd->saturation = SATURATION_DEF;
- sd->hue = HUE_DEF;
- if (sd->sensor == SENSOR_OV7630_3) /* jfm: from win trace */
- reg_w(gspca_dev, 0x01, probe_ov7630, sizeof probe_ov7630);
+
return 0;
}
static void sd_start(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
- int mode, l;
+ int mode, l = 0x1f;
const __u8 *sn9c10x;
- __u8 reg01, reg17;
__u8 reg17_19[3];
mode = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv;
reg17_19[2] = 0x20;
break;
case SENSOR_OV7630:
- sn9c10x = initOv7630;
- reg17_19[0] = 0x68;
- reg17_19[1] = (mode << 4) | COMP2;
- reg17_19[2] = MCK_INIT1;
- break;
- case SENSOR_OV7630_3:
- sn9c10x = initOv7630_3;
+ if (sd->fr_h_sz == 18) { /* SN9C103 */
+ sn9c10x = initOv7630_3;
+ l = sizeof initOv7630_3;
+ } else
+ sn9c10x = initOv7630;
reg17_19[0] = 0x68;
reg17_19[1] = (mode << 4) | COMP2;
reg17_19[2] = MCK_INIT1;
reg17_19[2] = mode ? 0x23 : 0x43;
break;
}
- switch (sd->sensor) {
- case SENSOR_OV7630:
- reg01 = 0x06;
- reg17 = 0x29;
- l = sizeof initOv7630;
- break;
- case SENSOR_OV7630_3:
- reg01 = 0x44;
- reg17 = 0x68;
- l = sizeof initOv7630_3;
- break;
- default:
- reg01 = sn9c10x[0];
- reg17 = sn9c10x[0x17 - 1];
- l = 0x1f;
- break;
- }
/* reg 0x01 bit 2 video transfert on */
- reg_w(gspca_dev, 0x01, ®01, 1);
+ reg_w(gspca_dev, 0x01, &sn9c10x[0x01 - 1], 1);
/* reg 0x17 SensorClk enable inv Clk 0x60 */
- reg_w(gspca_dev, 0x17, ®17, 1);
-/*fixme: for ov7630 102
- reg_w(gspca_dev, 0x01, {0x06, sn9c10x[1]}, 2); */
+ reg_w(gspca_dev, 0x17, &sn9c10x[0x17 - 1], 1);
/* Set the registers from the template */
reg_w_big(gspca_dev, 0x01, sn9c10x, l);
switch (sd->sensor) {
sizeof ov6650_sensor_init);
break;
case SENSOR_OV7630:
- i2c_w_vector(gspca_dev, ov7630_sensor_init_com,
- sizeof ov7630_sensor_init_com);
- msleep(200);
i2c_w_vector(gspca_dev, ov7630_sensor_init,
sizeof ov7630_sensor_init);
- break;
- case SENSOR_OV7630_3:
- i2c_w_vector(gspca_dev, ov7630_sensor_init_com,
- sizeof ov7630_sensor_init_com);
- msleep(200);
- i2c_w(gspca_dev, ov7630_sensor_init_3[mode]);
+ if (sd->fr_h_sz == 18) { /* SN9C103 */
+ const __u8 i2c[] = { 0xa0, 0x21, 0x13, 0x80, 0x00,
+ 0x00, 0x00, 0x10 };
+ i2c_w(gspca_dev, i2c);
+ }
break;
case SENSOR_PAS106:
pas106_i2cinit(gspca_dev);
reg_w(gspca_dev, 0x18, ®17_19[1], 2);
msleep(20);
+ sd->reg11 = -1;
+
setgain(gspca_dev);
setbrightness(gspca_dev);
setexposure(gspca_dev);
setfreq(gspca_dev);
- setsaturation(gspca_dev);
- sethue(gspca_dev);
- setcontrast(gspca_dev);
+ sd->frames_to_drop = 0;
sd->autogain_ignore_frames = 0;
atomic_set(&sd->avg_lum, -1);
}
&& data[3 + i] == 0xc4
&& data[4 + i] == 0xc4
&& data[5 + i] == 0x96) { /* start of frame */
- frame = gspca_frame_add(gspca_dev, LAST_PACKET,
- frame, data, 0);
+ int lum = -1;
+ int pkt_type = LAST_PACKET;
+
if (len - i < sd->fr_h_sz) {
- atomic_set(&sd->avg_lum, -1);
PDEBUG(D_STREAM, "packet too short to"
" get avg brightness");
} else if (sd->fr_h_sz == 12) {
- atomic_set(&sd->avg_lum,
- data[i + 8] +
- (data[i + 9] << 8));
+ lum = data[i + 8] + (data[i + 9] << 8);
} else {
- atomic_set(&sd->avg_lum,
- data[i + 9] +
- (data[i + 10] << 8));
+ lum = data[i + 9] +
+ (data[i + 10] << 8);
+ }
+ if (lum == 0) {
+ lum = -1;
+ sd->frames_to_drop = 2;
+ }
+ atomic_set(&sd->avg_lum, lum);
+
+ if (sd->frames_to_drop) {
+ sd->frames_to_drop--;
+ pkt_type = DISCARD_PACKET;
}
+
+ frame = gspca_frame_add(gspca_dev, pkt_type,
+ frame, data, 0);
data += i + sd->fr_h_sz;
len -= i + sd->fr_h_sz;
gspca_frame_add(gspca_dev, FIRST_PACKET,
return 0;
}
-static int sd_setsaturation(struct gspca_dev *gspca_dev, __s32 val)
-{
- struct sd *sd = (struct sd *) gspca_dev;
-
- sd->saturation = val;
- if (gspca_dev->streaming)
- setsaturation(gspca_dev);
- return 0;
-}
-
-static int sd_getsaturation(struct gspca_dev *gspca_dev, __s32 *val)
-{
- struct sd *sd = (struct sd *) gspca_dev;
-
- *val = sd->saturation;
- return 0;
-}
-
-static int sd_sethue(struct gspca_dev *gspca_dev, __s32 val)
-{
- struct sd *sd = (struct sd *) gspca_dev;
-
- sd->hue = val;
- if (gspca_dev->streaming)
- sethue(gspca_dev);
- return 0;
-}
-
-static int sd_gethue(struct gspca_dev *gspca_dev, __s32 *val)
-{
- struct sd *sd = (struct sd *) gspca_dev;
-
- *val = sd->hue;
- return 0;
-}
-
-static int sd_setcontrast(struct gspca_dev *gspca_dev, __s32 val)
-{
- struct sd *sd = (struct sd *) gspca_dev;
-
- sd->contrast = val;
- if (gspca_dev->streaming)
- setcontrast(gspca_dev);
- return 0;
-}
-
-static int sd_getcontrast(struct gspca_dev *gspca_dev, __s32 *val)
-{
- struct sd *sd = (struct sd *) gspca_dev;
-
- *val = sd->contrast;
- return 0;
-}
-
static int sd_querymenu(struct gspca_dev *gspca_dev,
struct v4l2_querymenu *menu)
{
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
+#define SFCI(sensor, flags, nctrls, i2c_addr) \
+ .driver_info = (SENSOR_ ## sensor << 24) \
+ | ((flags) << 16) \
+ | ((nctrls) << 8) \
+ | (i2c_addr)
static __devinitdata struct usb_device_id device_table[] = {
#ifndef CONFIG_USB_SN9C102
- {USB_DEVICE(0x0c45, 0x6001), DVNM("Genius VideoCAM NB")},
- {USB_DEVICE(0x0c45, 0x6005), DVNM("Sweex Tas5110")},
- {USB_DEVICE(0x0c45, 0x6007), DVNM("Sonix sn9c101 + Tas5110D")},
- {USB_DEVICE(0x0c45, 0x6009), DVNM("spcaCam@120")},
- {USB_DEVICE(0x0c45, 0x600d), DVNM("spcaCam@120")},
+ {USB_DEVICE(0x0c45, 0x6001), /* SN9C102 */
+ SFCI(TAS5110, F_GAIN|F_AUTO|F_SIF, 4, 0)},
+ {USB_DEVICE(0x0c45, 0x6005), /* SN9C101 */
+ SFCI(TAS5110, F_GAIN|F_AUTO|F_SIF, 4, 0)},
+ {USB_DEVICE(0x0c45, 0x6007), /* SN9C101 */
+ SFCI(TAS5110, F_GAIN|F_AUTO|F_SIF, 4, 0)},
+ {USB_DEVICE(0x0c45, 0x6009), /* SN9C101 */
+ SFCI(PAS106, F_SIF, 2, 0)},
+ {USB_DEVICE(0x0c45, 0x600d), /* SN9C101 */
+ SFCI(PAS106, F_SIF, 2, 0)},
#endif
- {USB_DEVICE(0x0c45, 0x6011), DVNM("MAX Webcam Microdia")},
+ {USB_DEVICE(0x0c45, 0x6011), /* SN9C101 - SN9C101G */
+ SFCI(OV6650, F_GAIN|F_AUTO|F_SIF, 5, 0x60)},
#ifndef CONFIG_USB_SN9C102
- {USB_DEVICE(0x0c45, 0x6019), DVNM("Generic Sonix OV7630")},
- {USB_DEVICE(0x0c45, 0x6024), DVNM("Generic Sonix Tas5130c")},
- {USB_DEVICE(0x0c45, 0x6025), DVNM("Xcam Shanga")},
- {USB_DEVICE(0x0c45, 0x6028), DVNM("Sonix Btc Pc380")},
- {USB_DEVICE(0x0c45, 0x6029), DVNM("spcaCam@150")},
- {USB_DEVICE(0x0c45, 0x602c), DVNM("Generic Sonix OV7630")},
- {USB_DEVICE(0x0c45, 0x602d), DVNM("LIC-200 LG")},
- {USB_DEVICE(0x0c45, 0x602e), DVNM("Genius VideoCam Messenger")},
- {USB_DEVICE(0x0c45, 0x60af), DVNM("Trust WB3100P")},
- {USB_DEVICE(0x0c45, 0x60b0), DVNM("Genius VideoCam Look")},
+ {USB_DEVICE(0x0c45, 0x6019), /* SN9C101 */
+ SFCI(OV7630, F_GAIN|F_AUTO, 5, 0x21)},
+ {USB_DEVICE(0x0c45, 0x6024), /* SN9C102 */
+ SFCI(TAS5130CXX, 0, 2, 0)},
+ {USB_DEVICE(0x0c45, 0x6025), /* SN9C102 */
+ SFCI(TAS5130CXX, 0, 2, 0)},
+ {USB_DEVICE(0x0c45, 0x6028), /* SN9C102 */
+ SFCI(PAS202, 0, 2, 0)},
+ {USB_DEVICE(0x0c45, 0x6029), /* SN9C101 */
+ SFCI(PAS106, F_SIF, 2, 0)},
+ {USB_DEVICE(0x0c45, 0x602c), /* SN9C102 */
+ SFCI(OV7630, F_GAIN|F_AUTO, 5, 0x21)},
+ {USB_DEVICE(0x0c45, 0x602d), /* SN9C102 */
+ SFCI(HV7131R, 0, 2, 0)},
+ {USB_DEVICE(0x0c45, 0x602e), /* SN9C102 */
+ SFCI(OV7630, F_GAIN|F_AUTO, 5, 0x21)},
+ {USB_DEVICE(0x0c45, 0x60af), /* SN9C103 */
+ SFCI(PAS202, F_H18, 2, 0)},
+ {USB_DEVICE(0x0c45, 0x60b0), /* SN9C103 */
+ SFCI(OV7630, F_GAIN|F_AUTO|F_H18, 5, 0x21)},
#endif
{}
};
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
#include "jpeg.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("GSPCA/SONIX JPEG USB Camera Driver");
MODULE_LICENSE("GPL");
};
static const __u8 ov7660_sensor_init[][8] = {
{0xa1, 0x21, 0x12, 0x80, 0x00, 0x00, 0x00, 0x10}, /* reset SCCB */
+/* (delay 20ms) */
{0xa1, 0x21, 0x12, 0x05, 0x00, 0x00, 0x00, 0x10},
/* Outformat ?? rawRGB */
{0xa1, 0x21, 0x13, 0xb8, 0x00, 0x00, 0x00, 0x10}, /* init COM8 */
value, 0,
gspca_dev->usb_buf, len,
500);
+ PDEBUG(D_USBI, "reg_r [%02x] -> %02x", value, gspca_dev->usb_buf[0]);
}
+static void reg_w1(struct gspca_dev *gspca_dev,
+ __u16 value,
+ __u8 data)
+{
+ PDEBUG(D_USBO, "reg_w1 [%02x] = %02x", value, data);
+ gspca_dev->usb_buf[0] = data;
+ usb_control_msg(gspca_dev->dev,
+ usb_sndctrlpipe(gspca_dev->dev, 0),
+ 0x08,
+ USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE,
+ value,
+ 0,
+ gspca_dev->usb_buf, 1,
+ 500);
+}
static void reg_w(struct gspca_dev *gspca_dev,
__u16 value,
const __u8 *buffer,
int len)
{
+ PDEBUG(D_USBO, "reg_w [%02x] = %02x %02x ..",
+ value, buffer[0], buffer[1]);
if (len <= sizeof gspca_dev->usb_buf) {
memcpy(gspca_dev->usb_buf, buffer, len);
usb_control_msg(gspca_dev->dev,
}
}
-/* I2C write 2 bytes */
-static void i2c_w2(struct gspca_dev *gspca_dev,
- const __u8 *buffer)
+/* I2C write 1 byte */
+static void i2c_w1(struct gspca_dev *gspca_dev, __u8 reg, __u8 val)
{
struct sd *sd = (struct sd *) gspca_dev;
- __u8 mode[8];
- /* is i2c ready */
- mode[0] = 0x81 | (2 << 4);
- mode[1] = sd->i2c_base;
- mode[2] = buffer[0];
- mode[3] = buffer[1];
- mode[4] = 0;
- mode[5] = 0;
- mode[6] = 0;
- mode[7] = 0x10;
- reg_w(gspca_dev, 0x08, mode, 8);
+ PDEBUG(D_USBO, "i2c_w2 [%02x] = %02x", reg, val);
+ gspca_dev->usb_buf[0] = 0x81 | (2 << 4); /* = a1 */
+ gspca_dev->usb_buf[1] = sd->i2c_base;
+ gspca_dev->usb_buf[2] = reg;
+ gspca_dev->usb_buf[3] = val;
+ gspca_dev->usb_buf[4] = 0;
+ gspca_dev->usb_buf[5] = 0;
+ gspca_dev->usb_buf[6] = 0;
+ gspca_dev->usb_buf[7] = 0x10;
+ usb_control_msg(gspca_dev->dev,
+ usb_sndctrlpipe(gspca_dev->dev, 0),
+ 0x08,
+ USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE,
+ 0x08, /* value = i2c */
+ 0,
+ gspca_dev->usb_buf, 8,
+ 500);
}
/* I2C write 8 bytes */
static void i2c_w8(struct gspca_dev *gspca_dev,
const __u8 *buffer)
{
- reg_w(gspca_dev, 0x08, buffer, 8);
- msleep(1);
+ memcpy(gspca_dev->usb_buf, buffer, 8);
+ usb_control_msg(gspca_dev->dev,
+ usb_sndctrlpipe(gspca_dev->dev, 0),
+ 0x08,
+ USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE,
+ 0x08, 0, /* value, index */
+ gspca_dev->usb_buf, 8,
+ 500);
}
/* read 5 bytes in gspca_dev->usb_buf */
mode[6] = 0;
mode[7] = 0x10;
i2c_w8(gspca_dev, mode);
+ msleep(2);
mode[0] = 0x81 | (5 << 4) | 0x02;
mode[2] = 0;
i2c_w8(gspca_dev, mode);
+ msleep(2);
reg_r(gspca_dev, 0x0a, 5);
}
static int probesensor(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
- __u8 reg02;
- static const __u8 datasend[] = { 2, 0 };
- /* reg val1 val2 val3 val4 */
- i2c_w2(gspca_dev, datasend);
-/* should write 0xa1 0x11 0x02 0x00 0x00 0x00 0x00 the 0x10 is add by i2cw */
+ i2c_w1(gspca_dev, 0x02, 0); /* sensor wakeup */
msleep(10);
- reg02 = 0x66;
- reg_w(gspca_dev, 0x02, ®02, 1); /* Gpio on */
+ reg_w1(gspca_dev, 0x02, 0x66); /* Gpio on */
msleep(10);
i2c_r5(gspca_dev, 0); /* read sensor id */
if (gspca_dev->usb_buf[0] == 0x02
sd->sensor = SENSOR_HV7131R;
return SENSOR_HV7131R;
}
- PDEBUG(D_PROBE, "Find Sensor %d %d %d",
+ PDEBUG(D_PROBE, "Find Sensor 0x%02x 0x%02x 0x%02x",
gspca_dev->usb_buf[0], gspca_dev->usb_buf[1],
gspca_dev->usb_buf[2]);
PDEBUG(D_PROBE, "Sensor sn9c102P Not found");
const __u8 *sn9c1xx)
{
struct sd *sd = (struct sd *) gspca_dev;
- __u8 data;
- __u8 regF1;
const __u8 *reg9a;
static const __u8 reg9a_def[] =
{0x08, 0x40, 0x20, 0x10, 0x00, 0x04};
static const __u8 reg9a_sn9c325[] =
{0x0a, 0x40, 0x38, 0x30, 0x00, 0x20};
-
- regF1 = 0x00;
- reg_w(gspca_dev, 0xf1, ®F1, 1);
- reg_w(gspca_dev, 0x01, &sn9c1xx[0], 1); /*fixme:jfm was [1] en v1*/
+ reg_w1(gspca_dev, 0xf1, 0x00);
+ reg_w1(gspca_dev, 0x01, sn9c1xx[0]); /*fixme:jfm was [1] en v1*/
/* configure gpio */
reg_w(gspca_dev, 0x01, &sn9c1xx[1], 2);
reg_w(gspca_dev, 0x08, &sn9c1xx[8], 2);
- reg_w(gspca_dev, 0x17, &sn9c1xx[0x17], 5); /* jfm was 3 */
+ reg_w(gspca_dev, 0x17, &sn9c1xx[0x17], 5); /* jfm len was 3 */
switch (sd->bridge) {
case BRIDGE_SN9C325:
reg9a = reg9a_sn9c325;
}
reg_w(gspca_dev, 0x9a, reg9a, 6);
- data = 0x60; /*fixme:jfm 60 00 00 (3) */
- reg_w(gspca_dev, 0xd4, &data, 1);
+ reg_w1(gspca_dev, 0xd4, 0x60); /*fixme:jfm 60 00 00 (3) ? */
reg_w(gspca_dev, 0x03, &sn9c1xx[3], 0x0f);
switch (sd->bridge) {
case BRIDGE_SN9C120: /* from win trace */
- data = 0x61;
- reg_w(gspca_dev, 0x01, &data, 1);
- data = 0x20;
- reg_w(gspca_dev, 0x17, &data, 1);
- data = 0x60;
- reg_w(gspca_dev, 0x01, &data, 1);
+ reg_w1(gspca_dev, 0x01, 0x61);
+ reg_w1(gspca_dev, 0x17, 0x20);
+ reg_w1(gspca_dev, 0x01, 0x60);
break;
case BRIDGE_SN9C325:
- data = 0x43;
- reg_w(gspca_dev, 0x01, &data, 1);
- data = 0xae;
- reg_w(gspca_dev, 0x17, &data, 1);
- data = 0x42;
- reg_w(gspca_dev, 0x01, &data, 1);
+ reg_w1(gspca_dev, 0x01, 0x43);
+ reg_w1(gspca_dev, 0x17, 0xae);
+ reg_w1(gspca_dev, 0x01, 0x42);
break;
default:
- data = 0x43;
- reg_w(gspca_dev, 0x01, &data, 1);
- data = 0x61;
- reg_w(gspca_dev, 0x17, &data, 1);
- data = 0x42;
- reg_w(gspca_dev, 0x01, &data, 1);
+ reg_w1(gspca_dev, 0x01, 0x43);
+ reg_w1(gspca_dev, 0x17, 0x61);
+ reg_w1(gspca_dev, 0x01, 0x42);
}
if (sd->sensor == SENSOR_HV7131R) {
{
int i = 0;
+ i2c_w8(gspca_dev, ov7660_sensor_init[i]); /* reset SCCB */
+ i++;
+ msleep(20);
while (ov7660_sensor_init[i][0]) {
i2c_w8(gspca_dev, ov7660_sensor_init[i]);
i++;
{
struct sd *sd = (struct sd *) gspca_dev;
struct cam *cam;
- __u16 vendor;
- __u16 product;
-
- vendor = id->idVendor;
- product = id->idProduct;
- sd->sensor = -1;
- switch (vendor) {
- case 0x0458: /* Genius */
-/* switch (product) {
- case 0x7025: */
- sd->bridge = BRIDGE_SN9C120;
- sd->sensor = SENSOR_MI0360;
- sd->i2c_base = 0x5d;
-/* break;
- } */
- break;
- case 0x045e:
-/* switch (product) {
- case 0x00f5:
- case 0x00f7: */
- sd->bridge = BRIDGE_SN9C105;
- sd->sensor = SENSOR_OV7660;
- sd->i2c_base = 0x21;
-/* break;
- } */
- break;
- case 0x0471: /* Philips */
-/* switch (product) {
- case 0x0327:
- case 0x0328:
- case 0x0330: */
- sd->bridge = BRIDGE_SN9C105;
- sd->sensor = SENSOR_MI0360;
- sd->i2c_base = 0x5d;
-/* break;
- } */
- break;
- case 0x0c45: /* Sonix */
- switch (product) {
- case 0x6040:
- sd->bridge = BRIDGE_SN9C102P;
-/* sd->sensor = SENSOR_MI0360; * from BW600.inf */
-/*fixme: MI0360 base=5d ? */
- sd->sensor = SENSOR_HV7131R; /* gspcav1 value */
- sd->i2c_base = 0x11;
- break;
-/* case 0x607a: * from BW600.inf
- sd->bridge = BRIDGE_SN9C102P;
- sd->sensor = SENSOR_OV7648;
- sd->i2c_base = 0x??;
- break; */
- case 0x607c:
- sd->bridge = BRIDGE_SN9C102P;
- sd->sensor = SENSOR_HV7131R;
- sd->i2c_base = 0x11;
- break;
-/* case 0x607e: * from BW600.inf
- sd->bridge = BRIDGE_SN9C102P;
- sd->sensor = SENSOR_OV7630;
- sd->i2c_base = 0x??;
- break; */
- case 0x60c0:
- sd->bridge = BRIDGE_SN9C105;
- sd->sensor = SENSOR_MI0360;
- sd->i2c_base = 0x5d;
- break;
-/* case 0x60c8: * from BW600.inf
- sd->bridge = BRIDGE_SN9C105;
- sd->sensor = SENSOR_OM6801;
- sd->i2c_base = 0x??;
- break; */
-/* case 0x60cc: * from BW600.inf
- sd->bridge = BRIDGE_SN9C105;
- sd->sensor = SENSOR_HV7131GP;
- sd->i2c_base = 0x??;
- break; */
- case 0x60ec:
- sd->bridge = BRIDGE_SN9C105;
- sd->sensor = SENSOR_MO4000;
- sd->i2c_base = 0x21;
- break;
-/* case 0x60ef: * from BW600.inf
- sd->bridge = BRIDGE_SN9C105;
- sd->sensor = SENSOR_ICM105C;
- sd->i2c_base = 0x??;
- break; */
-/* case 0x60fa: * from BW600.inf
- sd->bridge = BRIDGE_SN9C105;
- sd->sensor = SENSOR_OV7648;
- sd->i2c_base = 0x??;
- break; */
- case 0x60fb:
- sd->bridge = BRIDGE_SN9C105;
- sd->sensor = SENSOR_OV7660;
- sd->i2c_base = 0x21;
- break;
- case 0x60fc:
- sd->bridge = BRIDGE_SN9C105;
- sd->sensor = SENSOR_HV7131R;
- sd->i2c_base = 0x11;
- break;
-/* case 0x60fe: * from BW600.inf
- sd->bridge = BRIDGE_SN9C105;
- sd->sensor = SENSOR_OV7630;
- sd->i2c_base = 0x??;
- break; */
-/* case 0x6108: * from BW600.inf
- sd->bridge = BRIDGE_SN9C120;
- sd->sensor = SENSOR_OM6801;
- sd->i2c_base = 0x??;
- break; */
-/* case 0x6122: * from BW600.inf
- sd->bridge = BRIDGE_SN9C110;
- sd->sensor = SENSOR_ICM105C;
- sd->i2c_base = 0x??;
- break; */
- case 0x612a:
-/* sd->bridge = BRIDGE_SN9C110; * in BW600.inf */
- sd->bridge = BRIDGE_SN9C325;
- sd->sensor = SENSOR_OV7648;
- sd->i2c_base = 0x21;
-/*fixme: sensor_init has base = 00 et 6e!*/
- break;
-/* case 0x6123: * from BW600.inf
- sd->bridge = BRIDGE_SN9C110;
- sd->sensor = SENSOR_SanyoCCD;
- sd->i2c_base = 0x??;
- break; */
- case 0x612c:
- sd->bridge = BRIDGE_SN9C110;
- sd->sensor = SENSOR_MO4000;
- sd->i2c_base = 0x21;
- break;
-/* case 0x612e: * from BW600.inf
- sd->bridge = BRIDGE_SN9C110;
- sd->sensor = SENSOR_OV7630;
- sd->i2c_base = 0x??;
- break; */
-/* case 0x612f: * from BW600.inf
- sd->bridge = BRIDGE_SN9C110;
- sd->sensor = SENSOR_ICM105C;
- sd->i2c_base = 0x??;
- break; */
- case 0x6130:
- sd->bridge = BRIDGE_SN9C120;
- sd->sensor = SENSOR_MI0360;
- sd->i2c_base = 0x5d;
- break;
- case 0x6138:
- sd->bridge = BRIDGE_SN9C120;
- sd->sensor = SENSOR_MO4000;
- sd->i2c_base = 0x21;
- break;
-/* case 0x613a: * from BW600.inf
- sd->bridge = BRIDGE_SN9C120;
- sd->sensor = SENSOR_OV7648;
- sd->i2c_base = 0x??;
- break; */
- case 0x613b:
- sd->bridge = BRIDGE_SN9C120;
- sd->sensor = SENSOR_OV7660;
- sd->i2c_base = 0x21;
- break;
- case 0x613c:
- sd->bridge = BRIDGE_SN9C120;
- sd->sensor = SENSOR_HV7131R;
- sd->i2c_base = 0x11;
- break;
-/* case 0x613e: * from BW600.inf
- sd->bridge = BRIDGE_SN9C120;
- sd->sensor = SENSOR_OV7630;
- sd->i2c_base = 0x??;
- break; */
- }
- break;
- }
- if (sd->sensor < 0) {
- PDEBUG(D_ERR, "Invalid vendor/product %04x:%04x",
- vendor, product);
- return -EINVAL;
- }
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x01;
cam->cam_mode = vga_mode;
cam->nmodes = ARRAY_SIZE(vga_mode);
+ sd->bridge = id->driver_info >> 16;
+ sd->sensor = id->driver_info >> 8;
+ sd->i2c_base = id->driver_info;
+
sd->qindex = 4; /* set the quantization table */
sd->brightness = BRIGHTNESS_DEF;
sd->contrast = CONTRAST_DEF;
{
struct sd *sd = (struct sd *) gspca_dev;
/* const __u8 *sn9c1xx; */
- __u8 regF1;
__u8 regGpio[] = { 0x29, 0x74 };
+ __u8 regF1;
/* setup a selector by bridge */
- regF1 = 0x01;
- reg_w(gspca_dev, 0xf1, ®F1, 1);
+ reg_w1(gspca_dev, 0xf1, 0x01);
reg_r(gspca_dev, 0x00, 1); /* -> regF1 = 0x00 */
- regF1 = gspca_dev->usb_buf[0];
- reg_w(gspca_dev, 0xf1, ®F1, 1);
+ reg_w1(gspca_dev, 0xf1, gspca_dev->usb_buf[0]);
reg_r(gspca_dev, 0x00, 1);
regF1 = gspca_dev->usb_buf[0];
switch (sd->bridge) {
case BRIDGE_SN9C102P:
if (regF1 != 0x11)
return -ENODEV;
- reg_w(gspca_dev, 0x02, ®Gpio[1], 1);
+ reg_w1(gspca_dev, 0x02, regGpio[1]);
break;
case BRIDGE_SN9C105:
if (regF1 != 0x11)
return -ENODEV;
reg_w(gspca_dev, 0x02, regGpio, 2);
break;
- case BRIDGE_SN9C110:
- if (regF1 != 0x12)
- return -ENODEV;
- regGpio[1] = 0x62;
- reg_w(gspca_dev, 0x02, ®Gpio[1], 1);
- break;
case BRIDGE_SN9C120:
if (regF1 != 0x12)
return -ENODEV;
reg_w(gspca_dev, 0x02, regGpio, 2);
break;
default:
+/* case BRIDGE_SN9C110: */
/* case BRIDGE_SN9C325: */
if (regF1 != 0x12)
return -ENODEV;
- regGpio[1] = 0x62;
- reg_w(gspca_dev, 0x02, ®Gpio[1], 1);
+ reg_w1(gspca_dev, 0x02, 0x62);
break;
}
- regF1 = 0x01;
- reg_w(gspca_dev, 0xf1, ®F1, 1);
+ reg_w1(gspca_dev, 0xf1, 0x01);
return 0;
}
}
k2 = sd->brightness >> 10;
- reg_w(gspca_dev, 0x96, &k2, 1);
+ reg_w1(gspca_dev, 0x96, k2);
}
static void setcontrast(struct gspca_dev *gspca_dev)
data = (colour + 32) & 0x7f; /* blue */
else
data = (-colour + 32) & 0x7f; /* red */
- reg_w(gspca_dev, 0x05, &data, 1);
+ reg_w1(gspca_dev, 0x05, data);
}
/* -- start the camera -- */
__u8 reg17;
const __u8 *sn9c1xx;
int mode;
- static const __u8 DC29[] = { 0x6a, 0x50, 0x00, 0x00, 0x50, 0x3c };
static const __u8 C0[] = { 0x2d, 0x2d, 0x3a, 0x05, 0x04, 0x3f };
static const __u8 CA[] = { 0x28, 0xd8, 0x14, 0xec };
static const __u8 CA_sn9c120[] =
/*fixme:jfm this sequence should appear at end of sd_start */
/* with
- data = 0x44;
- reg_w(gspca_dev, 0x01, &data, 1); */
- reg_w(gspca_dev, 0x15, &sn9c1xx[0x15], 1);
- reg_w(gspca_dev, 0x16, &sn9c1xx[0x16], 1);
- reg_w(gspca_dev, 0x12, &sn9c1xx[0x12], 1);
- reg_w(gspca_dev, 0x13, &sn9c1xx[0x13], 1);
- reg_w(gspca_dev, 0x18, &sn9c1xx[0x18], 1);
- reg_w(gspca_dev, 0xd2, &DC29[0], 1);
- reg_w(gspca_dev, 0xd3, &DC29[1], 1);
- reg_w(gspca_dev, 0xc6, &DC29[2], 1);
- reg_w(gspca_dev, 0xc7, &DC29[3], 1);
- reg_w(gspca_dev, 0xc8, &DC29[4], 1);
- reg_w(gspca_dev, 0xc9, &DC29[5], 1);
+ reg_w1(gspca_dev, 0x01, 0x44); */
+ reg_w1(gspca_dev, 0x15, sn9c1xx[0x15]);
+ reg_w1(gspca_dev, 0x16, sn9c1xx[0x16]);
+ reg_w1(gspca_dev, 0x12, sn9c1xx[0x12]);
+ reg_w1(gspca_dev, 0x13, sn9c1xx[0x13]);
+ reg_w1(gspca_dev, 0x18, sn9c1xx[0x18]);
+ reg_w1(gspca_dev, 0xd2, 0x6a); /* DC29 */
+ reg_w1(gspca_dev, 0xd3, 0x50);
+ reg_w1(gspca_dev, 0xc6, 0x00);
+ reg_w1(gspca_dev, 0xc7, 0x00);
+ reg_w1(gspca_dev, 0xc8, 0x50);
+ reg_w1(gspca_dev, 0xc9, 0x3c);
/*fixme:jfm end of ending sequence */
- reg_w(gspca_dev, 0x18, &sn9c1xx[0x18], 1);
+ reg_w1(gspca_dev, 0x18, sn9c1xx[0x18]);
switch (sd->bridge) {
case BRIDGE_SN9C325:
data = 0xae;
data = 0x60;
break;
}
- reg_w(gspca_dev, 0x17, &data, 1);
- reg_w(gspca_dev, 0x05, &sn9c1xx[5], 1);
- reg_w(gspca_dev, 0x07, &sn9c1xx[7], 1);
- reg_w(gspca_dev, 0x06, &sn9c1xx[6], 1);
- reg_w(gspca_dev, 0x14, &sn9c1xx[0x14], 1);
+ reg_w1(gspca_dev, 0x17, data);
+ reg_w1(gspca_dev, 0x05, sn9c1xx[5]);
+ reg_w1(gspca_dev, 0x07, sn9c1xx[7]);
+ reg_w1(gspca_dev, 0x06, sn9c1xx[6]);
+ reg_w1(gspca_dev, 0x14, sn9c1xx[0x14]);
switch (sd->bridge) {
case BRIDGE_SN9C325:
reg_w(gspca_dev, 0x20, regsn20_sn9c325,
for (i = 0; i < 8; i++)
reg_w(gspca_dev, 0x84, reg84_sn9c325,
sizeof reg84_sn9c325);
- data = 0x0a;
- reg_w(gspca_dev, 0x9a, &data, 1);
- data = 0x60;
- reg_w(gspca_dev, 0x99, &data, 1);
+ reg_w1(gspca_dev, 0x9a, 0x0a);
+ reg_w1(gspca_dev, 0x99, 0x60);
break;
case BRIDGE_SN9C120:
reg_w(gspca_dev, 0x20, regsn20_sn9c120,
sizeof reg84_sn9c120_2);
reg_w(gspca_dev, 0x84, reg84_sn9c120_3,
sizeof reg84_sn9c120_3);
- data = 0x05;
- reg_w(gspca_dev, 0x9a, &data, 1);
- data = 0x5b;
- reg_w(gspca_dev, 0x99, &data, 1);
+ reg_w1(gspca_dev, 0x9a, 0x05);
+ reg_w1(gspca_dev, 0x99, 0x5b);
break;
default:
reg_w(gspca_dev, 0x20, regsn20, sizeof regsn20);
for (i = 0; i < 8; i++)
reg_w(gspca_dev, 0x84, reg84, sizeof reg84);
- data = 0x08;
- reg_w(gspca_dev, 0x9a, &data, 1);
- data = 0x59;
- reg_w(gspca_dev, 0x99, &data, 1);
+ reg_w1(gspca_dev, 0x9a, 0x08);
+ reg_w1(gspca_dev, 0x99, 0x59);
break;
}
mode = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv;
- reg1 = 0x02;
+ if (mode)
+ reg1 = 0x46; /* 320 clk 48Mhz */
+ else
+ reg1 = 0x06; /* 640 clk 24Mz */
reg17 = 0x61;
switch (sd->sensor) {
case SENSOR_HV7131R:
hv7131R_InitSensor(gspca_dev);
- if (mode)
- reg1 = 0x46; /* 320 clk 48Mhz */
- else
- reg1 = 0x06; /* 640 clk 24Mz */
break;
case SENSOR_MI0360:
mi0360_InitSensor(gspca_dev);
- if (mode)
- reg1 = 0x46; /* 320 clk 48Mhz */
- else
- reg1 = 0x06; /* 640 clk 24Mz */
break;
case SENSOR_MO4000:
mo4000_InitSensor(gspca_dev);
reg1 = 0x06; /* clk 24Mz */
} else {
reg17 = 0x22; /* 640 MCKSIZE */
- reg1 = 0x06; /* 640 clk 24Mz */
+/* reg1 = 0x06; * 640 clk 24Mz (done) */
}
break;
case SENSOR_OV7648:
+ ov7648_InitSensor(gspca_dev);
reg17 = 0xa2;
reg1 = 0x44;
- ov7648_InitSensor(gspca_dev);
/* if (mode)
; * 320x2...
else
if (mode) {
/* reg17 = 0x21; * 320 */
/* reg1 = 0x44; */
- reg1 = 0x46;
+/* reg1 = 0x46; (done) */
} else {
reg17 = 0xa2; /* 640 */
reg1 = 0x40;
/* here change size mode 0 -> VGA; 1 -> CIF */
data = 0x40 | sn9c1xx[0x18] | (mode << 4);
- reg_w(gspca_dev, 0x18, &data, 1);
+ reg_w1(gspca_dev, 0x18, data);
reg_w(gspca_dev, 0x100, qtable4, 0x40);
reg_w(gspca_dev, 0x140, qtable4 + 0x40, 0x40);
data = sn9c1xx[0x18] | (mode << 4);
- reg_w(gspca_dev, 0x18, &data, 1);
+ reg_w1(gspca_dev, 0x18, data);
- reg_w(gspca_dev, 0x17, ®17, 1);
- reg_w(gspca_dev, 0x01, ®1, 1);
+ reg_w1(gspca_dev, 0x17, reg17);
+ reg_w1(gspca_dev, 0x01, reg1);
setbrightness(gspca_dev);
setcontrast(gspca_dev);
}
{ 0xa1, 0x11, 0x02, 0x09, 0x00, 0x00, 0x00, 0x10 };
static const __u8 stopmi0360[] =
{ 0xb1, 0x5d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x10 };
- __u8 regF1;
__u8 data;
const __u8 *sn9c1xx;
break;
}
sn9c1xx = sn_tb[(int) sd->sensor];
- reg_w(gspca_dev, 0x01, &sn9c1xx[1], 1);
- reg_w(gspca_dev, 0x17, &sn9c1xx[0x17], 1);
- reg_w(gspca_dev, 0x01, &sn9c1xx[1], 1);
- reg_w(gspca_dev, 0x01, &data, 1);
- regF1 = 0x01;
- reg_w(gspca_dev, 0xf1, ®F1, 1);
+ reg_w1(gspca_dev, 0x01, sn9c1xx[1]);
+ reg_w1(gspca_dev, 0x17, sn9c1xx[0x17]);
+ reg_w1(gspca_dev, 0x01, sn9c1xx[1]);
+ reg_w1(gspca_dev, 0x01, data);
+ reg_w1(gspca_dev, 0xf1, 0x01);
}
static void sd_stop0(struct gspca_dev *gspca_dev)
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
+#define BSI(bridge, sensor, i2c_addr) \
+ .driver_info = (BRIDGE_ ## bridge << 16) \
+ | (SENSOR_ ## sensor << 8) \
+ | (i2c_addr)
static const __devinitdata struct usb_device_id device_table[] = {
#ifndef CONFIG_USB_SN9C102
- {USB_DEVICE(0x0458, 0x7025), DVNM("Genius Eye 311Q")},
- {USB_DEVICE(0x045e, 0x00f5), DVNM("MicroSoft VX3000")},
- {USB_DEVICE(0x045e, 0x00f7), DVNM("MicroSoft VX1000")},
- {USB_DEVICE(0x0471, 0x0327), DVNM("Philips SPC 600 NC")},
- {USB_DEVICE(0x0471, 0x0328), DVNM("Philips SPC 700 NC")},
+ {USB_DEVICE(0x0458, 0x7025), BSI(SN9C120, MI0360, 0x5d)},
+ {USB_DEVICE(0x045e, 0x00f5), BSI(SN9C105, OV7660, 0x21)},
+ {USB_DEVICE(0x045e, 0x00f7), BSI(SN9C105, OV7660, 0x21)},
+ {USB_DEVICE(0x0471, 0x0327), BSI(SN9C105, MI0360, 0x5d)},
+ {USB_DEVICE(0x0471, 0x0328), BSI(SN9C105, MI0360, 0x5d)},
#endif
- {USB_DEVICE(0x0471, 0x0330), DVNM("Philips SPC 710NC")},
- {USB_DEVICE(0x0c45, 0x6040), DVNM("Speed NVC 350K")},
- {USB_DEVICE(0x0c45, 0x607c), DVNM("Sonix sn9c102p Hv7131R")},
- {USB_DEVICE(0x0c45, 0x60c0), DVNM("Sangha Sn535")},
- {USB_DEVICE(0x0c45, 0x60ec), DVNM("SN9C105+MO4000")},
- {USB_DEVICE(0x0c45, 0x60fb), DVNM("Surfer NoName")},
- {USB_DEVICE(0x0c45, 0x60fc), DVNM("LG-LIC300")},
- {USB_DEVICE(0x0c45, 0x612a), DVNM("Avant Camera")},
- {USB_DEVICE(0x0c45, 0x612c), DVNM("Typhoon Rasy Cam 1.3MPix")},
+ {USB_DEVICE(0x0471, 0x0330), BSI(SN9C105, MI0360, 0x5d)},
+ {USB_DEVICE(0x0c45, 0x6040), BSI(SN9C102P, HV7131R, 0x11)},
+/* bw600.inf:
+ {USB_DEVICE(0x0c45, 0x6040), BSI(SN9C102P, MI0360, 0x5d)}, */
+/* {USB_DEVICE(0x0c45, 0x603a), BSI(SN9C102P, OV7648, 0x??)}, */
+/* {USB_DEVICE(0x0c45, 0x607a), BSI(SN9C102P, OV7648, 0x??)}, */
+ {USB_DEVICE(0x0c45, 0x607c), BSI(SN9C102P, HV7131R, 0x11)},
+/* {USB_DEVICE(0x0c45, 0x607e), BSI(SN9C102P, OV7630, 0x??)}, */
+ {USB_DEVICE(0x0c45, 0x60c0), BSI(SN9C105, MI0360, 0x5d)},
+/* {USB_DEVICE(0x0c45, 0x60c8), BSI(SN9C105, OM6801, 0x??)}, */
+/* {USB_DEVICE(0x0c45, 0x60cc), BSI(SN9C105, HV7131GP, 0x??)}, */
+ {USB_DEVICE(0x0c45, 0x60ec), BSI(SN9C105, MO4000, 0x21)},
+/* {USB_DEVICE(0x0c45, 0x60ef), BSI(SN9C105, ICM105C, 0x??)}, */
+/* {USB_DEVICE(0x0c45, 0x60fa), BSI(SN9C105, OV7648, 0x??)}, */
+ {USB_DEVICE(0x0c45, 0x60fb), BSI(SN9C105, OV7660, 0x21)},
+ {USB_DEVICE(0x0c45, 0x60fc), BSI(SN9C105, HV7131R, 0x11)},
+/* {USB_DEVICE(0x0c45, 0x60fe), BSI(SN9C105, OV7630, 0x??)}, */
+/* {USB_DEVICE(0x0c45, 0x6108), BSI(SN9C120, OM6801, 0x??)}, */
+/* {USB_DEVICE(0x0c45, 0x6122), BSI(SN9C110, ICM105C, 0x??)}, */
+/* {USB_DEVICE(0x0c45, 0x6123), BSI(SN9C110, SanyoCCD, 0x??)}, */
+ {USB_DEVICE(0x0c45, 0x612a), BSI(SN9C325, OV7648, 0x21)},
+/* bw600.inf:
+ {USB_DEVICE(0x0c45, 0x612a), BSI(SN9C110, OV7648, 0x21)}, */
+ {USB_DEVICE(0x0c45, 0x612c), BSI(SN9C110, MO4000, 0x21)},
+/* {USB_DEVICE(0x0c45, 0x612e), BSI(SN9C110, OV7630, 0x??)}, */
+/* {USB_DEVICE(0x0c45, 0x612f), BSI(SN9C110, ICM105C, 0x??)}, */
#ifndef CONFIG_USB_SN9C102
- {USB_DEVICE(0x0c45, 0x6130), DVNM("Sonix Pccam")},
- {USB_DEVICE(0x0c45, 0x6138), DVNM("Sn9c120 Mo4000")},
- {USB_DEVICE(0x0c45, 0x613b), DVNM("Surfer SN-206")},
- {USB_DEVICE(0x0c45, 0x613c), DVNM("Sonix Pccam168")},
+ {USB_DEVICE(0x0c45, 0x6130), BSI(SN9C120, MI0360, 0x5d)},
+ {USB_DEVICE(0x0c45, 0x6138), BSI(SN9C120, MO4000, 0x21)},
+/* {USB_DEVICE(0x0c45, 0x613a), BSI(SN9C120, OV7648, 0x??)}, */
+ {USB_DEVICE(0x0c45, 0x613b), BSI(SN9C120, OV7660, 0x21)},
+ {USB_DEVICE(0x0c45, 0x613c), BSI(SN9C120, HV7131R, 0x11)},
+/* {USB_DEVICE(0x0c45, 0x613e), BSI(SN9C120, OV7630, 0x??)}, */
#endif
+ {USB_DEVICE(0x0c45, 0x6143), BSI(SN9C120, MI0360, 0x5d)},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- info("v%s registered", version);
+ info("registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
#include "jpeg.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("GSPCA/SPCA500 USB Camera Driver");
MODULE_LICENSE("GPL");
{
struct sd *sd = (struct sd *) gspca_dev;
struct cam *cam;
- __u16 vendor;
- __u16 product;
-
- vendor = id->idVendor;
- product = id->idProduct;
- switch (vendor) {
- case 0x040a: /* Kodak cameras */
-/* switch (product) { */
-/* case 0x0300: */
- sd->subtype = KodakEZ200;
-/* break; */
-/* } */
- break;
- case 0x041e: /* Creative cameras */
-/* switch (product) { */
-/* case 0x400a: */
- sd->subtype = CreativePCCam300;
-/* break; */
-/* } */
- break;
- case 0x046d: /* Logitech Labtec */
- switch (product) {
- case 0x0890:
- sd->subtype = LogitechTraveler;
- break;
- case 0x0900:
- sd->subtype = LogitechClickSmart310;
- break;
- case 0x0901:
- sd->subtype = LogitechClickSmart510;
- break;
- }
- break;
- case 0x04a5: /* Benq */
-/* switch (product) { */
-/* case 0x300c: */
- sd->subtype = BenqDC1016;
-/* break; */
-/* } */
- break;
- case 0x04fc: /* SunPlus */
-/* switch (product) { */
-/* case 0x7333: */
- sd->subtype = PalmPixDC85;
-/* break; */
-/* } */
- break;
- case 0x055f: /* Mustek cameras */
- switch (product) {
- case 0xc200:
- sd->subtype = MustekGsmart300;
- break;
- case 0xc220:
- sd->subtype = Gsmartmini;
- break;
- }
- break;
- case 0x06bd: /* Agfa Cl20 */
-/* switch (product) { */
-/* case 0x0404: */
- sd->subtype = AgfaCl20;
-/* break; */
-/* } */
- break;
- case 0x06be: /* Optimedia */
-/* switch (product) { */
-/* case 0x0800: */
- sd->subtype = Optimedia;
-/* break; */
-/* } */
- break;
- case 0x084d: /* D-Link / Minton */
-/* switch (product) { */
-/* case 0x0003: * DSC-350 / S-Cam F5 */
- sd->subtype = DLinkDSC350;
-/* break; */
-/* } */
- break;
- case 0x08ca: /* Aiptek */
-/* switch (product) { */
-/* case 0x0103: */
- sd->subtype = AiptekPocketDV;
-/* break; */
-/* } */
- break;
- case 0x2899: /* ToptroIndustrial */
-/* switch (product) { */
-/* case 0x012c: */
- sd->subtype = ToptroIndus;
-/* break; */
-/* } */
- break;
- case 0x8086: /* Intel */
-/* switch (product) { */
-/* case 0x0630: * Pocket PC Camera */
- sd->subtype = IntelPocketPCCamera;
-/* break; */
-/* } */
- break;
- }
+
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x01;
+ sd->subtype = id->driver_info;
if (sd->subtype != LogitechClickSmart310) {
cam->cam_mode = vga_mode;
cam->nmodes = sizeof vga_mode / sizeof vga_mode[0];
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x040a, 0x0300), DVNM("Kodak EZ200")},
- {USB_DEVICE(0x041e, 0x400a), DVNM("Creative PC-CAM 300")},
- {USB_DEVICE(0x046d, 0x0890), DVNM("Logitech QuickCam traveler")},
- {USB_DEVICE(0x046d, 0x0900), DVNM("Logitech Inc. ClickSmart 310")},
- {USB_DEVICE(0x046d, 0x0901), DVNM("Logitech Inc. ClickSmart 510")},
- {USB_DEVICE(0x04a5, 0x300c), DVNM("Benq DC1016")},
- {USB_DEVICE(0x04fc, 0x7333), DVNM("PalmPixDC85")},
- {USB_DEVICE(0x055f, 0xc200), DVNM("Mustek Gsmart 300")},
- {USB_DEVICE(0x055f, 0xc220), DVNM("Gsmart Mini")},
- {USB_DEVICE(0x06bd, 0x0404), DVNM("Agfa CL20")},
- {USB_DEVICE(0x06be, 0x0800), DVNM("Optimedia")},
- {USB_DEVICE(0x084d, 0x0003), DVNM("D-Link DSC-350")},
- {USB_DEVICE(0x08ca, 0x0103), DVNM("Aiptek PocketDV")},
- {USB_DEVICE(0x2899, 0x012c), DVNM("Toptro Industrial")},
- {USB_DEVICE(0x8086, 0x0630), DVNM("Intel Pocket PC Camera")},
+ {USB_DEVICE(0x040a, 0x0300), .driver_info = KodakEZ200},
+ {USB_DEVICE(0x041e, 0x400a), .driver_info = CreativePCCam300},
+ {USB_DEVICE(0x046d, 0x0890), .driver_info = LogitechTraveler},
+ {USB_DEVICE(0x046d, 0x0900), .driver_info = LogitechClickSmart310},
+ {USB_DEVICE(0x046d, 0x0901), .driver_info = LogitechClickSmart510},
+ {USB_DEVICE(0x04a5, 0x300c), .driver_info = BenqDC1016},
+ {USB_DEVICE(0x04fc, 0x7333), .driver_info = PalmPixDC85},
+ {USB_DEVICE(0x055f, 0xc200), .driver_info = MustekGsmart300},
+ {USB_DEVICE(0x055f, 0xc220), .driver_info = Gsmartmini},
+ {USB_DEVICE(0x06bd, 0x0404), .driver_info = AgfaCl20},
+ {USB_DEVICE(0x06be, 0x0800), .driver_info = Optimedia},
+ {USB_DEVICE(0x084d, 0x0003), .driver_info = DLinkDSC350},
+ {USB_DEVICE(0x08ca, 0x0103), .driver_info = AiptekPocketDV},
+ {USB_DEVICE(0x2899, 0x012c), .driver_info = ToptroIndus},
+ {USB_DEVICE(0x8086, 0x0630), .driver_info = IntelPocketPCCamera},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("GSPCA/SPCA501 USB Camera Driver");
MODULE_LICENSE("GPL");
{
struct sd *sd = (struct sd *) gspca_dev;
struct cam *cam;
- __u16 vendor;
- __u16 product;
-
- vendor = id->idVendor;
- product = id->idProduct;
- switch (vendor) {
- case 0x0000: /* Unknow Camera */
-/* switch (product) { */
-/* case 0x0000: */
- sd->subtype = MystFromOriUnknownCamera;
-/* break; */
-/* } */
- break;
- case 0x040a: /* Kodak cameras */
-/* switch (product) { */
-/* case 0x0002: */
- sd->subtype = KodakDVC325;
-/* break; */
-/* } */
- break;
- case 0x0497: /* Smile International */
-/* switch (product) { */
-/* case 0xc001: */
- sd->subtype = SmileIntlCamera;
-/* break; */
-/* } */
- break;
- case 0x0506: /* 3COM cameras */
-/* switch (product) { */
-/* case 0x00df: */
- sd->subtype = ThreeComHomeConnectLite;
-/* break; */
-/* } */
- break;
- case 0x0733: /* Rebadged ViewQuest (Intel) and ViewQuest cameras */
- switch (product) {
- case 0x0401:
- sd->subtype = IntelCreateAndShare;
- break;
- case 0x0402:
- sd->subtype = ViewQuestM318B;
- break;
- }
- break;
- case 0x1776: /* Arowana */
-/* switch (product) { */
-/* case 0x501c: */
- sd->subtype = Arowana300KCMOSCamera;
-/* break; */
-/* } */
- break;
- }
+
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x01;
cam->cam_mode = vga_mode;
cam->nmodes = sizeof vga_mode / sizeof vga_mode[0];
+ sd->subtype = id->driver_info;
sd->brightness = sd_ctrls[MY_BRIGHTNESS].qctrl.default_value;
sd->contrast = sd_ctrls[MY_CONTRAST].qctrl.default_value;
sd->colors = sd_ctrls[MY_COLOR].qctrl.default_value;
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x040a, 0x0002), DVNM("Kodak DVC-325")},
- {USB_DEVICE(0x0497, 0xc001), DVNM("Smile International")},
- {USB_DEVICE(0x0506, 0x00df), DVNM("3Com HomeConnect Lite")},
- {USB_DEVICE(0x0733, 0x0401), DVNM("Intel Create and Share")},
- {USB_DEVICE(0x0733, 0x0402), DVNM("ViewQuest M318B")},
- {USB_DEVICE(0x1776, 0x501c), DVNM("Arowana 300K CMOS Camera")},
- {USB_DEVICE(0x0000, 0x0000), DVNM("MystFromOri Unknow Camera")},
+ {USB_DEVICE(0x040a, 0x0002), .driver_info = KodakDVC325},
+ {USB_DEVICE(0x0497, 0xc001), .driver_info = SmileIntlCamera},
+ {USB_DEVICE(0x0506, 0x00df), .driver_info = ThreeComHomeConnectLite},
+ {USB_DEVICE(0x0733, 0x0401), .driver_info = IntelCreateAndShare},
+ {USB_DEVICE(0x0733, 0x0402), .driver_info = ViewQuestM318B},
+ {USB_DEVICE(0x1776, 0x501c), .driver_info = Arowana300KCMOSCamera},
+ {USB_DEVICE(0x0000, 0x0000), .driver_info = MystFromOriUnknownCamera},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("GSPCA/SPCA505 USB Camera Driver");
MODULE_LICENSE("GPL");
struct sd {
struct gspca_dev gspca_dev; /* !! must be the first item */
- int buflen;
- unsigned char tmpbuf[640 * 480 * 3 / 2]; /* YYUV per line */
- unsigned char tmpbuf2[640 * 480 * 2]; /* YUYV */
-
unsigned char brightness;
char subtype;
};
static struct v4l2_pix_format vga_mode[] = {
- {160, 120, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 160 * 2,
- .sizeimage = 160 * 120 * 2,
+ {160, 120, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
+ .bytesperline = 160 * 3,
+ .sizeimage = 160 * 120 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 5},
- {176, 144, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 176 * 2,
- .sizeimage = 176 * 144 * 2,
+ {176, 144, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
+ .bytesperline = 176 * 3,
+ .sizeimage = 176 * 144 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 4},
- {320, 240, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 320 * 2,
- .sizeimage = 320 * 240 * 2,
+ {320, 240, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
+ .bytesperline = 320 * 3,
+ .sizeimage = 320 * 240 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 2},
- {352, 288, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 352 * 2,
- .sizeimage = 352 * 288 * 2,
+ {352, 288, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
+ .bytesperline = 352 * 3,
+ .sizeimage = 352 * 288 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 1},
- {640, 480, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 640 * 2,
- .sizeimage = 640 * 480 * 2,
+ {640, 480, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
+ .bytesperline = 640 * 3,
+ .sizeimage = 640 * 480 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 0},
};
{
struct sd *sd = (struct sd *) gspca_dev;
struct cam *cam;
- __u16 vendor;
- __u16 product;
-
- vendor = id->idVendor;
- product = id->idProduct;
- switch (vendor) {
- case 0x041e: /* Creative cameras */
-/* switch (product) { */
-/* case 0x401d: * here505b */
- sd->subtype = Nxultra;
-/* break; */
-/* } */
- break;
- case 0x0733: /* Rebadged ViewQuest (Intel) and ViewQuest cameras */
-/* switch (product) { */
-/* case 0x0430: */
-/* fixme: may be UsbGrabberPV321 BRIDGE_SPCA506 SENSOR_SAA7113 */
- sd->subtype = IntelPCCameraPro;
-/* break; */
-/* } */
- break;
- }
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x01;
cam->cam_mode = vga_mode;
+ sd->subtype = id->driver_info;
if (sd->subtype != IntelPCCameraPro)
cam->nmodes = sizeof vga_mode / sizeof vga_mode[0];
else /* no 640x480 for IntelPCCameraPro */
reg_write(gspca_dev->dev, 0x05, 0x11, 0xf);
}
-/* convert YYUV per line to YUYV (YUV 4:2:2) */
-static void yyuv_decode(unsigned char *out,
- unsigned char *in,
- int width,
- int height)
-{
- unsigned char *Ui, *Vi, *yi, *yi1;
- unsigned char *out1;
- int i, j;
-
- yi = in;
- for (i = height / 2; --i >= 0; ) {
- out1 = out + width * 2; /* next line */
- yi1 = yi + width;
- Ui = yi1 + width;
- Vi = Ui + width / 2;
- for (j = width / 2; --j >= 0; ) {
- *out++ = 128 + *yi++;
- *out++ = 128 + *Ui;
- *out++ = 128 + *yi++;
- *out++ = 128 + *Vi;
-
- *out1++ = 128 + *yi1++;
- *out1++ = 128 + *Ui++;
- *out1++ = 128 + *yi1++;
- *out1++ = 128 + *Vi++;
- }
- yi += width * 2;
- out = out1;
- }
-}
-
static void sd_pkt_scan(struct gspca_dev *gspca_dev,
struct gspca_frame *frame, /* target */
__u8 *data, /* isoc packet */
int len) /* iso packet length */
{
- struct sd *sd = (struct sd *) gspca_dev;
-
switch (data[0]) {
case 0: /* start of frame */
- if (gspca_dev->last_packet_type == FIRST_PACKET) {
- yyuv_decode(sd->tmpbuf2, sd->tmpbuf,
- gspca_dev->width,
- gspca_dev->height);
- frame = gspca_frame_add(gspca_dev,
- LAST_PACKET,
- frame,
- sd->tmpbuf2,
- gspca_dev->width
- * gspca_dev->height
- * 2);
- }
- gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
- data, 0);
+ frame = gspca_frame_add(gspca_dev, LAST_PACKET, frame,
+ data, 0);
data += SPCA50X_OFFSET_DATA;
len -= SPCA50X_OFFSET_DATA;
- if (len > 0)
- memcpy(sd->tmpbuf, data, len);
- else
- len = 0;
- sd->buflen = len;
- return;
+ gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
+ data, len);
+ break;
case 0xff: /* drop */
/* gspca_dev->last_packet_type = DISCARD_PACKET; */
- return;
+ break;
+ default:
+ data += 1;
+ len -= 1;
+ gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
+ data, len);
+ break;
}
- data += 1;
- len -= 1;
- memcpy(&sd->tmpbuf[sd->buflen], data, len);
- sd->buflen += len;
}
static void setbrightness(struct gspca_dev *gspca_dev)
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x041e, 0x401d), DVNM("Creative Webcam NX ULTRA")},
- {USB_DEVICE(0x0733, 0x0430), DVNM("Intel PC Camera Pro")},
+ {USB_DEVICE(0x041e, 0x401d), .driver_info = Nxultra},
+ {USB_DEVICE(0x0733, 0x0430), .driver_info = IntelPCCameraPro},
+/*fixme: may be UsbGrabberPV321 BRIDGE_SPCA506 SENSOR_SAA7113 */
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("GSPCA/SPCA506 USB Camera Driver");
MODULE_LICENSE("GPL");
struct sd {
struct gspca_dev gspca_dev; /* !! must be the first item */
- int buflen;
- __u8 tmpbuf[640 * 480 * 3]; /* YYUV per line */
- __u8 tmpbuf2[640 * 480 * 2]; /* YUYV */
-
unsigned char brightness;
unsigned char contrast;
unsigned char colors;
};
static struct v4l2_pix_format vga_mode[] = {
- {160, 120, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 160 * 2,
- .sizeimage = 160 * 120 * 2,
+ {160, 120, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
+ .bytesperline = 160 * 3,
+ .sizeimage = 160 * 120 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 5},
- {176, 144, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 176 * 2,
- .sizeimage = 176 * 144 * 2,
+ {176, 144, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
+ .bytesperline = 176 * 3,
+ .sizeimage = 176 * 144 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 4},
- {320, 240, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 320 * 2,
- .sizeimage = 320 * 240 * 2,
+ {320, 240, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
+ .bytesperline = 320 * 3,
+ .sizeimage = 320 * 240 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 2},
- {352, 288, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 352 * 2,
- .sizeimage = 352 * 288 * 2,
+ {352, 288, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
+ .bytesperline = 352 * 3,
+ .sizeimage = 352 * 288 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 1},
- {640, 480, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 640 * 2,
- .sizeimage = 640 * 480 * 2,
+ {640, 480, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
+ .bytesperline = 640 * 3,
+ .sizeimage = 640 * 480 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 0},
};
struct cam *cam;
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x01;
cam->cam_mode = vga_mode;
cam->nmodes = sizeof vga_mode / sizeof vga_mode[0];
{
}
-/* convert YYUV per line to YUYV (YUV 4:2:2) */
-static void yyuv_decode(unsigned char *out,
- unsigned char *in,
- int width,
- int height)
-{
- unsigned char *Ui, *Vi, *yi, *yi1;
- unsigned char *out1;
- int i, j;
-
- yi = in;
- for (i = height / 2; --i >= 0; ) {
- out1 = out + width * 2; /* next line */
- yi1 = yi + width;
- Ui = yi1 + width;
- Vi = Ui + width / 2;
- for (j = width / 2; --j >= 0; ) {
- *out++ = 128 + *yi++;
- *out++ = 128 + *Ui;
- *out++ = 128 + *yi++;
- *out++ = 128 + *Vi;
-
- *out1++ = 128 + *yi1++;
- *out1++ = 128 + *Ui++;
- *out1++ = 128 + *yi1++;
- *out1++ = 128 + *Vi++;
- }
- yi += width * 2;
- out = out1;
- }
-}
-
static void sd_pkt_scan(struct gspca_dev *gspca_dev,
struct gspca_frame *frame, /* target */
__u8 *data, /* isoc packet */
int len) /* iso packet length */
{
- struct sd *sd = (struct sd *) gspca_dev;
-
switch (data[0]) {
case 0: /* start of frame */
- if (gspca_dev->last_packet_type == FIRST_PACKET) {
- yyuv_decode(sd->tmpbuf2, sd->tmpbuf,
- gspca_dev->width,
- gspca_dev->height);
- frame = gspca_frame_add(gspca_dev,
- LAST_PACKET,
- frame,
- sd->tmpbuf2,
- gspca_dev->width
- * gspca_dev->height
- * 2);
- }
- gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
- data, 0);
+ frame = gspca_frame_add(gspca_dev, LAST_PACKET, frame,
+ data, 0);
data += SPCA50X_OFFSET_DATA;
len -= SPCA50X_OFFSET_DATA;
- if (len > 0)
- memcpy(sd->tmpbuf, data, len);
- else
- len = 0;
- sd->buflen = len;
- return;
+ gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
+ data, len);
+ break;
case 0xff: /* drop */
/* gspca_dev->last_packet_type = DISCARD_PACKET; */
- return;
+ break;
+ default:
+ data += 1;
+ len -= 1;
+ gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
+ data, len);
+ break;
}
- data += 1;
- len -= 1;
- memcpy(&sd->tmpbuf[sd->buflen], data, len);
- sd->buflen += len;
}
static void setbrightness(struct gspca_dev *gspca_dev)
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x06e1, 0xa190), DVNM("ADS Instant VCD")},
-/* {USB_DEVICE(0x0733, 0x0430), DVNM("UsbGrabber PV321c")}, */
- {USB_DEVICE(0x0734, 0x043b), DVNM("3DeMon USB Capture aka")},
- {USB_DEVICE(0x99fa, 0x8988), DVNM("Grandtec V.cap")},
+ {USB_DEVICE(0x06e1, 0xa190)},
+/*fixme: may be IntelPCCameraPro BRIDGE_SPCA505
+ {USB_DEVICE(0x0733, 0x0430)}, */
+ {USB_DEVICE(0x0734, 0x043b)},
+ {USB_DEVICE(0x99fa, 0x8988)},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("GSPCA/SPCA508 USB Camera Driver");
MODULE_LICENSE("GPL");
struct sd {
struct gspca_dev gspca_dev; /* !! must be the first item */
- int buflen;
- unsigned char tmpbuf[352 * 288 * 3 / 2]; /* YUVY per line */
- unsigned char tmpbuf2[352 * 288 * 2]; /* YUYV */
-
unsigned char brightness;
char subtype;
static struct v4l2_pix_format sif_mode[] = {
{160, 120, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 160 * 2,
- .sizeimage = 160 * 120 * 2,
+ .bytesperline = 160 * 3,
+ .sizeimage = 160 * 120 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 3},
{176, 144, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 176 * 2,
- .sizeimage = 176 * 144 * 2,
+ .bytesperline = 176 * 3,
+ .sizeimage = 176 * 144 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 2},
{320, 240, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 320 * 2,
- .sizeimage = 320 * 240 * 2,
+ .bytesperline = 320 * 3,
+ .sizeimage = 320 * 240 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 1},
{352, 288, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
- .bytesperline = 352 * 2,
- .sizeimage = 352 * 288 * 2,
+ .bytesperline = 352 * 3,
+ .sizeimage = 352 * 288 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 0},
};
{
struct sd *sd = (struct sd *) gspca_dev;
struct cam *cam;
- __u16 product;
int data1, data2;
- product = id->idProduct;
- switch (id->idVendor) {
- case 0x0130: /* Clone webcam */
-/* switch (product) { */
-/* case 0x0130: */
- sd->subtype = HamaUSBSightcam; /* same as Hama 0010 */
-/* break; */
-/* } */
- break;
- case 0x041e: /* Creative cameras */
-/* switch (product) { */
-/* case 0x4018: */
- sd->subtype = CreativeVista;
-/* break; */
-/* } */
- break;
- case 0x0461: /* MicroInnovation */
-/* switch (product) { */
-/* case 0x0815: */
- sd->subtype = MicroInnovationIC200;
-/* break; */
-/* } */
- break;
- case 0x0733: /* Rebadged ViewQuest (Intel) and ViewQuest cameras */
-/* switch (product) { */
-/* case 0x110: */
- sd->subtype = ViewQuestVQ110;
-/* break; */
-/* } */
- break;
- case 0x0af9: /* Hama cameras */
- switch (product) {
- case 0x0010:
- sd->subtype = HamaUSBSightcam;
- break;
- case 0x0011:
- sd->subtype = HamaUSBSightcam2;
- break;
- }
- break;
- case 0x8086: /* Intel */
-/* switch (product) { */
-/* case 0x0110: */
- sd->subtype = IntelEasyPCCamera;
-/* break; */
-/* } */
- break;
- }
-
/* Read from global register the USB product and vendor IDs, just to
* prove that we can communicate with the device. This works, which
* confirms at we are communicating properly and that the device
PDEBUG(D_PROBE, "Window 1 average luminance: %d", data1);
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x01;
cam->cam_mode = sif_mode;
cam->nmodes = ARRAY_SIZE(sif_mode);
+
+ sd->subtype = id->driver_info;
sd->brightness = BRIGHTNESS_DEF;
switch (sd->subtype) {
{
}
-/* convert YUVY per line to YUYV (YUV 4:2:2) */
-static void yuvy_decode(unsigned char *out,
- unsigned char *in,
- int width,
- int height)
-{
- unsigned char *Ui, *Vi, *yi, *yi1;
- unsigned char *out1;
- int i, j;
-
- yi = in;
- for (i = height / 2; --i >= 0; ) {
- out1 = out + width * 2; /* next line */
- Ui = yi + width;
- Vi = Ui + width / 2;
- yi1 = Vi + width / 2;
- for (j = width / 2; --j >= 0; ) {
- *out++ = 128 + *yi++;
- *out++ = 128 + *Ui;
- *out++ = 128 + *yi++;
- *out++ = 128 + *Vi;
-
- *out1++ = 128 + *yi1++;
- *out1++ = 128 + *Ui++;
- *out1++ = 128 + *yi1++;
- *out1++ = 128 + *Vi++;
- }
- yi += width * 2;
- out = out1;
- }
-}
-
static void sd_pkt_scan(struct gspca_dev *gspca_dev,
struct gspca_frame *frame, /* target */
__u8 *data, /* isoc packet */
int len) /* iso packet length */
{
- struct sd *sd = (struct sd *) gspca_dev;
-
switch (data[0]) {
case 0: /* start of frame */
- if (gspca_dev->last_packet_type == FIRST_PACKET) {
- yuvy_decode(sd->tmpbuf2, sd->tmpbuf,
- gspca_dev->width,
- gspca_dev->height);
- frame = gspca_frame_add(gspca_dev,
- LAST_PACKET,
- frame,
- sd->tmpbuf2,
- gspca_dev->width
- * gspca_dev->height
- * 2);
- }
- gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
- data, 0);
+ frame = gspca_frame_add(gspca_dev, LAST_PACKET, frame,
+ data, 0);
data += SPCA508_OFFSET_DATA;
len -= SPCA508_OFFSET_DATA;
- if (len > 0)
- memcpy(sd->tmpbuf, data, len);
- else
- len = 0;
- sd->buflen = len;
- return;
+ gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
+ data, len);
+ break;
case 0xff: /* drop */
/* gspca_dev->last_packet_type = DISCARD_PACKET; */
- return;
+ break;
+ default:
+ data += 1;
+ len -= 1;
+ gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
+ data, len);
+ break;
}
- data += 1;
- len -= 1;
- memcpy(&sd->tmpbuf[sd->buflen], data, len);
- sd->buflen += len;
}
static void setbrightness(struct gspca_dev *gspca_dev)
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x0130, 0x0130), DVNM("Clone Digital Webcam 11043")},
- {USB_DEVICE(0x041e, 0x4018), DVNM("Creative Webcam Vista (PD1100)")},
- {USB_DEVICE(0x0461, 0x0815), DVNM("Micro Innovation IC200")},
- {USB_DEVICE(0x0733, 0x0110), DVNM("ViewQuest VQ110")},
- {USB_DEVICE(0x0af9, 0x0010), DVNM("Hama USB Sightcam 100")},
- {USB_DEVICE(0x0af9, 0x0011), DVNM("Hama USB Sightcam 100")},
- {USB_DEVICE(0x8086, 0x0110), DVNM("Intel Easy PC Camera")},
+ {USB_DEVICE(0x0130, 0x0130), .driver_info = HamaUSBSightcam},
+ {USB_DEVICE(0x041e, 0x4018), .driver_info = CreativeVista},
+ {USB_DEVICE(0x0461, 0x0815), .driver_info = MicroInnovationIC200},
+ {USB_DEVICE(0x0733, 0x0110), .driver_info = ViewQuestVQ110},
+ {USB_DEVICE(0x0af9, 0x0010), .driver_info = HamaUSBSightcam},
+ {USB_DEVICE(0x0af9, 0x0011), .driver_info = HamaUSBSightcam2},
+ {USB_DEVICE(0x8086, 0x0110), .driver_info = IntelEasyPCCamera},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("GSPCA/SPCA561 USB Camera Driver");
MODULE_LICENSE("GPL");
PDEBUG(D_PROBE, "Bad vendor / product from device");
return -EINVAL;
}
- switch (product) {
- case 0x0928:
- case 0x0929:
- case 0x092a:
- case 0x092b:
- case 0x092c:
- case 0x092d:
- case 0x092e:
- case 0x092f:
- case 0x403b:
- sd->chip_revision = Rev012A;
- break;
- default:
-/* case 0x0561:
- case 0x0815: * ?? in spca508.c
- case 0x401a:
- case 0x7004:
- case 0x7e50:
- case 0xa001:
- case 0xcdee: */
- sd->chip_revision = Rev072A;
- break;
- }
+
cam = &gspca_dev->cam;
cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x01;
gspca_dev->nbalt = 7 + 1; /* choose alternate 7 first */
cam->cam_mode = sif_mode;
cam->nmodes = sizeof sif_mode / sizeof sif_mode[0];
+
+ sd->chip_revision = id->driver_info;
sd->brightness = sd_ctrls[SD_BRIGHTNESS].qctrl.default_value;
sd->contrast = sd_ctrls[SD_CONTRAST].qctrl.default_value;
sd->autogain = sd_ctrls[SD_AUTOGAIN].qctrl.default_value;
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x041e, 0x401a), DVNM("Creative Webcam Vista (PD1100)")},
- {USB_DEVICE(0x041e, 0x403b), DVNM("Creative Webcam Vista (VF0010)")},
- {USB_DEVICE(0x0458, 0x7004), DVNM("Genius VideoCAM Express V2")},
- {USB_DEVICE(0x046d, 0x0928), DVNM("Logitech QC Express Etch2")},
- {USB_DEVICE(0x046d, 0x0929), DVNM("Labtec Webcam Elch2")},
- {USB_DEVICE(0x046d, 0x092a), DVNM("Logitech QC for Notebook")},
- {USB_DEVICE(0x046d, 0x092b), DVNM("Labtec Webcam Plus")},
- {USB_DEVICE(0x046d, 0x092c), DVNM("Logitech QC chat Elch2")},
- {USB_DEVICE(0x046d, 0x092d), DVNM("Logitech QC Elch2")},
- {USB_DEVICE(0x046d, 0x092e), DVNM("Logitech QC Elch2")},
- {USB_DEVICE(0x046d, 0x092f), DVNM("Logitech QC Elch2")},
- {USB_DEVICE(0x04fc, 0x0561), DVNM("Flexcam 100")},
- {USB_DEVICE(0x060b, 0xa001), DVNM("Maxell Compact Pc PM3")},
- {USB_DEVICE(0x10fd, 0x7e50), DVNM("FlyCam Usb 100")},
- {USB_DEVICE(0xabcd, 0xcdee), DVNM("Petcam")},
+ {USB_DEVICE(0x041e, 0x401a), .driver_info = Rev072A},
+ {USB_DEVICE(0x041e, 0x403b), .driver_info = Rev012A},
+ {USB_DEVICE(0x0458, 0x7004), .driver_info = Rev072A},
+ {USB_DEVICE(0x046d, 0x0928), .driver_info = Rev012A},
+ {USB_DEVICE(0x046d, 0x0929), .driver_info = Rev012A},
+ {USB_DEVICE(0x046d, 0x092a), .driver_info = Rev012A},
+ {USB_DEVICE(0x046d, 0x092b), .driver_info = Rev012A},
+ {USB_DEVICE(0x046d, 0x092c), .driver_info = Rev012A},
+ {USB_DEVICE(0x046d, 0x092d), .driver_info = Rev012A},
+ {USB_DEVICE(0x046d, 0x092e), .driver_info = Rev012A},
+ {USB_DEVICE(0x046d, 0x092f), .driver_info = Rev012A},
+ {USB_DEVICE(0x04fc, 0x0561), .driver_info = Rev072A},
+ {USB_DEVICE(0x060b, 0xa001), .driver_info = Rev072A},
+ {USB_DEVICE(0x10fd, 0x7e50), .driver_info = Rev072A},
+ {USB_DEVICE(0xabcd, 0xcdee), .driver_info = Rev072A},
{}
};
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
#include "jpeg.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Jean-Francois Moine <http://moinejf.free.fr>");
MODULE_DESCRIPTION("Syntek DV4000 (STK014) USB Camera Driver");
MODULE_LICENSE("GPL");
struct sd *sd = (struct sd *) gspca_dev;
struct cam *cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x02;
gspca_dev->cam.cam_mode = vga_mode;
gspca_dev->cam.nmodes = ARRAY_SIZE(vga_mode);
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x05e1, 0x0893), DVNM("Syntek DV4000")},
+ {USB_DEVICE(0x05e1, 0x0893)},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- info("v%s registered", version);
+ info("registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
#include "jpeg.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 8)
-static const char version[] = "2.1.8";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("GSPCA/SPCA5xx USB Camera Driver");
MODULE_LICENSE("GPL");
struct sd *sd = (struct sd *) gspca_dev;
struct usb_device *dev = gspca_dev->dev;
struct cam *cam;
- __u16 vendor;
- __u16 product;
- __u8 fw;
-
- vendor = id->idVendor;
- product = id->idProduct;
- switch (vendor) {
- case 0x041e: /* Creative cameras */
-/* switch (product) { */
-/* case 0x400b: */
-/* case 0x4012: */
-/* case 0x4013: */
-/* sd->bridge = BRIDGE_SPCA504C; */
-/* break; */
-/* } */
- break;
- case 0x0458: /* Genius KYE cameras */
-/* switch (product) { */
-/* case 0x7006: */
- sd->bridge = BRIDGE_SPCA504B;
-/* break; */
-/* } */
- break;
- case 0x0461: /* MicroInnovation */
-/* switch (product) { */
-/* case 0x0821: */
- sd->bridge = BRIDGE_SPCA533;
-/* break; */
-/* } */
- break;
- case 0x046d: /* Logitech Labtec */
- switch (product) {
- case 0x0905:
- sd->subtype = LogitechClickSmart820;
- sd->bridge = BRIDGE_SPCA533;
- break;
- case 0x0960:
- sd->subtype = LogitechClickSmart420;
- sd->bridge = BRIDGE_SPCA504C;
- break;
- }
- break;
- case 0x0471: /* Philips */
-/* switch (product) { */
-/* case 0x0322: */
- sd->bridge = BRIDGE_SPCA504B;
-/* break; */
-/* } */
- break;
- case 0x04a5: /* Benq */
- switch (product) {
- case 0x3003:
- sd->bridge = BRIDGE_SPCA504B;
- break;
- case 0x3008:
- case 0x300a:
- sd->bridge = BRIDGE_SPCA533;
- break;
- }
- break;
- case 0x04f1: /* JVC */
-/* switch (product) { */
-/* case 0x1001: */
- sd->bridge = BRIDGE_SPCA504B;
-/* break; */
-/* } */
- break;
- case 0x04fc: /* SunPlus */
- switch (product) {
- case 0x500c:
- sd->bridge = BRIDGE_SPCA504B;
- break;
- case 0x504a:
+
+ cam = &gspca_dev->cam;
+ cam->epaddr = 0x01;
+
+ sd->bridge = id->driver_info >> 8;
+ sd->subtype = id->driver_info;
+
+ if (sd->subtype == AiptekMiniPenCam13) {
/* try to get the firmware as some cam answer 2.0.1.2.2
* and should be a spca504b then overwrite that setting */
- reg_r(dev, 0x20, 0, gspca_dev->usb_buf, 1);
- fw = gspca_dev->usb_buf[0];
- if (fw == 1) {
- sd->subtype = AiptekMiniPenCam13;
- sd->bridge = BRIDGE_SPCA504;
- } else if (fw == 2) {
- sd->bridge = BRIDGE_SPCA504B;
- } else
- return -ENODEV;
- break;
- case 0x504b:
- sd->bridge = BRIDGE_SPCA504B;
- break;
- case 0x5330:
- sd->bridge = BRIDGE_SPCA533;
- break;
- case 0x5360:
- sd->bridge = BRIDGE_SPCA536;
- break;
- case 0xffff:
- sd->bridge = BRIDGE_SPCA504B;
- break;
- }
- break;
- case 0x052b: /* ?? Megapix */
-/* switch (product) { */
-/* case 0x1513: */
- sd->subtype = MegapixV4;
- sd->bridge = BRIDGE_SPCA533;
-/* break; */
-/* } */
- break;
- case 0x0546: /* Polaroid */
- switch (product) {
- case 0x3155:
- sd->bridge = BRIDGE_SPCA533;
- break;
- case 0x3191:
- case 0x3273:
- sd->bridge = BRIDGE_SPCA504B;
- break;
- }
- break;
- case 0x055f: /* Mustek cameras */
- switch (product) {
- case 0xc211:
- sd->bridge = BRIDGE_SPCA536;
- break;
- case 0xc230:
- case 0xc232:
- sd->bridge = BRIDGE_SPCA533;
- break;
- case 0xc360:
- sd->bridge = BRIDGE_SPCA536;
- break;
- case 0xc420:
- sd->bridge = BRIDGE_SPCA504;
- break;
- case 0xc430:
- case 0xc440:
- sd->bridge = BRIDGE_SPCA533;
- break;
- case 0xc520:
- sd->bridge = BRIDGE_SPCA504;
- break;
- case 0xc530:
- case 0xc540:
- case 0xc630:
- case 0xc650:
- sd->bridge = BRIDGE_SPCA533;
- break;
- }
- break;
- case 0x05da: /* Digital Dream cameras */
-/* switch (product) { */
-/* case 0x1018: */
+ reg_r(dev, 0x20, 0, gspca_dev->usb_buf, 1);
+ switch (gspca_dev->usb_buf[0]) {
+ case 1:
+ break; /* (right bridge/subtype) */
+ case 2:
sd->bridge = BRIDGE_SPCA504B;
-/* break; */
-/* } */
- break;
- case 0x06d6: /* Trust */
-/* switch (product) { */
-/* case 0x0031: */
- sd->bridge = BRIDGE_SPCA533; /* SPCA533A */
-/* break; */
-/* } */
- break;
- case 0x0733: /* Rebadged ViewQuest (Intel) and ViewQuest cameras */
- switch (product) {
- case 0x1311:
- case 0x1314:
- case 0x2211:
- case 0x2221:
- sd->bridge = BRIDGE_SPCA533;
- break;
- case 0x3261:
- case 0x3281:
- sd->bridge = BRIDGE_SPCA536;
- break;
- }
- break;
- case 0x08ca: /* Aiptek */
- switch (product) {
- case 0x0104:
- case 0x0106:
- sd->bridge = BRIDGE_SPCA533;
- break;
- case 0x2008:
- sd->bridge = BRIDGE_SPCA504B;
- break;
- case 0x2010:
- sd->bridge = BRIDGE_SPCA533;
- break;
- case 0x2016:
- case 0x2018:
- sd->bridge = BRIDGE_SPCA504B;
- break;
- case 0x2020:
- case 0x2022:
- sd->bridge = BRIDGE_SPCA533;
- break;
- case 0x2024:
- sd->bridge = BRIDGE_SPCA536;
- break;
- case 0x2028:
- sd->bridge = BRIDGE_SPCA533;
- break;
- case 0x2040:
- case 0x2042:
- case 0x2050:
- case 0x2060:
- sd->bridge = BRIDGE_SPCA536;
+ sd->subtype = 0;
break;
+ default:
+ return -ENODEV;
}
- break;
- case 0x0d64: /* SunPlus */
-/* switch (product) { */
-/* case 0x0303: */
- sd->bridge = BRIDGE_SPCA536;
-/* break; */
-/* } */
- break;
}
- cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
- cam->epaddr = 0x01;
-
switch (sd->bridge) {
default:
/* case BRIDGE_SPCA504B: */
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
+#define BS(bridge, subtype) \
+ .driver_info = (BRIDGE_ ## bridge << 8) \
+ | (subtype)
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x041e, 0x400b), DVNM("Creative PC-CAM 600")},
- {USB_DEVICE(0x041e, 0x4012), DVNM("PC-Cam350")},
- {USB_DEVICE(0x041e, 0x4013), DVNM("Creative Pccam750")},
- {USB_DEVICE(0x0458, 0x7006), DVNM("Genius Dsc 1.3 Smart")},
- {USB_DEVICE(0x0461, 0x0821), DVNM("Fujifilm MV-1")},
- {USB_DEVICE(0x046d, 0x0905), DVNM("Logitech ClickSmart 820")},
- {USB_DEVICE(0x046d, 0x0960), DVNM("Logitech ClickSmart 420")},
- {USB_DEVICE(0x0471, 0x0322), DVNM("Philips DMVC1300K")},
- {USB_DEVICE(0x04a5, 0x3003), DVNM("Benq DC 1300")},
- {USB_DEVICE(0x04a5, 0x3008), DVNM("Benq DC 1500")},
- {USB_DEVICE(0x04a5, 0x300a), DVNM("Benq DC3410")},
- {USB_DEVICE(0x04f1, 0x1001), DVNM("JVC GC A50")},
- {USB_DEVICE(0x04fc, 0x500c), DVNM("Sunplus CA500C")},
- {USB_DEVICE(0x04fc, 0x504a), DVNM("Aiptek Mini PenCam 1.3")},
- {USB_DEVICE(0x04fc, 0x504b), DVNM("Maxell MaxPocket LE 1.3")},
- {USB_DEVICE(0x04fc, 0x5330), DVNM("Digitrex 2110")},
- {USB_DEVICE(0x04fc, 0x5360), DVNM("Sunplus Generic")},
- {USB_DEVICE(0x04fc, 0xffff), DVNM("Pure DigitalDakota")},
- {USB_DEVICE(0x052b, 0x1513), DVNM("Megapix V4")},
- {USB_DEVICE(0x0546, 0x3155), DVNM("Polaroid PDC3070")},
- {USB_DEVICE(0x0546, 0x3191), DVNM("Polaroid Ion 80")},
- {USB_DEVICE(0x0546, 0x3273), DVNM("Polaroid PDC2030")},
- {USB_DEVICE(0x055f, 0xc211), DVNM("Kowa Bs888e Microcamera")},
- {USB_DEVICE(0x055f, 0xc230), DVNM("Mustek Digicam 330K")},
- {USB_DEVICE(0x055f, 0xc232), DVNM("Mustek MDC3500")},
- {USB_DEVICE(0x055f, 0xc360), DVNM("Mustek DV4000 Mpeg4 ")},
- {USB_DEVICE(0x055f, 0xc420), DVNM("Mustek gSmart Mini 2")},
- {USB_DEVICE(0x055f, 0xc430), DVNM("Mustek Gsmart LCD 2")},
- {USB_DEVICE(0x055f, 0xc440), DVNM("Mustek DV 3000")},
- {USB_DEVICE(0x055f, 0xc520), DVNM("Mustek gSmart Mini 3")},
- {USB_DEVICE(0x055f, 0xc530), DVNM("Mustek Gsmart LCD 3")},
- {USB_DEVICE(0x055f, 0xc540), DVNM("Gsmart D30")},
- {USB_DEVICE(0x055f, 0xc630), DVNM("Mustek MDC4000")},
- {USB_DEVICE(0x055f, 0xc650), DVNM("Mustek MDC5500Z")},
- {USB_DEVICE(0x05da, 0x1018), DVNM("Digital Dream Enigma 1.3")},
- {USB_DEVICE(0x06d6, 0x0031), DVNM("Trust 610 LCD PowerC@m Zoom")},
- {USB_DEVICE(0x0733, 0x1311), DVNM("Digital Dream Epsilon 1.3")},
- {USB_DEVICE(0x0733, 0x1314), DVNM("Mercury 2.1MEG Deluxe Classic Cam")},
- {USB_DEVICE(0x0733, 0x2211), DVNM("Jenoptik jdc 21 LCD")},
- {USB_DEVICE(0x0733, 0x2221), DVNM("Mercury Digital Pro 3.1p")},
- {USB_DEVICE(0x0733, 0x3261), DVNM("Concord 3045 spca536a")},
- {USB_DEVICE(0x0733, 0x3281), DVNM("Cyberpix S550V")},
- {USB_DEVICE(0x08ca, 0x0104), DVNM("Aiptek PocketDVII 1.3")},
- {USB_DEVICE(0x08ca, 0x0106), DVNM("Aiptek Pocket DV3100+")},
- {USB_DEVICE(0x08ca, 0x2008), DVNM("Aiptek Mini PenCam 2 M")},
- {USB_DEVICE(0x08ca, 0x2010), DVNM("Aiptek PocketCam 3M")},
- {USB_DEVICE(0x08ca, 0x2016), DVNM("Aiptek PocketCam 2 Mega")},
- {USB_DEVICE(0x08ca, 0x2018), DVNM("Aiptek Pencam SD 2M")},
- {USB_DEVICE(0x08ca, 0x2020), DVNM("Aiptek Slim 3000F")},
- {USB_DEVICE(0x08ca, 0x2022), DVNM("Aiptek Slim 3200")},
- {USB_DEVICE(0x08ca, 0x2024), DVNM("Aiptek DV3500 Mpeg4 ")},
- {USB_DEVICE(0x08ca, 0x2028), DVNM("Aiptek PocketCam4M")},
- {USB_DEVICE(0x08ca, 0x2040), DVNM("Aiptek PocketDV4100M")},
- {USB_DEVICE(0x08ca, 0x2042), DVNM("Aiptek PocketDV5100")},
- {USB_DEVICE(0x08ca, 0x2050), DVNM("Medion MD 41437")},
- {USB_DEVICE(0x08ca, 0x2060), DVNM("Aiptek PocketDV5300")},
- {USB_DEVICE(0x0d64, 0x0303), DVNM("Sunplus FashionCam DXG")},
+ {USB_DEVICE(0x041e, 0x400b), BS(SPCA504C, 0)},
+ {USB_DEVICE(0x041e, 0x4012), BS(SPCA504C, 0)},
+ {USB_DEVICE(0x041e, 0x4013), BS(SPCA504C, 0)},
+ {USB_DEVICE(0x0458, 0x7006), BS(SPCA504B, 0)},
+ {USB_DEVICE(0x0461, 0x0821), BS(SPCA533, 0)},
+ {USB_DEVICE(0x046d, 0x0905), BS(SPCA533, LogitechClickSmart820)},
+ {USB_DEVICE(0x046d, 0x0960), BS(SPCA504C, LogitechClickSmart420)},
+ {USB_DEVICE(0x0471, 0x0322), BS(SPCA504B, 0)},
+ {USB_DEVICE(0x04a5, 0x3003), BS(SPCA504B, 0)},
+ {USB_DEVICE(0x04a5, 0x3008), BS(SPCA533, 0)},
+ {USB_DEVICE(0x04a5, 0x300a), BS(SPCA533, 0)},
+ {USB_DEVICE(0x04f1, 0x1001), BS(SPCA504B, 0)},
+ {USB_DEVICE(0x04fc, 0x500c), BS(SPCA504B, 0)},
+ {USB_DEVICE(0x04fc, 0x504a), BS(SPCA504, AiptekMiniPenCam13)},
+ {USB_DEVICE(0x04fc, 0x504b), BS(SPCA504B, 0)},
+ {USB_DEVICE(0x04fc, 0x5330), BS(SPCA533, 0)},
+ {USB_DEVICE(0x04fc, 0x5360), BS(SPCA536, 0)},
+ {USB_DEVICE(0x04fc, 0xffff), BS(SPCA504B, 0)},
+ {USB_DEVICE(0x052b, 0x1513), BS(SPCA533, MegapixV4)},
+ {USB_DEVICE(0x0546, 0x3155), BS(SPCA533, 0)},
+ {USB_DEVICE(0x0546, 0x3191), BS(SPCA504B, 0)},
+ {USB_DEVICE(0x0546, 0x3273), BS(SPCA504B, 0)},
+ {USB_DEVICE(0x055f, 0xc211), BS(SPCA536, 0)},
+ {USB_DEVICE(0x055f, 0xc230), BS(SPCA533, 0)},
+ {USB_DEVICE(0x055f, 0xc232), BS(SPCA533, 0)},
+ {USB_DEVICE(0x055f, 0xc360), BS(SPCA536, 0)},
+ {USB_DEVICE(0x055f, 0xc420), BS(SPCA504, 0)},
+ {USB_DEVICE(0x055f, 0xc430), BS(SPCA533, 0)},
+ {USB_DEVICE(0x055f, 0xc440), BS(SPCA533, 0)},
+ {USB_DEVICE(0x055f, 0xc520), BS(SPCA504, 0)},
+ {USB_DEVICE(0x055f, 0xc530), BS(SPCA533, 0)},
+ {USB_DEVICE(0x055f, 0xc540), BS(SPCA533, 0)},
+ {USB_DEVICE(0x055f, 0xc630), BS(SPCA533, 0)},
+ {USB_DEVICE(0x055f, 0xc650), BS(SPCA533, 0)},
+ {USB_DEVICE(0x05da, 0x1018), BS(SPCA504B, 0)},
+ {USB_DEVICE(0x06d6, 0x0031), BS(SPCA533, 0)},
+ {USB_DEVICE(0x0733, 0x1311), BS(SPCA533, 0)},
+ {USB_DEVICE(0x0733, 0x1314), BS(SPCA533, 0)},
+ {USB_DEVICE(0x0733, 0x2211), BS(SPCA533, 0)},
+ {USB_DEVICE(0x0733, 0x2221), BS(SPCA533, 0)},
+ {USB_DEVICE(0x0733, 0x3261), BS(SPCA536, 0)},
+ {USB_DEVICE(0x0733, 0x3281), BS(SPCA536, 0)},
+ {USB_DEVICE(0x08ca, 0x0104), BS(SPCA533, 0)},
+ {USB_DEVICE(0x08ca, 0x0106), BS(SPCA533, 0)},
+ {USB_DEVICE(0x08ca, 0x2008), BS(SPCA504B, 0)},
+ {USB_DEVICE(0x08ca, 0x2010), BS(SPCA533, 0)},
+ {USB_DEVICE(0x08ca, 0x2016), BS(SPCA504B, 0)},
+ {USB_DEVICE(0x08ca, 0x2018), BS(SPCA504B, 0)},
+ {USB_DEVICE(0x08ca, 0x2020), BS(SPCA533, 0)},
+ {USB_DEVICE(0x08ca, 0x2022), BS(SPCA533, 0)},
+ {USB_DEVICE(0x08ca, 0x2024), BS(SPCA536, 0)},
+ {USB_DEVICE(0x08ca, 0x2028), BS(SPCA533, 0)},
+ {USB_DEVICE(0x08ca, 0x2040), BS(SPCA536, 0)},
+ {USB_DEVICE(0x08ca, 0x2042), BS(SPCA536, 0)},
+ {USB_DEVICE(0x08ca, 0x2050), BS(SPCA536, 0)},
+ {USB_DEVICE(0x08ca, 0x2060), BS(SPCA536, 0)},
+ {USB_DEVICE(0x0d64, 0x0303), BS(SPCA536, 0)},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
/*
- *Notes: * t613 + tas5130A
- * * Focus to light do not balance well as in win.
- * Quality in win is not good, but its kinda better.
- * * Fix some "extraneous bytes", most of apps will show the image anyway
- * * Gamma table, is there, but its really doing something?
- * * 7~8 Fps, its ok, max on win its 10.
- * Costantino Leandro
- *
* V4L2 by Jean-Francois Moine <http://moinejf.free.fr>
*
* This program is free software; you can redistribute it and/or modify
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ *Notes: * t613 + tas5130A
+ * * Focus to light do not balance well as in win.
+ * Quality in win is not good, but its kinda better.
+ * * Fix some "extraneous bytes", most of apps will show the image anyway
+ * * Gamma table, is there, but its really doing something?
+ * * 7~8 Fps, its ok, max on win its 10.
+ * Costantino Leandro
*/
#define MODULE_NAME "t613"
+
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
#define MAX_GAMMA 0x10 /* 0 to 15 */
-/* From LUVCVIEW */
#define V4L2_CID_EFFECTS (V4L2_CID_PRIVATE_BASE + 3)
MODULE_AUTHOR("Leandro Costantino <le_costantino@pixartargentina.com.ar>");
struct cam *cam;
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x01;
cam->cam_mode = vga_mode_t16;
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x17a1, 0x0128), DVNM("XPX Webcam")},
+ {USB_DEVICE(0x17a1, 0x0128)},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("TV8532 USB Camera Driver");
MODULE_LICENSE("GPL");
tv_8532WriteEEprom(gspca_dev);
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 1;
cam->cam_mode = sif_mode;
cam->nmodes = sizeof sif_mode / sizeof sif_mode[0];
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x046d, 0x0920), DVNM("QC Express")},
- {USB_DEVICE(0x046d, 0x0921), DVNM("Labtec Webcam")},
- {USB_DEVICE(0x0545, 0x808b), DVNM("Veo Stingray")},
- {USB_DEVICE(0x0545, 0x8333), DVNM("Veo Stingray")},
- {USB_DEVICE(0x0923, 0x010f), DVNM("ICM532 cams")},
+ {USB_DEVICE(0x046d, 0x0920)},
+ {USB_DEVICE(0x046d, 0x0921)},
+ {USB_DEVICE(0x0545, 0x808b)},
+ {USB_DEVICE(0x0545, 0x8333)},
+ {USB_DEVICE(0x0923, 0x010f)},
{}
};
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("GSPCA/VC032X USB Camera Driver");
MODULE_LICENSE("GPL");
struct usb_device *dev = gspca_dev->dev;
struct cam *cam;
int sensor;
- __u16 product;
-
- product = id->idProduct;
- sd->bridge = BRIDGE_VC0321;
- switch (id->idVendor) {
- case 0x0ac8: /* Vimicro z-star */
- switch (product) {
- case 0x0323:
- sd->bridge = BRIDGE_VC0323;
- break;
- }
- break;
- case 0x17ef: /* Lenovo */
-/* switch (product) { */
-/* case 0x4802: * Lenovo MI1310_SOC */
- sd->bridge = BRIDGE_VC0323;
-/* break; */
-/* } */
- break;
- }
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x02;
+ sd->bridge = id->driver_info;
if (sd->bridge == BRIDGE_VC0321) {
cam->cam_mode = vc0321_mode;
cam->nmodes = ARRAY_SIZE(vc0321_mode);
};
/* -- module initialisation -- */
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x046d, 0x0892), DVNM("Logitech Orbicam")},
- {USB_DEVICE(0x046d, 0x0896), DVNM("Logitech Orbicam")},
- {USB_DEVICE(0x0ac8, 0x0321), DVNM("Vimicro generic vc0321")},
- {USB_DEVICE(0x0ac8, 0x0323), DVNM("Vimicro Vc0323")},
- {USB_DEVICE(0x0ac8, 0x0328), DVNM("A4Tech PK-130MG")},
- {USB_DEVICE(0x0ac8, 0xc001), DVNM("Sony embedded vimicro")},
- {USB_DEVICE(0x0ac8, 0xc002), DVNM("Sony embedded vimicro")},
- {USB_DEVICE(0x17ef, 0x4802), DVNM("Lenovo Vc0323+MI1310_SOC")},
+ {USB_DEVICE(0x046d, 0x0892), .driver_info = BRIDGE_VC0321},
+ {USB_DEVICE(0x046d, 0x0896), .driver_info = BRIDGE_VC0321},
+ {USB_DEVICE(0x0ac8, 0x0321), .driver_info = BRIDGE_VC0321},
+ {USB_DEVICE(0x0ac8, 0x0323), .driver_info = BRIDGE_VC0323},
+ {USB_DEVICE(0x0ac8, 0x0328), .driver_info = BRIDGE_VC0321},
+ {USB_DEVICE(0x0ac8, 0xc001), .driver_info = BRIDGE_VC0321},
+ {USB_DEVICE(0x0ac8, 0xc002), .driver_info = BRIDGE_VC0321},
+ {USB_DEVICE(0x17ef, 0x4802), .driver_info = BRIDGE_VC0323},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
#include "gspca.h"
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 7)
-static const char version[] = "2.1.7";
-
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>, "
"Serge A. Suchkov <Serge.A.S@tochka.ru>");
MODULE_DESCRIPTION("GSPCA ZC03xx/VC3xx USB Camera Driver");
__u8 sharpness;
char qindex;
- char sensor; /* Type of image sensor chip */
+ signed char sensor; /* Type of image sensor chip */
/* !! values used in different tables */
#define SENSOR_CS2102 0
#define SENSOR_CS2102K 1
};
static const struct usb_action hdcs2020b_50HZ[] = {
{0xa0, 0x00, ZC3XX_R019_AUTOADJUSTFPS}, /* 00,19,00,cc */
- {0xaa, 0x13, 0x0018}, /* 00,13,18,aa */
- {0xaa, 0x14, 0x0001}, /* 00,14,01,aa */
- {0xaa, 0x0e, 0x0005}, /* 00,0e,05,aa */
- {0xaa, 0x19, 0x001f}, /* 00,19,1f,aa */
+ {0xaa, 0x13, 0x0018}, /* 00,13,18,aa */
+ {0xaa, 0x14, 0x0001}, /* 00,14,01,aa */
+ {0xaa, 0x0e, 0x0005}, /* 00,0e,05,aa */
+ {0xaa, 0x19, 0x001f}, /* 00,19,1f,aa */
{0xa0, 0x00, ZC3XX_R190_EXPOSURELIMITHIGH}, /* 01,90,00,cc */
{0xa0, 0x02, ZC3XX_R191_EXPOSURELIMITMID}, /* 01,91,02,cc */
{0xa0, 0x76, ZC3XX_R192_EXPOSURELIMITLOW}, /* 01,92,76,cc */
};
static const struct usb_action hdcs2020b_60HZ[] = {
{0xa0, 0x00, ZC3XX_R019_AUTOADJUSTFPS}, /* 00,19,00,cc */
- {0xaa, 0x13, 0x0031}, /* 00,13,31,aa */
- {0xaa, 0x14, 0x0001}, /* 00,14,01,aa */
- {0xaa, 0x0e, 0x0004}, /* 00,0e,04,aa */
- {0xaa, 0x19, 0x00cd}, /* 00,19,cd,aa */
+ {0xaa, 0x13, 0x0031}, /* 00,13,31,aa */
+ {0xaa, 0x14, 0x0001}, /* 00,14,01,aa */
+ {0xaa, 0x0e, 0x0004}, /* 00,0e,04,aa */
+ {0xaa, 0x19, 0x00cd}, /* 00,19,cd,aa */
{0xa0, 0x00, ZC3XX_R190_EXPOSURELIMITHIGH}, /* 01,90,00,cc */
{0xa0, 0x02, ZC3XX_R191_EXPOSURELIMITMID}, /* 01,91,02,cc */
{0xa0, 0x62, ZC3XX_R192_EXPOSURELIMITLOW}, /* 01,92,62,cc */
};
static const struct usb_action hdcs2020b_NoFliker[] = {
{0xa0, 0x00, ZC3XX_R019_AUTOADJUSTFPS}, /* 00,19,00,cc */
- {0xaa, 0x13, 0x0010}, /* 00,13,10,aa */
- {0xaa, 0x14, 0x0001}, /* 00,14,01,aa */
- {0xaa, 0x0e, 0x0004}, /* 00,0e,04,aa */
- {0xaa, 0x19, 0x0000}, /* 00,19,00,aa */
+ {0xaa, 0x13, 0x0010}, /* 00,13,10,aa */
+ {0xaa, 0x14, 0x0001}, /* 00,14,01,aa */
+ {0xaa, 0x0e, 0x0004}, /* 00,0e,04,aa */
+ {0xaa, 0x19, 0x0000}, /* 00,19,00,aa */
{0xa0, 0x00, ZC3XX_R190_EXPOSURELIMITHIGH}, /* 01,90,00,cc */
{0xa0, 0x02, ZC3XX_R191_EXPOSURELIMITMID}, /* 01,91,02,cc */
{0xa0, 0x70, ZC3XX_R192_EXPOSURELIMITLOW}, /* 01,92,70,cc */
static const struct usb_action pas106b_Initial[] = { /* 176x144 */
/* JPEG control */
- {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING}, /* ClockSetting */
+ {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING},
/* Sream and Sensor specific */
- {0xa0, 0x0f, ZC3XX_R010_CMOSSENSORSELECT}, /* CMOSSensorSelect */
+ {0xa0, 0x0f, ZC3XX_R010_CMOSSENSORSELECT},
/* Picture size */
- {0xa0, 0x00, ZC3XX_R003_FRAMEWIDTHHIGH}, /* FrameWidthHigh 00 */
- {0xa0, 0xb0, ZC3XX_R004_FRAMEWIDTHLOW}, /* FrameWidthLow B0 */
- {0xa0, 0x00, ZC3XX_R005_FRAMEHEIGHTHIGH}, /* FrameHeightHigh 00 */
- {0xa0, 0x90, ZC3XX_R006_FRAMEHEIGHTLOW}, /* FrameHightLow 90 */
+ {0xa0, 0x00, ZC3XX_R003_FRAMEWIDTHHIGH},
+ {0xa0, 0xb0, ZC3XX_R004_FRAMEWIDTHLOW},
+ {0xa0, 0x00, ZC3XX_R005_FRAMEHEIGHTHIGH},
+ {0xa0, 0x90, ZC3XX_R006_FRAMEHEIGHTLOW},
/* System */
- {0xa0, 0x01, ZC3XX_R001_SYSTEMOPERATING}, /* SystemOperating */
+ {0xa0, 0x01, ZC3XX_R001_SYSTEMOPERATING},
/* Sream and Sensor specific */
- {0xa0, 0x03, ZC3XX_R012_VIDEOCONTROLFUNC}, /* VideoControlFunction */
- {0xa0, 0x01, ZC3XX_R012_VIDEOCONTROLFUNC}, /* VideoControlFunction */
+ {0xa0, 0x03, ZC3XX_R012_VIDEOCONTROLFUNC},
+ {0xa0, 0x01, ZC3XX_R012_VIDEOCONTROLFUNC},
/* Sensor Interface */
- {0xa0, 0x08, ZC3XX_R08D_COMPABILITYMODE}, /* Compatibily Mode */
+ {0xa0, 0x08, ZC3XX_R08D_COMPABILITYMODE},
/* Window inside sensor array */
- {0xa0, 0x03, ZC3XX_R09A_WINXSTARTLOW}, /* WinXStartLow */
- {0xa0, 0x00, ZC3XX_R11A_FIRSTYLOW}, /* FirstYLow */
- {0xa0, 0x03, ZC3XX_R11C_FIRSTXLOW}, /* FirstxLow */
- {0xa0, 0x28, ZC3XX_R09C_WINHEIGHTLOW}, /* WinHeightLow */
- {0xa0, 0x68, ZC3XX_R09E_WINWIDTHLOW}, /* WinWidthLow */
+ {0xa0, 0x03, ZC3XX_R09A_WINXSTARTLOW},
+ {0xa0, 0x00, ZC3XX_R11A_FIRSTYLOW},
+ {0xa0, 0x03, ZC3XX_R11C_FIRSTXLOW},
+ {0xa0, 0x28, ZC3XX_R09C_WINHEIGHTLOW},
+ {0xa0, 0x68, ZC3XX_R09E_WINWIDTHLOW},
/* Init the sensor */
{0xaa, 0x02, 0x0004},
{0xaa, 0x08, 0x0000},
{0xaa, 0x14, 0x0081},
/* Other registors */
- {0xa0, 0x37, ZC3XX_R101_SENSORCORRECTION}, /* SensorCorrection */
+ {0xa0, 0x37, ZC3XX_R101_SENSORCORRECTION},
/* Frame retreiving */
- {0xa0, 0x00, ZC3XX_R019_AUTOADJUSTFPS}, /* AutoAdjustFPS */
+ {0xa0, 0x00, ZC3XX_R019_AUTOADJUSTFPS},
/* Gains */
- {0xa0, 0xa0, ZC3XX_R1A8_DIGITALGAIN}, /* DigitalGain */
+ {0xa0, 0xa0, ZC3XX_R1A8_DIGITALGAIN},
/* Unknown */
{0xa0, 0x00, 0x01ad},
/* Sharpness */
- {0xa0, 0x03, ZC3XX_R1C5_SHARPNESSMODE}, /* SharpnessMode */
- {0xa0, 0x13, ZC3XX_R1CB_SHARPNESS05}, /* Sharpness05 */
+ {0xa0, 0x03, ZC3XX_R1C5_SHARPNESSMODE},
+ {0xa0, 0x13, ZC3XX_R1CB_SHARPNESS05},
/* Other registors */
- {0xa0, 0x0d, ZC3XX_R100_OPERATIONMODE}, /* OperationMode */
+ {0xa0, 0x0d, ZC3XX_R100_OPERATIONMODE},
/* Auto exposure and white balance */
- {0xa0, 0x06, ZC3XX_R189_AWBSTATUS}, /* AWBStatus */
+ {0xa0, 0x06, ZC3XX_R189_AWBSTATUS},
/*Dead pixels */
- {0xa0, 0x08, ZC3XX_R250_DEADPIXELSMODE}, /* DeadPixelsMode */
+ {0xa0, 0x08, ZC3XX_R250_DEADPIXELSMODE},
/* EEPROM */
- {0xa0, 0x08, ZC3XX_R301_EEPROMACCESS}, /* EEPROMAccess */
+ {0xa0, 0x08, ZC3XX_R301_EEPROMACCESS},
/* JPEG control */
- {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING}, /* ClockSetting */
- {0xa0, 0x08, ZC3XX_R1C6_SHARPNESS00}, /* sharpness+ */
- {0xa0, 0x0f, ZC3XX_R1CB_SHARPNESS05}, /* sharpness- */
+ {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING},
+ {0xa0, 0x08, ZC3XX_R1C6_SHARPNESS00},
+ {0xa0, 0x0f, ZC3XX_R1CB_SHARPNESS05},
/* Other registers */
- {0xa0, 0x0d, ZC3XX_R100_OPERATIONMODE}, /* OperationMode */
+ {0xa0, 0x0d, ZC3XX_R100_OPERATIONMODE},
/* Auto exposure and white balance */
- {0xa0, 0x06, ZC3XX_R189_AWBSTATUS}, /* AWBStatus */
+ {0xa0, 0x06, ZC3XX_R189_AWBSTATUS},
/*Dead pixels */
- {0xa0, 0x08, ZC3XX_R250_DEADPIXELSMODE}, /* DeadPixelsMode */
+ {0xa0, 0x08, ZC3XX_R250_DEADPIXELSMODE},
/* EEPROM */
- {0xa0, 0x08, ZC3XX_R301_EEPROMACCESS}, /* EEPROMAccess */
+ {0xa0, 0x08, ZC3XX_R301_EEPROMACCESS},
/* JPEG control */
- {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING}, /* ClockSetting */
- {0xa0, 0x08, ZC3XX_R1C6_SHARPNESS00}, /* sharpness+ */
- {0xa0, 0x0f, ZC3XX_R1CB_SHARPNESS05}, /* sharpness- */
+ {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING},
+ {0xa0, 0x08, ZC3XX_R1C6_SHARPNESS00},
+ {0xa0, 0x0f, ZC3XX_R1CB_SHARPNESS05},
{0xa0, 0x58, ZC3XX_R10A_RGB00}, /* matrix */
{0xa0, 0xf4, ZC3XX_R10B_RGB01},
{0xa0, 0xf4, ZC3XX_R111_RGB21},
{0xa0, 0x58, ZC3XX_R112_RGB22},
/* Auto correction */
- {0xa0, 0x03, ZC3XX_R181_WINXSTART}, /* WinXstart */
- {0xa0, 0x08, ZC3XX_R182_WINXWIDTH}, /* WinXWidth */
- {0xa0, 0x16, ZC3XX_R183_WINXCENTER}, /* WinXCenter */
- {0xa0, 0x03, ZC3XX_R184_WINYSTART}, /* WinYStart */
- {0xa0, 0x05, ZC3XX_R185_WINYWIDTH}, /* WinYWidth */
- {0xa0, 0x14, ZC3XX_R186_WINYCENTER}, /* WinYCenter */
- {0xa0, 0x00, ZC3XX_R180_AUTOCORRECTENABLE}, /* AutoCorrectEnable */
+ {0xa0, 0x03, ZC3XX_R181_WINXSTART},
+ {0xa0, 0x08, ZC3XX_R182_WINXWIDTH},
+ {0xa0, 0x16, ZC3XX_R183_WINXCENTER},
+ {0xa0, 0x03, ZC3XX_R184_WINYSTART},
+ {0xa0, 0x05, ZC3XX_R185_WINYWIDTH},
+ {0xa0, 0x14, ZC3XX_R186_WINYCENTER},
+ {0xa0, 0x00, ZC3XX_R180_AUTOCORRECTENABLE},
/* Auto exposure and white balance */
- {0xa0, 0x00, ZC3XX_R190_EXPOSURELIMITHIGH}, /* ExposureLimitHigh */
- {0xa0, 0x03, ZC3XX_R191_EXPOSURELIMITMID}, /* ExposureLimitMid */
- {0xa0, 0xb1, ZC3XX_R192_EXPOSURELIMITLOW}, /* ExposureLimitLow */
- {0xa0, 0x00, ZC3XX_R195_ANTIFLICKERHIGH}, /* AntiFlickerHigh */
- {0xa0, 0x00, ZC3XX_R196_ANTIFLICKERMID}, /* AntiFlickerLow */
- {0xa0, 0x87, ZC3XX_R197_ANTIFLICKERLOW}, /* AntiFlickerLow */
- {0xa0, 0x0c, ZC3XX_R18C_AEFREEZE}, /* AEBFreeze */
- {0xa0, 0x18, ZC3XX_R18F_AEUNFREEZE}, /* AEBUnfreeze */
+ {0xa0, 0x00, ZC3XX_R190_EXPOSURELIMITHIGH},
+ {0xa0, 0x03, ZC3XX_R191_EXPOSURELIMITMID},
+ {0xa0, 0xb1, ZC3XX_R192_EXPOSURELIMITLOW},
+ {0xa0, 0x00, ZC3XX_R195_ANTIFLICKERHIGH},
+ {0xa0, 0x00, ZC3XX_R196_ANTIFLICKERMID},
+ {0xa0, 0x87, ZC3XX_R197_ANTIFLICKERLOW},
+ {0xa0, 0x0c, ZC3XX_R18C_AEFREEZE},
+ {0xa0, 0x18, ZC3XX_R18F_AEUNFREEZE},
/* sensor on */
{0xaa, 0x07, 0x00b1},
{0xaa, 0x05, 0x0003},
{0xaa, 0x04, 0x0001},
{0xaa, 0x03, 0x003b},
/* Gains */
- {0xa0, 0x20, ZC3XX_R1A9_DIGITALLIMITDIFF}, /* DigitalLimitDiff */
- {0xa0, 0x26, ZC3XX_R1AA_DIGITALGAINSTEP}, /* DigitalGainStep */
- {0xa0, 0xa0, ZC3XX_R11D_GLOBALGAIN}, /* GlobalGain */
- {0xa0, 0x60, ZC3XX_R11D_GLOBALGAIN}, /* GlobalGain */
+ {0xa0, 0x20, ZC3XX_R1A9_DIGITALLIMITDIFF},
+ {0xa0, 0x26, ZC3XX_R1AA_DIGITALGAINSTEP},
+ {0xa0, 0xa0, ZC3XX_R11D_GLOBALGAIN},
+ {0xa0, 0x60, ZC3XX_R11D_GLOBALGAIN},
/* Auto correction */
- {0xa0, 0x40, ZC3XX_R180_AUTOCORRECTENABLE}, /* AutoCorrectEnable */
+ {0xa0, 0x40, ZC3XX_R180_AUTOCORRECTENABLE},
{0xa1, 0x01, 0x0180}, /* AutoCorrectEnable */
- {0xa0, 0x42, ZC3XX_R180_AUTOCORRECTENABLE}, /* AutoCorrectEnable */
+ {0xa0, 0x42, ZC3XX_R180_AUTOCORRECTENABLE},
/* Gains */
- {0xa0, 0x40, ZC3XX_R116_RGAIN}, /* RGain */
- {0xa0, 0x40, ZC3XX_R117_GGAIN}, /* GGain */
- {0xa0, 0x40, ZC3XX_R118_BGAIN}, /* BGain */
+ {0xa0, 0x40, ZC3XX_R116_RGAIN},
+ {0xa0, 0x40, ZC3XX_R117_GGAIN},
+ {0xa0, 0x40, ZC3XX_R118_BGAIN},
{}
};
static const struct usb_action pas106b_InitialScale[] = { /* 352x288 */
/* JPEG control */
- {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING}, /* ClockSetting */
+ {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING},
/* Sream and Sensor specific */
- {0xa0, 0x0f, ZC3XX_R010_CMOSSENSORSELECT}, /* CMOSSensorSelect */
+ {0xa0, 0x0f, ZC3XX_R010_CMOSSENSORSELECT},
/* Picture size */
- {0xa0, 0x01, ZC3XX_R003_FRAMEWIDTHHIGH}, /* FrameWidthHigh */
- {0xa0, 0x60, ZC3XX_R004_FRAMEWIDTHLOW}, /* FrameWidthLow */
- {0xa0, 0x01, ZC3XX_R005_FRAMEHEIGHTHIGH}, /* FrameHeightHigh */
- {0xa0, 0x20, ZC3XX_R006_FRAMEHEIGHTLOW}, /* FrameHightLow */
+ {0xa0, 0x01, ZC3XX_R003_FRAMEWIDTHHIGH},
+ {0xa0, 0x60, ZC3XX_R004_FRAMEWIDTHLOW},
+ {0xa0, 0x01, ZC3XX_R005_FRAMEHEIGHTHIGH},
+ {0xa0, 0x20, ZC3XX_R006_FRAMEHEIGHTLOW},
/* System */
- {0xa0, 0x01, ZC3XX_R001_SYSTEMOPERATING}, /* SystemOperating */
+ {0xa0, 0x01, ZC3XX_R001_SYSTEMOPERATING},
/* Sream and Sensor specific */
- {0xa0, 0x03, ZC3XX_R012_VIDEOCONTROLFUNC}, /* VideoControlFunction */
- {0xa0, 0x01, ZC3XX_R012_VIDEOCONTROLFUNC}, /* VideoControlFunction */
+ {0xa0, 0x03, ZC3XX_R012_VIDEOCONTROLFUNC},
+ {0xa0, 0x01, ZC3XX_R012_VIDEOCONTROLFUNC},
/* Sensor Interface */
- {0xa0, 0x08, ZC3XX_R08D_COMPABILITYMODE}, /* Compatibily Mode */
+ {0xa0, 0x08, ZC3XX_R08D_COMPABILITYMODE},
/* Window inside sensor array */
- {0xa0, 0x03, ZC3XX_R09A_WINXSTARTLOW}, /* WinXStartLow */
- {0xa0, 0x00, ZC3XX_R11A_FIRSTYLOW}, /* FirstYLow */
- {0xa0, 0x03, ZC3XX_R11C_FIRSTXLOW}, /* FirstxLow */
- {0xa0, 0x28, ZC3XX_R09C_WINHEIGHTLOW}, /* WinHeightLow */
- {0xa0, 0x68, ZC3XX_R09E_WINWIDTHLOW}, /* WinWidthLow */
+ {0xa0, 0x03, ZC3XX_R09A_WINXSTARTLOW},
+ {0xa0, 0x00, ZC3XX_R11A_FIRSTYLOW},
+ {0xa0, 0x03, ZC3XX_R11C_FIRSTXLOW},
+ {0xa0, 0x28, ZC3XX_R09C_WINHEIGHTLOW},
+ {0xa0, 0x68, ZC3XX_R09E_WINWIDTHLOW},
/* Init the sensor */
{0xaa, 0x02, 0x0004},
{0xaa, 0x08, 0x0000},
{0xaa, 0x14, 0x0081},
/* Other registors */
- {0xa0, 0x37, ZC3XX_R101_SENSORCORRECTION}, /* SensorCorrection */
+ {0xa0, 0x37, ZC3XX_R101_SENSORCORRECTION},
/* Frame retreiving */
- {0xa0, 0x00, ZC3XX_R019_AUTOADJUSTFPS}, /* AutoAdjustFPS */
+ {0xa0, 0x00, ZC3XX_R019_AUTOADJUSTFPS},
/* Gains */
- {0xa0, 0xa0, ZC3XX_R1A8_DIGITALGAIN}, /* DigitalGain */
+ {0xa0, 0xa0, ZC3XX_R1A8_DIGITALGAIN},
/* Unknown */
{0xa0, 0x00, 0x01ad},
/* Sharpness */
- {0xa0, 0x03, ZC3XX_R1C5_SHARPNESSMODE}, /* SharpnessMode */
- {0xa0, 0x13, ZC3XX_R1CB_SHARPNESS05}, /* Sharpness05 */
+ {0xa0, 0x03, ZC3XX_R1C5_SHARPNESSMODE},
+ {0xa0, 0x13, ZC3XX_R1CB_SHARPNESS05},
/* Other registors */
- {0xa0, 0x0d, ZC3XX_R100_OPERATIONMODE}, /* OperationMode */
+ {0xa0, 0x0d, ZC3XX_R100_OPERATIONMODE},
/* Auto exposure and white balance */
- {0xa0, 0x06, ZC3XX_R189_AWBSTATUS}, /* AWBStatus */
- {0xa0, 0x80, ZC3XX_R18D_YTARGET}, /* ????????? */
+ {0xa0, 0x06, ZC3XX_R189_AWBSTATUS},
+ {0xa0, 0x80, ZC3XX_R18D_YTARGET},
/*Dead pixels */
- {0xa0, 0x08, ZC3XX_R250_DEADPIXELSMODE}, /* DeadPixelsMode */
+ {0xa0, 0x08, ZC3XX_R250_DEADPIXELSMODE},
/* EEPROM */
- {0xa0, 0x08, ZC3XX_R301_EEPROMACCESS}, /* EEPROMAccess */
+ {0xa0, 0x08, ZC3XX_R301_EEPROMACCESS},
/* JPEG control */
- {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING}, /* ClockSetting */
- {0xa0, 0x08, ZC3XX_R1C6_SHARPNESS00}, /* sharpness+ */
- {0xa0, 0x0f, ZC3XX_R1CB_SHARPNESS05}, /* sharpness- */
+ {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING},
+ {0xa0, 0x08, ZC3XX_R1C6_SHARPNESS00},
+ {0xa0, 0x0f, ZC3XX_R1CB_SHARPNESS05},
/* Other registers */
- {0xa0, 0x0d, ZC3XX_R100_OPERATIONMODE}, /* OperationMode */
+ {0xa0, 0x0d, ZC3XX_R100_OPERATIONMODE},
/* Auto exposure and white balance */
- {0xa0, 0x06, ZC3XX_R189_AWBSTATUS}, /* AWBStatus */
+ {0xa0, 0x06, ZC3XX_R189_AWBSTATUS},
/*Dead pixels */
- {0xa0, 0x08, ZC3XX_R250_DEADPIXELSMODE}, /* DeadPixelsMode */
+ {0xa0, 0x08, ZC3XX_R250_DEADPIXELSMODE},
/* EEPROM */
- {0xa0, 0x08, ZC3XX_R301_EEPROMACCESS}, /* EEPROMAccess */
+ {0xa0, 0x08, ZC3XX_R301_EEPROMACCESS},
/* JPEG control */
- {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING}, /* ClockSetting */
- {0xa0, 0x08, ZC3XX_R1C6_SHARPNESS00}, /* sharpness+ */
- {0xa0, 0x0f, ZC3XX_R1CB_SHARPNESS05}, /* sharpness- */
+ {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING},
+ {0xa0, 0x08, ZC3XX_R1C6_SHARPNESS00},
+ {0xa0, 0x0f, ZC3XX_R1CB_SHARPNESS05},
{0xa0, 0x58, ZC3XX_R10A_RGB00}, /* matrix */
{0xa0, 0xf4, ZC3XX_R10B_RGB01},
{0xa0, 0xf4, ZC3XX_R111_RGB21},
{0xa0, 0x58, ZC3XX_R112_RGB22},
/* Auto correction */
- {0xa0, 0x03, ZC3XX_R181_WINXSTART}, /* WinXstart */
- {0xa0, 0x08, ZC3XX_R182_WINXWIDTH}, /* WinXWidth */
- {0xa0, 0x16, ZC3XX_R183_WINXCENTER}, /* WinXCenter */
- {0xa0, 0x03, ZC3XX_R184_WINYSTART}, /* WinYStart */
- {0xa0, 0x05, ZC3XX_R185_WINYWIDTH}, /* WinYWidth */
- {0xa0, 0x14, ZC3XX_R186_WINYCENTER}, /* WinYCenter */
- {0xa0, 0x00, ZC3XX_R180_AUTOCORRECTENABLE}, /* AutoCorrectEnable */
+ {0xa0, 0x03, ZC3XX_R181_WINXSTART},
+ {0xa0, 0x08, ZC3XX_R182_WINXWIDTH},
+ {0xa0, 0x16, ZC3XX_R183_WINXCENTER},
+ {0xa0, 0x03, ZC3XX_R184_WINYSTART},
+ {0xa0, 0x05, ZC3XX_R185_WINYWIDTH},
+ {0xa0, 0x14, ZC3XX_R186_WINYCENTER},
+ {0xa0, 0x00, ZC3XX_R180_AUTOCORRECTENABLE},
/* Auto exposure and white balance */
- {0xa0, 0x00, ZC3XX_R190_EXPOSURELIMITHIGH}, /* ExposureLimitHigh 0 */
- {0xa0, 0x03, ZC3XX_R191_EXPOSURELIMITMID}, /* ExposureLimitMid */
- {0xa0, 0xb1, ZC3XX_R192_EXPOSURELIMITLOW}, /* ExposureLimitLow 0xb1 */
+ {0xa0, 0x00, ZC3XX_R190_EXPOSURELIMITHIGH},
+ {0xa0, 0x03, ZC3XX_R191_EXPOSURELIMITMID},
+ {0xa0, 0xb1, ZC3XX_R192_EXPOSURELIMITLOW},
- {0xa0, 0x00, ZC3XX_R195_ANTIFLICKERHIGH}, /* AntiFlickerHigh 0x00 */
- {0xa0, 0x00, ZC3XX_R196_ANTIFLICKERMID}, /* AntiFlickerLow 0x00 */
- {0xa0, 0x87, ZC3XX_R197_ANTIFLICKERLOW}, /* AntiFlickerLow 0x87 */
+ {0xa0, 0x00, ZC3XX_R195_ANTIFLICKERHIGH},
+ {0xa0, 0x00, ZC3XX_R196_ANTIFLICKERMID},
+ {0xa0, 0x87, ZC3XX_R197_ANTIFLICKERLOW},
- {0xa0, 0x10, ZC3XX_R18C_AEFREEZE}, /* AEBFreeze 0x10 0x0c */
- {0xa0, 0x20, ZC3XX_R18F_AEUNFREEZE}, /* AEBUnfreeze 0x30 0x18 */
+ {0xa0, 0x10, ZC3XX_R18C_AEFREEZE},
+ {0xa0, 0x20, ZC3XX_R18F_AEUNFREEZE},
/* sensor on */
{0xaa, 0x07, 0x00b1},
{0xaa, 0x05, 0x0003},
{0xaa, 0x04, 0x0001},
{0xaa, 0x03, 0x003b},
/* Gains */
- {0xa0, 0x20, ZC3XX_R1A9_DIGITALLIMITDIFF}, /* DigitalLimitDiff */
- {0xa0, 0x26, ZC3XX_R1AA_DIGITALGAINSTEP}, /* DigitalGainStep */
- {0xa0, 0xa0, ZC3XX_R11D_GLOBALGAIN}, /* GlobalGain */
- {0xa0, 0x60, ZC3XX_R11D_GLOBALGAIN}, /* GlobalGain */
+ {0xa0, 0x20, ZC3XX_R1A9_DIGITALLIMITDIFF},
+ {0xa0, 0x26, ZC3XX_R1AA_DIGITALGAINSTEP},
+ {0xa0, 0xa0, ZC3XX_R11D_GLOBALGAIN},
+ {0xa0, 0x60, ZC3XX_R11D_GLOBALGAIN},
/* Auto correction */
- {0xa0, 0x40, ZC3XX_R180_AUTOCORRECTENABLE}, /* AutoCorrectEnable */
+ {0xa0, 0x40, ZC3XX_R180_AUTOCORRECTENABLE},
{0xa1, 0x01, 0x0180}, /* AutoCorrectEnable */
- {0xa0, 0x42, ZC3XX_R180_AUTOCORRECTENABLE}, /* AutoCorrectEnable */
+ {0xa0, 0x42, ZC3XX_R180_AUTOCORRECTENABLE},
/* Gains */
- {0xa0, 0x40, ZC3XX_R116_RGAIN}, /* RGain */
- {0xa0, 0x40, ZC3XX_R117_GGAIN}, /* GGain */
- {0xa0, 0x40, ZC3XX_R118_BGAIN}, /* BGain */
+ {0xa0, 0x40, ZC3XX_R116_RGAIN},
+ {0xa0, 0x40, ZC3XX_R117_GGAIN},
+ {0xa0, 0x40, ZC3XX_R118_BGAIN},
{0xa0, 0x00, 0x0007}, /* AutoCorrectEnable */
{0xa0, 0xff, ZC3XX_R018_FRAMELOST}, /* Frame adjust */
{0xa0, 0x50, ZC3XX_R112_RGB22},
{0xa1, 0x01, 0x0008},
- {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING}, /* clock ? */
- {0xa0, 0x08, ZC3XX_R1C6_SHARPNESS00}, /* sharpness+ */
+ {0xa0, 0x03, ZC3XX_R008_CLOCKSETTING},
+ {0xa0, 0x08, ZC3XX_R1C6_SHARPNESS00},
{0xa1, 0x01, 0x01c8},
{0xa1, 0x01, 0x01c9},
{0xa1, 0x01, 0x01ca},
{0xaa, 0x1b, 0x0000}, /* 00,1b,00,aa, */
{0xaa, 0x13, 0x0002}, /* 00,13,02,aa, */
{0xaa, 0x15, 0x0004}, /* 00,15,04,aa */
- {0xaa, 0x01, 0x0000},
+/*?? {0xaa, 0x01, 0x0000}, */
{0xaa, 0x01, 0x0000},
{0xaa, 0x1a, 0x0000}, /* 00,1a,00,aa, */
{0xaa, 0x1c, 0x0017}, /* 00,1c,17,aa, */
{0xaa, 0x0f, 0x00a0}, /* 00,0f,a0,aa, */
{0xaa, 0x10, 0x0000}, /* 00,10,00,aa, */
{0xaa, 0x11, 0x00a0}, /* 00,11,a0,aa, */
- {0xa0, 0x00, 0x0039},
- {0xa1, 0x01, 0x0037},
+/*?? {0xa0, 0x00, 0x0039},
+ {0xa1, 0x01, 0x0037}, */
{0xaa, 0x16, 0x0001}, /* 00,16,01,aa, */
{0xaa, 0x17, 0x00e8}, /* 00,17,e6,aa, (e6 -> e8) */
{0xaa, 0x18, 0x0002}, /* 00,18,02,aa, */
__u8 value,
__u16 index)
{
- PDEBUG(D_USBO, "reg w %02x -> [%04x]", value, index);
+ PDEBUG(D_USBO, "reg w [%04x] = %02x", index, value);
reg_w_i(dev, value, index);
}
__u8 reg)
{
__u8 retbyte;
- __u8 retval[2];
+ __u16 retval;
reg_w_i(gspca_dev->dev, reg, 0x92);
reg_w_i(gspca_dev->dev, 0x02, 0x90); /* <- read command */
msleep(25);
retbyte = reg_r_i(gspca_dev, 0x0091); /* read status */
- retval[0] = reg_r_i(gspca_dev, 0x0095); /* read Lowbyte */
- retval[1] = reg_r_i(gspca_dev, 0x0096); /* read Hightbyte */
- PDEBUG(D_USBO, "i2c r [%02x] -> (%02x) %02x%02x",
- reg, retbyte, retval[1], retval[0]);
- return (retval[1] << 8) | retval[0];
+ retval = reg_r_i(gspca_dev, 0x0095); /* read Lowbyte */
+ retval |= reg_r_i(gspca_dev, 0x0096) << 8; /* read Hightbyte */
+ PDEBUG(D_USBO, "i2c r [%02x] -> %04x (%02x)",
+ reg, retval, retbyte);
+ return retval;
}
static __u8 i2c_write(struct gspca_dev *gspca_dev,
reg_w_i(gspca_dev->dev, 0x01, 0x90); /* <- write command */
msleep(5);
retbyte = reg_r_i(gspca_dev, 0x0091); /* read status */
- PDEBUG(D_USBO, "i2c w [%02x] %02x%02x (%02x)",
+ PDEBUG(D_USBO, "i2c w [%02x] = %02x%02x (%02x)",
reg, valH, valL, retbyte);
return retbyte;
}
{0x58, 0xf4, 0xf4, 0xf4, 0x58, 0xf4, 0xf4, 0xf4, 0x58};
static const __u8 po2030_matrix[9] =
{0x60, 0xf0, 0xf0, 0xf0, 0x60, 0xf0, 0xf0, 0xf0, 0x60};
+ static const __u8 vf0250_matrix[9] =
+ {0x7b, 0xea, 0xea, 0xea, 0x7b, 0xea, 0xea, 0xea, 0x7b};
switch (sd->sensor) {
case SENSOR_GC0305:
case SENSOR_PO2030:
matrix = po2030_matrix;
break;
- case SENSOR_TAS5130C_VF0250: /* no matrix? */
- return;
+ case SENSOR_TAS5130C_VF0250:
+ matrix = vf0250_matrix;
+ break;
default: /* matrix already loaded */
return;
}
return 0x04; /* CS2102 */
start_2wr_probe(dev, 0x06); /* OmniVision */
- reg_w(dev, 0x08, 0x8d);
+ reg_w(dev, 0x08, 0x008d);
i2c_write(gspca_dev, 0x11, 0xaa, 0x00);
retbyte = i2c_read(gspca_dev, 0x11);
if (retbyte != 0) {
return 0x0c; /* ICM105A */
start_2wr_probe(dev, 0x0e); /* PAS202BCB */
- reg_w(dev, 0x08, 0x8d);
+ reg_w(dev, 0x08, 0x008d);
i2c_write(gspca_dev, 0x03, 0xaa, 0x00);
msleep(500);
retbyte = i2c_read(gspca_dev, 0x03);
{0x8001, 0x13},
{0x8000, 0x14}, /* CS2102K */
{0x8400, 0x15}, /* TAS5130K */
- {0, 0}
};
static int vga_3wr_probe(struct gspca_dev *gspca_dev)
/*fixme: lack of 8b=b3 (11,12)-> 10, 8b=e0 (14,15,16)-> 12 found in gspcav1*/
reg_w(dev, 0x02, 0x0010);
- reg_r(gspca_dev, 0x10);
+ reg_r(gspca_dev, 0x0010);
reg_w(dev, 0x01, 0x0000);
reg_w(dev, 0x00, 0x0010);
reg_w(dev, 0x01, 0x0001);
PDEBUG(D_PROBE, "probe 3wr vga 1 0x%04x", checkword);
reg_r(gspca_dev, 0x0010);
/* this is tested only once anyway */
- i = 0;
- while (chipset_revision_sensor[i].revision) {
+ for (i = 0; i < ARRAY_SIZE(chipset_revision_sensor); i++) {
if (chipset_revision_sensor[i].revision == checkword) {
sd->chip_revision = checkword;
send_unknown(dev, SENSOR_PB0330);
return chipset_revision_sensor[i].internal_sensor_id;
}
- i++;
}
- reg_w(dev, 0x01, 0x0000);
+ reg_w(dev, 0x01, 0x0000); /* check ?? */
reg_w(dev, 0x01, 0x0001);
reg_w(dev, 0xdd, 0x008b);
reg_w(dev, 0x0a, 0x0010);
retbyte = i2c_read(gspca_dev, 0x00);
if (retbyte != 0) {
PDEBUG(D_PROBE, "probe 3wr vga type %02x", retbyte);
- send_unknown(dev, SENSOR_GC0305);
- return retbyte; /* 0x29 = gc0305 - should continue? */
+ if (retbyte == 0x11) /* VF0250 */
+ return 0x0250;
+ if (retbyte == 0x29) /* gc0305 */
+ send_unknown(dev, SENSOR_GC0305);
+ return retbyte;
}
reg_w(dev, 0x01, 0x0000); /* check OmniVision */
return 0x06; /* OmniVision confirm ? */
}
- reg_w(dev, 0x01, 0x00);
- reg_w(dev, 0x00, 0x02);
- reg_w(dev, 0x01, 0x10);
- reg_w(dev, 0x01, 0x01);
- reg_w(dev, 0xee, 0x8b);
- reg_w(dev, 0x03, 0x12);
+ reg_w(dev, 0x01, 0x0000);
+ reg_w(dev, 0x00, 0x0002);
+ reg_w(dev, 0x01, 0x0010);
+ reg_w(dev, 0x01, 0x0001);
+ reg_w(dev, 0xee, 0x008b);
+ reg_w(dev, 0x03, 0x0012);
/* msleep(150); */
- reg_w(dev, 0x01, 0x12);
- reg_w(dev, 0x05, 0x12);
- retbyte = i2c_read(gspca_dev, 0x00); /* ID 0 */
+ reg_w(dev, 0x01, 0x0012);
+ reg_w(dev, 0x05, 0x0012);
+ retbyte = i2c_read(gspca_dev, 0x0000); /* ID 0 */
checkword = retbyte << 8;
- retbyte = i2c_read(gspca_dev, 0x01); /* ID 1 */
+ retbyte = i2c_read(gspca_dev, 0x0001); /* ID 1 */
checkword |= retbyte;
PDEBUG(D_PROBE, "probe 3wr vga 2 0x%04x", checkword);
if (checkword == 0x2030) {
return checkword;
}
- reg_w(dev, 0x01, 0x00);
- reg_w(dev, 0x0a, 0x10);
- reg_w(dev, 0xd3, 0x8b);
- reg_w(dev, 0x01, 0x01);
- reg_w(dev, 0x03, 0x12);
- reg_w(dev, 0x01, 0x12);
- reg_w(dev, 0x05, 0x01);
- reg_w(dev, 0xd3, 0x8b);
+ reg_w(dev, 0x01, 0x0000);
+ reg_w(dev, 0x0a, 0x0010);
+ reg_w(dev, 0xd3, 0x008b);
+ reg_w(dev, 0x01, 0x0001);
+ reg_w(dev, 0x03, 0x0012);
+ reg_w(dev, 0x01, 0x0012);
+ reg_w(dev, 0x05, 0x0001);
+ reg_w(dev, 0xd3, 0x008b);
retbyte = i2c_read(gspca_dev, 0x01);
if (retbyte != 0) {
PDEBUG(D_PROBE, "probe 3wr vga type 0a ?");
switch (sd->sensor) {
case SENSOR_MC501CB:
+ return -1; /* don't probe */
case SENSOR_TAS5130C_VF0250:
+ /* may probe but with write in reg 0x0010 */
return -1; /* don't probe */
}
sensor = vga_2wr_probe(gspca_dev);
/* define some sensors from the vendor/product */
sd->sharpness = 2;
- switch (id->idVendor) {
- case 0x041e: /* Creative */
- switch (id->idProduct) {
- case 0x4051: /* zc301 chips */
- case 0x4053:
- sd->sensor = SENSOR_TAS5130C_VF0250;
- break;
- }
- break;
- case 0x046d: /* Logitech Labtec */
- switch (id->idProduct) {
- case 0x08dd:
- sd->sensor = SENSOR_MC501CB;
- break;
- }
- break;
- case 0x0ac8: /* Vimicro z-star */
- switch (id->idProduct) {
- case 0x305b:
- sd->sensor = SENSOR_TAS5130C_VF0250;
- break;
- }
- break;
- }
+ sd->sensor = id->driver_info;
sensor = zcxx_probeSensor(gspca_dev);
if (sensor >= 0)
PDEBUG(D_PROBE, "probe sensor -> %02x", sensor);
PDEBUG(D_PROBE, "Find Sensor GC0305");
sd->sensor = SENSOR_GC0305;
break;
+ case 0x0250:
+ PDEBUG(D_PROBE, "Sensor Tas5130 (VF0250)");
+ sd->sensor = SENSOR_TAS5130C_VF0250;
+ break;
case 0x2030:
PDEBUG(D_PROBE, "Find Sensor PO2030");
sd->sensor = SENSOR_PO2030;
}
cam = &gspca_dev->cam;
- cam->dev_name = (char *) id->driver_info;
cam->epaddr = 0x01;
/*fixme:test*/
gspca_dev->nbalt--;
case SENSOR_GC0305:
case SENSOR_OV7620:
case SENSOR_PO2030:
+ case SENSOR_TAS5130C_VF0250:
msleep(100); /* ?? */
reg_r(gspca_dev, 0x0002); /* --> 0x40 */
reg_w(dev, 0x09, 0x01ad); /* (from win traces) */
.querymenu = sd_querymenu,
};
-#define DVNM(name) .driver_info = (kernel_ulong_t) name
static const __devinitdata struct usb_device_id device_table[] = {
- {USB_DEVICE(0x041e, 0x041e), DVNM("Creative WebCam Live!")},
+ {USB_DEVICE(0x041e, 0x041e)},
#ifndef CONFIG_USB_ZC0301
- {USB_DEVICE(0x041e, 0x4017), DVNM("Creative Webcam Mobile PD1090")},
- {USB_DEVICE(0x041e, 0x401c), DVNM("Creative NX")},
- {USB_DEVICE(0x041e, 0x401e), DVNM("Creative Nx Pro")},
- {USB_DEVICE(0x041e, 0x401f), DVNM("Creative Webcam Notebook PD1171")},
+ {USB_DEVICE(0x041e, 0x4017)},
+ {USB_DEVICE(0x041e, 0x401c)},
+ {USB_DEVICE(0x041e, 0x401e)},
+ {USB_DEVICE(0x041e, 0x401f)},
#endif
- {USB_DEVICE(0x041e, 0x4029), DVNM("Creative WebCam Vista Pro")},
+ {USB_DEVICE(0x041e, 0x4029)},
#ifndef CONFIG_USB_ZC0301
- {USB_DEVICE(0x041e, 0x4034), DVNM("Creative Instant P0620")},
- {USB_DEVICE(0x041e, 0x4035), DVNM("Creative Instant P0620D")},
- {USB_DEVICE(0x041e, 0x4036), DVNM("Creative Live !")},
- {USB_DEVICE(0x041e, 0x403a), DVNM("Creative Nx Pro 2")},
+ {USB_DEVICE(0x041e, 0x4034)},
+ {USB_DEVICE(0x041e, 0x4035)},
+ {USB_DEVICE(0x041e, 0x4036)},
+ {USB_DEVICE(0x041e, 0x403a)},
#endif
- {USB_DEVICE(0x041e, 0x4051), DVNM("Creative Notebook Pro (VF0250)")},
- {USB_DEVICE(0x041e, 0x4053), DVNM("Creative Live!Cam Video IM")},
+ {USB_DEVICE(0x041e, 0x4051), .driver_info = SENSOR_TAS5130C_VF0250},
+ {USB_DEVICE(0x041e, 0x4053), .driver_info = SENSOR_TAS5130C_VF0250},
#ifndef CONFIG_USB_ZC0301
- {USB_DEVICE(0x0458, 0x7007), DVNM("Genius VideoCam V2")},
- {USB_DEVICE(0x0458, 0x700c), DVNM("Genius VideoCam V3")},
- {USB_DEVICE(0x0458, 0x700f), DVNM("Genius VideoCam Web V2")},
+ {USB_DEVICE(0x0458, 0x7007)},
+ {USB_DEVICE(0x0458, 0x700c)},
+ {USB_DEVICE(0x0458, 0x700f)},
#endif
- {USB_DEVICE(0x0461, 0x0a00), DVNM("MicroInnovation WebCam320")},
- {USB_DEVICE(0x046d, 0x08a0), DVNM("Logitech QC IM")},
- {USB_DEVICE(0x046d, 0x08a1), DVNM("Logitech QC IM 0x08A1 +sound")},
- {USB_DEVICE(0x046d, 0x08a2), DVNM("Labtec Webcam Pro")},
- {USB_DEVICE(0x046d, 0x08a3), DVNM("Logitech QC Chat")},
- {USB_DEVICE(0x046d, 0x08a6), DVNM("Logitech QCim")},
- {USB_DEVICE(0x046d, 0x08a7), DVNM("Logitech QuickCam Image")},
- {USB_DEVICE(0x046d, 0x08a9), DVNM("Logitech Notebook Deluxe")},
- {USB_DEVICE(0x046d, 0x08aa), DVNM("Labtec Webcam Notebook")},
- {USB_DEVICE(0x046d, 0x08ac), DVNM("Logitech QuickCam Cool")},
- {USB_DEVICE(0x046d, 0x08ad), DVNM("Logitech QCCommunicate STX")},
+ {USB_DEVICE(0x0461, 0x0a00)},
+ {USB_DEVICE(0x046d, 0x08a0)},
+ {USB_DEVICE(0x046d, 0x08a1)},
+ {USB_DEVICE(0x046d, 0x08a2)},
+ {USB_DEVICE(0x046d, 0x08a3)},
+ {USB_DEVICE(0x046d, 0x08a6)},
+ {USB_DEVICE(0x046d, 0x08a7)},
+ {USB_DEVICE(0x046d, 0x08a9)},
+ {USB_DEVICE(0x046d, 0x08aa)},
+ {USB_DEVICE(0x046d, 0x08ac)},
+ {USB_DEVICE(0x046d, 0x08ad)},
#ifndef CONFIG_USB_ZC0301
- {USB_DEVICE(0x046d, 0x08ae), DVNM("Logitech QuickCam for Notebooks")},
+ {USB_DEVICE(0x046d, 0x08ae)},
#endif
- {USB_DEVICE(0x046d, 0x08af), DVNM("Logitech QuickCam Cool")},
- {USB_DEVICE(0x046d, 0x08b9), DVNM("Logitech QC IM ???")},
- {USB_DEVICE(0x046d, 0x08d7), DVNM("Logitech QCam STX")},
- {USB_DEVICE(0x046d, 0x08d9), DVNM("Logitech QuickCam IM/Connect")},
- {USB_DEVICE(0x046d, 0x08d8), DVNM("Logitech Notebook Deluxe")},
- {USB_DEVICE(0x046d, 0x08da), DVNM("Logitech QuickCam Messenger")},
- {USB_DEVICE(0x046d, 0x08dd), DVNM("Logitech QuickCam for Notebooks")},
- {USB_DEVICE(0x0471, 0x0325), DVNM("Philips SPC 200 NC")},
- {USB_DEVICE(0x0471, 0x0326), DVNM("Philips SPC 300 NC")},
- {USB_DEVICE(0x0471, 0x032d), DVNM("Philips spc210nc")},
- {USB_DEVICE(0x0471, 0x032e), DVNM("Philips spc315nc")},
- {USB_DEVICE(0x055f, 0xc005), DVNM("Mustek Wcam300A")},
+ {USB_DEVICE(0x046d, 0x08af)},
+ {USB_DEVICE(0x046d, 0x08b9)},
+ {USB_DEVICE(0x046d, 0x08d7)},
+ {USB_DEVICE(0x046d, 0x08d9)},
+ {USB_DEVICE(0x046d, 0x08d8)},
+ {USB_DEVICE(0x046d, 0x08da)},
+ {USB_DEVICE(0x046d, 0x08dd), .driver_info = SENSOR_MC501CB},
+ {USB_DEVICE(0x0471, 0x0325)},
+ {USB_DEVICE(0x0471, 0x0326)},
+ {USB_DEVICE(0x0471, 0x032d)},
+ {USB_DEVICE(0x0471, 0x032e)},
+ {USB_DEVICE(0x055f, 0xc005)},
#ifndef CONFIG_USB_ZC0301
- {USB_DEVICE(0x055f, 0xd003), DVNM("Mustek WCam300A")},
- {USB_DEVICE(0x055f, 0xd004), DVNM("Mustek WCam300 AN")},
+ {USB_DEVICE(0x055f, 0xd003)},
+ {USB_DEVICE(0x055f, 0xd004)},
#endif
- {USB_DEVICE(0x0698, 0x2003), DVNM("CTX M730V built in")},
- {USB_DEVICE(0x0ac8, 0x0302), DVNM("Z-star Vimicro zc0302")},
+ {USB_DEVICE(0x0698, 0x2003)},
+ {USB_DEVICE(0x0ac8, 0x0302)},
#ifndef CONFIG_USB_ZC0301
- {USB_DEVICE(0x0ac8, 0x301b), DVNM("Z-Star zc301b")},
- {USB_DEVICE(0x0ac8, 0x303b), DVNM("Vimicro 0x303b")},
+ {USB_DEVICE(0x0ac8, 0x301b)},
+ {USB_DEVICE(0x0ac8, 0x303b)},
#endif
- {USB_DEVICE(0x0ac8, 0x305b), DVNM("Z-star Vimicro zc0305b")},
+ {USB_DEVICE(0x0ac8, 0x305b), .driver_info = SENSOR_TAS5130C_VF0250},
#ifndef CONFIG_USB_ZC0301
- {USB_DEVICE(0x0ac8, 0x307b), DVNM("Z-Star 307b")},
- {USB_DEVICE(0x10fd, 0x0128), DVNM("Typhoon Webshot II 300k 0x0128")},
- {USB_DEVICE(0x10fd, 0x8050), DVNM("Typhoon Webshot II USB 300k")},
+ {USB_DEVICE(0x0ac8, 0x307b)},
+ {USB_DEVICE(0x10fd, 0x0128)},
+ {USB_DEVICE(0x10fd, 0x8050)},
#endif
{} /* end of entry */
};
{
if (usb_register(&sd_driver) < 0)
return -1;
- PDEBUG(D_PROBE, "v%s registered", version);
+ PDEBUG(D_PROBE, "registered");
return 0;
}
tristate "Conexant cx23416/cx23415 MPEG encoder/decoder support"
depends on VIDEO_V4L1 && VIDEO_V4L2 && PCI && I2C && EXPERIMENTAL
depends on INPUT # due to VIDEO_IR
- depends on HOTPLUG # due to FW_LOADER
select I2C_ALGOBIT
- select FW_LOADER
select VIDEO_IR
select VIDEO_TUNER
select VIDEO_TVEEPROM
if (itv->options.radio == -1)
itv->options.radio = (tv.has_radio != 0);
/* only enable newi2c if an IR blaster is present */
- /* FIXME: for 2.6.20 the test against 2 should be removed */
- if (itv->options.newi2c == -1 && tv.has_ir != -1 && tv.has_ir != 2) {
- itv->options.newi2c = (tv.has_ir & 2) ? 1 : 0;
+ if (itv->options.newi2c == -1 && tv.has_ir) {
+ itv->options.newi2c = (tv.has_ir & 4) ? 1 : 0;
if (itv->options.newi2c) {
IVTV_INFO("Reopen i2c bus for IR-blaster support\n");
exit_ivtv_i2c(itv);
#include <linux/dvb/video.h>
#include <linux/dvb/audio.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/tuner.h>
#include <media/cx2341x.h>
return res;
}
-void ivtv_set_funcs(struct video_device *vdev)
-{
- vdev->vidioc_querycap = ivtv_querycap;
- vdev->vidioc_g_priority = ivtv_g_priority;
- vdev->vidioc_s_priority = ivtv_s_priority;
- vdev->vidioc_s_audio = ivtv_s_audio;
- vdev->vidioc_g_audio = ivtv_g_audio;
- vdev->vidioc_enumaudio = ivtv_enumaudio;
- vdev->vidioc_s_audout = ivtv_s_audout;
- vdev->vidioc_g_audout = ivtv_g_audout;
- vdev->vidioc_enum_input = ivtv_enum_input;
- vdev->vidioc_enum_output = ivtv_enum_output;
- vdev->vidioc_enumaudout = ivtv_enumaudout;
- vdev->vidioc_cropcap = ivtv_cropcap;
- vdev->vidioc_s_crop = ivtv_s_crop;
- vdev->vidioc_g_crop = ivtv_g_crop;
- vdev->vidioc_g_input = ivtv_g_input;
- vdev->vidioc_s_input = ivtv_s_input;
- vdev->vidioc_g_output = ivtv_g_output;
- vdev->vidioc_s_output = ivtv_s_output;
- vdev->vidioc_g_frequency = ivtv_g_frequency;
- vdev->vidioc_s_frequency = ivtv_s_frequency;
- vdev->vidioc_s_tuner = ivtv_s_tuner;
- vdev->vidioc_g_tuner = ivtv_g_tuner;
- vdev->vidioc_g_enc_index = ivtv_g_enc_index;
- vdev->vidioc_g_fbuf = ivtv_g_fbuf;
- vdev->vidioc_s_fbuf = ivtv_s_fbuf;
- vdev->vidioc_g_std = ivtv_g_std;
- vdev->vidioc_s_std = ivtv_s_std;
- vdev->vidioc_overlay = ivtv_overlay;
- vdev->vidioc_log_status = ivtv_log_status;
- vdev->vidioc_enum_fmt_vid_cap = ivtv_enum_fmt_vid_cap;
- vdev->vidioc_encoder_cmd = ivtv_encoder_cmd;
- vdev->vidioc_try_encoder_cmd = ivtv_try_encoder_cmd;
- vdev->vidioc_enum_fmt_vid_out = ivtv_enum_fmt_vid_out;
- vdev->vidioc_g_fmt_vid_cap = ivtv_g_fmt_vid_cap;
- vdev->vidioc_g_fmt_vbi_cap = ivtv_g_fmt_vbi_cap;
- vdev->vidioc_g_fmt_sliced_vbi_cap = ivtv_g_fmt_sliced_vbi_cap;
- vdev->vidioc_g_fmt_vid_out = ivtv_g_fmt_vid_out;
- vdev->vidioc_g_fmt_vid_out_overlay = ivtv_g_fmt_vid_out_overlay;
- vdev->vidioc_g_fmt_sliced_vbi_out = ivtv_g_fmt_sliced_vbi_out;
- vdev->vidioc_s_fmt_vid_cap = ivtv_s_fmt_vid_cap;
- vdev->vidioc_s_fmt_vbi_cap = ivtv_s_fmt_vbi_cap;
- vdev->vidioc_s_fmt_sliced_vbi_cap = ivtv_s_fmt_sliced_vbi_cap;
- vdev->vidioc_s_fmt_vid_out = ivtv_s_fmt_vid_out;
- vdev->vidioc_s_fmt_vid_out_overlay = ivtv_s_fmt_vid_out_overlay;
- vdev->vidioc_s_fmt_sliced_vbi_out = ivtv_s_fmt_sliced_vbi_out;
- vdev->vidioc_try_fmt_vid_cap = ivtv_try_fmt_vid_cap;
- vdev->vidioc_try_fmt_vbi_cap = ivtv_try_fmt_vbi_cap;
- vdev->vidioc_try_fmt_sliced_vbi_cap = ivtv_try_fmt_sliced_vbi_cap;
- vdev->vidioc_try_fmt_vid_out = ivtv_try_fmt_vid_out;
- vdev->vidioc_try_fmt_vid_out_overlay = ivtv_try_fmt_vid_out_overlay;
- vdev->vidioc_try_fmt_sliced_vbi_out = ivtv_try_fmt_sliced_vbi_out;
- vdev->vidioc_g_sliced_vbi_cap = ivtv_g_sliced_vbi_cap;
- vdev->vidioc_g_chip_ident = ivtv_g_chip_ident;
+static const struct v4l2_ioctl_ops ivtv_ioctl_ops = {
+ .vidioc_querycap = ivtv_querycap,
+ .vidioc_g_priority = ivtv_g_priority,
+ .vidioc_s_priority = ivtv_s_priority,
+ .vidioc_s_audio = ivtv_s_audio,
+ .vidioc_g_audio = ivtv_g_audio,
+ .vidioc_enumaudio = ivtv_enumaudio,
+ .vidioc_s_audout = ivtv_s_audout,
+ .vidioc_g_audout = ivtv_g_audout,
+ .vidioc_enum_input = ivtv_enum_input,
+ .vidioc_enum_output = ivtv_enum_output,
+ .vidioc_enumaudout = ivtv_enumaudout,
+ .vidioc_cropcap = ivtv_cropcap,
+ .vidioc_s_crop = ivtv_s_crop,
+ .vidioc_g_crop = ivtv_g_crop,
+ .vidioc_g_input = ivtv_g_input,
+ .vidioc_s_input = ivtv_s_input,
+ .vidioc_g_output = ivtv_g_output,
+ .vidioc_s_output = ivtv_s_output,
+ .vidioc_g_frequency = ivtv_g_frequency,
+ .vidioc_s_frequency = ivtv_s_frequency,
+ .vidioc_s_tuner = ivtv_s_tuner,
+ .vidioc_g_tuner = ivtv_g_tuner,
+ .vidioc_g_enc_index = ivtv_g_enc_index,
+ .vidioc_g_fbuf = ivtv_g_fbuf,
+ .vidioc_s_fbuf = ivtv_s_fbuf,
+ .vidioc_g_std = ivtv_g_std,
+ .vidioc_s_std = ivtv_s_std,
+ .vidioc_overlay = ivtv_overlay,
+ .vidioc_log_status = ivtv_log_status,
+ .vidioc_enum_fmt_vid_cap = ivtv_enum_fmt_vid_cap,
+ .vidioc_encoder_cmd = ivtv_encoder_cmd,
+ .vidioc_try_encoder_cmd = ivtv_try_encoder_cmd,
+ .vidioc_enum_fmt_vid_out = ivtv_enum_fmt_vid_out,
+ .vidioc_g_fmt_vid_cap = ivtv_g_fmt_vid_cap,
+ .vidioc_g_fmt_vbi_cap = ivtv_g_fmt_vbi_cap,
+ .vidioc_g_fmt_sliced_vbi_cap = ivtv_g_fmt_sliced_vbi_cap,
+ .vidioc_g_fmt_vid_out = ivtv_g_fmt_vid_out,
+ .vidioc_g_fmt_vid_out_overlay = ivtv_g_fmt_vid_out_overlay,
+ .vidioc_g_fmt_sliced_vbi_out = ivtv_g_fmt_sliced_vbi_out,
+ .vidioc_s_fmt_vid_cap = ivtv_s_fmt_vid_cap,
+ .vidioc_s_fmt_vbi_cap = ivtv_s_fmt_vbi_cap,
+ .vidioc_s_fmt_sliced_vbi_cap = ivtv_s_fmt_sliced_vbi_cap,
+ .vidioc_s_fmt_vid_out = ivtv_s_fmt_vid_out,
+ .vidioc_s_fmt_vid_out_overlay = ivtv_s_fmt_vid_out_overlay,
+ .vidioc_s_fmt_sliced_vbi_out = ivtv_s_fmt_sliced_vbi_out,
+ .vidioc_try_fmt_vid_cap = ivtv_try_fmt_vid_cap,
+ .vidioc_try_fmt_vbi_cap = ivtv_try_fmt_vbi_cap,
+ .vidioc_try_fmt_sliced_vbi_cap = ivtv_try_fmt_sliced_vbi_cap,
+ .vidioc_try_fmt_vid_out = ivtv_try_fmt_vid_out,
+ .vidioc_try_fmt_vid_out_overlay = ivtv_try_fmt_vid_out_overlay,
+ .vidioc_try_fmt_sliced_vbi_out = ivtv_try_fmt_sliced_vbi_out,
+ .vidioc_g_sliced_vbi_cap = ivtv_g_sliced_vbi_cap,
+ .vidioc_g_chip_ident = ivtv_g_chip_ident,
#ifdef CONFIG_VIDEO_ADV_DEBUG
- vdev->vidioc_g_register = ivtv_g_register;
- vdev->vidioc_s_register = ivtv_s_register;
+ .vidioc_g_register = ivtv_g_register,
+ .vidioc_s_register = ivtv_s_register,
#endif
- vdev->vidioc_default = ivtv_default;
- vdev->vidioc_queryctrl = ivtv_queryctrl;
- vdev->vidioc_querymenu = ivtv_querymenu;
- vdev->vidioc_g_ext_ctrls = ivtv_g_ext_ctrls;
- vdev->vidioc_s_ext_ctrls = ivtv_s_ext_ctrls;
- vdev->vidioc_try_ext_ctrls = ivtv_try_ext_ctrls;
+ .vidioc_default = ivtv_default,
+ .vidioc_queryctrl = ivtv_queryctrl,
+ .vidioc_querymenu = ivtv_querymenu,
+ .vidioc_g_ext_ctrls = ivtv_g_ext_ctrls,
+ .vidioc_s_ext_ctrls = ivtv_s_ext_ctrls,
+ .vidioc_try_ext_ctrls = ivtv_try_ext_ctrls,
+};
+
+void ivtv_set_funcs(struct video_device *vdev)
+{
+ vdev->ioctl_ops = &ivtv_ioctl_ops;
}
return -ENOMEM;
}
- s->v4l2dev->type = VID_TYPE_CAPTURE | VID_TYPE_TUNER | VID_TYPE_TELETEXT |
- VID_TYPE_CLIPPING | VID_TYPE_SCALES | VID_TYPE_MPEG_ENCODER;
- if (itv->v4l2_cap & V4L2_CAP_VIDEO_OUTPUT) {
- s->v4l2dev->type |= VID_TYPE_MPEG_DECODER;
- }
snprintf(s->v4l2dev->name, sizeof(s->v4l2dev->name), "ivtv%d %s",
itv->num, s->name);
s->v4l2dev->minor = minor;
- s->v4l2dev->dev = &itv->dev->dev;
+ s->v4l2dev->parent = &itv->dev->dev;
s->v4l2dev->fops = ivtv_stream_info[type].fops;
s->v4l2dev->release = video_device_release;
s->v4l2dev->tvnorms = V4L2_STD_ALL;
#include <asm/uaccess.h>
#include <linux/i2c.h>
#include <linux/i2c-id.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <media/m52790.h>
#include <media/v4l2-common.h>
#include <media/v4l2-chip-ident.h>
#include <linux/init.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <linux/delay.h>
.llseek = no_llseek,
};
-static struct video_device meye_template = {
- .owner = THIS_MODULE,
- .name = "meye",
- .type = VID_TYPE_CAPTURE,
- .fops = &meye_fops,
- .release = video_device_release,
- .minor = -1,
+static const struct v4l2_ioctl_ops meye_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_input = vidioc_enum_input,
.vidioc_g_input = vidioc_g_input,
.vidioc_default = vidioc_default,
};
+static struct video_device meye_template = {
+ .name = "meye",
+ .fops = &meye_fops,
+ .ioctl_ops = &meye_ioctl_ops,
+ .release = video_device_release,
+ .minor = -1,
+};
+
#ifdef CONFIG_PM
static int meye_suspend(struct pci_dev *pdev, pm_message_t state)
{
}
memcpy(meye.video_dev, &meye_template, sizeof(meye_template));
- meye.video_dev->dev = &meye.mchip_dev->dev;
+ meye.video_dev->parent = &meye.mchip_dev->dev;
if ((ret = sony_pic_camera_command(SONY_PIC_COMMAND_SETCAMERA, 1))) {
printk(KERN_ERR "meye: unable to power on the camera\n");
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
-#include <linux/videodev.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/v4l2-i2c-drv-legacy.h>
#include <media/tvaudio.h>
#include <media/msp3400.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/freezer.h>
-#include <linux/videodev.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <media/msp3400.h>
int ret;
/* Disable chip, synchronous option update */
- dev_dbg(icd->vdev->dev, "%s\n", __func__);
+ dev_dbg(icd->vdev->parent, "%s\n", __func__);
ret = reg_write(icd, MT9M001_RESET, 1);
if (ret >= 0)
};
static struct video_device vdev_template = {
- .owner = THIS_MODULE,
.name = "OV511 USB Camera",
- .type = VID_TYPE_CAPTURE,
.fops = &ov511_fops,
.release = video_device_release,
.minor = -1,
{
int rc;
- rc = video_device_create_file(vdev, &dev_attr_custom_id);
+ rc = device_create_file(&vdev->dev, &dev_attr_custom_id);
if (rc) goto err;
- rc = video_device_create_file(vdev, &dev_attr_model);
+ rc = device_create_file(&vdev->dev, &dev_attr_model);
if (rc) goto err_id;
- rc = video_device_create_file(vdev, &dev_attr_bridge);
+ rc = device_create_file(&vdev->dev, &dev_attr_bridge);
if (rc) goto err_model;
- rc = video_device_create_file(vdev, &dev_attr_sensor);
+ rc = device_create_file(&vdev->dev, &dev_attr_sensor);
if (rc) goto err_bridge;
- rc = video_device_create_file(vdev, &dev_attr_brightness);
+ rc = device_create_file(&vdev->dev, &dev_attr_brightness);
if (rc) goto err_sensor;
- rc = video_device_create_file(vdev, &dev_attr_saturation);
+ rc = device_create_file(&vdev->dev, &dev_attr_saturation);
if (rc) goto err_bright;
- rc = video_device_create_file(vdev, &dev_attr_contrast);
+ rc = device_create_file(&vdev->dev, &dev_attr_contrast);
if (rc) goto err_sat;
- rc = video_device_create_file(vdev, &dev_attr_hue);
+ rc = device_create_file(&vdev->dev, &dev_attr_hue);
if (rc) goto err_contrast;
- rc = video_device_create_file(vdev, &dev_attr_exposure);
+ rc = device_create_file(&vdev->dev, &dev_attr_exposure);
if (rc) goto err_hue;
return 0;
err_hue:
- video_device_remove_file(vdev, &dev_attr_hue);
+ device_remove_file(&vdev->dev, &dev_attr_hue);
err_contrast:
- video_device_remove_file(vdev, &dev_attr_contrast);
+ device_remove_file(&vdev->dev, &dev_attr_contrast);
err_sat:
- video_device_remove_file(vdev, &dev_attr_saturation);
+ device_remove_file(&vdev->dev, &dev_attr_saturation);
err_bright:
- video_device_remove_file(vdev, &dev_attr_brightness);
+ device_remove_file(&vdev->dev, &dev_attr_brightness);
err_sensor:
- video_device_remove_file(vdev, &dev_attr_sensor);
+ device_remove_file(&vdev->dev, &dev_attr_sensor);
err_bridge:
- video_device_remove_file(vdev, &dev_attr_bridge);
+ device_remove_file(&vdev->dev, &dev_attr_bridge);
err_model:
- video_device_remove_file(vdev, &dev_attr_model);
+ device_remove_file(&vdev->dev, &dev_attr_model);
err_id:
- video_device_remove_file(vdev, &dev_attr_custom_id);
+ device_remove_file(&vdev->dev, &dev_attr_custom_id);
err:
return rc;
}
goto error;
memcpy(ov->vdev, &vdev_template, sizeof(*ov->vdev));
- ov->vdev->dev = &intf->dev;
+ ov->vdev->parent = &intf->dev;
video_set_drvdata(ov->vdev, ov);
for (i = 0; i < OV511_MAX_UNIT_VIDEO; i++) {
#include <asm/uaccess.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/usb.h>
#include <linux/mutex.h>
-/*
- planb - PlanB frame grabber driver
-
- PlanB is used in the 7x00/8x00 series of PowerMacintosh
- Computers as video input DMA controller.
-
- Copyright (C) 1998 Michel Lanners (mlan@cpu.lu)
-
- Based largely on the bttv driver by Ralph Metzler (rjkm@thp.uni-koeln.de)
-
- Additional debugging and coding by Takashi Oe (toe@unlserve.unl.edu)
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-
-/* $Id: planb.c,v 1.18 1999/05/02 17:36:34 mlan Exp $ */
-
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/major.h>
-#include <linux/slab.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/delay.h>
-#include <linux/vmalloc.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/videodev.h>
-#include <media/v4l2-common.h>
-#include <linux/wait.h>
-#include <asm/uaccess.h>
-#include <asm/io.h>
-#include <asm/prom.h>
-#include <asm/dbdma.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/irq.h>
-#include <linux/mutex.h>
-
-#include "planb.h"
-#include "saa7196.h"
-
-/* Would you mind for some ugly debugging? */
-#if 0
-#define DEBUG(x...) printk(KERN_DEBUG ## x) /* Debug driver */
-#else
-#define DEBUG(x...) /* Don't debug driver */
-#endif
-
-#if 0
-#define IDEBUG(x...) printk(KERN_DEBUG ## x) /* Debug interrupt part */
-#else
-#define IDEBUG(x...) /* Don't debug interrupt part */
-#endif
-
-/* Ever seen a Mac with more than 1 of these? */
-#define PLANB_MAX 1
-
-static int planb_num;
-static struct planb planbs[PLANB_MAX];
-static volatile struct planb_registers *planb_regs;
-
-static int def_norm = PLANB_DEF_NORM; /* default norm */
-static int video_nr = -1;
-
-module_param(def_norm, int, 0);
-MODULE_PARM_DESC(def_norm, "Default startup norm (0=PAL, 1=NTSC, 2=SECAM)");
-module_param(video_nr, int, 0);
-MODULE_LICENSE("GPL");
-
-
-/* ------------------ PlanB Exported Functions ------------------ */
-static long planb_write(struct video_device *, const char *, unsigned long, int);
-static long planb_read(struct video_device *, char *, unsigned long, int);
-static int planb_open(struct video_device *, int);
-static void planb_close(struct video_device *);
-static int planb_ioctl(struct video_device *, unsigned int, void *);
-static int planb_init_done(struct video_device *);
-static int planb_mmap(struct video_device *, const char *, unsigned long);
-static void release_planb(void);
-int init_planbs(struct video_init *);
-
-/* ------------------ PlanB Internal Functions ------------------ */
-static int planb_prepare_open(struct planb *);
-static void planb_prepare_close(struct planb *);
-static void saa_write_reg(unsigned char, unsigned char);
-static unsigned char saa_status(int, struct planb *);
-static void saa_set(unsigned char, unsigned char, struct planb *);
-static void saa_init_regs(struct planb *);
-static int grabbuf_alloc(struct planb *);
-static int vgrab(struct planb *, struct video_mmap *);
-static void add_clip(struct planb *, struct video_clip *);
-static void fill_cmd_buff(struct planb *);
-static void cmd_buff(struct planb *);
-static volatile struct dbdma_cmd *setup_grab_cmd(int, struct planb *);
-static void overlay_start(struct planb *);
-static void overlay_stop(struct planb *);
-static inline void tab_cmd_dbdma(volatile struct dbdma_cmd *, unsigned short,
- unsigned int);
-static inline void tab_cmd_store(volatile struct dbdma_cmd *, unsigned int,
- unsigned int);
-static inline void tab_cmd_gen(volatile struct dbdma_cmd *, unsigned short,
- unsigned short, unsigned int, unsigned int);
-static int init_planb(struct planb *);
-static int find_planb(void);
-static void planb_pre_capture(int, int, struct planb *);
-static volatile struct dbdma_cmd *cmd_geo_setup(volatile struct dbdma_cmd *,
- int, int, int, int, int, struct planb *);
-static inline void planb_dbdma_stop(volatile struct dbdma_regs *);
-static unsigned int saa_geo_setup(int, int, int, int, struct planb *);
-static inline int overlay_is_active(struct planb *);
-
-/*******************************/
-/* Memory management functions */
-/*******************************/
-
-static int grabbuf_alloc(struct planb *pb)
-{
- int i, npage;
-
- npage = MAX_GBUFFERS * ((PLANB_MAX_FBUF / PAGE_SIZE + 1)
-#ifndef PLANB_GSCANLINE
- + MAX_LNUM
-#endif /* PLANB_GSCANLINE */
- );
- if ((pb->rawbuf = kmalloc(npage
- * sizeof(unsigned long), GFP_KERNEL)) == 0)
- return -ENOMEM;
- for (i = 0; i < npage; i++) {
- pb->rawbuf[i] = (unsigned char *)__get_free_pages(GFP_KERNEL
- |GFP_DMA, 0);
- if (!pb->rawbuf[i])
- break;
- SetPageReserved(virt_to_page(pb->rawbuf[i]));
- }
- if (i-- < npage) {
- printk(KERN_DEBUG "PlanB: init_grab: grab buffer not allocated\n");
- for (; i > 0; i--) {
- ClearPageReserved(virt_to_page(pb->rawbuf[i]));
- free_pages((unsigned long)pb->rawbuf[i], 0);
- }
- kfree(pb->rawbuf);
- return -ENOBUFS;
- }
- pb->rawbuf_size = npage;
- return 0;
-}
-
-/*****************************/
-/* Hardware access functions */
-/*****************************/
-
-static void saa_write_reg(unsigned char addr, unsigned char val)
-{
- planb_regs->saa_addr = addr; eieio();
- planb_regs->saa_regval = val; eieio();
- return;
-}
-
-/* return status byte 0 or 1: */
-static unsigned char saa_status(int byte, struct planb *pb)
-{
- saa_regs[pb->win.norm][SAA7196_STDC] =
- (saa_regs[pb->win.norm][SAA7196_STDC] & ~2) | ((byte & 1) << 1);
- saa_write_reg (SAA7196_STDC, saa_regs[pb->win.norm][SAA7196_STDC]);
-
- /* Let's wait 30msec for this one */
- msleep_interruptible(30);
-
- return (unsigned char)in_8 (&planb_regs->saa_status);
-}
-
-static void saa_set(unsigned char addr, unsigned char val, struct planb *pb)
-{
- if(saa_regs[pb->win.norm][addr] != val) {
- saa_regs[pb->win.norm][addr] = val;
- saa_write_reg (addr, val);
- }
- return;
-}
-
-static void saa_init_regs(struct planb *pb)
-{
- int i;
-
- for (i = 0; i < SAA7196_NUMREGS; i++)
- saa_write_reg (i, saa_regs[pb->win.norm][i]);
-}
-
-static unsigned int saa_geo_setup(int width, int height, int interlace, int bpp,
- struct planb *pb)
-{
- int ht, norm = pb->win.norm;
-
- switch(bpp) {
- case 2:
- /* RGB555+a 1x16-bit + 16-bit transparent */
- saa_regs[norm][SAA7196_FMTS] &= ~0x3;
- break;
- case 1:
- case 4:
- /* RGB888 1x24-bit + 8-bit transparent */
- saa_regs[norm][SAA7196_FMTS] &= ~0x1;
- saa_regs[norm][SAA7196_FMTS] |= 0x2;
- break;
- default:
- return -EINVAL;
- }
- ht = (interlace ? height / 2 : height);
- saa_regs[norm][SAA7196_OUTPIX] = (unsigned char) (width & 0x00ff);
- saa_regs[norm][SAA7196_HFILT] = (saa_regs[norm][SAA7196_HFILT] & ~0x3)
- | (width >> 8 & 0x3);
- saa_regs[norm][SAA7196_OUTLINE] = (unsigned char) (ht & 0xff);
- saa_regs[norm][SAA7196_VYP] = (saa_regs[norm][SAA7196_VYP] & ~0x3)
- | (ht >> 8 & 0x3);
- /* feed both fields if interlaced, or else feed only even fields */
- saa_regs[norm][SAA7196_FMTS] = (interlace) ?
- (saa_regs[norm][SAA7196_FMTS] & ~0x60)
- : (saa_regs[norm][SAA7196_FMTS] | 0x60);
- /* transparent mode; extended format enabled */
- saa_regs[norm][SAA7196_DPATH] |= 0x3;
-
- return 0;
-}
-
-/***************************/
-/* DBDMA support functions */
-/***************************/
-
-static inline void planb_dbdma_restart(volatile struct dbdma_regs *ch)
-{
- out_le32(&ch->control, PLANB_CLR(RUN));
- out_le32(&ch->control, PLANB_SET(RUN|WAKE) | PLANB_CLR(PAUSE));
-}
-
-static inline void planb_dbdma_stop(volatile struct dbdma_regs *ch)
-{
- int i = 0;
-
- out_le32(&ch->control, PLANB_CLR(RUN) | PLANB_SET(FLUSH));
- while((in_le32(&ch->status) == (ACTIVE | FLUSH)) && (i < 999)) {
- IDEBUG("PlanB: waiting for DMA to stop\n");
- i++;
- }
-}
-
-static inline void tab_cmd_dbdma(volatile struct dbdma_cmd *ch,
- unsigned short command, unsigned int cmd_dep)
-{
- st_le16(&ch->command, command);
- st_le32(&ch->cmd_dep, cmd_dep);
-}
-
-static inline void tab_cmd_store(volatile struct dbdma_cmd *ch,
- unsigned int phy_addr, unsigned int cmd_dep)
-{
- st_le16(&ch->command, STORE_WORD | KEY_SYSTEM);
- st_le16(&ch->req_count, 4);
- st_le32(&ch->phy_addr, phy_addr);
- st_le32(&ch->cmd_dep, cmd_dep);
-}
-
-static inline void tab_cmd_gen(volatile struct dbdma_cmd *ch,
- unsigned short command, unsigned short req_count,
- unsigned int phy_addr, unsigned int cmd_dep)
-{
- st_le16(&ch->command, command);
- st_le16(&ch->req_count, req_count);
- st_le32(&ch->phy_addr, phy_addr);
- st_le32(&ch->cmd_dep, cmd_dep);
-}
-
-static volatile struct dbdma_cmd *cmd_geo_setup(
- volatile struct dbdma_cmd *c1, int width, int height, int interlace,
- int bpp, int clip, struct planb *pb)
-{
- int norm = pb->win.norm;
-
- if((saa_geo_setup(width, height, interlace, bpp, pb)) != 0)
- return (volatile struct dbdma_cmd *)NULL;
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_addr),
- SAA7196_FMTS);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_regval),
- saa_regs[norm][SAA7196_FMTS]);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_addr),
- SAA7196_DPATH);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_regval),
- saa_regs[norm][SAA7196_DPATH]);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->even),
- bpp | ((clip)? PLANB_CLIPMASK: 0));
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->odd),
- bpp | ((clip)? PLANB_CLIPMASK: 0));
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_addr),
- SAA7196_OUTPIX);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_regval),
- saa_regs[norm][SAA7196_OUTPIX]);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_addr),
- SAA7196_HFILT);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_regval),
- saa_regs[norm][SAA7196_HFILT]);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_addr),
- SAA7196_OUTLINE);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_regval),
- saa_regs[norm][SAA7196_OUTLINE]);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_addr),
- SAA7196_VYP);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->saa_regval),
- saa_regs[norm][SAA7196_VYP]);
- return c1;
-}
-
-/******************************/
-/* misc. supporting functions */
-/******************************/
-
-static inline void planb_lock(struct planb *pb)
-{
- mutex_lock(&pb->lock);
-}
-
-static inline void planb_unlock(struct planb *pb)
-{
- mutex_unlock(&pb->lock);
-}
-
-/***************/
-/* Driver Core */
-/***************/
-
-static int planb_prepare_open(struct planb *pb)
-{
- int i, size;
-
- /* allocate memory for two plus alpha command buffers (size: max lines,
- plus 40 commands handling, plus 1 alignment), plus dummy command buf,
- plus clipmask buffer, plus frame grabbing status */
- size = (pb->tab_size*(2+MAX_GBUFFERS*TAB_FACTOR)+1+MAX_GBUFFERS
- * PLANB_DUMMY)*sizeof(struct dbdma_cmd)
- +(PLANB_MAXLINES*((PLANB_MAXPIXELS+7)& ~7))/8
- +MAX_GBUFFERS*sizeof(unsigned int);
- if ((pb->priv_space = kzalloc (size, GFP_KERNEL)) == 0)
- return -ENOMEM;
- pb->overlay_last1 = pb->ch1_cmd = (volatile struct dbdma_cmd *)
- DBDMA_ALIGN (pb->priv_space);
- pb->overlay_last2 = pb->ch2_cmd = pb->ch1_cmd + pb->tab_size;
- pb->ch1_cmd_phys = virt_to_bus(pb->ch1_cmd);
- pb->cap_cmd[0] = pb->ch2_cmd + pb->tab_size;
- pb->pre_cmd[0] = pb->cap_cmd[0] + pb->tab_size * TAB_FACTOR;
- for (i = 1; i < MAX_GBUFFERS; i++) {
- pb->cap_cmd[i] = pb->pre_cmd[i-1] + PLANB_DUMMY;
- pb->pre_cmd[i] = pb->cap_cmd[i] + pb->tab_size * TAB_FACTOR;
- }
- pb->frame_stat=(volatile unsigned int *)(pb->pre_cmd[MAX_GBUFFERS-1]
- + PLANB_DUMMY);
- pb->mask = (unsigned char *)(pb->frame_stat+MAX_GBUFFERS);
-
- pb->rawbuf = NULL;
- pb->rawbuf_size = 0;
- pb->grabbing = 0;
- for (i = 0; i < MAX_GBUFFERS; i++) {
- pb->frame_stat[i] = GBUFFER_UNUSED;
- pb->gwidth[i] = 0;
- pb->gheight[i] = 0;
- pb->gfmt[i] = 0;
- pb->gnorm_switch[i] = 0;
-#ifndef PLANB_GSCANLINE
- pb->lsize[i] = 0;
- pb->lnum[i] = 0;
-#endif /* PLANB_GSCANLINE */
- }
- pb->gcount = 0;
- pb->suspend = 0;
- pb->last_fr = -999;
- pb->prev_last_fr = -999;
-
- /* Reset DMA controllers */
- planb_dbdma_stop(&pb->planb_base->ch2);
- planb_dbdma_stop(&pb->planb_base->ch1);
-
- return 0;
-}
-
-static void planb_prepare_close(struct planb *pb)
-{
- int i;
-
- /* make sure the dma's are idle */
- planb_dbdma_stop(&pb->planb_base->ch2);
- planb_dbdma_stop(&pb->planb_base->ch1);
- /* free kernel memory of command buffers */
- if(pb->priv_space != 0) {
- kfree (pb->priv_space);
- pb->priv_space = 0;
- pb->cmd_buff_inited = 0;
- }
- if(pb->rawbuf) {
- for (i = 0; i < pb->rawbuf_size; i++) {
- ClearPageReserved(virt_to_page(pb->rawbuf[i]));
- free_pages((unsigned long)pb->rawbuf[i], 0);
- }
- kfree(pb->rawbuf);
- }
- pb->rawbuf = NULL;
-}
-
-/*****************************/
-/* overlay support functions */
-/*****************************/
-
-static inline int overlay_is_active(struct planb *pb)
-{
- unsigned int size = pb->tab_size * sizeof(struct dbdma_cmd);
- unsigned int caddr = (unsigned)in_le32(&pb->planb_base->ch1.cmdptr);
-
- return (in_le32(&pb->overlay_last1->cmd_dep) == pb->ch1_cmd_phys)
- && (caddr < (pb->ch1_cmd_phys + size))
- && (caddr >= (unsigned)pb->ch1_cmd_phys);
-}
-
-static void overlay_start(struct planb *pb)
-{
-
- DEBUG("PlanB: overlay_start()\n");
-
- if(ACTIVE & in_le32(&pb->planb_base->ch1.status)) {
-
- DEBUG("PlanB: presumably, grabbing is in progress...\n");
-
- planb_dbdma_stop(&pb->planb_base->ch2);
- out_le32 (&pb->planb_base->ch2.cmdptr,
- virt_to_bus(pb->ch2_cmd));
- planb_dbdma_restart(&pb->planb_base->ch2);
- st_le16 (&pb->ch1_cmd->command, DBDMA_NOP);
- tab_cmd_dbdma(pb->last_cmd[pb->last_fr],
- DBDMA_NOP | BR_ALWAYS,
- virt_to_bus(pb->ch1_cmd));
- eieio();
- pb->prev_last_fr = pb->last_fr;
- pb->last_fr = -2;
- if(!(ACTIVE & in_le32(&pb->planb_base->ch1.status))) {
- IDEBUG("PlanB: became inactive "
- "in the mean time... reactivating\n");
- planb_dbdma_stop(&pb->planb_base->ch1);
- out_le32 (&pb->planb_base->ch1.cmdptr,
- virt_to_bus(pb->ch1_cmd));
- planb_dbdma_restart(&pb->planb_base->ch1);
- }
- } else {
-
- DEBUG("PlanB: currently idle, so can do whatever\n");
-
- planb_dbdma_stop(&pb->planb_base->ch2);
- planb_dbdma_stop(&pb->planb_base->ch1);
- st_le32 (&pb->planb_base->ch2.cmdptr,
- virt_to_bus(pb->ch2_cmd));
- st_le32 (&pb->planb_base->ch1.cmdptr,
- virt_to_bus(pb->ch1_cmd));
- out_le16 (&pb->ch1_cmd->command, DBDMA_NOP);
- planb_dbdma_restart(&pb->planb_base->ch2);
- planb_dbdma_restart(&pb->planb_base->ch1);
- pb->last_fr = -1;
- }
- return;
-}
-
-static void overlay_stop(struct planb *pb)
-{
- DEBUG("PlanB: overlay_stop()\n");
-
- if(pb->last_fr == -1) {
-
- DEBUG("PlanB: no grabbing, it seems...\n");
-
- planb_dbdma_stop(&pb->planb_base->ch2);
- planb_dbdma_stop(&pb->planb_base->ch1);
- pb->last_fr = -999;
- } else if(pb->last_fr == -2) {
- unsigned int cmd_dep;
- tab_cmd_dbdma(pb->cap_cmd[pb->prev_last_fr], DBDMA_STOP, 0);
- eieio();
- cmd_dep = (unsigned int)in_le32(&pb->overlay_last1->cmd_dep);
- if(overlay_is_active(pb)) {
-
- DEBUG("PlanB: overlay is currently active\n");
-
- planb_dbdma_stop(&pb->planb_base->ch2);
- planb_dbdma_stop(&pb->planb_base->ch1);
- if(cmd_dep != pb->ch1_cmd_phys) {
- out_le32(&pb->planb_base->ch1.cmdptr,
- virt_to_bus(pb->overlay_last1));
- planb_dbdma_restart(&pb->planb_base->ch1);
- }
- }
- pb->last_fr = pb->prev_last_fr;
- pb->prev_last_fr = -999;
- }
- return;
-}
-
-static void suspend_overlay(struct planb *pb)
-{
- int fr = -1;
- struct dbdma_cmd last;
-
- DEBUG("PlanB: suspend_overlay: %d\n", pb->suspend);
-
- if(pb->suspend++)
- return;
- if(ACTIVE & in_le32(&pb->planb_base->ch1.status)) {
- if(pb->last_fr == -2) {
- fr = pb->prev_last_fr;
- memcpy(&last, (void*)pb->last_cmd[fr], sizeof(last));
- tab_cmd_dbdma(pb->last_cmd[fr], DBDMA_STOP, 0);
- }
- if(overlay_is_active(pb)) {
- planb_dbdma_stop(&pb->planb_base->ch2);
- planb_dbdma_stop(&pb->planb_base->ch1);
- pb->suspended.overlay = 1;
- pb->suspended.frame = fr;
- memcpy(&pb->suspended.cmd, &last, sizeof(last));
- return;
- }
- }
- pb->suspended.overlay = 0;
- pb->suspended.frame = fr;
- memcpy(&pb->suspended.cmd, &last, sizeof(last));
- return;
-}
-
-static void resume_overlay(struct planb *pb)
-{
-
- DEBUG("PlanB: resume_overlay: %d\n", pb->suspend);
-
- if(pb->suspend > 1)
- return;
- if(pb->suspended.frame != -1) {
- memcpy((void*)pb->last_cmd[pb->suspended.frame],
- &pb->suspended.cmd, sizeof(pb->suspended.cmd));
- }
- if(ACTIVE & in_le32(&pb->planb_base->ch1.status)) {
- goto finish;
- }
- if(pb->suspended.overlay) {
-
- DEBUG("PlanB: overlay being resumed\n");
-
- st_le16 (&pb->ch1_cmd->command, DBDMA_NOP);
- st_le16 (&pb->ch2_cmd->command, DBDMA_NOP);
- /* Set command buffer addresses */
- st_le32(&pb->planb_base->ch1.cmdptr,
- virt_to_bus(pb->overlay_last1));
- out_le32(&pb->planb_base->ch2.cmdptr,
- virt_to_bus(pb->overlay_last2));
- /* Start the DMA controller */
- out_le32 (&pb->planb_base->ch2.control,
- PLANB_CLR(PAUSE) | PLANB_SET(RUN|WAKE));
- out_le32 (&pb->planb_base->ch1.control,
- PLANB_CLR(PAUSE) | PLANB_SET(RUN|WAKE));
- } else if(pb->suspended.frame != -1) {
- out_le32(&pb->planb_base->ch1.cmdptr,
- virt_to_bus(pb->last_cmd[pb->suspended.frame]));
- out_le32 (&pb->planb_base->ch1.control,
- PLANB_CLR(PAUSE) | PLANB_SET(RUN|WAKE));
- }
-
-finish:
- pb->suspend--;
- wake_up_interruptible(&pb->suspendq);
-}
-
-static void add_clip(struct planb *pb, struct video_clip *clip)
-{
- volatile unsigned char *base;
- int xc = clip->x, yc = clip->y;
- int wc = clip->width, hc = clip->height;
- int ww = pb->win.width, hw = pb->win.height;
- int x, y, xtmp1, xtmp2;
-
- DEBUG("PlanB: clip %dx%d+%d+%d\n", wc, hc, xc, yc);
-
- if(xc < 0) {
- wc += xc;
- xc = 0;
- }
- if(yc < 0) {
- hc += yc;
- yc = 0;
- }
- if(xc + wc > ww)
- wc = ww - xc;
- if(wc <= 0) /* Nothing to do */
- return;
- if(yc + hc > hw)
- hc = hw - yc;
-
- for (y = yc; y < yc+hc; y++) {
- xtmp1=xc>>3;
- xtmp2=(xc+wc)>>3;
- base = pb->mask + y*96;
- if(xc != 0 || wc >= 8)
- *(base + xtmp1) &= (unsigned char)(0x00ff &
- (0xff00 >> (xc&7)));
- for (x = xtmp1 + 1; x < xtmp2; x++) {
- *(base + x) = 0;
- }
- if(xc < (ww & ~0x7))
- *(base + xtmp2) &= (unsigned char)(0x00ff >>
- ((xc+wc) & 7));
- }
-
- return;
-}
-
-static void fill_cmd_buff(struct planb *pb)
-{
- int restore = 0;
- volatile struct dbdma_cmd last;
-
- DEBUG("PlanB: fill_cmd_buff()\n");
-
- if(pb->overlay_last1 != pb->ch1_cmd) {
- restore = 1;
- last = *(pb->overlay_last1);
- }
- memset ((void *) pb->ch1_cmd, 0, 2 * pb->tab_size
- * sizeof(struct dbdma_cmd));
- cmd_buff (pb);
- if(restore)
- *(pb->overlay_last1) = last;
- if(pb->suspended.overlay) {
- unsigned long jump_addr = in_le32(&pb->overlay_last1->cmd_dep);
- if(jump_addr != pb->ch1_cmd_phys) {
- int i;
-
- DEBUG("PlanB: adjusting ch1's jump address\n");
-
- for(i = 0; i < MAX_GBUFFERS; i++) {
- if(pb->need_pre_capture[i]) {
- if(jump_addr == virt_to_bus(pb->pre_cmd[i]))
- goto found;
- } else {
- if(jump_addr == virt_to_bus(pb->cap_cmd[i]))
- goto found;
- }
- }
-
- DEBUG("PlanB: not found...\n");
-
- goto out;
-found:
- if(pb->need_pre_capture[i])
- out_le32(&pb->pre_cmd[i]->phy_addr,
- virt_to_bus(pb->overlay_last1));
- else
- out_le32(&pb->cap_cmd[i]->phy_addr,
- virt_to_bus(pb->overlay_last1));
- }
- }
-out:
- pb->cmd_buff_inited = 1;
-
- return;
-}
-
-static void cmd_buff(struct planb *pb)
-{
- int i, bpp, count, nlines, stepsize, interlace;
- unsigned long base, jump, addr_com, addr_dep;
- volatile struct dbdma_cmd *c1 = pb->ch1_cmd;
- volatile struct dbdma_cmd *c2 = pb->ch2_cmd;
-
- interlace = pb->win.interlace;
- bpp = pb->win.bpp;
- count = (bpp * ((pb->win.x + pb->win.width > pb->win.swidth) ?
- (pb->win.swidth - pb->win.x) : pb->win.width));
- nlines = ((pb->win.y + pb->win.height > pb->win.sheight) ?
- (pb->win.sheight - pb->win.y) : pb->win.height);
-
- /* Do video in: */
-
- /* Preamble commands: */
- addr_com = virt_to_bus(c1);
- addr_dep = virt_to_bus(&c1->cmd_dep);
- tab_cmd_dbdma(c1++, DBDMA_NOP, 0);
- jump = virt_to_bus(c1+16); /* 14 by cmd_geo_setup() and 2 for padding */
- if((c1 = cmd_geo_setup(c1, pb->win.width, pb->win.height, interlace,
- bpp, 1, pb)) == NULL) {
- printk(KERN_WARNING "PlanB: encountered serious problems\n");
- tab_cmd_dbdma(pb->ch1_cmd + 1, DBDMA_STOP, 0);
- tab_cmd_dbdma(pb->ch2_cmd + 1, DBDMA_STOP, 0);
- return;
- }
- tab_cmd_store(c1++, addr_com, (unsigned)(DBDMA_NOP | BR_ALWAYS) << 16);
- tab_cmd_store(c1++, addr_dep, jump);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.wait_sel),
- PLANB_SET(FIELD_SYNC));
- /* (1) wait for field sync to be set */
- tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFCLR, 0);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
- PLANB_SET(ODD_FIELD));
- /* wait for field sync to be cleared */
- tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFSET, 0);
- /* if not odd field, wait until field sync is set again */
- tab_cmd_dbdma(c1, DBDMA_NOP | BR_IFSET, virt_to_bus(c1-3)); c1++;
- /* assert ch_sync to ch2 */
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch2.control),
- PLANB_SET(CH_SYNC));
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
- PLANB_SET(DMA_ABORT));
-
- base = (pb->frame_buffer_phys + pb->offset + pb->win.y * (pb->win.bpl
- + pb->win.pad) + pb->win.x * bpp);
-
- if (interlace) {
- stepsize = 2;
- jump = virt_to_bus(c1 + (nlines + 1) / 2);
- } else {
- stepsize = 1;
- jump = virt_to_bus(c1 + nlines);
- }
-
- /* even field data: */
- for (i=0; i < nlines; i += stepsize, c1++)
- tab_cmd_gen(c1, INPUT_MORE | KEY_STREAM0 | BR_IFSET,
- count, base + i * (pb->win.bpl + pb->win.pad), jump);
-
- /* For non-interlaced, we use even fields only */
- if (!interlace)
- goto cmd_tab_data_end;
-
- /* Resync to odd field */
- /* (2) wait for field sync to be set */
- tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFCLR, 0);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
- PLANB_SET(ODD_FIELD));
- /* wait for field sync to be cleared */
- tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFSET, 0);
- /* if not odd field, wait until field sync is set again */
- tab_cmd_dbdma(c1, DBDMA_NOP | BR_IFCLR, virt_to_bus(c1-3)); c1++;
- /* assert ch_sync to ch2 */
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch2.control),
- PLANB_SET(CH_SYNC));
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
- PLANB_SET(DMA_ABORT));
-
- /* odd field data: */
- jump = virt_to_bus(c1 + nlines / 2);
- for (i=1; i < nlines; i += stepsize, c1++)
- tab_cmd_gen(c1, INPUT_MORE | KEY_STREAM0 | BR_IFSET, count,
- base + i * (pb->win.bpl + pb->win.pad), jump);
-
- /* And jump back to the start */
-cmd_tab_data_end:
- pb->overlay_last1 = c1; /* keep a pointer to the last command */
- tab_cmd_dbdma(c1, DBDMA_NOP | BR_ALWAYS, virt_to_bus(pb->ch1_cmd));
-
- /* Clipmask command buffer */
-
- /* Preamble commands: */
- tab_cmd_dbdma(c2++, DBDMA_NOP, 0);
- tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch2.wait_sel),
- PLANB_SET(CH_SYNC));
- /* wait until ch1 asserts ch_sync */
- tab_cmd_dbdma(c2++, DBDMA_NOP | WAIT_IFCLR, 0);
- /* clear ch_sync asserted by ch1 */
- tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch2.control),
- PLANB_CLR(CH_SYNC));
- tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch2.wait_sel),
- PLANB_SET(FIELD_SYNC));
- tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch2.br_sel),
- PLANB_SET(ODD_FIELD));
-
- /* jump to end of even field if appropriate */
- /* this points to (interlace)? pos. C: pos. B */
- jump = (interlace) ? virt_to_bus(c2 + (nlines + 1) / 2 + 2):
- virt_to_bus(c2 + nlines + 2);
- /* if odd field, skip over to odd field clipmasking */
- tab_cmd_dbdma(c2++, DBDMA_NOP | BR_IFSET, jump);
-
- /* even field mask: */
- tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch2.br_sel),
- PLANB_SET(DMA_ABORT));
- /* this points to pos. B */
- jump = (interlace) ? virt_to_bus(c2 + nlines + 1):
- virt_to_bus(c2 + nlines);
- base = virt_to_bus(pb->mask);
- for (i=0; i < nlines; i += stepsize, c2++)
- tab_cmd_gen(c2, OUTPUT_MORE | KEY_STREAM0 | BR_IFSET, 96,
- base + i * 96, jump);
-
- /* For non-interlaced, we use only even fields */
- if(!interlace)
- goto cmd_tab_mask_end;
-
- /* odd field mask: */
-/* C */ tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch2.br_sel),
- PLANB_SET(DMA_ABORT));
- /* this points to pos. B */
- jump = virt_to_bus(c2 + nlines / 2);
- base = virt_to_bus(pb->mask);
- for (i=1; i < nlines; i += 2, c2++) /* abort if set */
- tab_cmd_gen(c2, OUTPUT_MORE | KEY_STREAM0 | BR_IFSET, 96,
- base + i * 96, jump);
-
- /* Inform channel 1 and jump back to start */
-cmd_tab_mask_end:
- /* ok, I just realized this is kind of flawed. */
- /* this part is reached only after odd field clipmasking. */
- /* wanna clean up? */
- /* wait for field sync to be set */
- /* corresponds to fsync (1) of ch1 */
-/* B */ tab_cmd_dbdma(c2++, DBDMA_NOP | WAIT_IFCLR, 0);
- /* restart ch1, meant to clear any dead bit or something */
- tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch1.control),
- PLANB_CLR(RUN));
- tab_cmd_store(c2++, (unsigned)(&pb->planb_base_phys->ch1.control),
- PLANB_SET(RUN));
- pb->overlay_last2 = c2; /* keep a pointer to the last command */
- /* start over even field clipmasking */
- tab_cmd_dbdma(c2, DBDMA_NOP | BR_ALWAYS, virt_to_bus(pb->ch2_cmd));
-
- eieio();
- return;
-}
-
-/*********************************/
-/* grabdisplay support functions */
-/*********************************/
-
-static int palette2fmt[] = {
- 0,
- PLANB_GRAY,
- 0,
- 0,
- 0,
- PLANB_COLOUR32,
- PLANB_COLOUR15,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
-};
-
-#define PLANB_PALETTE_MAX 15
-
-static int vgrab(struct planb *pb, struct video_mmap *mp)
-{
- unsigned int fr = mp->frame;
- unsigned int format;
-
- if(pb->rawbuf==NULL) {
- int err;
- if((err=grabbuf_alloc(pb)))
- return err;
- }
-
- IDEBUG("PlanB: grab %d: %dx%d(%u)\n", pb->grabbing,
- mp->width, mp->height, fr);
-
- if(pb->grabbing >= MAX_GBUFFERS)
- return -ENOBUFS;
- if(fr > (MAX_GBUFFERS - 1) || fr < 0)
- return -EINVAL;
- if(mp->height <= 0 || mp->width <= 0)
- return -EINVAL;
- if(mp->format < 0 || mp->format >= PLANB_PALETTE_MAX)
- return -EINVAL;
- if((format = palette2fmt[mp->format]) == 0)
- return -EINVAL;
- if (mp->height * mp->width * format > PLANB_MAX_FBUF) /* format = bpp */
- return -EINVAL;
-
- planb_lock(pb);
- if(mp->width != pb->gwidth[fr] || mp->height != pb->gheight[fr] ||
- format != pb->gfmt[fr] || (pb->gnorm_switch[fr])) {
- int i;
-#ifndef PLANB_GSCANLINE
- unsigned int osize = pb->gwidth[fr] * pb->gheight[fr]
- * pb->gfmt[fr];
- unsigned int nsize = mp->width * mp->height * format;
-#endif
-
- IDEBUG("PlanB: gwidth = %d, gheight = %d, mp->format = %u\n",
- mp->width, mp->height, mp->format);
-
-#ifndef PLANB_GSCANLINE
- if(pb->gnorm_switch[fr])
- nsize = 0;
- if (nsize < osize) {
- for(i = pb->gbuf_idx[fr]; osize > 0; i++) {
- memset((void *)pb->rawbuf[i], 0, PAGE_SIZE);
- osize -= PAGE_SIZE;
- }
- }
- for(i = pb->l_fr_addr_idx[fr]; i < pb->l_fr_addr_idx[fr]
- + pb->lnum[fr]; i++)
- memset((void *)pb->rawbuf[i], 0, PAGE_SIZE);
-#else
-/* XXX TODO */
-/*
- if(pb->gnorm_switch[fr])
- memset((void *)pb->gbuffer[fr], 0,
- pb->gbytes_per_line * pb->gheight[fr]);
- else {
- if(mp->
- for(i = 0; i < pb->gheight[fr]; i++) {
- memset((void *)(pb->gbuffer[fr]
- + pb->gbytes_per_line * i
- }
- }
-*/
-#endif
- pb->gwidth[fr] = mp->width;
- pb->gheight[fr] = mp->height;
- pb->gfmt[fr] = format;
- pb->last_cmd[fr] = setup_grab_cmd(fr, pb);
- planb_pre_capture(fr, pb->gfmt[fr], pb); /* gfmt = bpp */
- pb->need_pre_capture[fr] = 1;
- pb->gnorm_switch[fr] = 0;
- } else
- pb->need_pre_capture[fr] = 0;
- pb->frame_stat[fr] = GBUFFER_GRABBING;
- if(!(ACTIVE & in_le32(&pb->planb_base->ch1.status))) {
-
- IDEBUG("PlanB: ch1 inactive, initiating grabbing\n");
-
- planb_dbdma_stop(&pb->planb_base->ch1);
- if(pb->need_pre_capture[fr]) {
-
- IDEBUG("PlanB: padding pre-capture sequence\n");
-
- out_le32 (&pb->planb_base->ch1.cmdptr,
- virt_to_bus(pb->pre_cmd[fr]));
- } else {
- tab_cmd_dbdma(pb->last_cmd[fr], DBDMA_STOP, 0);
- tab_cmd_dbdma(pb->cap_cmd[fr], DBDMA_NOP, 0);
- /* let's be on the safe side. here is not timing critical. */
- tab_cmd_dbdma((pb->cap_cmd[fr] + 1), DBDMA_NOP, 0);
- out_le32 (&pb->planb_base->ch1.cmdptr,
- virt_to_bus(pb->cap_cmd[fr]));
- }
- planb_dbdma_restart(&pb->planb_base->ch1);
- pb->last_fr = fr;
- } else {
- int i;
-
- IDEBUG("PlanB: ch1 active, grabbing being queued\n");
-
- if((pb->last_fr == -1) || ((pb->last_fr == -2) &&
- overlay_is_active(pb))) {
-
- IDEBUG("PlanB: overlay is active, grabbing defered\n");
-
- tab_cmd_dbdma(pb->last_cmd[fr],
- DBDMA_NOP | BR_ALWAYS,
- virt_to_bus(pb->ch1_cmd));
- if(pb->need_pre_capture[fr]) {
-
- IDEBUG("PlanB: padding pre-capture sequence\n");
-
- tab_cmd_store(pb->pre_cmd[fr],
- virt_to_bus(&pb->overlay_last1->cmd_dep),
- virt_to_bus(pb->ch1_cmd));
- eieio();
- out_le32 (&pb->overlay_last1->cmd_dep,
- virt_to_bus(pb->pre_cmd[fr]));
- } else {
- tab_cmd_store(pb->cap_cmd[fr],
- virt_to_bus(&pb->overlay_last1->cmd_dep),
- virt_to_bus(pb->ch1_cmd));
- tab_cmd_dbdma((pb->cap_cmd[fr] + 1),
- DBDMA_NOP, 0);
- eieio();
- out_le32 (&pb->overlay_last1->cmd_dep,
- virt_to_bus(pb->cap_cmd[fr]));
- }
- for(i = 0; overlay_is_active(pb) && i < 999; i++)
- IDEBUG("PlanB: waiting for overlay done\n");
- tab_cmd_dbdma(pb->ch1_cmd, DBDMA_NOP, 0);
- pb->prev_last_fr = fr;
- pb->last_fr = -2;
- } else if(pb->last_fr == -2) {
-
- IDEBUG("PlanB: mixed mode detected, grabbing"
- " will be done before activating overlay\n");
-
- tab_cmd_dbdma(pb->ch1_cmd, DBDMA_NOP, 0);
- if(pb->need_pre_capture[fr]) {
-
- IDEBUG("PlanB: padding pre-capture sequence\n");
-
- tab_cmd_dbdma(pb->last_cmd[pb->prev_last_fr],
- DBDMA_NOP | BR_ALWAYS,
- virt_to_bus(pb->pre_cmd[fr]));
- eieio();
- } else {
- tab_cmd_dbdma(pb->cap_cmd[fr], DBDMA_NOP, 0);
- if(pb->gwidth[pb->prev_last_fr] !=
- pb->gwidth[fr]
- || pb->gheight[pb->prev_last_fr] !=
- pb->gheight[fr]
- || pb->gfmt[pb->prev_last_fr] !=
- pb->gfmt[fr])
- tab_cmd_dbdma((pb->cap_cmd[fr] + 1),
- DBDMA_NOP, 0);
- else
- tab_cmd_dbdma((pb->cap_cmd[fr] + 1),
- DBDMA_NOP | BR_ALWAYS,
- virt_to_bus(pb->cap_cmd[fr] + 16));
- tab_cmd_dbdma(pb->last_cmd[pb->prev_last_fr],
- DBDMA_NOP | BR_ALWAYS,
- virt_to_bus(pb->cap_cmd[fr]));
- eieio();
- }
- tab_cmd_dbdma(pb->last_cmd[fr],
- DBDMA_NOP | BR_ALWAYS,
- virt_to_bus(pb->ch1_cmd));
- eieio();
- pb->prev_last_fr = fr;
- pb->last_fr = -2;
- } else {
-
- IDEBUG("PlanB: active grabbing session detected\n");
-
- if(pb->need_pre_capture[fr]) {
-
- IDEBUG("PlanB: padding pre-capture sequence\n");
-
- tab_cmd_dbdma(pb->last_cmd[pb->last_fr],
- DBDMA_NOP | BR_ALWAYS,
- virt_to_bus(pb->pre_cmd[fr]));
- eieio();
- } else {
- tab_cmd_dbdma(pb->last_cmd[fr], DBDMA_STOP, 0);
- tab_cmd_dbdma(pb->cap_cmd[fr], DBDMA_NOP, 0);
- if(pb->gwidth[pb->last_fr] != pb->gwidth[fr]
- || pb->gheight[pb->last_fr] !=
- pb->gheight[fr]
- || pb->gfmt[pb->last_fr] !=
- pb->gfmt[fr])
- tab_cmd_dbdma((pb->cap_cmd[fr] + 1),
- DBDMA_NOP, 0);
- else
- tab_cmd_dbdma((pb->cap_cmd[fr] + 1),
- DBDMA_NOP | BR_ALWAYS,
- virt_to_bus(pb->cap_cmd[fr] + 16));
- tab_cmd_dbdma(pb->last_cmd[pb->last_fr],
- DBDMA_NOP | BR_ALWAYS,
- virt_to_bus(pb->cap_cmd[fr]));
- eieio();
- }
- pb->last_fr = fr;
- }
- if(!(ACTIVE & in_le32(&pb->planb_base->ch1.status))) {
-
- IDEBUG("PlanB: became inactive in the mean time..."
- "reactivating\n");
-
- planb_dbdma_stop(&pb->planb_base->ch1);
- out_le32 (&pb->planb_base->ch1.cmdptr,
- virt_to_bus(pb->cap_cmd[fr]));
- planb_dbdma_restart(&pb->planb_base->ch1);
- }
- }
- pb->grabbing++;
- planb_unlock(pb);
-
- return 0;
-}
-
-static void planb_pre_capture(int fr, int bpp, struct planb *pb)
-{
- volatile struct dbdma_cmd *c1 = pb->pre_cmd[fr];
- int interlace = (pb->gheight[fr] > pb->maxlines/2)? 1: 0;
-
- tab_cmd_dbdma(c1++, DBDMA_NOP, 0);
- if((c1 = cmd_geo_setup(c1, pb->gwidth[fr], pb->gheight[fr], interlace,
- bpp, 0, pb)) == NULL) {
- printk(KERN_WARNING "PlanB: encountered some problems\n");
- tab_cmd_dbdma(pb->pre_cmd[fr] + 1, DBDMA_STOP, 0);
- return;
- }
- /* Sync to even field */
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.wait_sel),
- PLANB_SET(FIELD_SYNC));
- tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFCLR, 0);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
- PLANB_SET(ODD_FIELD));
- tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFSET, 0);
- tab_cmd_dbdma(c1, DBDMA_NOP | BR_IFSET, virt_to_bus(c1-3)); c1++;
- tab_cmd_dbdma(c1++, DBDMA_NOP | INTR_ALWAYS, 0);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
- PLANB_SET(DMA_ABORT));
- /* For non-interlaced, we use even fields only */
- if (pb->gheight[fr] <= pb->maxlines/2)
- goto cmd_tab_data_end;
- /* Sync to odd field */
- tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFCLR, 0);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
- PLANB_SET(ODD_FIELD));
- tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFSET, 0);
- tab_cmd_dbdma(c1, DBDMA_NOP | BR_IFCLR, virt_to_bus(c1-3)); c1++;
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
- PLANB_SET(DMA_ABORT));
-cmd_tab_data_end:
- tab_cmd_dbdma(c1, DBDMA_NOP | BR_ALWAYS, virt_to_bus(pb->cap_cmd[fr]));
-
- eieio();
-}
-
-static volatile struct dbdma_cmd *setup_grab_cmd(int fr, struct planb *pb)
-{
- int i, bpp, count, nlines, stepsize, interlace;
-#ifdef PLANB_GSCANLINE
- int scanline;
-#else
- int nlpp, leftover1;
- unsigned long base;
-#endif
- unsigned long jump;
- int pagei;
- volatile struct dbdma_cmd *c1;
- volatile struct dbdma_cmd *jump_addr;
-
- c1 = pb->cap_cmd[fr];
- interlace = (pb->gheight[fr] > pb->maxlines/2)? 1: 0;
- bpp = pb->gfmt[fr]; /* gfmt = bpp */
- count = bpp * pb->gwidth[fr];
- nlines = pb->gheight[fr];
-#ifdef PLANB_GSCANLINE
- scanline = pb->gbytes_per_line;
-#else
- pb->lsize[fr] = count;
- pb->lnum[fr] = 0;
-#endif
-
- /* Do video in: */
-
- /* Preamble commands: */
- tab_cmd_dbdma(c1++, DBDMA_NOP, 0);
- tab_cmd_dbdma(c1, DBDMA_NOP | BR_ALWAYS, virt_to_bus(c1 + 16)); c1++;
- if((c1 = cmd_geo_setup(c1, pb->gwidth[fr], pb->gheight[fr], interlace,
- bpp, 0, pb)) == NULL) {
- printk(KERN_WARNING "PlanB: encountered serious problems\n");
- tab_cmd_dbdma(pb->cap_cmd[fr] + 1, DBDMA_STOP, 0);
- return (pb->cap_cmd[fr] + 2);
- }
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.wait_sel),
- PLANB_SET(FIELD_SYNC));
- tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFCLR, 0);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
- PLANB_SET(ODD_FIELD));
- tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFSET, 0);
- tab_cmd_dbdma(c1, DBDMA_NOP | BR_IFSET, virt_to_bus(c1-3)); c1++;
- tab_cmd_dbdma(c1++, DBDMA_NOP | INTR_ALWAYS, 0);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
- PLANB_SET(DMA_ABORT));
-
- if (interlace) {
- stepsize = 2;
- jump_addr = c1 + TAB_FACTOR * (nlines + 1) / 2;
- } else {
- stepsize = 1;
- jump_addr = c1 + TAB_FACTOR * nlines;
- }
- jump = virt_to_bus(jump_addr);
-
- /* even field data: */
-
- pagei = pb->gbuf_idx[fr];
-#ifdef PLANB_GSCANLINE
- for (i = 0; i < nlines; i += stepsize) {
- tab_cmd_gen(c1++, INPUT_MORE | BR_IFSET, count,
- virt_to_bus(pb->rawbuf[pagei
- + i * scanline / PAGE_SIZE]), jump);
- }
-#else
- i = 0;
- leftover1 = 0;
- do {
- int j;
-
- base = virt_to_bus(pb->rawbuf[pagei]);
- nlpp = (PAGE_SIZE - leftover1) / count / stepsize;
- for(j = 0; j < nlpp && i < nlines; j++, i += stepsize, c1++)
- tab_cmd_gen(c1, INPUT_MORE | KEY_STREAM0 | BR_IFSET,
- count, base + count * j * stepsize + leftover1, jump);
- if(i < nlines) {
- int lov0 = PAGE_SIZE - count * nlpp * stepsize - leftover1;
-
- if(lov0 == 0)
- leftover1 = 0;
- else {
- if(lov0 >= count) {
- tab_cmd_gen(c1++, INPUT_MORE | BR_IFSET, count, base
- + count * nlpp * stepsize + leftover1, jump);
- } else {
- pb->l_to_addr[fr][pb->lnum[fr]] = pb->rawbuf[pagei]
- + count * nlpp * stepsize + leftover1;
- pb->l_to_next_idx[fr][pb->lnum[fr]] = pagei + 1;
- pb->l_to_next_size[fr][pb->lnum[fr]] = count - lov0;
- tab_cmd_gen(c1++, INPUT_MORE | BR_IFSET, count,
- virt_to_bus(pb->rawbuf[pb->l_fr_addr_idx[fr]
- + pb->lnum[fr]]), jump);
- if(++pb->lnum[fr] > MAX_LNUM)
- pb->lnum[fr]--;
- }
- leftover1 = count * stepsize - lov0;
- i += stepsize;
- }
- }
- pagei++;
- } while(i < nlines);
- tab_cmd_dbdma(c1, DBDMA_NOP | BR_ALWAYS, jump);
- c1 = jump_addr;
-#endif /* PLANB_GSCANLINE */
-
- /* For non-interlaced, we use even fields only */
- if (!interlace)
- goto cmd_tab_data_end;
-
- /* Sync to odd field */
- tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFCLR, 0);
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
- PLANB_SET(ODD_FIELD));
- tab_cmd_dbdma(c1++, DBDMA_NOP | WAIT_IFSET, 0);
- tab_cmd_dbdma(c1, DBDMA_NOP | BR_IFCLR, virt_to_bus(c1-3)); c1++;
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->ch1.br_sel),
- PLANB_SET(DMA_ABORT));
-
- /* odd field data: */
- jump_addr = c1 + TAB_FACTOR * nlines / 2;
- jump = virt_to_bus(jump_addr);
-#ifdef PLANB_GSCANLINE
- for (i = 1; i < nlines; i += stepsize) {
- tab_cmd_gen(c1++, INPUT_MORE | BR_IFSET, count,
- virt_to_bus(pb->rawbuf[pagei
- + i * scanline / PAGE_SIZE]), jump);
- }
-#else
- i = 1;
- leftover1 = 0;
- pagei = pb->gbuf_idx[fr];
- if(nlines <= 1)
- goto skip;
- do {
- int j;
-
- base = virt_to_bus(pb->rawbuf[pagei]);
- nlpp = (PAGE_SIZE - leftover1) / count / stepsize;
- if(leftover1 >= count) {
- tab_cmd_gen(c1++, INPUT_MORE | KEY_STREAM0 | BR_IFSET, count,
- base + leftover1 - count, jump);
- i += stepsize;
- }
- for(j = 0; j < nlpp && i < nlines; j++, i += stepsize, c1++)
- tab_cmd_gen(c1, INPUT_MORE | KEY_STREAM0 | BR_IFSET, count,
- base + count * (j * stepsize + 1) + leftover1, jump);
- if(i < nlines) {
- int lov0 = PAGE_SIZE - count * nlpp * stepsize - leftover1;
-
- if(lov0 == 0)
- leftover1 = 0;
- else {
- if(lov0 > count) {
- pb->l_to_addr[fr][pb->lnum[fr]] = pb->rawbuf[pagei]
- + count * (nlpp * stepsize + 1) + leftover1;
- pb->l_to_next_idx[fr][pb->lnum[fr]] = pagei + 1;
- pb->l_to_next_size[fr][pb->lnum[fr]] = count * stepsize
- - lov0;
- tab_cmd_gen(c1++, INPUT_MORE | BR_IFSET, count,
- virt_to_bus(pb->rawbuf[pb->l_fr_addr_idx[fr]
- + pb->lnum[fr]]), jump);
- if(++pb->lnum[fr] > MAX_LNUM)
- pb->lnum[fr]--;
- i += stepsize;
- }
- leftover1 = count * stepsize - lov0;
- }
- }
- pagei++;
- } while(i < nlines);
-skip:
- tab_cmd_dbdma(c1, DBDMA_NOP | BR_ALWAYS, jump);
- c1 = jump_addr;
-#endif /* PLANB_GSCANLINE */
-
-cmd_tab_data_end:
- tab_cmd_store(c1++, (unsigned)(&pb->planb_base_phys->intr_stat),
- (fr << 9) | PLANB_FRM_IRQ | PLANB_GEN_IRQ);
- /* stop it */
- tab_cmd_dbdma(c1, DBDMA_STOP, 0);
-
- eieio();
- return c1;
-}
-
-static irqreturn_t planb_irq(int irq, void *dev_id)
-{
- unsigned int stat, astat;
- struct planb *pb = (struct planb *)dev_id;
-
- IDEBUG("PlanB: planb_irq()\n");
-
- /* get/clear interrupt status bits */
- eieio();
- stat = in_le32(&pb->planb_base->intr_stat);
- astat = stat & pb->intr_mask;
- out_le32(&pb->planb_base->intr_stat, PLANB_FRM_IRQ
- & ~astat & stat & ~PLANB_GEN_IRQ);
- IDEBUG("PlanB: stat = %X, astat = %X\n", stat, astat);
-
- if(astat & PLANB_FRM_IRQ) {
- unsigned int fr = stat >> 9;
-#ifndef PLANB_GSCANLINE
- int i;
-#endif
- IDEBUG("PlanB: PLANB_FRM_IRQ\n");
-
- pb->gcount++;
-
- IDEBUG("PlanB: grab %d: fr = %d, gcount = %d\n",
- pb->grabbing, fr, pb->gcount);
-#ifndef PLANB_GSCANLINE
- IDEBUG("PlanB: %d * %d bytes are being copied over\n",
- pb->lnum[fr], pb->lsize[fr]);
- for(i = 0; i < pb->lnum[fr]; i++) {
- int first = pb->lsize[fr] - pb->l_to_next_size[fr][i];
-
- memcpy(pb->l_to_addr[fr][i],
- pb->rawbuf[pb->l_fr_addr_idx[fr] + i],
- first);
- memcpy(pb->rawbuf[pb->l_to_next_idx[fr][i]],
- pb->rawbuf[pb->l_fr_addr_idx[fr] + i] + first,
- pb->l_to_next_size[fr][i]);
- }
-#endif
- pb->frame_stat[fr] = GBUFFER_DONE;
- pb->grabbing--;
- wake_up_interruptible(&pb->capq);
- return IRQ_HANDLED;
- }
- /* incorrect interrupts? */
- pb->intr_mask = PLANB_CLR_IRQ;
- out_le32(&pb->planb_base->intr_stat, PLANB_CLR_IRQ);
- printk(KERN_ERR "PlanB: IRQ lockup, cleared intrrupts"
- " unconditionally\n");
- return IRQ_HANDLED;
-}
-
-/*******************************
- * Device Operations functions *
- *******************************/
-
-static int planb_open(struct video_device *dev, int mode)
-{
- struct planb *pb = (struct planb *)dev;
-
- if (pb->user == 0) {
- int err;
- if((err = planb_prepare_open(pb)) != 0)
- return err;
- }
- pb->user++;
-
- DEBUG("PlanB: device opened\n");
- return 0;
-}
-
-static void planb_close(struct video_device *dev)
-{
- struct planb *pb = (struct planb *)dev;
-
- if(pb->user < 1) /* ??? */
- return;
- planb_lock(pb);
- if (pb->user == 1) {
- if (pb->overlay) {
- planb_dbdma_stop(&pb->planb_base->ch2);
- planb_dbdma_stop(&pb->planb_base->ch1);
- pb->overlay = 0;
- }
- planb_prepare_close(pb);
- }
- pb->user--;
- planb_unlock(pb);
-
- DEBUG("PlanB: device closed\n");
-}
-
-static long planb_read(struct video_device *v, char *buf, unsigned long count,
- int nonblock)
-{
- DEBUG("planb: read request\n");
- return -EINVAL;
-}
-
-static long planb_write(struct video_device *v, const char *buf,
- unsigned long count, int nonblock)
-{
- DEBUG("planb: write request\n");
- return -EINVAL;
-}
-
-static int planb_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
-{
- struct planb *pb=(struct planb *)dev;
-
- switch (cmd)
- {
- case VIDIOCGCAP:
- {
- struct video_capability b;
-
- DEBUG("PlanB: IOCTL VIDIOCGCAP\n");
-
- strcpy (b.name, pb->video_dev.name);
- b.type = VID_TYPE_OVERLAY | VID_TYPE_CLIPPING |
- VID_TYPE_FRAMERAM | VID_TYPE_SCALES |
- VID_TYPE_CAPTURE;
- b.channels = 2; /* composite & svhs */
- b.audios = 0;
- b.maxwidth = PLANB_MAXPIXELS;
- b.maxheight = PLANB_MAXLINES;
- b.minwidth = 32; /* wild guess */
- b.minheight = 32;
- if (copy_to_user(arg,&b,sizeof(b)))
- return -EFAULT;
- return 0;
- }
- case VIDIOCSFBUF:
- {
- struct video_buffer v;
- unsigned short bpp;
- unsigned int fmt;
-
- DEBUG("PlanB: IOCTL VIDIOCSFBUF\n");
-
- if (!capable(CAP_SYS_ADMIN)
- || !capable(CAP_SYS_RAWIO))
- return -EPERM;
- if (copy_from_user(&v, arg,sizeof(v)))
- return -EFAULT;
- planb_lock(pb);
- switch(v.depth) {
- case 8:
- bpp = 1;
- fmt = PLANB_GRAY;
- break;
- case 15:
- case 16:
- bpp = 2;
- fmt = PLANB_COLOUR15;
- break;
- case 24:
- case 32:
- bpp = 4;
- fmt = PLANB_COLOUR32;
- break;
- default:
- planb_unlock(pb);
- return -EINVAL;
- }
- if (bpp * v.width > v.bytesperline) {
- planb_unlock(pb);
- return -EINVAL;
- }
- pb->win.bpp = bpp;
- pb->win.color_fmt = fmt;
- pb->frame_buffer_phys = (unsigned long) v.base;
- pb->win.sheight = v.height;
- pb->win.swidth = v.width;
- pb->picture.depth = pb->win.depth = v.depth;
- pb->win.bpl = pb->win.bpp * pb->win.swidth;
- pb->win.pad = v.bytesperline - pb->win.bpl;
-
- DEBUG("PlanB: Display at %p is %d by %d, bytedepth %d,"
- " bpl %d (+ %d)\n", v.base, v.width,v.height,
- pb->win.bpp, pb->win.bpl, pb->win.pad);
-
- pb->cmd_buff_inited = 0;
- if(pb->overlay) {
- suspend_overlay(pb);
- fill_cmd_buff(pb);
- resume_overlay(pb);
- }
- planb_unlock(pb);
- return 0;
- }
- case VIDIOCGFBUF:
- {
- struct video_buffer v;
-
- DEBUG("PlanB: IOCTL VIDIOCGFBUF\n");
-
- v.base = (void *)pb->frame_buffer_phys;
- v.height = pb->win.sheight;
- v.width = pb->win.swidth;
- v.depth = pb->win.depth;
- v.bytesperline = pb->win.bpl + pb->win.pad;
- if (copy_to_user(arg, &v, sizeof(v)))
- return -EFAULT;
- return 0;
- }
- case VIDIOCCAPTURE:
- {
- int i;
-
- if(copy_from_user(&i, arg, sizeof(i)))
- return -EFAULT;
- if(i==0) {
- DEBUG("PlanB: IOCTL VIDIOCCAPTURE Stop\n");
-
- if (!(pb->overlay))
- return 0;
- planb_lock(pb);
- pb->overlay = 0;
- overlay_stop(pb);
- planb_unlock(pb);
- } else {
- DEBUG("PlanB: IOCTL VIDIOCCAPTURE Start\n");
-
- if (pb->frame_buffer_phys == 0 ||
- pb->win.width == 0 ||
- pb->win.height == 0)
- return -EINVAL;
- if (pb->overlay)
- return 0;
- planb_lock(pb);
- pb->overlay = 1;
- if(!(pb->cmd_buff_inited))
- fill_cmd_buff(pb);
- overlay_start(pb);
- planb_unlock(pb);
- }
- return 0;
- }
- case VIDIOCGCHAN:
- {
- struct video_channel v;
-
- DEBUG("PlanB: IOCTL VIDIOCGCHAN\n");
-
- if(copy_from_user(&v, arg,sizeof(v)))
- return -EFAULT;
- v.flags = 0;
- v.tuners = 0;
- v.type = VIDEO_TYPE_CAMERA;
- v.norm = pb->win.norm;
- switch(v.channel)
- {
- case 0:
- strcpy(v.name,"Composite");
- break;
- case 1:
- strcpy(v.name,"SVHS");
- break;
- default:
- return -EINVAL;
- break;
- }
- if(copy_to_user(arg,&v,sizeof(v)))
- return -EFAULT;
-
- return 0;
- }
- case VIDIOCSCHAN:
- {
- struct video_channel v;
-
- DEBUG("PlanB: IOCTL VIDIOCSCHAN\n");
-
- if(copy_from_user(&v, arg, sizeof(v)))
- return -EFAULT;
-
- if (v.norm != pb->win.norm) {
- int i, maxlines;
-
- switch (v.norm)
- {
- case VIDEO_MODE_PAL:
- case VIDEO_MODE_SECAM:
- maxlines = PLANB_MAXLINES;
- break;
- case VIDEO_MODE_NTSC:
- maxlines = PLANB_NTSC_MAXLINES;
- break;
- default:
- return -EINVAL;
- break;
- }
- planb_lock(pb);
- /* empty the grabbing queue */
- wait_event(pb->capq, !pb->grabbing);
- pb->maxlines = maxlines;
- pb->win.norm = v.norm;
- /* Stop overlay if running */
- suspend_overlay(pb);
- for(i = 0; i < MAX_GBUFFERS; i++)
- pb->gnorm_switch[i] = 1;
- /* I know it's an overkill, but.... */
- fill_cmd_buff(pb);
- /* ok, now init it accordingly */
- saa_init_regs (pb);
- /* restart overlay if it was running */
- resume_overlay(pb);
- planb_unlock(pb);
- }
-
- switch(v.channel)
- {
- case 0: /* Composite */
- saa_set (SAA7196_IOCC,
- ((saa_regs[pb->win.norm][SAA7196_IOCC] &
- ~7) | 3), pb);
- break;
- case 1: /* SVHS */
- saa_set (SAA7196_IOCC,
- ((saa_regs[pb->win.norm][SAA7196_IOCC] &
- ~7) | 4), pb);
- break;
- default:
- return -EINVAL;
- break;
- }
-
- return 0;
- }
- case VIDIOCGPICT:
- {
- struct video_picture vp = pb->picture;
-
- DEBUG("PlanB: IOCTL VIDIOCGPICT\n");
-
- switch(pb->win.color_fmt) {
- case PLANB_GRAY:
- vp.palette = VIDEO_PALETTE_GREY;
- case PLANB_COLOUR15:
- vp.palette = VIDEO_PALETTE_RGB555;
- break;
- case PLANB_COLOUR32:
- vp.palette = VIDEO_PALETTE_RGB32;
- break;
- default:
- vp.palette = 0;
- break;
- }
-
- if(copy_to_user(arg,&vp,sizeof(vp)))
- return -EFAULT;
- return 0;
- }
- case VIDIOCSPICT:
- {
- struct video_picture vp;
-
- DEBUG("PlanB: IOCTL VIDIOCSPICT\n");
-
- if(copy_from_user(&vp,arg,sizeof(vp)))
- return -EFAULT;
- pb->picture = vp;
- /* Should we do sanity checks here? */
- saa_set (SAA7196_BRIG, (unsigned char)
- ((pb->picture.brightness) >> 8), pb);
- saa_set (SAA7196_HUEC, (unsigned char)
- ((pb->picture.hue) >> 8) ^ 0x80, pb);
- saa_set (SAA7196_CSAT, (unsigned char)
- ((pb->picture.colour) >> 9), pb);
- saa_set (SAA7196_CONT, (unsigned char)
- ((pb->picture.contrast) >> 9), pb);
-
- return 0;
- }
- case VIDIOCSWIN:
- {
- struct video_window vw;
- struct video_clip clip;
- int i;
-
- DEBUG("PlanB: IOCTL VIDIOCSWIN\n");
-
- if(copy_from_user(&vw,arg,sizeof(vw)))
- return -EFAULT;
-
- planb_lock(pb);
- /* Stop overlay if running */
- suspend_overlay(pb);
- pb->win.interlace = (vw.height > pb->maxlines/2)? 1: 0;
- if (pb->win.x != vw.x ||
- pb->win.y != vw.y ||
- pb->win.width != vw.width ||
- pb->win.height != vw.height ||
- !pb->cmd_buff_inited) {
- pb->win.x = vw.x;
- pb->win.y = vw.y;
- pb->win.width = vw.width;
- pb->win.height = vw.height;
- fill_cmd_buff(pb);
- }
- /* Reset clip mask */
- memset ((void *) pb->mask, 0xff, (pb->maxlines
- * ((PLANB_MAXPIXELS + 7) & ~7)) / 8);
- /* Add any clip rects */
- for (i = 0; i < vw.clipcount; i++) {
- if (copy_from_user(&clip, vw.clips + i,
- sizeof(struct video_clip)))
- return -EFAULT;
- add_clip(pb, &clip);
- }
- /* restart overlay if it was running */
- resume_overlay(pb);
- planb_unlock(pb);
- return 0;
- }
- case VIDIOCGWIN:
- {
- struct video_window vw;
-
- DEBUG("PlanB: IOCTL VIDIOCGWIN\n");
-
- vw.x=pb->win.x;
- vw.y=pb->win.y;
- vw.width=pb->win.width;
- vw.height=pb->win.height;
- vw.chromakey=0;
- vw.flags=0;
- if(pb->win.interlace)
- vw.flags|=VIDEO_WINDOW_INTERLACE;
- if(copy_to_user(arg,&vw,sizeof(vw)))
- return -EFAULT;
- return 0;
- }
- case VIDIOCSYNC: {
- int i;
-
- IDEBUG("PlanB: IOCTL VIDIOCSYNC\n");
-
- if(copy_from_user((void *)&i,arg,sizeof(int)))
- return -EFAULT;
-
- IDEBUG("PlanB: sync to frame %d\n", i);
-
- if(i > (MAX_GBUFFERS - 1) || i < 0)
- return -EINVAL;
-chk_grab:
- switch (pb->frame_stat[i]) {
- case GBUFFER_UNUSED:
- return -EINVAL;
- case GBUFFER_GRABBING:
- IDEBUG("PlanB: waiting for grab"
- " done (%d)\n", i);
- interruptible_sleep_on(&pb->capq);
- if(signal_pending(current))
- return -EINTR;
- goto chk_grab;
- case GBUFFER_DONE:
- pb->frame_stat[i] = GBUFFER_UNUSED;
- break;
- }
- return 0;
- }
-
- case VIDIOCMCAPTURE:
- {
- struct video_mmap vm;
- volatile unsigned int status;
-
- IDEBUG("PlanB: IOCTL VIDIOCMCAPTURE\n");
-
- if(copy_from_user((void *) &vm,(void *)arg,sizeof(vm)))
- return -EFAULT;
- status = pb->frame_stat[vm.frame];
- if (status != GBUFFER_UNUSED)
- return -EBUSY;
-
- return vgrab(pb, &vm);
- }
-
- case VIDIOCGMBUF:
- {
- int i;
- struct video_mbuf vm;
-
- DEBUG("PlanB: IOCTL VIDIOCGMBUF\n");
-
- memset(&vm, 0 , sizeof(vm));
- vm.size = PLANB_MAX_FBUF * MAX_GBUFFERS;
- vm.frames = MAX_GBUFFERS;
- for(i = 0; i<MAX_GBUFFERS; i++)
- vm.offsets[i] = PLANB_MAX_FBUF * i;
- if(copy_to_user((void *)arg, (void *)&vm, sizeof(vm)))
- return -EFAULT;
- return 0;
- }
-
- case PLANBIOCGSAAREGS:
- {
- struct planb_saa_regs preg;
-
- DEBUG("PlanB: IOCTL PLANBIOCGSAAREGS\n");
-
- if(copy_from_user(&preg, arg, sizeof(preg)))
- return -EFAULT;
- if(preg.addr >= SAA7196_NUMREGS)
- return -EINVAL;
- preg.val = saa_regs[pb->win.norm][preg.addr];
- if(copy_to_user((void *)arg, (void *)&preg,
- sizeof(preg)))
- return -EFAULT;
- return 0;
- }
-
- case PLANBIOCSSAAREGS:
- {
- struct planb_saa_regs preg;
-
- DEBUG("PlanB: IOCTL PLANBIOCSSAAREGS\n");
-
- if(copy_from_user(&preg, arg, sizeof(preg)))
- return -EFAULT;
- if(preg.addr >= SAA7196_NUMREGS)
- return -EINVAL;
- saa_set (preg.addr, preg.val, pb);
- return 0;
- }
-
- case PLANBIOCGSTAT:
- {
- struct planb_stat_regs pstat;
-
- DEBUG("PlanB: IOCTL PLANBIOCGSTAT\n");
-
- pstat.ch1_stat = in_le32(&pb->planb_base->ch1.status);
- pstat.ch2_stat = in_le32(&pb->planb_base->ch2.status);
- pstat.saa_stat0 = saa_status(0, pb);
- pstat.saa_stat1 = saa_status(1, pb);
-
- if(copy_to_user((void *)arg, (void *)&pstat,
- sizeof(pstat)))
- return -EFAULT;
- return 0;
- }
-
- case PLANBIOCSMODE: {
- int v;
-
- DEBUG("PlanB: IOCTL PLANBIOCSMODE\n");
-
- if(copy_from_user(&v, arg, sizeof(v)))
- return -EFAULT;
-
- switch(v)
- {
- case PLANB_TV_MODE:
- saa_set (SAA7196_STDC,
- (saa_regs[pb->win.norm][SAA7196_STDC] &
- 0x7f), pb);
- break;
- case PLANB_VTR_MODE:
- saa_set (SAA7196_STDC,
- (saa_regs[pb->win.norm][SAA7196_STDC] |
- 0x80), pb);
- break;
- default:
- return -EINVAL;
- break;
- }
- pb->win.mode = v;
- return 0;
- }
- case PLANBIOCGMODE: {
- int v=pb->win.mode;
-
- DEBUG("PlanB: IOCTL PLANBIOCGMODE\n");
-
- if(copy_to_user(arg,&v,sizeof(v)))
- return -EFAULT;
- return 0;
- }
-#ifdef PLANB_GSCANLINE
- case PLANBG_GRAB_BPL: {
- int v=pb->gbytes_per_line;
-
- DEBUG("PlanB: IOCTL PLANBG_GRAB_BPL\n");
-
- if(copy_to_user(arg,&v,sizeof(v)))
- return -EFAULT;
- return 0;
- }
-#endif /* PLANB_GSCANLINE */
- case PLANB_INTR_DEBUG: {
- int i;
-
- DEBUG("PlanB: IOCTL PLANB_INTR_DEBUG\n");
-
- if(copy_from_user(&i, arg, sizeof(i)))
- return -EFAULT;
-
- /* avoid hang ups all together */
- for (i = 0; i < MAX_GBUFFERS; i++) {
- if(pb->frame_stat[i] == GBUFFER_GRABBING) {
- pb->frame_stat[i] = GBUFFER_DONE;
- }
- }
- if(pb->grabbing)
- pb->grabbing--;
- wake_up_interruptible(&pb->capq);
- return 0;
- }
- case PLANB_INV_REGS: {
- int i;
- struct planb_any_regs any;
-
- DEBUG("PlanB: IOCTL PLANB_INV_REGS\n");
-
- if(copy_from_user(&any, arg, sizeof(any)))
- return -EFAULT;
- if(any.offset < 0 || any.offset + any.bytes > 0x400)
- return -EINVAL;
- if(any.bytes > 128)
- return -EINVAL;
- for (i = 0; i < any.bytes; i++) {
- any.data[i] =
- in_8((unsigned char *)pb->planb_base
- + any.offset + i);
- }
- if(copy_to_user(arg,&any,sizeof(any)))
- return -EFAULT;
- return 0;
- }
- default:
- {
- DEBUG("PlanB: Unimplemented IOCTL\n");
- return -ENOIOCTLCMD;
- }
- /* Some IOCTLs are currently unsupported on PlanB */
- case VIDIOCGTUNER: {
- DEBUG("PlanB: IOCTL VIDIOCGTUNER\n");
- goto unimplemented; }
- case VIDIOCSTUNER: {
- DEBUG("PlanB: IOCTL VIDIOCSTUNER\n");
- goto unimplemented; }
- case VIDIOCSFREQ: {
- DEBUG("PlanB: IOCTL VIDIOCSFREQ\n");
- goto unimplemented; }
- case VIDIOCGFREQ: {
- DEBUG("PlanB: IOCTL VIDIOCGFREQ\n");
- goto unimplemented; }
- case VIDIOCKEY: {
- DEBUG("PlanB: IOCTL VIDIOCKEY\n");
- goto unimplemented; }
- case VIDIOCSAUDIO: {
- DEBUG("PlanB: IOCTL VIDIOCSAUDIO\n");
- goto unimplemented; }
- case VIDIOCGAUDIO: {
- DEBUG("PlanB: IOCTL VIDIOCGAUDIO\n");
- goto unimplemented; }
-unimplemented:
- DEBUG(" Unimplemented\n");
- return -ENOIOCTLCMD;
- }
- return 0;
-}
-
-static int planb_mmap(struct vm_area_struct *vma, struct video_device *dev, const char *adr, unsigned long size)
-{
- int i;
- struct planb *pb = (struct planb *)dev;
- unsigned long start = (unsigned long)adr;
-
- if (size > MAX_GBUFFERS * PLANB_MAX_FBUF)
- return -EINVAL;
- if (!pb->rawbuf) {
- int err;
- if((err=grabbuf_alloc(pb)))
- return err;
- }
- for (i = 0; i < pb->rawbuf_size; i++) {
- unsigned long pfn;
-
- pfn = virt_to_phys((void *)pb->rawbuf[i]) >> PAGE_SHIFT;
- if (remap_pfn_range(vma, start, pfn, PAGE_SIZE, PAGE_SHARED))
- return -EAGAIN;
- start += PAGE_SIZE;
- if (size <= PAGE_SIZE)
- break;
- size -= PAGE_SIZE;
- }
- return 0;
-}
-
-static struct video_device planb_template=
-{
- .owner = THIS_MODULE,
- .name = PLANB_DEVICE_NAME,
- .type = VID_TYPE_OVERLAY,
- .open = planb_open,
- .close = planb_close,
- .read = planb_read,
- .write = planb_write,
- .ioctl = planb_ioctl,
- .mmap = planb_mmap, /* mmap? */
-};
-
-static int init_planb(struct planb *pb)
-{
- unsigned char saa_rev;
- int i, result;
-
- memset ((void *) &pb->win, 0, sizeof (struct planb_window));
- /* Simple sanity check */
- if(def_norm >= NUM_SUPPORTED_NORM || def_norm < 0) {
- printk(KERN_ERR "PlanB: Option(s) invalid\n");
- return -2;
- }
- pb->win.norm = def_norm;
- pb->win.mode = PLANB_TV_MODE; /* TV mode */
- pb->win.interlace=1;
- pb->win.x=0;
- pb->win.y=0;
- pb->win.width=768; /* 640 */
- pb->win.height=576; /* 480 */
- pb->maxlines=576;
-#if 0
- btv->win.cropwidth=768; /* 640 */
- btv->win.cropheight=576; /* 480 */
- btv->win.cropx=0;
- btv->win.cropy=0;
-#endif
- pb->win.pad=0;
- pb->win.bpp=4;
- pb->win.depth=32;
- pb->win.color_fmt=PLANB_COLOUR32;
- pb->win.bpl=1024*pb->win.bpp;
- pb->win.swidth=1024;
- pb->win.sheight=768;
-#ifdef PLANB_GSCANLINE
- if((pb->gbytes_per_line = PLANB_MAXPIXELS * 4) > PAGE_SIZE
- || (pb->gbytes_per_line <= 0))
- return -3;
- else {
- /* page align pb->gbytes_per_line for DMA purpose */
- for(i = PAGE_SIZE; pb->gbytes_per_line < (i>>1);)
- i>>=1;
- pb->gbytes_per_line = i;
- }
-#endif
- pb->tab_size = PLANB_MAXLINES + 40;
- pb->suspend = 0;
- mutex_init(&pb->lock);
- pb->ch1_cmd = 0;
- pb->ch2_cmd = 0;
- pb->mask = 0;
- pb->priv_space = 0;
- pb->offset = 0;
- pb->user = 0;
- pb->overlay = 0;
- init_waitqueue_head(&pb->suspendq);
- pb->cmd_buff_inited = 0;
- pb->frame_buffer_phys = 0;
-
- /* Reset DMA controllers */
- planb_dbdma_stop(&pb->planb_base->ch2);
- planb_dbdma_stop(&pb->planb_base->ch1);
-
- saa_rev = (saa_status(0, pb) & 0xf0) >> 4;
- printk(KERN_INFO "PlanB: SAA7196 video processor rev. %d\n", saa_rev);
- /* Initialize the SAA registers in memory and on chip */
- saa_init_regs (pb);
-
- /* clear interrupt mask */
- pb->intr_mask = PLANB_CLR_IRQ;
-
- result = request_irq(pb->irq, planb_irq, 0, "PlanB", pb);
- if (result < 0) {
- if (result==-EINVAL)
- printk(KERN_ERR "PlanB: Bad irq number (%d) "
- "or handler\n", (int)pb->irq);
- else if (result==-EBUSY)
- printk(KERN_ERR "PlanB: I don't know why, "
- "but IRQ %d is busy\n", (int)pb->irq);
- return result;
- }
- disable_irq(pb->irq);
-
- /* Now add the template and register the device unit. */
- memcpy(&pb->video_dev,&planb_template,sizeof(planb_template));
-
- pb->picture.brightness=0x90<<8;
- pb->picture.contrast = 0x70 << 8;
- pb->picture.colour = 0x70<<8;
- pb->picture.hue = 0x8000;
- pb->picture.whiteness = 0;
- pb->picture.depth = pb->win.depth;
-
- pb->frame_stat=NULL;
- init_waitqueue_head(&pb->capq);
- for(i=0; i<MAX_GBUFFERS; i++) {
- pb->gbuf_idx[i] = PLANB_MAX_FBUF * i / PAGE_SIZE;
- pb->gwidth[i]=0;
- pb->gheight[i]=0;
- pb->gfmt[i]=0;
- pb->cap_cmd[i]=NULL;
-#ifndef PLANB_GSCANLINE
- pb->l_fr_addr_idx[i] = MAX_GBUFFERS * (PLANB_MAX_FBUF
- / PAGE_SIZE + 1) + MAX_LNUM * i;
- pb->lsize[i] = 0;
- pb->lnum[i] = 0;
-#endif
- }
- pb->rawbuf=NULL;
- pb->grabbing=0;
-
- /* enable interrupts */
- out_le32(&pb->planb_base->intr_stat, PLANB_CLR_IRQ);
- pb->intr_mask = PLANB_FRM_IRQ;
- enable_irq(pb->irq);
-
- if(video_register_device(&pb->video_dev, VFL_TYPE_GRABBER, video_nr)<0)
- return -1;
-
- return 0;
-}
-
-/*
- * Scan for a PlanB controller, request the irq and map the io memory
- */
-
-static int find_planb(void)
-{
- struct planb *pb;
- struct device_node *planb_devices;
- unsigned char dev_fn, confreg, bus;
- unsigned int old_base, new_base;
- unsigned int irq;
- struct pci_dev *pdev;
- int rc;
-
- if (!machine_is(powermac))
- return 0;
-
- planb_devices = of_find_node_by_name(NULL, "planb");
- if (planb_devices == 0) {
- planb_num=0;
- printk(KERN_WARNING "PlanB: no device found!\n");
- return planb_num;
- }
-
- if (planb_devices->next != NULL)
- printk(KERN_ERR "Warning: only using first PlanB device!\n");
- pb = &planbs[0];
- planb_num = 1;
-
- if (planb_devices->n_addrs != 1) {
- printk (KERN_WARNING "PlanB: expecting 1 address for planb "
- "(got %d)", planb_devices->n_addrs);
- of_node_put(planb_devices);
- return 0;
- }
-
- if (planb_devices->n_intrs == 0) {
- printk(KERN_WARNING "PlanB: no intrs for device %s\n",
- planb_devices->full_name);
- of_node_put(planb_devices);
- return 0;
- } else {
- irq = planb_devices->intrs[0].line;
- }
-
- /* Initialize PlanB's PCI registers */
-
- /* There is a bug with the way OF assigns addresses
- to the devices behind the chaos bridge.
- control needs only 0x1000 of space, but decodes only
- the upper 16 bits. It therefore occupies a full 64K.
- OF assigns the planb controller memory within this space;
- so we need to change that here in order to access planb. */
-
- /* We remap to 0xf1000000 in hope that nobody uses it ! */
-
- bus = (planb_devices->addrs[0].space >> 16) & 0xff;
- dev_fn = (planb_devices->addrs[0].space >> 8) & 0xff;
- confreg = planb_devices->addrs[0].space & 0xff;
- old_base = planb_devices->addrs[0].address;
- new_base = 0xf1000000;
- of_node_put(planb_devices);
-
- DEBUG("PlanB: Found on bus %d, dev %d, func %d, "
- "membase 0x%x (base reg. 0x%x)\n",
- bus, PCI_SLOT(dev_fn), PCI_FUNC(dev_fn), old_base, confreg);
-
- pdev = pci_get_bus_and_slot(bus, dev_fn);
- if (!pdev) {
- printk(KERN_ERR "planb: cannot find slot\n");
- goto err_out;
- }
-
- /* Enable response in memory space, bus mastering,
- use memory write and invalidate */
- rc = pci_enable_device(pdev);
- if (rc) {
- printk(KERN_ERR "planb: cannot enable PCI device %s\n",
- pci_name(pdev));
- goto err_out;
- }
- rc = pci_set_mwi(pdev);
- if (rc) {
- printk(KERN_ERR "planb: cannot enable MWI on PCI device %s\n",
- pci_name(pdev));
- goto err_out_disable;
- }
- pci_set_master(pdev);
-
- /* Set the new base address */
- pci_write_config_dword (pdev, confreg, new_base);
-
- planb_regs = (volatile struct planb_registers *)
- ioremap (new_base, 0x400);
- pb->planb_base = planb_regs;
- pb->planb_base_phys = (struct planb_registers *)new_base;
- pb->irq = irq;
- pb->dev = pdev;
-
- return planb_num;
-
-err_out_disable:
- pci_disable_device(pdev);
-err_out:
- /* FIXME handle error */ /* comment moved from pci_find_slot, above */
- pci_dev_put(pdev);
- return 0;
-}
-
-static void release_planb(void)
-{
- int i;
- struct planb *pb;
-
- for (i=0;i<planb_num; i++)
- {
- pb=&planbs[i];
-
- /* stop and flash DMAs unconditionally */
- planb_dbdma_stop(&pb->planb_base->ch2);
- planb_dbdma_stop(&pb->planb_base->ch1);
-
- /* clear and free interrupts */
- pb->intr_mask = PLANB_CLR_IRQ;
- out_le32 (&pb->planb_base->intr_stat, PLANB_CLR_IRQ);
- free_irq(pb->irq, pb);
-
- /* make sure all allocated memory are freed */
- planb_prepare_close(pb);
-
- printk(KERN_INFO "PlanB: unregistering with v4l\n");
- video_unregister_device(&pb->video_dev);
-
- pci_dev_put(pb->dev);
-
- /* note that iounmap() does nothing on the PPC right now */
- iounmap ((void *)pb->planb_base);
- }
-}
-
-static int __init init_planbs(void)
-{
- int i;
-
- if (find_planb()<=0)
- return -EIO;
-
- for (i=0; i<planb_num; i++) {
- if (init_planb(&planbs[i])<0) {
- printk(KERN_ERR "PlanB: error registering device %d"
- " with v4l\n", i);
- release_planb();
- return -EIO;
- }
- printk(KERN_INFO "PlanB: registered device %d with v4l\n", i);
- }
- return 0;
-}
-
-static void __exit exit_planbs(void)
-{
- release_planb();
-}
-
-module_init(init_planbs);
-module_exit(exit_planbs);
-/*
- planb - PlanB frame grabber driver
-
- PlanB is used in the 7x00/8x00 series of PowerMacintosh
- Computers as video input DMA controller.
-
- Copyright (C) 1998 Michel Lanners (mlan@cpu.lu)
-
- Based largely on the bttv driver by Ralph Metzler (rjkm@thp.uni-koeln.de)
-
- Additional debugging and coding by Takashi Oe (toe@unlserve.unl.edu)
-
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-
-/* $Id: planb.h,v 1.13 1999/05/03 19:28:56 mlan Exp $ */
-
-#ifndef _PLANB_H_
-#define _PLANB_H_
-
-#ifdef __KERNEL__
-#include <asm/dbdma.h>
-#include "saa7196.h"
-#endif /* __KERNEL__ */
-
-#define PLANB_DEVICE_NAME "Apple PlanB Video-In"
-#define PLANB_REV "1.0"
-
-#ifdef __KERNEL__
-//#define PLANB_GSCANLINE /* use this if apps have the notion of */
- /* grab buffer scanline */
-/* This should be safe for both PAL and NTSC */
-#define PLANB_MAXPIXELS 768
-#define PLANB_MAXLINES 576
-#define PLANB_NTSC_MAXLINES 480
-
-/* Uncomment your preferred norm ;-) */
-#define PLANB_DEF_NORM VIDEO_MODE_PAL
-//#define PLANB_DEF_NORM VIDEO_MODE_NTSC
-//#define PLANB_DEF_NORM VIDEO_MODE_SECAM
-
-/* fields settings */
-#define PLANB_GRAY 0x1 /* 8-bit mono? */
-#define PLANB_COLOUR15 0x2 /* 16-bit mode */
-#define PLANB_COLOUR32 0x4 /* 32-bit mode */
-#define PLANB_CLIPMASK 0x8 /* hardware clipmasking */
-
-/* misc. flags for PlanB DMA operation */
-#define CH_SYNC 0x1 /* synchronize channels (set by ch1;
- cleared by ch2) */
-#define FIELD_SYNC 0x2 /* used for the start of each field
- (0 -> 1 -> 0 for ch1; 0 -> 1 for ch2) */
-#define EVEN_FIELD 0x0 /* even field is detected if unset */
-#define DMA_ABORT 0x2 /* error or just out of sync if set */
-#define ODD_FIELD 0x4 /* odd field is detected if set */
-
-/* for capture operations */
-#define MAX_GBUFFERS 2
-/* note PLANB_MAX_FBUF must be divisible by PAGE_SIZE */
-#ifdef PLANB_GSCANLINE
-#define PLANB_MAX_FBUF 0x240000 /* 576 * 1024 * 4 */
-#define TAB_FACTOR (1)
-#else
-#define PLANB_MAX_FBUF 0x1b0000 /* 576 * 768 * 4 */
-#define TAB_FACTOR (2)
-#endif
-#endif /* __KERNEL__ */
-
-struct planb_saa_regs {
- unsigned char addr;
- unsigned char val;
-};
-
-struct planb_stat_regs {
- unsigned int ch1_stat;
- unsigned int ch2_stat;
- unsigned char saa_stat0;
- unsigned char saa_stat1;
-};
-
-struct planb_any_regs {
- unsigned int offset;
- unsigned int bytes;
- unsigned char data[128];
-};
-
-/* planb private ioctls */
-#define PLANBIOCGSAAREGS _IOWR('v', BASE_VIDIOCPRIVATE, struct planb_saa_regs) /* Read a saa7196 reg value */
-#define PLANBIOCSSAAREGS _IOW('v', BASE_VIDIOCPRIVATE + 1, struct planb_saa_regs) /* Set a saa7196 reg value */
-#define PLANBIOCGSTAT _IOR('v', BASE_VIDIOCPRIVATE + 2, struct planb_stat_regs) /* Read planb status */
-#define PLANB_TV_MODE 1
-#define PLANB_VTR_MODE 2
-#define PLANBIOCGMODE _IOR('v', BASE_VIDIOCPRIVATE + 3, int) /* Get TV/VTR mode */
-#define PLANBIOCSMODE _IOW('v', BASE_VIDIOCPRIVATE + 4, int) /* Set TV/VTR mode */
-
-#ifdef PLANB_GSCANLINE
-#define PLANBG_GRAB_BPL _IOR('v', BASE_VIDIOCPRIVATE + 5, int) /* # of bytes per scanline in grab buffer */
-#endif
-
-/* call wake_up_interruptible() with appropriate actions */
-#define PLANB_INTR_DEBUG _IOW('v', BASE_VIDIOCPRIVATE + 20, int)
-/* investigate which reg does what */
-#define PLANB_INV_REGS _IOWR('v', BASE_VIDIOCPRIVATE + 21, struct planb_any_regs)
-
-#ifdef __KERNEL__
-
-/* Potentially useful macros */
-#define PLANB_SET(x) ((x) << 16 | (x))
-#define PLANB_CLR(x) ((x) << 16)
-
-/* This represents the physical register layout */
-struct planb_registers {
- volatile struct dbdma_regs ch1; /* 0x00: video in */
- volatile unsigned int even; /* 0x40: even field setting */
- volatile unsigned int odd; /* 0x44; odd field setting */
- unsigned int pad1[14]; /* empty? */
- volatile struct dbdma_regs ch2; /* 0x80: clipmask out */
- unsigned int pad2[16]; /* 0xc0: empty? */
- volatile unsigned int reg3; /* 0x100: ???? */
- volatile unsigned int intr_stat; /* 0x104: irq status */
-#define PLANB_CLR_IRQ 0x00 /* clear Plan B interrupt */
-#define PLANB_GEN_IRQ 0x01 /* assert Plan B interrupt */
-#define PLANB_FRM_IRQ 0x0100 /* end of frame */
- unsigned int pad3[1]; /* empty? */
- volatile unsigned int reg5; /* 0x10c: ??? */
- unsigned int pad4[60]; /* empty? */
- volatile unsigned char saa_addr; /* 0x200: SAA subadr */
- char pad5[3];
- volatile unsigned char saa_regval; /* SAA7196 write reg. val */
- char pad6[3];
- volatile unsigned char saa_status; /* SAA7196 status byte */
- /* There is more unused stuff here */
-};
-
-struct planb_window {
- int x, y;
- ushort width, height;
- ushort bpp, bpl, depth, pad;
- ushort swidth, sheight;
- int norm;
- int interlace;
- u32 color_fmt;
- int chromakey;
- int mode; /* used to switch between TV/VTR modes */
-};
-
-struct planb_suspend {
- int overlay;
- int frame;
- struct dbdma_cmd cmd;
-};
-
-struct planb {
- struct video_device video_dev;
- struct video_picture picture; /* Current picture params */
- struct video_audio audio_dev; /* Current audio params */
-
- volatile struct planb_registers *planb_base; /* virt base of planb */
- struct planb_registers *planb_base_phys; /* phys base of planb */
- void *priv_space; /* Org. alloc. mem for kfree */
- int user;
- unsigned int tab_size;
- int maxlines;
- struct mutex lock;
- unsigned int irq; /* interrupt number */
- volatile unsigned int intr_mask;
- struct pci_dev *dev; /* Our PCI device */
-
- int overlay; /* overlay running? */
- struct planb_window win;
- unsigned long frame_buffer_phys; /* We need phys for DMA */
- int offset; /* offset of pixel 1 */
- volatile struct dbdma_cmd *ch1_cmd; /* Video In DMA cmd buffer */
- volatile struct dbdma_cmd *ch2_cmd; /* Clip Out DMA cmd buffer */
- volatile struct dbdma_cmd *overlay_last1;
- volatile struct dbdma_cmd *overlay_last2;
- unsigned long ch1_cmd_phys;
- volatile unsigned char *mask; /* Clipmask buffer */
- int suspend;
- wait_queue_head_t suspendq;
- struct planb_suspend suspended;
- int cmd_buff_inited; /* cmd buffer inited? */
-
- int grabbing;
- unsigned int gcount;
- wait_queue_head_t capq;
- int last_fr;
- int prev_last_fr;
- unsigned char **rawbuf;
- int rawbuf_size;
- int gbuf_idx[MAX_GBUFFERS];
- volatile struct dbdma_cmd *cap_cmd[MAX_GBUFFERS];
- volatile struct dbdma_cmd *last_cmd[MAX_GBUFFERS];
- volatile struct dbdma_cmd *pre_cmd[MAX_GBUFFERS];
- int need_pre_capture[MAX_GBUFFERS];
-#define PLANB_DUMMY 40 /* # of command buf's allocated for pre-capture seq. */
- int gwidth[MAX_GBUFFERS], gheight[MAX_GBUFFERS];
- unsigned int gfmt[MAX_GBUFFERS];
- int gnorm_switch[MAX_GBUFFERS];
- volatile unsigned int *frame_stat;
-#define GBUFFER_UNUSED 0x00U
-#define GBUFFER_GRABBING 0x01U
-#define GBUFFER_DONE 0x02U
-#ifdef PLANB_GSCANLINE
- int gbytes_per_line;
-#else
-#define MAX_LNUM 431 /* change this if PLANB_MAXLINES or */
- /* PLANB_MAXPIXELS changes */
- int l_fr_addr_idx[MAX_GBUFFERS];
- unsigned char *l_to_addr[MAX_GBUFFERS][MAX_LNUM];
- int l_to_next_idx[MAX_GBUFFERS][MAX_LNUM];
- int l_to_next_size[MAX_GBUFFERS][MAX_LNUM];
- int lsize[MAX_GBUFFERS], lnum[MAX_GBUFFERS];
-#endif
-};
-
-#endif /* __KERNEL__ */
-
-#endif /* _PLANB_H_ */
#include <asm/io.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/mutex.h>
#include <asm/uaccess.h>
static struct video_device pms_template=
{
- .owner = THIS_MODULE,
.name = "Mediavision PMS",
- .type = VID_TYPE_CAPTURE,
.fops = &pms_fops,
};
tristate "Hauppauge WinTV-PVR USB2 support"
depends on VIDEO_V4L2 && I2C
depends on VIDEO_MEDIA # Avoids pvrusb = Y / DVB = M
- depends on HOTPLUG # due to FW_LOADER
- select FW_LOADER
select VIDEO_TUNER
select VIDEO_TVEEPROM
select VIDEO_CX2341X
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
-#ifndef __PVRUSB2_BASE_H
-#define __PVRUSB2_BASE_H
+#ifndef __PVRUSB2_CONTEXT_H
+#define __PVRUSB2_CONTEXT_H
#include <linux/mutex.h>
#include <linux/usb.h>
.flag_has_cx25840 = !0,
.flag_has_wm8775 = !0,
.flag_has_hauppauge_rom = !0,
- .flag_has_hauppauge_custom_ir = !0,
.flag_has_analogtuner = !0,
.flag_has_fmradio = !0,
.flag_has_composite = !0,
.flag_has_svideo = !0,
.signal_routing_scheme = PVR2_ROUTING_SCHEME_HAUPPAUGE,
.led_scheme = PVR2_LED_SCHEME_HAUPPAUGE,
+ .ir_scheme = PVR2_IR_SCHEME_24XXX,
};
};
static const struct pvr2_device_desc pvr2_device_73xxx = {
- .description = "WinTV PVR USB2 Model Category 73xxx",
+ .description = "WinTV HVR-1900 Model Category 73xxx",
.shortname = "73xxx",
.client_modules.lst = pvr2_client_73xxx,
.client_modules.cnt = ARRAY_SIZE(pvr2_client_73xxx),
.signal_routing_scheme = PVR2_ROUTING_SCHEME_HAUPPAUGE,
.digital_control_scheme = PVR2_DIGITAL_SCHEME_HAUPPAUGE,
.led_scheme = PVR2_LED_SCHEME_HAUPPAUGE,
+ .ir_scheme = PVR2_IR_SCHEME_ZILOG,
#ifdef CONFIG_VIDEO_PVRUSB2_DVB
.dvb_props = &pvr2_73xxx_dvb_props,
#endif
};
static const struct pvr2_device_desc pvr2_device_750xx = {
- .description = "WinTV PVR USB2 Model Category 750xx",
+ .description = "WinTV HVR-1950 Model Category 750xx",
.shortname = "750xx",
.client_modules.lst = pvr2_client_75xxx,
.client_modules.cnt = ARRAY_SIZE(pvr2_client_75xxx),
.digital_control_scheme = PVR2_DIGITAL_SCHEME_HAUPPAUGE,
.default_std_mask = V4L2_STD_NTSC_M,
.led_scheme = PVR2_LED_SCHEME_HAUPPAUGE,
+ .ir_scheme = PVR2_IR_SCHEME_ZILOG,
#ifdef CONFIG_VIDEO_PVRUSB2_DVB
.dvb_props = &pvr2_750xx_dvb_props,
#endif
};
static const struct pvr2_device_desc pvr2_device_751xx = {
- .description = "WinTV PVR USB2 Model Category 751xx",
+ .description = "WinTV HVR-1950 Model Category 751xx",
.shortname = "751xx",
.client_modules.lst = pvr2_client_75xxx,
.client_modules.cnt = ARRAY_SIZE(pvr2_client_75xxx),
.digital_control_scheme = PVR2_DIGITAL_SCHEME_HAUPPAUGE,
.default_std_mask = V4L2_STD_NTSC_M,
.led_scheme = PVR2_LED_SCHEME_HAUPPAUGE,
+ .ir_scheme = PVR2_IR_SCHEME_ZILOG,
#ifdef CONFIG_VIDEO_PVRUSB2_DVB
.dvb_props = &pvr2_751xx_dvb_props,
#endif
#define PVR2_LED_SCHEME_NONE 0
#define PVR2_LED_SCHEME_HAUPPAUGE 1
+#define PVR2_IR_SCHEME_NONE 0
+#define PVR2_IR_SCHEME_24XXX 1
+#define PVR2_IR_SCHEME_ZILOG 2
+
/* This describes a particular hardware type (except for the USB device ID
which must live in a separate structure due to environmental
constraints). See the top of pvrusb2-hdw.c for where this is
ensure that it is found. */
unsigned int flag_has_wm8775:1;
- /* Device has IR hardware that can be faked into looking like a
- normal Hauppauge i2c IR receiver. This is currently very
- specific to the 24xxx device, where Hauppauge had replaced their
- 'standard' I2C IR receiver with a bunch of FPGA logic controlled
- directly via the FX2. Turning this on tells the pvrusb2 driver
- to virtualize the presence of the non-existant IR receiver chip and
- implement the virtual receiver in terms of appropriate FX2
- commands. */
- unsigned int flag_has_hauppauge_custom_ir:1;
+ /* Indicate any specialized IR scheme that might need to be
+ supported by this driver. If not set, then it is assumed that
+ IR can work without help from the driver (which is frequently
+ the case). This is otherwise set to one of
+ PVR2_IR_SCHEME_xxxx. For "xxxx", the value "24XXX" indicates a
+ Hauppauge 24xxx class device which has an FPGA-hosted IR
+ receiver that can only be reached via FX2 command codes. In
+ that case the pvrusb2 driver will emulate the behavior of the
+ older 29xxx device's IR receiver (a "virtual" I2C chip) in terms
+ of those command codes. For the value "ZILOG", we're dealing
+ with an IR chip that must be taken out of reset via another FX2
+ command code (which is the case for HVR-1950 devices). */
+ unsigned int ir_scheme:2;
/* These bits define which kinds of sources the device can handle.
Note: Digital tuner presence is inferred by the
#define FX2CMD_MEM_WRITE_DWORD 0x01u
#define FX2CMD_MEM_READ_DWORD 0x02u
+#define FX2CMD_HCW_ZILOG_RESET 0x10u /* 1=reset 0=release */
+
#define FX2CMD_MEM_READ_64BYTES 0x28u
#define FX2CMD_REG_WRITE 0x04u
static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
{FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
{FX2CMD_MEM_READ_DWORD, "read encoder dword"},
+ {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
{FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
{FX2CMD_REG_WRITE, "write encoder register"},
{FX2CMD_REG_READ, "read encoder register"},
if (!pvr2_hdw_dev_ok(hdw)) return;
}
+ /* Take the IR chip out of reset, if appropriate */
+ if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
+ pvr2_issue_simple_cmd(hdw,
+ FX2CMD_HCW_ZILOG_RESET |
+ (1 << 8) |
+ ((0) << 16));
+ }
+
// This step MUST happen after the earlier powerup step.
pvr2_i2c_core_init(hdw);
if (!pvr2_hdw_dev_ok(hdw)) return;
printk(KERN_INFO "%s: IR disabled\n",hdw->name);
hdw->i2c_func[0x18] = i2c_black_hole;
} else if (ir_mode[hdw->unit_number] == 1) {
- if (hdw->hdw_desc->flag_has_hauppauge_custom_ir) {
+ if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_24XXX) {
+ /* This comment is present PURELY to get
+ checkpatch.pl to STFU. Lovely, eh? */
hdw->i2c_func[0x18] = i2c_24xxx_ir;
}
}
#include <linux/videodev2.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
struct pvr2_v4l2_dev;
struct pvr2_v4l2_fh;
static struct video_device vdev_template = {
- .owner = THIS_MODULE,
- .type = VID_TYPE_CAPTURE | VID_TYPE_TUNER,
- .type2 = (V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VBI_CAPTURE
- | V4L2_CAP_TUNER | V4L2_CAP_AUDIO
- | V4L2_CAP_READWRITE),
.fops = &vdev_fops,
};
.llseek = no_llseek,
};
static struct video_device pwc_template = {
- .owner = THIS_MODULE,
.name = "Philips Webcam", /* Filled in later */
- .type = VID_TYPE_CAPTURE,
.release = video_device_release,
.fops = &pwc_fops,
.minor = -1,
struct pwc_device *pdev = video_get_drvdata(vdev);
int rc;
- rc = video_device_create_file(vdev, &dev_attr_button);
+ rc = device_create_file(&vdev->dev, &dev_attr_button);
if (rc)
goto err;
if (pdev->features & FEATURE_MOTOR_PANTILT) {
- rc = video_device_create_file(vdev, &dev_attr_pan_tilt);
+ rc = device_create_file(&vdev->dev, &dev_attr_pan_tilt);
if (rc) goto err_button;
}
return 0;
err_button:
- video_device_remove_file(vdev, &dev_attr_button);
+ device_remove_file(&vdev->dev, &dev_attr_button);
err:
+ PWC_ERROR("Could not create sysfs files.\n");
return rc;
}
{
struct pwc_device *pdev = video_get_drvdata(vdev);
if (pdev->features & FEATURE_MOTOR_PANTILT)
- video_device_remove_file(vdev, &dev_attr_pan_tilt);
- video_device_remove_file(vdev, &dev_attr_button);
+ device_remove_file(&vdev->dev, &dev_attr_pan_tilt);
+ device_remove_file(&vdev->dev, &dev_attr_button);
}
#ifdef CONFIG_USB_PWC_DEBUG
return -ENOMEM;
}
memcpy(pdev->vdev, &pwc_template, sizeof(pwc_template));
- pdev->vdev->dev = &(udev->dev);
+ pdev->vdev->parent = &(udev->dev);
strcpy(pdev->vdev->name, name);
- pdev->vdev->owner = THIS_MODULE;
video_set_drvdata(pdev->vdev, pdev);
pdev->release = le16_to_cpu(udev->descriptor.bcdDevice);
#include <linux/smp_lock.h>
#include <linux/version.h>
#include <linux/mutex.h>
+#include <linux/mm.h>
#include <asm/errno.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include "pwc-uncompress.h"
#include <media/pwc-ioctl.h>
#include <linux/mutex.h>
#include <linux/videodev2.h>
#include <linux/version.h>
+#include <linux/mm.h>
#include <media/videobuf-vmalloc.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/vmalloc.h>
#include <linux/usb.h>
#define S2255_FW_LOADED_DSPWAIT 1
#define S2255_FW_SUCCESS 2
#define S2255_FW_FAILED 3
+#define S2255_FW_DISCONNECTING 4
struct s2255_fw {
int fw_loaded;
struct s2255_fh {
struct s2255_dev *dev;
- unsigned int resources;
const struct s2255_fmt *fmt;
unsigned int width;
unsigned int height;
/* mode below is the desired mode.
mode in s2255_dev is the current mode that was last set */
struct s2255_mode mode;
+ int resources[MAX_CHANNELS];
};
-/*
- * TODO: fixme S2255_MAX_USERS. Do not limit open driver handles.
- * Limit V4L to one stream at a time.
- */
-#define S2255_MAX_USERS 1
-
#define CUR_USB_FWVER 774 /* current cypress EEPROM firmware version */
#define S2255_MAJOR_VERSION 1
#define S2255_MINOR_VERSION 13
dprintk(100, "s2255 timer\n");
if (usb_submit_urb(data->fw_urb, GFP_ATOMIC) < 0) {
printk(KERN_ERR "s2255: can't submit urb\n");
- if (data->fw) {
- release_firmware(data->fw);
- data->fw = NULL;
- }
+ atomic_set(&data->fw_state, S2255_FW_FAILED);
+ /* wake up anything waiting for the firmware */
+ wake_up(&data->wait_fw);
return;
}
}
struct usb_device *udev = urb->dev;
int len;
dprintk(100, "udev %p urb %p", udev, urb);
- /* TODO: fixme. reflect change in status */
if (urb->status) {
dev_err(&udev->dev, "URB failed with status %d", urb->status);
+ atomic_set(&data->fw_state, S2255_FW_FAILED);
+ /* wake up anything waiting for the firmware */
+ wake_up(&data->wait_fw);
return;
}
if (data->fw_urb == NULL) {
- dev_err(&udev->dev, "early disconncect\n");
+ dev_err(&udev->dev, "s2255 disconnected\n");
+ atomic_set(&data->fw_state, S2255_FW_FAILED);
+ /* wake up anything waiting for the firmware */
+ wake_up(&data->wait_fw);
return;
}
#define CHUNK_SIZE 512
}
/* it's free, grab it */
dev->resources[fh->channel] = 1;
- dprintk(1, "res: get\n");
+ fh->resources[fh->channel] = 1;
+ dprintk(1, "s2255: res: get\n");
mutex_unlock(&dev->lock);
return 1;
}
return dev->resources[fh->channel];
}
+static int res_check(struct s2255_fh *fh)
+{
+ return fh->resources[fh->channel];
+}
+
+
static void res_free(struct s2255_dev *dev, struct s2255_fh *fh)
{
+ mutex_lock(&dev->lock);
dev->resources[fh->channel] = 0;
+ fh->resources[fh->channel] = 0;
+ mutex_unlock(&dev->lock);
dprintk(1, "res: put\n");
}
}
if (!res_get(dev, fh)) {
- dev_err(&dev->udev->dev, "res get busy\n");
+ dev_err(&dev->udev->dev, "s2255: stream busy\n");
return -EBUSY;
}
}
s2255_stop_acquire(dev, fh->channel);
res = videobuf_streamoff(&fh->vb_vidq);
+ if (res < 0)
+ return res;
res_free(dev, fh);
- return res;
+ return 0;
}
static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *i)
mutex_lock(&dev->open_lock);
dev->users[cur_channel]++;
- if (dev->users[cur_channel] > S2255_MAX_USERS) {
- dev->users[cur_channel]--;
- mutex_unlock(&dev->open_lock);
- printk(KERN_INFO "s2255drv: too many open handles!\n");
- return -EBUSY;
- }
+ dprintk(4, "s2255: open_handles %d\n", dev->users[cur_channel]);
if (atomic_read(&dev->fw_data->fw_state) == S2255_FW_FAILED) {
err("2255 firmware load failed. retrying.\n");
msecs_to_jiffies(S2255_LOAD_TIMEOUT));
if (atomic_read(&dev->fw_data->fw_state)
!= S2255_FW_SUCCESS) {
- printk(KERN_INFO "2255 FW load failed after 2 tries\n");
+ printk(KERN_INFO "2255 FW load failed.\n");
+ dev->users[cur_channel]--;
mutex_unlock(&dev->open_lock);
return -EFAULT;
}
!= S2255_FW_SUCCESS) {
printk(KERN_INFO "2255 firmware not loaded"
"try again\n");
+ dev->users[cur_channel]--;
mutex_unlock(&dev->open_lock);
return -EBUSY;
}
/* allocate + initialize per filehandle data */
fh = kzalloc(sizeof(*fh), GFP_KERNEL);
if (NULL == fh) {
+ dev->users[cur_channel]--;
mutex_unlock(&dev->open_lock);
return -ENOMEM;
}
printk(KERN_ERR "s2255drv: kref problem\n");
return;
}
+
+ /*
+ * Wake up any firmware load waiting (only done in .open,
+ * which holds the open_lock mutex)
+ */
+ atomic_set(&dev->fw_data->fw_state, S2255_FW_DISCONNECTING);
+ wake_up(&dev->fw_data->wait_fw);
+
/* prevent s2255_disconnect from racing s2255_open */
mutex_lock(&dev->open_lock);
s2255_exit_v4l(dev);
- /* device unregistered so no longer possible to open. open_mutex
- can be unlocked */
+ /*
+ * device unregistered so no longer possible to open. open_mutex
+ * can be unlocked and timers deleted afterwards.
+ */
mutex_unlock(&dev->open_lock);
/* board shutdown stops the read pipe if it is running */
s2255_board_shutdown(dev);
/* make sure firmware still not trying to load */
+ del_timer(&dev->timer); /* only started in .probe and .open */
+
if (dev->fw_data->fw_urb) {
dprintk(2, "kill fw_urb\n");
usb_kill_urb(dev->fw_data->fw_urb);
usb_free_urb(dev->fw_data->fw_urb);
dev->fw_data->fw_urb = NULL;
}
+
/*
- * TODO: fixme(above, below): potentially leaving timers alive.
- * do not ignore timeout below if
- * it occurs.
+ * delete the dsp_wait timer, which sets the firmware
+ * state on completion. This is done before fw_data
+ * is freed below.
*/
- /* make sure we aren't waiting for the DSP */
- if (atomic_read(&dev->fw_data->fw_state) == S2255_FW_LOADED_DSPWAIT) {
- /* if we are, wait for the wakeup for fw_success or timeout */
- wait_event_timeout(dev->fw_data->wait_fw,
- (atomic_read(&dev->fw_data->fw_state)
- == S2255_FW_SUCCESS),
- msecs_to_jiffies(S2255_LOAD_TIMEOUT));
- }
+ del_timer(&dev->fw_data->dsp_wait); /* only started in .open */
- if (dev->fw_data) {
- if (dev->fw_data->fw)
- release_firmware(dev->fw_data->fw);
- kfree(dev->fw_data->pfw_data);
- kfree(dev->fw_data);
- }
+ if (dev->fw_data->fw)
+ release_firmware(dev->fw_data->fw);
+ kfree(dev->fw_data->pfw_data);
+ kfree(dev->fw_data);
usb_put_dev(dev->udev);
dprintk(1, "%s", __func__);
mutex_lock(&dev->open_lock);
- if (dev->b_acquire[fh->channel])
- s2255_stop_acquire(dev, fh->channel);
- res_free(dev, fh);
+ /* turn off stream */
+ if (res_check(fh)) {
+ if (dev->b_acquire[fh->channel])
+ s2255_stop_acquire(dev, fh->channel);
+ videobuf_streamoff(&fh->vb_vidq);
+ res_free(dev, fh);
+ }
+
videobuf_mmap_free(&fh->vb_vidq);
- kfree(fh);
dev->users[fh->channel]--;
+
mutex_unlock(&dev->open_lock);
kref_put(&dev->kref, s2255_destroy);
dprintk(1, "s2255: close called (minor=%d, users=%d)\n",
minor, dev->users[fh->channel]);
+ kfree(fh);
return 0;
}
.llseek = no_llseek,
};
-static struct video_device template = {
- .name = "s2255v",
- .type = VID_TYPE_CAPTURE,
- .fops = &s2255_fops_v4l,
- .minor = -1,
- .release = video_device_release,
+static const struct v4l2_ioctl_ops s2255_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
#ifdef CONFIG_VIDEO_V4L1_COMPAT
.vidiocgmbuf = vidioc_cgmbuf,
#endif
+};
+
+static struct video_device template = {
+ .name = "s2255v",
+ .fops = &s2255_fops_v4l,
+ .ioctl_ops = &s2255_ioctl_ops,
+ .minor = -1,
+ .release = video_device_release,
.tvnorms = S2255_NORMS,
.current_norm = V4L2_STD_NTSC_M,
};
/* register 4 video devices */
dev->vdev[i] = video_device_alloc();
memcpy(dev->vdev[i], &template, sizeof(struct video_device));
- dev->vdev[i]->dev = &dev->interface->dev;
+ dev->vdev[i]->parent = &dev->interface->dev;
if (video_nr == -1)
ret = video_register_device(dev->vdev[i],
VFL_TYPE_GRABBER,
#include <linux/videotext.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/mutex.h>
#include "saa5246a.h"
static struct video_device saa_template =
{
- .owner = THIS_MODULE,
.name = IF_NAME,
- .type = VID_TYPE_TELETEXT,
.fops = &saa_fops,
.release = video_device_release,
.minor = -1,
#include <linux/videotext.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/mutex.h>
static struct video_device saa_template =
{
- .owner = THIS_MODULE,
.name = IF_NAME,
- .type = VID_TYPE_TELETEXT, /*| VID_TYPE_TUNER ?? */
.fops = &saa_fops,
};
config VIDEO_SAA7134_DVB
tristate "DVB/ATSC Support for saa7134 based TV cards"
depends on VIDEO_SAA7134 && DVB_CORE
- depends on HOTPLUG # due to FW_LOADER
select VIDEOBUF_DVB
- select FW_LOADER
select DVB_PLL if !DVB_FE_CUSTOMISE
select DVB_MT352 if !DVB_FE_CUSTOMISE
select DVB_TDA1004X if !DVB_FE_CUSTOMISE
unsigned char buf;
int board;
- dev->tuner_type = saa7134_boards[dev->board].tuner_type;
- dev->tuner_addr = saa7134_boards[dev->board].tuner_addr;
-
switch (dev->board) {
case SAA7134_BOARD_BMK_MPEX_NOTUNER:
case SAA7134_BOARD_BMK_MPEX_TUNER:
return NULL;
*vfd = *template;
vfd->minor = -1;
- vfd->dev = &dev->pci->dev;
+ vfd->parent = &dev->pci->dev;
vfd->release = video_device_release;
vfd->debug = video_debug;
snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)",
dev->board = SAA7134_BOARD_UNKNOWN;
}
dev->autodetected = card[dev->nr] != dev->board;
- dev->tuner_type = saa7134_boards[dev->board].tuner_type;
+ dev->tuner_type = saa7134_boards[dev->board].tuner_type;
+ dev->tuner_addr = saa7134_boards[dev->board].tuner_addr;
dev->tda9887_conf = saa7134_boards[dev->board].tda9887_conf;
if (UNSET != tuner[dev->nr])
dev->tuner_type = tuner[dev->nr];
- printk(KERN_INFO "%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
+ printk(KERN_INFO "%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
dev->name,pci_dev->subsystem_vendor,
pci_dev->subsystem_device,saa7134_boards[dev->board].name,
dev->board, dev->autodetected ?
v4l2_prio_init(&dev->prio);
/* register v4l devices */
- if (saa7134_no_overlay <= 0) {
- saa7134_video_template.type |= VID_TYPE_OVERLAY;
- } else {
- printk("%s: Overlay support disabled.\n",dev->name);
- }
+ if (saa7134_no_overlay > 0)
+ printk(KERN_INFO "%s: Overlay support disabled.\n", dev->name);
+
dev->video_dev = vdev_init(dev,&saa7134_video_template,"video");
err = video_register_device(dev->video_dev,VFL_TYPE_GRABBER,
video_nr[dev->nr]);
dev->name,dev->video_dev->minor & 0x1f);
dev->vbi_dev = vdev_init(dev, &saa7134_video_template, "vbi");
- dev->vbi_dev->type = VID_TYPE_TUNER | VID_TYPE_TELETEXT;
err = video_register_device(dev->vbi_dev,VFL_TYPE_VBI,
vbi_nr[dev->nr]);
err = -EBUSY;
if (!mutex_trylock(&dev->empress_tsq.vb_lock))
goto done;
- if (dev->empress_users)
+ if (atomic_read(&dev->empress_users))
goto done_up;
/* Unmute audio */
saa_writeb(SAA7134_AUDIO_MUTE_CTRL,
saa_readb(SAA7134_AUDIO_MUTE_CTRL) & ~(1 << 6));
- dev->empress_users++;
+ atomic_inc(&dev->empress_users);
file->private_data = dev;
err = 0;
{
struct saa7134_dev *dev = file->private_data;
- mutex_lock(&dev->empress_tsq.vb_lock);
-
videobuf_stop(&dev->empress_tsq);
videobuf_mmap_free(&dev->empress_tsq);
saa_writeb(SAA7134_AUDIO_MUTE_CTRL,
saa_readb(SAA7134_AUDIO_MUTE_CTRL) | (1 << 6));
- dev->empress_users--;
-
- mutex_unlock(&dev->empress_tsq.vb_lock);
+ atomic_dec(&dev->empress_users);
return 0;
}
return saa7134_i2c_call_saa6752(dev, VIDIOC_G_EXT_CTRLS, ctrls);
}
+static int empress_g_ctrl(struct file *file, void *priv,
+ struct v4l2_control *c)
+{
+ struct saa7134_dev *dev = file->private_data;
+
+ return saa7134_g_ctrl_internal(dev, NULL, c);
+}
+
+static int empress_s_ctrl(struct file *file, void *priv,
+ struct v4l2_control *c)
+{
+ struct saa7134_dev *dev = file->private_data;
+
+ return saa7134_s_ctrl_internal(dev, NULL, c);
+}
+
static int empress_queryctrl(struct file *file, void *priv,
struct v4l2_queryctrl *c)
{
.llseek = no_llseek,
};
-/* ----------------------------------------------------------- */
-
-static struct video_device saa7134_empress_template =
-{
- .name = "saa7134-empress",
- .type = 0 /* FIXME */,
- .type2 = 0 /* FIXME */,
- .fops = &ts_fops,
- .minor = -1,
-
+static const struct v4l2_ioctl_ops ts_ioctl_ops = {
.vidioc_querycap = empress_querycap,
.vidioc_enum_fmt_vid_cap = empress_enum_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = empress_s_fmt_vid_cap,
.vidioc_queryctrl = empress_queryctrl,
.vidioc_querymenu = empress_querymenu,
- .vidioc_g_ctrl = saa7134_g_ctrl,
- .vidioc_s_ctrl = saa7134_s_ctrl,
+ .vidioc_g_ctrl = empress_g_ctrl,
+ .vidioc_s_ctrl = empress_s_ctrl,
+};
+
+/* ----------------------------------------------------------- */
+
+static struct video_device saa7134_empress_template = {
+ .name = "saa7134-empress",
+ .fops = &ts_fops,
+ .minor = -1,
+ .ioctl_ops = &ts_ioctl_ops,
.tvnorms = SAA7134_NORMS,
.current_norm = V4L2_STD_PAL,
ts_reset_encoder(dev);
} else {
dprintk("video signal acquired\n");
- if (dev->empress_users)
+ if (atomic_read(&dev->empress_users))
ts_init_encoder(dev);
}
}
if (NULL == dev->empress_dev)
return -ENOMEM;
*(dev->empress_dev) = saa7134_empress_template;
- dev->empress_dev->dev = &dev->pci->dev;
+ dev->empress_dev->parent = &dev->pci->dev;
dev->empress_dev->release = video_device_release;
snprintf(dev->empress_dev->name, sizeof(dev->empress_dev->name),
"%s empress (%s)", dev->name,
/* ------------------------------------------------------------------ */
-int saa7134_g_ctrl(struct file *file, void *priv, struct v4l2_control *c)
+int saa7134_g_ctrl_internal(struct saa7134_dev *dev, struct saa7134_fh *fh, struct v4l2_control *c)
{
- struct saa7134_fh *fh = priv;
- struct saa7134_dev *dev = fh->dev;
const struct v4l2_queryctrl* ctrl;
ctrl = ctrl_by_id(c->id);
}
return 0;
}
-EXPORT_SYMBOL_GPL(saa7134_g_ctrl);
+EXPORT_SYMBOL_GPL(saa7134_g_ctrl_internal);
+
+static int saa7134_g_ctrl(struct file *file, void *priv, struct v4l2_control *c)
+{
+ struct saa7134_fh *fh = priv;
+
+ return saa7134_g_ctrl_internal(fh->dev, fh, c);
+}
-int saa7134_s_ctrl(struct file *file, void *f, struct v4l2_control *c)
+int saa7134_s_ctrl_internal(struct saa7134_dev *dev, struct saa7134_fh *fh, struct v4l2_control *c)
{
const struct v4l2_queryctrl* ctrl;
- struct saa7134_fh *fh = f;
- struct saa7134_dev *dev = fh->dev;
unsigned long flags;
int restart_overlay = 0;
- int err = -EINVAL;
+ int err;
- err = v4l2_prio_check(&dev->prio, &fh->prio);
- if (0 != err)
- return err;
+ /* When called from the empress code fh == NULL.
+ That needs to be fixed somehow, but for now this is
+ good enough. */
+ if (fh) {
+ err = v4l2_prio_check(&dev->prio, &fh->prio);
+ if (0 != err)
+ return err;
+ }
+ err = -EINVAL;
mutex_lock(&dev->lock);
mutex_unlock(&dev->lock);
return err;
}
-EXPORT_SYMBOL_GPL(saa7134_s_ctrl);
+EXPORT_SYMBOL_GPL(saa7134_s_ctrl_internal);
+
+static int saa7134_s_ctrl(struct file *file, void *f, struct v4l2_control *c)
+{
+ struct saa7134_fh *fh = f;
+
+ return saa7134_s_ctrl_internal(fh->dev, fh, c);
+}
/* ------------------------------------------------------------------ */
.llseek = no_llseek,
};
-static const struct file_operations radio_fops =
-{
- .owner = THIS_MODULE,
- .open = video_open,
- .release = video_release,
- .ioctl = video_ioctl2,
- .compat_ioctl = v4l_compat_ioctl32,
- .llseek = no_llseek,
-};
-
-/* ----------------------------------------------------------- */
-/* exported stuff */
-
-struct video_device saa7134_video_template =
-{
- .name = "saa7134-video",
- .type = VID_TYPE_CAPTURE|VID_TYPE_TUNER |
- VID_TYPE_CLIPPING|VID_TYPE_SCALES,
- .fops = &video_fops,
- .minor = -1,
+static const struct v4l2_ioctl_ops video_ioctl_ops = {
.vidioc_querycap = saa7134_querycap,
.vidioc_enum_fmt_vid_cap = saa7134_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = saa7134_g_fmt_vid_cap,
.vidioc_g_register = vidioc_g_register,
.vidioc_s_register = vidioc_s_register,
#endif
- .tvnorms = SAA7134_NORMS,
- .current_norm = V4L2_STD_PAL,
};
-struct video_device saa7134_radio_template =
-{
- .name = "saa7134-radio",
- .type = VID_TYPE_TUNER,
- .fops = &radio_fops,
- .minor = -1,
+static const struct file_operations radio_fops = {
+ .owner = THIS_MODULE,
+ .open = video_open,
+ .release = video_release,
+ .ioctl = video_ioctl2,
+ .compat_ioctl = v4l_compat_ioctl32,
+ .llseek = no_llseek,
+};
+
+static const struct v4l2_ioctl_ops radio_ioctl_ops = {
.vidioc_querycap = radio_querycap,
.vidioc_g_tuner = radio_g_tuner,
.vidioc_enum_input = radio_enum_input,
.vidioc_s_frequency = saa7134_s_frequency,
};
+/* ----------------------------------------------------------- */
+/* exported stuff */
+
+struct video_device saa7134_video_template = {
+ .name = "saa7134-video",
+ .fops = &video_fops,
+ .ioctl_ops = &video_ioctl_ops,
+ .minor = -1,
+ .tvnorms = SAA7134_NORMS,
+ .current_norm = V4L2_STD_PAL,
+};
+
+struct video_device saa7134_radio_template = {
+ .name = "saa7134-radio",
+ .fops = &radio_fops,
+ .ioctl_ops = &radio_ioctl_ops,
+ .minor = -1,
+};
+
int saa7134_video_init1(struct saa7134_dev *dev)
{
/* sanitycheck insmod options */
#include <asm/io.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/tuner.h>
#include <media/ir-common.h>
#include <media/ir-kbd-i2c.h>
/* SAA7134_MPEG_EMPRESS only */
struct video_device *empress_dev;
struct videobuf_queue empress_tsq;
- unsigned int empress_users;
+ atomic_t empress_users;
struct work_struct empress_workqueue;
int empress_started;
extern struct video_device saa7134_video_template;
extern struct video_device saa7134_radio_template;
-int saa7134_g_ctrl(struct file *file, void *priv, struct v4l2_control *c);
-int saa7134_s_ctrl(struct file *file, void *f, struct v4l2_control *c);
+int saa7134_s_ctrl_internal(struct saa7134_dev *dev, struct saa7134_fh *fh, struct v4l2_control *c);
+int saa7134_g_ctrl_internal(struct saa7134_dev *dev, struct saa7134_fh *fh, struct v4l2_control *c);
int saa7134_queryctrl(struct file *file, void *priv, struct v4l2_queryctrl *c);
int saa7134_videoport_init(struct saa7134_dev *dev);
#include <linux/kernel.h>
#include <linux/sched.h>
-#include <linux/videodev.h>
#include <linux/videodev2.h>
#include <linux/i2c.h>
#include <media/v4l2-common.h>
-/*
- Definitions for the Philips SAA7196 digital video decoder,
- scaler, and clock generator circuit (DESCpro), as used in
- the PlanB video input of the Powermac 7x00/8x00 series.
-
- Copyright (C) 1998 Michel Lanners (mlan@cpu.lu)
-
- The register defines are shamelessly copied from the meteor
- driver out of NetBSD (with permission),
- and are copyrighted (c) 1995 Mark Tinguely and Jim Lowe
- (Thanks !)
-
- Additional debugging and coding by Takashi Oe (toe@unlinfo.unl.edu)
-
- The default values used for PlanB are my mistakes.
-*/
-
-/* $Id: saa7196.h,v 1.5 1999/03/26 23:28:47 mlan Exp $ */
-
-#ifndef _SAA7196_H_
-#define _SAA7196_H_
-
-#define SAA7196_NUMREGS 0x31 /* Number of registers (used)*/
-#define NUM_SUPPORTED_NORM 3 /* Number of supported norms by PlanB */
-
-/* Decoder part: */
-#define SAA7196_IDEL 0x00 /* Increment delay */
-#define SAA7196_HSB5 0x01 /* H-sync begin; 50 hz */
-#define SAA7196_HSS5 0x02 /* H-sync stop; 50 hz */
-#define SAA7196_HCB5 0x03 /* H-clamp begin; 50 hz */
-#define SAA7196_HCS5 0x04 /* H-clamp stop; 50 hz */
-#define SAA7196_HSP5 0x05 /* H-sync after PHI1; 50 hz */
-#define SAA7196_LUMC 0x06 /* Luminance control */
-#define SAA7196_HUEC 0x07 /* Hue control */
-#define SAA7196_CKTQ 0x08 /* Colour Killer Threshold QAM (PAL, NTSC) */
-#define SAA7196_CKTS 0x09 /* Colour Killer Threshold SECAM */
-#define SAA7196_PALS 0x0a /* PAL switch sensitivity */
-#define SAA7196_SECAMS 0x0b /* SECAM switch sensitivity */
-#define SAA7196_CGAINC 0x0c /* Chroma gain control */
-#define SAA7196_STDC 0x0d /* Standard/Mode control */
-#define SAA7196_IOCC 0x0e /* I/O and Clock Control */
-#define SAA7196_CTRL1 0x0f /* Control #1 */
-#define SAA7196_CTRL2 0x10 /* Control #2 */
-#define SAA7196_CGAINR 0x11 /* Chroma Gain Reference */
-#define SAA7196_CSAT 0x12 /* Chroma Saturation */
-#define SAA7196_CONT 0x13 /* Luminance Contrast */
-#define SAA7196_HSB6 0x14 /* H-sync begin; 60 hz */
-#define SAA7196_HSS6 0x15 /* H-sync stop; 60 hz */
-#define SAA7196_HCB6 0x16 /* H-clamp begin; 60 hz */
-#define SAA7196_HCS6 0x17 /* H-clamp stop; 60 hz */
-#define SAA7196_HSP6 0x18 /* H-sync after PHI1; 60 hz */
-#define SAA7196_BRIG 0x19 /* Luminance Brightness */
-
-/* Scaler part: */
-#define SAA7196_FMTS 0x20 /* Formats and sequence */
-#define SAA7196_OUTPIX 0x21 /* Output data pixel/line */
-#define SAA7196_INPIX 0x22 /* Input data pixel/line */
-#define SAA7196_HWS 0x23 /* Horiz. window start */
-#define SAA7196_HFILT 0x24 /* Horiz. filter */
-#define SAA7196_OUTLINE 0x25 /* Output data lines/field */
-#define SAA7196_INLINE 0x26 /* Input data lines/field */
-#define SAA7196_VWS 0x27 /* Vertical window start */
-#define SAA7196_VYP 0x28 /* AFS/vertical Y processing */
-#define SAA7196_VBS 0x29 /* Vertical Bypass start */
-#define SAA7196_VBCNT 0x2a /* Vertical Bypass count */
-#define SAA7196_VBP 0x2b /* veritcal Bypass Polarity */
-#define SAA7196_VLOW 0x2c /* Colour-keying lower V limit */
-#define SAA7196_VHIGH 0x2d /* Colour-keying upper V limit */
-#define SAA7196_ULOW 0x2e /* Colour-keying lower U limit */
-#define SAA7196_UHIGH 0x2f /* Colour-keying upper U limit */
-#define SAA7196_DPATH 0x30 /* Data path setting */
-
-/* Initialization default values: */
-
-unsigned char saa_regs[NUM_SUPPORTED_NORM][SAA7196_NUMREGS] = {
-
-/* PAL, 768x576 (no scaling), composite video-in */
-/* Decoder: */
- { 0x50, 0x30, 0x00, 0xe8, 0xb6, 0xe5, 0x63, 0xff,
- 0xfe, 0xf0, 0xfe, 0xe0, 0x20, 0x06, 0x3b, 0x98,
- 0x00, 0x59, 0x41, 0x45, 0x34, 0x0a, 0xf4, 0xd2,
- 0xe9, 0xa2,
-/* Padding */
- 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-/* Scaler: */
- 0x72, 0x80, 0x00, 0x03, 0x8d, 0x20, 0x20, 0x12,
- 0xa5, 0x12, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00,
- 0x87 },
-
-/* NTSC, 640x480? (no scaling), composite video-in */
-/* Decoder: */
- { 0x50, 0x30, 0x00, 0xe8, 0xb6, 0xe5, 0x50, 0x00,
- 0xf8, 0xf0, 0xfe, 0xe0, 0x00, 0x06, 0x3b, 0x98,
- 0x00, 0x2c, 0x3d, 0x40, 0x34, 0x0a, 0xf4, 0xd2,
- 0xe9, 0x98,
-/* Padding */
- 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-/* Scaler: */
- 0x72, 0x80, 0x80, 0x03, 0x89, 0xf0, 0xf0, 0x0d,
- 0xa0, 0x0d, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00,
- 0x87 },
-
-/* SECAM, 768x576 (no scaling), composite video-in */
-/* Decoder: */
- { 0x50, 0x30, 0x00, 0xe8, 0xb6, 0xe5, 0x63, 0xff,
- 0xfe, 0xf0, 0xfe, 0xe0, 0x20, 0x07, 0x3b, 0x98,
- 0x00, 0x59, 0x41, 0x45, 0x34, 0x0a, 0xf4, 0xd2,
- 0xe9, 0xa2,
-/* Padding */
- 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-/* Scaler: */
- 0x72, 0x80, 0x00, 0x03, 0x8d, 0x20, 0x20, 0x12,
- 0xa5, 0x12, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00,
- 0x87 }
- };
-
-#endif /* _SAA7196_H_ */
.llseek = no_llseek,
};
static struct video_device se401_template = {
- .owner = THIS_MODULE,
.name = "se401 USB camera",
- .type = VID_TYPE_CAPTURE,
.fops = &se401_fops,
};
#include <asm/uaccess.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/mutex.h>
#define se401_DEBUG /* Turn on debug messages */
void __iomem *base;
unsigned long video_limit;
+ /* lock used to protect videobuf */
spinlock_t lock;
struct list_head capture;
struct videobuf_buffer *active;
#include <linux/usb.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/spinlock.h>
if (mutex_lock_interruptible(&sn9c102_sysfs_lock))
return -ERESTARTSYS;
- cam = video_get_drvdata(container_of(cd, struct video_device,
- class_dev));
+ cam = video_get_drvdata(container_of(cd, struct video_device, dev));
if (!cam) {
mutex_unlock(&sn9c102_sysfs_lock);
return -ENODEV;
if (mutex_lock_interruptible(&sn9c102_sysfs_lock))
return -ERESTARTSYS;
- cam = video_get_drvdata(container_of(cd, struct video_device,
- class_dev));
+ cam = video_get_drvdata(container_of(cd, struct video_device, dev));
if (!cam) {
mutex_unlock(&sn9c102_sysfs_lock);
return -ENODEV;
if (mutex_lock_interruptible(&sn9c102_sysfs_lock))
return -ERESTARTSYS;
- cam = video_get_drvdata(container_of(cd, struct video_device,
- class_dev));
+ cam = video_get_drvdata(container_of(cd, struct video_device, dev));
if (!cam) {
mutex_unlock(&sn9c102_sysfs_lock);
return -ENODEV;
if (mutex_lock_interruptible(&sn9c102_sysfs_lock))
return -ERESTARTSYS;
- cam = video_get_drvdata(container_of(cd, struct video_device,
- class_dev));
+ cam = video_get_drvdata(container_of(cd, struct video_device, dev));
if (!cam) {
mutex_unlock(&sn9c102_sysfs_lock);
return -ENODEV;
if (mutex_lock_interruptible(&sn9c102_sysfs_lock))
return -ERESTARTSYS;
- cam = video_get_drvdata(container_of(cd, struct video_device,
- class_dev));
+ cam = video_get_drvdata(container_of(cd, struct video_device, dev));
if (!cam) {
mutex_unlock(&sn9c102_sysfs_lock);
return -ENODEV;
if (mutex_lock_interruptible(&sn9c102_sysfs_lock))
return -ERESTARTSYS;
- cam = video_get_drvdata(container_of(cd, struct video_device,
- class_dev));
+ cam = video_get_drvdata(container_of(cd, struct video_device, dev));
if (!cam) {
mutex_unlock(&sn9c102_sysfs_lock);
return -ENODEV;
if (mutex_lock_interruptible(&sn9c102_sysfs_lock))
return -ERESTARTSYS;
- cam = video_get_drvdata(container_of(cd, struct video_device,
- class_dev));
+ cam = video_get_drvdata(container_of(cd, struct video_device, dev));
if (!cam) {
mutex_unlock(&sn9c102_sysfs_lock);
return -ENODEV;
if (mutex_lock_interruptible(&sn9c102_sysfs_lock))
return -ERESTARTSYS;
- cam = video_get_drvdata(container_of(cd, struct video_device,
- class_dev));
+ cam = video_get_drvdata(container_of(cd, struct video_device, dev));
if (!cam) {
mutex_unlock(&sn9c102_sysfs_lock);
return -ENODEV;
if (mutex_lock_interruptible(&sn9c102_sysfs_lock))
return -ERESTARTSYS;
- cam = video_get_drvdata(container_of(cd, struct video_device,
- class_dev));
+ cam = video_get_drvdata(container_of(cd, struct video_device, dev));
if (!cam) {
mutex_unlock(&sn9c102_sysfs_lock);
return -ENODEV;
struct sn9c102_device* cam;
ssize_t count;
- cam = video_get_drvdata(container_of(cd, struct video_device,
- class_dev));
+ cam = video_get_drvdata(container_of(cd, struct video_device, dev));
if (!cam)
return -ENODEV;
static int sn9c102_create_sysfs(struct sn9c102_device* cam)
{
- struct device *classdev = &(cam->v4ldev->class_dev);
+ struct device *dev = &(cam->v4ldev->dev);
int err = 0;
- if ((err = device_create_file(classdev, &dev_attr_reg)))
+ if ((err = device_create_file(dev, &dev_attr_reg)))
goto err_out;
- if ((err = device_create_file(classdev, &dev_attr_val)))
+ if ((err = device_create_file(dev, &dev_attr_val)))
goto err_reg;
- if ((err = device_create_file(classdev, &dev_attr_frame_header)))
+ if ((err = device_create_file(dev, &dev_attr_frame_header)))
goto err_val;
if (cam->sensor.sysfs_ops) {
- if ((err = device_create_file(classdev, &dev_attr_i2c_reg)))
+ if ((err = device_create_file(dev, &dev_attr_i2c_reg)))
goto err_frame_header;
- if ((err = device_create_file(classdev, &dev_attr_i2c_val)))
+ if ((err = device_create_file(dev, &dev_attr_i2c_val)))
goto err_i2c_reg;
}
if (cam->bridge == BRIDGE_SN9C101 || cam->bridge == BRIDGE_SN9C102) {
- if ((err = device_create_file(classdev, &dev_attr_green)))
+ if ((err = device_create_file(dev, &dev_attr_green)))
goto err_i2c_val;
} else {
- if ((err = device_create_file(classdev, &dev_attr_blue)))
+ if ((err = device_create_file(dev, &dev_attr_blue)))
goto err_i2c_val;
- if ((err = device_create_file(classdev, &dev_attr_red)))
+ if ((err = device_create_file(dev, &dev_attr_red)))
goto err_blue;
}
return 0;
err_blue:
- device_remove_file(classdev, &dev_attr_blue);
+ device_remove_file(dev, &dev_attr_blue);
err_i2c_val:
if (cam->sensor.sysfs_ops)
- device_remove_file(classdev, &dev_attr_i2c_val);
+ device_remove_file(dev, &dev_attr_i2c_val);
err_i2c_reg:
if (cam->sensor.sysfs_ops)
- device_remove_file(classdev, &dev_attr_i2c_reg);
+ device_remove_file(dev, &dev_attr_i2c_reg);
err_frame_header:
- device_remove_file(classdev, &dev_attr_frame_header);
+ device_remove_file(dev, &dev_attr_frame_header);
err_val:
- device_remove_file(classdev, &dev_attr_val);
+ device_remove_file(dev, &dev_attr_val);
err_reg:
- device_remove_file(classdev, &dev_attr_reg);
+ device_remove_file(dev, &dev_attr_reg);
err_out:
return err;
}
}
strcpy(cam->v4ldev->name, "SN9C1xx PC Camera");
- cam->v4ldev->owner = THIS_MODULE;
- cam->v4ldev->type = VID_TYPE_CAPTURE | VID_TYPE_SCALES;
cam->v4ldev->fops = &sn9c102_fops;
cam->v4ldev->minor = video_nr[dev_nr];
cam->v4ldev->release = video_device_release;
#include <linux/vmalloc.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/v4l2-dev.h>
#include <media/videobuf-core.h>
#include <media/soc_camera.h>
mutex_lock(&video_lock);
vdev = video_devdata(file);
- icd = container_of(vdev->dev, struct soc_camera_device, dev);
+ icd = container_of(vdev->parent, struct soc_camera_device, dev);
ici = to_soc_camera_host(icd->dev.parent);
if (!try_module_get(icd->ops->owner)) {
vfree(icf);
- dev_dbg(vdev->dev, "camera device close\n");
+ dev_dbg(vdev->parent, "camera device close\n");
return 0;
}
struct video_device *vdev = icd->vdev;
int err = -EINVAL;
- dev_err(vdev->dev, "camera device read not implemented\n");
+ dev_err(vdev->parent, "camera device read not implemented\n");
return err;
}
}
EXPORT_SYMBOL(soc_camera_device_unregister);
+static const struct v4l2_ioctl_ops soc_camera_ioctl_ops = {
+ .vidioc_querycap = soc_camera_querycap,
+ .vidioc_g_fmt_vid_cap = soc_camera_g_fmt_vid_cap,
+ .vidioc_enum_fmt_vid_cap = soc_camera_enum_fmt_vid_cap,
+ .vidioc_s_fmt_vid_cap = soc_camera_s_fmt_vid_cap,
+ .vidioc_enum_input = soc_camera_enum_input,
+ .vidioc_g_input = soc_camera_g_input,
+ .vidioc_s_input = soc_camera_s_input,
+ .vidioc_s_std = soc_camera_s_std,
+ .vidioc_reqbufs = soc_camera_reqbufs,
+ .vidioc_try_fmt_vid_cap = soc_camera_try_fmt_vid_cap,
+ .vidioc_querybuf = soc_camera_querybuf,
+ .vidioc_qbuf = soc_camera_qbuf,
+ .vidioc_dqbuf = soc_camera_dqbuf,
+ .vidioc_streamon = soc_camera_streamon,
+ .vidioc_streamoff = soc_camera_streamoff,
+ .vidioc_queryctrl = soc_camera_queryctrl,
+ .vidioc_g_ctrl = soc_camera_g_ctrl,
+ .vidioc_s_ctrl = soc_camera_s_ctrl,
+ .vidioc_cropcap = soc_camera_cropcap,
+ .vidioc_g_crop = soc_camera_g_crop,
+ .vidioc_s_crop = soc_camera_s_crop,
+ .vidioc_g_chip_ident = soc_camera_g_chip_ident,
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+ .vidioc_g_register = soc_camera_g_register,
+ .vidioc_s_register = soc_camera_s_register,
+#endif
+};
+
int soc_camera_video_start(struct soc_camera_device *icd)
{
struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
strlcpy(vdev->name, ici->drv_name, sizeof(vdev->name));
/* Maybe better &ici->dev */
- vdev->dev = &icd->dev;
- vdev->type = VID_TYPE_CAPTURE;
+ vdev->parent = &icd->dev;
vdev->current_norm = V4L2_STD_UNKNOWN;
vdev->fops = &soc_camera_fops;
+ vdev->ioctl_ops = &soc_camera_ioctl_ops;
vdev->release = video_device_release;
vdev->minor = -1;
vdev->tvnorms = V4L2_STD_UNKNOWN,
- vdev->vidioc_querycap = soc_camera_querycap;
- vdev->vidioc_g_fmt_vid_cap = soc_camera_g_fmt_vid_cap;
- vdev->vidioc_enum_fmt_vid_cap = soc_camera_enum_fmt_vid_cap;
- vdev->vidioc_s_fmt_vid_cap = soc_camera_s_fmt_vid_cap;
- vdev->vidioc_enum_input = soc_camera_enum_input;
- vdev->vidioc_g_input = soc_camera_g_input;
- vdev->vidioc_s_input = soc_camera_s_input;
- vdev->vidioc_s_std = soc_camera_s_std;
- vdev->vidioc_reqbufs = soc_camera_reqbufs;
- vdev->vidioc_try_fmt_vid_cap = soc_camera_try_fmt_vid_cap;
- vdev->vidioc_querybuf = soc_camera_querybuf;
- vdev->vidioc_qbuf = soc_camera_qbuf;
- vdev->vidioc_dqbuf = soc_camera_dqbuf;
- vdev->vidioc_streamon = soc_camera_streamon;
- vdev->vidioc_streamoff = soc_camera_streamoff;
- vdev->vidioc_queryctrl = soc_camera_queryctrl;
- vdev->vidioc_g_ctrl = soc_camera_g_ctrl;
- vdev->vidioc_s_ctrl = soc_camera_s_ctrl;
- vdev->vidioc_cropcap = soc_camera_cropcap;
- vdev->vidioc_g_crop = soc_camera_g_crop;
- vdev->vidioc_s_crop = soc_camera_s_crop;
- vdev->vidioc_g_chip_ident = soc_camera_g_chip_ident;
-#ifdef CONFIG_VIDEO_ADV_DEBUG
- vdev->vidioc_g_register = soc_camera_g_register;
- vdev->vidioc_s_register = soc_camera_s_register;
-#endif
icd->current_fmt = &icd->formats[0];
err = video_register_device(vdev, VFL_TYPE_GRABBER, vdev->minor);
if (err < 0) {
- dev_err(vdev->dev, "video_register_device failed\n");
+ dev_err(vdev->parent, "video_register_device failed\n");
goto evidregd;
}
icd->vdev = vdev;
#include <linux/vmalloc.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include "stk-webcam.h"
{
int ret;
- ret = video_device_create_file(vdev, &dev_attr_brightness);
- ret += video_device_create_file(vdev, &dev_attr_hflip);
- ret += video_device_create_file(vdev, &dev_attr_vflip);
+ ret = device_create_file(&vdev->dev, &dev_attr_brightness);
+ ret += device_create_file(&vdev->dev, &dev_attr_hflip);
+ ret += device_create_file(&vdev->dev, &dev_attr_vflip);
+ if (ret)
+ STK_WARNING("Could not create sysfs files\n");
return ret;
}
static void stk_remove_sysfs_files(struct video_device *vdev)
{
- video_device_remove_file(vdev, &dev_attr_brightness);
- video_device_remove_file(vdev, &dev_attr_hflip);
- video_device_remove_file(vdev, &dev_attr_vflip);
+ device_remove_file(&vdev->dev, &dev_attr_brightness);
+ device_remove_file(&vdev->dev, &dev_attr_hflip);
+ device_remove_file(&vdev->dev, &dev_attr_vflip);
}
#else
fb->v4lbuf.bytesused = 0;
fill = fb->buffer;
} else if (fb->v4lbuf.bytesused == dev->frame_size) {
- list_move_tail(dev->sio_avail.next,
- &dev->sio_full);
- wake_up(&dev->wait_frame);
- if (list_empty(&dev->sio_avail)) {
- (void) (printk_ratelimit() &&
- STK_ERROR("No buffer available\n"));
- goto resubmit;
+ if (list_is_singular(&dev->sio_avail)) {
+ /* Always reuse the last buffer */
+ fb->v4lbuf.bytesused = 0;
+ fill = fb->buffer;
+ } else {
+ list_move_tail(dev->sio_avail.next,
+ &dev->sio_full);
+ wake_up(&dev->wait_frame);
+ fb = list_first_entry(&dev->sio_avail,
+ struct stk_sio_buffer, list);
+ fb->v4lbuf.bytesused = 0;
+ fill = fb->buffer;
}
- fb = list_first_entry(&dev->sio_avail,
- struct stk_sio_buffer, list);
- fb->v4lbuf.bytesused = 0;
- fill = fb->buffer;
}
} else {
framelen -= 4;
.llseek = no_llseek
};
-static void stk_v4l_dev_release(struct video_device *vd)
-{
-}
-
-static struct video_device stk_v4l_data = {
- .name = "stkwebcam",
- .type = VFL_TYPE_GRABBER,
- .type2 = VID_TYPE_CAPTURE,
- .minor = -1,
- .tvnorms = V4L2_STD_UNKNOWN,
- .current_norm = V4L2_STD_UNKNOWN,
- .fops = &v4l_stk_fops,
- .release = stk_v4l_dev_release,
-
+static const struct v4l2_ioctl_ops v4l_stk_ioctl_ops = {
.vidioc_querycap = stk_vidioc_querycap,
.vidioc_enum_fmt_vid_cap = stk_vidioc_enum_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = stk_vidioc_try_fmt_vid_cap,
.vidioc_g_parm = stk_vidioc_g_parm,
};
+static void stk_v4l_dev_release(struct video_device *vd)
+{
+}
+
+static struct video_device stk_v4l_data = {
+ .name = "stkwebcam",
+ .minor = -1,
+ .tvnorms = V4L2_STD_UNKNOWN,
+ .current_norm = V4L2_STD_UNKNOWN,
+ .fops = &v4l_stk_fops,
+ .ioctl_ops = &v4l_stk_ioctl_ops,
+ .release = stk_v4l_dev_release,
+};
+
static int stk_register_video_device(struct stk_camera *dev)
{
dev->vdev = stk_v4l_data;
dev->vdev.debug = debug;
- dev->vdev.dev = &dev->interface->dev;
+ dev->vdev.parent = &dev->interface->dev;
dev->vdev.priv = dev;
err = video_register_device(&dev->vdev, VFL_TYPE_GRABBER, -1);
if (err)
#include <linux/vmalloc.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include "saa7146.h"
#include "saa7146reg.h"
/* template for video_device-structure */
static struct video_device saa_template = {
.name = "SAA7146A",
- .type = VID_TYPE_CAPTURE | VID_TYPE_OVERLAY,
.fops = &saa_fops,
.minor = -1,
};
#include <linux/errno.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/usb.h>
#include <linux/mutex.h>
{
int rc;
- rc = video_device_create_file(vdev, &dev_attr_model);
+ rc = device_create_file(&vdev->dev, &dev_attr_model);
if (rc) goto err;
- rc = video_device_create_file(vdev, &dev_attr_in_use);
+ rc = device_create_file(&vdev->dev, &dev_attr_in_use);
if (rc) goto err_model;
- rc = video_device_create_file(vdev, &dev_attr_streaming);
+ rc = device_create_file(&vdev->dev, &dev_attr_streaming);
if (rc) goto err_inuse;
- rc = video_device_create_file(vdev, &dev_attr_palette);
+ rc = device_create_file(&vdev->dev, &dev_attr_palette);
if (rc) goto err_stream;
- rc = video_device_create_file(vdev, &dev_attr_frames_total);
+ rc = device_create_file(&vdev->dev, &dev_attr_frames_total);
if (rc) goto err_pal;
- rc = video_device_create_file(vdev, &dev_attr_frames_read);
+ rc = device_create_file(&vdev->dev, &dev_attr_frames_read);
if (rc) goto err_framtot;
- rc = video_device_create_file(vdev, &dev_attr_packets_dropped);
+ rc = device_create_file(&vdev->dev, &dev_attr_packets_dropped);
if (rc) goto err_framread;
- rc = video_device_create_file(vdev, &dev_attr_decoding_errors);
+ rc = device_create_file(&vdev->dev, &dev_attr_decoding_errors);
if (rc) goto err_dropped;
return 0;
err_dropped:
- video_device_remove_file(vdev, &dev_attr_packets_dropped);
+ device_remove_file(&vdev->dev, &dev_attr_packets_dropped);
err_framread:
- video_device_remove_file(vdev, &dev_attr_frames_read);
+ device_remove_file(&vdev->dev, &dev_attr_frames_read);
err_framtot:
- video_device_remove_file(vdev, &dev_attr_frames_total);
+ device_remove_file(&vdev->dev, &dev_attr_frames_total);
err_pal:
- video_device_remove_file(vdev, &dev_attr_palette);
+ device_remove_file(&vdev->dev, &dev_attr_palette);
err_stream:
- video_device_remove_file(vdev, &dev_attr_streaming);
+ device_remove_file(&vdev->dev, &dev_attr_streaming);
err_inuse:
- video_device_remove_file(vdev, &dev_attr_in_use);
+ device_remove_file(&vdev->dev, &dev_attr_in_use);
err_model:
- video_device_remove_file(vdev, &dev_attr_model);
+ device_remove_file(&vdev->dev, &dev_attr_model);
err:
+ PDEBUG(0, "STV(e): Could not create sysfs files");
return rc;
}
static void stv680_remove_sysfs_files(struct video_device *vdev)
{
- video_device_remove_file(vdev, &dev_attr_model);
- video_device_remove_file(vdev, &dev_attr_in_use);
- video_device_remove_file(vdev, &dev_attr_streaming);
- video_device_remove_file(vdev, &dev_attr_palette);
- video_device_remove_file(vdev, &dev_attr_frames_total);
- video_device_remove_file(vdev, &dev_attr_frames_read);
- video_device_remove_file(vdev, &dev_attr_packets_dropped);
- video_device_remove_file(vdev, &dev_attr_decoding_errors);
+ device_remove_file(&vdev->dev, &dev_attr_model);
+ device_remove_file(&vdev->dev, &dev_attr_in_use);
+ device_remove_file(&vdev->dev, &dev_attr_streaming);
+ device_remove_file(&vdev->dev, &dev_attr_palette);
+ device_remove_file(&vdev->dev, &dev_attr_frames_total);
+ device_remove_file(&vdev->dev, &dev_attr_frames_read);
+ device_remove_file(&vdev->dev, &dev_attr_packets_dropped);
+ device_remove_file(&vdev->dev, &dev_attr_decoding_errors);
}
/********************************************************************
.llseek = no_llseek,
};
static struct video_device stv680_template = {
- .owner = THIS_MODULE,
.name = "STV0680 USB camera",
- .type = VID_TYPE_CAPTURE,
.fops = &stv680_fops,
.release = video_device_release,
.minor = -1,
goto error;
}
memcpy(stv680->vdev, &stv680_template, sizeof(stv680_template));
- stv680->vdev->dev = &intf->dev;
+ stv680->vdev->parent = &intf->dev;
video_set_drvdata(stv680->vdev, stv680);
memcpy (stv680->vdev->name, stv680->camera_name, strlen (stv680->camera_name));
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/slab.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <linux/i2c.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/i2c-addr.h>
#ifndef VIDEO_AUDIO_BALANCE
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/slab.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <asm/uaccess.h>
#include <linux/i2c.h>
#include <linux/i2c-id.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <media/v4l2-i2c-drv-legacy.h>
#include <media/tuner.h>
#include <media/tuner-types.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/v4l2-i2c-drv-legacy.h>
#include "mt20xx.h"
#include "tda8290.h"
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <linux/i2c.h>
#include <media/tuner.h>
#include <media/tveeprom.h>
#include <media/v4l2-common.h>
-#include <media/audiochip.h>
+#include <media/v4l2-chip-ident.h>
MODULE_DESCRIPTION("i2c Hauppauge eeprom decoder driver");
MODULE_AUTHOR("John Klar");
{ TUNER_ABSENT, "MaxLinear MXL5005_v2"},
{ TUNER_PHILIPS_TDA8290, "Philips 18271_8295"},
/* 150-159 */
- { TUNER_ABSENT, "Xceive XC5000"},
+ { TUNER_ABSENT, "Xceive XC5000"},
};
+/* Use V4L2_IDENT_AMBIGUOUS for those audio 'chips' that are
+ * internal to a video chip, i.e. not a separate audio chip. */
static struct HAUPPAUGE_AUDIOIC
{
- enum audiochip id;
+ u32 id;
char *name;
}
audioIC[] =
{
/* 0-4 */
- {AUDIO_CHIP_NONE, "None"},
- {AUDIO_CHIP_TEA6300, "TEA6300"},
- {AUDIO_CHIP_TEA6300, "TEA6320"},
- {AUDIO_CHIP_TDA985X, "TDA9850"},
- {AUDIO_CHIP_MSP34XX, "MSP3400C"},
+ { V4L2_IDENT_NONE, "None" },
+ { V4L2_IDENT_UNKNOWN, "TEA6300" },
+ { V4L2_IDENT_UNKNOWN, "TEA6320" },
+ { V4L2_IDENT_UNKNOWN, "TDA9850" },
+ { V4L2_IDENT_MSPX4XX, "MSP3400C" },
/* 5-9 */
- {AUDIO_CHIP_MSP34XX, "MSP3410D"},
- {AUDIO_CHIP_MSP34XX, "MSP3415"},
- {AUDIO_CHIP_MSP34XX, "MSP3430"},
- {AUDIO_CHIP_MSP34XX, "MSP3438"},
- {AUDIO_CHIP_UNKNOWN, "CS5331"},
+ { V4L2_IDENT_MSPX4XX, "MSP3410D" },
+ { V4L2_IDENT_MSPX4XX, "MSP3415" },
+ { V4L2_IDENT_MSPX4XX, "MSP3430" },
+ { V4L2_IDENT_MSPX4XX, "MSP3438" },
+ { V4L2_IDENT_UNKNOWN, "CS5331" },
/* 10-14 */
- {AUDIO_CHIP_MSP34XX, "MSP3435"},
- {AUDIO_CHIP_MSP34XX, "MSP3440"},
- {AUDIO_CHIP_MSP34XX, "MSP3445"},
- {AUDIO_CHIP_MSP34XX, "MSP3411"},
- {AUDIO_CHIP_MSP34XX, "MSP3416"},
+ { V4L2_IDENT_MSPX4XX, "MSP3435" },
+ { V4L2_IDENT_MSPX4XX, "MSP3440" },
+ { V4L2_IDENT_MSPX4XX, "MSP3445" },
+ { V4L2_IDENT_MSPX4XX, "MSP3411" },
+ { V4L2_IDENT_MSPX4XX, "MSP3416" },
/* 15-19 */
- {AUDIO_CHIP_MSP34XX, "MSP3425"},
- {AUDIO_CHIP_MSP34XX, "MSP3451"},
- {AUDIO_CHIP_MSP34XX, "MSP3418"},
- {AUDIO_CHIP_UNKNOWN, "Type 0x12"},
- {AUDIO_CHIP_UNKNOWN, "OKI7716"},
+ { V4L2_IDENT_MSPX4XX, "MSP3425" },
+ { V4L2_IDENT_MSPX4XX, "MSP3451" },
+ { V4L2_IDENT_MSPX4XX, "MSP3418" },
+ { V4L2_IDENT_UNKNOWN, "Type 0x12" },
+ { V4L2_IDENT_UNKNOWN, "OKI7716" },
/* 20-24 */
- {AUDIO_CHIP_MSP34XX, "MSP4410"},
- {AUDIO_CHIP_MSP34XX, "MSP4420"},
- {AUDIO_CHIP_MSP34XX, "MSP4440"},
- {AUDIO_CHIP_MSP34XX, "MSP4450"},
- {AUDIO_CHIP_MSP34XX, "MSP4408"},
+ { V4L2_IDENT_MSPX4XX, "MSP4410" },
+ { V4L2_IDENT_MSPX4XX, "MSP4420" },
+ { V4L2_IDENT_MSPX4XX, "MSP4440" },
+ { V4L2_IDENT_MSPX4XX, "MSP4450" },
+ { V4L2_IDENT_MSPX4XX, "MSP4408" },
/* 25-29 */
- {AUDIO_CHIP_MSP34XX, "MSP4418"},
- {AUDIO_CHIP_MSP34XX, "MSP4428"},
- {AUDIO_CHIP_MSP34XX, "MSP4448"},
- {AUDIO_CHIP_MSP34XX, "MSP4458"},
- {AUDIO_CHIP_MSP34XX, "Type 0x1d"},
+ { V4L2_IDENT_MSPX4XX, "MSP4418" },
+ { V4L2_IDENT_MSPX4XX, "MSP4428" },
+ { V4L2_IDENT_MSPX4XX, "MSP4448" },
+ { V4L2_IDENT_MSPX4XX, "MSP4458" },
+ { V4L2_IDENT_MSPX4XX, "Type 0x1d" },
/* 30-34 */
- {AUDIO_CHIP_INTERNAL, "CX880"},
- {AUDIO_CHIP_INTERNAL, "CX881"},
- {AUDIO_CHIP_INTERNAL, "CX883"},
- {AUDIO_CHIP_INTERNAL, "CX882"},
- {AUDIO_CHIP_INTERNAL, "CX25840"},
+ { V4L2_IDENT_AMBIGUOUS, "CX880" },
+ { V4L2_IDENT_AMBIGUOUS, "CX881" },
+ { V4L2_IDENT_AMBIGUOUS, "CX883" },
+ { V4L2_IDENT_AMBIGUOUS, "CX882" },
+ { V4L2_IDENT_AMBIGUOUS, "CX25840" },
/* 35-39 */
- {AUDIO_CHIP_INTERNAL, "CX25841"},
- {AUDIO_CHIP_INTERNAL, "CX25842"},
- {AUDIO_CHIP_INTERNAL, "CX25843"},
- {AUDIO_CHIP_INTERNAL, "CX23418"},
- {AUDIO_CHIP_INTERNAL, "CX23885"},
+ { V4L2_IDENT_AMBIGUOUS, "CX25841" },
+ { V4L2_IDENT_AMBIGUOUS, "CX25842" },
+ { V4L2_IDENT_AMBIGUOUS, "CX25843" },
+ { V4L2_IDENT_AMBIGUOUS, "CX23418" },
+ { V4L2_IDENT_AMBIGUOUS, "CX23885" },
/* 40-44 */
- {AUDIO_CHIP_INTERNAL, "CX23888"},
- {AUDIO_CHIP_INTERNAL, "SAA7131"},
- {AUDIO_CHIP_INTERNAL, "CX23887"},
- {AUDIO_CHIP_INTERNAL, "SAA7164"},
- {AUDIO_CHIP_INTERNAL, "AU8522"},
+ { V4L2_IDENT_AMBIGUOUS, "CX23888" },
+ { V4L2_IDENT_AMBIGUOUS, "SAA7131" },
+ { V4L2_IDENT_AMBIGUOUS, "CX23887" },
+ { V4L2_IDENT_AMBIGUOUS, "SAA7164" },
+ { V4L2_IDENT_AMBIGUOUS, "AU8522" },
};
/* This list is supplied by Hauppauge. Thanks! */
tvee->has_radio = eeprom_data[i+len-1];
/* old style tag, don't know how to detect
IR presence, mark as unknown. */
- tvee->has_ir = -1;
+ tvee->has_ir = 0;
tvee->model =
eeprom_data[i+8] +
(eeprom_data[i+9] << 8);
if (audioic < ARRAY_SIZE(audioIC))
tvee->audio_processor = audioIC[audioic].id;
else
- tvee->audio_processor = AUDIO_CHIP_UNKNOWN;
+ tvee->audio_processor = V4L2_IDENT_UNKNOWN;
break;
/* case 0x03: tag 'EEInfo' */
if (audioic < ARRAY_SIZE(audioIC))
tvee->audio_processor = audioIC[audioic].id;
else
- tvee->audio_processor = AUDIO_CHIP_UNKNOWN;
+ tvee->audio_processor = V4L2_IDENT_UNKNOWN;
break;
case 0x0f:
/* tag 'IRInfo' */
- tvee->has_ir = eeprom_data[i+1];
+ tvee->has_ir = 1 | (eeprom_data[i+1] << 1);
break;
/* case 0x10: tag 'VBIInfo' */
t_fmt_name2[6], t_fmt_name2[7], t_format2);
if (audioic < 0) {
tveeprom_info("audio processor is unknown (no idx)\n");
- tvee->audio_processor = AUDIO_CHIP_UNKNOWN;
+ tvee->audio_processor = V4L2_IDENT_UNKNOWN;
} else {
if (audioic < ARRAY_SIZE(audioIC))
tveeprom_info("audio processor is %s (idx %d)\n",
tveeprom_info("decoder processor is %s (idx %d)\n",
STRM(decoderIC, tvee->decoder_processor),
tvee->decoder_processor);
- if (tvee->has_ir == -1)
- tveeprom_info("has %sradio\n",
- tvee->has_radio ? "" : "no ");
- else
+ if (tvee->has_ir)
tveeprom_info("has %sradio, has %sIR receiver, has %sIR transmitter\n",
tvee->has_radio ? "" : "no ",
- (tvee->has_ir & 1) ? "" : "no ",
- (tvee->has_ir & 2) ? "" : "no ");
+ (tvee->has_ir & 2) ? "" : "no ",
+ (tvee->has_ir & 4) ? "" : "no ");
+ else
+ tveeprom_info("has %sradio\n",
+ tvee->has_radio ? "" : "no ");
}
EXPORT_SYMBOL(tveeprom_hauppauge_analog);
*/
#include <linux/i2c.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <linux/delay.h>
#include <linux/video_decoder.h>
#include <media/v4l2-common.h>
.llseek = no_llseek,
};
static const struct video_device usbvideo_template = {
- .owner = THIS_MODULE,
- .type = VID_TYPE_CAPTURE,
.fops = &usbvideo_fops,
};
err("%s: uvd->dev == NULL", __func__);
return -EINVAL;
}
- uvd->vdev.dev = &uvd->dev->dev;
+ uvd->vdev.parent = &uvd->dev->dev;
if (video_register_device(&uvd->vdev, VFL_TYPE_GRABBER, video_nr) == -1) {
err("%s: video_register_device failed", __func__);
return -EPIPE;
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/usb.h>
#include <linux/mutex.h>
#include <linux/videodev.h>
#include <linux/usb.h>
#include <linux/vmalloc.h>
+#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/mutex.h>
#include <linux/firmware.h>
};
static struct video_device vicam_template = {
- .owner = THIS_MODULE,
.name = "ViCam-based USB Camera",
- .type = VID_TYPE_CAPTURE,
.fops = &vicam_fops,
.minor = -1,
};
#include <linux/mm.h>
#include <linux/utsname.h>
#include <linux/highmem.h>
-#include <linux/videodev.h>
#include <linux/vmalloc.h>
#include <linux/module.h>
#include <linux/init.h>
#include <media/saa7115.h>
#include <media/v4l2-common.h>
#include <media/tuner.h>
-#include <media/audiochip.h>
#include <linux/workqueue.h>
#include <linux/mm.h>
#include <linux/utsname.h>
#include <linux/highmem.h>
-#include <linux/videodev.h>
#include <linux/vmalloc.h>
#include <linux/module.h>
#include <linux/init.h>
#include <media/saa7115.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/tuner.h>
-#include <media/audiochip.h>
#include <linux/workqueue.h>
static inline struct usb_usbvision *cd_to_usbvision(struct device *cd)
{
struct video_device *vdev =
- container_of(cd, struct video_device, class_dev);
+ container_of(cd, struct video_device, dev);
return video_get_drvdata(vdev);
}
struct device_attribute *attr, char *buf)
{
struct video_device *vdev =
- container_of(cd, struct video_device, class_dev);
+ container_of(cd, struct video_device, dev);
struct usb_usbvision *usbvision = video_get_drvdata(vdev);
return sprintf(buf, "%s\n",
usbvision_device_data[usbvision->DevModel].ModelString);
struct device_attribute *attr, char *buf)
{
struct video_device *vdev =
- container_of(cd, struct video_device, class_dev);
+ container_of(cd, struct video_device, dev);
struct usb_usbvision *usbvision = video_get_drvdata(vdev);
struct v4l2_control ctrl;
ctrl.id = V4L2_CID_HUE;
struct device_attribute *attr, char *buf)
{
struct video_device *vdev =
- container_of(cd, struct video_device, class_dev);
+ container_of(cd, struct video_device, dev);
struct usb_usbvision *usbvision = video_get_drvdata(vdev);
struct v4l2_control ctrl;
ctrl.id = V4L2_CID_CONTRAST;
struct device_attribute *attr, char *buf)
{
struct video_device *vdev =
- container_of(cd, struct video_device, class_dev);
+ container_of(cd, struct video_device, dev);
struct usb_usbvision *usbvision = video_get_drvdata(vdev);
struct v4l2_control ctrl;
ctrl.id = V4L2_CID_BRIGHTNESS;
struct device_attribute *attr, char *buf)
{
struct video_device *vdev =
- container_of(cd, struct video_device, class_dev);
+ container_of(cd, struct video_device, dev);
struct usb_usbvision *usbvision = video_get_drvdata(vdev);
struct v4l2_control ctrl;
ctrl.id = V4L2_CID_SATURATION;
struct device_attribute *attr, char *buf)
{
struct video_device *vdev =
- container_of(cd, struct video_device, class_dev);
+ container_of(cd, struct video_device, dev);
struct usb_usbvision *usbvision = video_get_drvdata(vdev);
return sprintf(buf, "%s\n",
YES_NO(usbvision->streaming==Stream_On?1:0));
struct device_attribute *attr, char *buf)
{
struct video_device *vdev =
- container_of(cd, struct video_device, class_dev);
+ container_of(cd, struct video_device, dev);
struct usb_usbvision *usbvision = video_get_drvdata(vdev);
return sprintf(buf, "%s\n",
YES_NO(usbvision->isocMode==ISOC_MODE_COMPRESS));
struct device_attribute *attr, char *buf)
{
struct video_device *vdev =
- container_of(cd, struct video_device, class_dev);
+ container_of(cd, struct video_device, dev);
struct usb_usbvision *usbvision = video_get_drvdata(vdev);
return sprintf(buf, "%d\n", usbvision->bridgeType);
}
if (!vdev)
return;
do {
- res = device_create_file(&vdev->class_dev,
- &dev_attr_version);
+ res = device_create_file(&vdev->dev, &dev_attr_version);
if (res<0)
break;
- res = device_create_file(&vdev->class_dev,
- &dev_attr_model);
+ res = device_create_file(&vdev->dev, &dev_attr_model);
if (res<0)
break;
- res = device_create_file(&vdev->class_dev,
- &dev_attr_hue);
+ res = device_create_file(&vdev->dev, &dev_attr_hue);
if (res<0)
break;
- res = device_create_file(&vdev->class_dev,
- &dev_attr_contrast);
+ res = device_create_file(&vdev->dev, &dev_attr_contrast);
if (res<0)
break;
- res = device_create_file(&vdev->class_dev,
- &dev_attr_brightness);
+ res = device_create_file(&vdev->dev, &dev_attr_brightness);
if (res<0)
break;
- res = device_create_file(&vdev->class_dev,
- &dev_attr_saturation);
+ res = device_create_file(&vdev->dev, &dev_attr_saturation);
if (res<0)
break;
- res = device_create_file(&vdev->class_dev,
- &dev_attr_streaming);
+ res = device_create_file(&vdev->dev, &dev_attr_streaming);
if (res<0)
break;
- res = device_create_file(&vdev->class_dev,
- &dev_attr_compression);
+ res = device_create_file(&vdev->dev, &dev_attr_compression);
if (res<0)
break;
- res = device_create_file(&vdev->class_dev,
- &dev_attr_bridge);
+ res = device_create_file(&vdev->dev, &dev_attr_bridge);
if (res>=0)
return;
} while (0);
static void usbvision_remove_sysfs(struct video_device *vdev)
{
if (vdev) {
- device_remove_file(&vdev->class_dev,
- &dev_attr_version);
- device_remove_file(&vdev->class_dev,
- &dev_attr_model);
- device_remove_file(&vdev->class_dev,
- &dev_attr_hue);
- device_remove_file(&vdev->class_dev,
- &dev_attr_contrast);
- device_remove_file(&vdev->class_dev,
- &dev_attr_brightness);
- device_remove_file(&vdev->class_dev,
- &dev_attr_saturation);
- device_remove_file(&vdev->class_dev,
- &dev_attr_streaming);
- device_remove_file(&vdev->class_dev,
- &dev_attr_compression);
- device_remove_file(&vdev->class_dev,
- &dev_attr_bridge);
+ device_remove_file(&vdev->dev, &dev_attr_version);
+ device_remove_file(&vdev->dev, &dev_attr_model);
+ device_remove_file(&vdev->dev, &dev_attr_hue);
+ device_remove_file(&vdev->dev, &dev_attr_contrast);
+ device_remove_file(&vdev->dev, &dev_attr_brightness);
+ device_remove_file(&vdev->dev, &dev_attr_saturation);
+ device_remove_file(&vdev->dev, &dev_attr_streaming);
+ device_remove_file(&vdev->dev, &dev_attr_compression);
+ device_remove_file(&vdev->dev, &dev_attr_bridge);
}
}
/* .poll = video_poll, */
.compat_ioctl = v4l_compat_ioctl32,
};
-static struct video_device usbvision_video_template = {
- .owner = THIS_MODULE,
- .type = VID_TYPE_TUNER | VID_TYPE_CAPTURE,
- .fops = &usbvision_fops,
- .name = "usbvision-video",
- .release = video_device_release,
- .minor = -1,
+
+static const struct v4l2_ioctl_ops usbvision_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
.vidioc_g_register = vidioc_g_register,
.vidioc_s_register = vidioc_s_register,
#endif
+};
+
+static struct video_device usbvision_video_template = {
+ .fops = &usbvision_fops,
+ .ioctl_ops = &usbvision_ioctl_ops,
+ .name = "usbvision-video",
+ .release = video_device_release,
+ .minor = -1,
.tvnorms = USBVISION_NORMS,
.current_norm = V4L2_STD_PAL
};
.compat_ioctl = v4l_compat_ioctl32,
};
-static struct video_device usbvision_radio_template=
-{
- .owner = THIS_MODULE,
- .type = VID_TYPE_TUNER,
- .fops = &usbvision_radio_fops,
- .name = "usbvision-radio",
- .release = video_device_release,
- .minor = -1,
+static const struct v4l2_ioctl_ops usbvision_radio_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_input = vidioc_enum_input,
.vidioc_g_input = vidioc_g_input,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_g_frequency = vidioc_g_frequency,
.vidioc_s_frequency = vidioc_s_frequency,
+};
+
+static struct video_device usbvision_radio_template = {
+ .fops = &usbvision_radio_fops,
+ .name = "usbvision-radio",
+ .release = video_device_release,
+ .minor = -1,
+ .ioctl_ops = &usbvision_radio_ioctl_ops,
.tvnorms = USBVISION_NORMS,
.current_norm = V4L2_STD_PAL
static struct video_device usbvision_vbi_template=
{
- .owner = THIS_MODULE,
- .type = VID_TYPE_TUNER,
.fops = &usbvision_vbi_fops,
.release = video_device_release,
.name = "usbvision-vbi",
}
*vdev = *vdev_template;
// vdev->minor = -1;
- vdev->dev = &usb_dev->dev;
+ vdev->parent = &usb_dev->dev;
snprintf(vdev->name, sizeof(vdev->name), "%s", name);
video_set_drvdata(vdev, usbvision);
return vdev;
};
static struct uvc_menu_info exposure_auto_controls[] = {
- { 1, "Manual Mode" },
{ 2, "Auto Mode" },
+ { 1, "Manual Mode" },
{ 4, "Shutter Priority Mode" },
{ 8, "Aperture Priority Mode" },
};
if (ctrl == NULL)
return -EINVAL;
+ memset(v4l2_ctrl, 0, sizeof *v4l2_ctrl);
v4l2_ctrl->id = mapping->id;
v4l2_ctrl->type = mapping->v4l2_type;
strncpy(v4l2_ctrl->name, mapping->name, sizeof v4l2_ctrl->name);
v4l2_ctrl->default_value = uvc_get_le_value(data, mapping);
}
- if (mapping->v4l2_type == V4L2_CTRL_TYPE_MENU) {
+ switch (mapping->v4l2_type) {
+ case V4L2_CTRL_TYPE_MENU:
v4l2_ctrl->minimum = 0;
v4l2_ctrl->maximum = mapping->menu_count - 1;
v4l2_ctrl->step = 1;
}
return 0;
+
+ case V4L2_CTRL_TYPE_BOOLEAN:
+ v4l2_ctrl->minimum = 0;
+ v4l2_ctrl->maximum = 1;
+ v4l2_ctrl->step = 1;
+ return 0;
+
+ default:
+ break;
}
if (ctrl->info->flags & UVC_CONTROL_GET_MIN) {
* unregistered before the reference is released, so we don't need to
* get another one.
*/
- vdev->dev = &dev->intf->dev;
- vdev->type = 0;
- vdev->type2 = 0;
+ vdev->parent = &dev->intf->dev;
vdev->minor = -1;
vdev->fops = &uvc_fops;
vdev->release = video_device_release;
#include <asm/atomic.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include "uvcvideo.h"
#include <linux/slab.h>
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include <linux/kmod.h>
#endif
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
MODULE_AUTHOR("Bill Dirks, Justin Schoeman, Gerd Knorr");
MODULE_DESCRIPTION("misc helper functions for v4l2 device drivers");
--- /dev/null
+/*
+ * Video capture interface for Linux version 2
+ *
+ * A generic video device interface for the LINUX operating system
+ * using a set of device structures/vectors for low level operations.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Authors: Alan Cox, <alan@redhat.com> (version 1)
+ * Mauro Carvalho Chehab <mchehab@infradead.org> (version 2)
+ *
+ * Fixes: 20000516 Claudio Matsuoka <claudio@conectiva.com>
+ * - Added procfs support
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kmod.h>
+#include <linux/slab.h>
+#include <linux/smp_lock.h>
+#include <asm/uaccess.h>
+#include <asm/system.h>
+
+#include <media/v4l2-common.h>
+
+#define VIDEO_NUM_DEVICES 256
+#define VIDEO_NAME "video4linux"
+
+/*
+ * sysfs stuff
+ */
+
+static ssize_t show_index(struct device *cd,
+ struct device_attribute *attr, char *buf)
+{
+ struct video_device *vfd = container_of(cd, struct video_device, dev);
+ return sprintf(buf, "%i\n", vfd->index);
+}
+
+static ssize_t show_name(struct device *cd,
+ struct device_attribute *attr, char *buf)
+{
+ struct video_device *vfd = container_of(cd, struct video_device, dev);
+ return sprintf(buf, "%.*s\n", (int)sizeof(vfd->name), vfd->name);
+}
+
+static struct device_attribute video_device_attrs[] = {
+ __ATTR(name, S_IRUGO, show_name, NULL),
+ __ATTR(index, S_IRUGO, show_index, NULL),
+ __ATTR_NULL
+};
+
+struct video_device *video_device_alloc(void)
+{
+ struct video_device *vfd;
+
+ vfd = kzalloc(sizeof(*vfd), GFP_KERNEL);
+ return vfd;
+}
+EXPORT_SYMBOL(video_device_alloc);
+
+void video_device_release(struct video_device *vfd)
+{
+ kfree(vfd);
+}
+EXPORT_SYMBOL(video_device_release);
+
+static void video_release(struct device *cd)
+{
+ struct video_device *vfd = container_of(cd, struct video_device, dev);
+
+#if 1
+ /* needed until all drivers are fixed */
+ if (!vfd->release)
+ return;
+#endif
+ vfd->release(vfd);
+}
+
+static struct class video_class = {
+ .name = VIDEO_NAME,
+ .dev_attrs = video_device_attrs,
+ .dev_release = video_release,
+};
+
+/*
+ * Active devices
+ */
+
+static struct video_device *video_device[VIDEO_NUM_DEVICES];
+static DEFINE_MUTEX(videodev_lock);
+
+struct video_device *video_devdata(struct file *file)
+{
+ return video_device[iminor(file->f_path.dentry->d_inode)];
+}
+EXPORT_SYMBOL(video_devdata);
+
+/*
+ * Open a video device - FIXME: Obsoleted
+ */
+static int video_open(struct inode *inode, struct file *file)
+{
+ unsigned int minor = iminor(inode);
+ int err = 0;
+ struct video_device *vfl;
+ const struct file_operations *old_fops;
+
+ if (minor >= VIDEO_NUM_DEVICES)
+ return -ENODEV;
+ lock_kernel();
+ mutex_lock(&videodev_lock);
+ vfl = video_device[minor];
+ if (vfl == NULL) {
+ mutex_unlock(&videodev_lock);
+ request_module("char-major-%d-%d", VIDEO_MAJOR, minor);
+ mutex_lock(&videodev_lock);
+ vfl = video_device[minor];
+ if (vfl == NULL) {
+ mutex_unlock(&videodev_lock);
+ unlock_kernel();
+ return -ENODEV;
+ }
+ }
+ old_fops = file->f_op;
+ file->f_op = fops_get(vfl->fops);
+ if (file->f_op->open)
+ err = file->f_op->open(inode, file);
+ if (err) {
+ fops_put(file->f_op);
+ file->f_op = fops_get(old_fops);
+ }
+ fops_put(old_fops);
+ mutex_unlock(&videodev_lock);
+ unlock_kernel();
+ return err;
+}
+
+/*
+ * open/release helper functions -- handle exclusive opens
+ * Should be removed soon
+ */
+int video_exclusive_open(struct inode *inode, struct file *file)
+{
+ struct video_device *vfl = video_devdata(file);
+ int retval = 0;
+
+ mutex_lock(&vfl->lock);
+ if (vfl->users)
+ retval = -EBUSY;
+ else
+ vfl->users++;
+ mutex_unlock(&vfl->lock);
+ return retval;
+}
+EXPORT_SYMBOL(video_exclusive_open);
+
+int video_exclusive_release(struct inode *inode, struct file *file)
+{
+ struct video_device *vfl = video_devdata(file);
+
+ vfl->users--;
+ return 0;
+}
+EXPORT_SYMBOL(video_exclusive_release);
+
+/**
+ * get_index - assign stream number based on parent device
+ * @vdev: video_device to assign index number to, vdev->dev should be assigned
+ * @num: -1 if auto assign, requested number otherwise
+ *
+ *
+ * returns -ENFILE if num is already in use, a free index number if
+ * successful.
+ */
+static int get_index(struct video_device *vdev, int num)
+{
+ u32 used = 0;
+ const int max_index = sizeof(used) * 8 - 1;
+ int i;
+
+ /* Currently a single v4l driver instance cannot create more than
+ 32 devices.
+ Increase to u64 or an array of u32 if more are needed. */
+ if (num > max_index) {
+ printk(KERN_ERR "videodev: %s num is too large\n", __func__);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < VIDEO_NUM_DEVICES; i++) {
+ if (video_device[i] != NULL &&
+ video_device[i] != vdev &&
+ video_device[i]->parent == vdev->parent) {
+ used |= 1 << video_device[i]->index;
+ }
+ }
+
+ if (num >= 0) {
+ if (used & (1 << num))
+ return -ENFILE;
+ return num;
+ }
+
+ i = ffz(used);
+ return i > max_index ? -ENFILE : i;
+}
+
+static const struct file_operations video_fops;
+
+int video_register_device(struct video_device *vfd, int type, int nr)
+{
+ return video_register_device_index(vfd, type, nr, -1);
+}
+EXPORT_SYMBOL(video_register_device);
+
+/**
+ * video_register_device - register video4linux devices
+ * @vfd: video device structure we want to register
+ * @type: type of device to register
+ * @nr: which device number (0 == /dev/video0, 1 == /dev/video1, ...
+ * -1 == first free)
+ *
+ * The registration code assigns minor numbers based on the type
+ * requested. -ENFILE is returned in all the device slots for this
+ * category are full. If not then the minor field is set and the
+ * driver initialize function is called (if non %NULL).
+ *
+ * Zero is returned on success.
+ *
+ * Valid types are
+ *
+ * %VFL_TYPE_GRABBER - A frame grabber
+ *
+ * %VFL_TYPE_VTX - A teletext device
+ *
+ * %VFL_TYPE_VBI - Vertical blank data (undecoded)
+ *
+ * %VFL_TYPE_RADIO - A radio card
+ */
+
+int video_register_device_index(struct video_device *vfd, int type, int nr,
+ int index)
+{
+ int i = 0;
+ int base;
+ int end;
+ int ret;
+ char *name_base;
+
+ switch (type) {
+ case VFL_TYPE_GRABBER:
+ base = MINOR_VFL_TYPE_GRABBER_MIN;
+ end = MINOR_VFL_TYPE_GRABBER_MAX+1;
+ name_base = "video";
+ break;
+ case VFL_TYPE_VTX:
+ base = MINOR_VFL_TYPE_VTX_MIN;
+ end = MINOR_VFL_TYPE_VTX_MAX+1;
+ name_base = "vtx";
+ break;
+ case VFL_TYPE_VBI:
+ base = MINOR_VFL_TYPE_VBI_MIN;
+ end = MINOR_VFL_TYPE_VBI_MAX+1;
+ name_base = "vbi";
+ break;
+ case VFL_TYPE_RADIO:
+ base = MINOR_VFL_TYPE_RADIO_MIN;
+ end = MINOR_VFL_TYPE_RADIO_MAX+1;
+ name_base = "radio";
+ break;
+ default:
+ printk(KERN_ERR "%s called with unknown type: %d\n",
+ __func__, type);
+ return -1;
+ }
+
+ /* pick a minor number */
+ mutex_lock(&videodev_lock);
+ if (nr >= 0 && nr < end-base) {
+ /* use the one the driver asked for */
+ i = base + nr;
+ if (NULL != video_device[i]) {
+ mutex_unlock(&videodev_lock);
+ return -ENFILE;
+ }
+ } else {
+ /* use first free */
+ for (i = base; i < end; i++)
+ if (NULL == video_device[i])
+ break;
+ if (i == end) {
+ mutex_unlock(&videodev_lock);
+ return -ENFILE;
+ }
+ }
+ video_device[i] = vfd;
+ vfd->vfl_type = type;
+ vfd->minor = i;
+
+ ret = get_index(vfd, index);
+ vfd->index = ret;
+
+ mutex_unlock(&videodev_lock);
+
+ if (ret < 0) {
+ printk(KERN_ERR "%s: get_index failed\n", __func__);
+ goto fail_minor;
+ }
+
+ mutex_init(&vfd->lock);
+
+ /* sysfs class */
+ memset(&vfd->dev, 0x00, sizeof(vfd->dev));
+ vfd->dev.class = &video_class;
+ vfd->dev.devt = MKDEV(VIDEO_MAJOR, vfd->minor);
+ if (vfd->parent)
+ vfd->dev.parent = vfd->parent;
+ sprintf(vfd->dev.bus_id, "%s%d", name_base, i - base);
+ ret = device_register(&vfd->dev);
+ if (ret < 0) {
+ printk(KERN_ERR "%s: device_register failed\n", __func__);
+ goto fail_minor;
+ }
+
+#if 1
+ /* needed until all drivers are fixed */
+ if (!vfd->release)
+ printk(KERN_WARNING "videodev: \"%s\" has no release callback. "
+ "Please fix your driver for proper sysfs support, see "
+ "http://lwn.net/Articles/36850/\n", vfd->name);
+#endif
+ return 0;
+
+fail_minor:
+ mutex_lock(&videodev_lock);
+ video_device[vfd->minor] = NULL;
+ vfd->minor = -1;
+ mutex_unlock(&videodev_lock);
+ return ret;
+}
+EXPORT_SYMBOL(video_register_device_index);
+
+/**
+ * video_unregister_device - unregister a video4linux device
+ * @vfd: the device to unregister
+ *
+ * This unregisters the passed device and deassigns the minor
+ * number. Future open calls will be met with errors.
+ */
+
+void video_unregister_device(struct video_device *vfd)
+{
+ mutex_lock(&videodev_lock);
+ if (video_device[vfd->minor] != vfd)
+ panic("videodev: bad unregister");
+
+ video_device[vfd->minor] = NULL;
+ device_unregister(&vfd->dev);
+ mutex_unlock(&videodev_lock);
+}
+EXPORT_SYMBOL(video_unregister_device);
+
+/*
+ * Video fs operations
+ */
+static const struct file_operations video_fops = {
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .open = video_open,
+};
+
+/*
+ * Initialise video for linux
+ */
+
+static int __init videodev_init(void)
+{
+ int ret;
+
+ printk(KERN_INFO "Linux video capture interface: v2.00\n");
+ if (register_chrdev(VIDEO_MAJOR, VIDEO_NAME, &video_fops)) {
+ printk(KERN_WARNING "video_dev: unable to get major %d\n", VIDEO_MAJOR);
+ return -EIO;
+ }
+
+ ret = class_register(&video_class);
+ if (ret < 0) {
+ unregister_chrdev(VIDEO_MAJOR, VIDEO_NAME);
+ printk(KERN_WARNING "video_dev: class_register failed\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void __exit videodev_exit(void)
+{
+ class_unregister(&video_class);
+ unregister_chrdev(VIDEO_MAJOR, VIDEO_NAME);
+}
+
+module_init(videodev_init)
+module_exit(videodev_exit)
+
+MODULE_AUTHOR("Alan Cox, Mauro Carvalho Chehab <mchehab@infradead.org>");
+MODULE_DESCRIPTION("Device registrar for Video4Linux drivers v2");
+MODULE_LICENSE("GPL");
+
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
--- /dev/null
+/*
+ * Video capture interface for Linux version 2
+ *
+ * A generic framework to process V4L2 ioctl commands.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Authors: Alan Cox, <alan@redhat.com> (version 1)
+ * Mauro Carvalho Chehab <mchehab@infradead.org> (version 2)
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#define __OLD_VIDIOC_ /* To allow fixing old calls */
+#include <linux/videodev2.h>
+
+#ifdef CONFIG_VIDEO_V4L1
+#include <linux/videodev.h>
+#endif
+#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
+#include <linux/video_decoder.h>
+
+#define dbgarg(cmd, fmt, arg...) \
+ do { \
+ if (vfd->debug & V4L2_DEBUG_IOCTL_ARG) { \
+ printk(KERN_DEBUG "%s: ", vfd->name); \
+ v4l_printk_ioctl(cmd); \
+ printk(" " fmt, ## arg); \
+ } \
+ } while (0)
+
+#define dbgarg2(fmt, arg...) \
+ do { \
+ if (vfd->debug & V4L2_DEBUG_IOCTL_ARG) \
+ printk(KERN_DEBUG "%s: " fmt, vfd->name, ## arg);\
+ } while (0)
+
+struct std_descr {
+ v4l2_std_id std;
+ const char *descr;
+};
+
+static const struct std_descr standards[] = {
+ { V4L2_STD_NTSC, "NTSC" },
+ { V4L2_STD_NTSC_M, "NTSC-M" },
+ { V4L2_STD_NTSC_M_JP, "NTSC-M-JP" },
+ { V4L2_STD_NTSC_M_KR, "NTSC-M-KR" },
+ { V4L2_STD_NTSC_443, "NTSC-443" },
+ { V4L2_STD_PAL, "PAL" },
+ { V4L2_STD_PAL_BG, "PAL-BG" },
+ { V4L2_STD_PAL_B, "PAL-B" },
+ { V4L2_STD_PAL_B1, "PAL-B1" },
+ { V4L2_STD_PAL_G, "PAL-G" },
+ { V4L2_STD_PAL_H, "PAL-H" },
+ { V4L2_STD_PAL_I, "PAL-I" },
+ { V4L2_STD_PAL_DK, "PAL-DK" },
+ { V4L2_STD_PAL_D, "PAL-D" },
+ { V4L2_STD_PAL_D1, "PAL-D1" },
+ { V4L2_STD_PAL_K, "PAL-K" },
+ { V4L2_STD_PAL_M, "PAL-M" },
+ { V4L2_STD_PAL_N, "PAL-N" },
+ { V4L2_STD_PAL_Nc, "PAL-Nc" },
+ { V4L2_STD_PAL_60, "PAL-60" },
+ { V4L2_STD_SECAM, "SECAM" },
+ { V4L2_STD_SECAM_B, "SECAM-B" },
+ { V4L2_STD_SECAM_G, "SECAM-G" },
+ { V4L2_STD_SECAM_H, "SECAM-H" },
+ { V4L2_STD_SECAM_DK, "SECAM-DK" },
+ { V4L2_STD_SECAM_D, "SECAM-D" },
+ { V4L2_STD_SECAM_K, "SECAM-K" },
+ { V4L2_STD_SECAM_K1, "SECAM-K1" },
+ { V4L2_STD_SECAM_L, "SECAM-L" },
+ { V4L2_STD_SECAM_LC, "SECAM-Lc" },
+ { 0, "Unknown" }
+};
+
+/* video4linux standard ID conversion to standard name
+ */
+const char *v4l2_norm_to_name(v4l2_std_id id)
+{
+ u32 myid = id;
+ int i;
+
+ /* HACK: ppc32 architecture doesn't have __ucmpdi2 function to handle
+ 64 bit comparations. So, on that architecture, with some gcc
+ variants, compilation fails. Currently, the max value is 30bit wide.
+ */
+ BUG_ON(myid != id);
+
+ for (i = 0; standards[i].std; i++)
+ if (myid == standards[i].std)
+ break;
+ return standards[i].descr;
+}
+EXPORT_SYMBOL(v4l2_norm_to_name);
+
+/* Fill in the fields of a v4l2_standard structure according to the
+ 'id' and 'transmission' parameters. Returns negative on error. */
+int v4l2_video_std_construct(struct v4l2_standard *vs,
+ int id, const char *name)
+{
+ u32 index = vs->index;
+
+ memset(vs, 0, sizeof(struct v4l2_standard));
+ vs->index = index;
+ vs->id = id;
+ if (id & V4L2_STD_525_60) {
+ vs->frameperiod.numerator = 1001;
+ vs->frameperiod.denominator = 30000;
+ vs->framelines = 525;
+ } else {
+ vs->frameperiod.numerator = 1;
+ vs->frameperiod.denominator = 25;
+ vs->framelines = 625;
+ }
+ strlcpy(vs->name, name, sizeof(vs->name));
+ return 0;
+}
+EXPORT_SYMBOL(v4l2_video_std_construct);
+
+/* ----------------------------------------------------------------- */
+/* some arrays for pretty-printing debug messages of enum types */
+
+const char *v4l2_field_names[] = {
+ [V4L2_FIELD_ANY] = "any",
+ [V4L2_FIELD_NONE] = "none",
+ [V4L2_FIELD_TOP] = "top",
+ [V4L2_FIELD_BOTTOM] = "bottom",
+ [V4L2_FIELD_INTERLACED] = "interlaced",
+ [V4L2_FIELD_SEQ_TB] = "seq-tb",
+ [V4L2_FIELD_SEQ_BT] = "seq-bt",
+ [V4L2_FIELD_ALTERNATE] = "alternate",
+ [V4L2_FIELD_INTERLACED_TB] = "interlaced-tb",
+ [V4L2_FIELD_INTERLACED_BT] = "interlaced-bt",
+};
+EXPORT_SYMBOL(v4l2_field_names);
+
+const char *v4l2_type_names[] = {
+ [V4L2_BUF_TYPE_VIDEO_CAPTURE] = "vid-cap",
+ [V4L2_BUF_TYPE_VIDEO_OVERLAY] = "vid-overlay",
+ [V4L2_BUF_TYPE_VIDEO_OUTPUT] = "vid-out",
+ [V4L2_BUF_TYPE_VBI_CAPTURE] = "vbi-cap",
+ [V4L2_BUF_TYPE_VBI_OUTPUT] = "vbi-out",
+ [V4L2_BUF_TYPE_SLICED_VBI_CAPTURE] = "sliced-vbi-cap",
+ [V4L2_BUF_TYPE_SLICED_VBI_OUTPUT] = "sliced-vbi-out",
+ [V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY] = "vid-out-overlay",
+};
+EXPORT_SYMBOL(v4l2_type_names);
+
+static const char *v4l2_memory_names[] = {
+ [V4L2_MEMORY_MMAP] = "mmap",
+ [V4L2_MEMORY_USERPTR] = "userptr",
+ [V4L2_MEMORY_OVERLAY] = "overlay",
+};
+
+#define prt_names(a, arr) ((((a) >= 0) && ((a) < ARRAY_SIZE(arr))) ? \
+ arr[a] : "unknown")
+
+/* ------------------------------------------------------------------ */
+/* debug help functions */
+
+#ifdef CONFIG_VIDEO_V4L1_COMPAT
+static const char *v4l1_ioctls[] = {
+ [_IOC_NR(VIDIOCGCAP)] = "VIDIOCGCAP",
+ [_IOC_NR(VIDIOCGCHAN)] = "VIDIOCGCHAN",
+ [_IOC_NR(VIDIOCSCHAN)] = "VIDIOCSCHAN",
+ [_IOC_NR(VIDIOCGTUNER)] = "VIDIOCGTUNER",
+ [_IOC_NR(VIDIOCSTUNER)] = "VIDIOCSTUNER",
+ [_IOC_NR(VIDIOCGPICT)] = "VIDIOCGPICT",
+ [_IOC_NR(VIDIOCSPICT)] = "VIDIOCSPICT",
+ [_IOC_NR(VIDIOCCAPTURE)] = "VIDIOCCAPTURE",
+ [_IOC_NR(VIDIOCGWIN)] = "VIDIOCGWIN",
+ [_IOC_NR(VIDIOCSWIN)] = "VIDIOCSWIN",
+ [_IOC_NR(VIDIOCGFBUF)] = "VIDIOCGFBUF",
+ [_IOC_NR(VIDIOCSFBUF)] = "VIDIOCSFBUF",
+ [_IOC_NR(VIDIOCKEY)] = "VIDIOCKEY",
+ [_IOC_NR(VIDIOCGFREQ)] = "VIDIOCGFREQ",
+ [_IOC_NR(VIDIOCSFREQ)] = "VIDIOCSFREQ",
+ [_IOC_NR(VIDIOCGAUDIO)] = "VIDIOCGAUDIO",
+ [_IOC_NR(VIDIOCSAUDIO)] = "VIDIOCSAUDIO",
+ [_IOC_NR(VIDIOCSYNC)] = "VIDIOCSYNC",
+ [_IOC_NR(VIDIOCMCAPTURE)] = "VIDIOCMCAPTURE",
+ [_IOC_NR(VIDIOCGMBUF)] = "VIDIOCGMBUF",
+ [_IOC_NR(VIDIOCGUNIT)] = "VIDIOCGUNIT",
+ [_IOC_NR(VIDIOCGCAPTURE)] = "VIDIOCGCAPTURE",
+ [_IOC_NR(VIDIOCSCAPTURE)] = "VIDIOCSCAPTURE",
+ [_IOC_NR(VIDIOCSPLAYMODE)] = "VIDIOCSPLAYMODE",
+ [_IOC_NR(VIDIOCSWRITEMODE)] = "VIDIOCSWRITEMODE",
+ [_IOC_NR(VIDIOCGPLAYINFO)] = "VIDIOCGPLAYINFO",
+ [_IOC_NR(VIDIOCSMICROCODE)] = "VIDIOCSMICROCODE",
+ [_IOC_NR(VIDIOCGVBIFMT)] = "VIDIOCGVBIFMT",
+ [_IOC_NR(VIDIOCSVBIFMT)] = "VIDIOCSVBIFMT"
+};
+#define V4L1_IOCTLS ARRAY_SIZE(v4l1_ioctls)
+#endif
+
+static const char *v4l2_ioctls[] = {
+ [_IOC_NR(VIDIOC_QUERYCAP)] = "VIDIOC_QUERYCAP",
+ [_IOC_NR(VIDIOC_RESERVED)] = "VIDIOC_RESERVED",
+ [_IOC_NR(VIDIOC_ENUM_FMT)] = "VIDIOC_ENUM_FMT",
+ [_IOC_NR(VIDIOC_G_FMT)] = "VIDIOC_G_FMT",
+ [_IOC_NR(VIDIOC_S_FMT)] = "VIDIOC_S_FMT",
+ [_IOC_NR(VIDIOC_REQBUFS)] = "VIDIOC_REQBUFS",
+ [_IOC_NR(VIDIOC_QUERYBUF)] = "VIDIOC_QUERYBUF",
+ [_IOC_NR(VIDIOC_G_FBUF)] = "VIDIOC_G_FBUF",
+ [_IOC_NR(VIDIOC_S_FBUF)] = "VIDIOC_S_FBUF",
+ [_IOC_NR(VIDIOC_OVERLAY)] = "VIDIOC_OVERLAY",
+ [_IOC_NR(VIDIOC_QBUF)] = "VIDIOC_QBUF",
+ [_IOC_NR(VIDIOC_DQBUF)] = "VIDIOC_DQBUF",
+ [_IOC_NR(VIDIOC_STREAMON)] = "VIDIOC_STREAMON",
+ [_IOC_NR(VIDIOC_STREAMOFF)] = "VIDIOC_STREAMOFF",
+ [_IOC_NR(VIDIOC_G_PARM)] = "VIDIOC_G_PARM",
+ [_IOC_NR(VIDIOC_S_PARM)] = "VIDIOC_S_PARM",
+ [_IOC_NR(VIDIOC_G_STD)] = "VIDIOC_G_STD",
+ [_IOC_NR(VIDIOC_S_STD)] = "VIDIOC_S_STD",
+ [_IOC_NR(VIDIOC_ENUMSTD)] = "VIDIOC_ENUMSTD",
+ [_IOC_NR(VIDIOC_ENUMINPUT)] = "VIDIOC_ENUMINPUT",
+ [_IOC_NR(VIDIOC_G_CTRL)] = "VIDIOC_G_CTRL",
+ [_IOC_NR(VIDIOC_S_CTRL)] = "VIDIOC_S_CTRL",
+ [_IOC_NR(VIDIOC_G_TUNER)] = "VIDIOC_G_TUNER",
+ [_IOC_NR(VIDIOC_S_TUNER)] = "VIDIOC_S_TUNER",
+ [_IOC_NR(VIDIOC_G_AUDIO)] = "VIDIOC_G_AUDIO",
+ [_IOC_NR(VIDIOC_S_AUDIO)] = "VIDIOC_S_AUDIO",
+ [_IOC_NR(VIDIOC_QUERYCTRL)] = "VIDIOC_QUERYCTRL",
+ [_IOC_NR(VIDIOC_QUERYMENU)] = "VIDIOC_QUERYMENU",
+ [_IOC_NR(VIDIOC_G_INPUT)] = "VIDIOC_G_INPUT",
+ [_IOC_NR(VIDIOC_S_INPUT)] = "VIDIOC_S_INPUT",
+ [_IOC_NR(VIDIOC_G_OUTPUT)] = "VIDIOC_G_OUTPUT",
+ [_IOC_NR(VIDIOC_S_OUTPUT)] = "VIDIOC_S_OUTPUT",
+ [_IOC_NR(VIDIOC_ENUMOUTPUT)] = "VIDIOC_ENUMOUTPUT",
+ [_IOC_NR(VIDIOC_G_AUDOUT)] = "VIDIOC_G_AUDOUT",
+ [_IOC_NR(VIDIOC_S_AUDOUT)] = "VIDIOC_S_AUDOUT",
+ [_IOC_NR(VIDIOC_G_MODULATOR)] = "VIDIOC_G_MODULATOR",
+ [_IOC_NR(VIDIOC_S_MODULATOR)] = "VIDIOC_S_MODULATOR",
+ [_IOC_NR(VIDIOC_G_FREQUENCY)] = "VIDIOC_G_FREQUENCY",
+ [_IOC_NR(VIDIOC_S_FREQUENCY)] = "VIDIOC_S_FREQUENCY",
+ [_IOC_NR(VIDIOC_CROPCAP)] = "VIDIOC_CROPCAP",
+ [_IOC_NR(VIDIOC_G_CROP)] = "VIDIOC_G_CROP",
+ [_IOC_NR(VIDIOC_S_CROP)] = "VIDIOC_S_CROP",
+ [_IOC_NR(VIDIOC_G_JPEGCOMP)] = "VIDIOC_G_JPEGCOMP",
+ [_IOC_NR(VIDIOC_S_JPEGCOMP)] = "VIDIOC_S_JPEGCOMP",
+ [_IOC_NR(VIDIOC_QUERYSTD)] = "VIDIOC_QUERYSTD",
+ [_IOC_NR(VIDIOC_TRY_FMT)] = "VIDIOC_TRY_FMT",
+ [_IOC_NR(VIDIOC_ENUMAUDIO)] = "VIDIOC_ENUMAUDIO",
+ [_IOC_NR(VIDIOC_ENUMAUDOUT)] = "VIDIOC_ENUMAUDOUT",
+ [_IOC_NR(VIDIOC_G_PRIORITY)] = "VIDIOC_G_PRIORITY",
+ [_IOC_NR(VIDIOC_S_PRIORITY)] = "VIDIOC_S_PRIORITY",
+ [_IOC_NR(VIDIOC_G_SLICED_VBI_CAP)] = "VIDIOC_G_SLICED_VBI_CAP",
+ [_IOC_NR(VIDIOC_LOG_STATUS)] = "VIDIOC_LOG_STATUS",
+ [_IOC_NR(VIDIOC_G_EXT_CTRLS)] = "VIDIOC_G_EXT_CTRLS",
+ [_IOC_NR(VIDIOC_S_EXT_CTRLS)] = "VIDIOC_S_EXT_CTRLS",
+ [_IOC_NR(VIDIOC_TRY_EXT_CTRLS)] = "VIDIOC_TRY_EXT_CTRLS",
+#if 1
+ [_IOC_NR(VIDIOC_ENUM_FRAMESIZES)] = "VIDIOC_ENUM_FRAMESIZES",
+ [_IOC_NR(VIDIOC_ENUM_FRAMEINTERVALS)] = "VIDIOC_ENUM_FRAMEINTERVALS",
+ [_IOC_NR(VIDIOC_G_ENC_INDEX)] = "VIDIOC_G_ENC_INDEX",
+ [_IOC_NR(VIDIOC_ENCODER_CMD)] = "VIDIOC_ENCODER_CMD",
+ [_IOC_NR(VIDIOC_TRY_ENCODER_CMD)] = "VIDIOC_TRY_ENCODER_CMD",
+
+ [_IOC_NR(VIDIOC_DBG_S_REGISTER)] = "VIDIOC_DBG_S_REGISTER",
+ [_IOC_NR(VIDIOC_DBG_G_REGISTER)] = "VIDIOC_DBG_G_REGISTER",
+
+ [_IOC_NR(VIDIOC_G_CHIP_IDENT)] = "VIDIOC_G_CHIP_IDENT",
+ [_IOC_NR(VIDIOC_S_HW_FREQ_SEEK)] = "VIDIOC_S_HW_FREQ_SEEK",
+#endif
+};
+#define V4L2_IOCTLS ARRAY_SIZE(v4l2_ioctls)
+
+static const char *v4l2_int_ioctls[] = {
+#ifdef CONFIG_VIDEO_V4L1_COMPAT
+ [_IOC_NR(DECODER_GET_CAPABILITIES)] = "DECODER_GET_CAPABILITIES",
+ [_IOC_NR(DECODER_GET_STATUS)] = "DECODER_GET_STATUS",
+ [_IOC_NR(DECODER_SET_NORM)] = "DECODER_SET_NORM",
+ [_IOC_NR(DECODER_SET_INPUT)] = "DECODER_SET_INPUT",
+ [_IOC_NR(DECODER_SET_OUTPUT)] = "DECODER_SET_OUTPUT",
+ [_IOC_NR(DECODER_ENABLE_OUTPUT)] = "DECODER_ENABLE_OUTPUT",
+ [_IOC_NR(DECODER_SET_PICTURE)] = "DECODER_SET_PICTURE",
+ [_IOC_NR(DECODER_SET_GPIO)] = "DECODER_SET_GPIO",
+ [_IOC_NR(DECODER_INIT)] = "DECODER_INIT",
+ [_IOC_NR(DECODER_SET_VBI_BYPASS)] = "DECODER_SET_VBI_BYPASS",
+ [_IOC_NR(DECODER_DUMP)] = "DECODER_DUMP",
+#endif
+ [_IOC_NR(AUDC_SET_RADIO)] = "AUDC_SET_RADIO",
+
+ [_IOC_NR(TUNER_SET_TYPE_ADDR)] = "TUNER_SET_TYPE_ADDR",
+ [_IOC_NR(TUNER_SET_STANDBY)] = "TUNER_SET_STANDBY",
+ [_IOC_NR(TUNER_SET_CONFIG)] = "TUNER_SET_CONFIG",
+
+ [_IOC_NR(VIDIOC_INT_S_TUNER_MODE)] = "VIDIOC_INT_S_TUNER_MODE",
+ [_IOC_NR(VIDIOC_INT_RESET)] = "VIDIOC_INT_RESET",
+ [_IOC_NR(VIDIOC_INT_AUDIO_CLOCK_FREQ)] = "VIDIOC_INT_AUDIO_CLOCK_FREQ",
+ [_IOC_NR(VIDIOC_INT_DECODE_VBI_LINE)] = "VIDIOC_INT_DECODE_VBI_LINE",
+ [_IOC_NR(VIDIOC_INT_S_VBI_DATA)] = "VIDIOC_INT_S_VBI_DATA",
+ [_IOC_NR(VIDIOC_INT_G_VBI_DATA)] = "VIDIOC_INT_G_VBI_DATA",
+ [_IOC_NR(VIDIOC_INT_I2S_CLOCK_FREQ)] = "VIDIOC_INT_I2S_CLOCK_FREQ",
+ [_IOC_NR(VIDIOC_INT_S_STANDBY)] = "VIDIOC_INT_S_STANDBY",
+ [_IOC_NR(VIDIOC_INT_S_AUDIO_ROUTING)] = "VIDIOC_INT_S_AUDIO_ROUTING",
+ [_IOC_NR(VIDIOC_INT_G_AUDIO_ROUTING)] = "VIDIOC_INT_G_AUDIO_ROUTING",
+ [_IOC_NR(VIDIOC_INT_S_VIDEO_ROUTING)] = "VIDIOC_INT_S_VIDEO_ROUTING",
+ [_IOC_NR(VIDIOC_INT_G_VIDEO_ROUTING)] = "VIDIOC_INT_G_VIDEO_ROUTING",
+ [_IOC_NR(VIDIOC_INT_S_CRYSTAL_FREQ)] = "VIDIOC_INT_S_CRYSTAL_FREQ",
+ [_IOC_NR(VIDIOC_INT_INIT)] = "VIDIOC_INT_INIT",
+ [_IOC_NR(VIDIOC_INT_G_STD_OUTPUT)] = "VIDIOC_INT_G_STD_OUTPUT",
+ [_IOC_NR(VIDIOC_INT_S_STD_OUTPUT)] = "VIDIOC_INT_S_STD_OUTPUT",
+};
+#define V4L2_INT_IOCTLS ARRAY_SIZE(v4l2_int_ioctls)
+
+/* Common ioctl debug function. This function can be used by
+ external ioctl messages as well as internal V4L ioctl */
+void v4l_printk_ioctl(unsigned int cmd)
+{
+ char *dir, *type;
+
+ switch (_IOC_TYPE(cmd)) {
+ case 'd':
+ if (_IOC_NR(cmd) >= V4L2_INT_IOCTLS) {
+ type = "v4l2_int";
+ break;
+ }
+ printk("%s", v4l2_int_ioctls[_IOC_NR(cmd)]);
+ return;
+#ifdef CONFIG_VIDEO_V4L1_COMPAT
+ case 'v':
+ if (_IOC_NR(cmd) >= V4L1_IOCTLS) {
+ type = "v4l1";
+ break;
+ }
+ printk("%s", v4l1_ioctls[_IOC_NR(cmd)]);
+ return;
+#endif
+ case 'V':
+ if (_IOC_NR(cmd) >= V4L2_IOCTLS) {
+ type = "v4l2";
+ break;
+ }
+ printk("%s", v4l2_ioctls[_IOC_NR(cmd)]);
+ return;
+ default:
+ type = "unknown";
+ }
+
+ switch (_IOC_DIR(cmd)) {
+ case _IOC_NONE: dir = "--"; break;
+ case _IOC_READ: dir = "r-"; break;
+ case _IOC_WRITE: dir = "-w"; break;
+ case _IOC_READ | _IOC_WRITE: dir = "rw"; break;
+ default: dir = "*ERR*"; break;
+ }
+ printk("%s ioctl '%c', dir=%s, #%d (0x%08x)",
+ type, _IOC_TYPE(cmd), dir, _IOC_NR(cmd), cmd);
+}
+EXPORT_SYMBOL(v4l_printk_ioctl);
+
+/*
+ * helper function -- handles userspace copying for ioctl arguments
+ */
+
+#ifdef __OLD_VIDIOC_
+static unsigned int
+video_fix_command(unsigned int cmd)
+{
+ switch (cmd) {
+ case VIDIOC_OVERLAY_OLD:
+ cmd = VIDIOC_OVERLAY;
+ break;
+ case VIDIOC_S_PARM_OLD:
+ cmd = VIDIOC_S_PARM;
+ break;
+ case VIDIOC_S_CTRL_OLD:
+ cmd = VIDIOC_S_CTRL;
+ break;
+ case VIDIOC_G_AUDIO_OLD:
+ cmd = VIDIOC_G_AUDIO;
+ break;
+ case VIDIOC_G_AUDOUT_OLD:
+ cmd = VIDIOC_G_AUDOUT;
+ break;
+ case VIDIOC_CROPCAP_OLD:
+ cmd = VIDIOC_CROPCAP;
+ break;
+ }
+ return cmd;
+}
+#endif
+
+/*
+ * Obsolete usercopy function - Should be removed soon
+ */
+int
+video_usercopy(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg,
+ int (*func)(struct inode *inode, struct file *file,
+ unsigned int cmd, void *arg))
+{
+ char sbuf[128];
+ void *mbuf = NULL;
+ void *parg = NULL;
+ int err = -EINVAL;
+ int is_ext_ctrl;
+ size_t ctrls_size = 0;
+ void __user *user_ptr = NULL;
+
+#ifdef __OLD_VIDIOC_
+ cmd = video_fix_command(cmd);
+#endif
+ is_ext_ctrl = (cmd == VIDIOC_S_EXT_CTRLS || cmd == VIDIOC_G_EXT_CTRLS ||
+ cmd == VIDIOC_TRY_EXT_CTRLS);
+
+ /* Copy arguments into temp kernel buffer */
+ switch (_IOC_DIR(cmd)) {
+ case _IOC_NONE:
+ parg = NULL;
+ break;
+ case _IOC_READ:
+ case _IOC_WRITE:
+ case (_IOC_WRITE | _IOC_READ):
+ if (_IOC_SIZE(cmd) <= sizeof(sbuf)) {
+ parg = sbuf;
+ } else {
+ /* too big to allocate from stack */
+ mbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL);
+ if (NULL == mbuf)
+ return -ENOMEM;
+ parg = mbuf;
+ }
+
+ err = -EFAULT;
+ if (_IOC_DIR(cmd) & _IOC_WRITE)
+ if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd)))
+ goto out;
+ break;
+ }
+ if (is_ext_ctrl) {
+ struct v4l2_ext_controls *p = parg;
+
+ /* In case of an error, tell the caller that it wasn't
+ a specific control that caused it. */
+ p->error_idx = p->count;
+ user_ptr = (void __user *)p->controls;
+ if (p->count) {
+ ctrls_size = sizeof(struct v4l2_ext_control) * p->count;
+ /* Note: v4l2_ext_controls fits in sbuf[] so mbuf is still NULL. */
+ mbuf = kmalloc(ctrls_size, GFP_KERNEL);
+ err = -ENOMEM;
+ if (NULL == mbuf)
+ goto out_ext_ctrl;
+ err = -EFAULT;
+ if (copy_from_user(mbuf, user_ptr, ctrls_size))
+ goto out_ext_ctrl;
+ p->controls = mbuf;
+ }
+ }
+
+ /* call driver */
+ err = func(inode, file, cmd, parg);
+ if (err == -ENOIOCTLCMD)
+ err = -EINVAL;
+ if (is_ext_ctrl) {
+ struct v4l2_ext_controls *p = parg;
+
+ p->controls = (void *)user_ptr;
+ if (p->count && err == 0 && copy_to_user(user_ptr, mbuf, ctrls_size))
+ err = -EFAULT;
+ goto out_ext_ctrl;
+ }
+ if (err < 0)
+ goto out;
+
+out_ext_ctrl:
+ /* Copy results into user buffer */
+ switch (_IOC_DIR(cmd)) {
+ case _IOC_READ:
+ case (_IOC_WRITE | _IOC_READ):
+ if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd)))
+ err = -EFAULT;
+ break;
+ }
+
+out:
+ kfree(mbuf);
+ return err;
+}
+EXPORT_SYMBOL(video_usercopy);
+
+static void dbgbuf(unsigned int cmd, struct video_device *vfd,
+ struct v4l2_buffer *p)
+{
+ struct v4l2_timecode *tc = &p->timecode;
+
+ dbgarg(cmd, "%02ld:%02d:%02d.%08ld index=%d, type=%s, "
+ "bytesused=%d, flags=0x%08d, "
+ "field=%0d, sequence=%d, memory=%s, offset/userptr=0x%08lx, length=%d\n",
+ p->timestamp.tv_sec / 3600,
+ (int)(p->timestamp.tv_sec / 60) % 60,
+ (int)(p->timestamp.tv_sec % 60),
+ p->timestamp.tv_usec,
+ p->index,
+ prt_names(p->type, v4l2_type_names),
+ p->bytesused, p->flags,
+ p->field, p->sequence,
+ prt_names(p->memory, v4l2_memory_names),
+ p->m.userptr, p->length);
+ dbgarg2("timecode=%02d:%02d:%02d type=%d, "
+ "flags=0x%08d, frames=%d, userbits=0x%08x\n",
+ tc->hours, tc->minutes, tc->seconds,
+ tc->type, tc->flags, tc->frames, *(__u32 *)tc->userbits);
+}
+
+static inline void dbgrect(struct video_device *vfd, char *s,
+ struct v4l2_rect *r)
+{
+ dbgarg2("%sRect start at %dx%d, size=%dx%d\n", s, r->left, r->top,
+ r->width, r->height);
+};
+
+static inline void v4l_print_pix_fmt(struct video_device *vfd,
+ struct v4l2_pix_format *fmt)
+{
+ dbgarg2("width=%d, height=%d, format=%c%c%c%c, field=%s, "
+ "bytesperline=%d sizeimage=%d, colorspace=%d\n",
+ fmt->width, fmt->height,
+ (fmt->pixelformat & 0xff),
+ (fmt->pixelformat >> 8) & 0xff,
+ (fmt->pixelformat >> 16) & 0xff,
+ (fmt->pixelformat >> 24) & 0xff,
+ prt_names(fmt->field, v4l2_field_names),
+ fmt->bytesperline, fmt->sizeimage, fmt->colorspace);
+};
+
+static inline void v4l_print_ext_ctrls(unsigned int cmd,
+ struct video_device *vfd, struct v4l2_ext_controls *c, int show_vals)
+{
+ __u32 i;
+
+ if (!(vfd->debug & V4L2_DEBUG_IOCTL_ARG))
+ return;
+ dbgarg(cmd, "");
+ printk(KERN_CONT "class=0x%x", c->ctrl_class);
+ for (i = 0; i < c->count; i++) {
+ if (show_vals)
+ printk(KERN_CONT " id/val=0x%x/0x%x",
+ c->controls[i].id, c->controls[i].value);
+ else
+ printk(KERN_CONT " id=0x%x", c->controls[i].id);
+ }
+ printk(KERN_CONT "\n");
+};
+
+static inline int check_ext_ctrls(struct v4l2_ext_controls *c, int allow_priv)
+{
+ __u32 i;
+
+ /* zero the reserved fields */
+ c->reserved[0] = c->reserved[1] = 0;
+ for (i = 0; i < c->count; i++) {
+ c->controls[i].reserved2[0] = 0;
+ c->controls[i].reserved2[1] = 0;
+ }
+ /* V4L2_CID_PRIVATE_BASE cannot be used as control class
+ when using extended controls.
+ Only when passed in through VIDIOC_G_CTRL and VIDIOC_S_CTRL
+ is it allowed for backwards compatibility.
+ */
+ if (!allow_priv && c->ctrl_class == V4L2_CID_PRIVATE_BASE)
+ return 0;
+ /* Check that all controls are from the same control class. */
+ for (i = 0; i < c->count; i++) {
+ if (V4L2_CTRL_ID2CLASS(c->controls[i].id) != c->ctrl_class) {
+ c->error_idx = i;
+ return 0;
+ }
+ }
+ return 1;
+}
+
+static int check_fmt(const struct v4l2_ioctl_ops *ops, enum v4l2_buf_type type)
+{
+ if (ops == NULL)
+ return -EINVAL;
+
+ switch (type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ if (ops->vidioc_try_fmt_vid_cap)
+ return 0;
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ if (ops->vidioc_try_fmt_vid_overlay)
+ return 0;
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ if (ops->vidioc_try_fmt_vid_out)
+ return 0;
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY:
+ if (ops->vidioc_try_fmt_vid_out_overlay)
+ return 0;
+ break;
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ if (ops->vidioc_try_fmt_vbi_cap)
+ return 0;
+ break;
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ if (ops->vidioc_try_fmt_vbi_out)
+ return 0;
+ break;
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ if (ops->vidioc_try_fmt_sliced_vbi_cap)
+ return 0;
+ break;
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ if (ops->vidioc_try_fmt_sliced_vbi_out)
+ return 0;
+ break;
+ case V4L2_BUF_TYPE_PRIVATE:
+ if (ops->vidioc_try_fmt_type_private)
+ return 0;
+ break;
+ }
+ return -EINVAL;
+}
+
+static int __video_do_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, void *arg)
+{
+ struct video_device *vfd = video_devdata(file);
+ const struct v4l2_ioctl_ops *ops = vfd->ioctl_ops;
+ void *fh = file->private_data;
+ int ret = -EINVAL;
+
+ if ((vfd->debug & V4L2_DEBUG_IOCTL) &&
+ !(vfd->debug & V4L2_DEBUG_IOCTL_ARG)) {
+ v4l_print_ioctl(vfd->name, cmd);
+ printk(KERN_CONT "\n");
+ }
+
+ if (ops == NULL) {
+ printk(KERN_WARNING "videodev: \"%s\" has no ioctl_ops.\n",
+ vfd->name);
+ return -EINVAL;
+ }
+
+#ifdef CONFIG_VIDEO_V4L1_COMPAT
+ /***********************************************************
+ Handles calls to the obsoleted V4L1 API
+ Due to the nature of VIDIOCGMBUF, each driver that supports
+ V4L1 should implement its own handler for this ioctl.
+ ***********************************************************/
+
+ /* --- streaming capture ------------------------------------- */
+ if (cmd == VIDIOCGMBUF) {
+ struct video_mbuf *p = arg;
+
+ memset(p, 0, sizeof(*p));
+
+ if (!ops->vidiocgmbuf)
+ return ret;
+ ret = ops->vidiocgmbuf(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "size=%d, frames=%d, offsets=0x%08lx\n",
+ p->size, p->frames,
+ (unsigned long)p->offsets);
+ return ret;
+ }
+
+ /********************************************************
+ All other V4L1 calls are handled by v4l1_compat module.
+ Those calls will be translated into V4L2 calls, and
+ __video_do_ioctl will be called again, with one or more
+ V4L2 ioctls.
+ ********************************************************/
+ if (_IOC_TYPE(cmd) == 'v')
+ return v4l_compat_translate_ioctl(inode, file, cmd, arg,
+ __video_do_ioctl);
+#endif
+
+ switch (cmd) {
+ /* --- capabilities ------------------------------------------ */
+ case VIDIOC_QUERYCAP:
+ {
+ struct v4l2_capability *cap = (struct v4l2_capability *)arg;
+ memset(cap, 0, sizeof(*cap));
+
+ if (!ops->vidioc_querycap)
+ break;
+
+ ret = ops->vidioc_querycap(file, fh, cap);
+ if (!ret)
+ dbgarg(cmd, "driver=%s, card=%s, bus=%s, "
+ "version=0x%08x, "
+ "capabilities=0x%08x\n",
+ cap->driver, cap->card, cap->bus_info,
+ cap->version,
+ cap->capabilities);
+ break;
+ }
+
+ /* --- priority ------------------------------------------ */
+ case VIDIOC_G_PRIORITY:
+ {
+ enum v4l2_priority *p = arg;
+
+ if (!ops->vidioc_g_priority)
+ break;
+ ret = ops->vidioc_g_priority(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "priority is %d\n", *p);
+ break;
+ }
+ case VIDIOC_S_PRIORITY:
+ {
+ enum v4l2_priority *p = arg;
+
+ if (!ops->vidioc_s_priority)
+ break;
+ dbgarg(cmd, "setting priority to %d\n", *p);
+ ret = ops->vidioc_s_priority(file, fh, *p);
+ break;
+ }
+
+ /* --- capture ioctls ---------------------------------------- */
+ case VIDIOC_ENUM_FMT:
+ {
+ struct v4l2_fmtdesc *f = arg;
+ enum v4l2_buf_type type;
+ unsigned int index;
+
+ index = f->index;
+ type = f->type;
+ memset(f, 0, sizeof(*f));
+ f->index = index;
+ f->type = type;
+
+ switch (type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ if (ops->vidioc_enum_fmt_vid_cap)
+ ret = ops->vidioc_enum_fmt_vid_cap(file, fh, f);
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ if (ops->vidioc_enum_fmt_vid_overlay)
+ ret = ops->vidioc_enum_fmt_vid_overlay(file,
+ fh, f);
+ break;
+#if 1
+ /* V4L2_BUF_TYPE_VBI_CAPTURE should not support VIDIOC_ENUM_FMT
+ * according to the spec. The bttv and saa7134 drivers support
+ * it though, so just warn that this is deprecated and will be
+ * removed in the near future. */
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ if (ops->vidioc_enum_fmt_vbi_cap) {
+ printk(KERN_WARNING "vidioc_enum_fmt_vbi_cap will be removed in 2.6.28!\n");
+ ret = ops->vidioc_enum_fmt_vbi_cap(file, fh, f);
+ }
+ break;
+#endif
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ if (ops->vidioc_enum_fmt_vid_out)
+ ret = ops->vidioc_enum_fmt_vid_out(file, fh, f);
+ break;
+ case V4L2_BUF_TYPE_PRIVATE:
+ if (ops->vidioc_enum_fmt_type_private)
+ ret = ops->vidioc_enum_fmt_type_private(file,
+ fh, f);
+ break;
+ default:
+ break;
+ }
+ if (!ret)
+ dbgarg(cmd, "index=%d, type=%d, flags=%d, "
+ "pixelformat=%c%c%c%c, description='%s'\n",
+ f->index, f->type, f->flags,
+ (f->pixelformat & 0xff),
+ (f->pixelformat >> 8) & 0xff,
+ (f->pixelformat >> 16) & 0xff,
+ (f->pixelformat >> 24) & 0xff,
+ f->description);
+ break;
+ }
+ case VIDIOC_G_FMT:
+ {
+ struct v4l2_format *f = (struct v4l2_format *)arg;
+
+ memset(f->fmt.raw_data, 0, sizeof(f->fmt.raw_data));
+
+ /* FIXME: Should be one dump per type */
+ dbgarg(cmd, "type=%s\n", prt_names(f->type, v4l2_type_names));
+
+ switch (f->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ if (ops->vidioc_g_fmt_vid_cap)
+ ret = ops->vidioc_g_fmt_vid_cap(file, fh, f);
+ if (!ret)
+ v4l_print_pix_fmt(vfd, &f->fmt.pix);
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ if (ops->vidioc_g_fmt_vid_overlay)
+ ret = ops->vidioc_g_fmt_vid_overlay(file,
+ fh, f);
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ if (ops->vidioc_g_fmt_vid_out)
+ ret = ops->vidioc_g_fmt_vid_out(file, fh, f);
+ if (!ret)
+ v4l_print_pix_fmt(vfd, &f->fmt.pix);
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY:
+ if (ops->vidioc_g_fmt_vid_out_overlay)
+ ret = ops->vidioc_g_fmt_vid_out_overlay(file,
+ fh, f);
+ break;
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ if (ops->vidioc_g_fmt_vbi_cap)
+ ret = ops->vidioc_g_fmt_vbi_cap(file, fh, f);
+ break;
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ if (ops->vidioc_g_fmt_vbi_out)
+ ret = ops->vidioc_g_fmt_vbi_out(file, fh, f);
+ break;
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ if (ops->vidioc_g_fmt_sliced_vbi_cap)
+ ret = ops->vidioc_g_fmt_sliced_vbi_cap(file,
+ fh, f);
+ break;
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ if (ops->vidioc_g_fmt_sliced_vbi_out)
+ ret = ops->vidioc_g_fmt_sliced_vbi_out(file,
+ fh, f);
+ break;
+ case V4L2_BUF_TYPE_PRIVATE:
+ if (ops->vidioc_g_fmt_type_private)
+ ret = ops->vidioc_g_fmt_type_private(file,
+ fh, f);
+ break;
+ }
+
+ break;
+ }
+ case VIDIOC_S_FMT:
+ {
+ struct v4l2_format *f = (struct v4l2_format *)arg;
+
+ /* FIXME: Should be one dump per type */
+ dbgarg(cmd, "type=%s\n", prt_names(f->type, v4l2_type_names));
+
+ switch (f->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ v4l_print_pix_fmt(vfd, &f->fmt.pix);
+ if (ops->vidioc_s_fmt_vid_cap)
+ ret = ops->vidioc_s_fmt_vid_cap(file, fh, f);
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ if (ops->vidioc_s_fmt_vid_overlay)
+ ret = ops->vidioc_s_fmt_vid_overlay(file,
+ fh, f);
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ v4l_print_pix_fmt(vfd, &f->fmt.pix);
+ if (ops->vidioc_s_fmt_vid_out)
+ ret = ops->vidioc_s_fmt_vid_out(file, fh, f);
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY:
+ if (ops->vidioc_s_fmt_vid_out_overlay)
+ ret = ops->vidioc_s_fmt_vid_out_overlay(file,
+ fh, f);
+ break;
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ if (ops->vidioc_s_fmt_vbi_cap)
+ ret = ops->vidioc_s_fmt_vbi_cap(file, fh, f);
+ break;
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ if (ops->vidioc_s_fmt_vbi_out)
+ ret = ops->vidioc_s_fmt_vbi_out(file, fh, f);
+ break;
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ if (ops->vidioc_s_fmt_sliced_vbi_cap)
+ ret = ops->vidioc_s_fmt_sliced_vbi_cap(file,
+ fh, f);
+ break;
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ if (ops->vidioc_s_fmt_sliced_vbi_out)
+ ret = ops->vidioc_s_fmt_sliced_vbi_out(file,
+ fh, f);
+ break;
+ case V4L2_BUF_TYPE_PRIVATE:
+ if (ops->vidioc_s_fmt_type_private)
+ ret = ops->vidioc_s_fmt_type_private(file,
+ fh, f);
+ break;
+ }
+ break;
+ }
+ case VIDIOC_TRY_FMT:
+ {
+ struct v4l2_format *f = (struct v4l2_format *)arg;
+
+ /* FIXME: Should be one dump per type */
+ dbgarg(cmd, "type=%s\n", prt_names(f->type,
+ v4l2_type_names));
+ switch (f->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ if (ops->vidioc_try_fmt_vid_cap)
+ ret = ops->vidioc_try_fmt_vid_cap(file, fh, f);
+ if (!ret)
+ v4l_print_pix_fmt(vfd, &f->fmt.pix);
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ if (ops->vidioc_try_fmt_vid_overlay)
+ ret = ops->vidioc_try_fmt_vid_overlay(file,
+ fh, f);
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ if (ops->vidioc_try_fmt_vid_out)
+ ret = ops->vidioc_try_fmt_vid_out(file, fh, f);
+ if (!ret)
+ v4l_print_pix_fmt(vfd, &f->fmt.pix);
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY:
+ if (ops->vidioc_try_fmt_vid_out_overlay)
+ ret = ops->vidioc_try_fmt_vid_out_overlay(file,
+ fh, f);
+ break;
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ if (ops->vidioc_try_fmt_vbi_cap)
+ ret = ops->vidioc_try_fmt_vbi_cap(file, fh, f);
+ break;
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ if (ops->vidioc_try_fmt_vbi_out)
+ ret = ops->vidioc_try_fmt_vbi_out(file, fh, f);
+ break;
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ if (ops->vidioc_try_fmt_sliced_vbi_cap)
+ ret = ops->vidioc_try_fmt_sliced_vbi_cap(file,
+ fh, f);
+ break;
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ if (ops->vidioc_try_fmt_sliced_vbi_out)
+ ret = ops->vidioc_try_fmt_sliced_vbi_out(file,
+ fh, f);
+ break;
+ case V4L2_BUF_TYPE_PRIVATE:
+ if (ops->vidioc_try_fmt_type_private)
+ ret = ops->vidioc_try_fmt_type_private(file,
+ fh, f);
+ break;
+ }
+
+ break;
+ }
+ /* FIXME: Those buf reqs could be handled here,
+ with some changes on videobuf to allow its header to be included at
+ videodev2.h or being merged at videodev2.
+ */
+ case VIDIOC_REQBUFS:
+ {
+ struct v4l2_requestbuffers *p = arg;
+
+ if (!ops->vidioc_reqbufs)
+ break;
+ ret = check_fmt(ops, p->type);
+ if (ret)
+ break;
+
+ ret = ops->vidioc_reqbufs(file, fh, p);
+ dbgarg(cmd, "count=%d, type=%s, memory=%s\n",
+ p->count,
+ prt_names(p->type, v4l2_type_names),
+ prt_names(p->memory, v4l2_memory_names));
+ break;
+ }
+ case VIDIOC_QUERYBUF:
+ {
+ struct v4l2_buffer *p = arg;
+
+ if (!ops->vidioc_querybuf)
+ break;
+ ret = check_fmt(ops, p->type);
+ if (ret)
+ break;
+
+ ret = ops->vidioc_querybuf(file, fh, p);
+ if (!ret)
+ dbgbuf(cmd, vfd, p);
+ break;
+ }
+ case VIDIOC_QBUF:
+ {
+ struct v4l2_buffer *p = arg;
+
+ if (!ops->vidioc_qbuf)
+ break;
+ ret = check_fmt(ops, p->type);
+ if (ret)
+ break;
+
+ ret = ops->vidioc_qbuf(file, fh, p);
+ if (!ret)
+ dbgbuf(cmd, vfd, p);
+ break;
+ }
+ case VIDIOC_DQBUF:
+ {
+ struct v4l2_buffer *p = arg;
+
+ if (!ops->vidioc_dqbuf)
+ break;
+ ret = check_fmt(ops, p->type);
+ if (ret)
+ break;
+
+ ret = ops->vidioc_dqbuf(file, fh, p);
+ if (!ret)
+ dbgbuf(cmd, vfd, p);
+ break;
+ }
+ case VIDIOC_OVERLAY:
+ {
+ int *i = arg;
+
+ if (!ops->vidioc_overlay)
+ break;
+ dbgarg(cmd, "value=%d\n", *i);
+ ret = ops->vidioc_overlay(file, fh, *i);
+ break;
+ }
+ case VIDIOC_G_FBUF:
+ {
+ struct v4l2_framebuffer *p = arg;
+
+ if (!ops->vidioc_g_fbuf)
+ break;
+ ret = ops->vidioc_g_fbuf(file, fh, arg);
+ if (!ret) {
+ dbgarg(cmd, "capability=0x%x, flags=%d, base=0x%08lx\n",
+ p->capability, p->flags,
+ (unsigned long)p->base);
+ v4l_print_pix_fmt(vfd, &p->fmt);
+ }
+ break;
+ }
+ case VIDIOC_S_FBUF:
+ {
+ struct v4l2_framebuffer *p = arg;
+
+ if (!ops->vidioc_s_fbuf)
+ break;
+ dbgarg(cmd, "capability=0x%x, flags=%d, base=0x%08lx\n",
+ p->capability, p->flags, (unsigned long)p->base);
+ v4l_print_pix_fmt(vfd, &p->fmt);
+ ret = ops->vidioc_s_fbuf(file, fh, arg);
+ break;
+ }
+ case VIDIOC_STREAMON:
+ {
+ enum v4l2_buf_type i = *(int *)arg;
+
+ if (!ops->vidioc_streamon)
+ break;
+ dbgarg(cmd, "type=%s\n", prt_names(i, v4l2_type_names));
+ ret = ops->vidioc_streamon(file, fh, i);
+ break;
+ }
+ case VIDIOC_STREAMOFF:
+ {
+ enum v4l2_buf_type i = *(int *)arg;
+
+ if (!ops->vidioc_streamoff)
+ break;
+ dbgarg(cmd, "type=%s\n", prt_names(i, v4l2_type_names));
+ ret = ops->vidioc_streamoff(file, fh, i);
+ break;
+ }
+ /* ---------- tv norms ---------- */
+ case VIDIOC_ENUMSTD:
+ {
+ struct v4l2_standard *p = arg;
+ v4l2_std_id id = vfd->tvnorms, curr_id = 0;
+ unsigned int index = p->index, i, j = 0;
+ const char *descr = "";
+
+ /* Return norm array in a canonical way */
+ for (i = 0; i <= index && id; i++) {
+ /* last std value in the standards array is 0, so this
+ while always ends there since (id & 0) == 0. */
+ while ((id & standards[j].std) != standards[j].std)
+ j++;
+ curr_id = standards[j].std;
+ descr = standards[j].descr;
+ j++;
+ if (curr_id == 0)
+ break;
+ if (curr_id != V4L2_STD_PAL &&
+ curr_id != V4L2_STD_SECAM &&
+ curr_id != V4L2_STD_NTSC)
+ id &= ~curr_id;
+ }
+ if (i <= index)
+ return -EINVAL;
+
+ v4l2_video_std_construct(p, curr_id, descr);
+ p->index = index;
+
+ dbgarg(cmd, "index=%d, id=0x%Lx, name=%s, fps=%d/%d, "
+ "framelines=%d\n", p->index,
+ (unsigned long long)p->id, p->name,
+ p->frameperiod.numerator,
+ p->frameperiod.denominator,
+ p->framelines);
+
+ ret = 0;
+ break;
+ }
+ case VIDIOC_G_STD:
+ {
+ v4l2_std_id *id = arg;
+
+ ret = 0;
+ /* Calls the specific handler */
+ if (ops->vidioc_g_std)
+ ret = ops->vidioc_g_std(file, fh, id);
+ else
+ *id = vfd->current_norm;
+
+ if (!ret)
+ dbgarg(cmd, "std=0x%08Lx\n", (long long unsigned)*id);
+ break;
+ }
+ case VIDIOC_S_STD:
+ {
+ v4l2_std_id *id = arg, norm;
+
+ dbgarg(cmd, "std=%08Lx\n", (long long unsigned)*id);
+
+ norm = (*id) & vfd->tvnorms;
+ if (vfd->tvnorms && !norm) /* Check if std is supported */
+ break;
+
+ /* Calls the specific handler */
+ if (ops->vidioc_s_std)
+ ret = ops->vidioc_s_std(file, fh, &norm);
+ else
+ ret = -EINVAL;
+
+ /* Updates standard information */
+ if (ret >= 0)
+ vfd->current_norm = norm;
+ break;
+ }
+ case VIDIOC_QUERYSTD:
+ {
+ v4l2_std_id *p = arg;
+
+ if (!ops->vidioc_querystd)
+ break;
+ ret = ops->vidioc_querystd(file, fh, arg);
+ if (!ret)
+ dbgarg(cmd, "detected std=%08Lx\n",
+ (unsigned long long)*p);
+ break;
+ }
+ /* ------ input switching ---------- */
+ /* FIXME: Inputs can be handled inside videodev2 */
+ case VIDIOC_ENUMINPUT:
+ {
+ struct v4l2_input *p = arg;
+ int i = p->index;
+
+ if (!ops->vidioc_enum_input)
+ break;
+ memset(p, 0, sizeof(*p));
+ p->index = i;
+
+ ret = ops->vidioc_enum_input(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "index=%d, name=%s, type=%d, "
+ "audioset=%d, "
+ "tuner=%d, std=%08Lx, status=%d\n",
+ p->index, p->name, p->type, p->audioset,
+ p->tuner,
+ (unsigned long long)p->std,
+ p->status);
+ break;
+ }
+ case VIDIOC_G_INPUT:
+ {
+ unsigned int *i = arg;
+
+ if (!ops->vidioc_g_input)
+ break;
+ ret = ops->vidioc_g_input(file, fh, i);
+ if (!ret)
+ dbgarg(cmd, "value=%d\n", *i);
+ break;
+ }
+ case VIDIOC_S_INPUT:
+ {
+ unsigned int *i = arg;
+
+ if (!ops->vidioc_s_input)
+ break;
+ dbgarg(cmd, "value=%d\n", *i);
+ ret = ops->vidioc_s_input(file, fh, *i);
+ break;
+ }
+
+ /* ------ output switching ---------- */
+ case VIDIOC_ENUMOUTPUT:
+ {
+ struct v4l2_output *p = arg;
+ int i = p->index;
+
+ if (!ops->vidioc_enum_output)
+ break;
+ memset(p, 0, sizeof(*p));
+ p->index = i;
+
+ ret = ops->vidioc_enum_output(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "index=%d, name=%s, type=%d, "
+ "audioset=0x%x, "
+ "modulator=%d, std=0x%08Lx\n",
+ p->index, p->name, p->type, p->audioset,
+ p->modulator, (unsigned long long)p->std);
+ break;
+ }
+ case VIDIOC_G_OUTPUT:
+ {
+ unsigned int *i = arg;
+
+ if (!ops->vidioc_g_output)
+ break;
+ ret = ops->vidioc_g_output(file, fh, i);
+ if (!ret)
+ dbgarg(cmd, "value=%d\n", *i);
+ break;
+ }
+ case VIDIOC_S_OUTPUT:
+ {
+ unsigned int *i = arg;
+
+ if (!ops->vidioc_s_output)
+ break;
+ dbgarg(cmd, "value=%d\n", *i);
+ ret = ops->vidioc_s_output(file, fh, *i);
+ break;
+ }
+
+ /* --- controls ---------------------------------------------- */
+ case VIDIOC_QUERYCTRL:
+ {
+ struct v4l2_queryctrl *p = arg;
+
+ if (!ops->vidioc_queryctrl)
+ break;
+ ret = ops->vidioc_queryctrl(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "id=0x%x, type=%d, name=%s, min/max=%d/%d, "
+ "step=%d, default=%d, flags=0x%08x\n",
+ p->id, p->type, p->name,
+ p->minimum, p->maximum,
+ p->step, p->default_value, p->flags);
+ else
+ dbgarg(cmd, "id=0x%x\n", p->id);
+ break;
+ }
+ case VIDIOC_G_CTRL:
+ {
+ struct v4l2_control *p = arg;
+
+ if (ops->vidioc_g_ctrl)
+ ret = ops->vidioc_g_ctrl(file, fh, p);
+ else if (ops->vidioc_g_ext_ctrls) {
+ struct v4l2_ext_controls ctrls;
+ struct v4l2_ext_control ctrl;
+
+ ctrls.ctrl_class = V4L2_CTRL_ID2CLASS(p->id);
+ ctrls.count = 1;
+ ctrls.controls = &ctrl;
+ ctrl.id = p->id;
+ ctrl.value = p->value;
+ if (check_ext_ctrls(&ctrls, 1)) {
+ ret = ops->vidioc_g_ext_ctrls(file, fh, &ctrls);
+ if (ret == 0)
+ p->value = ctrl.value;
+ }
+ } else
+ break;
+ if (!ret)
+ dbgarg(cmd, "id=0x%x, value=%d\n", p->id, p->value);
+ else
+ dbgarg(cmd, "id=0x%x\n", p->id);
+ break;
+ }
+ case VIDIOC_S_CTRL:
+ {
+ struct v4l2_control *p = arg;
+ struct v4l2_ext_controls ctrls;
+ struct v4l2_ext_control ctrl;
+
+ if (!ops->vidioc_s_ctrl && !ops->vidioc_s_ext_ctrls)
+ break;
+
+ dbgarg(cmd, "id=0x%x, value=%d\n", p->id, p->value);
+
+ if (ops->vidioc_s_ctrl) {
+ ret = ops->vidioc_s_ctrl(file, fh, p);
+ break;
+ }
+ if (!ops->vidioc_s_ext_ctrls)
+ break;
+
+ ctrls.ctrl_class = V4L2_CTRL_ID2CLASS(p->id);
+ ctrls.count = 1;
+ ctrls.controls = &ctrl;
+ ctrl.id = p->id;
+ ctrl.value = p->value;
+ if (check_ext_ctrls(&ctrls, 1))
+ ret = ops->vidioc_s_ext_ctrls(file, fh, &ctrls);
+ break;
+ }
+ case VIDIOC_G_EXT_CTRLS:
+ {
+ struct v4l2_ext_controls *p = arg;
+
+ p->error_idx = p->count;
+ if (!ops->vidioc_g_ext_ctrls)
+ break;
+ if (check_ext_ctrls(p, 0))
+ ret = ops->vidioc_g_ext_ctrls(file, fh, p);
+ v4l_print_ext_ctrls(cmd, vfd, p, !ret);
+ break;
+ }
+ case VIDIOC_S_EXT_CTRLS:
+ {
+ struct v4l2_ext_controls *p = arg;
+
+ p->error_idx = p->count;
+ if (!ops->vidioc_s_ext_ctrls)
+ break;
+ v4l_print_ext_ctrls(cmd, vfd, p, 1);
+ if (check_ext_ctrls(p, 0))
+ ret = ops->vidioc_s_ext_ctrls(file, fh, p);
+ break;
+ }
+ case VIDIOC_TRY_EXT_CTRLS:
+ {
+ struct v4l2_ext_controls *p = arg;
+
+ p->error_idx = p->count;
+ if (!ops->vidioc_try_ext_ctrls)
+ break;
+ v4l_print_ext_ctrls(cmd, vfd, p, 1);
+ if (check_ext_ctrls(p, 0))
+ ret = ops->vidioc_try_ext_ctrls(file, fh, p);
+ break;
+ }
+ case VIDIOC_QUERYMENU:
+ {
+ struct v4l2_querymenu *p = arg;
+
+ if (!ops->vidioc_querymenu)
+ break;
+ ret = ops->vidioc_querymenu(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "id=0x%x, index=%d, name=%s\n",
+ p->id, p->index, p->name);
+ else
+ dbgarg(cmd, "id=0x%x, index=%d\n",
+ p->id, p->index);
+ break;
+ }
+ /* --- audio ---------------------------------------------- */
+ case VIDIOC_ENUMAUDIO:
+ {
+ struct v4l2_audio *p = arg;
+
+ if (!ops->vidioc_enumaudio)
+ break;
+ ret = ops->vidioc_enumaudio(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "index=%d, name=%s, capability=0x%x, "
+ "mode=0x%x\n", p->index, p->name,
+ p->capability, p->mode);
+ else
+ dbgarg(cmd, "index=%d\n", p->index);
+ break;
+ }
+ case VIDIOC_G_AUDIO:
+ {
+ struct v4l2_audio *p = arg;
+ __u32 index = p->index;
+
+ if (!ops->vidioc_g_audio)
+ break;
+
+ memset(p, 0, sizeof(*p));
+ p->index = index;
+ ret = ops->vidioc_g_audio(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "index=%d, name=%s, capability=0x%x, "
+ "mode=0x%x\n", p->index,
+ p->name, p->capability, p->mode);
+ else
+ dbgarg(cmd, "index=%d\n", p->index);
+ break;
+ }
+ case VIDIOC_S_AUDIO:
+ {
+ struct v4l2_audio *p = arg;
+
+ if (!ops->vidioc_s_audio)
+ break;
+ dbgarg(cmd, "index=%d, name=%s, capability=0x%x, "
+ "mode=0x%x\n", p->index, p->name,
+ p->capability, p->mode);
+ ret = ops->vidioc_s_audio(file, fh, p);
+ break;
+ }
+ case VIDIOC_ENUMAUDOUT:
+ {
+ struct v4l2_audioout *p = arg;
+
+ if (!ops->vidioc_enumaudout)
+ break;
+ dbgarg(cmd, "Enum for index=%d\n", p->index);
+ ret = ops->vidioc_enumaudout(file, fh, p);
+ if (!ret)
+ dbgarg2("index=%d, name=%s, capability=%d, "
+ "mode=%d\n", p->index, p->name,
+ p->capability, p->mode);
+ break;
+ }
+ case VIDIOC_G_AUDOUT:
+ {
+ struct v4l2_audioout *p = arg;
+
+ if (!ops->vidioc_g_audout)
+ break;
+ dbgarg(cmd, "Enum for index=%d\n", p->index);
+ ret = ops->vidioc_g_audout(file, fh, p);
+ if (!ret)
+ dbgarg2("index=%d, name=%s, capability=%d, "
+ "mode=%d\n", p->index, p->name,
+ p->capability, p->mode);
+ break;
+ }
+ case VIDIOC_S_AUDOUT:
+ {
+ struct v4l2_audioout *p = arg;
+
+ if (!ops->vidioc_s_audout)
+ break;
+ dbgarg(cmd, "index=%d, name=%s, capability=%d, "
+ "mode=%d\n", p->index, p->name,
+ p->capability, p->mode);
+
+ ret = ops->vidioc_s_audout(file, fh, p);
+ break;
+ }
+ case VIDIOC_G_MODULATOR:
+ {
+ struct v4l2_modulator *p = arg;
+
+ if (!ops->vidioc_g_modulator)
+ break;
+ ret = ops->vidioc_g_modulator(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "index=%d, name=%s, "
+ "capability=%d, rangelow=%d,"
+ " rangehigh=%d, txsubchans=%d\n",
+ p->index, p->name, p->capability,
+ p->rangelow, p->rangehigh,
+ p->txsubchans);
+ break;
+ }
+ case VIDIOC_S_MODULATOR:
+ {
+ struct v4l2_modulator *p = arg;
+
+ if (!ops->vidioc_s_modulator)
+ break;
+ dbgarg(cmd, "index=%d, name=%s, capability=%d, "
+ "rangelow=%d, rangehigh=%d, txsubchans=%d\n",
+ p->index, p->name, p->capability, p->rangelow,
+ p->rangehigh, p->txsubchans);
+ ret = ops->vidioc_s_modulator(file, fh, p);
+ break;
+ }
+ case VIDIOC_G_CROP:
+ {
+ struct v4l2_crop *p = arg;
+
+ if (!ops->vidioc_g_crop)
+ break;
+ dbgarg(cmd, "type=%s\n", prt_names(p->type, v4l2_type_names));
+ ret = ops->vidioc_g_crop(file, fh, p);
+ if (!ret)
+ dbgrect(vfd, "", &p->c);
+ break;
+ }
+ case VIDIOC_S_CROP:
+ {
+ struct v4l2_crop *p = arg;
+
+ if (!ops->vidioc_s_crop)
+ break;
+ dbgarg(cmd, "type=%s\n", prt_names(p->type, v4l2_type_names));
+ dbgrect(vfd, "", &p->c);
+ ret = ops->vidioc_s_crop(file, fh, p);
+ break;
+ }
+ case VIDIOC_CROPCAP:
+ {
+ struct v4l2_cropcap *p = arg;
+
+ /*FIXME: Should also show v4l2_fract pixelaspect */
+ if (!ops->vidioc_cropcap)
+ break;
+ dbgarg(cmd, "type=%s\n", prt_names(p->type, v4l2_type_names));
+ ret = ops->vidioc_cropcap(file, fh, p);
+ if (!ret) {
+ dbgrect(vfd, "bounds ", &p->bounds);
+ dbgrect(vfd, "defrect ", &p->defrect);
+ }
+ break;
+ }
+ case VIDIOC_G_JPEGCOMP:
+ {
+ struct v4l2_jpegcompression *p = arg;
+
+ if (!ops->vidioc_g_jpegcomp)
+ break;
+ ret = ops->vidioc_g_jpegcomp(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "quality=%d, APPn=%d, "
+ "APP_len=%d, COM_len=%d, "
+ "jpeg_markers=%d\n",
+ p->quality, p->APPn, p->APP_len,
+ p->COM_len, p->jpeg_markers);
+ break;
+ }
+ case VIDIOC_S_JPEGCOMP:
+ {
+ struct v4l2_jpegcompression *p = arg;
+
+ if (!ops->vidioc_g_jpegcomp)
+ break;
+ dbgarg(cmd, "quality=%d, APPn=%d, APP_len=%d, "
+ "COM_len=%d, jpeg_markers=%d\n",
+ p->quality, p->APPn, p->APP_len,
+ p->COM_len, p->jpeg_markers);
+ ret = ops->vidioc_s_jpegcomp(file, fh, p);
+ break;
+ }
+ case VIDIOC_G_ENC_INDEX:
+ {
+ struct v4l2_enc_idx *p = arg;
+
+ if (!ops->vidioc_g_enc_index)
+ break;
+ ret = ops->vidioc_g_enc_index(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "entries=%d, entries_cap=%d\n",
+ p->entries, p->entries_cap);
+ break;
+ }
+ case VIDIOC_ENCODER_CMD:
+ {
+ struct v4l2_encoder_cmd *p = arg;
+
+ if (!ops->vidioc_encoder_cmd)
+ break;
+ memset(&p->raw, 0, sizeof(p->raw));
+ ret = ops->vidioc_encoder_cmd(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "cmd=%d, flags=%x\n", p->cmd, p->flags);
+ break;
+ }
+ case VIDIOC_TRY_ENCODER_CMD:
+ {
+ struct v4l2_encoder_cmd *p = arg;
+
+ if (!ops->vidioc_try_encoder_cmd)
+ break;
+ memset(&p->raw, 0, sizeof(p->raw));
+ ret = ops->vidioc_try_encoder_cmd(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "cmd=%d, flags=%x\n", p->cmd, p->flags);
+ break;
+ }
+ case VIDIOC_G_PARM:
+ {
+ struct v4l2_streamparm *p = arg;
+ __u32 type = p->type;
+
+ memset(p, 0, sizeof(*p));
+ p->type = type;
+
+ if (ops->vidioc_g_parm) {
+ ret = ops->vidioc_g_parm(file, fh, p);
+ } else {
+ struct v4l2_standard s;
+
+ if (p->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+
+ v4l2_video_std_construct(&s, vfd->current_norm,
+ v4l2_norm_to_name(vfd->current_norm));
+
+ p->parm.capture.timeperframe = s.frameperiod;
+ ret = 0;
+ }
+
+ dbgarg(cmd, "type=%d\n", p->type);
+ break;
+ }
+ case VIDIOC_S_PARM:
+ {
+ struct v4l2_streamparm *p = arg;
+
+ if (!ops->vidioc_s_parm)
+ break;
+ dbgarg(cmd, "type=%d\n", p->type);
+ ret = ops->vidioc_s_parm(file, fh, p);
+ break;
+ }
+ case VIDIOC_G_TUNER:
+ {
+ struct v4l2_tuner *p = arg;
+ __u32 index = p->index;
+
+ if (!ops->vidioc_g_tuner)
+ break;
+
+ memset(p, 0, sizeof(*p));
+ p->index = index;
+
+ ret = ops->vidioc_g_tuner(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "index=%d, name=%s, type=%d, "
+ "capability=0x%x, rangelow=%d, "
+ "rangehigh=%d, signal=%d, afc=%d, "
+ "rxsubchans=0x%x, audmode=%d\n",
+ p->index, p->name, p->type,
+ p->capability, p->rangelow,
+ p->rangehigh, p->signal, p->afc,
+ p->rxsubchans, p->audmode);
+ break;
+ }
+ case VIDIOC_S_TUNER:
+ {
+ struct v4l2_tuner *p = arg;
+
+ if (!ops->vidioc_s_tuner)
+ break;
+ dbgarg(cmd, "index=%d, name=%s, type=%d, "
+ "capability=0x%x, rangelow=%d, "
+ "rangehigh=%d, signal=%d, afc=%d, "
+ "rxsubchans=0x%x, audmode=%d\n",
+ p->index, p->name, p->type,
+ p->capability, p->rangelow,
+ p->rangehigh, p->signal, p->afc,
+ p->rxsubchans, p->audmode);
+ ret = ops->vidioc_s_tuner(file, fh, p);
+ break;
+ }
+ case VIDIOC_G_FREQUENCY:
+ {
+ struct v4l2_frequency *p = arg;
+
+ if (!ops->vidioc_g_frequency)
+ break;
+
+ memset(p->reserved, 0, sizeof(p->reserved));
+
+ ret = ops->vidioc_g_frequency(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "tuner=%d, type=%d, frequency=%d\n",
+ p->tuner, p->type, p->frequency);
+ break;
+ }
+ case VIDIOC_S_FREQUENCY:
+ {
+ struct v4l2_frequency *p = arg;
+
+ if (!ops->vidioc_s_frequency)
+ break;
+ dbgarg(cmd, "tuner=%d, type=%d, frequency=%d\n",
+ p->tuner, p->type, p->frequency);
+ ret = ops->vidioc_s_frequency(file, fh, p);
+ break;
+ }
+ case VIDIOC_G_SLICED_VBI_CAP:
+ {
+ struct v4l2_sliced_vbi_cap *p = arg;
+ __u32 type = p->type;
+
+ if (!ops->vidioc_g_sliced_vbi_cap)
+ break;
+ memset(p, 0, sizeof(*p));
+ p->type = type;
+ dbgarg(cmd, "type=%s\n", prt_names(p->type, v4l2_type_names));
+ ret = ops->vidioc_g_sliced_vbi_cap(file, fh, p);
+ if (!ret)
+ dbgarg2("service_set=%d\n", p->service_set);
+ break;
+ }
+ case VIDIOC_LOG_STATUS:
+ {
+ if (!ops->vidioc_log_status)
+ break;
+ ret = ops->vidioc_log_status(file, fh);
+ break;
+ }
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+ case VIDIOC_DBG_G_REGISTER:
+ {
+ struct v4l2_register *p = arg;
+
+ if (!capable(CAP_SYS_ADMIN))
+ ret = -EPERM;
+ else if (ops->vidioc_g_register)
+ ret = ops->vidioc_g_register(file, fh, p);
+ break;
+ }
+ case VIDIOC_DBG_S_REGISTER:
+ {
+ struct v4l2_register *p = arg;
+
+ if (!capable(CAP_SYS_ADMIN))
+ ret = -EPERM;
+ else if (ops->vidioc_s_register)
+ ret = ops->vidioc_s_register(file, fh, p);
+ break;
+ }
+#endif
+ case VIDIOC_G_CHIP_IDENT:
+ {
+ struct v4l2_chip_ident *p = arg;
+
+ if (!ops->vidioc_g_chip_ident)
+ break;
+ ret = ops->vidioc_g_chip_ident(file, fh, p);
+ if (!ret)
+ dbgarg(cmd, "chip_ident=%u, revision=0x%x\n", p->ident, p->revision);
+ break;
+ }
+ case VIDIOC_S_HW_FREQ_SEEK:
+ {
+ struct v4l2_hw_freq_seek *p = arg;
+
+ if (!ops->vidioc_s_hw_freq_seek)
+ break;
+ dbgarg(cmd,
+ "tuner=%d, type=%d, seek_upward=%d, wrap_around=%d\n",
+ p->tuner, p->type, p->seek_upward, p->wrap_around);
+ ret = ops->vidioc_s_hw_freq_seek(file, fh, p);
+ break;
+ }
+ default:
+ {
+ if (!ops->vidioc_default)
+ break;
+ ret = ops->vidioc_default(file, fh, cmd, arg);
+ break;
+ }
+ } /* switch */
+
+ if (vfd->debug & V4L2_DEBUG_IOCTL_ARG) {
+ if (ret < 0) {
+ v4l_print_ioctl(vfd->name, cmd);
+ printk(KERN_CONT " error %d\n", ret);
+ }
+ }
+
+ return ret;
+}
+
+int video_ioctl2(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ char sbuf[128];
+ void *mbuf = NULL;
+ void *parg = NULL;
+ int err = -EINVAL;
+ int is_ext_ctrl;
+ size_t ctrls_size = 0;
+ void __user *user_ptr = NULL;
+
+#ifdef __OLD_VIDIOC_
+ cmd = video_fix_command(cmd);
+#endif
+ is_ext_ctrl = (cmd == VIDIOC_S_EXT_CTRLS || cmd == VIDIOC_G_EXT_CTRLS ||
+ cmd == VIDIOC_TRY_EXT_CTRLS);
+
+ /* Copy arguments into temp kernel buffer */
+ switch (_IOC_DIR(cmd)) {
+ case _IOC_NONE:
+ parg = NULL;
+ break;
+ case _IOC_READ:
+ case _IOC_WRITE:
+ case (_IOC_WRITE | _IOC_READ):
+ if (_IOC_SIZE(cmd) <= sizeof(sbuf)) {
+ parg = sbuf;
+ } else {
+ /* too big to allocate from stack */
+ mbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL);
+ if (NULL == mbuf)
+ return -ENOMEM;
+ parg = mbuf;
+ }
+
+ err = -EFAULT;
+ if (_IOC_DIR(cmd) & _IOC_WRITE)
+ if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd)))
+ goto out;
+ break;
+ }
+
+ if (is_ext_ctrl) {
+ struct v4l2_ext_controls *p = parg;
+
+ /* In case of an error, tell the caller that it wasn't
+ a specific control that caused it. */
+ p->error_idx = p->count;
+ user_ptr = (void __user *)p->controls;
+ if (p->count) {
+ ctrls_size = sizeof(struct v4l2_ext_control) * p->count;
+ /* Note: v4l2_ext_controls fits in sbuf[] so mbuf is still NULL. */
+ mbuf = kmalloc(ctrls_size, GFP_KERNEL);
+ err = -ENOMEM;
+ if (NULL == mbuf)
+ goto out_ext_ctrl;
+ err = -EFAULT;
+ if (copy_from_user(mbuf, user_ptr, ctrls_size))
+ goto out_ext_ctrl;
+ p->controls = mbuf;
+ }
+ }
+
+ /* Handles IOCTL */
+ err = __video_do_ioctl(inode, file, cmd, parg);
+ if (err == -ENOIOCTLCMD)
+ err = -EINVAL;
+ if (is_ext_ctrl) {
+ struct v4l2_ext_controls *p = parg;
+
+ p->controls = (void *)user_ptr;
+ if (p->count && err == 0 && copy_to_user(user_ptr, mbuf, ctrls_size))
+ err = -EFAULT;
+ goto out_ext_ctrl;
+ }
+ if (err < 0)
+ goto out;
+
+out_ext_ctrl:
+ /* Copy results into user buffer */
+ switch (_IOC_DIR(cmd)) {
+ case _IOC_READ:
+ case (_IOC_WRITE | _IOC_READ):
+ if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd)))
+ err = -EFAULT;
+ break;
+ }
+
+out:
+ kfree(mbuf);
+ return err;
+}
+EXPORT_SYMBOL(video_ioctl2);
};
#define MAGIC_DC_MEM 0x0733ac61
-#define MAGIC_CHECK(is, should) \
- if (unlikely((is) != (should))) { \
- pr_err("magic mismatch: %x expected %x\n", is, should); \
- BUG(); \
+#define MAGIC_CHECK(is, should) \
+ if (unlikely((is) != (should))) { \
+ pr_err("magic mismatch: %x expected %x\n", (is), (should)); \
+ BUG(); \
}
static void
return 0;
/* FIXME: to properly support USERPTR, remap should occur.
- The code bellow won't work, since mem->vma = NULL
+ The code below won't work, since mem->vma = NULL
*/
/* Try to remap memory */
rc = remap_vmalloc_range(mem->vma, (void *)vb->baddr, 0);
-/*
- * Video capture interface for Linux version 2
- *
- * A generic video device interface for the LINUX operating system
- * using a set of device structures/vectors for low level operations.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * Authors: Alan Cox, <alan@redhat.com> (version 1)
- * Mauro Carvalho Chehab <mchehab@infradead.org> (version 2)
- *
- * Fixes: 20000516 Claudio Matsuoka <claudio@conectiva.com>
- * - Added procfs support
- */
-
-#define dbgarg(cmd, fmt, arg...) \
- do { \
- if (vfd->debug & V4L2_DEBUG_IOCTL_ARG) { \
- printk(KERN_DEBUG "%s: ", vfd->name); \
- v4l_printk_ioctl(cmd); \
- printk(" " fmt, ## arg); \
- } \
- } while (0)
-
-#define dbgarg2(fmt, arg...) \
- do { \
- if (vfd->debug & V4L2_DEBUG_IOCTL_ARG) \
- printk(KERN_DEBUG "%s: " fmt, vfd->name, ## arg);\
- } while (0)
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/string.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kmod.h>
-#include <linux/slab.h>
-#include <linux/smp_lock.h>
-#include <asm/uaccess.h>
-#include <asm/system.h>
-
-#define __OLD_VIDIOC_ /* To allow fixing old calls*/
-#include <linux/videodev2.h>
-
-#ifdef CONFIG_VIDEO_V4L1
-#include <linux/videodev.h>
-#endif
-#include <media/v4l2-common.h>
-#include <linux/video_decoder.h>
-
-#define VIDEO_NUM_DEVICES 256
-#define VIDEO_NAME "video4linux"
-
-struct std_descr {
- v4l2_std_id std;
- const char *descr;
-};
-
-static const struct std_descr standards[] = {
- { V4L2_STD_NTSC, "NTSC" },
- { V4L2_STD_NTSC_M, "NTSC-M" },
- { V4L2_STD_NTSC_M_JP, "NTSC-M-JP" },
- { V4L2_STD_NTSC_M_KR, "NTSC-M-KR" },
- { V4L2_STD_NTSC_443, "NTSC-443" },
- { V4L2_STD_PAL, "PAL" },
- { V4L2_STD_PAL_BG, "PAL-BG" },
- { V4L2_STD_PAL_B, "PAL-B" },
- { V4L2_STD_PAL_B1, "PAL-B1" },
- { V4L2_STD_PAL_G, "PAL-G" },
- { V4L2_STD_PAL_H, "PAL-H" },
- { V4L2_STD_PAL_I, "PAL-I" },
- { V4L2_STD_PAL_DK, "PAL-DK" },
- { V4L2_STD_PAL_D, "PAL-D" },
- { V4L2_STD_PAL_D1, "PAL-D1" },
- { V4L2_STD_PAL_K, "PAL-K" },
- { V4L2_STD_PAL_M, "PAL-M" },
- { V4L2_STD_PAL_N, "PAL-N" },
- { V4L2_STD_PAL_Nc, "PAL-Nc" },
- { V4L2_STD_PAL_60, "PAL-60" },
- { V4L2_STD_SECAM, "SECAM" },
- { V4L2_STD_SECAM_B, "SECAM-B" },
- { V4L2_STD_SECAM_G, "SECAM-G" },
- { V4L2_STD_SECAM_H, "SECAM-H" },
- { V4L2_STD_SECAM_DK, "SECAM-DK" },
- { V4L2_STD_SECAM_D, "SECAM-D" },
- { V4L2_STD_SECAM_K, "SECAM-K" },
- { V4L2_STD_SECAM_K1, "SECAM-K1" },
- { V4L2_STD_SECAM_L, "SECAM-L" },
- { V4L2_STD_SECAM_LC, "SECAM-Lc" },
- { 0, "Unknown" }
-};
-
-/* video4linux standard ID conversion to standard name
- */
-const char *v4l2_norm_to_name(v4l2_std_id id)
-{
- u32 myid = id;
- int i;
-
- /* HACK: ppc32 architecture doesn't have __ucmpdi2 function to handle
- 64 bit comparations. So, on that architecture, with some gcc
- variants, compilation fails. Currently, the max value is 30bit wide.
- */
- BUG_ON(myid != id);
-
- for (i = 0; standards[i].std; i++)
- if (myid == standards[i].std)
- break;
- return standards[i].descr;
-}
-EXPORT_SYMBOL(v4l2_norm_to_name);
-
-/* Fill in the fields of a v4l2_standard structure according to the
- 'id' and 'transmission' parameters. Returns negative on error. */
-int v4l2_video_std_construct(struct v4l2_standard *vs,
- int id, const char *name)
-{
- u32 index = vs->index;
-
- memset(vs, 0, sizeof(struct v4l2_standard));
- vs->index = index;
- vs->id = id;
- if (id & V4L2_STD_525_60) {
- vs->frameperiod.numerator = 1001;
- vs->frameperiod.denominator = 30000;
- vs->framelines = 525;
- } else {
- vs->frameperiod.numerator = 1;
- vs->frameperiod.denominator = 25;
- vs->framelines = 625;
- }
- strlcpy(vs->name, name, sizeof(vs->name));
- return 0;
-}
-EXPORT_SYMBOL(v4l2_video_std_construct);
-
-/* ----------------------------------------------------------------- */
-/* some arrays for pretty-printing debug messages of enum types */
-
-const char *v4l2_field_names[] = {
- [V4L2_FIELD_ANY] = "any",
- [V4L2_FIELD_NONE] = "none",
- [V4L2_FIELD_TOP] = "top",
- [V4L2_FIELD_BOTTOM] = "bottom",
- [V4L2_FIELD_INTERLACED] = "interlaced",
- [V4L2_FIELD_SEQ_TB] = "seq-tb",
- [V4L2_FIELD_SEQ_BT] = "seq-bt",
- [V4L2_FIELD_ALTERNATE] = "alternate",
- [V4L2_FIELD_INTERLACED_TB] = "interlaced-tb",
- [V4L2_FIELD_INTERLACED_BT] = "interlaced-bt",
-};
-EXPORT_SYMBOL(v4l2_field_names);
-
-const char *v4l2_type_names[] = {
- [V4L2_BUF_TYPE_VIDEO_CAPTURE] = "vid-cap",
- [V4L2_BUF_TYPE_VIDEO_OVERLAY] = "vid-overlay",
- [V4L2_BUF_TYPE_VIDEO_OUTPUT] = "vid-out",
- [V4L2_BUF_TYPE_VBI_CAPTURE] = "vbi-cap",
- [V4L2_BUF_TYPE_VBI_OUTPUT] = "vbi-out",
- [V4L2_BUF_TYPE_SLICED_VBI_CAPTURE] = "sliced-vbi-cap",
- [V4L2_BUF_TYPE_SLICED_VBI_OUTPUT] = "sliced-vbi-out",
- [V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY] = "vid-out-overlay",
-};
-EXPORT_SYMBOL(v4l2_type_names);
-
-static const char *v4l2_memory_names[] = {
- [V4L2_MEMORY_MMAP] = "mmap",
- [V4L2_MEMORY_USERPTR] = "userptr",
- [V4L2_MEMORY_OVERLAY] = "overlay",
-};
-
-#define prt_names(a, arr) ((((a) >= 0) && ((a) < ARRAY_SIZE(arr))) ? \
- arr[a] : "unknown")
-
-/* ------------------------------------------------------------------ */
-/* debug help functions */
-
-#ifdef CONFIG_VIDEO_V4L1_COMPAT
-static const char *v4l1_ioctls[] = {
- [_IOC_NR(VIDIOCGCAP)] = "VIDIOCGCAP",
- [_IOC_NR(VIDIOCGCHAN)] = "VIDIOCGCHAN",
- [_IOC_NR(VIDIOCSCHAN)] = "VIDIOCSCHAN",
- [_IOC_NR(VIDIOCGTUNER)] = "VIDIOCGTUNER",
- [_IOC_NR(VIDIOCSTUNER)] = "VIDIOCSTUNER",
- [_IOC_NR(VIDIOCGPICT)] = "VIDIOCGPICT",
- [_IOC_NR(VIDIOCSPICT)] = "VIDIOCSPICT",
- [_IOC_NR(VIDIOCCAPTURE)] = "VIDIOCCAPTURE",
- [_IOC_NR(VIDIOCGWIN)] = "VIDIOCGWIN",
- [_IOC_NR(VIDIOCSWIN)] = "VIDIOCSWIN",
- [_IOC_NR(VIDIOCGFBUF)] = "VIDIOCGFBUF",
- [_IOC_NR(VIDIOCSFBUF)] = "VIDIOCSFBUF",
- [_IOC_NR(VIDIOCKEY)] = "VIDIOCKEY",
- [_IOC_NR(VIDIOCGFREQ)] = "VIDIOCGFREQ",
- [_IOC_NR(VIDIOCSFREQ)] = "VIDIOCSFREQ",
- [_IOC_NR(VIDIOCGAUDIO)] = "VIDIOCGAUDIO",
- [_IOC_NR(VIDIOCSAUDIO)] = "VIDIOCSAUDIO",
- [_IOC_NR(VIDIOCSYNC)] = "VIDIOCSYNC",
- [_IOC_NR(VIDIOCMCAPTURE)] = "VIDIOCMCAPTURE",
- [_IOC_NR(VIDIOCGMBUF)] = "VIDIOCGMBUF",
- [_IOC_NR(VIDIOCGUNIT)] = "VIDIOCGUNIT",
- [_IOC_NR(VIDIOCGCAPTURE)] = "VIDIOCGCAPTURE",
- [_IOC_NR(VIDIOCSCAPTURE)] = "VIDIOCSCAPTURE",
- [_IOC_NR(VIDIOCSPLAYMODE)] = "VIDIOCSPLAYMODE",
- [_IOC_NR(VIDIOCSWRITEMODE)] = "VIDIOCSWRITEMODE",
- [_IOC_NR(VIDIOCGPLAYINFO)] = "VIDIOCGPLAYINFO",
- [_IOC_NR(VIDIOCSMICROCODE)] = "VIDIOCSMICROCODE",
- [_IOC_NR(VIDIOCGVBIFMT)] = "VIDIOCGVBIFMT",
- [_IOC_NR(VIDIOCSVBIFMT)] = "VIDIOCSVBIFMT"
-};
-#define V4L1_IOCTLS ARRAY_SIZE(v4l1_ioctls)
-#endif
-
-static const char *v4l2_ioctls[] = {
- [_IOC_NR(VIDIOC_QUERYCAP)] = "VIDIOC_QUERYCAP",
- [_IOC_NR(VIDIOC_RESERVED)] = "VIDIOC_RESERVED",
- [_IOC_NR(VIDIOC_ENUM_FMT)] = "VIDIOC_ENUM_FMT",
- [_IOC_NR(VIDIOC_G_FMT)] = "VIDIOC_G_FMT",
- [_IOC_NR(VIDIOC_S_FMT)] = "VIDIOC_S_FMT",
- [_IOC_NR(VIDIOC_REQBUFS)] = "VIDIOC_REQBUFS",
- [_IOC_NR(VIDIOC_QUERYBUF)] = "VIDIOC_QUERYBUF",
- [_IOC_NR(VIDIOC_G_FBUF)] = "VIDIOC_G_FBUF",
- [_IOC_NR(VIDIOC_S_FBUF)] = "VIDIOC_S_FBUF",
- [_IOC_NR(VIDIOC_OVERLAY)] = "VIDIOC_OVERLAY",
- [_IOC_NR(VIDIOC_QBUF)] = "VIDIOC_QBUF",
- [_IOC_NR(VIDIOC_DQBUF)] = "VIDIOC_DQBUF",
- [_IOC_NR(VIDIOC_STREAMON)] = "VIDIOC_STREAMON",
- [_IOC_NR(VIDIOC_STREAMOFF)] = "VIDIOC_STREAMOFF",
- [_IOC_NR(VIDIOC_G_PARM)] = "VIDIOC_G_PARM",
- [_IOC_NR(VIDIOC_S_PARM)] = "VIDIOC_S_PARM",
- [_IOC_NR(VIDIOC_G_STD)] = "VIDIOC_G_STD",
- [_IOC_NR(VIDIOC_S_STD)] = "VIDIOC_S_STD",
- [_IOC_NR(VIDIOC_ENUMSTD)] = "VIDIOC_ENUMSTD",
- [_IOC_NR(VIDIOC_ENUMINPUT)] = "VIDIOC_ENUMINPUT",
- [_IOC_NR(VIDIOC_G_CTRL)] = "VIDIOC_G_CTRL",
- [_IOC_NR(VIDIOC_S_CTRL)] = "VIDIOC_S_CTRL",
- [_IOC_NR(VIDIOC_G_TUNER)] = "VIDIOC_G_TUNER",
- [_IOC_NR(VIDIOC_S_TUNER)] = "VIDIOC_S_TUNER",
- [_IOC_NR(VIDIOC_G_AUDIO)] = "VIDIOC_G_AUDIO",
- [_IOC_NR(VIDIOC_S_AUDIO)] = "VIDIOC_S_AUDIO",
- [_IOC_NR(VIDIOC_QUERYCTRL)] = "VIDIOC_QUERYCTRL",
- [_IOC_NR(VIDIOC_QUERYMENU)] = "VIDIOC_QUERYMENU",
- [_IOC_NR(VIDIOC_G_INPUT)] = "VIDIOC_G_INPUT",
- [_IOC_NR(VIDIOC_S_INPUT)] = "VIDIOC_S_INPUT",
- [_IOC_NR(VIDIOC_G_OUTPUT)] = "VIDIOC_G_OUTPUT",
- [_IOC_NR(VIDIOC_S_OUTPUT)] = "VIDIOC_S_OUTPUT",
- [_IOC_NR(VIDIOC_ENUMOUTPUT)] = "VIDIOC_ENUMOUTPUT",
- [_IOC_NR(VIDIOC_G_AUDOUT)] = "VIDIOC_G_AUDOUT",
- [_IOC_NR(VIDIOC_S_AUDOUT)] = "VIDIOC_S_AUDOUT",
- [_IOC_NR(VIDIOC_G_MODULATOR)] = "VIDIOC_G_MODULATOR",
- [_IOC_NR(VIDIOC_S_MODULATOR)] = "VIDIOC_S_MODULATOR",
- [_IOC_NR(VIDIOC_G_FREQUENCY)] = "VIDIOC_G_FREQUENCY",
- [_IOC_NR(VIDIOC_S_FREQUENCY)] = "VIDIOC_S_FREQUENCY",
- [_IOC_NR(VIDIOC_CROPCAP)] = "VIDIOC_CROPCAP",
- [_IOC_NR(VIDIOC_G_CROP)] = "VIDIOC_G_CROP",
- [_IOC_NR(VIDIOC_S_CROP)] = "VIDIOC_S_CROP",
- [_IOC_NR(VIDIOC_G_JPEGCOMP)] = "VIDIOC_G_JPEGCOMP",
- [_IOC_NR(VIDIOC_S_JPEGCOMP)] = "VIDIOC_S_JPEGCOMP",
- [_IOC_NR(VIDIOC_QUERYSTD)] = "VIDIOC_QUERYSTD",
- [_IOC_NR(VIDIOC_TRY_FMT)] = "VIDIOC_TRY_FMT",
- [_IOC_NR(VIDIOC_ENUMAUDIO)] = "VIDIOC_ENUMAUDIO",
- [_IOC_NR(VIDIOC_ENUMAUDOUT)] = "VIDIOC_ENUMAUDOUT",
- [_IOC_NR(VIDIOC_G_PRIORITY)] = "VIDIOC_G_PRIORITY",
- [_IOC_NR(VIDIOC_S_PRIORITY)] = "VIDIOC_S_PRIORITY",
- [_IOC_NR(VIDIOC_G_SLICED_VBI_CAP)] = "VIDIOC_G_SLICED_VBI_CAP",
- [_IOC_NR(VIDIOC_LOG_STATUS)] = "VIDIOC_LOG_STATUS",
- [_IOC_NR(VIDIOC_G_EXT_CTRLS)] = "VIDIOC_G_EXT_CTRLS",
- [_IOC_NR(VIDIOC_S_EXT_CTRLS)] = "VIDIOC_S_EXT_CTRLS",
- [_IOC_NR(VIDIOC_TRY_EXT_CTRLS)] = "VIDIOC_TRY_EXT_CTRLS",
-#if 1
- [_IOC_NR(VIDIOC_ENUM_FRAMESIZES)] = "VIDIOC_ENUM_FRAMESIZES",
- [_IOC_NR(VIDIOC_ENUM_FRAMEINTERVALS)] = "VIDIOC_ENUM_FRAMEINTERVALS",
- [_IOC_NR(VIDIOC_G_ENC_INDEX)] = "VIDIOC_G_ENC_INDEX",
- [_IOC_NR(VIDIOC_ENCODER_CMD)] = "VIDIOC_ENCODER_CMD",
- [_IOC_NR(VIDIOC_TRY_ENCODER_CMD)] = "VIDIOC_TRY_ENCODER_CMD",
-
- [_IOC_NR(VIDIOC_DBG_S_REGISTER)] = "VIDIOC_DBG_S_REGISTER",
- [_IOC_NR(VIDIOC_DBG_G_REGISTER)] = "VIDIOC_DBG_G_REGISTER",
-
- [_IOC_NR(VIDIOC_G_CHIP_IDENT)] = "VIDIOC_G_CHIP_IDENT",
- [_IOC_NR(VIDIOC_S_HW_FREQ_SEEK)] = "VIDIOC_S_HW_FREQ_SEEK",
-#endif
-};
-#define V4L2_IOCTLS ARRAY_SIZE(v4l2_ioctls)
-
-static const char *v4l2_int_ioctls[] = {
-#ifdef CONFIG_VIDEO_V4L1_COMPAT
- [_IOC_NR(DECODER_GET_CAPABILITIES)] = "DECODER_GET_CAPABILITIES",
- [_IOC_NR(DECODER_GET_STATUS)] = "DECODER_GET_STATUS",
- [_IOC_NR(DECODER_SET_NORM)] = "DECODER_SET_NORM",
- [_IOC_NR(DECODER_SET_INPUT)] = "DECODER_SET_INPUT",
- [_IOC_NR(DECODER_SET_OUTPUT)] = "DECODER_SET_OUTPUT",
- [_IOC_NR(DECODER_ENABLE_OUTPUT)] = "DECODER_ENABLE_OUTPUT",
- [_IOC_NR(DECODER_SET_PICTURE)] = "DECODER_SET_PICTURE",
- [_IOC_NR(DECODER_SET_GPIO)] = "DECODER_SET_GPIO",
- [_IOC_NR(DECODER_INIT)] = "DECODER_INIT",
- [_IOC_NR(DECODER_SET_VBI_BYPASS)] = "DECODER_SET_VBI_BYPASS",
- [_IOC_NR(DECODER_DUMP)] = "DECODER_DUMP",
-#endif
- [_IOC_NR(AUDC_SET_RADIO)] = "AUDC_SET_RADIO",
-
- [_IOC_NR(TUNER_SET_TYPE_ADDR)] = "TUNER_SET_TYPE_ADDR",
- [_IOC_NR(TUNER_SET_STANDBY)] = "TUNER_SET_STANDBY",
- [_IOC_NR(TUNER_SET_CONFIG)] = "TUNER_SET_CONFIG",
-
- [_IOC_NR(VIDIOC_INT_S_TUNER_MODE)] = "VIDIOC_INT_S_TUNER_MODE",
- [_IOC_NR(VIDIOC_INT_RESET)] = "VIDIOC_INT_RESET",
- [_IOC_NR(VIDIOC_INT_AUDIO_CLOCK_FREQ)] = "VIDIOC_INT_AUDIO_CLOCK_FREQ",
- [_IOC_NR(VIDIOC_INT_DECODE_VBI_LINE)] = "VIDIOC_INT_DECODE_VBI_LINE",
- [_IOC_NR(VIDIOC_INT_S_VBI_DATA)] = "VIDIOC_INT_S_VBI_DATA",
- [_IOC_NR(VIDIOC_INT_G_VBI_DATA)] = "VIDIOC_INT_G_VBI_DATA",
- [_IOC_NR(VIDIOC_INT_I2S_CLOCK_FREQ)] = "VIDIOC_INT_I2S_CLOCK_FREQ",
- [_IOC_NR(VIDIOC_INT_S_STANDBY)] = "VIDIOC_INT_S_STANDBY",
- [_IOC_NR(VIDIOC_INT_S_AUDIO_ROUTING)] = "VIDIOC_INT_S_AUDIO_ROUTING",
- [_IOC_NR(VIDIOC_INT_G_AUDIO_ROUTING)] = "VIDIOC_INT_G_AUDIO_ROUTING",
- [_IOC_NR(VIDIOC_INT_S_VIDEO_ROUTING)] = "VIDIOC_INT_S_VIDEO_ROUTING",
- [_IOC_NR(VIDIOC_INT_G_VIDEO_ROUTING)] = "VIDIOC_INT_G_VIDEO_ROUTING",
- [_IOC_NR(VIDIOC_INT_S_CRYSTAL_FREQ)] = "VIDIOC_INT_S_CRYSTAL_FREQ",
- [_IOC_NR(VIDIOC_INT_INIT)] = "VIDIOC_INT_INIT",
- [_IOC_NR(VIDIOC_INT_G_STD_OUTPUT)] = "VIDIOC_INT_G_STD_OUTPUT",
- [_IOC_NR(VIDIOC_INT_S_STD_OUTPUT)] = "VIDIOC_INT_S_STD_OUTPUT",
-};
-#define V4L2_INT_IOCTLS ARRAY_SIZE(v4l2_int_ioctls)
-
-/* Common ioctl debug function. This function can be used by
- external ioctl messages as well as internal V4L ioctl */
-void v4l_printk_ioctl(unsigned int cmd)
-{
- char *dir, *type;
-
- switch (_IOC_TYPE(cmd)) {
- case 'd':
- if (_IOC_NR(cmd) >= V4L2_INT_IOCTLS) {
- type = "v4l2_int";
- break;
- }
- printk("%s", v4l2_int_ioctls[_IOC_NR(cmd)]);
- return;
-#ifdef CONFIG_VIDEO_V4L1_COMPAT
- case 'v':
- if (_IOC_NR(cmd) >= V4L1_IOCTLS) {
- type = "v4l1";
- break;
- }
- printk("%s", v4l1_ioctls[_IOC_NR(cmd)]);
- return;
-#endif
- case 'V':
- if (_IOC_NR(cmd) >= V4L2_IOCTLS) {
- type = "v4l2";
- break;
- }
- printk("%s", v4l2_ioctls[_IOC_NR(cmd)]);
- return;
- default:
- type = "unknown";
- }
-
- switch (_IOC_DIR(cmd)) {
- case _IOC_NONE: dir = "--"; break;
- case _IOC_READ: dir = "r-"; break;
- case _IOC_WRITE: dir = "-w"; break;
- case _IOC_READ | _IOC_WRITE: dir = "rw"; break;
- default: dir = "*ERR*"; break;
- }
- printk("%s ioctl '%c', dir=%s, #%d (0x%08x)",
- type, _IOC_TYPE(cmd), dir, _IOC_NR(cmd), cmd);
-}
-EXPORT_SYMBOL(v4l_printk_ioctl);
-
-/*
- * sysfs stuff
- */
-
-static ssize_t show_index(struct device *cd,
- struct device_attribute *attr, char *buf)
-{
- struct video_device *vfd = container_of(cd, struct video_device,
- class_dev);
- return sprintf(buf, "%i\n", vfd->index);
-}
-
-static ssize_t show_name(struct device *cd,
- struct device_attribute *attr, char *buf)
-{
- struct video_device *vfd = container_of(cd, struct video_device,
- class_dev);
- return sprintf(buf, "%.*s\n", (int)sizeof(vfd->name), vfd->name);
-}
-
-static struct device_attribute video_device_attrs[] = {
- __ATTR(name, S_IRUGO, show_name, NULL),
- __ATTR(index, S_IRUGO, show_index, NULL),
- __ATTR_NULL
-};
-
-struct video_device *video_device_alloc(void)
-{
- struct video_device *vfd;
-
- vfd = kzalloc(sizeof(*vfd),GFP_KERNEL);
- return vfd;
-}
-EXPORT_SYMBOL(video_device_alloc);
-
-void video_device_release(struct video_device *vfd)
-{
- kfree(vfd);
-}
-EXPORT_SYMBOL(video_device_release);
-
-static void video_release(struct device *cd)
-{
- struct video_device *vfd = container_of(cd, struct video_device,
- class_dev);
-
-#if 1
- /* needed until all drivers are fixed */
- if (!vfd->release)
- return;
-#endif
- vfd->release(vfd);
-}
-
-static struct class video_class = {
- .name = VIDEO_NAME,
- .dev_attrs = video_device_attrs,
- .dev_release = video_release,
-};
-
-/*
- * Active devices
- */
-
-static struct video_device *video_device[VIDEO_NUM_DEVICES];
-static DEFINE_MUTEX(videodev_lock);
-
-struct video_device* video_devdata(struct file *file)
-{
- return video_device[iminor(file->f_path.dentry->d_inode)];
-}
-EXPORT_SYMBOL(video_devdata);
-
-/*
- * Open a video device - FIXME: Obsoleted
- */
-static int video_open(struct inode *inode, struct file *file)
-{
- unsigned int minor = iminor(inode);
- int err = 0;
- struct video_device *vfl;
- const struct file_operations *old_fops;
-
- if(minor>=VIDEO_NUM_DEVICES)
- return -ENODEV;
- lock_kernel();
- mutex_lock(&videodev_lock);
- vfl=video_device[minor];
- if(vfl==NULL) {
- mutex_unlock(&videodev_lock);
- request_module("char-major-%d-%d", VIDEO_MAJOR, minor);
- mutex_lock(&videodev_lock);
- vfl=video_device[minor];
- if (vfl==NULL) {
- mutex_unlock(&videodev_lock);
- unlock_kernel();
- return -ENODEV;
- }
- }
- old_fops = file->f_op;
- file->f_op = fops_get(vfl->fops);
- if(file->f_op->open)
- err = file->f_op->open(inode,file);
- if (err) {
- fops_put(file->f_op);
- file->f_op = fops_get(old_fops);
- }
- fops_put(old_fops);
- mutex_unlock(&videodev_lock);
- unlock_kernel();
- return err;
-}
-
-/*
- * helper function -- handles userspace copying for ioctl arguments
- */
-
-#ifdef __OLD_VIDIOC_
-static unsigned int
-video_fix_command(unsigned int cmd)
-{
- switch (cmd) {
- case VIDIOC_OVERLAY_OLD:
- cmd = VIDIOC_OVERLAY;
- break;
- case VIDIOC_S_PARM_OLD:
- cmd = VIDIOC_S_PARM;
- break;
- case VIDIOC_S_CTRL_OLD:
- cmd = VIDIOC_S_CTRL;
- break;
- case VIDIOC_G_AUDIO_OLD:
- cmd = VIDIOC_G_AUDIO;
- break;
- case VIDIOC_G_AUDOUT_OLD:
- cmd = VIDIOC_G_AUDOUT;
- break;
- case VIDIOC_CROPCAP_OLD:
- cmd = VIDIOC_CROPCAP;
- break;
- }
- return cmd;
-}
-#endif
-
-/*
- * Obsolete usercopy function - Should be removed soon
- */
-int
-video_usercopy(struct inode *inode, struct file *file,
- unsigned int cmd, unsigned long arg,
- int (*func)(struct inode *inode, struct file *file,
- unsigned int cmd, void *arg))
-{
- char sbuf[128];
- void *mbuf = NULL;
- void *parg = NULL;
- int err = -EINVAL;
- int is_ext_ctrl;
- size_t ctrls_size = 0;
- void __user *user_ptr = NULL;
-
-#ifdef __OLD_VIDIOC_
- cmd = video_fix_command(cmd);
-#endif
- is_ext_ctrl = (cmd == VIDIOC_S_EXT_CTRLS || cmd == VIDIOC_G_EXT_CTRLS ||
- cmd == VIDIOC_TRY_EXT_CTRLS);
-
- /* Copy arguments into temp kernel buffer */
- switch (_IOC_DIR(cmd)) {
- case _IOC_NONE:
- parg = NULL;
- break;
- case _IOC_READ:
- case _IOC_WRITE:
- case (_IOC_WRITE | _IOC_READ):
- if (_IOC_SIZE(cmd) <= sizeof(sbuf)) {
- parg = sbuf;
- } else {
- /* too big to allocate from stack */
- mbuf = kmalloc(_IOC_SIZE(cmd),GFP_KERNEL);
- if (NULL == mbuf)
- return -ENOMEM;
- parg = mbuf;
- }
-
- err = -EFAULT;
- if (_IOC_DIR(cmd) & _IOC_WRITE)
- if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd)))
- goto out;
- break;
- }
- if (is_ext_ctrl) {
- struct v4l2_ext_controls *p = parg;
-
- /* In case of an error, tell the caller that it wasn't
- a specific control that caused it. */
- p->error_idx = p->count;
- user_ptr = (void __user *)p->controls;
- if (p->count) {
- ctrls_size = sizeof(struct v4l2_ext_control) * p->count;
- /* Note: v4l2_ext_controls fits in sbuf[] so mbuf is still NULL. */
- mbuf = kmalloc(ctrls_size, GFP_KERNEL);
- err = -ENOMEM;
- if (NULL == mbuf)
- goto out_ext_ctrl;
- err = -EFAULT;
- if (copy_from_user(mbuf, user_ptr, ctrls_size))
- goto out_ext_ctrl;
- p->controls = mbuf;
- }
- }
-
- /* call driver */
- err = func(inode, file, cmd, parg);
- if (err == -ENOIOCTLCMD)
- err = -EINVAL;
- if (is_ext_ctrl) {
- struct v4l2_ext_controls *p = parg;
-
- p->controls = (void *)user_ptr;
- if (p->count && err == 0 && copy_to_user(user_ptr, mbuf, ctrls_size))
- err = -EFAULT;
- goto out_ext_ctrl;
- }
- if (err < 0)
- goto out;
-
-out_ext_ctrl:
- /* Copy results into user buffer */
- switch (_IOC_DIR(cmd))
- {
- case _IOC_READ:
- case (_IOC_WRITE | _IOC_READ):
- if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd)))
- err = -EFAULT;
- break;
- }
-
-out:
- kfree(mbuf);
- return err;
-}
-EXPORT_SYMBOL(video_usercopy);
-
-/*
- * open/release helper functions -- handle exclusive opens
- * Should be removed soon
- */
-int video_exclusive_open(struct inode *inode, struct file *file)
-{
- struct video_device *vfl = video_devdata(file);
- int retval = 0;
-
- mutex_lock(&vfl->lock);
- if (vfl->users) {
- retval = -EBUSY;
- } else {
- vfl->users++;
- }
- mutex_unlock(&vfl->lock);
- return retval;
-}
-EXPORT_SYMBOL(video_exclusive_open);
-
-int video_exclusive_release(struct inode *inode, struct file *file)
-{
- struct video_device *vfl = video_devdata(file);
-
- vfl->users--;
- return 0;
-}
-EXPORT_SYMBOL(video_exclusive_release);
-
-static void dbgbuf(unsigned int cmd, struct video_device *vfd,
- struct v4l2_buffer *p)
-{
- struct v4l2_timecode *tc=&p->timecode;
-
- dbgarg (cmd, "%02ld:%02d:%02d.%08ld index=%d, type=%s, "
- "bytesused=%d, flags=0x%08d, "
- "field=%0d, sequence=%d, memory=%s, offset/userptr=0x%08lx, length=%d\n",
- (p->timestamp.tv_sec/3600),
- (int)(p->timestamp.tv_sec/60)%60,
- (int)(p->timestamp.tv_sec%60),
- p->timestamp.tv_usec,
- p->index,
- prt_names(p->type, v4l2_type_names),
- p->bytesused, p->flags,
- p->field, p->sequence,
- prt_names(p->memory, v4l2_memory_names),
- p->m.userptr, p->length);
- dbgarg2("timecode=%02d:%02d:%02d type=%d, "
- "flags=0x%08d, frames=%d, userbits=0x%08x\n",
- tc->hours,tc->minutes,tc->seconds,
- tc->type, tc->flags, tc->frames, *(__u32 *) tc->userbits);
-}
-
-static inline void dbgrect(struct video_device *vfd, char *s,
- struct v4l2_rect *r)
-{
- dbgarg2("%sRect start at %dx%d, size=%dx%d\n", s, r->left, r->top,
- r->width, r->height);
-};
-
-static inline void v4l_print_pix_fmt (struct video_device *vfd,
- struct v4l2_pix_format *fmt)
-{
- dbgarg2 ("width=%d, height=%d, format=%c%c%c%c, field=%s, "
- "bytesperline=%d sizeimage=%d, colorspace=%d\n",
- fmt->width,fmt->height,
- (fmt->pixelformat & 0xff),
- (fmt->pixelformat >> 8) & 0xff,
- (fmt->pixelformat >> 16) & 0xff,
- (fmt->pixelformat >> 24) & 0xff,
- prt_names(fmt->field, v4l2_field_names),
- fmt->bytesperline, fmt->sizeimage, fmt->colorspace);
-};
-
-static inline void v4l_print_ext_ctrls(unsigned int cmd,
- struct video_device *vfd, struct v4l2_ext_controls *c, int show_vals)
-{
- __u32 i;
-
- if (!(vfd->debug & V4L2_DEBUG_IOCTL_ARG))
- return;
- dbgarg(cmd, "");
- printk(KERN_CONT "class=0x%x", c->ctrl_class);
- for (i = 0; i < c->count; i++) {
- if (show_vals)
- printk(KERN_CONT " id/val=0x%x/0x%x",
- c->controls[i].id, c->controls[i].value);
- else
- printk(KERN_CONT " id=0x%x", c->controls[i].id);
- }
- printk(KERN_CONT "\n");
-};
-
-static inline int check_ext_ctrls(struct v4l2_ext_controls *c, int allow_priv)
-{
- __u32 i;
-
- /* zero the reserved fields */
- c->reserved[0] = c->reserved[1] = 0;
- for (i = 0; i < c->count; i++) {
- c->controls[i].reserved2[0] = 0;
- c->controls[i].reserved2[1] = 0;
- }
- /* V4L2_CID_PRIVATE_BASE cannot be used as control class
- when using extended controls.
- Only when passed in through VIDIOC_G_CTRL and VIDIOC_S_CTRL
- is it allowed for backwards compatibility.
- */
- if (!allow_priv && c->ctrl_class == V4L2_CID_PRIVATE_BASE)
- return 0;
- /* Check that all controls are from the same control class. */
- for (i = 0; i < c->count; i++) {
- if (V4L2_CTRL_ID2CLASS(c->controls[i].id) != c->ctrl_class) {
- c->error_idx = i;
- return 0;
- }
- }
- return 1;
-}
-
-static int check_fmt (struct video_device *vfd, enum v4l2_buf_type type)
-{
- switch (type) {
- case V4L2_BUF_TYPE_VIDEO_CAPTURE:
- if (vfd->vidioc_try_fmt_vid_cap)
- return (0);
- break;
- case V4L2_BUF_TYPE_VIDEO_OVERLAY:
- if (vfd->vidioc_try_fmt_vid_overlay)
- return (0);
- break;
- case V4L2_BUF_TYPE_VIDEO_OUTPUT:
- if (vfd->vidioc_try_fmt_vid_out)
- return (0);
- break;
- case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY:
- if (vfd->vidioc_try_fmt_vid_out_overlay)
- return (0);
- break;
- case V4L2_BUF_TYPE_VBI_CAPTURE:
- if (vfd->vidioc_try_fmt_vbi_cap)
- return (0);
- break;
- case V4L2_BUF_TYPE_VBI_OUTPUT:
- if (vfd->vidioc_try_fmt_vbi_out)
- return (0);
- break;
- case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
- if (vfd->vidioc_try_fmt_sliced_vbi_cap)
- return (0);
- break;
- case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
- if (vfd->vidioc_try_fmt_sliced_vbi_out)
- return (0);
- break;
- case V4L2_BUF_TYPE_PRIVATE:
- if (vfd->vidioc_try_fmt_type_private)
- return (0);
- break;
- }
- return (-EINVAL);
-}
-
-static int __video_do_ioctl(struct inode *inode, struct file *file,
- unsigned int cmd, void *arg)
-{
- struct video_device *vfd = video_devdata(file);
- void *fh = file->private_data;
- int ret = -EINVAL;
-
- if ( (vfd->debug & V4L2_DEBUG_IOCTL) &&
- !(vfd->debug & V4L2_DEBUG_IOCTL_ARG)) {
- v4l_print_ioctl(vfd->name, cmd);
- printk("\n");
- }
-
-#ifdef CONFIG_VIDEO_V4L1_COMPAT
- /***********************************************************
- Handles calls to the obsoleted V4L1 API
- Due to the nature of VIDIOCGMBUF, each driver that supports
- V4L1 should implement its own handler for this ioctl.
- ***********************************************************/
-
- /* --- streaming capture ------------------------------------- */
- if (cmd == VIDIOCGMBUF) {
- struct video_mbuf *p=arg;
-
- memset(p, 0, sizeof(*p));
-
- if (!vfd->vidiocgmbuf)
- return ret;
- ret=vfd->vidiocgmbuf(file, fh, p);
- if (!ret)
- dbgarg (cmd, "size=%d, frames=%d, offsets=0x%08lx\n",
- p->size, p->frames,
- (unsigned long)p->offsets);
- return ret;
- }
-
- /********************************************************
- All other V4L1 calls are handled by v4l1_compat module.
- Those calls will be translated into V4L2 calls, and
- __video_do_ioctl will be called again, with one or more
- V4L2 ioctls.
- ********************************************************/
- if (_IOC_TYPE(cmd)=='v')
- return v4l_compat_translate_ioctl(inode,file,cmd,arg,
- __video_do_ioctl);
-#endif
-
- switch(cmd) {
- /* --- capabilities ------------------------------------------ */
- case VIDIOC_QUERYCAP:
- {
- struct v4l2_capability *cap = (struct v4l2_capability*)arg;
- memset(cap, 0, sizeof(*cap));
-
- if (!vfd->vidioc_querycap)
- break;
-
- ret=vfd->vidioc_querycap(file, fh, cap);
- if (!ret)
- dbgarg (cmd, "driver=%s, card=%s, bus=%s, "
- "version=0x%08x, "
- "capabilities=0x%08x\n",
- cap->driver,cap->card,cap->bus_info,
- cap->version,
- cap->capabilities);
- break;
- }
-
- /* --- priority ------------------------------------------ */
- case VIDIOC_G_PRIORITY:
- {
- enum v4l2_priority *p=arg;
-
- if (!vfd->vidioc_g_priority)
- break;
- ret=vfd->vidioc_g_priority(file, fh, p);
- if (!ret)
- dbgarg(cmd, "priority is %d\n", *p);
- break;
- }
- case VIDIOC_S_PRIORITY:
- {
- enum v4l2_priority *p=arg;
-
- if (!vfd->vidioc_s_priority)
- break;
- dbgarg(cmd, "setting priority to %d\n", *p);
- ret=vfd->vidioc_s_priority(file, fh, *p);
- break;
- }
-
- /* --- capture ioctls ---------------------------------------- */
- case VIDIOC_ENUM_FMT:
- {
- struct v4l2_fmtdesc *f = arg;
- enum v4l2_buf_type type;
- unsigned int index;
-
- index = f->index;
- type = f->type;
- memset(f,0,sizeof(*f));
- f->index = index;
- f->type = type;
-
- switch (type) {
- case V4L2_BUF_TYPE_VIDEO_CAPTURE:
- if (vfd->vidioc_enum_fmt_vid_cap)
- ret = vfd->vidioc_enum_fmt_vid_cap(file, fh, f);
- break;
- case V4L2_BUF_TYPE_VIDEO_OVERLAY:
- if (vfd->vidioc_enum_fmt_vid_overlay)
- ret = vfd->vidioc_enum_fmt_vid_overlay(file,
- fh, f);
- break;
-#if 1
- /* V4L2_BUF_TYPE_VBI_CAPTURE should not support VIDIOC_ENUM_FMT
- * according to the spec. The bttv and saa7134 drivers support
- * it though, so just warn that this is deprecated and will be
- * removed in the near future. */
- case V4L2_BUF_TYPE_VBI_CAPTURE:
- if (vfd->vidioc_enum_fmt_vbi_cap) {
- printk(KERN_WARNING "vidioc_enum_fmt_vbi_cap will be removed in 2.6.28!\n");
- ret = vfd->vidioc_enum_fmt_vbi_cap(file, fh, f);
- }
- break;
-#endif
- case V4L2_BUF_TYPE_VIDEO_OUTPUT:
- if (vfd->vidioc_enum_fmt_vid_out)
- ret = vfd->vidioc_enum_fmt_vid_out(file, fh, f);
- break;
- case V4L2_BUF_TYPE_PRIVATE:
- if (vfd->vidioc_enum_fmt_type_private)
- ret = vfd->vidioc_enum_fmt_type_private(file,
- fh, f);
- break;
- default:
- break;
- }
- if (!ret)
- dbgarg (cmd, "index=%d, type=%d, flags=%d, "
- "pixelformat=%c%c%c%c, description='%s'\n",
- f->index, f->type, f->flags,
- (f->pixelformat & 0xff),
- (f->pixelformat >> 8) & 0xff,
- (f->pixelformat >> 16) & 0xff,
- (f->pixelformat >> 24) & 0xff,
- f->description);
- break;
- }
- case VIDIOC_G_FMT:
- {
- struct v4l2_format *f = (struct v4l2_format *)arg;
-
- memset(f->fmt.raw_data, 0, sizeof(f->fmt.raw_data));
-
- /* FIXME: Should be one dump per type */
- dbgarg(cmd, "type=%s\n", prt_names(f->type, v4l2_type_names));
-
- switch (f->type) {
- case V4L2_BUF_TYPE_VIDEO_CAPTURE:
- if (vfd->vidioc_g_fmt_vid_cap)
- ret = vfd->vidioc_g_fmt_vid_cap(file, fh, f);
- if (!ret)
- v4l_print_pix_fmt(vfd, &f->fmt.pix);
- break;
- case V4L2_BUF_TYPE_VIDEO_OVERLAY:
- if (vfd->vidioc_g_fmt_vid_overlay)
- ret = vfd->vidioc_g_fmt_vid_overlay(file,
- fh, f);
- break;
- case V4L2_BUF_TYPE_VIDEO_OUTPUT:
- if (vfd->vidioc_g_fmt_vid_out)
- ret = vfd->vidioc_g_fmt_vid_out(file, fh, f);
- if (!ret)
- v4l_print_pix_fmt(vfd, &f->fmt.pix);
- break;
- case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY:
- if (vfd->vidioc_g_fmt_vid_out_overlay)
- ret = vfd->vidioc_g_fmt_vid_out_overlay(file,
- fh, f);
- break;
- case V4L2_BUF_TYPE_VBI_CAPTURE:
- if (vfd->vidioc_g_fmt_vbi_cap)
- ret = vfd->vidioc_g_fmt_vbi_cap(file, fh, f);
- break;
- case V4L2_BUF_TYPE_VBI_OUTPUT:
- if (vfd->vidioc_g_fmt_vbi_out)
- ret = vfd->vidioc_g_fmt_vbi_out(file, fh, f);
- break;
- case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
- if (vfd->vidioc_g_fmt_sliced_vbi_cap)
- ret = vfd->vidioc_g_fmt_sliced_vbi_cap(file,
- fh, f);
- break;
- case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
- if (vfd->vidioc_g_fmt_sliced_vbi_out)
- ret = vfd->vidioc_g_fmt_sliced_vbi_out(file,
- fh, f);
- break;
- case V4L2_BUF_TYPE_PRIVATE:
- if (vfd->vidioc_g_fmt_type_private)
- ret = vfd->vidioc_g_fmt_type_private(file,
- fh, f);
- break;
- }
-
- break;
- }
- case VIDIOC_S_FMT:
- {
- struct v4l2_format *f = (struct v4l2_format *)arg;
-
- /* FIXME: Should be one dump per type */
- dbgarg(cmd, "type=%s\n", prt_names(f->type, v4l2_type_names));
-
- switch (f->type) {
- case V4L2_BUF_TYPE_VIDEO_CAPTURE:
- v4l_print_pix_fmt(vfd, &f->fmt.pix);
- if (vfd->vidioc_s_fmt_vid_cap)
- ret = vfd->vidioc_s_fmt_vid_cap(file, fh, f);
- break;
- case V4L2_BUF_TYPE_VIDEO_OVERLAY:
- if (vfd->vidioc_s_fmt_vid_overlay)
- ret = vfd->vidioc_s_fmt_vid_overlay(file,
- fh, f);
- break;
- case V4L2_BUF_TYPE_VIDEO_OUTPUT:
- v4l_print_pix_fmt(vfd, &f->fmt.pix);
- if (vfd->vidioc_s_fmt_vid_out)
- ret = vfd->vidioc_s_fmt_vid_out(file, fh, f);
- break;
- case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY:
- if (vfd->vidioc_s_fmt_vid_out_overlay)
- ret = vfd->vidioc_s_fmt_vid_out_overlay(file,
- fh, f);
- break;
- case V4L2_BUF_TYPE_VBI_CAPTURE:
- if (vfd->vidioc_s_fmt_vbi_cap)
- ret = vfd->vidioc_s_fmt_vbi_cap(file, fh, f);
- break;
- case V4L2_BUF_TYPE_VBI_OUTPUT:
- if (vfd->vidioc_s_fmt_vbi_out)
- ret = vfd->vidioc_s_fmt_vbi_out(file, fh, f);
- break;
- case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
- if (vfd->vidioc_s_fmt_sliced_vbi_cap)
- ret = vfd->vidioc_s_fmt_sliced_vbi_cap(file,
- fh, f);
- break;
- case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
- if (vfd->vidioc_s_fmt_sliced_vbi_out)
- ret = vfd->vidioc_s_fmt_sliced_vbi_out(file,
- fh, f);
- break;
- case V4L2_BUF_TYPE_PRIVATE:
- if (vfd->vidioc_s_fmt_type_private)
- ret = vfd->vidioc_s_fmt_type_private(file,
- fh, f);
- break;
- }
- break;
- }
- case VIDIOC_TRY_FMT:
- {
- struct v4l2_format *f = (struct v4l2_format *)arg;
-
- /* FIXME: Should be one dump per type */
- dbgarg (cmd, "type=%s\n", prt_names(f->type,
- v4l2_type_names));
- switch (f->type) {
- case V4L2_BUF_TYPE_VIDEO_CAPTURE:
- if (vfd->vidioc_try_fmt_vid_cap)
- ret = vfd->vidioc_try_fmt_vid_cap(file, fh, f);
- if (!ret)
- v4l_print_pix_fmt(vfd, &f->fmt.pix);
- break;
- case V4L2_BUF_TYPE_VIDEO_OVERLAY:
- if (vfd->vidioc_try_fmt_vid_overlay)
- ret = vfd->vidioc_try_fmt_vid_overlay(file,
- fh, f);
- break;
- case V4L2_BUF_TYPE_VIDEO_OUTPUT:
- if (vfd->vidioc_try_fmt_vid_out)
- ret = vfd->vidioc_try_fmt_vid_out(file, fh, f);
- if (!ret)
- v4l_print_pix_fmt(vfd, &f->fmt.pix);
- break;
- case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY:
- if (vfd->vidioc_try_fmt_vid_out_overlay)
- ret = vfd->vidioc_try_fmt_vid_out_overlay(file,
- fh, f);
- break;
- case V4L2_BUF_TYPE_VBI_CAPTURE:
- if (vfd->vidioc_try_fmt_vbi_cap)
- ret = vfd->vidioc_try_fmt_vbi_cap(file, fh, f);
- break;
- case V4L2_BUF_TYPE_VBI_OUTPUT:
- if (vfd->vidioc_try_fmt_vbi_out)
- ret = vfd->vidioc_try_fmt_vbi_out(file, fh, f);
- break;
- case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
- if (vfd->vidioc_try_fmt_sliced_vbi_cap)
- ret = vfd->vidioc_try_fmt_sliced_vbi_cap(file,
- fh, f);
- break;
- case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
- if (vfd->vidioc_try_fmt_sliced_vbi_out)
- ret = vfd->vidioc_try_fmt_sliced_vbi_out(file,
- fh, f);
- break;
- case V4L2_BUF_TYPE_PRIVATE:
- if (vfd->vidioc_try_fmt_type_private)
- ret = vfd->vidioc_try_fmt_type_private(file,
- fh, f);
- break;
- }
-
- break;
- }
- /* FIXME: Those buf reqs could be handled here,
- with some changes on videobuf to allow its header to be included at
- videodev2.h or being merged at videodev2.
- */
- case VIDIOC_REQBUFS:
- {
- struct v4l2_requestbuffers *p=arg;
-
- if (!vfd->vidioc_reqbufs)
- break;
- ret = check_fmt (vfd, p->type);
- if (ret)
- break;
-
- ret=vfd->vidioc_reqbufs(file, fh, p);
- dbgarg (cmd, "count=%d, type=%s, memory=%s\n",
- p->count,
- prt_names(p->type, v4l2_type_names),
- prt_names(p->memory, v4l2_memory_names));
- break;
- }
- case VIDIOC_QUERYBUF:
- {
- struct v4l2_buffer *p=arg;
-
- if (!vfd->vidioc_querybuf)
- break;
- ret = check_fmt (vfd, p->type);
- if (ret)
- break;
-
- ret=vfd->vidioc_querybuf(file, fh, p);
- if (!ret)
- dbgbuf(cmd,vfd,p);
- break;
- }
- case VIDIOC_QBUF:
- {
- struct v4l2_buffer *p=arg;
-
- if (!vfd->vidioc_qbuf)
- break;
- ret = check_fmt (vfd, p->type);
- if (ret)
- break;
-
- ret=vfd->vidioc_qbuf(file, fh, p);
- if (!ret)
- dbgbuf(cmd,vfd,p);
- break;
- }
- case VIDIOC_DQBUF:
- {
- struct v4l2_buffer *p=arg;
- if (!vfd->vidioc_dqbuf)
- break;
- ret = check_fmt (vfd, p->type);
- if (ret)
- break;
-
- ret=vfd->vidioc_dqbuf(file, fh, p);
- if (!ret)
- dbgbuf(cmd,vfd,p);
- break;
- }
- case VIDIOC_OVERLAY:
- {
- int *i = arg;
-
- if (!vfd->vidioc_overlay)
- break;
- dbgarg (cmd, "value=%d\n",*i);
- ret=vfd->vidioc_overlay(file, fh, *i);
- break;
- }
- case VIDIOC_G_FBUF:
- {
- struct v4l2_framebuffer *p = arg;
-
- if (!vfd->vidioc_g_fbuf)
- break;
- ret = vfd->vidioc_g_fbuf(file, fh, arg);
- if (!ret) {
- dbgarg(cmd, "capability=0x%x, flags=%d, base=0x%08lx\n",
- p->capability, p->flags,
- (unsigned long)p->base);
- v4l_print_pix_fmt(vfd, &p->fmt);
- }
- break;
- }
- case VIDIOC_S_FBUF:
- {
- struct v4l2_framebuffer *p = arg;
-
- if (!vfd->vidioc_s_fbuf)
- break;
- dbgarg(cmd, "capability=0x%x, flags=%d, base=0x%08lx\n",
- p->capability, p->flags, (unsigned long)p->base);
- v4l_print_pix_fmt(vfd, &p->fmt);
- ret = vfd->vidioc_s_fbuf(file, fh, arg);
- break;
- }
- case VIDIOC_STREAMON:
- {
- enum v4l2_buf_type i = *(int *)arg;
- if (!vfd->vidioc_streamon)
- break;
- dbgarg(cmd, "type=%s\n", prt_names(i, v4l2_type_names));
- ret=vfd->vidioc_streamon(file, fh,i);
- break;
- }
- case VIDIOC_STREAMOFF:
- {
- enum v4l2_buf_type i = *(int *)arg;
-
- if (!vfd->vidioc_streamoff)
- break;
- dbgarg(cmd, "type=%s\n", prt_names(i, v4l2_type_names));
- ret=vfd->vidioc_streamoff(file, fh, i);
- break;
- }
- /* ---------- tv norms ---------- */
- case VIDIOC_ENUMSTD:
- {
- struct v4l2_standard *p = arg;
- v4l2_std_id id = vfd->tvnorms, curr_id = 0;
- unsigned int index = p->index, i, j = 0;
- const char *descr = "";
-
- /* Return norm array in a canonical way */
- for (i = 0; i <= index && id; i++) {
- /* last std value in the standards array is 0, so this
- while always ends there since (id & 0) == 0. */
- while ((id & standards[j].std) != standards[j].std)
- j++;
- curr_id = standards[j].std;
- descr = standards[j].descr;
- j++;
- if (curr_id == 0)
- break;
- if (curr_id != V4L2_STD_PAL &&
- curr_id != V4L2_STD_SECAM &&
- curr_id != V4L2_STD_NTSC)
- id &= ~curr_id;
- }
- if (i <= index)
- return -EINVAL;
-
- v4l2_video_std_construct(p, curr_id, descr);
- p->index = index;
-
- dbgarg(cmd, "index=%d, id=0x%Lx, name=%s, fps=%d/%d, "
- "framelines=%d\n", p->index,
- (unsigned long long)p->id, p->name,
- p->frameperiod.numerator,
- p->frameperiod.denominator,
- p->framelines);
-
- ret = 0;
- break;
- }
- case VIDIOC_G_STD:
- {
- v4l2_std_id *id = arg;
-
- ret = 0;
- /* Calls the specific handler */
- if (vfd->vidioc_g_std)
- ret = vfd->vidioc_g_std(file, fh, id);
- else
- *id = vfd->current_norm;
-
- if (!ret)
- dbgarg(cmd, "std=0x%08Lx\n", (long long unsigned)*id);
- break;
- }
- case VIDIOC_S_STD:
- {
- v4l2_std_id *id = arg,norm;
-
- dbgarg(cmd, "std=%08Lx\n", (long long unsigned)*id);
-
- norm = (*id) & vfd->tvnorms;
- if ( vfd->tvnorms && !norm) /* Check if std is supported */
- break;
-
- /* Calls the specific handler */
- if (vfd->vidioc_s_std)
- ret=vfd->vidioc_s_std(file, fh, &norm);
- else
- ret=-EINVAL;
-
- /* Updates standard information */
- if (ret>=0)
- vfd->current_norm=norm;
-
- break;
- }
- case VIDIOC_QUERYSTD:
- {
- v4l2_std_id *p=arg;
-
- if (!vfd->vidioc_querystd)
- break;
- ret=vfd->vidioc_querystd(file, fh, arg);
- if (!ret)
- dbgarg (cmd, "detected std=%08Lx\n",
- (unsigned long long)*p);
- break;
- }
- /* ------ input switching ---------- */
- /* FIXME: Inputs can be handled inside videodev2 */
- case VIDIOC_ENUMINPUT:
- {
- struct v4l2_input *p=arg;
- int i=p->index;
-
- if (!vfd->vidioc_enum_input)
- break;
- memset(p, 0, sizeof(*p));
- p->index=i;
-
- ret=vfd->vidioc_enum_input(file, fh, p);
- if (!ret)
- dbgarg (cmd, "index=%d, name=%s, type=%d, "
- "audioset=%d, "
- "tuner=%d, std=%08Lx, status=%d\n",
- p->index,p->name,p->type,p->audioset,
- p->tuner,
- (unsigned long long)p->std,
- p->status);
- break;
- }
- case VIDIOC_G_INPUT:
- {
- unsigned int *i = arg;
-
- if (!vfd->vidioc_g_input)
- break;
- ret=vfd->vidioc_g_input(file, fh, i);
- if (!ret)
- dbgarg (cmd, "value=%d\n",*i);
- break;
- }
- case VIDIOC_S_INPUT:
- {
- unsigned int *i = arg;
-
- if (!vfd->vidioc_s_input)
- break;
- dbgarg (cmd, "value=%d\n",*i);
- ret=vfd->vidioc_s_input(file, fh, *i);
- break;
- }
-
- /* ------ output switching ---------- */
- case VIDIOC_ENUMOUTPUT:
- {
- struct v4l2_output *p = arg;
- int i = p->index;
-
- if (!vfd->vidioc_enum_output)
- break;
- memset(p, 0, sizeof(*p));
- p->index = i;
-
- ret = vfd->vidioc_enum_output(file, fh, p);
- if (!ret)
- dbgarg(cmd, "index=%d, name=%s, type=%d, "
- "audioset=0x%x, "
- "modulator=%d, std=0x%08Lx\n",
- p->index, p->name, p->type, p->audioset,
- p->modulator, (unsigned long long)p->std);
- break;
- }
- case VIDIOC_G_OUTPUT:
- {
- unsigned int *i = arg;
-
- if (!vfd->vidioc_g_output)
- break;
- ret=vfd->vidioc_g_output(file, fh, i);
- if (!ret)
- dbgarg (cmd, "value=%d\n",*i);
- break;
- }
- case VIDIOC_S_OUTPUT:
- {
- unsigned int *i = arg;
-
- if (!vfd->vidioc_s_output)
- break;
- dbgarg (cmd, "value=%d\n",*i);
- ret=vfd->vidioc_s_output(file, fh, *i);
- break;
- }
-
- /* --- controls ---------------------------------------------- */
- case VIDIOC_QUERYCTRL:
- {
- struct v4l2_queryctrl *p = arg;
-
- if (!vfd->vidioc_queryctrl)
- break;
- ret = vfd->vidioc_queryctrl(file, fh, p);
- if (!ret)
- dbgarg(cmd, "id=0x%x, type=%d, name=%s, min/max=%d/%d, "
- "step=%d, default=%d, flags=0x%08x\n",
- p->id, p->type, p->name,
- p->minimum, p->maximum,
- p->step, p->default_value, p->flags);
- else
- dbgarg(cmd, "id=0x%x\n", p->id);
- break;
- }
- case VIDIOC_G_CTRL:
- {
- struct v4l2_control *p = arg;
-
- if (vfd->vidioc_g_ctrl)
- ret = vfd->vidioc_g_ctrl(file, fh, p);
- else if (vfd->vidioc_g_ext_ctrls) {
- struct v4l2_ext_controls ctrls;
- struct v4l2_ext_control ctrl;
-
- ctrls.ctrl_class = V4L2_CTRL_ID2CLASS(p->id);
- ctrls.count = 1;
- ctrls.controls = &ctrl;
- ctrl.id = p->id;
- ctrl.value = p->value;
- if (check_ext_ctrls(&ctrls, 1)) {
- ret = vfd->vidioc_g_ext_ctrls(file, fh, &ctrls);
- if (ret == 0)
- p->value = ctrl.value;
- }
- } else
- break;
- if (!ret)
- dbgarg(cmd, "id=0x%x, value=%d\n", p->id, p->value);
- else
- dbgarg(cmd, "id=0x%x\n", p->id);
- break;
- }
- case VIDIOC_S_CTRL:
- {
- struct v4l2_control *p = arg;
- struct v4l2_ext_controls ctrls;
- struct v4l2_ext_control ctrl;
-
- if (!vfd->vidioc_s_ctrl && !vfd->vidioc_s_ext_ctrls)
- break;
-
- dbgarg(cmd, "id=0x%x, value=%d\n", p->id, p->value);
-
- if (vfd->vidioc_s_ctrl) {
- ret = vfd->vidioc_s_ctrl(file, fh, p);
- break;
- }
- if (!vfd->vidioc_s_ext_ctrls)
- break;
-
- ctrls.ctrl_class = V4L2_CTRL_ID2CLASS(p->id);
- ctrls.count = 1;
- ctrls.controls = &ctrl;
- ctrl.id = p->id;
- ctrl.value = p->value;
- if (check_ext_ctrls(&ctrls, 1))
- ret = vfd->vidioc_s_ext_ctrls(file, fh, &ctrls);
- break;
- }
- case VIDIOC_G_EXT_CTRLS:
- {
- struct v4l2_ext_controls *p = arg;
-
- p->error_idx = p->count;
- if (!vfd->vidioc_g_ext_ctrls)
- break;
- if (check_ext_ctrls(p, 0))
- ret = vfd->vidioc_g_ext_ctrls(file, fh, p);
- v4l_print_ext_ctrls(cmd, vfd, p, !ret);
- break;
- }
- case VIDIOC_S_EXT_CTRLS:
- {
- struct v4l2_ext_controls *p = arg;
-
- p->error_idx = p->count;
- if (!vfd->vidioc_s_ext_ctrls)
- break;
- v4l_print_ext_ctrls(cmd, vfd, p, 1);
- if (check_ext_ctrls(p, 0))
- ret = vfd->vidioc_s_ext_ctrls(file, fh, p);
- break;
- }
- case VIDIOC_TRY_EXT_CTRLS:
- {
- struct v4l2_ext_controls *p = arg;
-
- p->error_idx = p->count;
- if (!vfd->vidioc_try_ext_ctrls)
- break;
- v4l_print_ext_ctrls(cmd, vfd, p, 1);
- if (check_ext_ctrls(p, 0))
- ret = vfd->vidioc_try_ext_ctrls(file, fh, p);
- break;
- }
- case VIDIOC_QUERYMENU:
- {
- struct v4l2_querymenu *p = arg;
-
- if (!vfd->vidioc_querymenu)
- break;
- ret = vfd->vidioc_querymenu(file, fh, p);
- if (!ret)
- dbgarg(cmd, "id=0x%x, index=%d, name=%s\n",
- p->id, p->index, p->name);
- else
- dbgarg(cmd, "id=0x%x, index=%d\n",
- p->id, p->index);
- break;
- }
- /* --- audio ---------------------------------------------- */
- case VIDIOC_ENUMAUDIO:
- {
- struct v4l2_audio *p = arg;
-
- if (!vfd->vidioc_enumaudio)
- break;
- ret = vfd->vidioc_enumaudio(file, fh, p);
- if (!ret)
- dbgarg(cmd, "index=%d, name=%s, capability=0x%x, "
- "mode=0x%x\n", p->index, p->name,
- p->capability, p->mode);
- else
- dbgarg(cmd, "index=%d\n", p->index);
- break;
- }
- case VIDIOC_G_AUDIO:
- {
- struct v4l2_audio *p = arg;
- __u32 index = p->index;
-
- if (!vfd->vidioc_g_audio)
- break;
-
- memset(p, 0, sizeof(*p));
- p->index = index;
- ret = vfd->vidioc_g_audio(file, fh, p);
- if (!ret)
- dbgarg(cmd, "index=%d, name=%s, capability=0x%x, "
- "mode=0x%x\n", p->index,
- p->name, p->capability, p->mode);
- else
- dbgarg(cmd, "index=%d\n", p->index);
- break;
- }
- case VIDIOC_S_AUDIO:
- {
- struct v4l2_audio *p = arg;
-
- if (!vfd->vidioc_s_audio)
- break;
- dbgarg(cmd, "index=%d, name=%s, capability=0x%x, "
- "mode=0x%x\n", p->index, p->name,
- p->capability, p->mode);
- ret = vfd->vidioc_s_audio(file, fh, p);
- break;
- }
- case VIDIOC_ENUMAUDOUT:
- {
- struct v4l2_audioout *p=arg;
-
- if (!vfd->vidioc_enumaudout)
- break;
- dbgarg(cmd, "Enum for index=%d\n", p->index);
- ret=vfd->vidioc_enumaudout(file, fh, p);
- if (!ret)
- dbgarg2("index=%d, name=%s, capability=%d, "
- "mode=%d\n", p->index, p->name,
- p->capability,p->mode);
- break;
- }
- case VIDIOC_G_AUDOUT:
- {
- struct v4l2_audioout *p=arg;
-
- if (!vfd->vidioc_g_audout)
- break;
- dbgarg(cmd, "Enum for index=%d\n", p->index);
- ret=vfd->vidioc_g_audout(file, fh, p);
- if (!ret)
- dbgarg2("index=%d, name=%s, capability=%d, "
- "mode=%d\n", p->index, p->name,
- p->capability,p->mode);
- break;
- }
- case VIDIOC_S_AUDOUT:
- {
- struct v4l2_audioout *p=arg;
-
- if (!vfd->vidioc_s_audout)
- break;
- dbgarg(cmd, "index=%d, name=%s, capability=%d, "
- "mode=%d\n", p->index, p->name,
- p->capability,p->mode);
-
- ret=vfd->vidioc_s_audout(file, fh, p);
- break;
- }
- case VIDIOC_G_MODULATOR:
- {
- struct v4l2_modulator *p=arg;
- if (!vfd->vidioc_g_modulator)
- break;
- ret=vfd->vidioc_g_modulator(file, fh, p);
- if (!ret)
- dbgarg(cmd, "index=%d, name=%s, "
- "capability=%d, rangelow=%d,"
- " rangehigh=%d, txsubchans=%d\n",
- p->index, p->name,p->capability,
- p->rangelow, p->rangehigh,
- p->txsubchans);
- break;
- }
- case VIDIOC_S_MODULATOR:
- {
- struct v4l2_modulator *p=arg;
- if (!vfd->vidioc_s_modulator)
- break;
- dbgarg(cmd, "index=%d, name=%s, capability=%d, "
- "rangelow=%d, rangehigh=%d, txsubchans=%d\n",
- p->index, p->name,p->capability,p->rangelow,
- p->rangehigh,p->txsubchans);
- ret=vfd->vidioc_s_modulator(file, fh, p);
- break;
- }
- case VIDIOC_G_CROP:
- {
- struct v4l2_crop *p=arg;
- if (!vfd->vidioc_g_crop)
- break;
- dbgarg(cmd, "type=%s\n", prt_names(p->type, v4l2_type_names));
- ret=vfd->vidioc_g_crop(file, fh, p);
- if (!ret) {
- dbgrect(vfd, "", &p->c);
- }
- break;
- }
- case VIDIOC_S_CROP:
- {
- struct v4l2_crop *p=arg;
- if (!vfd->vidioc_s_crop)
- break;
- dbgarg(cmd, "type=%s\n", prt_names(p->type, v4l2_type_names));
- dbgrect(vfd, "", &p->c);
- ret=vfd->vidioc_s_crop(file, fh, p);
- break;
- }
- case VIDIOC_CROPCAP:
- {
- struct v4l2_cropcap *p = arg;
-
- /*FIXME: Should also show v4l2_fract pixelaspect */
- if (!vfd->vidioc_cropcap)
- break;
- dbgarg(cmd, "type=%s\n", prt_names(p->type, v4l2_type_names));
- ret = vfd->vidioc_cropcap(file, fh, p);
- if (!ret) {
- dbgrect(vfd, "bounds ", &p->bounds);
- dbgrect(vfd, "defrect ", &p->defrect);
- }
- break;
- }
- case VIDIOC_G_JPEGCOMP:
- {
- struct v4l2_jpegcompression *p=arg;
- if (!vfd->vidioc_g_jpegcomp)
- break;
- ret=vfd->vidioc_g_jpegcomp(file, fh, p);
- if (!ret)
- dbgarg (cmd, "quality=%d, APPn=%d, "
- "APP_len=%d, COM_len=%d, "
- "jpeg_markers=%d\n",
- p->quality,p->APPn,p->APP_len,
- p->COM_len,p->jpeg_markers);
- break;
- }
- case VIDIOC_S_JPEGCOMP:
- {
- struct v4l2_jpegcompression *p=arg;
- if (!vfd->vidioc_g_jpegcomp)
- break;
- dbgarg (cmd, "quality=%d, APPn=%d, APP_len=%d, "
- "COM_len=%d, jpeg_markers=%d\n",
- p->quality,p->APPn,p->APP_len,
- p->COM_len,p->jpeg_markers);
- ret=vfd->vidioc_s_jpegcomp(file, fh, p);
- break;
- }
- case VIDIOC_G_ENC_INDEX:
- {
- struct v4l2_enc_idx *p=arg;
-
- if (!vfd->vidioc_g_enc_index)
- break;
- ret=vfd->vidioc_g_enc_index(file, fh, p);
- if (!ret)
- dbgarg (cmd, "entries=%d, entries_cap=%d\n",
- p->entries,p->entries_cap);
- break;
- }
- case VIDIOC_ENCODER_CMD:
- {
- struct v4l2_encoder_cmd *p = arg;
-
- if (!vfd->vidioc_encoder_cmd)
- break;
- memset(&p->raw, 0, sizeof(p->raw));
- ret = vfd->vidioc_encoder_cmd(file, fh, p);
- if (!ret)
- dbgarg(cmd, "cmd=%d, flags=%x\n", p->cmd, p->flags);
- break;
- }
- case VIDIOC_TRY_ENCODER_CMD:
- {
- struct v4l2_encoder_cmd *p = arg;
-
- if (!vfd->vidioc_try_encoder_cmd)
- break;
- memset(&p->raw, 0, sizeof(p->raw));
- ret = vfd->vidioc_try_encoder_cmd(file, fh, p);
- if (!ret)
- dbgarg(cmd, "cmd=%d, flags=%x\n", p->cmd, p->flags);
- break;
- }
- case VIDIOC_G_PARM:
- {
- struct v4l2_streamparm *p=arg;
- __u32 type=p->type;
-
- memset(p,0,sizeof(*p));
- p->type=type;
-
- if (vfd->vidioc_g_parm) {
- ret=vfd->vidioc_g_parm(file, fh, p);
- } else {
- struct v4l2_standard s;
-
- if (p->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
- return -EINVAL;
-
- v4l2_video_std_construct(&s, vfd->current_norm,
- v4l2_norm_to_name(vfd->current_norm));
-
- p->parm.capture.timeperframe = s.frameperiod;
- ret=0;
- }
-
- dbgarg (cmd, "type=%d\n", p->type);
- break;
- }
- case VIDIOC_S_PARM:
- {
- struct v4l2_streamparm *p=arg;
- if (!vfd->vidioc_s_parm)
- break;
- dbgarg (cmd, "type=%d\n", p->type);
- ret=vfd->vidioc_s_parm(file, fh, p);
- break;
- }
- case VIDIOC_G_TUNER:
- {
- struct v4l2_tuner *p = arg;
- __u32 index = p->index;
-
- if (!vfd->vidioc_g_tuner)
- break;
-
- memset(p, 0, sizeof(*p));
- p->index = index;
-
- ret = vfd->vidioc_g_tuner(file, fh, p);
- if (!ret)
- dbgarg(cmd, "index=%d, name=%s, type=%d, "
- "capability=0x%x, rangelow=%d, "
- "rangehigh=%d, signal=%d, afc=%d, "
- "rxsubchans=0x%x, audmode=%d\n",
- p->index, p->name, p->type,
- p->capability, p->rangelow,
- p->rangehigh, p->signal, p->afc,
- p->rxsubchans, p->audmode);
- break;
- }
- case VIDIOC_S_TUNER:
- {
- struct v4l2_tuner *p = arg;
-
- if (!vfd->vidioc_s_tuner)
- break;
- dbgarg(cmd, "index=%d, name=%s, type=%d, "
- "capability=0x%x, rangelow=%d, "
- "rangehigh=%d, signal=%d, afc=%d, "
- "rxsubchans=0x%x, audmode=%d\n",
- p->index, p->name, p->type,
- p->capability, p->rangelow,
- p->rangehigh, p->signal, p->afc,
- p->rxsubchans, p->audmode);
- ret = vfd->vidioc_s_tuner(file, fh, p);
- break;
- }
- case VIDIOC_G_FREQUENCY:
- {
- struct v4l2_frequency *p = arg;
-
- if (!vfd->vidioc_g_frequency)
- break;
-
- memset(p->reserved, 0, sizeof(p->reserved));
-
- ret = vfd->vidioc_g_frequency(file, fh, p);
- if (!ret)
- dbgarg(cmd, "tuner=%d, type=%d, frequency=%d\n",
- p->tuner, p->type, p->frequency);
- break;
- }
- case VIDIOC_S_FREQUENCY:
- {
- struct v4l2_frequency *p=arg;
- if (!vfd->vidioc_s_frequency)
- break;
- dbgarg (cmd, "tuner=%d, type=%d, frequency=%d\n",
- p->tuner,p->type,p->frequency);
- ret=vfd->vidioc_s_frequency(file, fh, p);
- break;
- }
- case VIDIOC_G_SLICED_VBI_CAP:
- {
- struct v4l2_sliced_vbi_cap *p = arg;
- __u32 type = p->type;
-
- if (!vfd->vidioc_g_sliced_vbi_cap)
- break;
- memset(p, 0, sizeof(*p));
- p->type = type;
- dbgarg(cmd, "type=%s\n", prt_names(p->type, v4l2_type_names));
- ret = vfd->vidioc_g_sliced_vbi_cap(file, fh, p);
- if (!ret)
- dbgarg2("service_set=%d\n", p->service_set);
- break;
- }
- case VIDIOC_LOG_STATUS:
- {
- if (!vfd->vidioc_log_status)
- break;
- ret=vfd->vidioc_log_status(file, fh);
- break;
- }
-#ifdef CONFIG_VIDEO_ADV_DEBUG
- case VIDIOC_DBG_G_REGISTER:
- {
- struct v4l2_register *p=arg;
- if (!capable(CAP_SYS_ADMIN))
- ret=-EPERM;
- else if (vfd->vidioc_g_register)
- ret=vfd->vidioc_g_register(file, fh, p);
- break;
- }
- case VIDIOC_DBG_S_REGISTER:
- {
- struct v4l2_register *p=arg;
- if (!capable(CAP_SYS_ADMIN))
- ret=-EPERM;
- else if (vfd->vidioc_s_register)
- ret=vfd->vidioc_s_register(file, fh, p);
- break;
- }
-#endif
- case VIDIOC_G_CHIP_IDENT:
- {
- struct v4l2_chip_ident *p=arg;
- if (!vfd->vidioc_g_chip_ident)
- break;
- ret=vfd->vidioc_g_chip_ident(file, fh, p);
- if (!ret)
- dbgarg (cmd, "chip_ident=%u, revision=0x%x\n", p->ident, p->revision);
- break;
- }
- default:
- {
- if (!vfd->vidioc_default)
- break;
- ret = vfd->vidioc_default(file, fh, cmd, arg);
- break;
- }
- case VIDIOC_S_HW_FREQ_SEEK:
- {
- struct v4l2_hw_freq_seek *p = arg;
- if (!vfd->vidioc_s_hw_freq_seek)
- break;
- dbgarg(cmd,
- "tuner=%d, type=%d, seek_upward=%d, wrap_around=%d\n",
- p->tuner, p->type, p->seek_upward, p->wrap_around);
- ret = vfd->vidioc_s_hw_freq_seek(file, fh, p);
- break;
- }
- } /* switch */
-
- if (vfd->debug & V4L2_DEBUG_IOCTL_ARG) {
- if (ret < 0) {
- v4l_print_ioctl(vfd->name, cmd);
- printk(KERN_CONT " error %d\n", ret);
- }
- }
-
- return ret;
-}
-
-int video_ioctl2 (struct inode *inode, struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- char sbuf[128];
- void *mbuf = NULL;
- void *parg = NULL;
- int err = -EINVAL;
- int is_ext_ctrl;
- size_t ctrls_size = 0;
- void __user *user_ptr = NULL;
-
-#ifdef __OLD_VIDIOC_
- cmd = video_fix_command(cmd);
-#endif
- is_ext_ctrl = (cmd == VIDIOC_S_EXT_CTRLS || cmd == VIDIOC_G_EXT_CTRLS ||
- cmd == VIDIOC_TRY_EXT_CTRLS);
-
- /* Copy arguments into temp kernel buffer */
- switch (_IOC_DIR(cmd)) {
- case _IOC_NONE:
- parg = NULL;
- break;
- case _IOC_READ:
- case _IOC_WRITE:
- case (_IOC_WRITE | _IOC_READ):
- if (_IOC_SIZE(cmd) <= sizeof(sbuf)) {
- parg = sbuf;
- } else {
- /* too big to allocate from stack */
- mbuf = kmalloc(_IOC_SIZE(cmd),GFP_KERNEL);
- if (NULL == mbuf)
- return -ENOMEM;
- parg = mbuf;
- }
-
- err = -EFAULT;
- if (_IOC_DIR(cmd) & _IOC_WRITE)
- if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd)))
- goto out;
- break;
- }
-
- if (is_ext_ctrl) {
- struct v4l2_ext_controls *p = parg;
-
- /* In case of an error, tell the caller that it wasn't
- a specific control that caused it. */
- p->error_idx = p->count;
- user_ptr = (void __user *)p->controls;
- if (p->count) {
- ctrls_size = sizeof(struct v4l2_ext_control) * p->count;
- /* Note: v4l2_ext_controls fits in sbuf[] so mbuf is still NULL. */
- mbuf = kmalloc(ctrls_size, GFP_KERNEL);
- err = -ENOMEM;
- if (NULL == mbuf)
- goto out_ext_ctrl;
- err = -EFAULT;
- if (copy_from_user(mbuf, user_ptr, ctrls_size))
- goto out_ext_ctrl;
- p->controls = mbuf;
- }
- }
-
- /* Handles IOCTL */
- err = __video_do_ioctl(inode, file, cmd, parg);
- if (err == -ENOIOCTLCMD)
- err = -EINVAL;
- if (is_ext_ctrl) {
- struct v4l2_ext_controls *p = parg;
-
- p->controls = (void *)user_ptr;
- if (p->count && err == 0 && copy_to_user(user_ptr, mbuf, ctrls_size))
- err = -EFAULT;
- goto out_ext_ctrl;
- }
- if (err < 0)
- goto out;
-
-out_ext_ctrl:
- /* Copy results into user buffer */
- switch (_IOC_DIR(cmd))
- {
- case _IOC_READ:
- case (_IOC_WRITE | _IOC_READ):
- if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd)))
- err = -EFAULT;
- break;
- }
-
-out:
- kfree(mbuf);
- return err;
-}
-EXPORT_SYMBOL(video_ioctl2);
-
-/**
- * get_index - assign stream number based on parent device
- * @vdev: video_device to assign index number to, vdev->dev should be assigned
- * @num: -1 if auto assign, requested number otherwise
- *
- *
- * returns -ENFILE if num is already in use, a free index number if
- * successful.
- */
-static int get_index(struct video_device *vdev, int num)
-{
- u32 used = 0;
- const int max_index = sizeof(used) * 8 - 1;
- int i;
-
- /* Currently a single v4l driver instance cannot create more than
- 32 devices.
- Increase to u64 or an array of u32 if more are needed. */
- if (num > max_index) {
- printk(KERN_ERR "videodev: %s num is too large\n", __func__);
- return -EINVAL;
- }
-
- for (i = 0; i < VIDEO_NUM_DEVICES; i++) {
- if (video_device[i] != NULL &&
- video_device[i] != vdev &&
- video_device[i]->dev == vdev->dev) {
- used |= 1 << video_device[i]->index;
- }
- }
-
- if (num >= 0) {
- if (used & (1 << num))
- return -ENFILE;
- return num;
- }
-
- i = ffz(used);
- return i > max_index ? -ENFILE : i;
-}
-
-static const struct file_operations video_fops;
-
-int video_register_device(struct video_device *vfd, int type, int nr)
-{
- return video_register_device_index(vfd, type, nr, -1);
-}
-EXPORT_SYMBOL(video_register_device);
-
-/**
- * video_register_device - register video4linux devices
- * @vfd: video device structure we want to register
- * @type: type of device to register
- * @nr: which device number (0 == /dev/video0, 1 == /dev/video1, ...
- * -1 == first free)
- *
- * The registration code assigns minor numbers based on the type
- * requested. -ENFILE is returned in all the device slots for this
- * category are full. If not then the minor field is set and the
- * driver initialize function is called (if non %NULL).
- *
- * Zero is returned on success.
- *
- * Valid types are
- *
- * %VFL_TYPE_GRABBER - A frame grabber
- *
- * %VFL_TYPE_VTX - A teletext device
- *
- * %VFL_TYPE_VBI - Vertical blank data (undecoded)
- *
- * %VFL_TYPE_RADIO - A radio card
- */
-
-int video_register_device_index(struct video_device *vfd, int type, int nr,
- int index)
-{
- int i=0;
- int base;
- int end;
- int ret;
- char *name_base;
-
- switch(type)
- {
- case VFL_TYPE_GRABBER:
- base=MINOR_VFL_TYPE_GRABBER_MIN;
- end=MINOR_VFL_TYPE_GRABBER_MAX+1;
- name_base = "video";
- break;
- case VFL_TYPE_VTX:
- base=MINOR_VFL_TYPE_VTX_MIN;
- end=MINOR_VFL_TYPE_VTX_MAX+1;
- name_base = "vtx";
- break;
- case VFL_TYPE_VBI:
- base=MINOR_VFL_TYPE_VBI_MIN;
- end=MINOR_VFL_TYPE_VBI_MAX+1;
- name_base = "vbi";
- break;
- case VFL_TYPE_RADIO:
- base=MINOR_VFL_TYPE_RADIO_MIN;
- end=MINOR_VFL_TYPE_RADIO_MAX+1;
- name_base = "radio";
- break;
- default:
- printk(KERN_ERR "%s called with unknown type: %d\n",
- __func__, type);
- return -1;
- }
-
- /* pick a minor number */
- mutex_lock(&videodev_lock);
- if (nr >= 0 && nr < end-base) {
- /* use the one the driver asked for */
- i = base+nr;
- if (NULL != video_device[i]) {
- mutex_unlock(&videodev_lock);
- return -ENFILE;
- }
- } else {
- /* use first free */
- for(i=base;i<end;i++)
- if (NULL == video_device[i])
- break;
- if (i == end) {
- mutex_unlock(&videodev_lock);
- return -ENFILE;
- }
- }
- video_device[i]=vfd;
- vfd->minor=i;
-
- ret = get_index(vfd, index);
- vfd->index = ret;
-
- mutex_unlock(&videodev_lock);
-
- if (ret < 0) {
- printk(KERN_ERR "%s: get_index failed\n", __func__);
- goto fail_minor;
- }
-
- mutex_init(&vfd->lock);
-
- /* sysfs class */
- memset(&vfd->class_dev, 0x00, sizeof(vfd->class_dev));
- vfd->class_dev.class = &video_class;
- vfd->class_dev.devt = MKDEV(VIDEO_MAJOR, vfd->minor);
- if (vfd->dev)
- vfd->class_dev.parent = vfd->dev;
- sprintf(vfd->class_dev.bus_id, "%s%d", name_base, i - base);
- ret = device_register(&vfd->class_dev);
- if (ret < 0) {
- printk(KERN_ERR "%s: device_register failed\n", __func__);
- goto fail_minor;
- }
-
-#if 1
- /* needed until all drivers are fixed */
- if (!vfd->release)
- printk(KERN_WARNING "videodev: \"%s\" has no release callback. "
- "Please fix your driver for proper sysfs support, see "
- "http://lwn.net/Articles/36850/\n", vfd->name);
-#endif
- return 0;
-
-fail_minor:
- mutex_lock(&videodev_lock);
- video_device[vfd->minor] = NULL;
- vfd->minor = -1;
- mutex_unlock(&videodev_lock);
- return ret;
-}
-EXPORT_SYMBOL(video_register_device_index);
-
-/**
- * video_unregister_device - unregister a video4linux device
- * @vfd: the device to unregister
- *
- * This unregisters the passed device and deassigns the minor
- * number. Future open calls will be met with errors.
- */
-
-void video_unregister_device(struct video_device *vfd)
-{
- mutex_lock(&videodev_lock);
- if(video_device[vfd->minor]!=vfd)
- panic("videodev: bad unregister");
-
- video_device[vfd->minor]=NULL;
- device_unregister(&vfd->class_dev);
- mutex_unlock(&videodev_lock);
-}
-EXPORT_SYMBOL(video_unregister_device);
-
-/*
- * Video fs operations
- */
-static const struct file_operations video_fops=
-{
- .owner = THIS_MODULE,
- .llseek = no_llseek,
- .open = video_open,
-};
-
-/*
- * Initialise video for linux
- */
-
-static int __init videodev_init(void)
-{
- int ret;
-
- printk(KERN_INFO "Linux video capture interface: v2.00\n");
- if (register_chrdev(VIDEO_MAJOR, VIDEO_NAME, &video_fops)) {
- printk(KERN_WARNING "video_dev: unable to get major %d\n", VIDEO_MAJOR);
- return -EIO;
- }
-
- ret = class_register(&video_class);
- if (ret < 0) {
- unregister_chrdev(VIDEO_MAJOR, VIDEO_NAME);
- printk(KERN_WARNING "video_dev: class_register failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static void __exit videodev_exit(void)
-{
- class_unregister(&video_class);
- unregister_chrdev(VIDEO_MAJOR, VIDEO_NAME);
-}
-
-module_init(videodev_init)
-module_exit(videodev_exit)
-
-MODULE_AUTHOR("Alan Cox, Mauro Carvalho Chehab <mchehab@infradead.org>");
-MODULE_DESCRIPTION("Device registrar for Video4Linux drivers v2");
-MODULE_LICENSE("GPL");
-
-
-/*
- * Local variables:
- * c-basic-offset: 8
- * End:
- */
#include <linux/i2c.h>
#include <linux/i2c-algo-sgi.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <linux/video_decoder.h>
#include <linux/mutex.h>
static struct video_device v4l_device_template = {
.name = "NOT SET",
- /*.type = VID_TYPE_CAPTURE | VID_TYPE_SUBCAPTURE | */
- /* VID_TYPE_CLIPPING | VID_TYPE_SCALES, VID_TYPE_OVERLAY */
.fops = &vino_fops,
.minor = -1,
};
#include <linux/interrupt.h>
#include <media/videobuf-vmalloc.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/kthread.h>
#include <linux/highmem.h>
#include <linux/freezer.h>
.llseek = no_llseek,
};
-static struct video_device vivi_template = {
- .name = "vivi",
- .type = VID_TYPE_CAPTURE,
- .fops = &vivi_fops,
- .minor = -1,
- .release = video_device_release,
-
+static const struct v4l2_ioctl_ops vivi_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
#ifdef CONFIG_VIDEO_V4L1_COMPAT
.vidiocgmbuf = vidiocgmbuf,
#endif
+};
+
+static struct video_device vivi_template = {
+ .name = "vivi",
+ .fops = &vivi_fops,
+ .ioctl_ops = &vivi_ioctl_ops,
+ .minor = -1,
+ .release = video_device_release,
+
.tvnorms = V4L2_STD_525_60,
.current_norm = V4L2_STD_NTSC_M,
};
#include <asm/uaccess.h>
#include <linux/i2c.h>
#include <linux/i2c-id.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <media/v4l2-chip-ident.h>
#include <media/v4l2-i2c-drv.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/parport.h>
/*#define DEBUG*/ /* Undef me for production */
.llseek = no_llseek,
};
static struct video_device w9966_template = {
- .owner = THIS_MODULE,
.name = W9966_DRIVERNAME,
- .type = VID_TYPE_CAPTURE | VID_TYPE_SCALES,
.fops = &w9966_fops,
};
#include <asm/page.h>
#include <asm/uaccess.h>
#include <linux/page-flags.h>
+#include <media/v4l2-ioctl.h>
#include "w9968cf.h"
#include "w9968cf_decoder.h"
}
strcpy(cam->v4ldev->name, symbolic(camlist, mod_id));
- cam->v4ldev->owner = THIS_MODULE;
- cam->v4ldev->type = VID_TYPE_CAPTURE | VID_TYPE_SCALES;
cam->v4ldev->fops = &w9968cf_fops;
cam->v4ldev->minor = video_nr[dev_nr];
cam->v4ldev->release = video_device_release;
video_set_drvdata(cam->v4ldev, cam);
- cam->v4ldev->dev = &cam->dev;
+ cam->v4ldev->parent = &cam->dev;
err = video_register_device(cam->v4ldev, VFL_TYPE_GRABBER,
video_nr[dev_nr]);
#ifndef _W9968CF_H_
#define _W9968CF_H_
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <linux/usb.h>
#include <linux/i2c.h>
#include <linux/device.h>
#include <asm/uaccess.h>
#include <linux/i2c.h>
#include <linux/i2c-id.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <media/v4l2-chip-ident.h>
#include <media/v4l2-i2c-drv.h>
#include <asm/uaccess.h>
#include <linux/i2c.h>
#include <linux/i2c-id.h>
-#include <linux/videodev.h>
+#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <media/v4l2-chip-ident.h>
#include <media/v4l2-i2c-drv-legacy.h>
#include <linux/usb.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/spinlock.h>
}
strcpy(cam->v4ldev->name, "ZC0301[P] PC Camera");
- cam->v4ldev->owner = THIS_MODULE;
- cam->v4ldev->type = VID_TYPE_CAPTURE | VID_TYPE_SCALES;
cam->v4ldev->fops = &zc0301_fops;
cam->v4ldev->minor = video_nr[dev_nr];
cam->v4ldev->release = video_device_release;
MODULE_DEVICE_TABLE(pci, zr36067_pci_tbl);
int zoran_num; /* number of Buzs in use */
-struct zoran zoran[BUZ_MAX];
+struct zoran *zoran[BUZ_MAX];
/* videocodec bus functions ZR36060 */
static u32
case I2C_DRIVERID_BT856:
name = "bt856";
break;
+ case I2C_DRIVERID_BT866:
+ name = "bt866";
+ break;
case I2C_DRIVERID_VPX3220:
name = "vpx3220";
break;
+ case I2C_DRIVERID_KS0127:
+ name = "ks0127";
+ break;
}
return name;
zoran_release (struct zoran *zr)
{
if (!zr->initialized)
- return;
+ goto exit_free;
/* unregister videocodec bus */
if (zr->codec) {
struct videocodec_master *master = zr->codec->master_data;
iounmap(zr->zr36057_mem);
pci_disable_device(zr->pci_dev);
video_unregister_device(zr->video_dev);
+exit_free:
+ kfree(zr);
}
void
while (zoran_num < BUZ_MAX &&
(dev = pci_get_device(PCI_VENDOR_ID_ZORAN, PCI_DEVICE_ID_ZORAN_36057, dev)) != NULL) {
card_num = card[zoran_num];
- zr = &zoran[zoran_num];
- memset(zr, 0, sizeof(struct zoran)); // Just in case if previous cycle failed
+ zr = kzalloc(sizeof(struct zoran), GFP_KERNEL);
+ if (!zr) {
+ dprintk(1,
+ KERN_ERR
+ "%s: find_zr36057() - kzalloc failed\n",
+ ZORAN_NAME);
+ continue;
+ }
zr->pci_dev = dev;
//zr->zr36057_mem = NULL;
zr->id = zoran_num;
spin_lock_init(&zr->spinlock);
mutex_init(&zr->resource_lock);
if (pci_enable_device(dev))
- continue;
+ goto zr_free_mem;
zr->zr36057_adr = pci_resource_start(zr->pci_dev, 0);
pci_read_config_byte(zr->pci_dev, PCI_CLASS_REVISION,
&zr->revision);
KERN_ERR
"%s: find_zr36057() - no card specified, please use the card=X insmod option\n",
ZR_DEVNAME(zr));
- continue;
+ goto zr_free_mem;
}
} else {
int i;
KERN_ERR
"%s: find_zr36057() - unknown card\n",
ZR_DEVNAME(zr));
- continue;
+ goto zr_free_mem;
}
}
}
KERN_ERR
"%s: find_zr36057() - invalid cardnum %d\n",
ZR_DEVNAME(zr), card_num);
- continue;
+ goto zr_free_mem;
}
/* even though we make this a non pointer and thus
KERN_ERR
"%s: find_zr36057() - ioremap failed\n",
ZR_DEVNAME(zr));
- continue;
+ goto zr_free_mem;
}
result = request_irq(zr->pci_dev->irq,
}
/* Success so keep the pci_dev referenced */
pci_dev_get(zr->pci_dev);
- zoran_num++;
+ zoran[zoran_num++] = zr;
continue;
// Init errors
free_irq(zr->pci_dev->irq, zr);
zr_unmap:
iounmap(zr->zr36057_mem);
+ zr_free_mem:
+ kfree(zr);
continue;
}
if (dev) /* Clean up ref count on early exit */
/* take care of Natoma chipset and a revision 1 zr36057 */
for (i = 0; i < zoran_num; i++) {
- struct zoran *zr = &zoran[i];
+ struct zoran *zr = zoran[i];
if ((pci_pci_problems & PCIPCI_NATOMA) && zr->revision <= 1) {
zr->jpg_buffers.need_contiguous = 1;
if (zr36057_init(zr) < 0) {
for (i = 0; i < zoran_num; i++)
- zoran_release(&zoran[i]);
+ zoran_release(zoran[i]);
return -EIO;
}
zoran_proc_init(zr);
int i;
for (i = 0; i < zoran_num; i++)
- zoran_release(&zoran[i]);
+ zoran_release(zoran[i]);
}
module_init(init_dc10_cards);
/* Anybody who uses more than four? */
#define BUZ_MAX 4
extern int zoran_num;
-extern struct zoran zoran[BUZ_MAX];
+extern struct zoran *zoran[BUZ_MAX];
extern struct video_device zoran_template;
#include <linux/videodev.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include "videocodec.h"
#include <asm/byteorder.h>
/* find the device */
for (i = 0; i < zoran_num; i++) {
- if (zoran[i].video_dev->minor == minor) {
- zr = &zoran[i];
+ if (zoran[i]->video_dev->minor == minor) {
+ zr = zoran[i];
break;
}
}
struct video_device zoran_template __devinitdata = {
.name = ZORAN_NAME,
- .type = ZORAN_VID_TYPE,
- .type2 = ZORAN_V4L2_VID_FLAGS,
.fops = &zoran_fops,
.release = &zoran_vdev_release,
.minor = -1
#include <linux/proc_fs.h>
#include <linux/highmem.h>
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
/* Version Information */
.llseek = no_llseek,
};
-static struct video_device zr364xx_template = {
- .owner = THIS_MODULE,
- .name = DRIVER_DESC,
- .type = VID_TYPE_CAPTURE,
- .fops = &zr364xx_fops,
- .release = video_device_release,
- .minor = -1,
-
+static const struct v4l2_ioctl_ops zr364xx_ioctl_ops = {
.vidioc_querycap = zr364xx_vidioc_querycap,
.vidioc_enum_fmt_vid_cap = zr364xx_vidioc_enum_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = zr364xx_vidioc_try_fmt_vid_cap,
.vidioc_s_ctrl = zr364xx_vidioc_s_ctrl,
};
+static struct video_device zr364xx_template = {
+ .name = DRIVER_DESC,
+ .fops = &zr364xx_fops,
+ .ioctl_ops = &zr364xx_ioctl_ops,
+ .release = video_device_release,
+ .minor = -1,
+};
+
/*******************/
bank + ASIC3_GPIO_TRIGGER_TYPE);
asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
- if (type == IRQT_RISING) {
+ if (type == IRQ_TYPE_EDGE_RISING) {
trigger |= bit;
edge |= bit;
- } else if (type == IRQT_FALLING) {
+ } else if (type == IRQ_TYPE_EDGE_FALLING) {
trigger |= bit;
edge &= ~bit;
- } else if (type == IRQT_BOTHEDGE) {
+ } else if (type == IRQ_TYPE_EDGE_BOTH) {
trigger |= bit;
if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
edge &= ~bit;
else
edge |= bit;
asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
- } else if (type == IRQT_LOW) {
+ } else if (type == IRQ_TYPE_LEVEL_LOW) {
trigger &= ~bit;
level &= ~bit;
- } else if (type == IRQT_HIGH) {
+ } else if (type == IRQ_TYPE_LEVEL_HIGH) {
trigger &= ~bit;
level |= bit;
} else {
/*
- * if type == IRQT_NOEDGE, we should mask interrupts, but
+ * if type == IRQ_TYPE_NONE, we should mask interrupts, but
* be careful to not unmask them if mask was also called.
* Probably need internal state for mask.
*/
ASIC3_INTMASK_GINTMASK);
set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
- set_irq_type(asic->irq_nr, IRQT_RISING);
+ set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
set_irq_data(asic->irq_nr, asic);
return 0;
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
- set_irq_type(tc6393xb->irq, IRQT_FALLING);
+ set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING);
set_irq_data(tc6393xb->irq, tc6393xb);
set_irq_chained_handler(tc6393xb->irq, tc6393xb_irq);
}
*/
if (skt->irq_state != 1 && state->io_irq) {
skt->irq_state = 1;
- set_irq_type(skt->irq, IRQT_FALLING);
+ set_irq_type(skt->irq, IRQ_TYPE_EDGE_FALLING);
} else if (skt->irq_state == 1 && state->io_irq == 0) {
skt->irq_state = 0;
- set_irq_type(skt->irq, IRQT_NOEDGE);
+ set_irq_type(skt->irq, IRQ_TYPE_NONE);
}
skt->cs_state = *state;
IRQF_DISABLED, irqs[i].str, skt);
if (res)
break;
- set_irq_type(irqs[i].irq, IRQT_NOEDGE);
+ set_irq_type(irqs[i].irq, IRQ_TYPE_NONE);
}
if (res) {
for (i = 0; i < nr; i++)
if (irqs[i].sock == skt->nr)
- set_irq_type(irqs[i].irq, IRQT_NOEDGE);
+ set_irq_type(irqs[i].irq, IRQ_TYPE_NONE);
}
EXPORT_SYMBOL(soc_pcmcia_disable_irqs);
for (i = 0; i < nr; i++)
if (irqs[i].sock == skt->nr) {
- set_irq_type(irqs[i].irq, IRQT_RISING);
- set_irq_type(irqs[i].irq, IRQT_BOTHEDGE);
+ set_irq_type(irqs[i].irq, IRQ_TYPE_EDGE_RISING);
+ set_irq_type(irqs[i].irq, IRQ_TYPE_EDGE_BOTH);
}
}
EXPORT_SYMBOL(soc_pcmcia_enable_irqs);
return retval;
}
- return set_irq_type(IRQ_GPIO(RDY_GPIO_PIN), IRQT_FALLING);
+ return set_irq_type(IRQ_GPIO(RDY_GPIO_PIN), IRQ_TYPE_EDGE_FALLING);
}
static void am200_set_rst(struct metronomefb_par *par, int state)
sossi_write_reg(SOSSI_INIT1_REG, l);
if ((r = request_irq(INT_1610_SoSSI_MATCH, sossi_match_irq,
- IRQT_FALLING,
+ IRQ_TYPE_EDGE_FALLING,
"sossi_match", sossi.fbdev->dev)) < 0) {
dev_err(sossi.fbdev->dev, "can't get SoSSI match IRQ\n");
goto err;
fbi->dma_buff_phys = fbi->map_dma;
fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
- pr_debug("pxafb: palette_mem_size = 0x%08lx\n", fbi->palette_size*sizeof(u16));
+ pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16));
#ifdef CONFIG_FB_PXA_SMARTPANEL
fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
* ones were explicitly specified. Fall back to legacy behavior and
* just return success.
*/
- if ((nfsvers == 4 && options4->version == 1) ||
- (nfsvers <= 3 && options->version >= 1 &&
- options->version <= 6))
+ if ((nfsvers == 4 && (!options4 || options4->version == 1)) ||
+ (nfsvers <= 3 && (!options || (options->version >= 1 &&
+ options->version <= 6))))
return 0;
data = kzalloc(sizeof(*data), GFP_KERNEL);
static void nfs_async_unlink_release(void *calldata)
{
struct nfs_unlinkdata *data = calldata;
+ struct super_block *sb = data->dir->i_sb;
nfs_dec_sillycount(data->dir);
- nfs_sb_deactive(NFS_SERVER(data->dir));
nfs_free_unlinkdata(data);
+ nfs_sb_deactive(NFS_SB(sb));
}
static const struct rpc_call_ops nfs_unlink_ops = {
#ifdef CONFIG_TASK_IO_ACCOUNTING
static int do_io_accounting(struct task_struct *task, char *buffer, int whole)
{
- struct proc_io_accounting acct = task->ioac;
+ struct task_io_accounting acct = task->ioac;
unsigned long flags;
if (whole && lock_task_sighand(task, &flags)) {
"read_bytes: %llu\n"
"write_bytes: %llu\n"
"cancelled_write_bytes: %llu\n",
- acct.chr.rchar, acct.chr.wchar,
- acct.chr.syscr, acct.chr.syscw,
- acct.blk.read_bytes, acct.blk.write_bytes,
- acct.blk.cancelled_write_bytes);
+ acct.rchar, acct.wchar,
+ acct.syscr, acct.syscw,
+ acct.read_bytes, acct.write_bytes,
+ acct.cancelled_write_bytes);
}
static int proc_tid_io_accounting(struct task_struct *task, char *buffer)
#define PNX4008_IRQ_TYPES \
{ /*IRQ #'s: */ \
-IRQT_LOW, IRQT_LOW, IRQT_LOW, IRQT_HIGH, /* 0, 1, 2, 3 */ \
-IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 4, 5, 6, 7 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 8, 9,10,11 */ \
-IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 12,13,14,15 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 16,17,18,19 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 20,21,22,23 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 24,25,26,27 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 28,29,30,31 */ \
-IRQT_HIGH, IRQT_LOW, IRQT_HIGH, IRQT_HIGH, /* 32,33,34,35 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_FALLING, IRQT_HIGH, /* 36,37,38,39 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 40,41,42,43 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 44,45,46,47 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 48,49,50,51 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 52,53,54,55 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_HIGH, /* 56,57,58,59 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 60,61,62,63 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 64,65,66,67 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 68,69,70,71 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 72,73,74,75 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 76,77,78,79 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 80,81,82,83 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 84,85,86,87 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 88,89,90,91 */ \
-IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 92,93,94,95 */ \
+IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 0, 1, 2, 3 */ \
+IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 4, 5, 6, 7 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 8, 9,10,11 */ \
+IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 28,29,30,31 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 48,49,50,51 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */ \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */ \
}
/* Start Enable Pin Interrupts - table 58 page 66 */
#define TOUCH_PANEL_IRQ IRQ_GPIO(5)
#define IDE_IRQ IRQ_GPIO(21)
-#define TOUCH_PANEL_IRQ_EDGE IRQT_FALLING
+#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
#define ETHERNET_IRQ IRQ_GPIO(4)
-#define ETHERNET_IRQ_EDGE IRQT_RISING
+#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING
-#define IDE_IRQ_EDGE IRQT_RISING
+#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define PCMCIA_S0_CD_VALID IRQ_GPIO(7)
-#define PCMCIA_S0_CD_VALID_EDGE IRQT_BOTHEDGE
+#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
#define PCMCIA_S1_CD_VALID IRQ_GPIO(8)
-#define PCMCIA_S1_CD_VALID_EDGE IRQT_BOTHEDGE
+#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
#define PCMCIA_S0_RDYINT IRQ_GPIO(19)
#define PCMCIA_S1_RDYINT IRQ_GPIO(22)
/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
#define PCM990_CTRL_INT_IRQ_GPIO 9
#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
-#define PCM990_CTRL_INT_IRQ_EDGE IRQT_RISING
+#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */
#define PCM990_CTRL_BASE 0xea000000
#define PCM990_CTRL_SIZE (1*1024*1024)
#define PCM990_CTRL_PWR_IRQ_GPIO 14
#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
-#define PCM990_CTRL_PWR_IRQ_EDGE IRQT_RISING
+#define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING
/* visible CPLD (U7) registers */
#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
*/
#define PCM990_IDE_IRQ_GPIO 13
#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
-#define PCM990_IDE_IRQ_EDGE IRQT_RISING
+#define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */
#define PCM990_IDE_PLD_BASE 0xee000000
#define PCM990_IDE_PLD_SIZE (1*1024*1024)
*/
#define PCM990_CF_IRQ_GPIO 11
#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO)
-#define PCM990_CF_IRQ_EDGE IRQT_RISING
+#define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define PCM990_CF_CD_GPIO 12
#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO)
-#define PCM990_CF_CD_EDGE IRQT_RISING
+#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING
#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */
#define PCM990_CF_PLD_BASE 0xef000000
*/
#define PCM990_AC97_IRQ_GPIO 10
#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
-#define PCM990_AC97_IRQ_EDGE IRQT_RISING
+#define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING
/*
* MMC phyCORE
*/
#define PCM990_MMC0_IRQ_GPIO 9
#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
-#define PCM990_MMC0_IRQ_EDGE IRQT_FALLING
+#define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
/*
* USB phyCore
#define _ASM_ARCH_PXA25X_UDC_H
#ifdef _ASM_ARCH_PXA27X_UDC_H
-#error You can't include both PXA25x and PXA27x UDC support
+#error "You can't include both PXA25x and PXA27x UDC support"
#endif
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
/* Enable GPIO as interrupt line */
GPDR &= ~LART_GPIO_IDE;
- set_irq_type(LART_IRQ_IDE, IRQT_RISING);
+ set_irq_type(LART_IRQ_IDE, IRQ_TYPE_EDGE_RISING);
/* set PCMCIA interface timing */
MECR = 0x00060006;
* the clz instruction for much better code efficiency.
*/
-#define fls(x) \
+#define __fls(x) \
( __builtin_constant_p(x) ? constant_fls(x) : \
({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) )
+
+/* Implement fls() in C so that 64-bit args are suitably truncated */
+static inline int fls(int x)
+{
+ return __fls(x);
+}
+
#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
#define __ffs(x) (ffs(x) - 1)
#define ffz(x) __ffs( ~(x) )
#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
-
+/*
+ * VIVT caches only
+ */
#define cache_is_vivt() 1
#define cache_is_vipt() 0
#define cache_is_vipt_nonaliasing() 0
#define cache_is_vipt_aliasing() 0
#define icache_is_vivt_asid_tagged() 0
-#elif defined(CONFIG_CPU_CACHE_VIPT)
-
+#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
+/*
+ * VIPT caches only
+ */
#define cache_is_vivt() 0
#define cache_is_vipt() 1
#define cache_is_vipt_nonaliasing() \
})
#else
-
+/*
+ * VIVT or VIPT caches. Note that this is unreliable since ARM926
+ * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
+ * There's no way to tell from the CacheType register what type (!)
+ * the cache is.
+ */
#define cache_is_vivt() \
({ \
unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
#define NO_IRQ ((unsigned int)(-1))
#endif
-
-/*
- * Migration helpers
- */
-#define __IRQT_FALEDGE IRQ_TYPE_EDGE_FALLING
-#define __IRQT_RISEDGE IRQ_TYPE_EDGE_RISING
-#define __IRQT_LOWLVL IRQ_TYPE_LEVEL_LOW
-#define __IRQT_HIGHLVL IRQ_TYPE_LEVEL_HIGH
-
-#define IRQT_NOEDGE (0)
-#define IRQT_RISING (__IRQT_RISEDGE)
-#define IRQT_FALLING (__IRQT_FALEDGE)
-#define IRQT_BOTHEDGE (__IRQT_RISEDGE|__IRQT_FALEDGE)
-#define IRQT_LOW (__IRQT_LOWLVL)
-#define IRQT_HIGH (__IRQT_HIGHLVL)
-#define IRQT_PROBE IRQ_TYPE_PROBE
-
#ifndef __ASSEMBLY__
struct irqaction;
extern void migrate_irqs(void);
return root;
}
+/*
+ * Dummy implementation; always return 0.
+ */
+static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+{
+ return 0;
+}
+
#endif /* __KERNEL__ */
#endif
*/
struct s3c2410_platform_i2c {
+ int bus_num; /* bus number to use */
unsigned int flags;
unsigned int slave_addr; /* slave address for controller */
unsigned long bus_freq; /* standard bus frequency */
+++ /dev/null
-# dummy file to avoid breaking make headers_install
+++ /dev/null
-#ifndef AGP_H
-#define AGP_H 1
-
-/* dummy for now */
-
-#define map_page_into_agp(page)
-#define unmap_page_from_agp(page)
-#define flush_agp_cache() mb()
-
-/* Convert a physical address to an address suitable for the GART. */
-#define phys_to_gart(x) (x)
-#define gart_to_phys(x) (x)
-
-/* GATT allocation. Returns/accepts GATT kernel virtual address. */
-#define alloc_gatt_pages(order) \
- ((char *)__get_free_pages(GFP_KERNEL, (order)))
-#define free_gatt_pages(table, order) \
- free_pages((unsigned long)(table), (order))
-
-#endif
+++ /dev/null
-/*
- * apb.h: Advanced PCI Bridge Configuration Registers and Bits
- *
- * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
- */
-
-#ifndef _SPARC64_APB_H
-#define _SPARC64_APB_H
-
-#define APB_TICK_REGISTER 0xb0
-#define APB_INT_ACK 0xb8
-#define APB_PRIMARY_MASTER_RETRY_LIMIT 0xc0
-#define APB_DMA_ASFR 0xc8
-#define APB_DMA_AFAR 0xd0
-#define APB_PIO_TARGET_RETRY_LIMIT 0xd8
-#define APB_PIO_TARGET_LATENCY_TIMER 0xd9
-#define APB_DMA_TARGET_RETRY_LIMIT 0xda
-#define APB_DMA_TARGET_LATENCY_TIMER 0xdb
-#define APB_SECONDARY_MASTER_RETRY_LIMIT 0xdc
-#define APB_SECONDARY_CONTROL 0xdd
-#define APB_IO_ADDRESS_MAP 0xde
-#define APB_MEM_ADDRESS_MAP 0xdf
-
-#define APB_PCI_CONTROL_LOW 0xe0
-# define APB_PCI_CTL_LOW_ARB_PARK (1 << 21)
-# define APB_PCI_CTL_LOW_ERRINT_EN (1 << 8)
-
-#define APB_PCI_CONTROL_HIGH 0xe4
-# define APB_PCI_CTL_HIGH_SERR (1 << 2)
-# define APB_PCI_CTL_HIGH_ARBITER_EN (1 << 0)
-
-#define APB_PIO_ASFR 0xe8
-#define APB_PIO_AFAR 0xf0
-#define APB_DIAG_REGISTER 0xf8
-
-#endif /* !(_SPARC64_APB_H) */
+++ /dev/null
-/* apc - Driver definitions for power management functions
- * of Aurora Personality Chip (APC) on SPARCstation-4/5 and
- * derivatives
- *
- * Copyright (c) 2001 Eric Brower (ebrower@usa.net)
- *
- */
-
-#ifndef _SPARC_APC_H
-#define _SPARC_APC_H
-
-#include <linux/ioctl.h>
-
-#define APC_IOC 'A'
-
-#define APCIOCGFANCTL _IOR(APC_IOC, 0x00, int) /* Get fan speed */
-#define APCIOCSFANCTL _IOW(APC_IOC, 0x01, int) /* Set fan speed */
-
-#define APCIOCGCPWR _IOR(APC_IOC, 0x02, int) /* Get CPOWER state */
-#define APCIOCSCPWR _IOW(APC_IOC, 0x03, int) /* Set CPOWER state */
-
-#define APCIOCGBPORT _IOR(APC_IOC, 0x04, int) /* Get BPORT state */
-#define APCIOCSBPORT _IOW(APC_IOC, 0x05, int) /* Set BPORT state */
-
-/*
- * Register offsets
- */
-#define APC_IDLE_REG 0x00
-#define APC_FANCTL_REG 0x20
-#define APC_CPOWER_REG 0x24
-#define APC_BPORT_REG 0x30
-
-#define APC_REGMASK 0x01
-#define APC_BPMASK 0x03
-
-/*
- * IDLE - CPU standby values (set to initiate standby)
- */
-#define APC_IDLE_ON 0x01
-
-/*
- * FANCTL - Fan speed control state values
- */
-#define APC_FANCTL_HI 0x00 /* Fan speed high */
-#define APC_FANCTL_LO 0x01 /* Fan speed low */
-
-/*
- * CPWR - Convenience power outlet state values
- */
-#define APC_CPOWER_ON 0x00 /* Conv power on */
-#define APC_CPOWER_OFF 0x01 /* Conv power off */
-
-/*
- * BPA/BPB - Read-Write "Bit Ports" state values (reset to 0 at power-on)
- *
- * WARNING: Internal usage of bit ports is platform dependent--
- * don't modify BPORT settings unless you know what you are doing.
- *
- * On SS5 BPA seems to toggle onboard ethernet loopback... -E
- */
-#define APC_BPORT_A 0x01 /* Bit Port A */
-#define APC_BPORT_B 0x02 /* Bit Port B */
-
-#endif /* !(_SPARC_APC_H) */
+++ /dev/null
-#ifndef _SPARC_ASI_H
-#define _SPARC_ASI_H
-
-/* asi.h: Address Space Identifier values for the sparc.
- *
- * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
- *
- * Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au)
- * Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su>
- */
-
-/* The first batch are for the sun4c. */
-
-#define ASI_NULL1 0x00
-#define ASI_NULL2 0x01
-
-/* sun4c and sun4 control registers and mmu/vac ops */
-#define ASI_CONTROL 0x02
-#define ASI_SEGMAP 0x03
-#define ASI_PTE 0x04
-#define ASI_HWFLUSHSEG 0x05
-#define ASI_HWFLUSHPAGE 0x06
-#define ASI_REGMAP 0x06
-#define ASI_HWFLUSHCONTEXT 0x07
-
-#define ASI_USERTXT 0x08
-#define ASI_KERNELTXT 0x09
-#define ASI_USERDATA 0x0a
-#define ASI_KERNELDATA 0x0b
-
-/* VAC Cache flushing on sun4c and sun4 */
-#define ASI_FLUSHSEG 0x0c
-#define ASI_FLUSHPG 0x0d
-#define ASI_FLUSHCTX 0x0e
-
-/* SPARCstation-5: only 6 bits are decoded. */
-/* wo = Write Only, rw = Read Write; */
-/* ss = Single Size, as = All Sizes; */
-#define ASI_M_RES00 0x00 /* Don't touch... */
-#define ASI_M_UNA01 0x01 /* Same here... */
-#define ASI_M_MXCC 0x02 /* Access to TI VIKING MXCC registers */
-#define ASI_M_FLUSH_PROBE 0x03 /* Reference MMU Flush/Probe; rw, ss */
-#define ASI_M_MMUREGS 0x04 /* MMU Registers; rw, ss */
-#define ASI_M_TLBDIAG 0x05 /* MMU TLB only Diagnostics */
-#define ASI_M_DIAGS 0x06 /* Reference MMU Diagnostics */
-#define ASI_M_IODIAG 0x07 /* MMU I/O TLB only Diagnostics */
-#define ASI_M_USERTXT 0x08 /* Same as ASI_USERTXT; rw, as */
-#define ASI_M_KERNELTXT 0x09 /* Same as ASI_KERNELTXT; rw, as */
-#define ASI_M_USERDATA 0x0A /* Same as ASI_USERDATA; rw, as */
-#define ASI_M_KERNELDATA 0x0B /* Same as ASI_KERNELDATA; rw, as */
-#define ASI_M_TXTC_TAG 0x0C /* Instruction Cache Tag; rw, ss */
-#define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */
-#define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */
-#define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */
-
-/* The following cache flushing ASIs work only with the 'sta'
- * instruction. Results are unpredictable for 'swap' and 'ldstuba',
- * so don't do it.
- */
-
-/* These ASI flushes affect external caches too. */
-#define ASI_M_FLUSH_PAGE 0x10 /* Flush I&D Cache Line (page); wo, ss */
-#define ASI_M_FLUSH_SEG 0x11 /* Flush I&D Cache Line (seg); wo, ss */
-#define ASI_M_FLUSH_REGION 0x12 /* Flush I&D Cache Line (region); wo, ss */
-#define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */
-#define ASI_M_FLUSH_USER 0x14 /* Flush I&D Cache Line (user); wo, ss */
-
-/* Block-copy operations are available only on certain V8 cpus. */
-#define ASI_M_BCOPY 0x17 /* Block copy */
-
-/* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */
-#define ASI_M_IFLUSH_PAGE 0x18 /* Flush I Cache Line (page); wo, ss */
-#define ASI_M_IFLUSH_SEG 0x19 /* Flush I Cache Line (seg); wo, ss */
-#define ASI_M_IFLUSH_REGION 0x1A /* Flush I Cache Line (region); wo, ss */
-#define ASI_M_IFLUSH_CTX 0x1B /* Flush I Cache Line (context); wo, ss */
-#define ASI_M_IFLUSH_USER 0x1C /* Flush I Cache Line (user); wo, ss */
-
-/* Block-fill operations are available on certain V8 cpus */
-#define ASI_M_BFILL 0x1F
-
-/* This allows direct access to main memory, actually 0x20 to 0x2f are
- * the available ASI's for physical ram pass-through, but I don't have
- * any idea what the other ones do....
- */
-
-#define ASI_M_BYPASS 0x20 /* Reference MMU bypass; rw, as */
-#define ASI_M_FBMEM 0x29 /* Graphics card frame buffer access */
-#define ASI_M_VMEUS 0x2A /* VME user 16-bit access */
-#define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */
-#define ASI_M_VMEUT 0x2C /* VME user 32-bit access */
-#define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */
-#define ASI_M_SBUS 0x2E /* Direct SBus access */
-#define ASI_M_CTL 0x2F /* Control Space (ECC and MXCC are here) */
-
-
-/* This is ROSS HyperSparc only. */
-#define ASI_M_FLUSH_IWHOLE 0x31 /* Flush entire ICACHE; wo, ss */
-
-/* Tsunami/Viking/TurboSparc i/d cache flash clear. */
-#define ASI_M_IC_FLCLEAR 0x36
-#define ASI_M_DC_FLCLEAR 0x37
-
-#define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */
-
-#define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */
-/* only available on SuperSparc I */
-/* #define ASI_M_VIKING_TMP2 0x41 */ /* Emulation temporary 2 on Viking */
-
-#define ASI_M_ACTION 0x4c /* Breakpoint Action Register (GNU/Viking) */
-
-/* V9 Architecture mandary ASIs. */
-#define ASI_N 0x04 /* Nucleus */
-#define ASI_NL 0x0c /* Nucleus, little endian */
-#define ASI_AIUP 0x10 /* Primary, user */
-#define ASI_AIUS 0x11 /* Secondary, user */
-#define ASI_AIUPL 0x18 /* Primary, user, little endian */
-#define ASI_AIUSL 0x19 /* Secondary, user, little endian */
-#define ASI_P 0x80 /* Primary, implicit */
-#define ASI_S 0x81 /* Secondary, implicit */
-#define ASI_PNF 0x82 /* Primary, no fault */
-#define ASI_SNF 0x83 /* Secondary, no fault */
-#define ASI_PL 0x88 /* Primary, implicit, l-endian */
-#define ASI_SL 0x89 /* Secondary, implicit, l-endian */
-#define ASI_PNFL 0x8a /* Primary, no fault, l-endian */
-#define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
-
-/* SpitFire and later extended ASIs. The "(III)" marker designates
- * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates
- * Chip Multi Threading specific ASIs. "(NG)" designates Niagara specific
- * ASIs, "(4V)" designates SUN4V specific ASIs.
- */
-#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */
-#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
-#define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */
-#define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */
-#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/
-#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
-#define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/
-#define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */
-#define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */
-#define ASI_MMU 0x21 /* (4V) MMU Context Registers */
-#define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
- * secondary, user
- */
-#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */
-#define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */
-#define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */
-#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */
-#define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */
-#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
-#define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */
-#define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */
-#define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */
-#define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */
-#define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */
-#define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */
-#define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */
-#define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */
-#define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */
-#define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */
-#define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */
-#define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */
-#define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */
-#define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */
-#define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */
-#define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */
-#define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */
-#define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */
-#define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */
-#define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */
-#define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */
-#define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */
-#define ASI_LSU_CONTROL 0x45 /* Load-store control unit */
-#define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */
-#define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */
-#define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/
-#define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */
-#define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */
-#define ASI_UPA_CONFIG 0x4a /* UPA config space */
-#define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */
-#define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */
-#define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */
-#define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */
-#define ASI_AFSR 0x4c /* Async fault status register */
-#define ASI_AFAR 0x4d /* Async fault address register */
-#define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */
-#define ASI_IMMU 0x50 /* Insn-MMU main register space */
-#define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */
-#define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */
-#define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */
-#define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */
-#define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */
-#define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */
-#define ASI_DMMU 0x58 /* Data-MMU main register space */
-#define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */
-#define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */
-#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */
-#define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */
-#define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */
-#define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */
-#define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */
-#define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */
-#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */
-#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */
-#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */
-#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */
-#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */
-#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */
-#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */
-#define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */
-#define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/
-#define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */
-#define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */
-#define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */
-#define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */
-#define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */
-#define ASI_EC_W 0x76 /* E-cache diag write access */
-#define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */
-#define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */
-#define ASI_INTR_W 0x77 /* IRQ vector dispatch write */
-#define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */
-#define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */
-#define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/
-#define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/
-#define ASI_EC_R 0x7e /* E-cache diag read access */
-#define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */
-#define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */
-#define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */
-#define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/
-#define ASI_INTR_R 0x7f /* IRQ vector dispatch read */
-#define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */
-#define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */
-#define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
-#define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */
-#define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */
-#define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */
-#define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */
-#define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */
-#define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */
-#define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */
-#define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */
-#define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */
-#define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */
-#define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */
-#define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */
-#define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */
-#define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */
-#define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */
-#define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/
-#define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */
-#define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/
-#define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */
-#define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */
-#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load,
- * primary, implicit
- */
-#define ASI_BLK_P 0xf0 /* Primary, blk ld/st */
-#define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */
-#define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */
-#define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */
-
-#endif /* _SPARC_ASI_H */
+++ /dev/null
-/* asmmacro.h: Assembler macros.
- *
- * Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu)
- */
-
-#ifndef _SPARC_ASMMACRO_H
-#define _SPARC_ASMMACRO_H
-
-#include <asm/btfixup.h>
-#include <asm/asi.h>
-
-#define GET_PROCESSOR4M_ID(reg) \
- rd %tbr, %reg; \
- srl %reg, 12, %reg; \
- and %reg, 3, %reg;
-
-#define GET_PROCESSOR4D_ID(reg) \
- lda [%g0] ASI_M_VIKING_TMP1, %reg;
-
-/* All trap entry points _must_ begin with this macro or else you
- * lose. It makes sure the kernel has a proper window so that
- * c-code can be called.
- */
-#define SAVE_ALL_HEAD \
- sethi %hi(trap_setup), %l4; \
- jmpl %l4 + %lo(trap_setup), %l6;
-#define SAVE_ALL \
- SAVE_ALL_HEAD \
- nop;
-
-/* All traps low-level code here must end with this macro. */
-#define RESTORE_ALL b ret_trap_entry; clr %l6;
-
-/* sun4 probably wants half word accesses to ASI_SEGMAP, while sun4c+
- likes byte accesses. These are to avoid ifdef mania. */
-
-#ifdef CONFIG_SUN4
-#define lduXa lduha
-#define stXa stha
-#else
-#define lduXa lduba
-#define stXa stba
-#endif
-
-#endif /* !(_SPARC_ASMMACRO_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_ATOMIC_H
-#define ___ASM_SPARC_ATOMIC_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/atomic_64.h>
-#else
-#include <asm-sparc/atomic_32.h>
-#endif
-#endif
+++ /dev/null
-/* atomic.h: These still suck, but the I-cache hit rate is higher.
- *
- * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
- * Copyright (C) 2000 Anton Blanchard (anton@linuxcare.com.au)
- * Copyright (C) 2007 Kyle McMartin (kyle@parisc-linux.org)
- *
- * Additions by Keith M Wesolowski (wesolows@foobazco.org) based
- * on asm-parisc/atomic.h Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>.
- */
-
-#ifndef __ARCH_SPARC_ATOMIC__
-#define __ARCH_SPARC_ATOMIC__
-
-#include <linux/types.h>
-
-typedef struct { volatile int counter; } atomic_t;
-
-#ifdef __KERNEL__
-
-#define ATOMIC_INIT(i) { (i) }
-
-extern int __atomic_add_return(int, atomic_t *);
-extern int atomic_cmpxchg(atomic_t *, int, int);
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-extern int atomic_add_unless(atomic_t *, int, int);
-extern void atomic_set(atomic_t *, int);
-
-#define atomic_read(v) ((v)->counter)
-
-#define atomic_add(i, v) ((void)__atomic_add_return( (int)(i), (v)))
-#define atomic_sub(i, v) ((void)__atomic_add_return(-(int)(i), (v)))
-#define atomic_inc(v) ((void)__atomic_add_return( 1, (v)))
-#define atomic_dec(v) ((void)__atomic_add_return( -1, (v)))
-
-#define atomic_add_return(i, v) (__atomic_add_return( (int)(i), (v)))
-#define atomic_sub_return(i, v) (__atomic_add_return(-(int)(i), (v)))
-#define atomic_inc_return(v) (__atomic_add_return( 1, (v)))
-#define atomic_dec_return(v) (__atomic_add_return( -1, (v)))
-
-#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
-#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
-
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-/* This is the old 24-bit implementation. It's still used internally
- * by some sparc-specific code, notably the semaphore implementation.
- */
-typedef struct { volatile int counter; } atomic24_t;
-
-#ifndef CONFIG_SMP
-
-#define ATOMIC24_INIT(i) { (i) }
-#define atomic24_read(v) ((v)->counter)
-#define atomic24_set(v, i) (((v)->counter) = i)
-
-#else
-/* We do the bulk of the actual work out of line in two common
- * routines in assembler, see arch/sparc/lib/atomic.S for the
- * "fun" details.
- *
- * For SMP the trick is you embed the spin lock byte within
- * the word, use the low byte so signedness is easily retained
- * via a quick arithmetic shift. It looks like this:
- *
- * ----------------------------------------
- * | signed 24-bit counter value | lock | atomic_t
- * ----------------------------------------
- * 31 8 7 0
- */
-
-#define ATOMIC24_INIT(i) { ((i) << 8) }
-
-static inline int atomic24_read(const atomic24_t *v)
-{
- int ret = v->counter;
-
- while(ret & 0xff)
- ret = v->counter;
-
- return ret >> 8;
-}
-
-#define atomic24_set(v, i) (((v)->counter) = ((i) << 8))
-#endif
-
-static inline int __atomic24_add(int i, atomic24_t *v)
-{
- register volatile int *ptr asm("g1");
- register int increment asm("g2");
- register int tmp1 asm("g3");
- register int tmp2 asm("g4");
- register int tmp3 asm("g7");
-
- ptr = &v->counter;
- increment = i;
-
- __asm__ __volatile__(
- "mov %%o7, %%g4\n\t"
- "call ___atomic24_add\n\t"
- " add %%o7, 8, %%o7\n"
- : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
- : "0" (increment), "r" (ptr)
- : "memory", "cc");
-
- return increment;
-}
-
-static inline int __atomic24_sub(int i, atomic24_t *v)
-{
- register volatile int *ptr asm("g1");
- register int increment asm("g2");
- register int tmp1 asm("g3");
- register int tmp2 asm("g4");
- register int tmp3 asm("g7");
-
- ptr = &v->counter;
- increment = i;
-
- __asm__ __volatile__(
- "mov %%o7, %%g4\n\t"
- "call ___atomic24_sub\n\t"
- " add %%o7, 8, %%o7\n"
- : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
- : "0" (increment), "r" (ptr)
- : "memory", "cc");
-
- return increment;
-}
-
-#define atomic24_add(i, v) ((void)__atomic24_add((i), (v)))
-#define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v)))
-
-#define atomic24_dec_return(v) __atomic24_sub(1, (v))
-#define atomic24_inc_return(v) __atomic24_add(1, (v))
-
-#define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0)
-#define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0)
-
-#define atomic24_inc(v) ((void)__atomic24_add(1, (v)))
-#define atomic24_dec(v) ((void)__atomic24_sub(1, (v)))
-
-#define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0)
-
-/* Atomic operations are already serializing */
-#define smp_mb__before_atomic_dec() barrier()
-#define smp_mb__after_atomic_dec() barrier()
-#define smp_mb__before_atomic_inc() barrier()
-#define smp_mb__after_atomic_inc() barrier()
-
-#endif /* !(__KERNEL__) */
-
-#include <asm-generic/atomic.h>
-#endif /* !(__ARCH_SPARC_ATOMIC__) */
+++ /dev/null
-/* atomic.h: Thankfully the V9 is at least reasonable for this
- * stuff.
- *
- * Copyright (C) 1996, 1997, 2000 David S. Miller (davem@redhat.com)
- */
-
-#ifndef __ARCH_SPARC64_ATOMIC__
-#define __ARCH_SPARC64_ATOMIC__
-
-#include <linux/types.h>
-#include <asm/system.h>
-
-typedef struct { volatile int counter; } atomic_t;
-typedef struct { volatile __s64 counter; } atomic64_t;
-
-#define ATOMIC_INIT(i) { (i) }
-#define ATOMIC64_INIT(i) { (i) }
-
-#define atomic_read(v) ((v)->counter)
-#define atomic64_read(v) ((v)->counter)
-
-#define atomic_set(v, i) (((v)->counter) = i)
-#define atomic64_set(v, i) (((v)->counter) = i)
-
-extern void atomic_add(int, atomic_t *);
-extern void atomic64_add(int, atomic64_t *);
-extern void atomic_sub(int, atomic_t *);
-extern void atomic64_sub(int, atomic64_t *);
-
-extern int atomic_add_ret(int, atomic_t *);
-extern int atomic64_add_ret(int, atomic64_t *);
-extern int atomic_sub_ret(int, atomic_t *);
-extern int atomic64_sub_ret(int, atomic64_t *);
-
-#define atomic_dec_return(v) atomic_sub_ret(1, v)
-#define atomic64_dec_return(v) atomic64_sub_ret(1, v)
-
-#define atomic_inc_return(v) atomic_add_ret(1, v)
-#define atomic64_inc_return(v) atomic64_add_ret(1, v)
-
-#define atomic_sub_return(i, v) atomic_sub_ret(i, v)
-#define atomic64_sub_return(i, v) atomic64_sub_ret(i, v)
-
-#define atomic_add_return(i, v) atomic_add_ret(i, v)
-#define atomic64_add_return(i, v) atomic64_add_ret(i, v)
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
-
-#define atomic_sub_and_test(i, v) (atomic_sub_ret(i, v) == 0)
-#define atomic64_sub_and_test(i, v) (atomic64_sub_ret(i, v) == 0)
-
-#define atomic_dec_and_test(v) (atomic_sub_ret(1, v) == 0)
-#define atomic64_dec_and_test(v) (atomic64_sub_ret(1, v) == 0)
-
-#define atomic_inc(v) atomic_add(1, v)
-#define atomic64_inc(v) atomic64_add(1, v)
-
-#define atomic_dec(v) atomic_sub(1, v)
-#define atomic64_dec(v) atomic64_sub(1, v)
-
-#define atomic_add_negative(i, v) (atomic_add_ret(i, v) < 0)
-#define atomic64_add_negative(i, v) (atomic64_add_ret(i, v) < 0)
-
-#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-
-static inline int atomic_add_unless(atomic_t *v, int a, int u)
-{
- int c, old;
- c = atomic_read(v);
- for (;;) {
- if (unlikely(c == (u)))
- break;
- old = atomic_cmpxchg((v), c, c + (a));
- if (likely(old == c))
- break;
- c = old;
- }
- return c != (u);
-}
-
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-#define atomic64_cmpxchg(v, o, n) \
- ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
-#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
-
-static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
-{
- long c, old;
- c = atomic64_read(v);
- for (;;) {
- if (unlikely(c == (u)))
- break;
- old = atomic64_cmpxchg((v), c, c + (a));
- if (likely(old == c))
- break;
- c = old;
- }
- return c != (u);
-}
-
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
-
-/* Atomic operations are already serializing */
-#ifdef CONFIG_SMP
-#define smp_mb__before_atomic_dec() membar_storeload_loadload();
-#define smp_mb__after_atomic_dec() membar_storeload_storestore();
-#define smp_mb__before_atomic_inc() membar_storeload_loadload();
-#define smp_mb__after_atomic_inc() membar_storeload_storestore();
-#else
-#define smp_mb__before_atomic_dec() barrier()
-#define smp_mb__after_atomic_dec() barrier()
-#define smp_mb__before_atomic_inc() barrier()
-#define smp_mb__after_atomic_inc() barrier()
-#endif
-
-#include <asm-generic/atomic.h>
-#endif /* !(__ARCH_SPARC64_ATOMIC__) */
+++ /dev/null
-#ifndef ___ASM_SPARC_AUXIO_H
-#define ___ASM_SPARC_AUXIO_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/auxio_64.h>
-#else
-#include <asm-sparc/auxio_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * auxio.h: Definitions and code for the Auxiliary I/O register.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-#ifndef _SPARC_AUXIO_H
-#define _SPARC_AUXIO_H
-
-#include <asm/system.h>
-#include <asm/vaddrs.h>
-
-/* This register is an unsigned char in IO space. It does two things.
- * First, it is used to control the front panel LED light on machines
- * that have it (good for testing entry points to trap handlers and irq's)
- * Secondly, it controls various floppy drive parameters.
- */
-#define AUXIO_ORMEIN 0xf0 /* All writes must set these bits. */
-#define AUXIO_ORMEIN4M 0xc0 /* sun4m - All writes must set these bits. */
-#define AUXIO_FLPY_DENS 0x20 /* Floppy density, high if set. Read only. */
-#define AUXIO_FLPY_DCHG 0x10 /* A disk change occurred. Read only. */
-#define AUXIO_EDGE_ON 0x10 /* sun4m - On means Jumper block is in. */
-#define AUXIO_FLPY_DSEL 0x08 /* Drive select/start-motor. Write only. */
-#define AUXIO_LINK_TEST 0x08 /* sun4m - On means TPE Carrier detect. */
-
-/* Set the following to one, then zero, after doing a pseudo DMA transfer. */
-#define AUXIO_FLPY_TCNT 0x04 /* Floppy terminal count. Write only. */
-
-/* Set the following to zero to eject the floppy. */
-#define AUXIO_FLPY_EJCT 0x02 /* Eject floppy disk. Write only. */
-#define AUXIO_LED 0x01 /* On if set, off if unset. Read/Write */
-
-#ifndef __ASSEMBLY__
-
-/*
- * NOTE: these routines are implementation dependent--
- * understand the hardware you are querying!
- */
-extern void set_auxio(unsigned char bits_on, unsigned char bits_off);
-extern unsigned char get_auxio(void); /* .../asm-sparc/floppy.h */
-
-/*
- * The following routines are provided for driver-compatibility
- * with sparc64 (primarily sunlance.c)
- */
-
-#define AUXIO_LTE_ON 1
-#define AUXIO_LTE_OFF 0
-
-/* auxio_set_lte - Set Link Test Enable (TPE Link Detect)
- *
- * on - AUXIO_LTE_ON or AUXIO_LTE_OFF
- */
-#define auxio_set_lte(on) \
-do { \
- if(on) { \
- set_auxio(AUXIO_LINK_TEST, 0); \
- } else { \
- set_auxio(0, AUXIO_LINK_TEST); \
- } \
-} while (0)
-
-#define AUXIO_LED_ON 1
-#define AUXIO_LED_OFF 0
-
-/* auxio_set_led - Set system front panel LED
- *
- * on - AUXIO_LED_ON or AUXIO_LED_OFF
- */
-#define auxio_set_led(on) \
-do { \
- if(on) { \
- set_auxio(AUXIO_LED, 0); \
- } else { \
- set_auxio(0, AUXIO_LED); \
- } \
-} while (0)
-
-#endif /* !(__ASSEMBLY__) */
-
-
-/* AUXIO2 (Power Off Control) */
-extern __volatile__ unsigned char * auxio_power_register;
-
-#define AUXIO_POWER_DETECT_FAILURE 32
-#define AUXIO_POWER_CLEAR_FAILURE 2
-#define AUXIO_POWER_OFF 1
-
-
-#endif /* !(_SPARC_AUXIO_H) */
+++ /dev/null
-/*
- * auxio.h: Definitions and code for the Auxiliary I/O registers.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- *
- * Refactoring for unified NCR/PCIO support 2002 Eric Brower (ebrower@usa.net)
- */
-#ifndef _SPARC64_AUXIO_H
-#define _SPARC64_AUXIO_H
-
-/* AUXIO implementations:
- * sbus-based NCR89C105 "Slavio"
- * LED/Floppy (AUX1) register
- * Power (AUX2) register
- *
- * ebus-based auxio on PCIO
- * LED Auxio Register
- * Power Auxio Register
- *
- * Register definitions from NCR _NCR89C105 Chip Specification_
- *
- * SLAVIO AUX1 @ 0x1900000
- * -------------------------------------------------
- * | (R) | (R) | D | (R) | E | M | T | L |
- * -------------------------------------------------
- * (R) - bit 7:6,4 are reserved and should be masked in s/w
- * D - Floppy Density Sense (1=high density) R/O
- * E - Link Test Enable, directly reflected on AT&T 7213 LTE pin
- * M - Monitor/Mouse Mux, directly reflected on MON_MSE_MUX pin
- * T - Terminal Count: sends TC pulse to 82077 floppy controller
- * L - System LED on front panel (0=off, 1=on)
- */
-#define AUXIO_AUX1_MASK 0xc0 /* Mask bits */
-#define AUXIO_AUX1_FDENS 0x20 /* Floppy Density Sense */
-#define AUXIO_AUX1_LTE 0x08 /* Link Test Enable */
-#define AUXIO_AUX1_MMUX 0x04 /* Monitor/Mouse Mux */
-#define AUXIO_AUX1_FTCNT 0x02 /* Terminal Count, */
-#define AUXIO_AUX1_LED 0x01 /* System LED */
-
-/* SLAVIO AUX2 @ 0x1910000
- * -------------------------------------------------
- * | (R) | (R) | D | (R) | (R) | (R) | C | F |
- * -------------------------------------------------
- * (R) - bits 7:6,4:2 are reserved and should be masked in s/w
- * D - Power Failure Detect (1=power fail)
- * C - Clear Power Failure Detect Int (1=clear)
- * F - Power Off (1=power off)
- */
-#define AUXIO_AUX2_MASK 0xdc /* Mask Bits */
-#define AUXIO_AUX2_PFAILDET 0x20 /* Power Fail Detect */
-#define AUXIO_AUX2_PFAILCLR 0x02 /* Clear Pwr Fail Det Intr */
-#define AUXIO_AUX2_PWR_OFF 0x01 /* Power Off */
-
-/* Register definitions from Sun Microsystems _PCIO_ p/n 802-7837
- *
- * PCIO LED Auxio @ 0x726000
- * -------------------------------------------------
- * | 31:1 Unused | LED |
- * -------------------------------------------------
- * Bits 31:1 unused
- * LED - System LED on front panel (0=off, 1=on)
- */
-#define AUXIO_PCIO_LED 0x01 /* System LED */
-
-/* PCIO Power Auxio @ 0x724000
- * -------------------------------------------------
- * | 31:2 Unused | CPO | SPO |
- * -------------------------------------------------
- * Bits 31:2 unused
- * CPO - Courtesy Power Off (1=off)
- * SPO - System Power Off (1=off)
- */
-#define AUXIO_PCIO_CPWR_OFF 0x02 /* Courtesy Power Off */
-#define AUXIO_PCIO_SPWR_OFF 0x01 /* System Power Off */
-
-#ifndef __ASSEMBLY__
-
-extern void __iomem *auxio_register;
-
-#define AUXIO_LTE_ON 1
-#define AUXIO_LTE_OFF 0
-
-/* auxio_set_lte - Set Link Test Enable (TPE Link Detect)
- *
- * on - AUXIO_LTE_ON or AUXIO_LTE_OFF
- */
-extern void auxio_set_lte(int on);
-
-#define AUXIO_LED_ON 1
-#define AUXIO_LED_OFF 0
-
-/* auxio_set_led - Set system front panel LED
- *
- * on - AUXIO_LED_ON or AUXIO_LED_OFF
- */
-extern void auxio_set_led(int on);
-
-#endif /* ifndef __ASSEMBLY__ */
-
-#endif /* !(_SPARC64_AUXIO_H) */
+++ /dev/null
-#ifndef __ASMSPARC_AUXVEC_H
-#define __ASMSPARC_AUXVEC_H
-
-#endif /* !(__ASMSPARC_AUXVEC_H) */
+++ /dev/null
-#ifndef _SPARC64_BACKOFF_H
-#define _SPARC64_BACKOFF_H
-
-#define BACKOFF_LIMIT (4 * 1024)
-
-#ifdef CONFIG_SMP
-
-#define BACKOFF_SETUP(reg) \
- mov 1, reg
-
-#define BACKOFF_SPIN(reg, tmp, label) \
- mov reg, tmp; \
-88: brnz,pt tmp, 88b; \
- sub tmp, 1, tmp; \
- set BACKOFF_LIMIT, tmp; \
- cmp reg, tmp; \
- bg,pn %xcc, label; \
- nop; \
- ba,pt %xcc, label; \
- sllx reg, 1, reg;
-
-#else
-
-#define BACKOFF_SETUP(reg)
-#define BACKOFF_SPIN(reg, tmp, label) \
- ba,pt %xcc, label; \
- nop;
-
-#endif
-
-#endif /* _SPARC64_BACKOFF_H */
+++ /dev/null
-/*
- * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
- * systems.
- *
- * Copyright (C) 2000 David S. Miller (davem@redhat.com)
- */
-
-#ifndef _SPARC64_BBC_H
-#define _SPARC64_BBC_H
-
-/* Register sizes are indicated by "B" (Byte, 1-byte),
- * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
- * "Q" (Quad, 8 bytes) inside brackets.
- */
-
-#define BBC_AID 0x00 /* [B] Agent ID */
-#define BBC_DEVP 0x01 /* [B] Device Present */
-#define BBC_ARB 0x02 /* [B] Arbitration */
-#define BBC_QUIESCE 0x03 /* [B] Quiesce */
-#define BBC_WDACTION 0x04 /* [B] Watchdog Action */
-#define BBC_SPG 0x06 /* [B] Soft POR Gen */
-#define BBC_SXG 0x07 /* [B] Soft XIR Gen */
-#define BBC_PSRC 0x08 /* [W] POR Source */
-#define BBC_XSRC 0x0c /* [B] XIR Source */
-#define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/
-#define BBC_ES_CTRL 0x0e /* [H] Energy Star Control */
-#define BBC_ES_ACT 0x10 /* [W] E* Assert Change Time */
-#define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
-#define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
-#define BBC_ES_ABT 0x16 /* [H] E* Assert Bypass Time */
-#define BBC_ES_PST 0x18 /* [W] E* PLL Settle Time */
-#define BBC_ES_FSL 0x1c /* [W] E* Frequency Switch Latency*/
-#define BBC_EBUST 0x20 /* [Q] EBUS Timing */
-#define BBC_JTAG_CMD 0x28 /* [W] JTAG+ Command */
-#define BBC_JTAG_CTRL 0x2c /* [B] JTAG+ Control */
-#define BBC_I2C_SEL 0x2d /* [B] I2C Selection */
-#define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
-#define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
-#define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
-#define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
-#define BBC_KBD_BEEP 0x32 /* [B] Keyboard Beep */
-#define BBC_KBD_BCNT 0x34 /* [W] Keyboard Beep Counter */
-
-#define BBC_REGS_SIZE 0x40
-
-/* There is a 2K scratch ram area at offset 0x80000 but I doubt
- * we will use it for anything.
- */
-
-/* Agent ID register. This register shows the Safari Agent ID
- * for the processors. The value returned depends upon which
- * cpu is reading the register.
- */
-#define BBC_AID_ID 0x07 /* Safari ID */
-#define BBC_AID_RESV 0xf8 /* Reserved */
-
-/* Device Present register. One can determine which cpus are actually
- * present in the machine by interrogating this register.
- */
-#define BBC_DEVP_CPU0 0x01 /* Processor 0 present */
-#define BBC_DEVP_CPU1 0x02 /* Processor 1 present */
-#define BBC_DEVP_CPU2 0x04 /* Processor 2 present */
-#define BBC_DEVP_CPU3 0x08 /* Processor 3 present */
-#define BBC_DEVP_RESV 0xf0 /* Reserved */
-
-/* Arbitration register. This register is used to block access to
- * the BBC from a particular cpu.
- */
-#define BBC_ARB_CPU0 0x01 /* Enable cpu 0 BBC arbitratrion */
-#define BBC_ARB_CPU1 0x02 /* Enable cpu 1 BBC arbitratrion */
-#define BBC_ARB_CPU2 0x04 /* Enable cpu 2 BBC arbitratrion */
-#define BBC_ARB_CPU3 0x08 /* Enable cpu 3 BBC arbitratrion */
-#define BBC_ARB_RESV 0xf0 /* Reserved */
-
-/* Quiesce register. Bus and BBC segments for cpus can be disabled
- * with this register, ie. for hot plugging.
- */
-#define BBC_QUIESCE_S02 0x01 /* Quiesce Safari segment for cpu 0 and 2 */
-#define BBC_QUIESCE_S13 0x02 /* Quiesce Safari segment for cpu 1 and 3 */
-#define BBC_QUIESCE_B02 0x04 /* Quiesce BBC segment for cpu 0 and 2 */
-#define BBC_QUIESCE_B13 0x08 /* Quiesce BBC segment for cpu 1 and 3 */
-#define BBC_QUIESCE_FD0 0x10 /* Disable Fatal_Error[0] reporting */
-#define BBC_QUIESCE_FD1 0x20 /* Disable Fatal_Error[1] reporting */
-#define BBC_QUIESCE_FD2 0x40 /* Disable Fatal_Error[2] reporting */
-#define BBC_QUIESCE_FD3 0x80 /* Disable Fatal_Error[3] reporting */
-
-/* Watchdog Action register. When the watchdog device timer expires
- * a line is enabled to the BBC. The action BBC takes when this line
- * is asserted can be controlled by this regiser.
- */
-#define BBC_WDACTION_RST 0x01 /* When set, watchdog causes system reset.
- * When clear, BBC ignores watchdog signal.
- */
-#define BBC_WDACTION_RESV 0xfe /* Reserved */
-
-/* Soft_POR_GEN register. The POR (Power On Reset) signal may be asserted
- * for specific processors or all processors via this register.
- */
-#define BBC_SPG_CPU0 0x01 /* Assert POR for processor 0 */
-#define BBC_SPG_CPU1 0x02 /* Assert POR for processor 1 */
-#define BBC_SPG_CPU2 0x04 /* Assert POR for processor 2 */
-#define BBC_SPG_CPU3 0x08 /* Assert POR for processor 3 */
-#define BBC_SPG_CPUALL 0x10 /* Reset all processors and reset
- * the entire system.
- */
-#define BBC_SPG_RESV 0xe0 /* Reserved */
-
-/* Soft_XIR_GEN register. The XIR (eXternally Initiated Reset) signal
- * may be asserted to specific processors via this register.
- */
-#define BBC_SXG_CPU0 0x01 /* Assert XIR for processor 0 */
-#define BBC_SXG_CPU1 0x02 /* Assert XIR for processor 1 */
-#define BBC_SXG_CPU2 0x04 /* Assert XIR for processor 2 */
-#define BBC_SXG_CPU3 0x08 /* Assert XIR for processor 3 */
-#define BBC_SXG_RESV 0xf0 /* Reserved */
-
-/* POR Source register. One may identify the cause of the most recent
- * reset by reading this register.
- */
-#define BBC_PSRC_SPG0 0x0001 /* CPU 0 reset via BBC_SPG register */
-#define BBC_PSRC_SPG1 0x0002 /* CPU 1 reset via BBC_SPG register */
-#define BBC_PSRC_SPG2 0x0004 /* CPU 2 reset via BBC_SPG register */
-#define BBC_PSRC_SPG3 0x0008 /* CPU 3 reset via BBC_SPG register */
-#define BBC_PSRC_SPGSYS 0x0010 /* System reset via BBC_SPG register */
-#define BBC_PSRC_JTAG 0x0020 /* System reset via JTAG+ */
-#define BBC_PSRC_BUTTON 0x0040 /* System reset via push-button dongle */
-#define BBC_PSRC_PWRUP 0x0080 /* System reset via power-up */
-#define BBC_PSRC_FE0 0x0100 /* CPU 0 reported Fatal_Error */
-#define BBC_PSRC_FE1 0x0200 /* CPU 1 reported Fatal_Error */
-#define BBC_PSRC_FE2 0x0400 /* CPU 2 reported Fatal_Error */
-#define BBC_PSRC_FE3 0x0800 /* CPU 3 reported Fatal_Error */
-#define BBC_PSRC_FE4 0x1000 /* Schizo reported Fatal_Error */
-#define BBC_PSRC_FE5 0x2000 /* Safari device 5 reported Fatal_Error */
-#define BBC_PSRC_FE6 0x4000 /* CPMS reported Fatal_Error */
-#define BBC_PSRC_SYNTH 0x8000 /* System reset when on-board clock synthesizers
- * were updated.
- */
-#define BBC_PSRC_WDT 0x10000 /* System reset via Super I/O watchdog */
-#define BBC_PSRC_RSC 0x20000 /* System reset via RSC remote monitoring
- * device
- */
-
-/* XIR Source register. The source of an XIR event sent to a processor may
- * be determined via this register.
- */
-#define BBC_XSRC_SXG0 0x01 /* CPU 0 received XIR via Soft_XIR_GEN reg */
-#define BBC_XSRC_SXG1 0x02 /* CPU 1 received XIR via Soft_XIR_GEN reg */
-#define BBC_XSRC_SXG2 0x04 /* CPU 2 received XIR via Soft_XIR_GEN reg */
-#define BBC_XSRC_SXG3 0x08 /* CPU 3 received XIR via Soft_XIR_GEN reg */
-#define BBC_XSRC_JTAG 0x10 /* All CPUs received XIR via JTAG+ */
-#define BBC_XSRC_W_OR_B 0x20 /* All CPUs received XIR either because:
- * a) Super I/O watchdog fired, or
- * b) XIR push button was activated
- */
-#define BBC_XSRC_RESV 0xc0 /* Reserved */
-
-/* Clock Synthesizers Control register. This register provides the big-bang
- * programming interface to the two clock synthesizers of the machine.
- */
-#define BBC_CSC_SLOAD 0x01 /* Directly connected to S_LOAD pins */
-#define BBC_CSC_SDATA 0x02 /* Directly connected to S_DATA pins */
-#define BBC_CSC_SCLOCK 0x04 /* Directly connected to S_CLOCK pins */
-#define BBC_CSC_RESV 0x78 /* Reserved */
-#define BBC_CSC_RST 0x80 /* Generate system reset when S_LOAD==1 */
-
-/* Energy Star Control register. This register is used to generate the
- * clock frequency change trigger to the main system devices (Schizo and
- * the processors). The transition occurs when bits in this register
- * go from 0 to 1, only one bit must be set at once else no action
- * occurs. Basically the sequence of events is:
- * a) Choose new frequency: full, 1/2 or 1/32
- * b) Program this desired frequency into the cpus and Schizo.
- * c) Set the same value in this register.
- * d) 16 system clocks later, clear this register.
- */
-#define BBC_ES_CTRL_1_1 0x01 /* Full frequency */
-#define BBC_ES_CTRL_1_2 0x02 /* 1/2 frequency */
-#define BBC_ES_CTRL_1_32 0x20 /* 1/32 frequency */
-#define BBC_ES_RESV 0xdc /* Reserved */
-
-/* Energy Star Assert Change Time register. This determines the number
- * of BBC clock cycles (which is half the system frequency) between
- * the detection of FREEZE_ACK being asserted and the assertion of
- * the CLK_CHANGE_L[2:0] signals.
- */
-#define BBC_ES_ACT_VAL 0xff
-
-/* Energy Star Assert Bypass Time register. This determines the number
- * of BBC clock cycles (which is half the system frequency) between
- * the assertion of the CLK_CHANGE_L[2:0] signals and the assertion of
- * the ESTAR_PLL_BYPASS signal.
- */
-#define BBC_ES_ABT_VAL 0xffff
-
-/* Energy Star PLL Settle Time register. This determines the number of
- * BBC clock cycles (which is half the system frequency) between the
- * de-assertion of CLK_CHANGE_L[2:0] and the de-assertion of the FREEZE_L
- * signal.
- */
-#define BBC_ES_PST_VAL 0xffffffff
-
-/* Energy Star Frequency Switch Latency register. This is the number of
- * BBC clocks between the de-assertion of CLK_CHANGE_L[2:0] and the first
- * edge of the Safari clock at the new frequency.
- */
-#define BBC_ES_FSL_VAL 0xffffffff
-
-/* Keyboard Beep control register. This is a simple enabler for the audio
- * beep sound.
- */
-#define BBC_KBD_BEEP_ENABLE 0x01 /* Enable beep */
-#define BBC_KBD_BEEP_RESV 0xfe /* Reserved */
-
-/* Keyboard Beep Counter register. There is a free-running counter inside
- * the BBC which runs at half the system clock. The bit set in this register
- * determines when the audio sound is generated. So for example if bit
- * 10 is set, the audio beep will oscillate at 1/(2**12). The keyboard beep
- * generator automatically selects a different bit to use if the system clock
- * is changed via Energy Star.
- */
-#define BBC_KBD_BCNT_BITS 0x0007fc00
-#define BBC_KBC_BCNT_RESV 0xfff803ff
-
-#endif /* _SPARC64_BBC_H */
-
+++ /dev/null
-/*
- * bitext.h: Bit string operations on the sparc, specific to architecture.
- *
- * Copyright 2002 Pete Zaitcev <zaitcev@yahoo.com>
- */
-
-#ifndef _SPARC_BITEXT_H
-#define _SPARC_BITEXT_H
-
-#include <linux/spinlock.h>
-
-struct bit_map {
- spinlock_t lock;
- unsigned long *map;
- int size;
- int used;
- int last_off;
- int last_size;
- int first_free;
- int num_colors;
-};
-
-extern int bit_map_string_get(struct bit_map *t, int len, int align);
-extern void bit_map_clear(struct bit_map *t, int offset, int len);
-extern void bit_map_init(struct bit_map *t, unsigned long *map, int size);
-
-#endif /* defined(_SPARC_BITEXT_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_BITOPS_H
-#define ___ASM_SPARC_BITOPS_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/bitops_64.h>
-#else
-#include <asm-sparc/bitops_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * bitops.h: Bit string operations on the Sparc.
- *
- * Copyright 1995 David S. Miller (davem@caip.rutgers.edu)
- * Copyright 1996 Eddie C. Dost (ecd@skynet.be)
- * Copyright 2001 Anton Blanchard (anton@samba.org)
- */
-
-#ifndef _SPARC_BITOPS_H
-#define _SPARC_BITOPS_H
-
-#include <linux/compiler.h>
-#include <asm/byteorder.h>
-
-#ifdef __KERNEL__
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-extern unsigned long ___set_bit(unsigned long *addr, unsigned long mask);
-extern unsigned long ___clear_bit(unsigned long *addr, unsigned long mask);
-extern unsigned long ___change_bit(unsigned long *addr, unsigned long mask);
-
-/*
- * Set bit 'nr' in 32-bit quantity at address 'addr' where bit '0'
- * is in the highest of the four bytes and bit '31' is the high bit
- * within the first byte. Sparc is BIG-Endian. Unless noted otherwise
- * all bit-ops return 0 if bit was previously clear and != 0 otherwise.
- */
-static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
-{
- unsigned long *ADDR, mask;
-
- ADDR = ((unsigned long *) addr) + (nr >> 5);
- mask = 1 << (nr & 31);
-
- return ___set_bit(ADDR, mask) != 0;
-}
-
-static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
-{
- unsigned long *ADDR, mask;
-
- ADDR = ((unsigned long *) addr) + (nr >> 5);
- mask = 1 << (nr & 31);
-
- (void) ___set_bit(ADDR, mask);
-}
-
-static inline int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
-{
- unsigned long *ADDR, mask;
-
- ADDR = ((unsigned long *) addr) + (nr >> 5);
- mask = 1 << (nr & 31);
-
- return ___clear_bit(ADDR, mask) != 0;
-}
-
-static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
-{
- unsigned long *ADDR, mask;
-
- ADDR = ((unsigned long *) addr) + (nr >> 5);
- mask = 1 << (nr & 31);
-
- (void) ___clear_bit(ADDR, mask);
-}
-
-static inline int test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
-{
- unsigned long *ADDR, mask;
-
- ADDR = ((unsigned long *) addr) + (nr >> 5);
- mask = 1 << (nr & 31);
-
- return ___change_bit(ADDR, mask) != 0;
-}
-
-static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
-{
- unsigned long *ADDR, mask;
-
- ADDR = ((unsigned long *) addr) + (nr >> 5);
- mask = 1 << (nr & 31);
-
- (void) ___change_bit(ADDR, mask);
-}
-
-#include <asm-generic/bitops/non-atomic.h>
-
-#define smp_mb__before_clear_bit() do { } while(0)
-#define smp_mb__after_clear_bit() do { } while(0)
-
-#include <asm-generic/bitops/ffz.h>
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/lock.h>
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/ext2-non-atomic.h>
-#include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/minix.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* defined(_SPARC_BITOPS_H) */
+++ /dev/null
-/*
- * bitops.h: Bit string operations on the V9.
- *
- * Copyright 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC64_BITOPS_H
-#define _SPARC64_BITOPS_H
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <linux/compiler.h>
-#include <asm/byteorder.h>
-
-extern int test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
-extern int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
-extern int test_and_change_bit(unsigned long nr, volatile unsigned long *addr);
-extern void set_bit(unsigned long nr, volatile unsigned long *addr);
-extern void clear_bit(unsigned long nr, volatile unsigned long *addr);
-extern void change_bit(unsigned long nr, volatile unsigned long *addr);
-
-#include <asm-generic/bitops/non-atomic.h>
-
-#ifdef CONFIG_SMP
-#define smp_mb__before_clear_bit() membar_storeload_loadload()
-#define smp_mb__after_clear_bit() membar_storeload_storestore()
-#else
-#define smp_mb__before_clear_bit() barrier()
-#define smp_mb__after_clear_bit() barrier()
-#endif
-
-#include <asm-generic/bitops/ffz.h>
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-
-#ifdef __KERNEL__
-
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/ffs.h>
-
-/*
- * hweightN: returns the hamming weight (i.e. the number
- * of bits set) of a N-bit word
- */
-
-#ifdef ULTRA_HAS_POPULATION_COUNT
-
-static inline unsigned int hweight64(unsigned long w)
-{
- unsigned int res;
-
- __asm__ ("popc %1,%0" : "=r" (res) : "r" (w));
- return res;
-}
-
-static inline unsigned int hweight32(unsigned int w)
-{
- unsigned int res;
-
- __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffffffff));
- return res;
-}
-
-static inline unsigned int hweight16(unsigned int w)
-{
- unsigned int res;
-
- __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffff));
- return res;
-}
-
-static inline unsigned int hweight8(unsigned int w)
-{
- unsigned int res;
-
- __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xff));
- return res;
-}
-
-#else
-
-#include <asm-generic/bitops/hweight.h>
-
-#endif
-#include <asm-generic/bitops/lock.h>
-#endif /* __KERNEL__ */
-
-#include <asm-generic/bitops/find.h>
-
-#ifdef __KERNEL__
-
-#include <asm-generic/bitops/ext2-non-atomic.h>
-
-#define ext2_set_bit_atomic(lock,nr,addr) \
- test_and_set_bit((nr) ^ 0x38,(unsigned long *)(addr))
-#define ext2_clear_bit_atomic(lock,nr,addr) \
- test_and_clear_bit((nr) ^ 0x38,(unsigned long *)(addr))
-
-#include <asm-generic/bitops/minix.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* defined(_SPARC64_BITOPS_H) */
+++ /dev/null
-#ifndef _SPARC_BPP_H
-#define _SPARC_BPP_H
-
-/*
- * Copyright (c) 1995 Picture Elements
- * Stephen Williams
- * Gus Baldauf
- *
- * Linux/SPARC port by Peter Zaitcev.
- * Integration into SPARC tree by Tom Dyas.
- */
-
-#include <linux/ioctl.h>
-
-/*
- * This is a driver that supports IEEE Std 1284-1994 communications
- * with compliant or compatible devices. It will use whatever features
- * the device supports, prefering those that are typically faster.
- *
- * When the device is opened, it is left in COMPATIBILITY mode, and
- * writes work like any printer device. The driver only attempt to
- * negotiate 1284 modes when needed so that plugs can be pulled,
- * switch boxes switched, etc., without disrupting things. It will
- * also leave the device in compatibility mode when closed.
- */
-
-
-
-/*
- * This driver also supplies ioctls to manually manipulate the
- * pins. This is great for testing devices, or writing code to deal
- * with bizzarro-mode of the ACME Special TurboThingy Plus.
- *
- * NOTE: These ioctl currently do not interact well with
- * read/write. Caveat emptor.
- *
- * PUT_PINS allows us to assign the sense of all the pins, including
- * the data pins if being driven by the host. The GET_PINS returns the
- * pins that the peripheral drives, including data if appropriate.
- */
-
-# define BPP_PUT_PINS _IOW('B', 1, int)
-# define BPP_GET_PINS _IOR('B', 2, char) /* that's bogus - should've been _IO */
-# define BPP_PUT_DATA _IOW('B', 3, int)
-# define BPP_GET_DATA _IOR('B', 4, char) /* ditto */
-
-/*
- * Set the data bus to input mode. Disengage the data bin driver and
- * be prepared to read values from the peripheral. If the arg is 0,
- * then revert the bus to output mode.
- */
-# define BPP_SET_INPUT _IOW('B', 5, int)
-
-/*
- * These bits apply to the PUT operation...
- */
-# define BPP_PP_nStrobe 0x0001
-# define BPP_PP_nAutoFd 0x0002
-# define BPP_PP_nInit 0x0004
-# define BPP_PP_nSelectIn 0x0008
-
-/*
- * These apply to the GET operation, which also reads the current value
- * of the previously put values. A bit mask of these will be returned
- * as a bit mask in the return code of the ioctl().
- */
-# define BPP_GP_nAck 0x0100
-# define BPP_GP_Busy 0x0200
-# define BPP_GP_PError 0x0400
-# define BPP_GP_Select 0x0800
-# define BPP_GP_nFault 0x1000
-
-#endif
+++ /dev/null
-/*
- * asm-sparc/btfixup.h: Macros for boot time linking.
- *
- * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-
-#ifndef _SPARC_BTFIXUP_H
-#define _SPARC_BTFIXUP_H
-
-#include <linux/init.h>
-
-#ifndef __ASSEMBLY__
-
-#ifdef MODULE
-extern unsigned int ___illegal_use_of_BTFIXUP_SIMM13_in_module(void);
-extern unsigned int ___illegal_use_of_BTFIXUP_SETHI_in_module(void);
-extern unsigned int ___illegal_use_of_BTFIXUP_HALF_in_module(void);
-extern unsigned int ___illegal_use_of_BTFIXUP_INT_in_module(void);
-
-#define BTFIXUP_SIMM13(__name) ___illegal_use_of_BTFIXUP_SIMM13_in_module()
-#define BTFIXUP_HALF(__name) ___illegal_use_of_BTFIXUP_HALF_in_module()
-#define BTFIXUP_SETHI(__name) ___illegal_use_of_BTFIXUP_SETHI_in_module()
-#define BTFIXUP_INT(__name) ___illegal_use_of_BTFIXUP_INT_in_module()
-#define BTFIXUP_BLACKBOX(__name) ___illegal_use_of_BTFIXUP_BLACKBOX_in_module
-
-#else
-
-#define BTFIXUP_SIMM13(__name) ___sf_##__name()
-#define BTFIXUP_HALF(__name) ___af_##__name()
-#define BTFIXUP_SETHI(__name) ___hf_##__name()
-#define BTFIXUP_INT(__name) ((unsigned int)&___i_##__name)
-/* This must be written in assembly and present in a sethi */
-#define BTFIXUP_BLACKBOX(__name) ___b_##__name
-#endif /* MODULE */
-
-/* Fixup call xx */
-
-#define BTFIXUPDEF_CALL(__type, __name, __args...) \
- extern __type ___f_##__name(__args); \
- extern unsigned ___fs_##__name[3];
-#define BTFIXUPDEF_CALL_CONST(__type, __name, __args...) \
- extern __type ___f_##__name(__args) __attribute_const__; \
- extern unsigned ___fs_##__name[3];
-#define BTFIXUP_CALL(__name) ___f_##__name
-
-#define BTFIXUPDEF_BLACKBOX(__name) \
- extern unsigned ___bs_##__name[2];
-
-/* Put bottom 13bits into some register variable */
-
-#define BTFIXUPDEF_SIMM13(__name) \
- static inline unsigned int ___sf_##__name(void) __attribute_const__; \
- extern unsigned ___ss_##__name[2]; \
- static inline unsigned int ___sf_##__name(void) { \
- unsigned int ret; \
- __asm__ ("or %%g0, ___s_" #__name ", %0" : "=r"(ret)); \
- return ret; \
- }
-#define BTFIXUPDEF_SIMM13_INIT(__name,__val) \
- static inline unsigned int ___sf_##__name(void) __attribute_const__; \
- extern unsigned ___ss_##__name[2]; \
- static inline unsigned int ___sf_##__name(void) { \
- unsigned int ret; \
- __asm__ ("or %%g0, ___s_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
- return ret; \
- }
-
-/* Put either bottom 13 bits, or upper 22 bits into some register variable
- * (depending on the value, this will lead into sethi FIX, reg; or
- * mov FIX, reg; )
- */
-
-#define BTFIXUPDEF_HALF(__name) \
- static inline unsigned int ___af_##__name(void) __attribute_const__; \
- extern unsigned ___as_##__name[2]; \
- static inline unsigned int ___af_##__name(void) { \
- unsigned int ret; \
- __asm__ ("or %%g0, ___a_" #__name ", %0" : "=r"(ret)); \
- return ret; \
- }
-#define BTFIXUPDEF_HALF_INIT(__name,__val) \
- static inline unsigned int ___af_##__name(void) __attribute_const__; \
- extern unsigned ___as_##__name[2]; \
- static inline unsigned int ___af_##__name(void) { \
- unsigned int ret; \
- __asm__ ("or %%g0, ___a_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
- return ret; \
- }
-
-/* Put upper 22 bits into some register variable */
-
-#define BTFIXUPDEF_SETHI(__name) \
- static inline unsigned int ___hf_##__name(void) __attribute_const__; \
- extern unsigned ___hs_##__name[2]; \
- static inline unsigned int ___hf_##__name(void) { \
- unsigned int ret; \
- __asm__ ("sethi %%hi(___h_" #__name "), %0" : "=r"(ret)); \
- return ret; \
- }
-#define BTFIXUPDEF_SETHI_INIT(__name,__val) \
- static inline unsigned int ___hf_##__name(void) __attribute_const__; \
- extern unsigned ___hs_##__name[2]; \
- static inline unsigned int ___hf_##__name(void) { \
- unsigned int ret; \
- __asm__ ("sethi %%hi(___h_" #__name "__btset_" #__val "), %0" : \
- "=r"(ret)); \
- return ret; \
- }
-
-/* Put a full 32bit integer into some register variable */
-
-#define BTFIXUPDEF_INT(__name) \
- extern unsigned char ___i_##__name; \
- extern unsigned ___is_##__name[2];
-
-#define BTFIXUPCALL_NORM 0x00000000 /* Always call */
-#define BTFIXUPCALL_NOP 0x01000000 /* Possibly optimize to nop */
-#define BTFIXUPCALL_RETINT(i) (0x90102000|((i) & 0x1fff)) /* Possibly optimize to mov i, %o0 */
-#define BTFIXUPCALL_ORINT(i) (0x90122000|((i) & 0x1fff)) /* Possibly optimize to or %o0, i, %o0 */
-#define BTFIXUPCALL_RETO0 0x01000000 /* Return first parameter, actually a nop */
-#define BTFIXUPCALL_ANDNINT(i) (0x902a2000|((i) & 0x1fff)) /* Possibly optimize to andn %o0, i, %o0 */
-#define BTFIXUPCALL_SWAPO0O1 0xd27a0000 /* Possibly optimize to swap [%o0],%o1 */
-#define BTFIXUPCALL_SWAPO0G0 0xc07a0000 /* Possibly optimize to swap [%o0],%g0 */
-#define BTFIXUPCALL_SWAPG1G2 0xc4784000 /* Possibly optimize to swap [%g1],%g2 */
-#define BTFIXUPCALL_STG0O0 0xc0220000 /* Possibly optimize to st %g0,[%o0] */
-#define BTFIXUPCALL_STO1O0 0xd2220000 /* Possibly optimize to st %o1,[%o0] */
-
-#define BTFIXUPSET_CALL(__name, __addr, __insn) \
- do { \
- ___fs_##__name[0] |= 1; \
- ___fs_##__name[1] = (unsigned long)__addr; \
- ___fs_##__name[2] = __insn; \
- } while (0)
-
-#define BTFIXUPSET_BLACKBOX(__name, __func) \
- do { \
- ___bs_##__name[0] |= 1; \
- ___bs_##__name[1] = (unsigned long)__func; \
- } while (0)
-
-#define BTFIXUPCOPY_CALL(__name, __from) \
- do { \
- ___fs_##__name[0] |= 1; \
- ___fs_##__name[1] = ___fs_##__from[1]; \
- ___fs_##__name[2] = ___fs_##__from[2]; \
- } while (0)
-
-#define BTFIXUPSET_SIMM13(__name, __val) \
- do { \
- ___ss_##__name[0] |= 1; \
- ___ss_##__name[1] = (unsigned)__val; \
- } while (0)
-
-#define BTFIXUPCOPY_SIMM13(__name, __from) \
- do { \
- ___ss_##__name[0] |= 1; \
- ___ss_##__name[1] = ___ss_##__from[1]; \
- } while (0)
-
-#define BTFIXUPSET_HALF(__name, __val) \
- do { \
- ___as_##__name[0] |= 1; \
- ___as_##__name[1] = (unsigned)__val; \
- } while (0)
-
-#define BTFIXUPCOPY_HALF(__name, __from) \
- do { \
- ___as_##__name[0] |= 1; \
- ___as_##__name[1] = ___as_##__from[1]; \
- } while (0)
-
-#define BTFIXUPSET_SETHI(__name, __val) \
- do { \
- ___hs_##__name[0] |= 1; \
- ___hs_##__name[1] = (unsigned)__val; \
- } while (0)
-
-#define BTFIXUPCOPY_SETHI(__name, __from) \
- do { \
- ___hs_##__name[0] |= 1; \
- ___hs_##__name[1] = ___hs_##__from[1]; \
- } while (0)
-
-#define BTFIXUPSET_INT(__name, __val) \
- do { \
- ___is_##__name[0] |= 1; \
- ___is_##__name[1] = (unsigned)__val; \
- } while (0)
-
-#define BTFIXUPCOPY_INT(__name, __from) \
- do { \
- ___is_##__name[0] |= 1; \
- ___is_##__name[1] = ___is_##__from[1]; \
- } while (0)
-
-#define BTFIXUPVAL_CALL(__name) \
- ((unsigned long)___fs_##__name[1])
-
-extern void btfixup(void);
-
-#else /* __ASSEMBLY__ */
-
-#define BTFIXUP_SETHI(__name) %hi(___h_ ## __name)
-#define BTFIXUP_SETHI_INIT(__name,__val) %hi(___h_ ## __name ## __btset_ ## __val)
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* !(_SPARC_BTFIXUP_H) */
+++ /dev/null
-#ifndef _SPARC_BUG_H
-#define _SPARC_BUG_H
-
-#ifdef CONFIG_BUG
-#include <linux/compiler.h>
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-extern void do_BUG(const char *file, int line);
-#define BUG() do { \
- do_BUG(__FILE__, __LINE__); \
- __builtin_trap(); \
-} while (0)
-#else
-#define BUG() __builtin_trap()
-#endif
-
-#define HAVE_ARCH_BUG
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
+++ /dev/null
-/* include/asm-sparc/bugs.h: Sparc probes for various bugs.
- *
- * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
- */
-
-#ifdef CONFIG_SPARC32
-#include <asm/cpudata.h>
-#endif
-
-#ifdef CONFIG_SPARC64
-#include <asm/sstate.h>
-#endif
-
-extern unsigned long loops_per_jiffy;
-
-static void __init check_bugs(void)
-{
-#if defined(CONFIG_SPARC32) && !defined(CONFIG_SMP)
- cpu_data(0).udelay_val = loops_per_jiffy;
-#endif
-#ifdef CONFIG_SPARC64
- sstate_running();
-#endif
-}
+++ /dev/null
-#ifndef _SPARC_BYTEORDER_H
-#define _SPARC_BYTEORDER_H
-
-#include <asm/types.h>
-#include <asm/asi.h>
-
-#ifdef __GNUC__
-
-#ifdef CONFIG_SPARC32
-#define __SWAB_64_THRU_32__
-#endif
-
-#ifdef CONFIG_SPARC64
-
-static inline __u16 ___arch__swab16p(const __u16 *addr)
-{
- __u16 ret;
-
- __asm__ __volatile__ ("lduha [%1] %2, %0"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PL));
- return ret;
-}
-
-static inline __u32 ___arch__swab32p(const __u32 *addr)
-{
- __u32 ret;
-
- __asm__ __volatile__ ("lduwa [%1] %2, %0"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PL));
- return ret;
-}
-
-static inline __u64 ___arch__swab64p(const __u64 *addr)
-{
- __u64 ret;
-
- __asm__ __volatile__ ("ldxa [%1] %2, %0"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PL));
- return ret;
-}
-
-#define __arch__swab16p(x) ___arch__swab16p(x)
-#define __arch__swab32p(x) ___arch__swab32p(x)
-#define __arch__swab64p(x) ___arch__swab64p(x)
-
-#endif /* CONFIG_SPARC64 */
-
-#define __BYTEORDER_HAS_U64__
-
-#endif
-
-#include <linux/byteorder/big_endian.h>
-
-#endif /* _SPARC_BYTEORDER_H */
+++ /dev/null
-/* cache.h: Cache specific code for the Sparc. These include flushing
- * and direct tag/data line access.
- *
- * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
- */
-
-#ifndef _SPARC_CACHE_H
-#define _SPARC_CACHE_H
-
-#define L1_CACHE_SHIFT 5
-#define L1_CACHE_BYTES 32
-#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
-
-#ifdef CONFIG_SPARC32
-#define SMP_CACHE_BYTES_SHIFT 5
-#else
-#define SMP_CACHE_BYTES_SHIFT 6
-#endif
-
-#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
-
-#define __read_mostly __attribute__((__section__(".data.read_mostly")))
-
-#ifdef CONFIG_SPARC32
-#include <asm/asi.h>
-
-/* Direct access to the instruction cache is provided through and
- * alternate address space. The IDC bit must be off in the ICCR on
- * HyperSparcs for these accesses to work. The code below does not do
- * any checking, the caller must do so. These routines are for
- * diagnostics only, but could end up being useful. Use with care.
- * Also, you are asking for trouble if you execute these in one of the
- * three instructions following a %asr/%psr access or modification.
- */
-
-/* First, cache-tag access. */
-static inline unsigned int get_icache_tag(int setnum, int tagnum)
-{
- unsigned int vaddr, retval;
-
- vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
- __asm__ __volatile__("lda [%1] %2, %0\n\t" :
- "=r" (retval) :
- "r" (vaddr), "i" (ASI_M_TXTC_TAG));
- return retval;
-}
-
-static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
-{
- unsigned int vaddr;
-
- vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
- __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
- "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
- "memory");
-}
-
-/* Second cache-data access. The data is returned two-32bit quantities
- * at a time.
- */
-static inline void get_icache_data(int setnum, int tagnum, int subblock,
- unsigned int *data)
-{
- unsigned int value1, value2, vaddr;
-
- vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
- ((subblock&0x3) << 3);
- __asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
- "or %%g0, %%g2, %0\n\t"
- "or %%g0, %%g3, %1\n\t" :
- "=r" (value1), "=r" (value2) :
- "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
- "g2", "g3");
- data[0] = value1; data[1] = value2;
-}
-
-static inline void put_icache_data(int setnum, int tagnum, int subblock,
- unsigned int *data)
-{
- unsigned int value1, value2, vaddr;
-
- vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
- ((subblock&0x3) << 3);
- value1 = data[0]; value2 = data[1];
- __asm__ __volatile__("or %%g0, %0, %%g2\n\t"
- "or %%g0, %1, %%g3\n\t"
- "stda %%g2, [%2] %3\n\t" : :
- "r" (value1), "r" (value2),
- "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
- "g2", "g3", "memory" /* no joke */);
-}
-
-/* Different types of flushes with the ICACHE. Some of the flushes
- * affect both the ICACHE and the external cache. Others only clear
- * the ICACHE entries on the cpu itself. V8's (most) allow
- * granularity of flushes on the packet (element in line), whole line,
- * and entire cache (ie. all lines) level. The ICACHE only flushes are
- * ROSS HyperSparc specific and are in ross.h
- */
-
-/* Flushes which clear out both the on-chip and external caches */
-static inline void flush_ei_page(unsigned int addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
- "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
- "memory");
-}
-
-static inline void flush_ei_seg(unsigned int addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
- "r" (addr), "i" (ASI_M_FLUSH_SEG) :
- "memory");
-}
-
-static inline void flush_ei_region(unsigned int addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
- "r" (addr), "i" (ASI_M_FLUSH_REGION) :
- "memory");
-}
-
-static inline void flush_ei_ctx(unsigned int addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
- "r" (addr), "i" (ASI_M_FLUSH_CTX) :
- "memory");
-}
-
-static inline void flush_ei_user(unsigned int addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
- "r" (addr), "i" (ASI_M_FLUSH_USER) :
- "memory");
-}
-#endif /* CONFIG_SPARC32 */
-
-#endif /* !(_SPARC_CACHE_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_CACHEFLUSH_H
-#define ___ASM_SPARC_CACHEFLUSH_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/cacheflush_64.h>
-#else
-#include <asm-sparc/cacheflush_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _SPARC_CACHEFLUSH_H
-#define _SPARC_CACHEFLUSH_H
-
-#include <linux/mm.h> /* Common for other includes */
-// #include <linux/kernel.h> from pgalloc.h
-// #include <linux/sched.h> from pgalloc.h
-
-// #include <asm/page.h>
-#include <asm/btfixup.h>
-
-/*
- * Fine grained cache flushing.
- */
-#ifdef CONFIG_SMP
-
-BTFIXUPDEF_CALL(void, local_flush_cache_all, void)
-BTFIXUPDEF_CALL(void, local_flush_cache_mm, struct mm_struct *)
-BTFIXUPDEF_CALL(void, local_flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long)
-BTFIXUPDEF_CALL(void, local_flush_cache_page, struct vm_area_struct *, unsigned long)
-
-#define local_flush_cache_all() BTFIXUP_CALL(local_flush_cache_all)()
-#define local_flush_cache_mm(mm) BTFIXUP_CALL(local_flush_cache_mm)(mm)
-#define local_flush_cache_range(vma,start,end) BTFIXUP_CALL(local_flush_cache_range)(vma,start,end)
-#define local_flush_cache_page(vma,addr) BTFIXUP_CALL(local_flush_cache_page)(vma,addr)
-
-BTFIXUPDEF_CALL(void, local_flush_page_to_ram, unsigned long)
-BTFIXUPDEF_CALL(void, local_flush_sig_insns, struct mm_struct *, unsigned long)
-
-#define local_flush_page_to_ram(addr) BTFIXUP_CALL(local_flush_page_to_ram)(addr)
-#define local_flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(local_flush_sig_insns)(mm,insn_addr)
-
-extern void smp_flush_cache_all(void);
-extern void smp_flush_cache_mm(struct mm_struct *mm);
-extern void smp_flush_cache_range(struct vm_area_struct *vma,
- unsigned long start,
- unsigned long end);
-extern void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
-
-extern void smp_flush_page_to_ram(unsigned long page);
-extern void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
-
-#endif /* CONFIG_SMP */
-
-BTFIXUPDEF_CALL(void, flush_cache_all, void)
-BTFIXUPDEF_CALL(void, flush_cache_mm, struct mm_struct *)
-BTFIXUPDEF_CALL(void, flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long)
-BTFIXUPDEF_CALL(void, flush_cache_page, struct vm_area_struct *, unsigned long)
-
-#define flush_cache_all() BTFIXUP_CALL(flush_cache_all)()
-#define flush_cache_mm(mm) BTFIXUP_CALL(flush_cache_mm)(mm)
-#define flush_cache_dup_mm(mm) BTFIXUP_CALL(flush_cache_mm)(mm)
-#define flush_cache_range(vma,start,end) BTFIXUP_CALL(flush_cache_range)(vma,start,end)
-#define flush_cache_page(vma,addr,pfn) BTFIXUP_CALL(flush_cache_page)(vma,addr)
-#define flush_icache_range(start, end) do { } while (0)
-#define flush_icache_page(vma, pg) do { } while (0)
-
-#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
- do { \
- flush_cache_page(vma, vaddr, page_to_pfn(page));\
- memcpy(dst, src, len); \
- } while (0)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
- do { \
- flush_cache_page(vma, vaddr, page_to_pfn(page));\
- memcpy(dst, src, len); \
- } while (0)
-
-BTFIXUPDEF_CALL(void, __flush_page_to_ram, unsigned long)
-BTFIXUPDEF_CALL(void, flush_sig_insns, struct mm_struct *, unsigned long)
-
-#define __flush_page_to_ram(addr) BTFIXUP_CALL(__flush_page_to_ram)(addr)
-#define flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(flush_sig_insns)(mm,insn_addr)
-
-extern void sparc_flush_page_to_ram(struct page *page);
-
-#define flush_dcache_page(page) sparc_flush_page_to_ram(page)
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-
-#define flush_cache_vmap(start, end) flush_cache_all()
-#define flush_cache_vunmap(start, end) flush_cache_all()
-
-#endif /* _SPARC_CACHEFLUSH_H */
+++ /dev/null
-#ifndef _SPARC64_CACHEFLUSH_H
-#define _SPARC64_CACHEFLUSH_H
-
-#include <asm/page.h>
-
-#ifndef __ASSEMBLY__
-
-#include <linux/mm.h>
-
-/* Cache flush operations. */
-
-/* These are the same regardless of whether this is an SMP kernel or not. */
-#define flush_cache_mm(__mm) \
- do { if ((__mm) == current->mm) flushw_user(); } while(0)
-#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
-#define flush_cache_range(vma, start, end) \
- flush_cache_mm((vma)->vm_mm)
-#define flush_cache_page(vma, page, pfn) \
- flush_cache_mm((vma)->vm_mm)
-
-/*
- * On spitfire, the icache doesn't snoop local stores and we don't
- * use block commit stores (which invalidate icache lines) during
- * module load, so we need this.
- */
-extern void flush_icache_range(unsigned long start, unsigned long end);
-extern void __flush_icache_page(unsigned long);
-
-extern void __flush_dcache_page(void *addr, int flush_icache);
-extern void flush_dcache_page_impl(struct page *page);
-#ifdef CONFIG_SMP
-extern void smp_flush_dcache_page_impl(struct page *page, int cpu);
-extern void flush_dcache_page_all(struct mm_struct *mm, struct page *page);
-#else
-#define smp_flush_dcache_page_impl(page,cpu) flush_dcache_page_impl(page)
-#define flush_dcache_page_all(mm,page) flush_dcache_page_impl(page)
-#endif
-
-extern void __flush_dcache_range(unsigned long start, unsigned long end);
-extern void flush_dcache_page(struct page *page);
-
-#define flush_icache_page(vma, pg) do { } while(0)
-#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
-
-extern void flush_ptrace_access(struct vm_area_struct *, struct page *,
- unsigned long uaddr, void *kaddr,
- unsigned long len, int write);
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
- do { \
- flush_cache_page(vma, vaddr, page_to_pfn(page)); \
- memcpy(dst, src, len); \
- flush_ptrace_access(vma, page, vaddr, src, len, 0); \
- } while (0)
-
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
- do { \
- flush_cache_page(vma, vaddr, page_to_pfn(page)); \
- memcpy(dst, src, len); \
- flush_ptrace_access(vma, page, vaddr, dst, len, 1); \
- } while (0)
-
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-
-#define flush_cache_vmap(start, end) do { } while (0)
-#define flush_cache_vunmap(start, end) do { } while (0)
-
-#ifdef CONFIG_DEBUG_PAGEALLOC
-/* internal debugging function */
-void kernel_map_pages(struct page *page, int numpages, int enable);
-#endif
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _SPARC64_CACHEFLUSH_H */
+++ /dev/null
-#ifndef _SPARC64_CHAFSR_H
-#define _SPARC64_CHAFSR_H
-
-/* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
-
-/* Comments indicate which processor variants on which the bit definition
- * is valid. Codes are:
- * ch --> cheetah
- * ch+ --> cheetah plus
- * jp --> jalapeno
- */
-
-/* All bits of this register except M_SYNDROME and E_SYNDROME are
- * read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only.
- */
-
-/* Software bit set by linux trap handlers to indicate that the trap was
- * signalled at %tl >= 1.
- */
-#define CHAFSR_TL1 (1UL << 63UL) /* n/a */
-
-/* Unmapped error from system bus for prefetch queue or
- * store queue read operation
- */
-#define CHPAFSR_DTO (1UL << 59UL) /* ch+ */
-
-/* Bus error from system bus for prefetch queue or store queue
- * read operation
- */
-#define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */
-
-/* Hardware corrected E-cache Tag ECC error */
-#define CHPAFSR_THCE (1UL << 57UL) /* ch+ */
-/* System interface protocol error, hw timeout caused */
-#define JPAFSR_JETO (1UL << 57UL) /* jp */
-
-/* SW handled correctable E-cache Tag ECC error */
-#define CHPAFSR_TSCE (1UL << 56UL) /* ch+ */
-/* Parity error on system snoop results */
-#define JPAFSR_SCE (1UL << 56UL) /* jp */
-
-/* Uncorrectable E-cache Tag ECC error */
-#define CHPAFSR_TUE (1UL << 55UL) /* ch+ */
-/* System interface protocol error, illegal command detected */
-#define JPAFSR_JEIC (1UL << 55UL) /* jp */
-
-/* Uncorrectable system bus data ECC error due to prefetch
- * or store fill request
- */
-#define CHPAFSR_DUE (1UL << 54UL) /* ch+ */
-/* System interface protocol error, illegal ADTYPE detected */
-#define JPAFSR_JEIT (1UL << 54UL) /* jp */
-
-/* Multiple errors of the same type have occurred. This bit is set when
- * an uncorrectable error or a SW correctable error occurs and the status
- * bit to report that error is already set. When multiple errors of
- * different types are indicated by setting multiple status bits.
- *
- * This bit is not set if multiple HW corrected errors with the same
- * status bit occur, only uncorrectable and SW correctable ones have
- * this behavior.
- *
- * This bit is not set when multiple ECC errors happen within a single
- * 64-byte system bus transaction. Only the first ECC error in a 16-byte
- * subunit will be logged. All errors in subsequent 16-byte subunits
- * from the same 64-byte transaction are ignored.
- */
-#define CHAFSR_ME (1UL << 53UL) /* ch,ch+,jp */
-
-/* Privileged state error has occurred. This is a capture of PSTATE.PRIV
- * at the time the error is detected.
- */
-#define CHAFSR_PRIV (1UL << 52UL) /* ch,ch+,jp */
-
-/* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error
- * bits and record the most recently detected errors. Bits accumulate
- * errors that have been detected since the last write to clear the bit.
- */
-
-/* System interface protocol error. The processor asserts its' ERROR
- * pin when this event occurs and it also logs a specific cause code
- * into a JTAG scannable flop.
- */
-#define CHAFSR_PERR (1UL << 51UL) /* ch,ch+,jp */
-
-/* Internal processor error. The processor asserts its' ERROR
- * pin when this event occurs and it also logs a specific cause code
- * into a JTAG scannable flop.
- */
-#define CHAFSR_IERR (1UL << 50UL) /* ch,ch+,jp */
-
-/* System request parity error on incoming address */
-#define CHAFSR_ISAP (1UL << 49UL) /* ch,ch+,jp */
-
-/* HW Corrected system bus MTAG ECC error */
-#define CHAFSR_EMC (1UL << 48UL) /* ch,ch+ */
-/* Parity error on L2 cache tag SRAM */
-#define JPAFSR_ETP (1UL << 48UL) /* jp */
-
-/* Uncorrectable system bus MTAG ECC error */
-#define CHAFSR_EMU (1UL << 47UL) /* ch,ch+ */
-/* Out of range memory error has occurred */
-#define JPAFSR_OM (1UL << 47UL) /* jp */
-
-/* HW Corrected system bus data ECC error for read of interrupt vector */
-#define CHAFSR_IVC (1UL << 46UL) /* ch,ch+ */
-/* Error due to unsupported store */
-#define JPAFSR_UMS (1UL << 46UL) /* jp */
-
-/* Uncorrectable system bus data ECC error for read of interrupt vector */
-#define CHAFSR_IVU (1UL << 45UL) /* ch,ch+,jp */
-
-/* Unmapped error from system bus */
-#define CHAFSR_TO (1UL << 44UL) /* ch,ch+,jp */
-
-/* Bus error response from system bus */
-#define CHAFSR_BERR (1UL << 43UL) /* ch,ch+,jp */
-
-/* SW Correctable E-cache ECC error for instruction fetch or data access
- * other than block load.
- */
-#define CHAFSR_UCC (1UL << 42UL) /* ch,ch+,jp */
-
-/* Uncorrectable E-cache ECC error for instruction fetch or data access
- * other than block load.
- */
-#define CHAFSR_UCU (1UL << 41UL) /* ch,ch+,jp */
-
-/* Copyout HW Corrected ECC error */
-#define CHAFSR_CPC (1UL << 40UL) /* ch,ch+,jp */
-
-/* Copyout Uncorrectable ECC error */
-#define CHAFSR_CPU (1UL << 39UL) /* ch,ch+,jp */
-
-/* HW Corrected ECC error from E-cache for writeback */
-#define CHAFSR_WDC (1UL << 38UL) /* ch,ch+,jp */
-
-/* Uncorrectable ECC error from E-cache for writeback */
-#define CHAFSR_WDU (1UL << 37UL) /* ch,ch+,jp */
-
-/* HW Corrected ECC error from E-cache for store merge or block load */
-#define CHAFSR_EDC (1UL << 36UL) /* ch,ch+,jp */
-
-/* Uncorrectable ECC error from E-cache for store merge or block load */
-#define CHAFSR_EDU (1UL << 35UL) /* ch,ch+,jp */
-
-/* Uncorrectable system bus data ECC error for read of memory or I/O */
-#define CHAFSR_UE (1UL << 34UL) /* ch,ch+,jp */
-
-/* HW Corrected system bus data ECC error for read of memory or I/O */
-#define CHAFSR_CE (1UL << 33UL) /* ch,ch+,jp */
-
-/* Uncorrectable ECC error from remote cache/memory */
-#define JPAFSR_RUE (1UL << 32UL) /* jp */
-
-/* Correctable ECC error from remote cache/memory */
-#define JPAFSR_RCE (1UL << 31UL) /* jp */
-
-/* JBUS parity error on returned read data */
-#define JPAFSR_BP (1UL << 30UL) /* jp */
-
-/* JBUS parity error on data for writeback or block store */
-#define JPAFSR_WBP (1UL << 29UL) /* jp */
-
-/* Foreign read to DRAM incurring correctable ECC error */
-#define JPAFSR_FRC (1UL << 28UL) /* jp */
-
-/* Foreign read to DRAM incurring uncorrectable ECC error */
-#define JPAFSR_FRU (1UL << 27UL) /* jp */
-
-#define CHAFSR_ERRORS (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
- CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
- CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
- CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
- CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
-#define CHPAFSR_ERRORS (CHPAFSR_DTO | CHPAFSR_DBERR | CHPAFSR_THCE | \
- CHPAFSR_TSCE | CHPAFSR_TUE | CHPAFSR_DUE | \
- CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
- CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
- CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
- CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
- CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
-#define JPAFSR_ERRORS (JPAFSR_JETO | JPAFSR_SCE | JPAFSR_JEIC | \
- JPAFSR_JEIT | CHAFSR_PERR | CHAFSR_IERR | \
- CHAFSR_ISAP | JPAFSR_ETP | JPAFSR_OM | \
- JPAFSR_UMS | CHAFSR_IVU | CHAFSR_TO | \
- CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | \
- CHAFSR_CPC | CHAFSR_CPU | CHAFSR_WDC | \
- CHAFSR_WDU | CHAFSR_EDC | CHAFSR_EDU | \
- CHAFSR_UE | CHAFSR_CE | JPAFSR_RUE | \
- JPAFSR_RCE | JPAFSR_BP | JPAFSR_WBP | \
- JPAFSR_FRC | JPAFSR_FRU)
-
-/* Active JBUS request signal when error occurred */
-#define JPAFSR_JBREQ (0x7UL << 24UL) /* jp */
-#define JPAFSR_JBREQ_SHIFT 24UL
-
-/* L2 cache way information */
-#define JPAFSR_ETW (0x3UL << 22UL) /* jp */
-#define JPAFSR_ETW_SHIFT 22UL
-
-/* System bus MTAG ECC syndrome. This field captures the status of the
- * first occurrence of the highest-priority error according to the M_SYND
- * overwrite policy. After the AFSR sticky bit, corresponding to the error
- * for which the M_SYND is reported, is cleared, the contents of the M_SYND
- * field will be unchanged by will be unfrozen for further error capture.
- */
-#define CHAFSR_M_SYNDROME (0xfUL << 16UL) /* ch,ch+,jp */
-#define CHAFSR_M_SYNDROME_SHIFT 16UL
-
-/* Agenid Id of the foreign device causing the UE/CE errors */
-#define JPAFSR_AID (0x1fUL << 9UL) /* jp */
-#define JPAFSR_AID_SHIFT 9UL
-
-/* System bus or E-cache data ECC syndrome. This field captures the status
- * of the first occurrence of the highest-priority error according to the
- * E_SYND overwrite policy. After the AFSR sticky bit, corresponding to the
- * error for which the E_SYND is reported, is cleare, the contents of the E_SYND
- * field will be unchanged but will be unfrozen for further error capture.
- */
-#define CHAFSR_E_SYNDROME (0x1ffUL << 0UL) /* ch,ch+,jp */
-#define CHAFSR_E_SYNDROME_SHIFT 0UL
-
-/* The AFSR must be explicitly cleared by software, it is not cleared automatically
- * by a read. Writes to bits <51:33> with bits set will clear the corresponding
- * bits in the AFSR. Bits associated with disrupting traps must be cleared before
- * interrupts are re-enabled to prevent multiple traps for the same error. I.e.
- * PSTATE.IE and AFSR bits control delivery of disrupting traps.
- *
- * Since there is only one AFAR, when multiple events have been logged by the
- * bits in the AFSR, at most one of these events will have its status captured
- * in the AFAR. The highest priority of those event bits will get AFAR logging.
- * The AFAR will be unlocked and available to capture the address of another event
- * as soon as the one bit in AFSR that corresponds to the event logged in AFAR is
- * cleared. For example, if AFSR.CE is detected, then AFSR.UE (which overwrites
- * the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked
- * and ready for another event, even though AFSR.CE is still set. The same rules
- * also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR.
- */
-
-#endif /* _SPARC64_CHAFSR_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_CHECKSUM_H
-#define ___ASM_SPARC_CHECKSUM_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/checksum_64.h>
-#else
-#include <asm-sparc/checksum_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef __SPARC_CHECKSUM_H
-#define __SPARC_CHECKSUM_H
-
-/* checksum.h: IP/UDP/TCP checksum routines on the Sparc.
- *
- * Copyright(C) 1995 Linus Torvalds
- * Copyright(C) 1995 Miguel de Icaza
- * Copyright(C) 1996 David S. Miller
- * Copyright(C) 1996 Eddie C. Dost
- * Copyright(C) 1997 Jakub Jelinek
- *
- * derived from:
- * Alpha checksum c-code
- * ix86 inline assembly
- * RFC1071 Computing the Internet Checksum
- */
-
-#include <linux/in6.h>
-#include <asm/uaccess.h>
-
-/* computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-extern __wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/* the same as csum_partial, but copies from fs:src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-extern unsigned int __csum_partial_copy_sparc_generic (const unsigned char *, unsigned char *);
-
-static inline __wsum
-csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum)
-{
- register unsigned int ret asm("o0") = (unsigned int)src;
- register char *d asm("o1") = dst;
- register int l asm("g1") = len;
-
- __asm__ __volatile__ (
- "call __csum_partial_copy_sparc_generic\n\t"
- " mov %6, %%g7\n"
- : "=&r" (ret), "=&r" (d), "=&r" (l)
- : "0" (ret), "1" (d), "2" (l), "r" (sum)
- : "o2", "o3", "o4", "o5", "o7",
- "g2", "g3", "g4", "g5", "g7",
- "memory", "cc");
- return (__force __wsum)ret;
-}
-
-static inline __wsum
-csum_partial_copy_from_user(const void __user *src, void *dst, int len,
- __wsum sum, int *err)
- {
- register unsigned long ret asm("o0") = (unsigned long)src;
- register char *d asm("o1") = dst;
- register int l asm("g1") = len;
- register __wsum s asm("g7") = sum;
-
- __asm__ __volatile__ (
- ".section __ex_table,#alloc\n\t"
- ".align 4\n\t"
- ".word 1f,2\n\t"
- ".previous\n"
- "1:\n\t"
- "call __csum_partial_copy_sparc_generic\n\t"
- " st %8, [%%sp + 64]\n"
- : "=&r" (ret), "=&r" (d), "=&r" (l), "=&r" (s)
- : "0" (ret), "1" (d), "2" (l), "3" (s), "r" (err)
- : "o2", "o3", "o4", "o5", "o7", "g2", "g3", "g4", "g5",
- "cc", "memory");
- return (__force __wsum)ret;
-}
-
-static inline __wsum
-csum_partial_copy_to_user(const void *src, void __user *dst, int len,
- __wsum sum, int *err)
-{
- if (!access_ok (VERIFY_WRITE, dst, len)) {
- *err = -EFAULT;
- return sum;
- } else {
- register unsigned long ret asm("o0") = (unsigned long)src;
- register char __user *d asm("o1") = dst;
- register int l asm("g1") = len;
- register __wsum s asm("g7") = sum;
-
- __asm__ __volatile__ (
- ".section __ex_table,#alloc\n\t"
- ".align 4\n\t"
- ".word 1f,1\n\t"
- ".previous\n"
- "1:\n\t"
- "call __csum_partial_copy_sparc_generic\n\t"
- " st %8, [%%sp + 64]\n"
- : "=&r" (ret), "=&r" (d), "=&r" (l), "=&r" (s)
- : "0" (ret), "1" (d), "2" (l), "3" (s), "r" (err)
- : "o2", "o3", "o4", "o5", "o7",
- "g2", "g3", "g4", "g5",
- "cc", "memory");
- return (__force __wsum)ret;
- }
-}
-
-#define HAVE_CSUM_COPY_USER
-#define csum_and_copy_to_user csum_partial_copy_to_user
-
-/* ihl is always 5 or greater, almost always is 5, and iph is word aligned
- * the majority of the time.
- */
-static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
- __sum16 sum;
-
- /* Note: We must read %2 before we touch %0 for the first time,
- * because GCC can legitimately use the same register for
- * both operands.
- */
- __asm__ __volatile__("sub\t%2, 4, %%g4\n\t"
- "ld\t[%1 + 0x00], %0\n\t"
- "ld\t[%1 + 0x04], %%g2\n\t"
- "ld\t[%1 + 0x08], %%g3\n\t"
- "addcc\t%%g2, %0, %0\n\t"
- "addxcc\t%%g3, %0, %0\n\t"
- "ld\t[%1 + 0x0c], %%g2\n\t"
- "ld\t[%1 + 0x10], %%g3\n\t"
- "addxcc\t%%g2, %0, %0\n\t"
- "addx\t%0, %%g0, %0\n"
- "1:\taddcc\t%%g3, %0, %0\n\t"
- "add\t%1, 4, %1\n\t"
- "addxcc\t%0, %%g0, %0\n\t"
- "subcc\t%%g4, 1, %%g4\n\t"
- "be,a\t2f\n\t"
- "sll\t%0, 16, %%g2\n\t"
- "b\t1b\n\t"
- "ld\t[%1 + 0x10], %%g3\n"
- "2:\taddcc\t%0, %%g2, %%g2\n\t"
- "srl\t%%g2, 16, %0\n\t"
- "addx\t%0, %%g0, %0\n\t"
- "xnor\t%%g0, %0, %0"
- : "=r" (sum), "=&r" (iph)
- : "r" (ihl), "1" (iph)
- : "g2", "g3", "g4", "cc", "memory");
- return sum;
-}
-
-/* Fold a partial checksum without adding pseudo headers. */
-static inline __sum16 csum_fold(__wsum sum)
-{
- unsigned int tmp;
-
- __asm__ __volatile__("addcc\t%0, %1, %1\n\t"
- "srl\t%1, 16, %1\n\t"
- "addx\t%1, %%g0, %1\n\t"
- "xnor\t%%g0, %1, %0"
- : "=&r" (sum), "=r" (tmp)
- : "0" (sum), "1" ((__force u32)sum<<16)
- : "cc");
- return (__force __sum16)sum;
-}
-
-static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
- unsigned short len,
- unsigned short proto,
- __wsum sum)
-{
- __asm__ __volatile__("addcc\t%1, %0, %0\n\t"
- "addxcc\t%2, %0, %0\n\t"
- "addxcc\t%3, %0, %0\n\t"
- "addx\t%0, %%g0, %0\n\t"
- : "=r" (sum), "=r" (saddr)
- : "r" (daddr), "r" (proto + len), "0" (sum),
- "1" (saddr)
- : "cc");
- return sum;
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
- unsigned short len,
- unsigned short proto,
- __wsum sum)
-{
- return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
-}
-
-#define _HAVE_ARCH_IPV6_CSUM
-
-static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
- const struct in6_addr *daddr,
- __u32 len, unsigned short proto,
- __wsum sum)
-{
- __asm__ __volatile__ (
- "addcc %3, %4, %%g4\n\t"
- "addxcc %5, %%g4, %%g4\n\t"
- "ld [%2 + 0x0c], %%g2\n\t"
- "ld [%2 + 0x08], %%g3\n\t"
- "addxcc %%g2, %%g4, %%g4\n\t"
- "ld [%2 + 0x04], %%g2\n\t"
- "addxcc %%g3, %%g4, %%g4\n\t"
- "ld [%2 + 0x00], %%g3\n\t"
- "addxcc %%g2, %%g4, %%g4\n\t"
- "ld [%1 + 0x0c], %%g2\n\t"
- "addxcc %%g3, %%g4, %%g4\n\t"
- "ld [%1 + 0x08], %%g3\n\t"
- "addxcc %%g2, %%g4, %%g4\n\t"
- "ld [%1 + 0x04], %%g2\n\t"
- "addxcc %%g3, %%g4, %%g4\n\t"
- "ld [%1 + 0x00], %%g3\n\t"
- "addxcc %%g2, %%g4, %%g4\n\t"
- "addxcc %%g3, %%g4, %0\n\t"
- "addx 0, %0, %0\n"
- : "=&r" (sum)
- : "r" (saddr), "r" (daddr),
- "r"(htonl(len)), "r"(htonl(proto)), "r"(sum)
- : "g2", "g3", "g4", "cc");
-
- return csum_fold(sum);
-}
-
-/* this routine is used for miscellaneous IP-like checksums, mainly in icmp.c */
-static inline __sum16 ip_compute_csum(const void *buff, int len)
-{
- return csum_fold(csum_partial(buff, len, 0));
-}
-
-#endif /* !(__SPARC_CHECKSUM_H) */
+++ /dev/null
-#ifndef __SPARC64_CHECKSUM_H
-#define __SPARC64_CHECKSUM_H
-
-/* checksum.h: IP/UDP/TCP checksum routines on the V9.
- *
- * Copyright(C) 1995 Linus Torvalds
- * Copyright(C) 1995 Miguel de Icaza
- * Copyright(C) 1996 David S. Miller
- * Copyright(C) 1996 Eddie C. Dost
- * Copyright(C) 1997 Jakub Jelinek
- *
- * derived from:
- * Alpha checksum c-code
- * ix86 inline assembly
- * RFC1071 Computing the Internet Checksum
- */
-
-#include <linux/in6.h>
-#include <asm/uaccess.h>
-
-/* computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-extern __wsum csum_partial(const void * buff, int len, __wsum sum);
-
-/* the same as csum_partial, but copies from user space while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-extern __wsum csum_partial_copy_nocheck(const void *src, void *dst,
- int len, __wsum sum);
-
-extern long __csum_partial_copy_from_user(const void __user *src,
- void *dst, int len,
- __wsum sum);
-
-static inline __wsum
-csum_partial_copy_from_user(const void __user *src,
- void *dst, int len,
- __wsum sum, int *err)
-{
- long ret = __csum_partial_copy_from_user(src, dst, len, sum);
- if (ret < 0)
- *err = -EFAULT;
- return (__force __wsum) ret;
-}
-
-/*
- * Copy and checksum to user
- */
-#define HAVE_CSUM_COPY_USER
-extern long __csum_partial_copy_to_user(const void *src,
- void __user *dst, int len,
- __wsum sum);
-
-static inline __wsum
-csum_and_copy_to_user(const void *src,
- void __user *dst, int len,
- __wsum sum, int *err)
-{
- long ret = __csum_partial_copy_to_user(src, dst, len, sum);
- if (ret < 0)
- *err = -EFAULT;
- return (__force __wsum) ret;
-}
-
-/* ihl is always 5 or greater, almost always is 5, and iph is word aligned
- * the majority of the time.
- */
-extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
-
-/* Fold a partial checksum without adding pseudo headers. */
-static inline __sum16 csum_fold(__wsum sum)
-{
- unsigned int tmp;
-
- __asm__ __volatile__(
-" addcc %0, %1, %1\n"
-" srl %1, 16, %1\n"
-" addc %1, %%g0, %1\n"
-" xnor %%g0, %1, %0\n"
- : "=&r" (sum), "=r" (tmp)
- : "0" (sum), "1" ((__force u32)sum<<16)
- : "cc");
- return (__force __sum16)sum;
-}
-
-static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
- unsigned int len,
- unsigned short proto,
- __wsum sum)
-{
- __asm__ __volatile__(
-" addcc %1, %0, %0\n"
-" addccc %2, %0, %0\n"
-" addccc %3, %0, %0\n"
-" addc %0, %%g0, %0\n"
- : "=r" (sum), "=r" (saddr)
- : "r" (daddr), "r" (proto + len), "0" (sum), "1" (saddr)
- : "cc");
- return sum;
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
- unsigned short len,
- unsigned short proto,
- __wsum sum)
-{
- return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
-}
-
-#define _HAVE_ARCH_IPV6_CSUM
-
-static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
- const struct in6_addr *daddr,
- __u32 len, unsigned short proto,
- __wsum sum)
-{
- __asm__ __volatile__ (
-" addcc %3, %4, %%g7\n"
-" addccc %5, %%g7, %%g7\n"
-" lduw [%2 + 0x0c], %%g2\n"
-" lduw [%2 + 0x08], %%g3\n"
-" addccc %%g2, %%g7, %%g7\n"
-" lduw [%2 + 0x04], %%g2\n"
-" addccc %%g3, %%g7, %%g7\n"
-" lduw [%2 + 0x00], %%g3\n"
-" addccc %%g2, %%g7, %%g7\n"
-" lduw [%1 + 0x0c], %%g2\n"
-" addccc %%g3, %%g7, %%g7\n"
-" lduw [%1 + 0x08], %%g3\n"
-" addccc %%g2, %%g7, %%g7\n"
-" lduw [%1 + 0x04], %%g2\n"
-" addccc %%g3, %%g7, %%g7\n"
-" lduw [%1 + 0x00], %%g3\n"
-" addccc %%g2, %%g7, %%g7\n"
-" addccc %%g3, %%g7, %0\n"
-" addc 0, %0, %0\n"
- : "=&r" (sum)
- : "r" (saddr), "r" (daddr), "r"(htonl(len)),
- "r"(htonl(proto)), "r"(sum)
- : "g2", "g3", "g7", "cc");
-
- return csum_fold(sum);
-}
-
-/* this routine is used for miscellaneous IP-like checksums, mainly in icmp.c */
-static inline __sum16 ip_compute_csum(const void *buff, int len)
-{
- return csum_fold(csum_partial(buff, len, 0));
-}
-
-#endif /* !(__SPARC64_CHECKSUM_H) */
+++ /dev/null
-#ifndef _SPARC64_CHMCTRL_H
-#define _SPARC64_CHMCTRL_H
-
-/* Cheetah memory controller programmable registers. */
-#define CHMCTRL_TCTRL1 0x00 /* Memory Timing Control I */
-#define CHMCTRL_TCTRL2 0x08 /* Memory Timing Control II */
-#define CHMCTRL_TCTRL3 0x38 /* Memory Timing Control III */
-#define CHMCTRL_TCTRL4 0x40 /* Memory Timing Control IV */
-#define CHMCTRL_DECODE1 0x10 /* Memory Address Decode I */
-#define CHMCTRL_DECODE2 0x18 /* Memory Address Decode II */
-#define CHMCTRL_DECODE3 0x20 /* Memory Address Decode III */
-#define CHMCTRL_DECODE4 0x28 /* Memory Address Decode IV */
-#define CHMCTRL_MACTRL 0x30 /* Memory Address Control */
-
-/* Memory Timing Control I */
-#define TCTRL1_SDRAMCTL_DLY 0xf000000000000000UL
-#define TCTRL1_SDRAMCTL_DLY_SHIFT 60
-#define TCTRL1_SDRAMCLK_DLY 0x0e00000000000000UL
-#define TCTRL1_SDRAMCLK_DLY_SHIFT 57
-#define TCTRL1_R 0x0100000000000000UL
-#define TCTRL1_R_SHIFT 56
-#define TCTRL1_AUTORFR_CYCLE 0x00fe000000000000UL
-#define TCTRL1_AUTORFR_CYCLE_SHIFT 49
-#define TCTRL1_RD_WAIT 0x0001f00000000000UL
-#define TCTRL1_RD_WAIT_SHIFT 44
-#define TCTRL1_PC_CYCLE 0x00000fc000000000UL
-#define TCTRL1_PC_CYCLE_SHIFT 38
-#define TCTRL1_WR_MORE_RAS_PW 0x0000003f00000000UL
-#define TCTRL1_WR_MORE_RAS_PW_SHIFT 32
-#define TCTRL1_RD_MORE_RAW_PW 0x00000000fc000000UL
-#define TCTRL1_RD_MORE_RAS_PW_SHIFT 26
-#define TCTRL1_ACT_WR_DLY 0x0000000003f00000UL
-#define TCTRL1_ACT_WR_DLY_SHIFT 20
-#define TCTRL1_ACT_RD_DLY 0x00000000000fc000UL
-#define TCTRL1_ACT_RD_DLY_SHIFT 14
-#define TCTRL1_BANK_PRESENT 0x0000000000003000UL
-#define TCTRL1_BANK_PRESENT_SHIFT 12
-#define TCTRL1_RFR_INT 0x0000000000000ff8UL
-#define TCTRL1_RFR_INT_SHIFT 3
-#define TCTRL1_SET_MODE_REG 0x0000000000000004UL
-#define TCTRL1_SET_MODE_REG_SHIFT 2
-#define TCTRL1_RFR_ENABLE 0x0000000000000002UL
-#define TCTRL1_RFR_ENABLE_SHIFT 1
-#define TCTRL1_PRECHG_ALL 0x0000000000000001UL
-#define TCTRL1_PRECHG_ALL_SHIFT 0
-
-/* Memory Timing Control II */
-#define TCTRL2_WR_MSEL_DLY 0xfc00000000000000UL
-#define TCTRL2_WR_MSEL_DLY_SHIFT 58
-#define TCTRL2_RD_MSEL_DLY 0x03f0000000000000UL
-#define TCTRL2_RD_MSEL_DLY_SHIFT 52
-#define TCTRL2_WRDATA_THLD 0x000c000000000000UL
-#define TCTRL2_WRDATA_THLD_SHIFT 50
-#define TCTRL2_RDWR_RD_TI_DLY 0x0003f00000000000UL
-#define TCTRL2_RDWR_RD_TI_DLY_SHIFT 44
-#define TCTRL2_AUTOPRECHG_ENBL 0x0000080000000000UL
-#define TCTRL2_AUTOPRECHG_ENBL_SHIFT 43
-#define TCTRL2_RDWR_PI_MORE_DLY 0x000007c000000000UL
-#define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38
-#define TCTRL2_RDWR_1_DLY 0x0000003f00000000UL
-#define TCTRL2_RDWR_1_DLY_SHIFT 32
-#define TCTRL2_WRWR_PI_MORE_DLY 0x00000000f8000000UL
-#define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27
-#define TCTRL2_WRWR_1_DLY 0x0000000007e00000UL
-#define TCTRL2_WRWR_1_DLY_SHIFT 21
-#define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000UL
-#define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16
-#define TCTRL2_R 0x0000000000008000UL
-#define TCTRL2_R_SHIFT 15
-#define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
-#define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0
-
-/* Memory Timing Control III */
-#define TCTRL3_SDRAM_CTL_DLY 0xf000000000000000UL
-#define TCTRL3_SDRAM_CTL_DLY_SHIFT 60
-#define TCTRL3_SDRAM_CLK_DLY 0x0e00000000000000UL
-#define TCTRL3_SDRAM_CLK_DLY_SHIFT 57
-#define TCTRL3_R 0x0100000000000000UL
-#define TCTRL3_R_SHIFT 56
-#define TCTRL3_AUTO_RFR_CYCLE 0x00fe000000000000UL
-#define TCTRL3_AUTO_RFR_CYCLE_SHIFT 49
-#define TCTRL3_RD_WAIT 0x0001f00000000000UL
-#define TCTRL3_RD_WAIT_SHIFT 44
-#define TCTRL3_PC_CYCLE 0x00000fc000000000UL
-#define TCTRL3_PC_CYCLE_SHIFT 38
-#define TCTRL3_WR_MORE_RAW_PW 0x0000003f00000000UL
-#define TCTRL3_WR_MORE_RAW_PW_SHIFT 32
-#define TCTRL3_RD_MORE_RAW_PW 0x00000000fc000000UL
-#define TCTRL3_RD_MORE_RAW_PW_SHIFT 26
-#define TCTRL3_ACT_WR_DLY 0x0000000003f00000UL
-#define TCTRL3_ACT_WR_DLY_SHIFT 20
-#define TCTRL3_ACT_RD_DLY 0x00000000000fc000UL
-#define TCTRL3_ACT_RD_DLY_SHIFT 14
-#define TCTRL3_BANK_PRESENT 0x0000000000003000UL
-#define TCTRL3_BANK_PRESENT_SHIFT 12
-#define TCTRL3_RFR_INT 0x0000000000000ff8UL
-#define TCTRL3_RFR_INT_SHIFT 3
-#define TCTRL3_SET_MODE_REG 0x0000000000000004UL
-#define TCTRL3_SET_MODE_REG_SHIFT 2
-#define TCTRL3_RFR_ENABLE 0x0000000000000002UL
-#define TCTRL3_RFR_ENABLE_SHIFT 1
-#define TCTRL3_PRECHG_ALL 0x0000000000000001UL
-#define TCTRL3_PRECHG_ALL_SHIFT 0
-
-/* Memory Timing Control IV */
-#define TCTRL4_WR_MSEL_DLY 0xfc00000000000000UL
-#define TCTRL4_WR_MSEL_DLY_SHIFT 58
-#define TCTRL4_RD_MSEL_DLY 0x03f0000000000000UL
-#define TCTRL4_RD_MSEL_DLY_SHIFT 52
-#define TCTRL4_WRDATA_THLD 0x000c000000000000UL
-#define TCTRL4_WRDATA_THLD_SHIFT 50
-#define TCTRL4_RDWR_RD_RI_DLY 0x0003f00000000000UL
-#define TCTRL4_RDWR_RD_RI_DLY_SHIFT 44
-#define TCTRL4_AUTO_PRECHG_ENBL 0x0000080000000000UL
-#define TCTRL4_AUTO_PRECHG_ENBL_SHIFT 43
-#define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000UL
-#define TCTRL4_RD_WR_PI_MORE_DLY_SHIFT 38
-#define TCTRL4_RD_WR_TI_DLY 0x0000003f00000000UL
-#define TCTRL4_RD_WR_TI_DLY_SHIFT 32
-#define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000UL
-#define TCTRL4_WR_WR_PI_MORE_DLY_SHIFT 27
-#define TCTRL4_WR_WR_TI_DLY 0x0000000007e00000UL
-#define TCTRL4_WR_WR_TI_DLY_SHIFT 21
-#define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f000UL0
-#define TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT 16
-#define TCTRL4_R 0x0000000000008000UL
-#define TCTRL4_R_SHIFT 15
-#define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
-#define TCTRL4_SDRAM_MODE_REG_DATA_SHIFT 0
-
-/* All 4 memory address decoding registers have the
- * same layout.
- */
-#define MEM_DECODE_VALID 0x8000000000000000UL /* Valid */
-#define MEM_DECODE_VALID_SHIFT 63
-#define MEM_DECODE_UK 0x001ffe0000000000UL /* Upper mask */
-#define MEM_DECODE_UK_SHIFT 41
-#define MEM_DECODE_UM 0x0000001ffff00000UL /* Upper match */
-#define MEM_DECODE_UM_SHIFT 20
-#define MEM_DECODE_LK 0x000000000003c000UL /* Lower mask */
-#define MEM_DECODE_LK_SHIFT 14
-#define MEM_DECODE_LM 0x0000000000000f00UL /* Lower match */
-#define MEM_DECODE_LM_SHIFT 8
-
-#define PA_UPPER_BITS 0x000007fffc000000UL
-#define PA_UPPER_BITS_SHIFT 26
-#define PA_LOWER_BITS 0x00000000000003c0UL
-#define PA_LOWER_BITS_SHIFT 6
-
-#define MACTRL_R0 0x8000000000000000UL
-#define MACTRL_R0_SHIFT 63
-#define MACTRL_ADDR_LE_PW 0x7000000000000000UL
-#define MACTRL_ADDR_LE_PW_SHIFT 60
-#define MACTRL_CMD_PW 0x0f00000000000000UL
-#define MACTRL_CMD_PW_SHIFT 56
-#define MACTRL_HALF_MODE_WR_MSEL_DLY 0x00fc000000000000UL
-#define MACTRL_HALF_MODE_WR_MSEL_DLY_SHIFT 50
-#define MACTRL_HALF_MODE_RD_MSEL_DLY 0x0003f00000000000UL
-#define MACTRL_HALF_MODE_RD_MSEL_DLY_SHIFT 44
-#define MACTRL_HALF_MODE_SDRAM_CTL_DLY 0x00000f0000000000UL
-#define MACTRL_HALF_MODE_SDRAM_CTL_DLY_SHIFT 40
-#define MACTRL_HALF_MODE_SDRAM_CLK_DLY 0x000000e000000000UL
-#define MACTRL_HALF_MODE_SDRAM_CLK_DLY_SHIFT 37
-#define MACTRL_R1 0x0000001000000000UL
-#define MACTRL_R1_SHIFT 36
-#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000UL
-#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3_SHIFT 32
-#define MACTRL_ENC_INTLV_B3 0x00000000f8000000UL
-#define MACTRL_ENC_INTLV_B3_SHIFT 27
-#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000UL
-#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2_SHIFT 23
-#define MACTRL_ENC_INTLV_B2 0x00000000007c0000UL
-#define MACTRL_ENC_INTLV_B2_SHIFT 18
-#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000UL
-#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1_SHIFT 14
-#define MACTRL_ENC_INTLV_B1 0x0000000000003e00UL
-#define MACTRL_ENC_INTLV_B1_SHIFT 9
-#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0UL
-#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0_SHIFT 5
-#define MACTRL_ENC_INTLV_B0 0x000000000000001fUL
-#define MACTRL_ENC_INTLV_B0_SHIFT 0
-
-#endif /* _SPARC64_CHMCTRL_H */
+++ /dev/null
-/*
- * clock.h: Definitions for clock operations on the Sparc.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-#ifndef _SPARC_CLOCK_H
-#define _SPARC_CLOCK_H
-
-/* Foo for now. */
-
-#endif /* !(_SPARC_CLOCK_H) */
+++ /dev/null
-#ifndef _SPARC64_CMT_H
-#define _SPARC64_CMT_H
-
-/* cmt.h: Chip Multi-Threading register definitions
- *
- * Copyright (C) 2004 David S. Miller (davem@redhat.com)
- */
-
-/* ASI_CORE_ID - private */
-#define LP_ID 0x0000000000000010UL
-#define LP_ID_MAX 0x00000000003f0000UL
-#define LP_ID_ID 0x000000000000003fUL
-
-/* ASI_INTR_ID - private */
-#define LP_INTR_ID 0x0000000000000000UL
-#define LP_INTR_ID_ID 0x00000000000003ffUL
-
-/* ASI_CESR_ID - private */
-#define CESR_ID 0x0000000000000040UL
-#define CESR_ID_ID 0x00000000000000ffUL
-
-/* ASI_CORE_AVAILABLE - shared */
-#define LP_AVAIL 0x0000000000000000UL
-#define LP_AVAIL_1 0x0000000000000002UL
-#define LP_AVAIL_0 0x0000000000000001UL
-
-/* ASI_CORE_ENABLE_STATUS - shared */
-#define LP_ENAB_STAT 0x0000000000000010UL
-#define LP_ENAB_STAT_1 0x0000000000000002UL
-#define LP_ENAB_STAT_0 0x0000000000000001UL
-
-/* ASI_CORE_ENABLE - shared */
-#define LP_ENAB 0x0000000000000020UL
-#define LP_ENAB_1 0x0000000000000002UL
-#define LP_ENAB_0 0x0000000000000001UL
-
-/* ASI_CORE_RUNNING - shared */
-#define LP_RUNNING_RW 0x0000000000000050UL
-#define LP_RUNNING_W1S 0x0000000000000060UL
-#define LP_RUNNING_W1C 0x0000000000000068UL
-#define LP_RUNNING_1 0x0000000000000002UL
-#define LP_RUNNING_0 0x0000000000000001UL
-
-/* ASI_CORE_RUNNING_STAT - shared */
-#define LP_RUN_STAT 0x0000000000000058UL
-#define LP_RUN_STAT_1 0x0000000000000002UL
-#define LP_RUN_STAT_0 0x0000000000000001UL
-
-/* ASI_XIR_STEERING - shared */
-#define LP_XIR_STEER 0x0000000000000030UL
-#define LP_XIR_STEER_1 0x0000000000000002UL
-#define LP_XIR_STEER_0 0x0000000000000001UL
-
-/* ASI_CMT_ERROR_STEERING - shared */
-#define CMT_ER_STEER 0x0000000000000040UL
-#define CMT_ER_STEER_1 0x0000000000000002UL
-#define CMT_ER_STEER_0 0x0000000000000001UL
-
-#endif /* _SPARC64_CMT_H */
+++ /dev/null
-#ifndef _ASM_SPARC64_COMPAT_H
-#define _ASM_SPARC64_COMPAT_H
-/*
- * Architecture specific compatibility types
- */
-#include <linux/types.h>
-
-#define COMPAT_USER_HZ 100
-
-typedef u32 compat_size_t;
-typedef s32 compat_ssize_t;
-typedef s32 compat_time_t;
-typedef s32 compat_clock_t;
-typedef s32 compat_pid_t;
-typedef u16 __compat_uid_t;
-typedef u16 __compat_gid_t;
-typedef u32 __compat_uid32_t;
-typedef u32 __compat_gid32_t;
-typedef u16 compat_mode_t;
-typedef u32 compat_ino_t;
-typedef u16 compat_dev_t;
-typedef s32 compat_off_t;
-typedef s64 compat_loff_t;
-typedef s16 compat_nlink_t;
-typedef u16 compat_ipc_pid_t;
-typedef s32 compat_daddr_t;
-typedef u32 compat_caddr_t;
-typedef __kernel_fsid_t compat_fsid_t;
-typedef s32 compat_key_t;
-typedef s32 compat_timer_t;
-
-typedef s32 compat_int_t;
-typedef s32 compat_long_t;
-typedef s64 compat_s64;
-typedef u32 compat_uint_t;
-typedef u32 compat_ulong_t;
-typedef u64 compat_u64;
-
-struct compat_timespec {
- compat_time_t tv_sec;
- s32 tv_nsec;
-};
-
-struct compat_timeval {
- compat_time_t tv_sec;
- s32 tv_usec;
-};
-
-struct compat_stat {
- compat_dev_t st_dev;
- compat_ino_t st_ino;
- compat_mode_t st_mode;
- compat_nlink_t st_nlink;
- __compat_uid_t st_uid;
- __compat_gid_t st_gid;
- compat_dev_t st_rdev;
- compat_off_t st_size;
- compat_time_t st_atime;
- compat_ulong_t st_atime_nsec;
- compat_time_t st_mtime;
- compat_ulong_t st_mtime_nsec;
- compat_time_t st_ctime;
- compat_ulong_t st_ctime_nsec;
- compat_off_t st_blksize;
- compat_off_t st_blocks;
- u32 __unused4[2];
-};
-
-struct compat_stat64 {
- unsigned long long st_dev;
-
- unsigned long long st_ino;
-
- unsigned int st_mode;
- unsigned int st_nlink;
-
- unsigned int st_uid;
- unsigned int st_gid;
-
- unsigned long long st_rdev;
-
- unsigned char __pad3[8];
-
- long long st_size;
- unsigned int st_blksize;
-
- unsigned char __pad4[8];
- unsigned int st_blocks;
-
- unsigned int st_atime;
- unsigned int st_atime_nsec;
-
- unsigned int st_mtime;
- unsigned int st_mtime_nsec;
-
- unsigned int st_ctime;
- unsigned int st_ctime_nsec;
-
- unsigned int __unused4;
- unsigned int __unused5;
-};
-
-struct compat_flock {
- short l_type;
- short l_whence;
- compat_off_t l_start;
- compat_off_t l_len;
- compat_pid_t l_pid;
- short __unused;
-};
-
-#define F_GETLK64 12
-#define F_SETLK64 13
-#define F_SETLKW64 14
-
-struct compat_flock64 {
- short l_type;
- short l_whence;
- compat_loff_t l_start;
- compat_loff_t l_len;
- compat_pid_t l_pid;
- short __unused;
-};
-
-struct compat_statfs {
- int f_type;
- int f_bsize;
- int f_blocks;
- int f_bfree;
- int f_bavail;
- int f_files;
- int f_ffree;
- compat_fsid_t f_fsid;
- int f_namelen; /* SunOS ignores this field. */
- int f_frsize;
- int f_spare[5];
-};
-
-#define COMPAT_RLIM_INFINITY 0x7fffffff
-
-typedef u32 compat_old_sigset_t;
-
-#define _COMPAT_NSIG 64
-#define _COMPAT_NSIG_BPW 32
-
-typedef u32 compat_sigset_word;
-
-#define COMPAT_OFF_T_MAX 0x7fffffff
-#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
-
-/*
- * A pointer passed in from user mode. This should not
- * be used for syscall parameters, just declare them
- * as pointers because the syscall entry code will have
- * appropriately converted them already.
- */
-typedef u32 compat_uptr_t;
-
-static inline void __user *compat_ptr(compat_uptr_t uptr)
-{
- return (void __user *)(unsigned long)uptr;
-}
-
-static inline compat_uptr_t ptr_to_compat(void __user *uptr)
-{
- return (u32)(unsigned long)uptr;
-}
-
-static inline void __user *compat_alloc_user_space(long len)
-{
- struct pt_regs *regs = current_thread_info()->kregs;
- unsigned long usp = regs->u_regs[UREG_I6];
-
- if (!(test_thread_flag(TIF_32BIT)))
- usp += STACK_BIAS;
- else
- usp &= 0xffffffffUL;
-
- usp -= len;
- usp &= ~0x7UL;
-
- return (void __user *) usp;
-}
-
-struct compat_ipc64_perm {
- compat_key_t key;
- __compat_uid32_t uid;
- __compat_gid32_t gid;
- __compat_uid32_t cuid;
- __compat_gid32_t cgid;
- unsigned short __pad1;
- compat_mode_t mode;
- unsigned short __pad2;
- unsigned short seq;
- unsigned long __unused1; /* yes they really are 64bit pads */
- unsigned long __unused2;
-};
-
-struct compat_semid64_ds {
- struct compat_ipc64_perm sem_perm;
- unsigned int __pad1;
- compat_time_t sem_otime;
- unsigned int __pad2;
- compat_time_t sem_ctime;
- u32 sem_nsems;
- u32 __unused1;
- u32 __unused2;
-};
-
-struct compat_msqid64_ds {
- struct compat_ipc64_perm msg_perm;
- unsigned int __pad1;
- compat_time_t msg_stime;
- unsigned int __pad2;
- compat_time_t msg_rtime;
- unsigned int __pad3;
- compat_time_t msg_ctime;
- unsigned int msg_cbytes;
- unsigned int msg_qnum;
- unsigned int msg_qbytes;
- compat_pid_t msg_lspid;
- compat_pid_t msg_lrpid;
- unsigned int __unused1;
- unsigned int __unused2;
-};
-
-struct compat_shmid64_ds {
- struct compat_ipc64_perm shm_perm;
- unsigned int __pad1;
- compat_time_t shm_atime;
- unsigned int __pad2;
- compat_time_t shm_dtime;
- unsigned int __pad3;
- compat_time_t shm_ctime;
- compat_size_t shm_segsz;
- compat_pid_t shm_cpid;
- compat_pid_t shm_lpid;
- unsigned int shm_nattch;
- unsigned int __unused1;
- unsigned int __unused2;
-};
-
-#endif /* _ASM_SPARC64_COMPAT_H */
+++ /dev/null
-#ifndef _COMPAT_SIGNAL_H
-#define _COMPAT_SIGNAL_H
-
-#include <linux/compat.h>
-#include <asm/signal.h>
-
-#ifdef CONFIG_COMPAT
-struct __new_sigaction32 {
- unsigned sa_handler;
- unsigned int sa_flags;
- unsigned sa_restorer; /* not used by Linux/SPARC yet */
- compat_sigset_t sa_mask;
-};
-
-struct __old_sigaction32 {
- unsigned sa_handler;
- compat_old_sigset_t sa_mask;
- unsigned int sa_flags;
- unsigned sa_restorer; /* not used by Linux/SPARC yet */
-};
-
-typedef struct sigaltstack32 {
- u32 ss_sp;
- int ss_flags;
- compat_size_t ss_size;
-} stack_t32;
-#endif
-
-#endif /* !(_COMPAT_SIGNAL_H) */
+++ /dev/null
-#ifndef _SPARC_CONTREGS_H
-#define _SPARC_CONTREGS_H
-
-/* contregs.h: Addresses of registers in the ASI_CONTROL alternate address
- * space. These are for the mmu's context register, etc.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-/* 3=sun3
- 4=sun4 (as in sun4 sysmaint student book)
- c=sun4c (according to davem) */
-
-#define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
-#define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
-#define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
-#define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
-#define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
-#define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
-#define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
-#define AC_SYNC_ERR 0x60000000 /* c fault type */
-#define AC_SYNC_VA 0x60000004 /* c fault virtual address */
-#define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
-#define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */
-#define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */
-#define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */
-#define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */
-#define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */
-#define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */
-#define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/
-
-/* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */
-#define AC_M_PCR 0x0000 /* shv Processor Control Reg */
-#define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
-#define AC_M_CXR 0x0200 /* shv Context Register */
-#define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
-#define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
-#define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
-#define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
-#define AC_M_RESET 0x0700 /* hv Reset Reg */
-#define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
-#define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
-#define AC_M_IAPTP 0x1100 /* hv Instruction Access PTP */
-#define AC_M_DAPTP 0x1200 /* hv Data Access PTP */
-#define AC_M_ITR 0x1300 /* hv Index Tag Register */
-#define AC_M_TRCR 0x1400 /* hv TLB Replacement Control Reg */
-#define AC_M_SFSRX 0x1300 /* s Synch Fault Status Reg prim */
-#define AC_M_SFARX 0x1400 /* s Synch Fault Address Reg prim */
-#define AC_M_RPR1 0x1500 /* h Root Pointer Reg (entry 2) */
-#define AC_M_IAPTP1 0x1600 /* h Instruction Access PTP (entry 2) */
-#define AC_M_DAPTP1 0x1700 /* h Data Access PTP (entry 2) */
-
-#endif /* _SPARC_CONTREGS_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_CPUDATA_H
-#define ___ASM_SPARC_CPUDATA_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/cpudata_64.h>
-#else
-#include <asm-sparc/cpudata_32.h>
-#endif
-#endif
+++ /dev/null
-/* cpudata.h: Per-cpu parameters.
- *
- * Copyright (C) 2004 Keith M Wesolowski (wesolows@foobazco.org)
- *
- * Based on include/asm-sparc64/cpudata.h and Linux 2.4 smp.h
- * both (C) David S. Miller.
- */
-
-#ifndef _SPARC_CPUDATA_H
-#define _SPARC_CPUDATA_H
-
-#include <linux/percpu.h>
-
-typedef struct {
- unsigned long udelay_val;
- unsigned long clock_tick;
- unsigned int multiplier;
- unsigned int counter;
- int prom_node;
- int mid;
- int next;
-} cpuinfo_sparc;
-
-DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
-#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
-
-#endif /* _SPARC_CPUDATA_H */
+++ /dev/null
-/* cpudata.h: Per-cpu parameters.
- *
- * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
- */
-
-#ifndef _SPARC64_CPUDATA_H
-#define _SPARC64_CPUDATA_H
-
-#include <asm/hypervisor.h>
-#include <asm/asi.h>
-
-#ifndef __ASSEMBLY__
-
-#include <linux/percpu.h>
-#include <linux/threads.h>
-
-typedef struct {
- /* Dcache line 1 */
- unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
- unsigned int __pad0;
- unsigned long clock_tick; /* %tick's per second */
- unsigned long __pad;
- unsigned int __pad1;
- unsigned int __pad2;
-
- /* Dcache line 2, rarely used */
- unsigned int dcache_size;
- unsigned int dcache_line_size;
- unsigned int icache_size;
- unsigned int icache_line_size;
- unsigned int ecache_size;
- unsigned int ecache_line_size;
- int core_id;
- int proc_id;
-} cpuinfo_sparc;
-
-DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
-#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
-#define local_cpu_data() __get_cpu_var(__cpu_data)
-
-/* Trap handling code needs to get at a few critical values upon
- * trap entry and to process TSB misses. These cannot be in the
- * per_cpu() area as we really need to lock them into the TLB and
- * thus make them part of the main kernel image. As a result we
- * try to make this as small as possible.
- *
- * This is padded out and aligned to 64-bytes to avoid false sharing
- * on SMP.
- */
-
-/* If you modify the size of this structure, please update
- * TRAP_BLOCK_SZ_SHIFT below.
- */
-struct thread_info;
-struct trap_per_cpu {
-/* D-cache line 1: Basic thread information, cpu and device mondo queues */
- struct thread_info *thread;
- unsigned long pgd_paddr;
- unsigned long cpu_mondo_pa;
- unsigned long dev_mondo_pa;
-
-/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
- unsigned long resum_mondo_pa;
- unsigned long resum_kernel_buf_pa;
- unsigned long nonresum_mondo_pa;
- unsigned long nonresum_kernel_buf_pa;
-
-/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
- struct hv_fault_status fault_info;
-
-/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list. */
- unsigned long cpu_mondo_block_pa;
- unsigned long cpu_list_pa;
- unsigned long tsb_huge;
- unsigned long tsb_huge_temp;
-
-/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */
- unsigned long irq_worklist_pa;
- unsigned int cpu_mondo_qmask;
- unsigned int dev_mondo_qmask;
- unsigned int resum_qmask;
- unsigned int nonresum_qmask;
- void *hdesc;
-} __attribute__((aligned(64)));
-extern struct trap_per_cpu trap_block[NR_CPUS];
-extern void init_cur_cpu_trap(struct thread_info *);
-extern void setup_tba(void);
-extern int ncpus_probed;
-extern void __init cpu_probe(void);
-extern const struct seq_operations cpuinfo_op;
-
-extern unsigned long real_hard_smp_processor_id(void);
-
-struct cpuid_patch_entry {
- unsigned int addr;
- unsigned int cheetah_safari[4];
- unsigned int cheetah_jbus[4];
- unsigned int starfire[4];
- unsigned int sun4v[4];
-};
-extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
-
-struct sun4v_1insn_patch_entry {
- unsigned int addr;
- unsigned int insn;
-};
-extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
- __sun4v_1insn_patch_end;
-
-struct sun4v_2insn_patch_entry {
- unsigned int addr;
- unsigned int insns[2];
-};
-extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
- __sun4v_2insn_patch_end;
-
-#endif /* !(__ASSEMBLY__) */
-
-#define TRAP_PER_CPU_THREAD 0x00
-#define TRAP_PER_CPU_PGD_PADDR 0x08
-#define TRAP_PER_CPU_CPU_MONDO_PA 0x10
-#define TRAP_PER_CPU_DEV_MONDO_PA 0x18
-#define TRAP_PER_CPU_RESUM_MONDO_PA 0x20
-#define TRAP_PER_CPU_RESUM_KBUF_PA 0x28
-#define TRAP_PER_CPU_NONRESUM_MONDO_PA 0x30
-#define TRAP_PER_CPU_NONRESUM_KBUF_PA 0x38
-#define TRAP_PER_CPU_FAULT_INFO 0x40
-#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
-#define TRAP_PER_CPU_CPU_LIST_PA 0xc8
-#define TRAP_PER_CPU_TSB_HUGE 0xd0
-#define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8
-#define TRAP_PER_CPU_IRQ_WORKLIST_PA 0xe0
-#define TRAP_PER_CPU_CPU_MONDO_QMASK 0xe8
-#define TRAP_PER_CPU_DEV_MONDO_QMASK 0xec
-#define TRAP_PER_CPU_RESUM_QMASK 0xf0
-#define TRAP_PER_CPU_NONRESUM_QMASK 0xf4
-
-#define TRAP_BLOCK_SZ_SHIFT 8
-
-#include <asm/scratchpad.h>
-
-#define __GET_CPUID(REG) \
- /* Spitfire implementation (default). */ \
-661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
- srlx REG, 17, REG; \
- and REG, 0x1f, REG; \
- nop; \
- .section .cpuid_patch, "ax"; \
- /* Instruction location. */ \
- .word 661b; \
- /* Cheetah Safari implementation. */ \
- ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
- srlx REG, 17, REG; \
- and REG, 0x3ff, REG; \
- nop; \
- /* Cheetah JBUS implementation. */ \
- ldxa [%g0] ASI_JBUS_CONFIG, REG; \
- srlx REG, 17, REG; \
- and REG, 0x1f, REG; \
- nop; \
- /* Starfire implementation. */ \
- sethi %hi(0x1fff40000d0 >> 9), REG; \
- sllx REG, 9, REG; \
- or REG, 0xd0, REG; \
- lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
- /* sun4v implementation. */ \
- mov SCRATCHPAD_CPUID, REG; \
- ldxa [REG] ASI_SCRATCHPAD, REG; \
- nop; \
- nop; \
- .previous;
-
-#ifdef CONFIG_SMP
-
-#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
- __GET_CPUID(TMP) \
- sethi %hi(trap_block), DEST; \
- sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
- or DEST, %lo(trap_block), DEST; \
- add DEST, TMP, DEST; \
-
-/* Clobbers TMP, current address space PGD phys address into DEST. */
-#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
- TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
- ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
-
-/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
-#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \
- TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
- add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
-
-/* Clobbers TMP, loads DEST with current thread info pointer. */
-#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
- TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
- ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
-
-/* Given the current thread info pointer in THR, load the per-cpu
- * area base of the current processor into DEST. REG1, REG2, and REG3 are
- * clobbered.
- *
- * You absolutely cannot use DEST as a temporary in this code. The
- * reason is that traps can happen during execution, and return from
- * trap will load the fully resolved DEST per-cpu base. This can corrupt
- * the calculations done by the macro mid-stream.
- */
-#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
- lduh [THR + TI_CPU], REG1; \
- sethi %hi(__per_cpu_shift), REG3; \
- sethi %hi(__per_cpu_base), REG2; \
- ldx [REG3 + %lo(__per_cpu_shift)], REG3; \
- ldx [REG2 + %lo(__per_cpu_base)], REG2; \
- sllx REG1, REG3, REG3; \
- add REG3, REG2, DEST;
-
-#else
-
-#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
- sethi %hi(trap_block), DEST; \
- or DEST, %lo(trap_block), DEST; \
-
-/* Uniprocessor versions, we know the cpuid is zero. */
-#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
- TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
- ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
-
-/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
-#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \
- TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
- add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
-
-#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
- TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
- ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
-
-/* No per-cpu areas on uniprocessor, so no need to load DEST. */
-#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
-
-#endif /* !(CONFIG_SMP) */
-
-#endif /* _SPARC64_CPUDATA_H */
+++ /dev/null
-#ifndef __SPARC_CPUTIME_H
-#define __SPARC_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif /* __SPARC_CPUTIME_H */
+++ /dev/null
-/* include/asm-sparc/current.h
- *
- * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
- * Copyright (C) 2002 Pete Zaitcev (zaitcev@yahoo.com)
- * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
- *
- * Derived from "include/asm-s390/current.h" by
- * Martin Schwidefsky (schwidefsky@de.ibm.com)
- * Derived from "include/asm-i386/current.h"
-*/
-#ifndef _SPARC_CURRENT_H
-#define _SPARC_CURRENT_H
-
-#include <linux/thread_info.h>
-
-#ifdef CONFIG_SPARC64
-register struct task_struct *current asm("g4");
-#endif
-
-#ifdef CONFIG_SPARC32
-/* We might want to consider using %g4 like sparc64 to shave a few cycles.
- *
- * Two stage process (inline + #define) for type-checking.
- * We also obfuscate get_current() to check if anyone used that by mistake.
- */
-struct task_struct;
-static inline struct task_struct *__get_current(void)
-{
- return current_thread_info()->task;
-}
-#define current __get_current()
-#endif
-
-#endif /* !(_SPARC_CURRENT_H) */
+++ /dev/null
-/*
- * cypress.h: Cypress module specific definitions and defines.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_CYPRESS_H
-#define _SPARC_CYPRESS_H
-
-/* Cypress chips have %psr 'impl' of '0001' and 'vers' of '0001'. */
-
-/* The MMU control register fields on the Sparc Cypress 604/605 MMU's.
- *
- * ---------------------------------------------------------------
- * |implvers| MCA | MCM |MV| MID |BM| C|RSV|MR|CM|CL|CE|RSV|NF|ME|
- * ---------------------------------------------------------------
- * 31 24 23-22 21-20 19 18-15 14 13 12 11 10 9 8 7-2 1 0
- *
- * MCA: MultiChip Access -- Used for configuration of multiple
- * CY7C604/605 cache units.
- * MCM: MultiChip Mask -- Again, for multiple cache unit config.
- * MV: MultiChip Valid -- Indicates MCM and MCA have valid settings.
- * MID: ModuleID -- Unique processor ID for MBus transactions. (605 only)
- * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
- * C: Cacheable -- Indicates whether accesses are cacheable while
- * the MMU is off. 0=no 1=yes
- * MR: MemoryReflection -- Indicates whether the bus attached to the
- * MBus supports memory reflection. 0=no 1=yes (605 only)
- * CM: CacheMode -- Indicates whether the cache is operating in write
- * through or copy-back mode. 0=write-through 1=copy-back
- * CL: CacheLock -- Indicates if the entire cache is locked or not.
- * 0=not-locked 1=locked (604 only)
- * CE: CacheEnable -- Is the virtual cache on? 0=no 1=yes
- * NF: NoFault -- Do faults generate traps? 0=yes 1=no
- * ME: MmuEnable -- Is the MMU doing translations? 0=no 1=yes
- */
-
-#define CYPRESS_MCA 0x00c00000
-#define CYPRESS_MCM 0x00300000
-#define CYPRESS_MVALID 0x00080000
-#define CYPRESS_MIDMASK 0x00078000 /* Only on 605 */
-#define CYPRESS_BMODE 0x00004000
-#define CYPRESS_ACENABLE 0x00002000
-#define CYPRESS_MRFLCT 0x00000800 /* Only on 605 */
-#define CYPRESS_CMODE 0x00000400
-#define CYPRESS_CLOCK 0x00000200 /* Only on 604 */
-#define CYPRESS_CENABLE 0x00000100
-#define CYPRESS_NFAULT 0x00000002
-#define CYPRESS_MENABLE 0x00000001
-
-static inline void cypress_flush_page(unsigned long page)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
- "r" (page), "i" (ASI_M_FLUSH_PAGE));
-}
-
-static inline void cypress_flush_segment(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
- "r" (addr), "i" (ASI_M_FLUSH_SEG));
-}
-
-static inline void cypress_flush_region(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
- "r" (addr), "i" (ASI_M_FLUSH_REGION));
-}
-
-static inline void cypress_flush_context(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
- "i" (ASI_M_FLUSH_CTX));
-}
-
-/* XXX Displacement flushes for buggy chips and initial testing
- * XXX go here.
- */
-
-#endif /* !(_SPARC_CYPRESS_H) */
+++ /dev/null
-#ifndef _SPARC64_DCR_H
-#define _SPARC64_DCR_H
-
-/* UltraSparc-III/III+ Dispatch Control Register, ASR 0x12 */
-#define DCR_DPE 0x0000000000001000 /* III+: D$ Parity Error Enable */
-#define DCR_OBS 0x0000000000000fc0 /* Observability Bus Controls */
-#define DCR_BPE 0x0000000000000020 /* Branch Predict Enable */
-#define DCR_RPE 0x0000000000000010 /* Return Address Prediction Enable */
-#define DCR_SI 0x0000000000000008 /* Single Instruction Disable */
-#define DCR_IPE 0x0000000000000004 /* III+: I$ Parity Error Enable */
-#define DCR_IFPOE 0x0000000000000002 /* IRQ FP Operation Enable */
-#define DCR_MS 0x0000000000000001 /* Multi-Scalar dispatch */
-
-#endif /* _SPARC64_DCR_H */
+++ /dev/null
-#ifndef _SPARC64_DCU_H
-#define _SPARC64_DCU_H
-
-#include <linux/const.h>
-
-/* UltraSparc-III Data Cache Unit Control Register */
-#define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */
-#define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */
-#define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */
-#define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */
-#define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */
-#define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */
-#define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */
-#define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/
-#define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */
-#define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */
-#define DCU_VM _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask */
-#define DCU_PR _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */
-#define DCU_PW _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/
-#define DCU_VR _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */
-#define DCU_VW _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/
-#define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */
-#define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */
-#define DCU_DC _AC(0x0000000000000002,UL) /* Data Cache Enable */
-#define DCU_IC _AC(0x0000000000000001,UL) /* Instruction Cache Enable */
-
-#endif /* _SPARC64_DCU_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_DELAY_H
-#define ___ASM_SPARC_DELAY_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/delay_64.h>
-#else
-#include <asm-sparc/delay_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * delay.h: Linux delay routines on the Sparc.
- *
- * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu).
- */
-
-#ifndef __SPARC_DELAY_H
-#define __SPARC_DELAY_H
-
-#include <asm/cpudata.h>
-
-static inline void __delay(unsigned long loops)
-{
- __asm__ __volatile__("cmp %0, 0\n\t"
- "1: bne 1b\n\t"
- "subcc %0, 1, %0\n" :
- "=&r" (loops) :
- "0" (loops) :
- "cc");
-}
-
-/* This is too messy with inline asm on the Sparc. */
-extern void __udelay(unsigned long usecs, unsigned long lpj);
-extern void __ndelay(unsigned long nsecs, unsigned long lpj);
-
-#ifdef CONFIG_SMP
-#define __udelay_val cpu_data(smp_processor_id()).udelay_val
-#else /* SMP */
-#define __udelay_val loops_per_jiffy
-#endif /* SMP */
-#define udelay(__usecs) __udelay(__usecs, __udelay_val)
-#define ndelay(__nsecs) __ndelay(__nsecs, __udelay_val)
-
-#endif /* defined(__SPARC_DELAY_H) */
+++ /dev/null
-/* delay.h: Linux delay routines on sparc64.
- *
- * Copyright (C) 1996, 2004, 2007 David S. Miller (davem@davemloft.net).
- */
-
-#ifndef _SPARC64_DELAY_H
-#define _SPARC64_DELAY_H
-
-#ifndef __ASSEMBLY__
-
-extern void __delay(unsigned long loops);
-extern void udelay(unsigned long usecs);
-#define mdelay(n) udelay((n) * 1000)
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _SPARC64_DELAY_H */
+++ /dev/null
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#ifndef _ASM_SPARC_DEVICE_H
-#define _ASM_SPARC_DEVICE_H
-
-struct device_node;
-struct of_device;
-
-struct dev_archdata {
- void *iommu;
- void *stc;
- void *host_controller;
-
- struct device_node *prom_node;
- struct of_device *op;
-
- int numa_node;
-};
-
-#endif /* _ASM_SPARC_DEVICE_H */
+++ /dev/null
-/*
- *
- * display7seg - Driver interface for the 7-segment display
- * present on Sun Microsystems CP1400 and CP1500
- *
- * Copyright (c) 2000 Eric Brower <ebrower@usa.net>
- *
- */
-
-#ifndef __display7seg_h__
-#define __display7seg_h__
-
-#define D7S_IOC 'p'
-
-#define D7SIOCRD _IOR(D7S_IOC, 0x45, int) /* Read device state */
-#define D7SIOCWR _IOW(D7S_IOC, 0x46, int) /* Write device state */
-#define D7SIOCTM _IO (D7S_IOC, 0x47) /* Translate mode (FLIP)*/
-
-/*
- * ioctl flag definitions
- *
- * POINT - Toggle decimal point (0=absent 1=present)
- * ALARM - Toggle alarm LED (0=green 1=red)
- * FLIP - Toggle inverted mode (0=normal 1=flipped)
- * bits 0-4 - Character displayed (see definitions below)
- *
- * Display segments are defined as follows,
- * subject to D7S_FLIP register state:
- *
- * a
- * ---
- * f| |b
- * -g-
- * e| |c
- * ---
- * d
- */
-
-#define D7S_POINT (1 << 7) /* Decimal point*/
-#define D7S_ALARM (1 << 6) /* Alarm LED */
-#define D7S_FLIP (1 << 5) /* Flip display */
-
-#define D7S_0 0x00 /* Numerals 0-9 */
-#define D7S_1 0x01
-#define D7S_2 0x02
-#define D7S_3 0x03
-#define D7S_4 0x04
-#define D7S_5 0x05
-#define D7S_6 0x06
-#define D7S_7 0x07
-#define D7S_8 0x08
-#define D7S_9 0x09
-#define D7S_A 0x0A /* Letters A-F, H, L, P */
-#define D7S_B 0x0B
-#define D7S_C 0x0C
-#define D7S_D 0x0D
-#define D7S_E 0x0E
-#define D7S_F 0x0F
-#define D7S_H 0x10
-#define D7S_E2 0x11
-#define D7S_L 0x12
-#define D7S_P 0x13
-#define D7S_SEGA 0x14 /* Individual segments */
-#define D7S_SEGB 0x15
-#define D7S_SEGC 0x16
-#define D7S_SEGD 0x17
-#define D7S_SEGE 0x18
-#define D7S_SEGF 0x19
-#define D7S_SEGG 0x1A
-#define D7S_SEGABFG 0x1B /* Segment groupings */
-#define D7S_SEGCDEG 0x1C
-#define D7S_SEGBCEF 0x1D
-#define D7S_SEGADG 0x1E
-#define D7S_BLANK 0x1F /* Clear all segments */
-
-#define D7S_MIN_VAL 0x0
-#define D7S_MAX_VAL 0x1F
-
-#endif /* ifndef __display7seg_h__ */
+++ /dev/null
-#include <asm-generic/div64.h>
+++ /dev/null
-#ifndef ___ASM_SPARC_DMA_MAPPING_H
-#define ___ASM_SPARC_DMA_MAPPING_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/dma-mapping_64.h>
-#else
-#include <asm-sparc/dma-mapping_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _ASM_SPARC_DMA_MAPPING_H
-#define _ASM_SPARC_DMA_MAPPING_H
-
-
-#ifdef CONFIG_PCI
-#include <asm-generic/dma-mapping.h>
-#else
-#include <asm-generic/dma-mapping-broken.h>
-#endif /* PCI */
-
-#endif /* _ASM_SPARC_DMA_MAPPING_H */
+++ /dev/null
-#ifndef _ASM_SPARC64_DMA_MAPPING_H
-#define _ASM_SPARC64_DMA_MAPPING_H
-
-#include <linux/scatterlist.h>
-#include <linux/mm.h>
-
-#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
-
-struct dma_ops {
- void *(*alloc_coherent)(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t flag);
- void (*free_coherent)(struct device *dev, size_t size,
- void *cpu_addr, dma_addr_t dma_handle);
- dma_addr_t (*map_single)(struct device *dev, void *cpu_addr,
- size_t size,
- enum dma_data_direction direction);
- void (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
- size_t size,
- enum dma_data_direction direction);
- int (*map_sg)(struct device *dev, struct scatterlist *sg, int nents,
- enum dma_data_direction direction);
- void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
- int nhwentries,
- enum dma_data_direction direction);
- void (*sync_single_for_cpu)(struct device *dev,
- dma_addr_t dma_handle, size_t size,
- enum dma_data_direction direction);
- void (*sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg,
- int nelems,
- enum dma_data_direction direction);
-};
-extern const struct dma_ops *dma_ops;
-
-extern int dma_supported(struct device *dev, u64 mask);
-extern int dma_set_mask(struct device *dev, u64 dma_mask);
-
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t flag)
-{
- return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
-}
-
-static inline void dma_free_coherent(struct device *dev, size_t size,
- void *cpu_addr, dma_addr_t dma_handle)
-{
- dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
-}
-
-static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
- size_t size,
- enum dma_data_direction direction)
-{
- return dma_ops->map_single(dev, cpu_addr, size, direction);
-}
-
-static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
- size_t size,
- enum dma_data_direction direction)
-{
- dma_ops->unmap_single(dev, dma_addr, size, direction);
-}
-
-static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size,
- enum dma_data_direction direction)
-{
- return dma_ops->map_single(dev, page_address(page) + offset,
- size, direction);
-}
-
-static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
- size_t size,
- enum dma_data_direction direction)
-{
- dma_ops->unmap_single(dev, dma_address, size, direction);
-}
-
-static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
- int nents, enum dma_data_direction direction)
-{
- return dma_ops->map_sg(dev, sg, nents, direction);
-}
-
-static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
- int nents, enum dma_data_direction direction)
-{
- dma_ops->unmap_sg(dev, sg, nents, direction);
-}
-
-static inline void dma_sync_single_for_cpu(struct device *dev,
- dma_addr_t dma_handle, size_t size,
- enum dma_data_direction direction)
-{
- dma_ops->sync_single_for_cpu(dev, dma_handle, size, direction);
-}
-
-static inline void dma_sync_single_for_device(struct device *dev,
- dma_addr_t dma_handle,
- size_t size,
- enum dma_data_direction direction)
-{
- /* No flushing needed to sync cpu writes to the device. */
-}
-
-static inline void dma_sync_single_range_for_cpu(struct device *dev,
- dma_addr_t dma_handle,
- unsigned long offset,
- size_t size,
- enum dma_data_direction direction)
-{
- dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
-}
-
-static inline void dma_sync_single_range_for_device(struct device *dev,
- dma_addr_t dma_handle,
- unsigned long offset,
- size_t size,
- enum dma_data_direction direction)
-{
- /* No flushing needed to sync cpu writes to the device. */
-}
-
-
-static inline void dma_sync_sg_for_cpu(struct device *dev,
- struct scatterlist *sg, int nelems,
- enum dma_data_direction direction)
-{
- dma_ops->sync_sg_for_cpu(dev, sg, nelems, direction);
-}
-
-static inline void dma_sync_sg_for_device(struct device *dev,
- struct scatterlist *sg, int nelems,
- enum dma_data_direction direction)
-{
- /* No flushing needed to sync cpu writes to the device. */
-}
-
-static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
-{
- return (dma_addr == DMA_ERROR_CODE);
-}
-
-static inline int dma_get_cache_alignment(void)
-{
- /* no easy way to get cache size on all processors, so return
- * the maximum possible, to be safe */
- return (1 << INTERNODE_CACHE_SHIFT);
-}
-
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-#define dma_is_consistent(d, h) (1)
-
-#endif /* _ASM_SPARC64_DMA_MAPPING_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_DMA_H
-#define ___ASM_SPARC_DMA_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/dma_64.h>
-#else
-#include <asm-sparc/dma_32.h>
-#endif
-#endif
+++ /dev/null
-/* include/asm-sparc/dma.h
- *
- * Copyright 1995 (C) David S. Miller (davem@davemloft.net)
- */
-
-#ifndef _ASM_SPARC_DMA_H
-#define _ASM_SPARC_DMA_H
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-#include <asm/vac-ops.h> /* for invalidate's, etc. */
-#include <asm/sbus.h>
-#include <asm/delay.h>
-#include <asm/oplib.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <linux/spinlock.h>
-
-struct page;
-extern spinlock_t dma_spin_lock;
-
-static inline unsigned long claim_dma_lock(void)
-{
- unsigned long flags;
- spin_lock_irqsave(&dma_spin_lock, flags);
- return flags;
-}
-
-static inline void release_dma_lock(unsigned long flags)
-{
- spin_unlock_irqrestore(&dma_spin_lock, flags);
-}
-
-/* These are irrelevant for Sparc DMA, but we leave it in so that
- * things can compile.
- */
-#define MAX_DMA_CHANNELS 8
-#define MAX_DMA_ADDRESS (~0UL)
-#define DMA_MODE_READ 1
-#define DMA_MODE_WRITE 2
-
-/* Useful constants */
-#define SIZE_16MB (16*1024*1024)
-#define SIZE_64K (64*1024)
-
-/* SBUS DMA controller reg offsets */
-#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
-#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
-#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
-#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
-
-/* DVMA chip revisions */
-enum dvma_rev {
- dvmarev0,
- dvmaesc1,
- dvmarev1,
- dvmarev2,
- dvmarev3,
- dvmarevplus,
- dvmahme
-};
-
-#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
-
-/* Linux DMA information structure, filled during probe. */
-struct sbus_dma {
- struct sbus_dma *next;
- struct sbus_dev *sdev;
- void __iomem *regs;
-
- /* Status, misc info */
- int node; /* Prom node for this DMA device */
- int running; /* Are we doing DMA now? */
- int allocated; /* Are we "owned" by anyone yet? */
-
- /* Transfer information. */
- unsigned long addr; /* Start address of current transfer */
- int nbytes; /* Size of current transfer */
- int realbytes; /* For splitting up large transfers, etc. */
-
- /* DMA revision */
- enum dvma_rev revision;
-};
-
-extern struct sbus_dma *dma_chain;
-
-/* Broken hardware... */
-#ifdef CONFIG_SUN4
-/* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken?
- * Or is rev0 present only on sun4 boxes? -jj */
-#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1)
-#else
-#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
-#endif
-#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
-
-/* Main routines in dma.c */
-extern void dvma_init(struct sbus_bus *);
-
-/* Fields in the cond_reg register */
-/* First, the version identification bits */
-#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
-#define DMA_VERS0 0x00000000 /* Sunray DMA version */
-#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
-#define DMA_VERS1 0x80000000 /* DMA rev 1 */
-#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
-#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
-#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
-
-#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
-#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
-#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
-#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
-#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
-#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
-#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
-#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
-#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
-#define DMA_RST_BPP DMA_RST_SCSI /* Reset the BPP controller */
-#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
-#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
-#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
-#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
-#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
-#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
-#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
-#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
-#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
-#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
-#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
-#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
-#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
-#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
-#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
-#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
-#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
-#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
-#define DMA_BRST32 0x00040000 /* SCSI/BPP: 32byte bursts */
-#define DMA_BRST16 0x00000000 /* SCSI/BPP: 16byte bursts */
-#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
-#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
-#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
-#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
-#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
-#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
-#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
-#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
-#define DMA_BPP_ON DMA_SCSI_ON /* Enable BPP dma */
-#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
-#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
-#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
-#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
-
-/* Values describing the burst-size property from the PROM */
-#define DMA_BURST1 0x01
-#define DMA_BURST2 0x02
-#define DMA_BURST4 0x04
-#define DMA_BURST8 0x08
-#define DMA_BURST16 0x10
-#define DMA_BURST32 0x20
-#define DMA_BURST64 0x40
-#define DMA_BURSTBITS 0x7f
-
-/* Determine highest possible final transfer address given a base */
-#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
-
-/* Yes, I hack a lot of elisp in my spare time... */
-#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
-#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
-#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
-#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
-#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
-#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
-#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
-#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
-#define DMA_BEGINDMA_W(regs) \
- ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
-#define DMA_BEGINDMA_R(regs) \
- ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
-
-/* For certain DMA chips, we need to disable ints upon irq entry
- * and turn them back on when we are done. So in any ESP interrupt
- * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
- * when leaving the handler. You have been warned...
- */
-#define DMA_IRQ_ENTRY(dma, dregs) do { \
- if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
- } while (0)
-
-#define DMA_IRQ_EXIT(dma, dregs) do { \
- if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
- } while(0)
-
-#if 0 /* P3 this stuff is inline in ledma.c:init_restart_ledma() */
-/* Pause until counter runs out or BIT isn't set in the DMA condition
- * register.
- */
-static inline void sparc_dma_pause(struct sparc_dma_registers *regs,
- unsigned long bit)
-{
- int ctr = 50000; /* Let's find some bugs ;) */
-
- /* Busy wait until the bit is not set any more */
- while((regs->cond_reg&bit) && (ctr>0)) {
- ctr--;
- __delay(5);
- }
-
- /* Check for bogus outcome. */
- if(!ctr)
- panic("DMA timeout");
-}
-
-/* Reset the friggin' thing... */
-#define DMA_RESET(dma) do { \
- struct sparc_dma_registers *regs = dma->regs; \
- /* Let the current FIFO drain itself */ \
- sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
- /* Reset the logic */ \
- regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
- __delay(400); /* let the bits set ;) */ \
- regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
- sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
- /* Enable FAST transfers if available */ \
- if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
- dma->running = 0; \
-} while(0)
-#endif
-
-#define for_each_dvma(dma) \
- for((dma) = dma_chain; (dma); (dma) = (dma)->next)
-
-extern int get_dma_list(char *);
-extern int request_dma(unsigned int, __const__ char *);
-extern void free_dma(unsigned int);
-
-/* From PCI */
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy (0)
-#endif
-
-/* Routines for data transfer buffers. */
-BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long)
-BTFIXUPDEF_CALL(void, mmu_unlockarea, char *, unsigned long)
-
-#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len)
-#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len)
-
-/* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */
-BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, char *, unsigned long, struct sbus_bus *sbus)
-BTFIXUPDEF_CALL(void, mmu_get_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
-BTFIXUPDEF_CALL(void, mmu_release_scsi_one, __u32, unsigned long, struct sbus_bus *sbus)
-BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
-
-#define mmu_get_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_get_scsi_one)(vaddr,len,sbus)
-#define mmu_get_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_get_scsi_sgl)(sg,sz,sbus)
-#define mmu_release_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_release_scsi_one)(vaddr,len,sbus)
-#define mmu_release_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_release_scsi_sgl)(sg,sz,sbus)
-
-/*
- * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep.
- *
- * The mmu_map_dma_area establishes two mappings in one go.
- * These mappings point to pages normally mapped at 'va' (linear address).
- * First mapping is for CPU visible address at 'a', uncached.
- * This is an alias, but it works because it is an uncached mapping.
- * Second mapping is for device visible address, or "bus" address.
- * The bus address is returned at '*pba'.
- *
- * These functions seem distinct, but are hard to split. On sun4c,
- * at least for now, 'a' is equal to bus address, and retured in *pba.
- * On sun4m, page attributes depend on the CPU type, so we have to
- * know if we are mapping RAM or I/O, so it has to be an additional argument
- * to a separate mapping function for CPU visible mappings.
- */
-BTFIXUPDEF_CALL(int, mmu_map_dma_area, dma_addr_t *, unsigned long, unsigned long, int len)
-BTFIXUPDEF_CALL(struct page *, mmu_translate_dvma, unsigned long busa)
-BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, unsigned long busa, int len)
-
-#define mmu_map_dma_area(pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(pba,va,a,len)
-#define mmu_unmap_dma_area(ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(ba,len)
-#define mmu_translate_dvma(ba) BTFIXUP_CALL(mmu_translate_dvma)(ba)
-
-#endif /* !(_ASM_SPARC_DMA_H) */
+++ /dev/null
-/*
- * include/asm-sparc64/dma.h
- *
- * Copyright 1996 (C) David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _ASM_SPARC64_DMA_H
-#define _ASM_SPARC64_DMA_H
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/spinlock.h>
-
-#include <asm/sbus.h>
-#include <asm/delay.h>
-#include <asm/oplib.h>
-
-/* These are irrelevant for Sparc DMA, but we leave it in so that
- * things can compile.
- */
-#define MAX_DMA_CHANNELS 8
-#define DMA_MODE_READ 1
-#define DMA_MODE_WRITE 2
-#define MAX_DMA_ADDRESS (~0UL)
-
-/* Useful constants */
-#define SIZE_16MB (16*1024*1024)
-#define SIZE_64K (64*1024)
-
-/* SBUS DMA controller reg offsets */
-#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
-#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
-#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
-#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
-
-/* DVMA chip revisions */
-enum dvma_rev {
- dvmarev0,
- dvmaesc1,
- dvmarev1,
- dvmarev2,
- dvmarev3,
- dvmarevplus,
- dvmahme
-};
-
-#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
-
-/* Linux DMA information structure, filled during probe. */
-struct sbus_dma {
- struct sbus_dma *next;
- struct sbus_dev *sdev;
- void __iomem *regs;
-
- /* Status, misc info */
- int node; /* Prom node for this DMA device */
- int running; /* Are we doing DMA now? */
- int allocated; /* Are we "owned" by anyone yet? */
-
- /* Transfer information. */
- u32 addr; /* Start address of current transfer */
- int nbytes; /* Size of current transfer */
- int realbytes; /* For splitting up large transfers, etc. */
-
- /* DMA revision */
- enum dvma_rev revision;
-};
-
-extern struct sbus_dma *dma_chain;
-
-/* Broken hardware... */
-#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
-#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
-
-/* Main routines in dma.c */
-extern void dvma_init(struct sbus_bus *);
-
-/* Fields in the cond_reg register */
-/* First, the version identification bits */
-#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
-#define DMA_VERS0 0x00000000 /* Sunray DMA version */
-#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
-#define DMA_VERS1 0x80000000 /* DMA rev 1 */
-#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
-#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
-#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
-
-#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
-#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
-#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
-#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
-#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
-#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
-#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
-#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
-#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
-#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
-#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
-#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
-#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
-#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
-#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
-#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
-#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
-#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
-#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
-#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
-#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
-#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
-#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
-#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
-#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
-#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
-#define DMA_BRST64 0x000c0000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
-#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
-#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
-#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
-#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
-#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
-#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
-#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
-#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
-#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
-#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
-#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
-#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
-#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
-#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
-
-/* Values describing the burst-size property from the PROM */
-#define DMA_BURST1 0x01
-#define DMA_BURST2 0x02
-#define DMA_BURST4 0x04
-#define DMA_BURST8 0x08
-#define DMA_BURST16 0x10
-#define DMA_BURST32 0x20
-#define DMA_BURST64 0x40
-#define DMA_BURSTBITS 0x7f
-
-/* Determine highest possible final transfer address given a base */
-#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
-
-/* Yes, I hack a lot of elisp in my spare time... */
-#define DMA_ERROR_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_HNDL_ERROR))
-#define DMA_IRQ_P(regs) ((sbus_readl((regs) + DMA_CSR)) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
-#define DMA_WRITE_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_ST_WRITE))
-#define DMA_OFF(__regs) \
-do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
- tmp &= ~DMA_ENABLE; \
- sbus_writel(tmp, (__regs) + DMA_CSR); \
-} while(0)
-#define DMA_INTSOFF(__regs) \
-do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
- tmp &= ~DMA_INT_ENAB; \
- sbus_writel(tmp, (__regs) + DMA_CSR); \
-} while(0)
-#define DMA_INTSON(__regs) \
-do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
- tmp |= DMA_INT_ENAB; \
- sbus_writel(tmp, (__regs) + DMA_CSR); \
-} while(0)
-#define DMA_PUNTFIFO(__regs) \
-do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
- tmp |= DMA_FIFO_INV; \
- sbus_writel(tmp, (__regs) + DMA_CSR); \
-} while(0)
-#define DMA_SETSTART(__regs, __addr) \
- sbus_writel((u32)(__addr), (__regs) + DMA_ADDR);
-#define DMA_BEGINDMA_W(__regs) \
-do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
- tmp |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB); \
- sbus_writel(tmp, (__regs) + DMA_CSR); \
-} while(0)
-#define DMA_BEGINDMA_R(__regs) \
-do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
- tmp |= (DMA_ENABLE|DMA_INT_ENAB); \
- tmp &= ~DMA_ST_WRITE; \
- sbus_writel(tmp, (__regs) + DMA_CSR); \
-} while(0)
-
-/* For certain DMA chips, we need to disable ints upon irq entry
- * and turn them back on when we are done. So in any ESP interrupt
- * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
- * when leaving the handler. You have been warned...
- */
-#define DMA_IRQ_ENTRY(dma, dregs) do { \
- if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
- } while (0)
-
-#define DMA_IRQ_EXIT(dma, dregs) do { \
- if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
- } while(0)
-
-#define for_each_dvma(dma) \
- for((dma) = dma_chain; (dma); (dma) = (dma)->next)
-
-/* From PCI */
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy (0)
-#endif
-
-#endif /* !(_ASM_SPARC64_DMA_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_EBUS_H
-#define ___ASM_SPARC_EBUS_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/ebus_64.h>
-#else
-#include <asm-sparc/ebus_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * ebus.h: PCI to Ebus pseudo driver software state.
- *
- * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
- *
- * Adopted for sparc by V. Roganov and G. Raiko.
- */
-
-#ifndef __SPARC_EBUS_H
-#define __SPARC_EBUS_H
-
-#ifndef _LINUX_IOPORT_H
-#include <linux/ioport.h>
-#endif
-#include <asm/oplib.h>
-#include <asm/prom.h>
-#include <asm/of_device.h>
-
-struct linux_ebus_child {
- struct linux_ebus_child *next;
- struct linux_ebus_device *parent;
- struct linux_ebus *bus;
- struct device_node *prom_node;
- struct resource resource[PROMREG_MAX];
- int num_addrs;
- unsigned int irqs[PROMINTR_MAX];
- int num_irqs;
-};
-
-struct linux_ebus_device {
- struct of_device ofdev;
- struct linux_ebus_device *next;
- struct linux_ebus_child *children;
- struct linux_ebus *bus;
- struct device_node *prom_node;
- struct resource resource[PROMREG_MAX];
- int num_addrs;
- unsigned int irqs[PROMINTR_MAX];
- int num_irqs;
-};
-#define to_ebus_device(d) container_of(d, struct linux_ebus_device, ofdev.dev)
-
-struct linux_ebus {
- struct of_device ofdev;
- struct linux_ebus *next;
- struct linux_ebus_device *devices;
- struct linux_pbm_info *parent;
- struct pci_dev *self;
- struct device_node *prom_node;
-};
-#define to_ebus(d) container_of(d, struct linux_ebus, ofdev.dev)
-
-struct linux_ebus_dma {
- unsigned int dcsr;
- unsigned int dacr;
- unsigned int dbcr;
-};
-
-#define EBUS_DCSR_INT_PEND 0x00000001
-#define EBUS_DCSR_ERR_PEND 0x00000002
-#define EBUS_DCSR_DRAIN 0x00000004
-#define EBUS_DCSR_INT_EN 0x00000010
-#define EBUS_DCSR_RESET 0x00000080
-#define EBUS_DCSR_WRITE 0x00000100
-#define EBUS_DCSR_EN_DMA 0x00000200
-#define EBUS_DCSR_CYC_PEND 0x00000400
-#define EBUS_DCSR_DIAG_RD_DONE 0x00000800
-#define EBUS_DCSR_DIAG_WR_DONE 0x00001000
-#define EBUS_DCSR_EN_CNT 0x00002000
-#define EBUS_DCSR_TC 0x00004000
-#define EBUS_DCSR_DIS_CSR_DRN 0x00010000
-#define EBUS_DCSR_BURST_SZ_MASK 0x000c0000
-#define EBUS_DCSR_BURST_SZ_1 0x00080000
-#define EBUS_DCSR_BURST_SZ_4 0x00000000
-#define EBUS_DCSR_BURST_SZ_8 0x00040000
-#define EBUS_DCSR_BURST_SZ_16 0x000c0000
-#define EBUS_DCSR_DIAG_EN 0x00100000
-#define EBUS_DCSR_DIS_ERR_PEND 0x00400000
-#define EBUS_DCSR_TCI_DIS 0x00800000
-#define EBUS_DCSR_EN_NEXT 0x01000000
-#define EBUS_DCSR_DMA_ON 0x02000000
-#define EBUS_DCSR_A_LOADED 0x04000000
-#define EBUS_DCSR_NA_LOADED 0x08000000
-#define EBUS_DCSR_DEV_ID_MASK 0xf0000000
-
-extern struct linux_ebus *ebus_chain;
-
-extern void ebus_init(void);
-
-#define for_each_ebus(bus) \
- for((bus) = ebus_chain; (bus); (bus) = (bus)->next)
-
-#define for_each_ebusdev(dev, bus) \
- for((dev) = (bus)->devices; (dev); (dev) = (dev)->next)
-
-#define for_each_edevchild(dev, child) \
- for((child) = (dev)->children; (child); (child) = (child)->next)
-
-#endif /* !(__SPARC_EBUS_H) */
+++ /dev/null
-/*
- * ebus.h: PCI to Ebus pseudo driver software state.
- *
- * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
- * Copyright (C) 1999 David S. Miller (davem@redhat.com)
- */
-
-#ifndef __SPARC64_EBUS_H
-#define __SPARC64_EBUS_H
-
-#include <asm/oplib.h>
-#include <asm/prom.h>
-#include <asm/of_device.h>
-
-struct linux_ebus_child {
- struct linux_ebus_child *next;
- struct linux_ebus_device *parent;
- struct linux_ebus *bus;
- struct device_node *prom_node;
- struct resource resource[PROMREG_MAX];
- int num_addrs;
- unsigned int irqs[PROMINTR_MAX];
- int num_irqs;
-};
-
-struct linux_ebus_device {
- struct of_device ofdev;
- struct linux_ebus_device *next;
- struct linux_ebus_child *children;
- struct linux_ebus *bus;
- struct device_node *prom_node;
- struct resource resource[PROMREG_MAX];
- int num_addrs;
- unsigned int irqs[PROMINTR_MAX];
- int num_irqs;
-};
-#define to_ebus_device(d) container_of(d, struct linux_ebus_device, ofdev.dev)
-
-struct linux_ebus {
- struct of_device ofdev;
- struct linux_ebus *next;
- struct linux_ebus_device *devices;
- struct pci_dev *self;
- int index;
- int is_rio;
- struct device_node *prom_node;
-};
-#define to_ebus(d) container_of(d, struct linux_ebus, ofdev.dev)
-
-struct ebus_dma_info {
- spinlock_t lock;
- void __iomem *regs;
-
- unsigned int flags;
-#define EBUS_DMA_FLAG_USE_EBDMA_HANDLER 0x00000001
-#define EBUS_DMA_FLAG_TCI_DISABLE 0x00000002
-
- /* These are only valid is EBUS_DMA_FLAG_USE_EBDMA_HANDLER is
- * set.
- */
- void (*callback)(struct ebus_dma_info *p, int event, void *cookie);
- void *client_cookie;
- unsigned int irq;
-#define EBUS_DMA_EVENT_ERROR 1
-#define EBUS_DMA_EVENT_DMA 2
-#define EBUS_DMA_EVENT_DEVICE 4
-
- unsigned char name[64];
-};
-
-extern int ebus_dma_register(struct ebus_dma_info *p);
-extern int ebus_dma_irq_enable(struct ebus_dma_info *p, int on);
-extern void ebus_dma_unregister(struct ebus_dma_info *p);
-extern int ebus_dma_request(struct ebus_dma_info *p, dma_addr_t bus_addr,
- size_t len);
-extern void ebus_dma_prepare(struct ebus_dma_info *p, int write);
-extern unsigned int ebus_dma_residue(struct ebus_dma_info *p);
-extern unsigned int ebus_dma_addr(struct ebus_dma_info *p);
-extern void ebus_dma_enable(struct ebus_dma_info *p, int on);
-
-extern struct linux_ebus *ebus_chain;
-
-extern void ebus_init(void);
-
-#define for_each_ebus(bus) \
- for((bus) = ebus_chain; (bus); (bus) = (bus)->next)
-
-#define for_each_ebusdev(dev, bus) \
- for((dev) = (bus)->devices; (dev); (dev) = (dev)->next)
-
-#define for_each_edevchild(dev, child) \
- for((child) = (dev)->children; (child); (child) = (child)->next)
-
-#endif /* !(__SPARC64_EBUS_H) */
+++ /dev/null
-/*
- * ecc.h: Definitions and defines for the external cache/memory
- * controller on the sun4m.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_ECC_H
-#define _SPARC_ECC_H
-
-/* These registers are accessed through the SRMMU passthrough ASI 0x20 */
-#define ECC_ENABLE 0x00000000 /* ECC enable register */
-#define ECC_FSTATUS 0x00000008 /* ECC fault status register */
-#define ECC_FADDR 0x00000010 /* ECC fault address register */
-#define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */
-#define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */
-#define ECC_DMESG 0x00001000 /* Diagnostic message passing area */
-
-/* ECC MBus Arbiter Enable register:
- *
- * ----------------------------------------
- * | |SBUS|MOD3|MOD2|MOD1|RSV|
- * ----------------------------------------
- * 31 5 4 3 2 1 0
- *
- * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on
- * MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on
- * MOD2: Enable MBus Arbiter on MBus module 2 0=off 1=on
- * MOD1: Enable MBus Arbiter on MBus module 1 0=off 1=on
- */
-
-#define ECC_MBAE_SBUS 0x00000010
-#define ECC_MBAE_MOD3 0x00000008
-#define ECC_MBAE_MOD2 0x00000004
-#define ECC_MBAE_MOD1 0x00000002
-
-/* ECC Fault Control Register layout:
- *
- * -----------------------------
- * | RESV | ECHECK | EINT |
- * -----------------------------
- * 31 2 1 0
- *
- * ECHECK: Enable ECC checking. 0=off 1=on
- * EINT: Enable Interrupts for correctable errors. 0=off 1=on
- */
-#define ECC_FCR_CHECK 0x00000002
-#define ECC_FCR_INTENAB 0x00000001
-
-/* ECC Fault Address Register Zero layout:
- *
- * -----------------------------------------------------
- * | MID | S | RSV | VA | BM |AT| C| SZ |TYP| PADDR |
- * -----------------------------------------------------
- * 31-28 27 26-22 21-14 13 12 11 10-8 7-4 3-0
- *
- * MID: ModuleID of the faulting processor. ie. who did it?
- * S: Supervisor/Privileged access? 0=no 1=yes
- * VA: Bits 19-12 of the virtual faulting address, these are the
- * superset bits in the virtual cache and can be used for
- * a flush operation if necessary.
- * BM: Boot mode? 0=no 1=yes This is just like the SRMMU boot
- * mode bit.
- * AT: Did this fault happen during an atomic instruction? 0=no
- * 1=yes. This means either an 'ldstub' or 'swap' instruction
- * was in progress (but not finished) when this fault happened.
- * This indicated whether the bus was locked when the fault
- * occurred.
- * C: Did the pte for this access indicate that it was cacheable?
- * 0=no 1=yes
- * SZ: The size of the transaction.
- * TYP: The transaction type.
- * PADDR: Bits 35-32 of the physical address for the fault.
- */
-#define ECC_FADDR0_MIDMASK 0xf0000000
-#define ECC_FADDR0_S 0x08000000
-#define ECC_FADDR0_VADDR 0x003fc000
-#define ECC_FADDR0_BMODE 0x00002000
-#define ECC_FADDR0_ATOMIC 0x00001000
-#define ECC_FADDR0_CACHE 0x00000800
-#define ECC_FADDR0_SIZE 0x00000700
-#define ECC_FADDR0_TYPE 0x000000f0
-#define ECC_FADDR0_PADDR 0x0000000f
-
-/* ECC Fault Address Register One layout:
- *
- * -------------------------------------
- * | Physical Address 31-0 |
- * -------------------------------------
- * 31 0
- *
- * You get the upper 4 bits of the physical address from the
- * PADDR field in ECC Fault Address Zero register.
- */
-
-/* ECC Fault Status Register layout:
- *
- * ----------------------------------------------
- * | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C|
- * ----------------------------------------------
- * 31-18 17 16 15-8 7-4 3 2 1 0
- *
- * C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only)
- * MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes)
- * SYNDROME: Controller is mentally unstable.
- * DWORD:
- * UNC: Uncorrectable error. 0=no 1=yes
- * TIMEO: Timeout occurred. 0=no 1=yes
- * BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only)
- * C: Correctable error? 0=no 1=yes
- */
-
-#define ECC_FSR_C2ERR 0x00020000
-#define ECC_FSR_MULT 0x00010000
-#define ECC_FSR_SYND 0x0000ff00
-#define ECC_FSR_DWORD 0x000000f0
-#define ECC_FSR_UNC 0x00000008
-#define ECC_FSR_TIMEO 0x00000004
-#define ECC_FSR_BADSLOT 0x00000002
-#define ECC_FSR_C 0x00000001
-
-#endif /* !(_SPARC_ECC_H) */
+++ /dev/null
-/*
- * eeprom.h: Definitions for the Sun eeprom.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-/* The EEPROM and the Mostek Mk48t02 use the same IO address space
- * for their registers/data areas. The IDPROM lives here too.
- */
+++ /dev/null
-#ifndef ___ASM_SPARC_ELF_H
-#define ___ASM_SPARC_ELF_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/elf_64.h>
-#else
-#include <asm-sparc/elf_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef __ASMSPARC_ELF_H
-#define __ASMSPARC_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-
-/*
- * Sparc section types
- */
-#define STT_REGISTER 13
-
-/*
- * Sparc ELF relocation types
- */
-#define R_SPARC_NONE 0
-#define R_SPARC_8 1
-#define R_SPARC_16 2
-#define R_SPARC_32 3
-#define R_SPARC_DISP8 4
-#define R_SPARC_DISP16 5
-#define R_SPARC_DISP32 6
-#define R_SPARC_WDISP30 7
-#define R_SPARC_WDISP22 8
-#define R_SPARC_HI22 9
-#define R_SPARC_22 10
-#define R_SPARC_13 11
-#define R_SPARC_LO10 12
-#define R_SPARC_GOT10 13
-#define R_SPARC_GOT13 14
-#define R_SPARC_GOT22 15
-#define R_SPARC_PC10 16
-#define R_SPARC_PC22 17
-#define R_SPARC_WPLT30 18
-#define R_SPARC_COPY 19
-#define R_SPARC_GLOB_DAT 20
-#define R_SPARC_JMP_SLOT 21
-#define R_SPARC_RELATIVE 22
-#define R_SPARC_UA32 23
-#define R_SPARC_PLT32 24
-#define R_SPARC_HIPLT22 25
-#define R_SPARC_LOPLT10 26
-#define R_SPARC_PCPLT32 27
-#define R_SPARC_PCPLT22 28
-#define R_SPARC_PCPLT10 29
-#define R_SPARC_10 30
-#define R_SPARC_11 31
-#define R_SPARC_64 32
-#define R_SPARC_OLO10 33
-#define R_SPARC_WDISP16 40
-#define R_SPARC_WDISP19 41
-#define R_SPARC_7 43
-#define R_SPARC_5 44
-#define R_SPARC_6 45
-
-/* Bits present in AT_HWCAP, primarily for Sparc32. */
-
-#define HWCAP_SPARC_FLUSH 1 /* CPU supports flush instruction. */
-#define HWCAP_SPARC_STBAR 2
-#define HWCAP_SPARC_SWAP 4
-#define HWCAP_SPARC_MULDIV 8
-#define HWCAP_SPARC_V9 16
-#define HWCAP_SPARC_ULTRA3 32
-
-#define CORE_DUMP_USE_REGSET
-
-/* Format is:
- * G0 --> G7
- * O0 --> O7
- * L0 --> L7
- * I0 --> I7
- * PSR, PC, nPC, Y, WIM, TBR
- */
-typedef unsigned long elf_greg_t;
-#define ELF_NGREG 38
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct {
- union {
- unsigned long pr_regs[32];
- double pr_dregs[16];
- } pr_fr;
- unsigned long __unused;
- unsigned long pr_fsr;
- unsigned char pr_qcnt;
- unsigned char pr_q_entrysize;
- unsigned char pr_en;
- unsigned int pr_q[64];
-} elf_fpregset_t;
-
-#include <asm/mbus.h>
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_SPARC)
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_ARCH EM_SPARC
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2MSB
-
-#define USE_ELF_CORE_DUMP
-#ifndef CONFIG_SUN4
-#define ELF_EXEC_PAGESIZE 4096
-#else
-#define ELF_EXEC_PAGESIZE 8192
-#endif
-
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#define ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE)
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this cpu supports. This can NOT be done in userspace
- on Sparc. */
-
-/* Sun4c has none of the capabilities, most sun4m's have them all.
- * XXX This is gross, set some global variable at boot time. -DaveM
- */
-#define ELF_HWCAP ((ARCH_SUN4C_SUN4) ? 0 : \
- (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \
- HWCAP_SPARC_SWAP | \
- ((srmmu_modtype != Cypress && \
- srmmu_modtype != Cypress_vE && \
- srmmu_modtype != Cypress_vD) ? \
- HWCAP_SPARC_MULDIV : 0)))
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo. */
-
-#define ELF_PLATFORM (NULL)
-
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
-
-#endif /* !(__ASMSPARC_ELF_H) */
+++ /dev/null
-#ifndef __ASM_SPARC64_ELF_H
-#define __ASM_SPARC64_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-#include <asm/processor.h>
-#include <asm/uaccess.h>
-#include <asm/spitfire.h>
-
-/*
- * Sparc section types
- */
-#define STT_REGISTER 13
-
-/*
- * Sparc ELF relocation types
- */
-#define R_SPARC_NONE 0
-#define R_SPARC_8 1
-#define R_SPARC_16 2
-#define R_SPARC_32 3
-#define R_SPARC_DISP8 4
-#define R_SPARC_DISP16 5
-#define R_SPARC_DISP32 6
-#define R_SPARC_WDISP30 7
-#define R_SPARC_WDISP22 8
-#define R_SPARC_HI22 9
-#define R_SPARC_22 10
-#define R_SPARC_13 11
-#define R_SPARC_LO10 12
-#define R_SPARC_GOT10 13
-#define R_SPARC_GOT13 14
-#define R_SPARC_GOT22 15
-#define R_SPARC_PC10 16
-#define R_SPARC_PC22 17
-#define R_SPARC_WPLT30 18
-#define R_SPARC_COPY 19
-#define R_SPARC_GLOB_DAT 20
-#define R_SPARC_JMP_SLOT 21
-#define R_SPARC_RELATIVE 22
-#define R_SPARC_UA32 23
-#define R_SPARC_PLT32 24
-#define R_SPARC_HIPLT22 25
-#define R_SPARC_LOPLT10 26
-#define R_SPARC_PCPLT32 27
-#define R_SPARC_PCPLT22 28
-#define R_SPARC_PCPLT10 29
-#define R_SPARC_10 30
-#define R_SPARC_11 31
-#define R_SPARC_64 32
-#define R_SPARC_OLO10 33
-#define R_SPARC_WDISP16 40
-#define R_SPARC_WDISP19 41
-#define R_SPARC_7 43
-#define R_SPARC_5 44
-#define R_SPARC_6 45
-
-/* Bits present in AT_HWCAP, primarily for Sparc32. */
-
-#define HWCAP_SPARC_FLUSH 1 /* CPU supports flush instruction. */
-#define HWCAP_SPARC_STBAR 2
-#define HWCAP_SPARC_SWAP 4
-#define HWCAP_SPARC_MULDIV 8
-#define HWCAP_SPARC_V9 16
-#define HWCAP_SPARC_ULTRA3 32
-#define HWCAP_SPARC_BLKINIT 64
-#define HWCAP_SPARC_N2 128
-
-#define CORE_DUMP_USE_REGSET
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_ARCH EM_SPARCV9
-#define ELF_CLASS ELFCLASS64
-#define ELF_DATA ELFDATA2MSB
-
-/* Format of 64-bit elf_gregset_t is:
- * G0 --> G7
- * O0 --> O7
- * L0 --> L7
- * I0 --> I7
- * TSTATE
- * TPC
- * TNPC
- * Y
- */
-typedef unsigned long elf_greg_t;
-#define ELF_NGREG 36
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct {
- unsigned long pr_regs[32];
- unsigned long pr_fsr;
- unsigned long pr_gsr;
- unsigned long pr_fprs;
-} elf_fpregset_t;
-
-/* Format of 32-bit elf_gregset_t is:
- * G0 --> G7
- * O0 --> O7
- * L0 --> L7
- * I0 --> I7
- * PSR, PC, nPC, Y, WIM, TBR
- */
-typedef unsigned int compat_elf_greg_t;
-#define COMPAT_ELF_NGREG 38
-typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG];
-
-typedef struct {
- union {
- unsigned int pr_regs[32];
- unsigned long pr_dregs[16];
- } pr_fr;
- unsigned int __unused;
- unsigned int pr_fsr;
- unsigned char pr_qcnt;
- unsigned char pr_q_entrysize;
- unsigned char pr_en;
- unsigned int pr_q[64];
-} compat_elf_fpregset_t;
-
-/* UltraSparc extensions. Still unused, but will be eventually. */
-typedef struct {
- unsigned int pr_type;
- unsigned int pr_align;
- union {
- struct {
- union {
- unsigned int pr_regs[32];
- unsigned long pr_dregs[16];
- long double pr_qregs[8];
- } pr_xfr;
- } pr_v8p;
- unsigned int pr_xfsr;
- unsigned int pr_fprs;
- unsigned int pr_xg[8];
- unsigned int pr_xo[8];
- unsigned long pr_tstate;
- unsigned int pr_filler[8];
- } pr_un;
-} elf_xregset_t;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
-#define compat_elf_check_arch(x) ((x)->e_machine == EM_SPARC || \
- (x)->e_machine == EM_SPARC32PLUS)
-#define compat_start_thread start_thread32
-
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE PAGE_SIZE
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#define ELF_ET_DYN_BASE 0x0000010000000000UL
-#define COMPAT_ELF_ET_DYN_BASE 0x0000000070000000UL
-
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this cpu supports. */
-
-/* On Ultra, we support all of the v8 capabilities. */
-static inline unsigned int sparc64_elf_hwcap(void)
-{
- unsigned int cap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
- HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
- HWCAP_SPARC_V9);
-
- if (tlb_type == cheetah || tlb_type == cheetah_plus)
- cap |= HWCAP_SPARC_ULTRA3;
- else if (tlb_type == hypervisor) {
- if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
- sun4v_chip_type == SUN4V_CHIP_NIAGARA2)
- cap |= HWCAP_SPARC_BLKINIT;
- if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2)
- cap |= HWCAP_SPARC_N2;
- }
-
- return cap;
-}
-
-#define ELF_HWCAP sparc64_elf_hwcap();
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo. */
-
-#define ELF_PLATFORM (NULL)
-
-#define SET_PERSONALITY(ex, ibcs2) \
-do { unsigned long new_flags = current_thread_info()->flags; \
- new_flags &= _TIF_32BIT; \
- if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
- new_flags |= _TIF_32BIT; \
- else \
- new_flags &= ~_TIF_32BIT; \
- if ((current_thread_info()->flags & _TIF_32BIT) \
- != new_flags) \
- set_thread_flag(TIF_ABI_PENDING); \
- else \
- clear_thread_flag(TIF_ABI_PENDING); \
- /* flush_thread will update pgd cache */ \
- if (ibcs2) \
- set_personality(PER_SVR4); \
- else if (current->personality != PER_LINUX32) \
- set_personality(PER_LINUX); \
-} while (0)
-
-#endif /* !(__ASM_SPARC64_ELF_H) */
+++ /dev/null
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_EMERGENCY_RESTART_H */
+++ /dev/null
-/*
- *
- * envctrl.h: Definitions for access to the i2c environment
- * monitoring on Ultrasparc systems.
- *
- * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
- * Copyright (C) 2000 Vinh Truong (vinh.truong@eng.sun.com)
- * VT - Add all ioctl commands and environment status definitions
- * VT - Add application note
- */
-#ifndef _SPARC64_ENVCTRL_H
-#define _SPARC64_ENVCTRL_H 1
-
-#include <linux/ioctl.h>
-
-/* Application note:
- *
- * The driver supports 4 operations: open(), close(), ioctl(), read()
- * The device name is /dev/envctrl.
- * Below is sample usage:
- *
- * fd = open("/dev/envtrl", O_RDONLY);
- * if (ioctl(fd, ENVCTRL_READ_SHUTDOWN_TEMPERATURE, 0) < 0)
- * printf("error\n");
- * ret = read(fd, buf, 10);
- * close(fd);
- *
- * Notice in the case of cpu voltage and temperature, the default is
- * cpu0. If we need to know the info of cpu1, cpu2, cpu3, we need to
- * pass in cpu number in ioctl() last parameter. For example, to
- * get the voltage of cpu2:
- *
- * ioctlbuf[0] = 2;
- * if (ioctl(fd, ENVCTRL_READ_CPU_VOLTAGE, ioctlbuf) < 0)
- * printf("error\n");
- * ret = read(fd, buf, 10);
- *
- * All the return values are in ascii. So check read return value
- * and do appropriate conversions in your application.
- */
-
-/* IOCTL commands */
-
-/* Note: these commands reflect possible monitor features.
- * Some boards choose to support some of the features only.
- */
-#define ENVCTRL_RD_CPU_TEMPERATURE _IOR('p', 0x40, int)
-#define ENVCTRL_RD_CPU_VOLTAGE _IOR('p', 0x41, int)
-#define ENVCTRL_RD_FAN_STATUS _IOR('p', 0x42, int)
-#define ENVCTRL_RD_WARNING_TEMPERATURE _IOR('p', 0x43, int)
-#define ENVCTRL_RD_SHUTDOWN_TEMPERATURE _IOR('p', 0x44, int)
-#define ENVCTRL_RD_VOLTAGE_STATUS _IOR('p', 0x45, int)
-#define ENVCTRL_RD_SCSI_TEMPERATURE _IOR('p', 0x46, int)
-#define ENVCTRL_RD_ETHERNET_TEMPERATURE _IOR('p', 0x47, int)
-#define ENVCTRL_RD_MTHRBD_TEMPERATURE _IOR('p', 0x48, int)
-
-#define ENVCTRL_RD_GLOBALADDRESS _IOR('p', 0x49, int)
-
-/* Read return values for a voltage status request. */
-#define ENVCTRL_VOLTAGE_POWERSUPPLY_GOOD 0x01
-#define ENVCTRL_VOLTAGE_BAD 0x02
-#define ENVCTRL_POWERSUPPLY_BAD 0x03
-#define ENVCTRL_VOLTAGE_POWERSUPPLY_BAD 0x04
-
-/* Read return values for a fan status request.
- * A failure match means either the fan fails or
- * the fan is not connected. Some boards have optional
- * connectors to connect extra fans.
- *
- * There are maximum 8 monitor fans. Some are cpu fans
- * some are system fans. The mask below only indicates
- * fan by order number.
- * Below is a sample application:
- *
- * if (ioctl(fd, ENVCTRL_READ_FAN_STATUS, 0) < 0) {
- * printf("ioctl fan failed\n");
- * }
- * if (read(fd, rslt, 1) <= 0) {
- * printf("error or fan not monitored\n");
- * } else {
- * if (rslt[0] == ENVCTRL_ALL_FANS_GOOD) {
- * printf("all fans good\n");
- * } else if (rslt[0] == ENVCTRL_ALL_FANS_BAD) {
- * printf("all fans bad\n");
- * } else {
- * if (rslt[0] & ENVCTRL_FAN0_FAILURE_MASK) {
- * printf("fan 0 failed or not connected\n");
- * }
- * ......
- */
-
-#define ENVCTRL_ALL_FANS_GOOD 0x00
-#define ENVCTRL_FAN0_FAILURE_MASK 0x01
-#define ENVCTRL_FAN1_FAILURE_MASK 0x02
-#define ENVCTRL_FAN2_FAILURE_MASK 0x04
-#define ENVCTRL_FAN3_FAILURE_MASK 0x08
-#define ENVCTRL_FAN4_FAILURE_MASK 0x10
-#define ENVCTRL_FAN5_FAILURE_MASK 0x20
-#define ENVCTRL_FAN6_FAILURE_MASK 0x40
-#define ENVCTRL_FAN7_FAILURE_MASK 0x80
-#define ENVCTRL_ALL_FANS_BAD 0xFF
-
-#endif /* !(_SPARC64_ENVCTRL_H) */
+++ /dev/null
-#ifndef _SPARC_ERRNO_H
-#define _SPARC_ERRNO_H
-
-/* These match the SunOS error numbering scheme. */
-
-#include <asm-generic/errno-base.h>
-
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define EINPROGRESS 36 /* Operation now in progress */
-#define EALREADY 37 /* Operation already in progress */
-#define ENOTSOCK 38 /* Socket operation on non-socket */
-#define EDESTADDRREQ 39 /* Destination address required */
-#define EMSGSIZE 40 /* Message too long */
-#define EPROTOTYPE 41 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 42 /* Protocol not available */
-#define EPROTONOSUPPORT 43 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 44 /* Socket type not supported */
-#define EOPNOTSUPP 45 /* Op not supported on transport endpoint */
-#define EPFNOSUPPORT 46 /* Protocol family not supported */
-#define EAFNOSUPPORT 47 /* Address family not supported by protocol */
-#define EADDRINUSE 48 /* Address already in use */
-#define EADDRNOTAVAIL 49 /* Cannot assign requested address */
-#define ENETDOWN 50 /* Network is down */
-#define ENETUNREACH 51 /* Network is unreachable */
-#define ENETRESET 52 /* Net dropped connection because of reset */
-#define ECONNABORTED 53 /* Software caused connection abort */
-#define ECONNRESET 54 /* Connection reset by peer */
-#define ENOBUFS 55 /* No buffer space available */
-#define EISCONN 56 /* Transport endpoint is already connected */
-#define ENOTCONN 57 /* Transport endpoint is not connected */
-#define ESHUTDOWN 58 /* No send after transport endpoint shutdown */
-#define ETOOMANYREFS 59 /* Too many references: cannot splice */
-#define ETIMEDOUT 60 /* Connection timed out */
-#define ECONNREFUSED 61 /* Connection refused */
-#define ELOOP 62 /* Too many symbolic links encountered */
-#define ENAMETOOLONG 63 /* File name too long */
-#define EHOSTDOWN 64 /* Host is down */
-#define EHOSTUNREACH 65 /* No route to host */
-#define ENOTEMPTY 66 /* Directory not empty */
-#define EPROCLIM 67 /* SUNOS: Too many processes */
-#define EUSERS 68 /* Too many users */
-#define EDQUOT 69 /* Quota exceeded */
-#define ESTALE 70 /* Stale NFS file handle */
-#define EREMOTE 71 /* Object is remote */
-#define ENOSTR 72 /* Device not a stream */
-#define ETIME 73 /* Timer expired */
-#define ENOSR 74 /* Out of streams resources */
-#define ENOMSG 75 /* No message of desired type */
-#define EBADMSG 76 /* Not a data message */
-#define EIDRM 77 /* Identifier removed */
-#define EDEADLK 78 /* Resource deadlock would occur */
-#define ENOLCK 79 /* No record locks available */
-#define ENONET 80 /* Machine is not on the network */
-#define ERREMOTE 81 /* SunOS: Too many lvls of remote in path */
-#define ENOLINK 82 /* Link has been severed */
-#define EADV 83 /* Advertise error */
-#define ESRMNT 84 /* Srmount error */
-#define ECOMM 85 /* Communication error on send */
-#define EPROTO 86 /* Protocol error */
-#define EMULTIHOP 87 /* Multihop attempted */
-#define EDOTDOT 88 /* RFS specific error */
-#define EREMCHG 89 /* Remote address changed */
-#define ENOSYS 90 /* Function not implemented */
-
-/* The rest have no SunOS equivalent. */
-#define ESTRPIPE 91 /* Streams pipe error */
-#define EOVERFLOW 92 /* Value too large for defined data type */
-#define EBADFD 93 /* File descriptor in bad state */
-#define ECHRNG 94 /* Channel number out of range */
-#define EL2NSYNC 95 /* Level 2 not synchronized */
-#define EL3HLT 96 /* Level 3 halted */
-#define EL3RST 97 /* Level 3 reset */
-#define ELNRNG 98 /* Link number out of range */
-#define EUNATCH 99 /* Protocol driver not attached */
-#define ENOCSI 100 /* No CSI structure available */
-#define EL2HLT 101 /* Level 2 halted */
-#define EBADE 102 /* Invalid exchange */
-#define EBADR 103 /* Invalid request descriptor */
-#define EXFULL 104 /* Exchange full */
-#define ENOANO 105 /* No anode */
-#define EBADRQC 106 /* Invalid request code */
-#define EBADSLT 107 /* Invalid slot */
-#define EDEADLOCK 108 /* File locking deadlock error */
-#define EBFONT 109 /* Bad font file format */
-#define ELIBEXEC 110 /* Cannot exec a shared library directly */
-#define ENODATA 111 /* No data available */
-#define ELIBBAD 112 /* Accessing a corrupted shared library */
-#define ENOPKG 113 /* Package not installed */
-#define ELIBACC 114 /* Can not access a needed shared library */
-#define ENOTUNIQ 115 /* Name not unique on network */
-#define ERESTART 116 /* Interrupted syscall should be restarted */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EILSEQ 122 /* Illegal byte sequence */
-#define ELIBMAX 123 /* Atmpt to link in too many shared libs */
-#define ELIBSCN 124 /* .lib section in a.out corrupted */
-
-#define ENOMEDIUM 125 /* No medium found */
-#define EMEDIUMTYPE 126 /* Wrong medium type */
-#define ECANCELED 127 /* Operation Cancelled */
-#define ENOKEY 128 /* Required key not available */
-#define EKEYEXPIRED 129 /* Key has expired */
-#define EKEYREVOKED 130 /* Key has been revoked */
-#define EKEYREJECTED 131 /* Key was rejected by service */
-
-/* for robust mutexes */
-#define EOWNERDEAD 132 /* Owner died */
-#define ENOTRECOVERABLE 133 /* State not recoverable */
-
-#endif
+++ /dev/null
-#ifndef _SPARC64_ESTATE_H
-#define _SPARC64_ESTATE_H
-
-/* UltraSPARC-III E-cache Error Enable */
-#define ESTATE_ERROR_FMT 0x0000000000040000 /* Force MTAG ECC */
-#define ESTATE_ERROR_FMESS 0x000000000003c000 /* Forced MTAG ECC val */
-#define ESTATE_ERROR_FMD 0x0000000000002000 /* Force DATA ECC */
-#define ESTATE_ERROR_FDECC 0x0000000000001ff0 /* Forced DATA ECC val */
-#define ESTATE_ERROR_UCEEN 0x0000000000000008 /* See below */
-#define ESTATE_ERROR_NCEEN 0x0000000000000002 /* See below */
-#define ESTATE_ERROR_CEEN 0x0000000000000001 /* See below */
-
-/* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache
- * errors 2) uncorrectable E-cache errors. Such events only occur on reads
- * of the E-cache by the local processor for: 1) data loads 2) instruction
- * fetches 3) atomic operations. Such events _cannot_ occur for: 1) merge
- * 2) writeback 2) copyout. The AFSR bits associated with these traps are
- * UCC and UCU.
- */
-
-/* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps
- * for uncorrectable ECC errors and system errors.
- *
- * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT,
- * or system bus BusERR:
- * 1) As the result of an instruction fetch, will generate instruction_access_error
- * 2) As the result of a load etc. will generate data_access_error.
- * 3) As the result of store merge completion, writeback, or copyout will
- * generate a disrupting ECC_error trap.
- * 4) As the result of such errors on instruction vector fetch can generate any
- * of the 3 trap types.
- *
- * The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE,
- * BERR, and TO.
- */
-
-/* CEEN enables the ECC_error trap for hardware corrected ECC errors. System bus
- * reads resulting in a hardware corrected data or MTAG ECC error will generate an
- * ECC_error disrupting trap with this bit enabled.
- *
- * This same trap will also be generated when a hardware corrected ECC error results
- * during store merge, writeback, and copyout operations.
- */
-
-/* In general, if the trap enable bits above are disabled the AFSR bits will still
- * log the events even though the trap will not be generated by the processor.
- */
-
-#endif /* _SPARC64_ESTATE_H */
+++ /dev/null
-#ifndef _SPARC_FB_H_
-#define _SPARC_FB_H_
-#include <linux/fb.h>
-#include <linux/fs.h>
-#include <asm/page.h>
-#include <asm/prom.h>
-
-static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
- unsigned long off)
-{
-#ifdef CONFIG_SPARC64
- vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
-#endif
-}
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
- struct device *dev = info->device;
- struct device_node *node;
-
- node = dev->archdata.prom_node;
- if (node &&
- node == of_console_device)
- return 1;
-
- return 0;
-}
-
-#endif /* _SPARC_FB_H_ */
+++ /dev/null
-#ifndef __LINUX_FBIO_H
-#define __LINUX_FBIO_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-
-/* Constants used for fbio SunOS compatibility */
-/* (C) 1996 Miguel de Icaza */
-
-/* Frame buffer types */
-#define FBTYPE_NOTYPE -1
-#define FBTYPE_SUN1BW 0 /* mono */
-#define FBTYPE_SUN1COLOR 1
-#define FBTYPE_SUN2BW 2
-#define FBTYPE_SUN2COLOR 3
-#define FBTYPE_SUN2GP 4
-#define FBTYPE_SUN5COLOR 5
-#define FBTYPE_SUN3COLOR 6
-#define FBTYPE_MEMCOLOR 7
-#define FBTYPE_SUN4COLOR 8
-
-#define FBTYPE_NOTSUN1 9
-#define FBTYPE_NOTSUN2 10
-#define FBTYPE_NOTSUN3 11
-
-#define FBTYPE_SUNFAST_COLOR 12 /* cg6 */
-#define FBTYPE_SUNROP_COLOR 13
-#define FBTYPE_SUNFB_VIDEO 14
-#define FBTYPE_SUNGIFB 15
-#define FBTYPE_SUNGPLAS 16
-#define FBTYPE_SUNGP3 17
-#define FBTYPE_SUNGT 18
-#define FBTYPE_SUNLEO 19 /* zx Leo card */
-#define FBTYPE_MDICOLOR 20 /* cg14 */
-#define FBTYPE_TCXCOLOR 21 /* SUNW,tcx card */
-
-#define FBTYPE_LASTPLUSONE 21 /* This is not last + 1 in fact... */
-
-/* Does not seem to be listed in the Sun file either */
-#define FBTYPE_CREATOR 22
-#define FBTYPE_PCI_IGA1682 23
-#define FBTYPE_P9100COLOR 24
-
-#define FBTYPE_PCI_GENERIC 1000
-#define FBTYPE_PCI_MACH64 1001
-
-/* fbio ioctls */
-/* Returned by FBIOGTYPE */
-struct fbtype {
- int fb_type; /* fb type, see above */
- int fb_height; /* pixels */
- int fb_width; /* pixels */
- int fb_depth;
- int fb_cmsize; /* color map entries */
- int fb_size; /* fb size in bytes */
-};
-#define FBIOGTYPE _IOR('F', 0, struct fbtype)
-
-struct fbcmap {
- int index; /* first element (0 origin) */
- int count;
- unsigned char __user *red;
- unsigned char __user *green;
- unsigned char __user *blue;
-};
-
-#ifdef __KERNEL__
-#define FBIOPUTCMAP_SPARC _IOW('F', 3, struct fbcmap)
-#define FBIOGETCMAP_SPARC _IOW('F', 4, struct fbcmap)
-#else
-#define FBIOPUTCMAP _IOW('F', 3, struct fbcmap)
-#define FBIOGETCMAP _IOW('F', 4, struct fbcmap)
-#endif
-
-/* # of device specific values */
-#define FB_ATTR_NDEVSPECIFIC 8
-/* # of possible emulations */
-#define FB_ATTR_NEMUTYPES 4
-
-struct fbsattr {
- int flags;
- int emu_type; /* -1 if none */
- int dev_specific[FB_ATTR_NDEVSPECIFIC];
-};
-
-struct fbgattr {
- int real_type; /* real frame buffer type */
- int owner; /* unknown */
- struct fbtype fbtype; /* real frame buffer fbtype */
- struct fbsattr sattr;
- int emu_types[FB_ATTR_NEMUTYPES]; /* supported emulations */
-};
-#define FBIOSATTR _IOW('F', 5, struct fbgattr) /* Unsupported: */
-#define FBIOGATTR _IOR('F', 6, struct fbgattr) /* supported */
-
-#define FBIOSVIDEO _IOW('F', 7, int)
-#define FBIOGVIDEO _IOR('F', 8, int)
-
-struct fbcursor {
- short set; /* what to set, choose from the list above */
- short enable; /* cursor on/off */
- struct fbcurpos pos; /* cursor position */
- struct fbcurpos hot; /* cursor hot spot */
- struct fbcmap cmap; /* color map info */
- struct fbcurpos size; /* cursor bit map size */
- char __user *image; /* cursor image bits */
- char __user *mask; /* cursor mask bits */
-};
-
-/* set/get cursor attributes/shape */
-#define FBIOSCURSOR _IOW('F', 24, struct fbcursor)
-#define FBIOGCURSOR _IOWR('F', 25, struct fbcursor)
-
-/* set/get cursor position */
-#define FBIOSCURPOS _IOW('F', 26, struct fbcurpos)
-#define FBIOGCURPOS _IOW('F', 27, struct fbcurpos)
-
-/* get max cursor size */
-#define FBIOGCURMAX _IOR('F', 28, struct fbcurpos)
-
-/* wid manipulation */
-struct fb_wid_alloc {
-#define FB_WID_SHARED_8 0
-#define FB_WID_SHARED_24 1
-#define FB_WID_DBL_8 2
-#define FB_WID_DBL_24 3
- __u32 wa_type;
- __s32 wa_index; /* Set on return */
- __u32 wa_count;
-};
-struct fb_wid_item {
- __u32 wi_type;
- __s32 wi_index;
- __u32 wi_attrs;
- __u32 wi_values[32];
-};
-struct fb_wid_list {
- __u32 wl_flags;
- __u32 wl_count;
- struct fb_wid_item *wl_list;
-};
-
-#define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc)
-#define FBIO_WID_FREE _IOW('F', 31, struct fb_wid_alloc)
-#define FBIO_WID_PUT _IOW('F', 32, struct fb_wid_list)
-#define FBIO_WID_GET _IOWR('F', 33, struct fb_wid_list)
-
-/* Creator ioctls */
-#define FFB_IOCTL ('F'<<8)
-#define FFB_SYS_INFO (FFB_IOCTL|80)
-#define FFB_CLUTREAD (FFB_IOCTL|81)
-#define FFB_CLUTPOST (FFB_IOCTL|82)
-#define FFB_SETDIAGMODE (FFB_IOCTL|83)
-#define FFB_GETMONITORID (FFB_IOCTL|84)
-#define FFB_GETVIDEOMODE (FFB_IOCTL|85)
-#define FFB_SETVIDEOMODE (FFB_IOCTL|86)
-#define FFB_SETSERVER (FFB_IOCTL|87)
-#define FFB_SETOVCTL (FFB_IOCTL|88)
-#define FFB_GETOVCTL (FFB_IOCTL|89)
-#define FFB_GETSAXNUM (FFB_IOCTL|90)
-#define FFB_FBDEBUG (FFB_IOCTL|91)
-
-/* Cg14 ioctls */
-#define MDI_IOCTL ('M'<<8)
-#define MDI_RESET (MDI_IOCTL|1)
-#define MDI_GET_CFGINFO (MDI_IOCTL|2)
-#define MDI_SET_PIXELMODE (MDI_IOCTL|3)
-# define MDI_32_PIX 32
-# define MDI_16_PIX 16
-# define MDI_8_PIX 8
-
-struct mdi_cfginfo {
- int mdi_ncluts; /* Number of implemented CLUTs in this MDI */
- int mdi_type; /* FBTYPE name */
- int mdi_height; /* height */
- int mdi_width; /* widht */
- int mdi_size; /* available ram */
- int mdi_mode; /* 8bpp, 16bpp or 32bpp */
- int mdi_pixfreq; /* pixel clock (from PROM) */
-};
-
-/* SparcLinux specific ioctl for the MDI, should be replaced for
- * the SET_XLUT/SET_CLUTn ioctls instead
- */
-#define MDI_CLEAR_XLUT (MDI_IOCTL|9)
-
-/* leo & ffb ioctls */
-struct fb_clut_alloc {
- __u32 clutid; /* Set on return */
- __u32 flag;
- __u32 index;
-};
-
-struct fb_clut {
-#define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
- __u32 flag;
- __u32 clutid;
- __u32 offset;
- __u32 count;
- char * red;
- char * green;
- char * blue;
-};
-
-struct fb_clut32 {
- __u32 flag;
- __u32 clutid;
- __u32 offset;
- __u32 count;
- __u32 red;
- __u32 green;
- __u32 blue;
-};
-
-#define LEO_CLUTALLOC _IOWR('L', 53, struct fb_clut_alloc)
-#define LEO_CLUTFREE _IOW('L', 54, struct fb_clut_alloc)
-#define LEO_CLUTREAD _IOW('L', 55, struct fb_clut)
-#define LEO_CLUTPOST _IOW('L', 56, struct fb_clut)
-#define LEO_SETGAMMA _IOW('L', 68, int) /* Not yet implemented */
-#define LEO_GETGAMMA _IOR('L', 69, int) /* Not yet implemented */
-
-#ifdef __KERNEL__
-/* Addresses on the fd of a cgsix that are mappable */
-#define CG6_FBC 0x70000000
-#define CG6_TEC 0x70001000
-#define CG6_BTREGS 0x70002000
-#define CG6_FHC 0x70004000
-#define CG6_THC 0x70005000
-#define CG6_ROM 0x70006000
-#define CG6_RAM 0x70016000
-#define CG6_DHC 0x80000000
-
-#define CG3_MMAP_OFFSET 0x4000000
-
-/* Addresses on the fd of a tcx that are mappable */
-#define TCX_RAM8BIT 0x00000000
-#define TCX_RAM24BIT 0x01000000
-#define TCX_UNK3 0x10000000
-#define TCX_UNK4 0x20000000
-#define TCX_CONTROLPLANE 0x28000000
-#define TCX_UNK6 0x30000000
-#define TCX_UNK7 0x38000000
-#define TCX_TEC 0x70000000
-#define TCX_BTREGS 0x70002000
-#define TCX_THC 0x70004000
-#define TCX_DHC 0x70008000
-#define TCX_ALT 0x7000a000
-#define TCX_SYNC 0x7000e000
-#define TCX_UNK2 0x70010000
-
-/* CG14 definitions */
-
-/* Offsets into the OBIO space: */
-#define CG14_REGS 0 /* registers */
-#define CG14_CURSORREGS 0x1000 /* cursor registers */
-#define CG14_DACREGS 0x2000 /* DAC registers */
-#define CG14_XLUT 0x3000 /* X Look Up Table -- ??? */
-#define CG14_CLUT1 0x4000 /* Color Look Up Table */
-#define CG14_CLUT2 0x5000 /* Color Look Up Table */
-#define CG14_CLUT3 0x6000 /* Color Look Up Table */
-#define CG14_AUTO 0xf000
-
-#endif /* KERNEL */
-
-/* These are exported to userland for applications to use */
-/* Mappable offsets for the cg14: control registers */
-#define MDI_DIRECT_MAP 0x10000000
-#define MDI_CTLREG_MAP 0x20000000
-#define MDI_CURSOR_MAP 0x30000000
-#define MDI_SHDW_VRT_MAP 0x40000000
-
-/* Mappable offsets for the cg14: frame buffer resolutions */
-/* 32 bits */
-#define MDI_CHUNKY_XBGR_MAP 0x50000000
-#define MDI_CHUNKY_BGR_MAP 0x60000000
-
-/* 16 bits */
-#define MDI_PLANAR_X16_MAP 0x70000000
-#define MDI_PLANAR_C16_MAP 0x80000000
-
-/* 8 bit is done as CG3 MMAP offset */
-/* 32 bits, planar */
-#define MDI_PLANAR_X32_MAP 0x90000000
-#define MDI_PLANAR_B32_MAP 0xa0000000
-#define MDI_PLANAR_G32_MAP 0xb0000000
-#define MDI_PLANAR_R32_MAP 0xc0000000
-
-/* Mappable offsets on leo */
-#define LEO_SS0_MAP 0x00000000
-#define LEO_LC_SS0_USR_MAP 0x00800000
-#define LEO_LD_SS0_MAP 0x00801000
-#define LEO_LX_CURSOR_MAP 0x00802000
-#define LEO_SS1_MAP 0x00803000
-#define LEO_LC_SS1_USR_MAP 0x01003000
-#define LEO_LD_SS1_MAP 0x01004000
-#define LEO_UNK_MAP 0x01005000
-#define LEO_LX_KRN_MAP 0x01006000
-#define LEO_LC_SS0_KRN_MAP 0x01007000
-#define LEO_LC_SS1_KRN_MAP 0x01008000
-#define LEO_LD_GBL_MAP 0x01009000
-#define LEO_UNK2_MAP 0x0100a000
-
-#ifdef __KERNEL__
-struct fbcmap32 {
- int index; /* first element (0 origin) */
- int count;
- u32 red;
- u32 green;
- u32 blue;
-};
-
-#define FBIOPUTCMAP32 _IOW('F', 3, struct fbcmap32)
-#define FBIOGETCMAP32 _IOW('F', 4, struct fbcmap32)
-
-struct fbcursor32 {
- short set; /* what to set, choose from the list above */
- short enable; /* cursor on/off */
- struct fbcurpos pos; /* cursor position */
- struct fbcurpos hot; /* cursor hot spot */
- struct fbcmap32 cmap; /* color map info */
- struct fbcurpos size; /* cursor bit map size */
- u32 image; /* cursor image bits */
- u32 mask; /* cursor mask bits */
-};
-
-#define FBIOSCURSOR32 _IOW('F', 24, struct fbcursor32)
-#define FBIOGCURSOR32 _IOW('F', 25, struct fbcursor32)
-#endif
-
-#endif /* __LINUX_FBIO_H */
+++ /dev/null
-#ifndef _SPARC_FCNTL_H
-#define _SPARC_FCNTL_H
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
- located on an ext2 file system */
-#define O_APPEND 0x0008
-#define FASYNC 0x0040 /* fcntl, for BSD compatibility */
-#define O_CREAT 0x0200 /* not fcntl */
-#define O_TRUNC 0x0400 /* not fcntl */
-#define O_EXCL 0x0800 /* not fcntl */
-#define O_SYNC 0x2000
-#define O_NONBLOCK 0x4000
-#if defined(__sparc__) && defined(__arch64__)
-#define O_NDELAY 0x0004
-#else
-#define O_NDELAY (0x0004 | O_NONBLOCK)
-#endif
-#define O_NOCTTY 0x8000 /* not fcntl */
-#define O_LARGEFILE 0x40000
-#define O_DIRECT 0x100000 /* direct disk access hint */
-#define O_NOATIME 0x200000
-#define O_CLOEXEC 0x400000
-
-#define F_GETOWN 5 /* for sockets. */
-#define F_SETOWN 6 /* for sockets. */
-#define F_GETLK 7
-#define F_SETLK 8
-#define F_SETLKW 9
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK 1
-#define F_WRLCK 2
-#define F_UNLCK 3
-
-#define __ARCH_FLOCK_PAD short __unused;
-#define __ARCH_FLOCK64_PAD short __unused;
-
-#include <asm-generic/fcntl.h>
-
-#endif
+++ /dev/null
-/*
- * fhc.h: Structures for central/fhc pseudo driver on Sunfire/Starfire/Wildfire.
- *
- * Copyright (C) 1997, 1999 David S. Miller (davem@redhat.com)
- */
-
-#ifndef _SPARC64_FHC_H
-#define _SPARC64_FHC_H
-
-#include <linux/timer.h>
-
-#include <asm/oplib.h>
-#include <asm/prom.h>
-#include <asm/upa.h>
-
-struct linux_fhc;
-
-/* Clock board register offsets. */
-#define CLOCK_CTRL 0x00UL /* Main control */
-#define CLOCK_STAT1 0x10UL /* Status one */
-#define CLOCK_STAT2 0x20UL /* Status two */
-#define CLOCK_PWRSTAT 0x30UL /* Power status */
-#define CLOCK_PWRPRES 0x40UL /* Power presence */
-#define CLOCK_TEMP 0x50UL /* Temperature */
-#define CLOCK_IRQDIAG 0x60UL /* IRQ diagnostics */
-#define CLOCK_PWRSTAT2 0x70UL /* Power status two */
-
-#define CLOCK_CTRL_LLED 0x04 /* Left LED, 0 == on */
-#define CLOCK_CTRL_MLED 0x02 /* Mid LED, 1 == on */
-#define CLOCK_CTRL_RLED 0x01 /* RIght LED, 1 == on */
-
-struct linux_central {
- struct linux_fhc *child;
- unsigned long cfreg;
- unsigned long clkregs;
- unsigned long clkver;
- int slots;
- struct device_node *prom_node;
-
- struct linux_prom_ranges central_ranges[PROMREG_MAX];
- int num_central_ranges;
-};
-
-/* Firehose controller register offsets */
-struct fhc_regs {
- unsigned long pregs; /* FHC internal regs */
-#define FHC_PREGS_ID 0x00UL /* FHC ID */
-#define FHC_ID_VERS 0xf0000000 /* Version of this FHC */
-#define FHC_ID_PARTID 0x0ffff000 /* Part ID code (0x0f9f == FHC) */
-#define FHC_ID_MANUF 0x0000007e /* Manufacturer (0x3e == SUN's JEDEC)*/
-#define FHC_ID_RESV 0x00000001 /* Read as one */
-#define FHC_PREGS_RCS 0x10UL /* FHC Reset Control/Status Register */
-#define FHC_RCS_POR 0x80000000 /* Last reset was a power cycle */
-#define FHC_RCS_SPOR 0x40000000 /* Last reset was sw power on reset */
-#define FHC_RCS_SXIR 0x20000000 /* Last reset was sw XIR reset */
-#define FHC_RCS_BPOR 0x10000000 /* Last reset was due to POR button */
-#define FHC_RCS_BXIR 0x08000000 /* Last reset was due to XIR button */
-#define FHC_RCS_WEVENT 0x04000000 /* CPU reset was due to wakeup event */
-#define FHC_RCS_CFATAL 0x02000000 /* Centerplane Fatal Error signalled */
-#define FHC_RCS_FENAB 0x01000000 /* Fatal errors elicit system reset */
-#define FHC_PREGS_CTRL 0x20UL /* FHC Control Register */
-#define FHC_CONTROL_ICS 0x00100000 /* Ignore Centerplane Signals */
-#define FHC_CONTROL_FRST 0x00080000 /* Fatal Error Reset Enable */
-#define FHC_CONTROL_LFAT 0x00040000 /* AC/DC signalled a local error */
-#define FHC_CONTROL_SLINE 0x00010000 /* Firmware Synchronization Line */
-#define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
-#define FHC_CONTROL_POFF 0x00004000 /* AC/DC Controller PLL Disable */
-#define FHC_CONTROL_FOFF 0x00002000 /* FHC Controller PLL Disable */
-#define FHC_CONTROL_AOFF 0x00001000 /* CPU A SRAM/SBD Low Power Mode */
-#define FHC_CONTROL_BOFF 0x00000800 /* CPU B SRAM/SBD Low Power Mode */
-#define FHC_CONTROL_PSOFF 0x00000400 /* Turns off this FHC's power supply */
-#define FHC_CONTROL_IXIST 0x00000200 /* 0=FHC tells clock board it exists */
-#define FHC_CONTROL_XMSTR 0x00000100 /* 1=Causes this FHC to be XIR master*/
-#define FHC_CONTROL_LLED 0x00000040 /* 0=Left LED ON */
-#define FHC_CONTROL_MLED 0x00000020 /* 1=Middle LED ON */
-#define FHC_CONTROL_RLED 0x00000010 /* 1=Right LED */
-#define FHC_CONTROL_BPINS 0x00000003 /* Spare Bidirectional Pins */
-#define FHC_PREGS_BSR 0x30UL /* FHC Board Status Register */
-#define FHC_BSR_DA64 0x00040000 /* Port A: 0=128bit 1=64bit data path */
-#define FHC_BSR_DB64 0x00020000 /* Port B: 0=128bit 1=64bit data path */
-#define FHC_BSR_BID 0x0001e000 /* Board ID */
-#define FHC_BSR_SA 0x00001c00 /* Port A UPA Speed (from the pins) */
-#define FHC_BSR_SB 0x00000380 /* Port B UPA Speed (from the pins) */
-#define FHC_BSR_NDIAG 0x00000040 /* Not in Diag Mode */
-#define FHC_BSR_NTBED 0x00000020 /* Not in TestBED Mode */
-#define FHC_BSR_NIA 0x0000001c /* Jumper, bit 18 in PROM space */
-#define FHC_BSR_SI 0x00000001 /* Spare input pin value */
-#define FHC_PREGS_ECC 0x40UL /* FHC ECC Control Register (16 bits) */
-#define FHC_PREGS_JCTRL 0xf0UL /* FHC JTAG Control Register */
-#define FHC_JTAG_CTRL_MENAB 0x80000000 /* Indicates this is JTAG Master */
-#define FHC_JTAG_CTRL_MNONE 0x40000000 /* Indicates no JTAG Master present */
-#define FHC_PREGS_JCMD 0x100UL /* FHC JTAG Command Register */
- unsigned long ireg; /* FHC IGN reg */
-#define FHC_IREG_IGN 0x00UL /* This FHC's IGN */
- unsigned long ffregs; /* FHC fanfail regs */
-#define FHC_FFREGS_IMAP 0x00UL /* FHC Fanfail IMAP */
-#define FHC_FFREGS_ICLR 0x10UL /* FHC Fanfail ICLR */
- unsigned long sregs; /* FHC system regs */
-#define FHC_SREGS_IMAP 0x00UL /* FHC System IMAP */
-#define FHC_SREGS_ICLR 0x10UL /* FHC System ICLR */
- unsigned long uregs; /* FHC uart regs */
-#define FHC_UREGS_IMAP 0x00UL /* FHC Uart IMAP */
-#define FHC_UREGS_ICLR 0x10UL /* FHC Uart ICLR */
- unsigned long tregs; /* FHC TOD regs */
-#define FHC_TREGS_IMAP 0x00UL /* FHC TOD IMAP */
-#define FHC_TREGS_ICLR 0x10UL /* FHC TOD ICLR */
-};
-
-struct linux_fhc {
- struct linux_fhc *next;
- struct linux_central *parent; /* NULL if not central FHC */
- struct fhc_regs fhc_regs;
- int board;
- int jtag_master;
- struct device_node *prom_node;
-
- struct linux_prom_ranges fhc_ranges[PROMREG_MAX];
- int num_fhc_ranges;
-};
-
-#endif /* !(_SPARC64_FHC_H) */
+++ /dev/null
-/*
- * fixmap.h: compile-time virtual memory allocation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998 Ingo Molnar
- *
- * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
- */
-
-#ifndef _ASM_FIXMAP_H
-#define _ASM_FIXMAP_H
-
-#include <linux/kernel.h>
-#include <asm/page.h>
-#ifdef CONFIG_HIGHMEM
-#include <linux/threads.h>
-#include <asm/kmap_types.h>
-#endif
-
-/*
- * Here we define all the compile-time 'special' virtual
- * addresses. The point is to have a constant address at
- * compile time, but to set the physical address only
- * in the boot process. We allocate these special addresses
- * from the top of unused virtual memory (0xfd000000 - 1 page) backwards.
- * Also this lets us do fail-safe vmalloc(), we
- * can guarantee that these special addresses and
- * vmalloc()-ed addresses never overlap.
- *
- * these 'compile-time allocated' memory buffers are
- * fixed-size 4k pages. (or larger if used with an increment
- * highger than 1) use fixmap_set(idx,phys) to associate
- * physical memory with fixmap indices.
- *
- * TLB entries of such buffers will not be flushed across
- * task switches.
- */
-
-/*
- * on UP currently we will have no trace of the fixmap mechanism,
- * no page table allocations, etc. This might change in the
- * future, say framebuffers for the console driver(s) could be
- * fix-mapped?
- */
-enum fixed_addresses {
- FIX_HOLE,
-#ifdef CONFIG_HIGHMEM
- FIX_KMAP_BEGIN,
- FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
-#endif
- __end_of_fixed_addresses
-};
-
-extern void __set_fixmap (enum fixed_addresses idx,
- unsigned long phys, pgprot_t flags);
-
-#define set_fixmap(idx, phys) \
- __set_fixmap(idx, phys, PAGE_KERNEL)
-/*
- * Some hardware wants to get fixmapped without caching.
- */
-#define set_fixmap_nocache(idx, phys) \
- __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
-/*
- * used by vmalloc.c.
- *
- * Leave one empty page between IO pages at 0xfd000000 and
- * the start of the fixmap.
- */
-#define FIXADDR_TOP (0xfcfff000UL)
-#define FIXADDR_SIZE ((__end_of_fixed_addresses) << PAGE_SHIFT)
-#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
-
-#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static inline unsigned long fix_to_virt(const unsigned int idx)
-{
- /*
- * this branch gets completely eliminated after inlining,
- * except when someone tries to use fixaddr indices in an
- * illegal way. (such as mixing up address types or using
- * out-of-range indices).
- *
- * If it doesn't get removed, the linker will complain
- * loudly with a reasonably clear error message..
- */
- if (idx >= __end_of_fixed_addresses)
- __this_fixmap_does_not_exist();
-
- return __fix_to_virt(idx);
-}
-
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
- BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
- return __virt_to_fix(vaddr);
-}
-
-#endif
+++ /dev/null
-#ifndef ___ASM_SPARC_FLOPPY_H
-#define ___ASM_SPARC_FLOPPY_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/floppy_64.h>
-#else
-#include <asm-sparc/floppy_32.h>
-#endif
-#endif
+++ /dev/null
-/* asm-sparc/floppy.h: Sparc specific parts of the Floppy driver.
- *
- * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
- */
-
-#ifndef __ASM_SPARC_FLOPPY_H
-#define __ASM_SPARC_FLOPPY_H
-
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/system.h>
-#include <asm/idprom.h>
-#include <asm/machines.h>
-#include <asm/oplib.h>
-#include <asm/auxio.h>
-#include <asm/irq.h>
-
-/* We don't need no stinkin' I/O port allocation crap. */
-#undef release_region
-#undef request_region
-#define release_region(X, Y) do { } while(0)
-#define request_region(X, Y, Z) (1)
-
-/* References:
- * 1) Netbsd Sun floppy driver.
- * 2) NCR 82077 controller manual
- * 3) Intel 82077 controller manual
- */
-struct sun_flpy_controller {
- volatile unsigned char status_82072; /* Main Status reg. */
-#define dcr_82072 status_82072 /* Digital Control reg. */
-#define status1_82077 status_82072 /* Auxiliary Status reg. 1 */
-
- volatile unsigned char data_82072; /* Data fifo. */
-#define status2_82077 data_82072 /* Auxiliary Status reg. 2 */
-
- volatile unsigned char dor_82077; /* Digital Output reg. */
- volatile unsigned char tapectl_82077; /* What the? Tape control reg? */
-
- volatile unsigned char status_82077; /* Main Status Register. */
-#define drs_82077 status_82077 /* Digital Rate Select reg. */
-
- volatile unsigned char data_82077; /* Data fifo. */
- volatile unsigned char ___unused;
- volatile unsigned char dir_82077; /* Digital Input reg. */
-#define dcr_82077 dir_82077 /* Config Control reg. */
-};
-
-/* You'll only ever find one controller on a SparcStation anyways. */
-static struct sun_flpy_controller *sun_fdc = NULL;
-extern volatile unsigned char *fdc_status;
-
-struct sun_floppy_ops {
- unsigned char (*fd_inb)(int port);
- void (*fd_outb)(unsigned char value, int port);
-};
-
-static struct sun_floppy_ops sun_fdops;
-
-#define fd_inb(port) sun_fdops.fd_inb(port)
-#define fd_outb(value,port) sun_fdops.fd_outb(value,port)
-#define fd_enable_dma() sun_fd_enable_dma()
-#define fd_disable_dma() sun_fd_disable_dma()
-#define fd_request_dma() (0) /* nothing... */
-#define fd_free_dma() /* nothing... */
-#define fd_clear_dma_ff() /* nothing... */
-#define fd_set_dma_mode(mode) sun_fd_set_dma_mode(mode)
-#define fd_set_dma_addr(addr) sun_fd_set_dma_addr(addr)
-#define fd_set_dma_count(count) sun_fd_set_dma_count(count)
-#define fd_enable_irq() /* nothing... */
-#define fd_disable_irq() /* nothing... */
-#define fd_cacheflush(addr, size) /* nothing... */
-#define fd_request_irq() sun_fd_request_irq()
-#define fd_free_irq() /* nothing... */
-#if 0 /* P3: added by Alain, these cause a MMU corruption. 19960524 XXX */
-#define fd_dma_mem_alloc(size) ((unsigned long) vmalloc(size))
-#define fd_dma_mem_free(addr,size) (vfree((void *)(addr)))
-#endif
-
-/* XXX This isn't really correct. XXX */
-#define get_dma_residue(x) (0)
-
-#define FLOPPY0_TYPE 4
-#define FLOPPY1_TYPE 0
-
-/* Super paranoid... */
-#undef HAVE_DISABLE_HLT
-
-/* Here is where we catch the floppy driver trying to initialize,
- * therefore this is where we call the PROM device tree probing
- * routine etc. on the Sparc.
- */
-#define FDC1 sun_floppy_init()
-
-#define N_FDC 1
-#define N_DRIVE 8
-
-/* No 64k boundary crossing problems on the Sparc. */
-#define CROSS_64KB(a,s) (0)
-
-/* Routines unique to each controller type on a Sun. */
-static void sun_set_dor(unsigned char value, int fdc_82077)
-{
- if (sparc_cpu_model == sun4c) {
- unsigned int bits = 0;
- if (value & 0x10)
- bits |= AUXIO_FLPY_DSEL;
- if ((value & 0x80) == 0)
- bits |= AUXIO_FLPY_EJCT;
- set_auxio(bits, (~bits) & (AUXIO_FLPY_DSEL|AUXIO_FLPY_EJCT));
- }
- if (fdc_82077) {
- sun_fdc->dor_82077 = value;
- }
-}
-
-static unsigned char sun_read_dir(void)
-{
- if (sparc_cpu_model == sun4c)
- return (get_auxio() & AUXIO_FLPY_DCHG) ? 0x80 : 0;
- else
- return sun_fdc->dir_82077;
-}
-
-static unsigned char sun_82072_fd_inb(int port)
-{
- udelay(5);
- switch(port & 7) {
- default:
- printk("floppy: Asked to read unknown port %d\n", port);
- panic("floppy: Port bolixed.");
- case 4: /* FD_STATUS */
- return sun_fdc->status_82072 & ~STATUS_DMA;
- case 5: /* FD_DATA */
- return sun_fdc->data_82072;
- case 7: /* FD_DIR */
- return sun_read_dir();
- };
- panic("sun_82072_fd_inb: How did I get here?");
-}
-
-static void sun_82072_fd_outb(unsigned char value, int port)
-{
- udelay(5);
- switch(port & 7) {
- default:
- printk("floppy: Asked to write to unknown port %d\n", port);
- panic("floppy: Port bolixed.");
- case 2: /* FD_DOR */
- sun_set_dor(value, 0);
- break;
- case 5: /* FD_DATA */
- sun_fdc->data_82072 = value;
- break;
- case 7: /* FD_DCR */
- sun_fdc->dcr_82072 = value;
- break;
- case 4: /* FD_STATUS */
- sun_fdc->status_82072 = value;
- break;
- };
- return;
-}
-
-static unsigned char sun_82077_fd_inb(int port)
-{
- udelay(5);
- switch(port & 7) {
- default:
- printk("floppy: Asked to read unknown port %d\n", port);
- panic("floppy: Port bolixed.");
- case 0: /* FD_STATUS_0 */
- return sun_fdc->status1_82077;
- case 1: /* FD_STATUS_1 */
- return sun_fdc->status2_82077;
- case 2: /* FD_DOR */
- return sun_fdc->dor_82077;
- case 3: /* FD_TDR */
- return sun_fdc->tapectl_82077;
- case 4: /* FD_STATUS */
- return sun_fdc->status_82077 & ~STATUS_DMA;
- case 5: /* FD_DATA */
- return sun_fdc->data_82077;
- case 7: /* FD_DIR */
- return sun_read_dir();
- };
- panic("sun_82077_fd_inb: How did I get here?");
-}
-
-static void sun_82077_fd_outb(unsigned char value, int port)
-{
- udelay(5);
- switch(port & 7) {
- default:
- printk("floppy: Asked to write to unknown port %d\n", port);
- panic("floppy: Port bolixed.");
- case 2: /* FD_DOR */
- sun_set_dor(value, 1);
- break;
- case 5: /* FD_DATA */
- sun_fdc->data_82077 = value;
- break;
- case 7: /* FD_DCR */
- sun_fdc->dcr_82077 = value;
- break;
- case 4: /* FD_STATUS */
- sun_fdc->status_82077 = value;
- break;
- case 3: /* FD_TDR */
- sun_fdc->tapectl_82077 = value;
- break;
- };
- return;
-}
-
-/* For pseudo-dma (Sun floppy drives have no real DMA available to
- * them so we must eat the data fifo bytes directly ourselves) we have
- * three state variables. doing_pdma tells our inline low-level
- * assembly floppy interrupt entry point whether it should sit and eat
- * bytes from the fifo or just transfer control up to the higher level
- * floppy interrupt c-code. I tried very hard but I could not get the
- * pseudo-dma to work in c-code without getting many overruns and
- * underruns. If non-zero, doing_pdma encodes the direction of
- * the transfer for debugging. 1=read 2=write
- */
-extern char *pdma_vaddr;
-extern unsigned long pdma_size;
-extern volatile int doing_pdma;
-
-/* This is software state */
-extern char *pdma_base;
-extern unsigned long pdma_areasize;
-
-/* Common routines to all controller types on the Sparc. */
-static inline void virtual_dma_init(void)
-{
- /* nothing... */
-}
-
-static inline void sun_fd_disable_dma(void)
-{
- doing_pdma = 0;
- if (pdma_base) {
- mmu_unlockarea(pdma_base, pdma_areasize);
- pdma_base = NULL;
- }
-}
-
-static inline void sun_fd_set_dma_mode(int mode)
-{
- switch(mode) {
- case DMA_MODE_READ:
- doing_pdma = 1;
- break;
- case DMA_MODE_WRITE:
- doing_pdma = 2;
- break;
- default:
- printk("Unknown dma mode %d\n", mode);
- panic("floppy: Giving up...");
- }
-}
-
-static inline void sun_fd_set_dma_addr(char *buffer)
-{
- pdma_vaddr = buffer;
-}
-
-static inline void sun_fd_set_dma_count(int length)
-{
- pdma_size = length;
-}
-
-static inline void sun_fd_enable_dma(void)
-{
- pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size);
- pdma_base = pdma_vaddr;
- pdma_areasize = pdma_size;
-}
-
-/* Our low-level entry point in arch/sparc/kernel/entry.S */
-extern int sparc_floppy_request_irq(int irq, unsigned long flags,
- irq_handler_t irq_handler);
-
-static int sun_fd_request_irq(void)
-{
- static int once = 0;
- int error;
-
- if(!once) {
- once = 1;
- error = sparc_floppy_request_irq(FLOPPY_IRQ,
- IRQF_DISABLED,
- floppy_interrupt);
- return ((error == 0) ? 0 : -1);
- } else return 0;
-}
-
-static struct linux_prom_registers fd_regs[2];
-
-static int sun_floppy_init(void)
-{
- char state[128];
- int tnode, fd_node, num_regs;
- struct resource r;
-
- use_virtual_dma = 1;
-
- FLOPPY_IRQ = 11;
- /* Forget it if we aren't on a machine that could possibly
- * ever have a floppy drive.
- */
- if((sparc_cpu_model != sun4c && sparc_cpu_model != sun4m) ||
- ((idprom->id_machtype == (SM_SUN4C | SM_4C_SLC)) ||
- (idprom->id_machtype == (SM_SUN4C | SM_4C_ELC)))) {
- /* We certainly don't have a floppy controller. */
- goto no_sun_fdc;
- }
- /* Well, try to find one. */
- tnode = prom_getchild(prom_root_node);
- fd_node = prom_searchsiblings(tnode, "obio");
- if(fd_node != 0) {
- tnode = prom_getchild(fd_node);
- fd_node = prom_searchsiblings(tnode, "SUNW,fdtwo");
- } else {
- fd_node = prom_searchsiblings(tnode, "fd");
- }
- if(fd_node == 0) {
- goto no_sun_fdc;
- }
-
- /* The sun4m lets us know if the controller is actually usable. */
- if(sparc_cpu_model == sun4m &&
- prom_getproperty(fd_node, "status", state, sizeof(state)) != -1) {
- if(!strcmp(state, "disabled")) {
- goto no_sun_fdc;
- }
- }
- num_regs = prom_getproperty(fd_node, "reg", (char *) fd_regs, sizeof(fd_regs));
- num_regs = (num_regs / sizeof(fd_regs[0]));
- prom_apply_obio_ranges(fd_regs, num_regs);
- memset(&r, 0, sizeof(r));
- r.flags = fd_regs[0].which_io;
- r.start = fd_regs[0].phys_addr;
- sun_fdc = (struct sun_flpy_controller *)
- sbus_ioremap(&r, 0, fd_regs[0].reg_size, "floppy");
-
- /* Last minute sanity check... */
- if(sun_fdc->status_82072 == 0xff) {
- sun_fdc = NULL;
- goto no_sun_fdc;
- }
-
- sun_fdops.fd_inb = sun_82077_fd_inb;
- sun_fdops.fd_outb = sun_82077_fd_outb;
- fdc_status = &sun_fdc->status_82077;
-
- if (sun_fdc->dor_82077 == 0x80) {
- sun_fdc->dor_82077 = 0x02;
- if (sun_fdc->dor_82077 == 0x80) {
- sun_fdops.fd_inb = sun_82072_fd_inb;
- sun_fdops.fd_outb = sun_82072_fd_outb;
- fdc_status = &sun_fdc->status_82072;
- }
- }
-
- /* Success... */
- allowed_drive_mask = 0x01;
- return (int) sun_fdc;
-
-no_sun_fdc:
- return -1;
-}
-
-static int sparc_eject(void)
-{
- set_dor(0x00, 0xff, 0x90);
- udelay(500);
- set_dor(0x00, 0x6f, 0x00);
- udelay(500);
- return 0;
-}
-
-#define fd_eject(drive) sparc_eject()
-
-#define EXTRA_FLOPPY_PARAMS
-
-#endif /* !(__ASM_SPARC_FLOPPY_H) */
+++ /dev/null
-/* floppy.h: Sparc specific parts of the Floppy driver.
- *
- * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
- * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- *
- * Ultra/PCI support added: Sep 1997 Eddie C. Dost (ecd@skynet.be)
- */
-
-#ifndef __ASM_SPARC64_FLOPPY_H
-#define __ASM_SPARC64_FLOPPY_H
-
-#include <linux/init.h>
-#include <linux/pci.h>
-
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/system.h>
-#include <asm/idprom.h>
-#include <asm/oplib.h>
-#include <asm/auxio.h>
-#include <asm/sbus.h>
-#include <asm/irq.h>
-
-
-/*
- * Define this to enable exchanging drive 0 and 1 if only drive 1 is
- * probed on PCI machines.
- */
-#undef PCI_FDC_SWAP_DRIVES
-
-
-/* References:
- * 1) Netbsd Sun floppy driver.
- * 2) NCR 82077 controller manual
- * 3) Intel 82077 controller manual
- */
-struct sun_flpy_controller {
- volatile unsigned char status1_82077; /* Auxiliary Status reg. 1 */
- volatile unsigned char status2_82077; /* Auxiliary Status reg. 2 */
- volatile unsigned char dor_82077; /* Digital Output reg. */
- volatile unsigned char tapectl_82077; /* Tape Control reg */
- volatile unsigned char status_82077; /* Main Status Register. */
-#define drs_82077 status_82077 /* Digital Rate Select reg. */
- volatile unsigned char data_82077; /* Data fifo. */
- volatile unsigned char ___unused;
- volatile unsigned char dir_82077; /* Digital Input reg. */
-#define dcr_82077 dir_82077 /* Config Control reg. */
-};
-
-/* You'll only ever find one controller on an Ultra anyways. */
-static struct sun_flpy_controller *sun_fdc = (struct sun_flpy_controller *)-1;
-unsigned long fdc_status;
-static struct sbus_dev *floppy_sdev = NULL;
-
-struct sun_floppy_ops {
- unsigned char (*fd_inb) (unsigned long port);
- void (*fd_outb) (unsigned char value, unsigned long port);
- void (*fd_enable_dma) (void);
- void (*fd_disable_dma) (void);
- void (*fd_set_dma_mode) (int);
- void (*fd_set_dma_addr) (char *);
- void (*fd_set_dma_count) (int);
- unsigned int (*get_dma_residue) (void);
- int (*fd_request_irq) (void);
- void (*fd_free_irq) (void);
- int (*fd_eject) (int);
-};
-
-static struct sun_floppy_ops sun_fdops;
-
-#define fd_inb(port) sun_fdops.fd_inb(port)
-#define fd_outb(value,port) sun_fdops.fd_outb(value,port)
-#define fd_enable_dma() sun_fdops.fd_enable_dma()
-#define fd_disable_dma() sun_fdops.fd_disable_dma()
-#define fd_request_dma() (0) /* nothing... */
-#define fd_free_dma() /* nothing... */
-#define fd_clear_dma_ff() /* nothing... */
-#define fd_set_dma_mode(mode) sun_fdops.fd_set_dma_mode(mode)
-#define fd_set_dma_addr(addr) sun_fdops.fd_set_dma_addr(addr)
-#define fd_set_dma_count(count) sun_fdops.fd_set_dma_count(count)
-#define get_dma_residue(x) sun_fdops.get_dma_residue()
-#define fd_cacheflush(addr, size) /* nothing... */
-#define fd_request_irq() sun_fdops.fd_request_irq()
-#define fd_free_irq() sun_fdops.fd_free_irq()
-#define fd_eject(drive) sun_fdops.fd_eject(drive)
-
-/* Super paranoid... */
-#undef HAVE_DISABLE_HLT
-
-static int sun_floppy_types[2] = { 0, 0 };
-
-/* Here is where we catch the floppy driver trying to initialize,
- * therefore this is where we call the PROM device tree probing
- * routine etc. on the Sparc.
- */
-#define FLOPPY0_TYPE sun_floppy_init()
-#define FLOPPY1_TYPE sun_floppy_types[1]
-
-#define FDC1 ((unsigned long)sun_fdc)
-
-#define N_FDC 1
-#define N_DRIVE 8
-
-/* No 64k boundary crossing problems on the Sparc. */
-#define CROSS_64KB(a,s) (0)
-
-static unsigned char sun_82077_fd_inb(unsigned long port)
-{
- udelay(5);
- switch(port & 7) {
- default:
- printk("floppy: Asked to read unknown port %lx\n", port);
- panic("floppy: Port bolixed.");
- case 4: /* FD_STATUS */
- return sbus_readb(&sun_fdc->status_82077) & ~STATUS_DMA;
- case 5: /* FD_DATA */
- return sbus_readb(&sun_fdc->data_82077);
- case 7: /* FD_DIR */
- /* XXX: Is DCL on 0x80 in sun4m? */
- return sbus_readb(&sun_fdc->dir_82077);
- };
- panic("sun_82072_fd_inb: How did I get here?");
-}
-
-static void sun_82077_fd_outb(unsigned char value, unsigned long port)
-{
- udelay(5);
- switch(port & 7) {
- default:
- printk("floppy: Asked to write to unknown port %lx\n", port);
- panic("floppy: Port bolixed.");
- case 2: /* FD_DOR */
- /* Happily, the 82077 has a real DOR register. */
- sbus_writeb(value, &sun_fdc->dor_82077);
- break;
- case 5: /* FD_DATA */
- sbus_writeb(value, &sun_fdc->data_82077);
- break;
- case 7: /* FD_DCR */
- sbus_writeb(value, &sun_fdc->dcr_82077);
- break;
- case 4: /* FD_STATUS */
- sbus_writeb(value, &sun_fdc->status_82077);
- break;
- };
- return;
-}
-
-/* For pseudo-dma (Sun floppy drives have no real DMA available to
- * them so we must eat the data fifo bytes directly ourselves) we have
- * three state variables. doing_pdma tells our inline low-level
- * assembly floppy interrupt entry point whether it should sit and eat
- * bytes from the fifo or just transfer control up to the higher level
- * floppy interrupt c-code. I tried very hard but I could not get the
- * pseudo-dma to work in c-code without getting many overruns and
- * underruns. If non-zero, doing_pdma encodes the direction of
- * the transfer for debugging. 1=read 2=write
- */
-unsigned char *pdma_vaddr;
-unsigned long pdma_size;
-volatile int doing_pdma = 0;
-
-/* This is software state */
-char *pdma_base = NULL;
-unsigned long pdma_areasize;
-
-/* Common routines to all controller types on the Sparc. */
-static void sun_fd_disable_dma(void)
-{
- doing_pdma = 0;
- if (pdma_base) {
- mmu_unlockarea(pdma_base, pdma_areasize);
- pdma_base = NULL;
- }
-}
-
-static void sun_fd_set_dma_mode(int mode)
-{
- switch(mode) {
- case DMA_MODE_READ:
- doing_pdma = 1;
- break;
- case DMA_MODE_WRITE:
- doing_pdma = 2;
- break;
- default:
- printk("Unknown dma mode %d\n", mode);
- panic("floppy: Giving up...");
- }
-}
-
-static void sun_fd_set_dma_addr(char *buffer)
-{
- pdma_vaddr = buffer;
-}
-
-static void sun_fd_set_dma_count(int length)
-{
- pdma_size = length;
-}
-
-static void sun_fd_enable_dma(void)
-{
- pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size);
- pdma_base = pdma_vaddr;
- pdma_areasize = pdma_size;
-}
-
-irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie)
-{
- if (likely(doing_pdma)) {
- void __iomem *stat = (void __iomem *) fdc_status;
- unsigned char *vaddr = pdma_vaddr;
- unsigned long size = pdma_size;
- u8 val;
-
- while (size) {
- val = readb(stat);
- if (unlikely(!(val & 0x80))) {
- pdma_vaddr = vaddr;
- pdma_size = size;
- return IRQ_HANDLED;
- }
- if (unlikely(!(val & 0x20))) {
- pdma_vaddr = vaddr;
- pdma_size = size;
- doing_pdma = 0;
- goto main_interrupt;
- }
- if (val & 0x40) {
- /* read */
- *vaddr++ = readb(stat + 1);
- } else {
- unsigned char data = *vaddr++;
-
- /* write */
- writeb(data, stat + 1);
- }
- size--;
- }
-
- pdma_vaddr = vaddr;
- pdma_size = size;
-
- /* Send Terminal Count pulse to floppy controller. */
- val = readb(auxio_register);
- val |= AUXIO_AUX1_FTCNT;
- writeb(val, auxio_register);
- val &= ~AUXIO_AUX1_FTCNT;
- writeb(val, auxio_register);
-
- doing_pdma = 0;
- }
-
-main_interrupt:
- return floppy_interrupt(irq, dev_cookie);
-}
-
-static int sun_fd_request_irq(void)
-{
- static int once = 0;
- int error;
-
- if(!once) {
- once = 1;
-
- error = request_irq(FLOPPY_IRQ, sparc_floppy_irq,
- IRQF_DISABLED, "floppy", NULL);
-
- return ((error == 0) ? 0 : -1);
- }
- return 0;
-}
-
-static void sun_fd_free_irq(void)
-{
-}
-
-static unsigned int sun_get_dma_residue(void)
-{
- /* XXX This isn't really correct. XXX */
- return 0;
-}
-
-static int sun_fd_eject(int drive)
-{
- set_dor(0x00, 0xff, 0x90);
- udelay(500);
- set_dor(0x00, 0x6f, 0x00);
- udelay(500);
- return 0;
-}
-
-#ifdef CONFIG_PCI
-#include <asm/ebus.h>
-#include <asm/ns87303.h>
-
-static struct ebus_dma_info sun_pci_fd_ebus_dma;
-static struct pci_dev *sun_pci_ebus_dev;
-static int sun_pci_broken_drive = -1;
-
-struct sun_pci_dma_op {
- unsigned int addr;
- int len;
- int direction;
- char *buf;
-};
-static struct sun_pci_dma_op sun_pci_dma_current = { -1U, 0, 0, NULL};
-static struct sun_pci_dma_op sun_pci_dma_pending = { -1U, 0, 0, NULL};
-
-extern irqreturn_t floppy_interrupt(int irq, void *dev_id);
-
-static unsigned char sun_pci_fd_inb(unsigned long port)
-{
- udelay(5);
- return inb(port);
-}
-
-static void sun_pci_fd_outb(unsigned char val, unsigned long port)
-{
- udelay(5);
- outb(val, port);
-}
-
-static void sun_pci_fd_broken_outb(unsigned char val, unsigned long port)
-{
- udelay(5);
- /*
- * XXX: Due to SUN's broken floppy connector on AX and AXi
- * we need to turn on MOTOR_0 also, if the floppy is
- * jumpered to DS1 (like most PC floppies are). I hope
- * this does not hurt correct hardware like the AXmp.
- * (Eddie, Sep 12 1998).
- */
- if (port == ((unsigned long)sun_fdc) + 2) {
- if (((val & 0x03) == sun_pci_broken_drive) && (val & 0x20)) {
- val |= 0x10;
- }
- }
- outb(val, port);
-}
-
-#ifdef PCI_FDC_SWAP_DRIVES
-static void sun_pci_fd_lde_broken_outb(unsigned char val, unsigned long port)
-{
- udelay(5);
- /*
- * XXX: Due to SUN's broken floppy connector on AX and AXi
- * we need to turn on MOTOR_0 also, if the floppy is
- * jumpered to DS1 (like most PC floppies are). I hope
- * this does not hurt correct hardware like the AXmp.
- * (Eddie, Sep 12 1998).
- */
- if (port == ((unsigned long)sun_fdc) + 2) {
- if (((val & 0x03) == sun_pci_broken_drive) && (val & 0x10)) {
- val &= ~(0x03);
- val |= 0x21;
- }
- }
- outb(val, port);
-}
-#endif /* PCI_FDC_SWAP_DRIVES */
-
-static void sun_pci_fd_enable_dma(void)
-{
- BUG_ON((NULL == sun_pci_dma_pending.buf) ||
- (0 == sun_pci_dma_pending.len) ||
- (0 == sun_pci_dma_pending.direction));
-
- sun_pci_dma_current.buf = sun_pci_dma_pending.buf;
- sun_pci_dma_current.len = sun_pci_dma_pending.len;
- sun_pci_dma_current.direction = sun_pci_dma_pending.direction;
-
- sun_pci_dma_pending.buf = NULL;
- sun_pci_dma_pending.len = 0;
- sun_pci_dma_pending.direction = 0;
- sun_pci_dma_pending.addr = -1U;
-
- sun_pci_dma_current.addr =
- pci_map_single(sun_pci_ebus_dev,
- sun_pci_dma_current.buf,
- sun_pci_dma_current.len,
- sun_pci_dma_current.direction);
-
- ebus_dma_enable(&sun_pci_fd_ebus_dma, 1);
-
- if (ebus_dma_request(&sun_pci_fd_ebus_dma,
- sun_pci_dma_current.addr,
- sun_pci_dma_current.len))
- BUG();
-}
-
-static void sun_pci_fd_disable_dma(void)
-{
- ebus_dma_enable(&sun_pci_fd_ebus_dma, 0);
- if (sun_pci_dma_current.addr != -1U)
- pci_unmap_single(sun_pci_ebus_dev,
- sun_pci_dma_current.addr,
- sun_pci_dma_current.len,
- sun_pci_dma_current.direction);
- sun_pci_dma_current.addr = -1U;
-}
-
-static void sun_pci_fd_set_dma_mode(int mode)
-{
- if (mode == DMA_MODE_WRITE)
- sun_pci_dma_pending.direction = PCI_DMA_TODEVICE;
- else
- sun_pci_dma_pending.direction = PCI_DMA_FROMDEVICE;
-
- ebus_dma_prepare(&sun_pci_fd_ebus_dma, mode != DMA_MODE_WRITE);
-}
-
-static void sun_pci_fd_set_dma_count(int length)
-{
- sun_pci_dma_pending.len = length;
-}
-
-static void sun_pci_fd_set_dma_addr(char *buffer)
-{
- sun_pci_dma_pending.buf = buffer;
-}
-
-static unsigned int sun_pci_get_dma_residue(void)
-{
- return ebus_dma_residue(&sun_pci_fd_ebus_dma);
-}
-
-static int sun_pci_fd_request_irq(void)
-{
- return ebus_dma_irq_enable(&sun_pci_fd_ebus_dma, 1);
-}
-
-static void sun_pci_fd_free_irq(void)
-{
- ebus_dma_irq_enable(&sun_pci_fd_ebus_dma, 0);
-}
-
-static int sun_pci_fd_eject(int drive)
-{
- return -EINVAL;
-}
-
-void sun_pci_fd_dma_callback(struct ebus_dma_info *p, int event, void *cookie)
-{
- floppy_interrupt(0, NULL);
-}
-
-/*
- * Floppy probing, we'd like to use /dev/fd0 for a single Floppy on PCI,
- * even if this is configured using DS1, thus looks like /dev/fd1 with
- * the cabling used in Ultras.
- */
-#define DOR (port + 2)
-#define MSR (port + 4)
-#define FIFO (port + 5)
-
-static void sun_pci_fd_out_byte(unsigned long port, unsigned char val,
- unsigned long reg)
-{
- unsigned char status;
- int timeout = 1000;
-
- while (!((status = inb(MSR)) & 0x80) && --timeout)
- udelay(100);
- outb(val, reg);
-}
-
-static unsigned char sun_pci_fd_sensei(unsigned long port)
-{
- unsigned char result[2] = { 0x70, 0x00 };
- unsigned char status;
- int i = 0;
-
- sun_pci_fd_out_byte(port, 0x08, FIFO);
- do {
- int timeout = 1000;
-
- while (!((status = inb(MSR)) & 0x80) && --timeout)
- udelay(100);
-
- if (!timeout)
- break;
-
- if ((status & 0xf0) == 0xd0)
- result[i++] = inb(FIFO);
- else
- break;
- } while (i < 2);
-
- return result[0];
-}
-
-static void sun_pci_fd_reset(unsigned long port)
-{
- unsigned char mask = 0x00;
- unsigned char status;
- int timeout = 10000;
-
- outb(0x80, MSR);
- do {
- status = sun_pci_fd_sensei(port);
- if ((status & 0xc0) == 0xc0)
- mask |= 1 << (status & 0x03);
- else
- udelay(100);
- } while ((mask != 0x0f) && --timeout);
-}
-
-static int sun_pci_fd_test_drive(unsigned long port, int drive)
-{
- unsigned char status, data;
- int timeout = 1000;
- int ready;
-
- sun_pci_fd_reset(port);
-
- data = (0x10 << drive) | 0x0c | drive;
- sun_pci_fd_out_byte(port, data, DOR);
-
- sun_pci_fd_out_byte(port, 0x07, FIFO);
- sun_pci_fd_out_byte(port, drive & 0x03, FIFO);
-
- do {
- udelay(100);
- status = sun_pci_fd_sensei(port);
- } while (((status & 0xc0) == 0x80) && --timeout);
-
- if (!timeout)
- ready = 0;
- else
- ready = (status & 0x10) ? 0 : 1;
-
- sun_pci_fd_reset(port);
- return ready;
-}
-#undef FIFO
-#undef MSR
-#undef DOR
-
-#endif /* CONFIG_PCI */
-
-#ifdef CONFIG_PCI
-static int __init ebus_fdthree_p(struct linux_ebus_device *edev)
-{
- if (!strcmp(edev->prom_node->name, "fdthree"))
- return 1;
- if (!strcmp(edev->prom_node->name, "floppy")) {
- const char *compat;
-
- compat = of_get_property(edev->prom_node,
- "compatible", NULL);
- if (compat && !strcmp(compat, "fdthree"))
- return 1;
- }
- return 0;
-}
-#endif
-
-static unsigned long __init sun_floppy_init(void)
-{
- char state[128];
- struct sbus_bus *bus;
- struct sbus_dev *sdev = NULL;
- static int initialized = 0;
-
- if (initialized)
- return sun_floppy_types[0];
- initialized = 1;
-
- for_all_sbusdev (sdev, bus) {
- if (!strcmp(sdev->prom_name, "SUNW,fdtwo"))
- break;
- }
- if(sdev) {
- floppy_sdev = sdev;
- FLOPPY_IRQ = sdev->irqs[0];
- } else {
-#ifdef CONFIG_PCI
- struct linux_ebus *ebus;
- struct linux_ebus_device *edev = NULL;
- unsigned long config = 0;
- void __iomem *auxio_reg;
- const char *state_prop;
-
- for_each_ebus(ebus) {
- for_each_ebusdev(edev, ebus) {
- if (ebus_fdthree_p(edev))
- goto ebus_done;
- }
- }
- ebus_done:
- if (!edev)
- return 0;
-
- state_prop = of_get_property(edev->prom_node, "status", NULL);
- if (state_prop && !strncmp(state_prop, "disabled", 8))
- return 0;
-
- FLOPPY_IRQ = edev->irqs[0];
-
- /* Make sure the high density bit is set, some systems
- * (most notably Ultra5/Ultra10) come up with it clear.
- */
- auxio_reg = (void __iomem *) edev->resource[2].start;
- writel(readl(auxio_reg)|0x2, auxio_reg);
-
- sun_pci_ebus_dev = ebus->self;
-
- spin_lock_init(&sun_pci_fd_ebus_dma.lock);
-
- /* XXX ioremap */
- sun_pci_fd_ebus_dma.regs = (void __iomem *)
- edev->resource[1].start;
- if (!sun_pci_fd_ebus_dma.regs)
- return 0;
-
- sun_pci_fd_ebus_dma.flags = (EBUS_DMA_FLAG_USE_EBDMA_HANDLER |
- EBUS_DMA_FLAG_TCI_DISABLE);
- sun_pci_fd_ebus_dma.callback = sun_pci_fd_dma_callback;
- sun_pci_fd_ebus_dma.client_cookie = NULL;
- sun_pci_fd_ebus_dma.irq = FLOPPY_IRQ;
- strcpy(sun_pci_fd_ebus_dma.name, "floppy");
- if (ebus_dma_register(&sun_pci_fd_ebus_dma))
- return 0;
-
- /* XXX ioremap */
- sun_fdc = (struct sun_flpy_controller *)edev->resource[0].start;
-
- sun_fdops.fd_inb = sun_pci_fd_inb;
- sun_fdops.fd_outb = sun_pci_fd_outb;
-
- can_use_virtual_dma = use_virtual_dma = 0;
- sun_fdops.fd_enable_dma = sun_pci_fd_enable_dma;
- sun_fdops.fd_disable_dma = sun_pci_fd_disable_dma;
- sun_fdops.fd_set_dma_mode = sun_pci_fd_set_dma_mode;
- sun_fdops.fd_set_dma_addr = sun_pci_fd_set_dma_addr;
- sun_fdops.fd_set_dma_count = sun_pci_fd_set_dma_count;
- sun_fdops.get_dma_residue = sun_pci_get_dma_residue;
-
- sun_fdops.fd_request_irq = sun_pci_fd_request_irq;
- sun_fdops.fd_free_irq = sun_pci_fd_free_irq;
-
- sun_fdops.fd_eject = sun_pci_fd_eject;
-
- fdc_status = (unsigned long) &sun_fdc->status_82077;
-
- /*
- * XXX: Find out on which machines this is really needed.
- */
- if (1) {
- sun_pci_broken_drive = 1;
- sun_fdops.fd_outb = sun_pci_fd_broken_outb;
- }
-
- allowed_drive_mask = 0;
- if (sun_pci_fd_test_drive((unsigned long)sun_fdc, 0))
- sun_floppy_types[0] = 4;
- if (sun_pci_fd_test_drive((unsigned long)sun_fdc, 1))
- sun_floppy_types[1] = 4;
-
- /*
- * Find NS87303 SuperIO config registers (through ecpp).
- */
- for_each_ebus(ebus) {
- for_each_ebusdev(edev, ebus) {
- if (!strcmp(edev->prom_node->name, "ecpp")) {
- config = edev->resource[1].start;
- goto config_done;
- }
- }
- }
- config_done:
-
- /*
- * Sanity check, is this really the NS87303?
- */
- switch (config & 0x3ff) {
- case 0x02e:
- case 0x15c:
- case 0x26e:
- case 0x398:
- break;
- default:
- config = 0;
- }
-
- if (!config)
- return sun_floppy_types[0];
-
- /* Enable PC-AT mode. */
- ns87303_modify(config, ASC, 0, 0xc0);
-
-#ifdef PCI_FDC_SWAP_DRIVES
- /*
- * If only Floppy 1 is present, swap drives.
- */
- if (!sun_floppy_types[0] && sun_floppy_types[1]) {
- /*
- * Set the drive exchange bit in FCR on NS87303,
- * make sure other bits are sane before doing so.
- */
- ns87303_modify(config, FER, FER_EDM, 0);
- ns87303_modify(config, ASC, ASC_DRV2_SEL, 0);
- ns87303_modify(config, FCR, 0, FCR_LDE);
-
- config = sun_floppy_types[0];
- sun_floppy_types[0] = sun_floppy_types[1];
- sun_floppy_types[1] = config;
-
- if (sun_pci_broken_drive != -1) {
- sun_pci_broken_drive = 1 - sun_pci_broken_drive;
- sun_fdops.fd_outb = sun_pci_fd_lde_broken_outb;
- }
- }
-#endif /* PCI_FDC_SWAP_DRIVES */
-
- return sun_floppy_types[0];
-#else
- return 0;
-#endif
- }
- prom_getproperty(sdev->prom_node, "status", state, sizeof(state));
- if(!strncmp(state, "disabled", 8))
- return 0;
-
- /*
- * We cannot do sbus_ioremap here: it does request_region,
- * which the generic floppy driver tries to do once again.
- * But we must use the sdev resource values as they have
- * had parent ranges applied.
- */
- sun_fdc = (struct sun_flpy_controller *)
- (sdev->resource[0].start +
- ((sdev->resource[0].flags & 0x1ffUL) << 32UL));
-
- /* Last minute sanity check... */
- if(sbus_readb(&sun_fdc->status1_82077) == 0xff) {
- sun_fdc = (struct sun_flpy_controller *)-1;
- return 0;
- }
-
- sun_fdops.fd_inb = sun_82077_fd_inb;
- sun_fdops.fd_outb = sun_82077_fd_outb;
-
- can_use_virtual_dma = use_virtual_dma = 1;
- sun_fdops.fd_enable_dma = sun_fd_enable_dma;
- sun_fdops.fd_disable_dma = sun_fd_disable_dma;
- sun_fdops.fd_set_dma_mode = sun_fd_set_dma_mode;
- sun_fdops.fd_set_dma_addr = sun_fd_set_dma_addr;
- sun_fdops.fd_set_dma_count = sun_fd_set_dma_count;
- sun_fdops.get_dma_residue = sun_get_dma_residue;
-
- sun_fdops.fd_request_irq = sun_fd_request_irq;
- sun_fdops.fd_free_irq = sun_fd_free_irq;
-
- sun_fdops.fd_eject = sun_fd_eject;
-
- fdc_status = (unsigned long) &sun_fdc->status_82077;
-
- /* Success... */
- allowed_drive_mask = 0x01;
- sun_floppy_types[0] = 4;
- sun_floppy_types[1] = 0;
-
- return sun_floppy_types[0];
-}
-
-#define EXTRA_FLOPPY_PARAMS
-
-static DEFINE_SPINLOCK(dma_spin_lock);
-
-#define claim_dma_lock() \
-({ unsigned long flags; \
- spin_lock_irqsave(&dma_spin_lock, flags); \
- flags; \
-})
-
-#define release_dma_lock(__flags) \
- spin_unlock_irqrestore(&dma_spin_lock, __flags);
-
-#endif /* !(__ASM_SPARC64_FLOPPY_H) */
+++ /dev/null
-/* fpumacro.h: FPU related macros.
- *
- * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC64_FPUMACRO_H
-#define _SPARC64_FPUMACRO_H
-
-#include <asm/asi.h>
-#include <asm/visasm.h>
-
-struct fpustate {
- u32 regs[64];
-};
-
-#define FPUSTATE (struct fpustate *)(current_thread_info()->fpregs)
-
-static inline unsigned long fprs_read(void)
-{
- unsigned long retval;
-
- __asm__ __volatile__("rd %%fprs, %0" : "=r" (retval));
-
- return retval;
-}
-
-static inline void fprs_write(unsigned long val)
-{
- __asm__ __volatile__("wr %0, 0x0, %%fprs" : : "r" (val));
-}
-
-#endif /* !(_SPARC64_FPUMACRO_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_FUTEX_H
-#define ___ASM_SPARC_FUTEX_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/futex_64.h>
-#else
-#include <asm-sparc/futex_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#include <asm-generic/futex.h>
-
-#endif
+++ /dev/null
-#ifndef _SPARC64_FUTEX_H
-#define _SPARC64_FUTEX_H
-
-#include <linux/futex.h>
-#include <linux/uaccess.h>
-#include <asm/errno.h>
-#include <asm/system.h>
-
-#define __futex_cas_op(insn, ret, oldval, uaddr, oparg) \
- __asm__ __volatile__( \
- "\n1: lduwa [%3] %%asi, %2\n" \
- " " insn "\n" \
- "2: casa [%3] %%asi, %2, %1\n" \
- " cmp %2, %1\n" \
- " bne,pn %%icc, 1b\n" \
- " mov 0, %0\n" \
- "3:\n" \
- " .section .fixup,#alloc,#execinstr\n" \
- " .align 4\n" \
- "4: sethi %%hi(3b), %0\n" \
- " jmpl %0 + %%lo(3b), %%g0\n" \
- " mov %5, %0\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .align 4\n" \
- " .word 1b, 4b\n" \
- " .word 2b, 4b\n" \
- " .previous\n" \
- : "=&r" (ret), "=&r" (oldval), "=&r" (tem) \
- : "r" (uaddr), "r" (oparg), "i" (-EFAULT) \
- : "memory")
-
-static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
-{
- int op = (encoded_op >> 28) & 7;
- int cmp = (encoded_op >> 24) & 15;
- int oparg = (encoded_op << 8) >> 20;
- int cmparg = (encoded_op << 20) >> 20;
- int oldval = 0, ret, tem;
-
- if (unlikely(!access_ok(VERIFY_WRITE, uaddr, sizeof(int))))
- return -EFAULT;
- if (unlikely((((unsigned long) uaddr) & 0x3UL)))
- return -EINVAL;
-
- if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
- oparg = 1 << oparg;
-
- pagefault_disable();
-
- switch (op) {
- case FUTEX_OP_SET:
- __futex_cas_op("mov\t%4, %1", ret, oldval, uaddr, oparg);
- break;
- case FUTEX_OP_ADD:
- __futex_cas_op("add\t%2, %4, %1", ret, oldval, uaddr, oparg);
- break;
- case FUTEX_OP_OR:
- __futex_cas_op("or\t%2, %4, %1", ret, oldval, uaddr, oparg);
- break;
- case FUTEX_OP_ANDN:
- __futex_cas_op("and\t%2, %4, %1", ret, oldval, uaddr, oparg);
- break;
- case FUTEX_OP_XOR:
- __futex_cas_op("xor\t%2, %4, %1", ret, oldval, uaddr, oparg);
- break;
- default:
- ret = -ENOSYS;
- }
-
- pagefault_enable();
-
- if (!ret) {
- switch (cmp) {
- case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
- case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
- case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
- case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
- case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
- case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
- default: ret = -ENOSYS;
- }
- }
- return ret;
-}
-
-static inline int
-futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
-{
- __asm__ __volatile__(
- "\n1: casa [%3] %%asi, %2, %0\n"
- "2:\n"
- " .section .fixup,#alloc,#execinstr\n"
- " .align 4\n"
- "3: sethi %%hi(2b), %0\n"
- " jmpl %0 + %%lo(2b), %%g0\n"
- " mov %4, %0\n"
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .align 4\n"
- " .word 1b, 3b\n"
- " .previous\n"
- : "=r" (newval)
- : "0" (newval), "r" (oldval), "r" (uaddr), "i" (-EFAULT)
- : "memory");
-
- return newval;
-}
-
-#endif /* !(_SPARC64_FUTEX_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_HARDIRQ_H
-#define ___ASM_SPARC_HARDIRQ_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/hardirq_64.h>
-#else
-#include <asm-sparc/hardirq_32.h>
-#endif
-#endif
+++ /dev/null
-/* hardirq.h: 32-bit Sparc hard IRQ support.
- *
- * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1998-2000 Anton Blanchard (anton@samba.org)
- */
-
-#ifndef __SPARC_HARDIRQ_H
-#define __SPARC_HARDIRQ_H
-
-#include <linux/threads.h>
-#include <linux/spinlock.h>
-#include <linux/cache.h>
-
-/* entry.S is sensitive to the offsets of these fields */ /* XXX P3 Is it? */
-typedef struct {
- unsigned int __softirq_pending;
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
-
-#define HARDIRQ_BITS 8
-
-#endif /* __SPARC_HARDIRQ_H */
+++ /dev/null
-/* hardirq.h: 64-bit Sparc hard IRQ support.
- *
- * Copyright (C) 1997, 1998, 2005 David S. Miller (davem@davemloft.net)
- */
-
-#ifndef __SPARC64_HARDIRQ_H
-#define __SPARC64_HARDIRQ_H
-
-#include <asm/cpudata.h>
-
-#define __ARCH_IRQ_STAT
-#define local_softirq_pending() \
- (local_cpu_data().__softirq_pending)
-
-void ack_bad_irq(unsigned int irq);
-
-#define HARDIRQ_BITS 8
-
-#endif /* !(__SPARC64_HARDIRQ_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_HEAD_H
-#define ___ASM_SPARC_HEAD_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/head_64.h>
-#else
-#include <asm-sparc/head_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef __SPARC_HEAD_H
-#define __SPARC_HEAD_H
-
-#define KERNBASE 0xf0000000 /* First address the kernel will eventually be */
-#define LOAD_ADDR 0x4000 /* prom jumps to us here unless this is elf /boot */
-#define SUN4C_SEGSZ (1 << 18)
-#define SRMMU_L1_KBASE_OFFSET ((KERNBASE>>24)<<2) /* Used in boot remapping. */
-#define INTS_ENAB 0x01 /* entry.S uses this. */
-
-#define SUN4_PROM_VECTOR 0xFFE81000 /* SUN4 PROM needs to be hardwired */
-
-#define WRITE_PAUSE nop; nop; nop; /* Have to do this after %wim/%psr chg */
-#define NOP_INSN 0x01000000 /* Used to patch sparc_save_state */
-
-/* Here are some trap goodies */
-
-/* Generic trap entry. */
-#define TRAP_ENTRY(type, label) \
- rd %psr, %l0; b label; rd %wim, %l3; nop;
-
-/* Data/text faults. Defaults to sun4c version at boot time. */
-#define SPARC_TFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 1, %l7;
-#define SPARC_DFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 0, %l7;
-#define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
-#define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
-
-/* This is for traps we should NEVER get. */
-#define BAD_TRAP(num) \
- rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
-
-/* This is for traps when we want just skip the instruction which caused it */
-#define SKIP_TRAP(type, name) \
- jmpl %l2, %g0; rett %l2 + 4; nop; nop;
-
-/* Notice that for the system calls we pull a trick. We load up a
- * different pointer to the system call vector table in %l7, but call
- * the same generic system call low-level entry point. The trap table
- * entry sequences are also HyperSparc pipeline friendly ;-)
- */
-
-/* Software trap for Linux system calls. */
-#define LINUX_SYSCALL_TRAP \
- sethi %hi(sys_call_table), %l7; \
- or %l7, %lo(sys_call_table), %l7; \
- b linux_sparc_syscall; \
- rd %psr, %l0;
-
-#define BREAKPOINT_TRAP \
- b breakpoint_trap; \
- rd %psr,%l0; \
- nop; \
- nop;
-
-#ifdef CONFIG_KGDB
-#define KGDB_TRAP(num) \
- b kgdb_trap_low; \
- rd %psr,%l0; \
- nop; \
- nop;
-#else
-#define KGDB_TRAP(num) \
- BAD_TRAP(num)
-#endif
-
-/* The Get Condition Codes software trap for userland. */
-#define GETCC_TRAP \
- b getcc_trap_handler; mov %psr, %l0; nop; nop;
-
-/* The Set Condition Codes software trap for userland. */
-#define SETCC_TRAP \
- b setcc_trap_handler; mov %psr, %l0; nop; nop;
-
-/* The Get PSR software trap for userland. */
-#define GETPSR_TRAP \
- mov %psr, %i0; jmp %l2; rett %l2 + 4; nop;
-
-/* This is for hard interrupts from level 1-14, 15 is non-maskable (nmi) and
- * gets handled with another macro.
- */
-#define TRAP_ENTRY_INTERRUPT(int_level) \
- mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
-
-/* NMI's (Non Maskable Interrupts) are special, you can't keep them
- * from coming in, and basically if you get one, the shows over. ;(
- * On the sun4c they are usually asynchronous memory errors, on the
- * the sun4m they could be either due to mem errors or a software
- * initiated interrupt from the prom/kern on an SMP box saying "I
- * command you to do CPU tricks, read your mailbox for more info."
- */
-#define NMI_TRAP \
- rd %wim, %l3; b linux_trap_nmi_sun4c; mov %psr, %l0; nop;
-
-/* Window overflows/underflows are special and we need to try to be as
- * efficient as possible here....
- */
-#define WINDOW_SPILL \
- rd %psr, %l0; rd %wim, %l3; b spill_window_entry; andcc %l0, PSR_PS, %g0;
-
-#define WINDOW_FILL \
- rd %psr, %l0; rd %wim, %l3; b fill_window_entry; andcc %l0, PSR_PS, %g0;
-
-#endif /* __SPARC_HEAD_H */
+++ /dev/null
-#ifndef _SPARC64_HEAD_H
-#define _SPARC64_HEAD_H
-
-#include <asm/pstate.h>
-
- /* wrpr %g0, val, %gl */
-#define SET_GL(val) \
- .word 0xa1902000 | val
-
- /* rdpr %gl, %gN */
-#define GET_GL_GLOBAL(N) \
- .word 0x81540000 | (N << 25)
-
-#define KERNBASE 0x400000
-
-#define PTREGS_OFF (STACK_BIAS + STACKFRAME_SZ)
-
-#define __CHEETAH_ID 0x003e0014
-#define __JALAPENO_ID 0x003e0016
-#define __SERRANO_ID 0x003e0022
-
-#define CHEETAH_MANUF 0x003e
-#define CHEETAH_IMPL 0x0014 /* Ultra-III */
-#define CHEETAH_PLUS_IMPL 0x0015 /* Ultra-III+ */
-#define JALAPENO_IMPL 0x0016 /* Ultra-IIIi */
-#define JAGUAR_IMPL 0x0018 /* Ultra-IV */
-#define PANTHER_IMPL 0x0019 /* Ultra-IV+ */
-#define SERRANO_IMPL 0x0022 /* Ultra-IIIi+ */
-
-#define BRANCH_IF_SUN4V(tmp1,label) \
- sethi %hi(is_sun4v), %tmp1; \
- lduw [%tmp1 + %lo(is_sun4v)], %tmp1; \
- brnz,pn %tmp1, label; \
- nop
-
-#define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \
- rdpr %ver, %tmp1; \
- sethi %hi(__CHEETAH_ID), %tmp2; \
- srlx %tmp1, 32, %tmp1; \
- or %tmp2, %lo(__CHEETAH_ID), %tmp2;\
- cmp %tmp1, %tmp2; \
- be,pn %icc, label; \
- nop;
-
-#define BRANCH_IF_JALAPENO(tmp1,tmp2,label) \
- rdpr %ver, %tmp1; \
- sethi %hi(__JALAPENO_ID), %tmp2; \
- srlx %tmp1, 32, %tmp1; \
- or %tmp2, %lo(__JALAPENO_ID), %tmp2;\
- cmp %tmp1, %tmp2; \
- be,pn %icc, label; \
- nop;
-
-#define BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(tmp1,tmp2,label) \
- rdpr %ver, %tmp1; \
- srlx %tmp1, (32 + 16), %tmp2; \
- cmp %tmp2, CHEETAH_MANUF; \
- bne,pt %xcc, 99f; \
- sllx %tmp1, 16, %tmp1; \
- srlx %tmp1, (32 + 16), %tmp2; \
- cmp %tmp2, CHEETAH_PLUS_IMPL; \
- bgeu,pt %xcc, label; \
-99: nop;
-
-#define BRANCH_IF_ANY_CHEETAH(tmp1,tmp2,label) \
- rdpr %ver, %tmp1; \
- srlx %tmp1, (32 + 16), %tmp2; \
- cmp %tmp2, CHEETAH_MANUF; \
- bne,pt %xcc, 99f; \
- sllx %tmp1, 16, %tmp1; \
- srlx %tmp1, (32 + 16), %tmp2; \
- cmp %tmp2, CHEETAH_IMPL; \
- bgeu,pt %xcc, label; \
-99: nop;
-
-#endif /* !(_SPARC64_HEAD_H) */
+++ /dev/null
-/*
- * highmem.h: virtual kernel memory mappings for high memory
- *
- * Used in CONFIG_HIGHMEM systems for memory pages which
- * are not addressable by direct kernel virtual addresses.
- *
- * Copyright (C) 1999 Gerhard Wichert, Siemens AG
- * Gerhard.Wichert@pdb.siemens.de
- *
- *
- * Redesigned the x86 32-bit VM architecture to deal with
- * up to 16 Terrabyte physical memory. With current x86 CPUs
- * we now support up to 64 Gigabytes physical RAM.
- *
- * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
- */
-
-#ifndef _ASM_HIGHMEM_H
-#define _ASM_HIGHMEM_H
-
-#ifdef __KERNEL__
-
-#include <linux/interrupt.h>
-#include <asm/fixmap.h>
-#include <asm/vaddrs.h>
-#include <asm/kmap_types.h>
-#include <asm/pgtable.h>
-
-/* declarations for highmem.c */
-extern unsigned long highstart_pfn, highend_pfn;
-
-extern pte_t *kmap_pte;
-extern pgprot_t kmap_prot;
-extern pte_t *pkmap_page_table;
-
-extern void kmap_init(void) __init;
-
-/*
- * Right now we initialize only a single pte table. It can be extended
- * easily, subsequent pte tables have to be allocated in one physical
- * chunk of RAM. Currently the simplest way to do this is to align the
- * pkmap region on a pagetable boundary (4MB).
- */
-#define LAST_PKMAP 1024
-#define PKMAP_SIZE (LAST_PKMAP << PAGE_SHIFT)
-#define PKMAP_BASE PMD_ALIGN(SRMMU_NOCACHE_VADDR + (SRMMU_MAX_NOCACHE_PAGES << PAGE_SHIFT))
-
-#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
-#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT)
-#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-
-#define PKMAP_END (PKMAP_ADDR(LAST_PKMAP))
-
-extern void *kmap_high(struct page *page);
-extern void kunmap_high(struct page *page);
-
-static inline void *kmap(struct page *page)
-{
- BUG_ON(in_interrupt());
- if (!PageHighMem(page))
- return page_address(page);
- return kmap_high(page);
-}
-
-static inline void kunmap(struct page *page)
-{
- BUG_ON(in_interrupt());
- if (!PageHighMem(page))
- return;
- kunmap_high(page);
-}
-
-extern void *kmap_atomic(struct page *page, enum km_type type);
-extern void kunmap_atomic(void *kvaddr, enum km_type type);
-extern struct page *kmap_atomic_to_page(void *vaddr);
-
-#define flush_cache_kmaps() flush_cache_all()
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_HIGHMEM_H */
+++ /dev/null
-#ifndef _ASM_SPARC64_HUGETLB_H
-#define _ASM_SPARC64_HUGETLB_H
-
-#include <asm/page.h>
-
-
-void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
- pte_t *ptep, pte_t pte);
-
-pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
- pte_t *ptep);
-
-void hugetlb_prefault_arch_hook(struct mm_struct *mm);
-
-static inline int is_hugepage_only_range(struct mm_struct *mm,
- unsigned long addr,
- unsigned long len) {
- return 0;
-}
-
-/*
- * If the arch doesn't supply something else, assume that hugepage
- * size aligned regions are ok without further preparation.
- */
-static inline int prepare_hugepage_range(struct file *file,
- unsigned long addr, unsigned long len)
-{
- if (len & ~HPAGE_MASK)
- return -EINVAL;
- if (addr & ~HPAGE_MASK)
- return -EINVAL;
- return 0;
-}
-
-static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
- unsigned long addr, unsigned long end,
- unsigned long floor,
- unsigned long ceiling)
-{
- free_pgd_range(tlb, addr, end, floor, ceiling);
-}
-
-static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
- unsigned long addr, pte_t *ptep)
-{
-}
-
-static inline int huge_pte_none(pte_t pte)
-{
- return pte_none(pte);
-}
-
-static inline pte_t huge_pte_wrprotect(pte_t pte)
-{
- return pte_wrprotect(pte);
-}
-
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
- unsigned long addr, pte_t *ptep)
-{
- ptep_set_wrprotect(mm, addr, ptep);
-}
-
-static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
- unsigned long addr, pte_t *ptep,
- pte_t pte, int dirty)
-{
- return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
-}
-
-static inline pte_t huge_ptep_get(pte_t *ptep)
-{
- return *ptep;
-}
-
-static inline int arch_prepare_hugepage(struct page *page)
-{
- return 0;
-}
-
-static inline void arch_release_hugepage(struct page *page)
-{
-}
-
-#endif /* _ASM_SPARC64_HUGETLB_H */
+++ /dev/null
-#ifndef _SPARC64_HVTRAP_H
-#define _SPARC64_HVTRAP_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-struct hvtramp_mapping {
- __u64 vaddr;
- __u64 tte;
-};
-
-struct hvtramp_descr {
- __u32 cpu;
- __u32 num_mappings;
- __u64 fault_info_va;
- __u64 fault_info_pa;
- __u64 thread_reg;
- struct hvtramp_mapping maps[1];
-};
-
-extern void hv_cpu_startup(unsigned long hvdescr_pa);
-
-#endif
-
-#define HVTRAMP_DESCR_CPU 0x00
-#define HVTRAMP_DESCR_NUM_MAPPINGS 0x04
-#define HVTRAMP_DESCR_FAULT_INFO_VA 0x08
-#define HVTRAMP_DESCR_FAULT_INFO_PA 0x10
-#define HVTRAMP_DESCR_THREAD_REG 0x18
-#define HVTRAMP_DESCR_MAPS 0x20
-
-#define HVTRAMP_MAPPING_VADDR 0x00
-#define HVTRAMP_MAPPING_TTE 0x08
-#define HVTRAMP_MAPPING_SIZE 0x10
-
-#endif /* _SPARC64_HVTRAP_H */
+++ /dev/null
-#ifndef __ASM_SPARC_HW_IRQ_H
-#define __ASM_SPARC_HW_IRQ_H
-
-/* Dummy include. */
-
-#endif
+++ /dev/null
-#ifndef _SPARC64_HYPERVISOR_H
-#define _SPARC64_HYPERVISOR_H
-
-/* Sun4v hypervisor interfaces and defines.
- *
- * Hypervisor calls are made via traps to software traps number 0x80
- * and above. Registers %o0 to %o5 serve as argument, status, and
- * return value registers.
- *
- * There are two kinds of these traps. First there are the normal
- * "fast traps" which use software trap 0x80 and encode the function
- * to invoke by number in register %o5. Argument and return value
- * handling is as follows:
- *
- * -----------------------------------------------
- * | %o5 | function number | undefined |
- * | %o0 | argument 0 | return status |
- * | %o1 | argument 1 | return value 1 |
- * | %o2 | argument 2 | return value 2 |
- * | %o3 | argument 3 | return value 3 |
- * | %o4 | argument 4 | return value 4 |
- * -----------------------------------------------
- *
- * The second type are "hyper-fast traps" which encode the function
- * number in the software trap number itself. So these use trap
- * numbers > 0x80. The register usage for hyper-fast traps is as
- * follows:
- *
- * -----------------------------------------------
- * | %o0 | argument 0 | return status |
- * | %o1 | argument 1 | return value 1 |
- * | %o2 | argument 2 | return value 2 |
- * | %o3 | argument 3 | return value 3 |
- * | %o4 | argument 4 | return value 4 |
- * -----------------------------------------------
- *
- * Registers providing explicit arguments to the hypervisor calls
- * are volatile across the call. Upon return their values are
- * undefined unless explicitly specified as containing a particular
- * return value by the specific call. The return status is always
- * returned in register %o0, zero indicates a successful execution of
- * the hypervisor call and other values indicate an error status as
- * defined below. So, for example, if a hyper-fast trap takes
- * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
- * the call and %o3, %o4, and %o5 would be preserved.
- *
- * If the hypervisor trap is invalid, or the fast trap function number
- * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
- * of the argument and return values are significant.
- */
-
-/* Trap numbers. */
-#define HV_FAST_TRAP 0x80
-#define HV_MMU_MAP_ADDR_TRAP 0x83
-#define HV_MMU_UNMAP_ADDR_TRAP 0x84
-#define HV_TTRACE_ADDENTRY_TRAP 0x85
-#define HV_CORE_TRAP 0xff
-
-/* Error codes. */
-#define HV_EOK 0 /* Successful return */
-#define HV_ENOCPU 1 /* Invalid CPU id */
-#define HV_ENORADDR 2 /* Invalid real address */
-#define HV_ENOINTR 3 /* Invalid interrupt id */
-#define HV_EBADPGSZ 4 /* Invalid pagesize encoding */
-#define HV_EBADTSB 5 /* Invalid TSB description */
-#define HV_EINVAL 6 /* Invalid argument */
-#define HV_EBADTRAP 7 /* Invalid function number */
-#define HV_EBADALIGN 8 /* Invalid address alignment */
-#define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */
-#define HV_ENOACCESS 10 /* No access to resource */
-#define HV_EIO 11 /* I/O error */
-#define HV_ECPUERROR 12 /* CPU in error state */
-#define HV_ENOTSUPPORTED 13 /* Function not supported */
-#define HV_ENOMAP 14 /* No mapping found */
-#define HV_ETOOMANY 15 /* Too many items specified */
-#define HV_ECHANNEL 16 /* Invalid LDC channel */
-#define HV_EBUSY 17 /* Resource busy */
-
-/* mach_exit()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MACH_EXIT
- * ARG0: exit code
- * ERRORS: This service does not return.
- *
- * Stop all CPUs in the virtual domain and place them into the stopped
- * state. The 64-bit exit code may be passed to a service entity as
- * the domain's exit status. On systems without a service entity, the
- * domain will undergo a reset, and the boot firmware will be
- * reloaded.
- *
- * This function will never return to the guest that invokes it.
- *
- * Note: By convention an exit code of zero denotes a successful exit by
- * the guest code. A non-zero exit code denotes a guest specific
- * error indication.
- *
- */
-#define HV_FAST_MACH_EXIT 0x00
-
-#ifndef __ASSEMBLY__
-extern void sun4v_mach_exit(unsigned long exit_code);
-#endif
-
-/* Domain services. */
-
-/* mach_desc()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MACH_DESC
- * ARG0: buffer
- * ARG1: length
- * RET0: status
- * RET1: length
- * ERRORS: HV_EBADALIGN Buffer is badly aligned
- * HV_ENORADDR Buffer is to an illegal real address.
- * HV_EINVAL Buffer length is too small for complete
- * machine description.
- *
- * Copy the most current machine description into the buffer indicated
- * by the real address in ARG0. The buffer provided must be 16 byte
- * aligned. Upon success or HV_EINVAL, this service returns the
- * actual size of the machine description in the RET1 return value.
- *
- * Note: A method of determining the appropriate buffer size for the
- * machine description is to first call this service with a buffer
- * length of 0 bytes.
- */
-#define HV_FAST_MACH_DESC 0x01
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_mach_desc(unsigned long buffer_pa,
- unsigned long buf_len,
- unsigned long *real_buf_len);
-#endif
-
-/* mach_sir()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MACH_SIR
- * ERRORS: This service does not return.
- *
- * Perform a software initiated reset of the virtual machine domain.
- * All CPUs are captured as soon as possible, all hardware devices are
- * returned to the entry default state, and the domain is restarted at
- * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
- * of the CPUs. The single CPU restarted is selected as determined by
- * platform specific policy. Memory is preserved across this
- * operation.
- */
-#define HV_FAST_MACH_SIR 0x02
-
-#ifndef __ASSEMBLY__
-extern void sun4v_mach_sir(void);
-#endif
-
-/* mach_set_watchdog()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MACH_SET_WATCHDOG
- * ARG0: timeout in milliseconds
- * RET0: status
- * RET1: time remaining in milliseconds
- *
- * A guest uses this API to set a watchdog timer. Once the gues has set
- * the timer, it must call the timer service again either to disable or
- * postpone the expiration. If the timer expires before being reset or
- * disabled, then the hypervisor take a platform specific action leading
- * to guest termination within a bounded time period. The platform action
- * may include recovery actions such as reporting the expiration to a
- * Service Processor, and/or automatically restarting the gues.
- *
- * The 'timeout' parameter is specified in milliseconds, however the
- * implementated granularity is given by the 'watchdog-resolution'
- * property in the 'platform' node of the guest's machine description.
- * The largest allowed timeout value is specified by the
- * 'watchdog-max-timeout' property of the 'platform' node.
- *
- * If the 'timeout' argument is not zero, the watchdog timer is set to
- * expire after a minimum of 'timeout' milliseconds.
- *
- * If the 'timeout' argument is zero, the watchdog timer is disabled.
- *
- * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
- * property, the hypervisor leaves the watchdog timer state unchanged,
- * and returns a status of EINVAL.
- *
- * The 'time remaining' return value is valid regardless of whether the
- * return status is EOK or EINVAL. A non-zero return value indicates the
- * number of milliseconds that were remaining until the timer was to expire.
- * If less than one millisecond remains, the return value is '1'. If the
- * watchdog timer was disabled at the time of the call, the return value is
- * zero.
- *
- * If the hypervisor cannot support the exact timeout value requested, but
- * can support a larger timeout value, the hypervisor may round the actual
- * timeout to a value larger than the requested timeout, consequently the
- * 'time remaining' return value may be larger than the previously requested
- * timeout value.
- *
- * Any guest OS debugger should be aware that the watchdog service may be in
- * use. Consequently, it is recommended that the watchdog service is
- * disabled upon debugger entry (e.g. reaching a breakpoint), and then
- * re-enabled upon returning to normal execution. The API has been designed
- * with this in mind, and the 'time remaining' result of the disable call may
- * be used directly as the timeout argument of the re-enable call.
- */
-#define HV_FAST_MACH_SET_WATCHDOG 0x05
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
- unsigned long *orig_timeout);
-#endif
-
-/* CPU services.
- *
- * CPUs represent devices that can execute software threads. A single
- * chip that contains multiple cores or strands is represented as
- * multiple CPUs with unique CPU identifiers. CPUs are exported to
- * OBP via the machine description (and to the OS via the OBP device
- * tree). CPUs are always in one of three states: stopped, running,
- * or error.
- *
- * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
- * CPU within a logical domain. Operations that are to be performed
- * on multiple CPUs specify them via a CPU list. A CPU list is an
- * array in real memory, of which each 16-bit word is a CPU ID. CPU
- * lists are passed through the API as two arguments. The first is
- * the number of entries (16-bit words) in the CPU list, and the
- * second is the (real address) pointer to the CPU ID list.
- */
-
-/* cpu_start()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CPU_START
- * ARG0: CPU ID
- * ARG1: PC
- * ARG2: RTBA
- * ARG3: target ARG0
- * RET0: status
- * ERRORS: ENOCPU Invalid CPU ID
- * EINVAL Target CPU ID is not in the stopped state
- * ENORADDR Invalid PC or RTBA real address
- * EBADALIGN Unaligned PC or unaligned RTBA
- * EWOULDBLOCK Starting resources are not available
- *
- * Start CPU with given CPU ID with PC in %pc and with a real trap
- * base address value of RTBA. The indicated CPU must be in the
- * stopped state. The supplied RTBA must be aligned on a 256 byte
- * boundary. On successful completion, the specified CPU will be in
- * the running state and will be supplied with "target ARG0" in %o0
- * and RTBA in %tba.
- */
-#define HV_FAST_CPU_START 0x10
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_cpu_start(unsigned long cpuid,
- unsigned long pc,
- unsigned long rtba,
- unsigned long arg0);
-#endif
-
-/* cpu_stop()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CPU_STOP
- * ARG0: CPU ID
- * RET0: status
- * ERRORS: ENOCPU Invalid CPU ID
- * EINVAL Target CPU ID is the current cpu
- * EINVAL Target CPU ID is not in the running state
- * EWOULDBLOCK Stopping resources are not available
- * ENOTSUPPORTED Not supported on this platform
- *
- * The specified CPU is stopped. The indicated CPU must be in the
- * running state. On completion, it will be in the stopped state. It
- * is not legal to stop the current CPU.
- *
- * Note: As this service cannot be used to stop the current cpu, this service
- * may not be used to stop the last running CPU in a domain. To stop
- * and exit a running domain, a guest must use the mach_exit() service.
- */
-#define HV_FAST_CPU_STOP 0x11
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_cpu_stop(unsigned long cpuid);
-#endif
-
-/* cpu_yield()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CPU_YIELD
- * RET0: status
- * ERRORS: No possible error.
- *
- * Suspend execution on the current CPU. Execution will resume when
- * an interrupt (device, %stick_compare, or cross-call) is targeted to
- * the CPU. On some CPUs, this API may be used by the hypervisor to
- * save power by disabling hardware strands.
- */
-#define HV_FAST_CPU_YIELD 0x12
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_cpu_yield(void);
-#endif
-
-/* cpu_qconf()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CPU_QCONF
- * ARG0: queue
- * ARG1: base real address
- * ARG2: number of entries
- * RET0: status
- * ERRORS: ENORADDR Invalid base real address
- * EINVAL Invalid queue or number of entries is less
- * than 2 or too large.
- * EBADALIGN Base real address is not correctly aligned
- * for size.
- *
- * Configure the given queue to be placed at the given base real
- * address, with the given number of entries. The number of entries
- * must be a power of 2. The base real address must be aligned
- * exactly to match the queue size. Each queue entry is 64 bytes
- * long, so for example a 32 entry queue must be aligned on a 2048
- * byte real address boundary.
- *
- * The specified queue is unconfigured if the number of entries is given
- * as zero.
- *
- * For the current version of this API service, the argument queue is defined
- * as follows:
- *
- * queue description
- * ----- -------------------------
- * 0x3c cpu mondo queue
- * 0x3d device mondo queue
- * 0x3e resumable error queue
- * 0x3f non-resumable error queue
- *
- * Note: The maximum number of entries for each queue for a specific cpu may
- * be determined from the machine description.
- */
-#define HV_FAST_CPU_QCONF 0x14
-#define HV_CPU_QUEUE_CPU_MONDO 0x3c
-#define HV_CPU_QUEUE_DEVICE_MONDO 0x3d
-#define HV_CPU_QUEUE_RES_ERROR 0x3e
-#define HV_CPU_QUEUE_NONRES_ERROR 0x3f
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_cpu_qconf(unsigned long type,
- unsigned long queue_paddr,
- unsigned long num_queue_entries);
-#endif
-
-/* cpu_qinfo()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CPU_QINFO
- * ARG0: queue
- * RET0: status
- * RET1: base real address
- * RET1: number of entries
- * ERRORS: EINVAL Invalid queue
- *
- * Return the configuration info for the given queue. The base real
- * address and number of entries of the defined queue are returned.
- * The queue argument values are the same as for cpu_qconf() above.
- *
- * If the specified queue is a valid queue number, but no queue has
- * been defined, the number of entries will be set to zero and the
- * base real address returned is undefined.
- */
-#define HV_FAST_CPU_QINFO 0x15
-
-/* cpu_mondo_send()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CPU_MONDO_SEND
- * ARG0-1: CPU list
- * ARG2: data real address
- * RET0: status
- * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list
- * is not 2-byte aligned.
- * ENORADDR Invalid data mondo address, or invalid cpu list
- * address.
- * ENOCPU Invalid cpu in CPU list
- * EWOULDBLOCK Some or all of the listed CPUs did not receive
- * the mondo
- * ECPUERROR One or more of the listed CPUs are in error
- * state, use HV_FAST_CPU_STATE to see which ones
- * EINVAL CPU list includes caller's CPU ID
- *
- * Send a mondo interrupt to the CPUs in the given CPU list with the
- * 64-bytes at the given data real address. The data must be 64-byte
- * aligned. The mondo data will be delivered to the cpu_mondo queues
- * of the recipient CPUs.
- *
- * In all cases, error or not, the CPUs in the CPU list to which the
- * mondo has been successfully delivered will be indicated by having
- * their entry in CPU list updated with the value 0xffff.
- */
-#define HV_FAST_CPU_MONDO_SEND 0x42
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count, unsigned long cpu_list_pa, unsigned long mondo_block_pa);
-#endif
-
-/* cpu_myid()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CPU_MYID
- * RET0: status
- * RET1: CPU ID
- * ERRORS: No errors defined.
- *
- * Return the hypervisor ID handle for the current CPU. Use by a
- * virtual CPU to discover it's own identity.
- */
-#define HV_FAST_CPU_MYID 0x16
-
-/* cpu_state()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CPU_STATE
- * ARG0: CPU ID
- * RET0: status
- * RET1: state
- * ERRORS: ENOCPU Invalid CPU ID
- *
- * Retrieve the current state of the CPU with the given CPU ID.
- */
-#define HV_FAST_CPU_STATE 0x17
-#define HV_CPU_STATE_STOPPED 0x01
-#define HV_CPU_STATE_RUNNING 0x02
-#define HV_CPU_STATE_ERROR 0x03
-
-#ifndef __ASSEMBLY__
-extern long sun4v_cpu_state(unsigned long cpuid);
-#endif
-
-/* cpu_set_rtba()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CPU_SET_RTBA
- * ARG0: RTBA
- * RET0: status
- * RET1: previous RTBA
- * ERRORS: ENORADDR Invalid RTBA real address
- * EBADALIGN RTBA is incorrectly aligned for a trap table
- *
- * Set the real trap base address of the local cpu to the given RTBA.
- * The supplied RTBA must be aligned on a 256 byte boundary. Upon
- * success the previous value of the RTBA is returned in RET1.
- *
- * Note: This service does not affect %tba
- */
-#define HV_FAST_CPU_SET_RTBA 0x18
-
-/* cpu_set_rtba()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CPU_GET_RTBA
- * RET0: status
- * RET1: previous RTBA
- * ERRORS: No possible error.
- *
- * Returns the current value of RTBA in RET1.
- */
-#define HV_FAST_CPU_GET_RTBA 0x19
-
-/* MMU services.
- *
- * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
- */
-#ifndef __ASSEMBLY__
-struct hv_tsb_descr {
- unsigned short pgsz_idx;
- unsigned short assoc;
- unsigned int num_ttes; /* in TTEs */
- unsigned int ctx_idx;
- unsigned int pgsz_mask;
- unsigned long tsb_base;
- unsigned long resv;
-};
-#endif
-#define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00
-#define HV_TSB_DESCR_ASSOC_OFFSET 0x02
-#define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04
-#define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08
-#define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c
-#define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10
-#define HV_TSB_DESCR_RESV_OFFSET 0x18
-
-/* Page size bitmask. */
-#define HV_PGSZ_MASK_8K (1 << 0)
-#define HV_PGSZ_MASK_64K (1 << 1)
-#define HV_PGSZ_MASK_512K (1 << 2)
-#define HV_PGSZ_MASK_4MB (1 << 3)
-#define HV_PGSZ_MASK_32MB (1 << 4)
-#define HV_PGSZ_MASK_256MB (1 << 5)
-#define HV_PGSZ_MASK_2GB (1 << 6)
-#define HV_PGSZ_MASK_16GB (1 << 7)
-
-/* Page size index. The value given in the TSB descriptor must correspond
- * to the smallest page size specified in the pgsz_mask page size bitmask.
- */
-#define HV_PGSZ_IDX_8K 0
-#define HV_PGSZ_IDX_64K 1
-#define HV_PGSZ_IDX_512K 2
-#define HV_PGSZ_IDX_4MB 3
-#define HV_PGSZ_IDX_32MB 4
-#define HV_PGSZ_IDX_256MB 5
-#define HV_PGSZ_IDX_2GB 6
-#define HV_PGSZ_IDX_16GB 7
-
-/* MMU fault status area.
- *
- * MMU related faults have their status and fault address information
- * placed into a memory region made available by privileged code. Each
- * virtual processor must make a mmu_fault_area_conf() call to tell the
- * hypervisor where that processor's fault status should be stored.
- *
- * The fault status block is a multiple of 64-bytes and must be aligned
- * on a 64-byte boundary.
- */
-#ifndef __ASSEMBLY__
-struct hv_fault_status {
- unsigned long i_fault_type;
- unsigned long i_fault_addr;
- unsigned long i_fault_ctx;
- unsigned long i_reserved[5];
- unsigned long d_fault_type;
- unsigned long d_fault_addr;
- unsigned long d_fault_ctx;
- unsigned long d_reserved[5];
-};
-#endif
-#define HV_FAULT_I_TYPE_OFFSET 0x00
-#define HV_FAULT_I_ADDR_OFFSET 0x08
-#define HV_FAULT_I_CTX_OFFSET 0x10
-#define HV_FAULT_D_TYPE_OFFSET 0x40
-#define HV_FAULT_D_ADDR_OFFSET 0x48
-#define HV_FAULT_D_CTX_OFFSET 0x50
-
-#define HV_FAULT_TYPE_FAST_MISS 1
-#define HV_FAULT_TYPE_FAST_PROT 2
-#define HV_FAULT_TYPE_MMU_MISS 3
-#define HV_FAULT_TYPE_INV_RA 4
-#define HV_FAULT_TYPE_PRIV_VIOL 5
-#define HV_FAULT_TYPE_PROT_VIOL 6
-#define HV_FAULT_TYPE_NFO 7
-#define HV_FAULT_TYPE_NFO_SEFF 8
-#define HV_FAULT_TYPE_INV_VA 9
-#define HV_FAULT_TYPE_INV_ASI 10
-#define HV_FAULT_TYPE_NC_ATOMIC 11
-#define HV_FAULT_TYPE_PRIV_ACT 12
-#define HV_FAULT_TYPE_RESV1 13
-#define HV_FAULT_TYPE_UNALIGNED 14
-#define HV_FAULT_TYPE_INV_PGSZ 15
-/* Values 16 --> -2 are reserved. */
-#define HV_FAULT_TYPE_MULTIPLE -1
-
-/* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
- * and mmu_{map,unmap}_perm_addr().
- */
-#define HV_MMU_DMMU 0x01
-#define HV_MMU_IMMU 0x02
-#define HV_MMU_ALL (HV_MMU_DMMU | HV_MMU_IMMU)
-
-/* mmu_map_addr()
- * TRAP: HV_MMU_MAP_ADDR_TRAP
- * ARG0: virtual address
- * ARG1: mmu context
- * ARG2: TTE
- * ARG3: flags (HV_MMU_{IMMU,DMMU})
- * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
- * EBADPGSZ Invalid page size value
- * ENORADDR Invalid real address in TTE
- *
- * Create a non-permanent mapping using the given TTE, virtual
- * address, and mmu context. The flags argument determines which
- * (data, or instruction, or both) TLB the mapping gets loaded into.
- *
- * The behavior is undefined if the valid bit is clear in the TTE.
- *
- * Note: This API call is for privileged code to specify temporary translation
- * mappings without the need to create and manage a TSB.
- */
-
-/* mmu_unmap_addr()
- * TRAP: HV_MMU_UNMAP_ADDR_TRAP
- * ARG0: virtual address
- * ARG1: mmu context
- * ARG2: flags (HV_MMU_{IMMU,DMMU})
- * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
- *
- * Demaps the given virtual address in the given mmu context on this
- * CPU. This function is intended to be used to demap pages mapped
- * with mmu_map_addr. This service is equivalent to invoking
- * mmu_demap_page() with only the current CPU in the CPU list. The
- * flags argument determines which (data, or instruction, or both) TLB
- * the mapping gets unmapped from.
- *
- * Attempting to perform an unmap operation for a previously defined
- * permanent mapping will have undefined results.
- */
-
-/* mmu_tsb_ctx0()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMU_TSB_CTX0
- * ARG0: number of TSB descriptions
- * ARG1: TSB descriptions pointer
- * RET0: status
- * ERRORS: ENORADDR Invalid TSB descriptions pointer or
- * TSB base within a descriptor
- * EBADALIGN TSB descriptions pointer is not aligned
- * to an 8-byte boundary, or TSB base
- * within a descriptor is not aligned for
- * the given TSB size
- * EBADPGSZ Invalid page size in a TSB descriptor
- * EBADTSB Invalid associativity or size in a TSB
- * descriptor
- * EINVAL Invalid number of TSB descriptions, or
- * invalid context index in a TSB
- * descriptor, or index page size not
- * equal to smallest page size in page
- * size bitmask field.
- *
- * Configures the TSBs for the current CPU for virtual addresses with
- * context zero. The TSB descriptions pointer is a pointer to an
- * array of the given number of TSB descriptions.
- *
- * Note: The maximum number of TSBs available to a virtual CPU is given by the
- * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
- * machine description.
- */
-#define HV_FAST_MMU_TSB_CTX0 0x20
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
- unsigned long tsb_desc_ra);
-#endif
-
-/* mmu_tsb_ctxnon0()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMU_TSB_CTXNON0
- * ARG0: number of TSB descriptions
- * ARG1: TSB descriptions pointer
- * RET0: status
- * ERRORS: Same as for mmu_tsb_ctx0() above.
- *
- * Configures the TSBs for the current CPU for virtual addresses with
- * non-zero contexts. The TSB descriptions pointer is a pointer to an
- * array of the given number of TSB descriptions.
- *
- * Note: A maximum of 16 TSBs may be specified in the TSB description list.
- */
-#define HV_FAST_MMU_TSB_CTXNON0 0x21
-
-/* mmu_demap_page()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMU_DEMAP_PAGE
- * ARG0: reserved, must be zero
- * ARG1: reserved, must be zero
- * ARG2: virtual address
- * ARG3: mmu context
- * ARG4: flags (HV_MMU_{IMMU,DMMU})
- * RET0: status
- * ERRORS: EINVAL Invalid virutal address, context, or
- * flags value
- * ENOTSUPPORTED ARG0 or ARG1 is non-zero
- *
- * Demaps any page mapping of the given virtual address in the given
- * mmu context for the current virtual CPU. Any virtually tagged
- * caches are guaranteed to be kept consistent. The flags argument
- * determines which TLB (instruction, or data, or both) participate in
- * the operation.
- *
- * ARG0 and ARG1 are both reserved and must be set to zero.
- */
-#define HV_FAST_MMU_DEMAP_PAGE 0x22
-
-/* mmu_demap_ctx()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMU_DEMAP_CTX
- * ARG0: reserved, must be zero
- * ARG1: reserved, must be zero
- * ARG2: mmu context
- * ARG3: flags (HV_MMU_{IMMU,DMMU})
- * RET0: status
- * ERRORS: EINVAL Invalid context or flags value
- * ENOTSUPPORTED ARG0 or ARG1 is non-zero
- *
- * Demaps all non-permanent virtual page mappings previously specified
- * for the given context for the current virtual CPU. Any virtual
- * tagged caches are guaranteed to be kept consistent. The flags
- * argument determines which TLB (instruction, or data, or both)
- * participate in the operation.
- *
- * ARG0 and ARG1 are both reserved and must be set to zero.
- */
-#define HV_FAST_MMU_DEMAP_CTX 0x23
-
-/* mmu_demap_all()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMU_DEMAP_ALL
- * ARG0: reserved, must be zero
- * ARG1: reserved, must be zero
- * ARG2: flags (HV_MMU_{IMMU,DMMU})
- * RET0: status
- * ERRORS: EINVAL Invalid flags value
- * ENOTSUPPORTED ARG0 or ARG1 is non-zero
- *
- * Demaps all non-permanent virtual page mappings previously specified
- * for the current virtual CPU. Any virtual tagged caches are
- * guaranteed to be kept consistent. The flags argument determines
- * which TLB (instruction, or data, or both) participate in the
- * operation.
- *
- * ARG0 and ARG1 are both reserved and must be set to zero.
- */
-#define HV_FAST_MMU_DEMAP_ALL 0x24
-
-#ifndef __ASSEMBLY__
-extern void sun4v_mmu_demap_all(void);
-#endif
-
-/* mmu_map_perm_addr()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMU_MAP_PERM_ADDR
- * ARG0: virtual address
- * ARG1: reserved, must be zero
- * ARG2: TTE
- * ARG3: flags (HV_MMU_{IMMU,DMMU})
- * RET0: status
- * ERRORS: EINVAL Invalid virutal address or flags value
- * EBADPGSZ Invalid page size value
- * ENORADDR Invalid real address in TTE
- * ETOOMANY Too many mappings (max of 8 reached)
- *
- * Create a permanent mapping using the given TTE and virtual address
- * for context 0 on the calling virtual CPU. A maximum of 8 such
- * permanent mappings may be specified by privileged code. Mappings
- * may be removed with mmu_unmap_perm_addr().
- *
- * The behavior is undefined if a TTE with the valid bit clear is given.
- *
- * Note: This call is used to specify address space mappings for which
- * privileged code does not expect to receive misses. For example,
- * this mechanism can be used to map kernel nucleus code and data.
- */
-#define HV_FAST_MMU_MAP_PERM_ADDR 0x25
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
- unsigned long set_to_zero,
- unsigned long tte,
- unsigned long flags);
-#endif
-
-/* mmu_fault_area_conf()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF
- * ARG0: real address
- * RET0: status
- * RET1: previous mmu fault area real address
- * ERRORS: ENORADDR Invalid real address
- * EBADALIGN Invalid alignment for fault area
- *
- * Configure the MMU fault status area for the calling CPU. A 64-byte
- * aligned real address specifies where MMU fault status information
- * is placed. The return value is the previously specified area, or 0
- * for the first invocation. Specifying a fault area at real address
- * 0 is not allowed.
- */
-#define HV_FAST_MMU_FAULT_AREA_CONF 0x26
-
-/* mmu_enable()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMU_ENABLE
- * ARG0: enable flag
- * ARG1: return target address
- * RET0: status
- * ERRORS: ENORADDR Invalid real address when disabling
- * translation.
- * EBADALIGN The return target address is not
- * aligned to an instruction.
- * EINVAL The enable flag request the current
- * operating mode (e.g. disable if already
- * disabled)
- *
- * Enable or disable virtual address translation for the calling CPU
- * within the virtual machine domain. If the enable flag is zero,
- * translation is disabled, any non-zero value will enable
- * translation.
- *
- * When this function returns, the newly selected translation mode
- * will be active. If the mmu is being enabled, then the return
- * target address is a virtual address else it is a real address.
- *
- * Upon successful completion, control will be returned to the given
- * return target address (ie. the cpu will jump to that address). On
- * failure, the previous mmu mode remains and the trap simply returns
- * as normal with the appropriate error code in RET0.
- */
-#define HV_FAST_MMU_ENABLE 0x27
-
-/* mmu_unmap_perm_addr()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMU_UNMAP_PERM_ADDR
- * ARG0: virtual address
- * ARG1: reserved, must be zero
- * ARG2: flags (HV_MMU_{IMMU,DMMU})
- * RET0: status
- * ERRORS: EINVAL Invalid virutal address or flags value
- * ENOMAP Specified mapping was not found
- *
- * Demaps any permanent page mapping (established via
- * mmu_map_perm_addr()) at the given virtual address for context 0 on
- * the current virtual CPU. Any virtual tagged caches are guaranteed
- * to be kept consistent.
- */
-#define HV_FAST_MMU_UNMAP_PERM_ADDR 0x28
-
-/* mmu_tsb_ctx0_info()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMU_TSB_CTX0_INFO
- * ARG0: max TSBs
- * ARG1: buffer pointer
- * RET0: status
- * RET1: number of TSBs
- * ERRORS: EINVAL Supplied buffer is too small
- * EBADALIGN The buffer pointer is badly aligned
- * ENORADDR Invalid real address for buffer pointer
- *
- * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
- * into the provided buffer. The size of the buffer is given in ARG1
- * in terms of the number of TSB description entries.
- *
- * Upon return, RET1 always contains the number of TSB descriptions
- * previously configured. If zero TSBs were configured, EOK is
- * returned with RET1 containing 0.
- */
-#define HV_FAST_MMU_TSB_CTX0_INFO 0x29
-
-/* mmu_tsb_ctxnon0_info()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMU_TSB_CTXNON0_INFO
- * ARG0: max TSBs
- * ARG1: buffer pointer
- * RET0: status
- * RET1: number of TSBs
- * ERRORS: EINVAL Supplied buffer is too small
- * EBADALIGN The buffer pointer is badly aligned
- * ENORADDR Invalid real address for buffer pointer
- *
- * Return the TSB configuration as previous defined by
- * mmu_tsb_ctxnon0() into the provided buffer. The size of the buffer
- * is given in ARG1 in terms of the number of TSB description entries.
- *
- * Upon return, RET1 always contains the number of TSB descriptions
- * previously configured. If zero TSBs were configured, EOK is
- * returned with RET1 containing 0.
- */
-#define HV_FAST_MMU_TSB_CTXNON0_INFO 0x2a
-
-/* mmu_fault_area_info()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMU_FAULT_AREA_INFO
- * RET0: status
- * RET1: fault area real address
- * ERRORS: No errors defined.
- *
- * Return the currently defined MMU fault status area for the current
- * CPU. The real address of the fault status area is returned in
- * RET1, or 0 is returned in RET1 if no fault status area is defined.
- *
- * Note: mmu_fault_area_conf() may be called with the return value (RET1)
- * from this service if there is a need to save and restore the fault
- * area for a cpu.
- */
-#define HV_FAST_MMU_FAULT_AREA_INFO 0x2b
-
-/* Cache and Memory services. */
-
-/* mem_scrub()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MEM_SCRUB
- * ARG0: real address
- * ARG1: length
- * RET0: status
- * RET1: length scrubbed
- * ERRORS: ENORADDR Invalid real address
- * EBADALIGN Start address or length are not correctly
- * aligned
- * EINVAL Length is zero
- *
- * Zero the memory contents in the range real address to real address
- * plus length minus 1. Also, valid ECC will be generated for that
- * memory address range. Scrubbing is started at the given real
- * address, but may not scrub the entire given length. The actual
- * length scrubbed will be returned in RET1.
- *
- * The real address and length must be aligned on an 8K boundary, or
- * contain the start address and length from a sun4v error report.
- *
- * Note: There are two uses for this function. The first use is to block clear
- * and initialize memory and the second is to scrub an u ncorrectable
- * error reported via a resumable or non-resumable trap. The second
- * use requires the arguments to be equal to the real address and length
- * provided in a sun4v memory error report.
- */
-#define HV_FAST_MEM_SCRUB 0x31
-
-/* mem_sync()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MEM_SYNC
- * ARG0: real address
- * ARG1: length
- * RET0: status
- * RET1: length synced
- * ERRORS: ENORADDR Invalid real address
- * EBADALIGN Start address or length are not correctly
- * aligned
- * EINVAL Length is zero
- *
- * Force the next access within the real address to real address plus
- * length minus 1 to be fetches from main system memory. Less than
- * the given length may be synced, the actual amount synced is
- * returned in RET1. The real address and length must be aligned on
- * an 8K boundary.
- */
-#define HV_FAST_MEM_SYNC 0x32
-
-/* Time of day services.
- *
- * The hypervisor maintains the time of day on a per-domain basis.
- * Changing the time of day in one domain does not affect the time of
- * day on any other domain.
- *
- * Time is described by a single unsigned 64-bit word which is the
- * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
- * 1970).
- */
-
-/* tod_get()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_TOD_GET
- * RET0: status
- * RET1: TOD
- * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
- * ENOTSUPPORTED If TOD not supported on this platform
- *
- * Return the current time of day. May block if TOD access is
- * temporarily not possible.
- */
-#define HV_FAST_TOD_GET 0x50
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_tod_get(unsigned long *time);
-#endif
-
-/* tod_set()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_TOD_SET
- * ARG0: TOD
- * RET0: status
- * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
- * ENOTSUPPORTED If TOD not supported on this platform
- *
- * The current time of day is set to the value specified in ARG0. May
- * block if TOD access is temporarily not possible.
- */
-#define HV_FAST_TOD_SET 0x51
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_tod_set(unsigned long time);
-#endif
-
-/* Console services */
-
-/* con_getchar()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CONS_GETCHAR
- * RET0: status
- * RET1: character
- * ERRORS: EWOULDBLOCK No character available.
- *
- * Returns a character from the console device. If no character is
- * available then an EWOULDBLOCK error is returned. If a character is
- * available, then the returned status is EOK and the character value
- * is in RET1.
- *
- * A virtual BREAK is represented by the 64-bit value -1.
- *
- * A virtual HUP signal is represented by the 64-bit value -2.
- */
-#define HV_FAST_CONS_GETCHAR 0x60
-
-/* con_putchar()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CONS_PUTCHAR
- * ARG0: character
- * RET0: status
- * ERRORS: EINVAL Illegal character
- * EWOULDBLOCK Output buffer currently full, would block
- *
- * Send a character to the console device. Only character values
- * between 0 and 255 may be used. Values outside this range are
- * invalid except for the 64-bit value -1 which is used to send a
- * virtual BREAK.
- */
-#define HV_FAST_CONS_PUTCHAR 0x61
-
-/* con_read()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CONS_READ
- * ARG0: buffer real address
- * ARG1: buffer size in bytes
- * RET0: status
- * RET1: bytes read or BREAK or HUP
- * ERRORS: EWOULDBLOCK No character available.
- *
- * Reads characters into a buffer from the console device. If no
- * character is available then an EWOULDBLOCK error is returned.
- * If a character is available, then the returned status is EOK
- * and the number of bytes read into the given buffer is provided
- * in RET1.
- *
- * A virtual BREAK is represented by the 64-bit RET1 value -1.
- *
- * A virtual HUP signal is represented by the 64-bit RET1 value -2.
- *
- * If BREAK or HUP are indicated, no bytes were read into buffer.
- */
-#define HV_FAST_CONS_READ 0x62
-
-/* con_write()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_CONS_WRITE
- * ARG0: buffer real address
- * ARG1: buffer size in bytes
- * RET0: status
- * RET1: bytes written
- * ERRORS: EWOULDBLOCK Output buffer currently full, would block
- *
- * Send a characters in buffer to the console device. Breaks must be
- * sent using con_putchar().
- */
-#define HV_FAST_CONS_WRITE 0x63
-
-#ifndef __ASSEMBLY__
-extern long sun4v_con_getchar(long *status);
-extern long sun4v_con_putchar(long c);
-extern long sun4v_con_read(unsigned long buffer,
- unsigned long size,
- unsigned long *bytes_read);
-extern unsigned long sun4v_con_write(unsigned long buffer,
- unsigned long size,
- unsigned long *bytes_written);
-#endif
-
-/* mach_set_soft_state()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
- * ARG0: software state
- * ARG1: software state description pointer
- * RET0: status
- * ERRORS: EINVAL software state not valid or software state
- * description is not NULL terminated
- * ENORADDR software state description pointer is not a
- * valid real address
- * EBADALIGNED software state description is not correctly
- * aligned
- *
- * This allows the guest to report it's soft state to the hypervisor. There
- * are two primary components to this state. The first part states whether
- * the guest software is running or not. The second containts optional
- * details specific to the software.
- *
- * The software state argument is defined below in HV_SOFT_STATE_*, and
- * indicates whether the guest is operating normally or in a transitional
- * state.
- *
- * The software state description argument is a real address of a data buffer
- * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
- * terminated 7-bit ASCII string of up to 31 characters not including the
- * NULL termination.
- */
-#define HV_FAST_MACH_SET_SOFT_STATE 0x70
-#define HV_SOFT_STATE_NORMAL 0x01
-#define HV_SOFT_STATE_TRANSITION 0x02
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
- unsigned long msg_string_ra);
-#endif
-
-/* mach_get_soft_state()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
- * ARG0: software state description pointer
- * RET0: status
- * RET1: software state
- * ERRORS: ENORADDR software state description pointer is not a
- * valid real address
- * EBADALIGNED software state description is not correctly
- * aligned
- *
- * Retrieve the current value of the guest's software state. The rules
- * for the software state pointer are the same as for mach_set_soft_state()
- * above.
- */
-#define HV_FAST_MACH_GET_SOFT_STATE 0x71
-
-/* svc_send()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_SVC_SEND
- * ARG0: service ID
- * ARG1: buffer real address
- * ARG2: buffer size
- * RET0: STATUS
- * RET1: sent_bytes
- *
- * Be careful, all output registers are clobbered by this operation,
- * so for example it is not possible to save away a value in %o4
- * across the trap.
- */
-#define HV_FAST_SVC_SEND 0x80
-
-/* svc_recv()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_SVC_RECV
- * ARG0: service ID
- * ARG1: buffer real address
- * ARG2: buffer size
- * RET0: STATUS
- * RET1: recv_bytes
- *
- * Be careful, all output registers are clobbered by this operation,
- * so for example it is not possible to save away a value in %o4
- * across the trap.
- */
-#define HV_FAST_SVC_RECV 0x81
-
-/* svc_getstatus()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_SVC_GETSTATUS
- * ARG0: service ID
- * RET0: STATUS
- * RET1: status bits
- */
-#define HV_FAST_SVC_GETSTATUS 0x82
-
-/* svc_setstatus()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_SVC_SETSTATUS
- * ARG0: service ID
- * ARG1: bits to set
- * RET0: STATUS
- */
-#define HV_FAST_SVC_SETSTATUS 0x83
-
-/* svc_clrstatus()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_SVC_CLRSTATUS
- * ARG0: service ID
- * ARG1: bits to clear
- * RET0: STATUS
- */
-#define HV_FAST_SVC_CLRSTATUS 0x84
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_svc_send(unsigned long svc_id,
- unsigned long buffer,
- unsigned long buffer_size,
- unsigned long *sent_bytes);
-extern unsigned long sun4v_svc_recv(unsigned long svc_id,
- unsigned long buffer,
- unsigned long buffer_size,
- unsigned long *recv_bytes);
-extern unsigned long sun4v_svc_getstatus(unsigned long svc_id,
- unsigned long *status_bits);
-extern unsigned long sun4v_svc_setstatus(unsigned long svc_id,
- unsigned long status_bits);
-extern unsigned long sun4v_svc_clrstatus(unsigned long svc_id,
- unsigned long status_bits);
-#endif
-
-/* Trap trace services.
- *
- * The hypervisor provides a trap tracing capability for privileged
- * code running on each virtual CPU. Privileged code provides a
- * round-robin trap trace queue within which the hypervisor writes
- * 64-byte entries detailing hyperprivileged traps taken n behalf of
- * privileged code. This is provided as a debugging capability for
- * privileged code.
- *
- * The trap trace control structure is 64-bytes long and placed at the
- * start (offset 0) of the trap trace buffer, and is described as
- * follows:
- */
-#ifndef __ASSEMBLY__
-struct hv_trap_trace_control {
- unsigned long head_offset;
- unsigned long tail_offset;
- unsigned long __reserved[0x30 / sizeof(unsigned long)];
-};
-#endif
-#define HV_TRAP_TRACE_CTRL_HEAD_OFFSET 0x00
-#define HV_TRAP_TRACE_CTRL_TAIL_OFFSET 0x08
-
-/* The head offset is the offset of the most recently completed entry
- * in the trap-trace buffer. The tail offset is the offset of the
- * next entry to be written. The control structure is owned and
- * modified by the hypervisor. A guest may not modify the control
- * structure contents. Attempts to do so will result in undefined
- * behavior for the guest.
- *
- * Each trap trace buffer entry is layed out as follows:
- */
-#ifndef __ASSEMBLY__
-struct hv_trap_trace_entry {
- unsigned char type; /* Hypervisor or guest entry? */
- unsigned char hpstate; /* Hyper-privileged state */
- unsigned char tl; /* Trap level */
- unsigned char gl; /* Global register level */
- unsigned short tt; /* Trap type */
- unsigned short tag; /* Extended trap identifier */
- unsigned long tstate; /* Trap state */
- unsigned long tick; /* Tick */
- unsigned long tpc; /* Trap PC */
- unsigned long f1; /* Entry specific */
- unsigned long f2; /* Entry specific */
- unsigned long f3; /* Entry specific */
- unsigned long f4; /* Entry specific */
-};
-#endif
-#define HV_TRAP_TRACE_ENTRY_TYPE 0x00
-#define HV_TRAP_TRACE_ENTRY_HPSTATE 0x01
-#define HV_TRAP_TRACE_ENTRY_TL 0x02
-#define HV_TRAP_TRACE_ENTRY_GL 0x03
-#define HV_TRAP_TRACE_ENTRY_TT 0x04
-#define HV_TRAP_TRACE_ENTRY_TAG 0x06
-#define HV_TRAP_TRACE_ENTRY_TSTATE 0x08
-#define HV_TRAP_TRACE_ENTRY_TICK 0x10
-#define HV_TRAP_TRACE_ENTRY_TPC 0x18
-#define HV_TRAP_TRACE_ENTRY_F1 0x20
-#define HV_TRAP_TRACE_ENTRY_F2 0x28
-#define HV_TRAP_TRACE_ENTRY_F3 0x30
-#define HV_TRAP_TRACE_ENTRY_F4 0x38
-
-/* The type field is encoded as follows. */
-#define HV_TRAP_TYPE_UNDEF 0x00 /* Entry content undefined */
-#define HV_TRAP_TYPE_HV 0x01 /* Hypervisor trap entry */
-#define HV_TRAP_TYPE_GUEST 0xff /* Added via ttrace_addentry() */
-
-/* ttrace_buf_conf()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_TTRACE_BUF_CONF
- * ARG0: real address
- * ARG1: number of entries
- * RET0: status
- * RET1: number of entries
- * ERRORS: ENORADDR Invalid real address
- * EINVAL Size is too small
- * EBADALIGN Real address not aligned on 64-byte boundary
- *
- * Requests hypervisor trap tracing and declares a virtual CPU's trap
- * trace buffer to the hypervisor. The real address supplies the real
- * base address of the trap trace queue and must be 64-byte aligned.
- * Specifying a value of 0 for the number of entries disables trap
- * tracing for the calling virtual CPU. The buffer allocated must be
- * sized for a power of two number of 64-byte trap trace entries plus
- * an initial 64-byte control structure.
- *
- * This may be invoked any number of times so that a virtual CPU may
- * relocate a trap trace buffer or create "snapshots" of information.
- *
- * If the real address is illegal or badly aligned, then trap tracing
- * is disabled and an error is returned.
- *
- * Upon failure with EINVAL, this service call returns in RET1 the
- * minimum number of buffer entries required. Upon other failures
- * RET1 is undefined.
- */
-#define HV_FAST_TTRACE_BUF_CONF 0x90
-
-/* ttrace_buf_info()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_TTRACE_BUF_INFO
- * RET0: status
- * RET1: real address
- * RET2: size
- * ERRORS: None defined.
- *
- * Returns the size and location of the previously declared trap-trace
- * buffer. In the event that no buffer was previously defined, or the
- * buffer is disabled, this call will return a size of zero bytes.
- */
-#define HV_FAST_TTRACE_BUF_INFO 0x91
-
-/* ttrace_enable()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_TTRACE_ENABLE
- * ARG0: enable
- * RET0: status
- * RET1: previous enable state
- * ERRORS: EINVAL No trap trace buffer currently defined
- *
- * Enable or disable trap tracing, and return the previous enabled
- * state in RET1. Future systems may define various flags for the
- * enable argument (ARG0), for the moment a guest should pass
- * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
- * tracing - which will ensure future compatability.
- */
-#define HV_FAST_TTRACE_ENABLE 0x92
-
-/* ttrace_freeze()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_TTRACE_FREEZE
- * ARG0: freeze
- * RET0: status
- * RET1: previous freeze state
- * ERRORS: EINVAL No trap trace buffer currently defined
- *
- * Freeze or unfreeze trap tracing, returning the previous freeze
- * state in RET1. A guest should pass a non-zero value to freeze and
- * a zero value to unfreeze all tracing. The returned previous state
- * is 0 for not frozen and 1 for frozen.
- */
-#define HV_FAST_TTRACE_FREEZE 0x93
-
-/* ttrace_addentry()
- * TRAP: HV_TTRACE_ADDENTRY_TRAP
- * ARG0: tag (16-bits)
- * ARG1: data word 0
- * ARG2: data word 1
- * ARG3: data word 2
- * ARG4: data word 3
- * RET0: status
- * ERRORS: EINVAL No trap trace buffer currently defined
- *
- * Add an entry to the trap trace buffer. Upon return only ARG0/RET0
- * is modified - none of the other registers holding arguments are
- * volatile across this hypervisor service.
- */
-
-/* Core dump services.
- *
- * Since the hypervisor viraulizes and thus obscures a lot of the
- * physical machine layout and state, traditional OS crash dumps can
- * be difficult to diagnose especially when the problem is a
- * configuration error of some sort.
- *
- * The dump services provide an opaque buffer into which the
- * hypervisor can place it's internal state in order to assist in
- * debugging such situations. The contents are opaque and extremely
- * platform and hypervisor implementation specific. The guest, during
- * a core dump, requests that the hypervisor update any information in
- * the dump buffer in preparation to being dumped as part of the
- * domain's memory image.
- */
-
-/* dump_buf_update()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_DUMP_BUF_UPDATE
- * ARG0: real address
- * ARG1: size
- * RET0: status
- * RET1: required size of dump buffer
- * ERRORS: ENORADDR Invalid real address
- * EBADALIGN Real address is not aligned on a 64-byte
- * boundary
- * EINVAL Size is non-zero but less than minimum size
- * required
- * ENOTSUPPORTED Operation not supported on current logical
- * domain
- *
- * Declare a domain dump buffer to the hypervisor. The real address
- * provided for the domain dump buffer must be 64-byte aligned. The
- * size specifies the size of the dump buffer and may be larger than
- * the minimum size specified in the machine description. The
- * hypervisor will fill the dump buffer with opaque data.
- *
- * Note: A guest may elect to include dump buffer contents as part of a crash
- * dump to assist with debugging. This function may be called any number
- * of times so that a guest may relocate a dump buffer, or create
- * "snapshots" of any dump-buffer information. Each call to
- * dump_buf_update() atomically declares the new dump buffer to the
- * hypervisor.
- *
- * A specified size of 0 unconfigures the dump buffer. If the real
- * address is illegal or badly aligned, then any currently active dump
- * buffer is disabled and an error is returned.
- *
- * In the event that the call fails with EINVAL, RET1 contains the
- * minimum size requires by the hypervisor for a valid dump buffer.
- */
-#define HV_FAST_DUMP_BUF_UPDATE 0x94
-
-/* dump_buf_info()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_DUMP_BUF_INFO
- * RET0: status
- * RET1: real address of current dump buffer
- * RET2: size of current dump buffer
- * ERRORS: No errors defined.
- *
- * Return the currently configures dump buffer description. A
- * returned size of 0 bytes indicates an undefined dump buffer. In
- * this case the return address in RET1 is undefined.
- */
-#define HV_FAST_DUMP_BUF_INFO 0x95
-
-/* Device interrupt services.
- *
- * Device interrupts are allocated to system bus bridges by the hypervisor,
- * and described to OBP in the machine description. OBP then describes
- * these interrupts to the OS via properties in the device tree.
- *
- * Terminology:
- *
- * cpuid Unique opaque value which represents a target cpu.
- *
- * devhandle Device handle. It uniquely identifies a device, and
- * consistes of the lower 28-bits of the hi-cell of the
- * first entry of the device's "reg" property in the
- * OBP device tree.
- *
- * devino Device interrupt number. Specifies the relative
- * interrupt number within the device. The unique
- * combination of devhandle and devino are used to
- * identify a specific device interrupt.
- *
- * Note: The devino value is the same as the values in the
- * "interrupts" property or "interrupt-map" property
- * in the OBP device tree for that device.
- *
- * sysino System interrupt number. A 64-bit unsigned interger
- * representing a unique interrupt within a virtual
- * machine.
- *
- * intr_state A flag representing the interrupt state for a given
- * sysino. The state values are defined below.
- *
- * intr_enabled A flag representing the 'enabled' state for a given
- * sysino. The enable values are defined below.
- */
-
-#define HV_INTR_STATE_IDLE 0 /* Nothing pending */
-#define HV_INTR_STATE_RECEIVED 1 /* Interrupt received by hardware */
-#define HV_INTR_STATE_DELIVERED 2 /* Interrupt delivered to queue */
-
-#define HV_INTR_DISABLED 0 /* sysino not enabled */
-#define HV_INTR_ENABLED 1 /* sysino enabled */
-
-/* intr_devino_to_sysino()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_INTR_DEVINO2SYSINO
- * ARG0: devhandle
- * ARG1: devino
- * RET0: status
- * RET1: sysino
- * ERRORS: EINVAL Invalid devhandle/devino
- *
- * Converts a device specific interrupt number of the given
- * devhandle/devino into a system specific ino (sysino).
- */
-#define HV_FAST_INTR_DEVINO2SYSINO 0xa0
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
- unsigned long devino);
-#endif
-
-/* intr_getenabled()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_INTR_GETENABLED
- * ARG0: sysino
- * RET0: status
- * RET1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
- * ERRORS: EINVAL Invalid sysino
- *
- * Returns interrupt enabled state in RET1 for the interrupt defined
- * by the given sysino.
- */
-#define HV_FAST_INTR_GETENABLED 0xa1
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_intr_getenabled(unsigned long sysino);
-#endif
-
-/* intr_setenabled()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_INTR_SETENABLED
- * ARG0: sysino
- * ARG1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
- * RET0: status
- * ERRORS: EINVAL Invalid sysino or intr_enabled value
- *
- * Set the 'enabled' state of the interrupt sysino.
- */
-#define HV_FAST_INTR_SETENABLED 0xa2
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_intr_setenabled(unsigned long sysino, unsigned long intr_enabled);
-#endif
-
-/* intr_getstate()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_INTR_GETSTATE
- * ARG0: sysino
- * RET0: status
- * RET1: intr_state (HV_INTR_STATE_*)
- * ERRORS: EINVAL Invalid sysino
- *
- * Returns current state of the interrupt defined by the given sysino.
- */
-#define HV_FAST_INTR_GETSTATE 0xa3
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_intr_getstate(unsigned long sysino);
-#endif
-
-/* intr_setstate()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_INTR_SETSTATE
- * ARG0: sysino
- * ARG1: intr_state (HV_INTR_STATE_*)
- * RET0: status
- * ERRORS: EINVAL Invalid sysino or intr_state value
- *
- * Sets the current state of the interrupt described by the given sysino
- * value.
- *
- * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
- * interrupt for sysino.
- */
-#define HV_FAST_INTR_SETSTATE 0xa4
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
-#endif
-
-/* intr_gettarget()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_INTR_GETTARGET
- * ARG0: sysino
- * RET0: status
- * RET1: cpuid
- * ERRORS: EINVAL Invalid sysino
- *
- * Returns CPU that is the current target of the interrupt defined by
- * the given sysino. The CPU value returned is undefined if the target
- * has not been set via intr_settarget().
- */
-#define HV_FAST_INTR_GETTARGET 0xa5
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_intr_gettarget(unsigned long sysino);
-#endif
-
-/* intr_settarget()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_INTR_SETTARGET
- * ARG0: sysino
- * ARG1: cpuid
- * RET0: status
- * ERRORS: EINVAL Invalid sysino
- * ENOCPU Invalid cpuid
- *
- * Set the target CPU for the interrupt defined by the given sysino.
- */
-#define HV_FAST_INTR_SETTARGET 0xa6
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
-#endif
-
-/* vintr_get_cookie()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_VINTR_GET_COOKIE
- * ARG0: device handle
- * ARG1: device ino
- * RET0: status
- * RET1: cookie
- */
-#define HV_FAST_VINTR_GET_COOKIE 0xa7
-
-/* vintr_set_cookie()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_VINTR_SET_COOKIE
- * ARG0: device handle
- * ARG1: device ino
- * ARG2: cookie
- * RET0: status
- */
-#define HV_FAST_VINTR_SET_COOKIE 0xa8
-
-/* vintr_get_valid()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_VINTR_GET_VALID
- * ARG0: device handle
- * ARG1: device ino
- * RET0: status
- * RET1: valid state
- */
-#define HV_FAST_VINTR_GET_VALID 0xa9
-
-/* vintr_set_valid()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_VINTR_SET_VALID
- * ARG0: device handle
- * ARG1: device ino
- * ARG2: valid state
- * RET0: status
- */
-#define HV_FAST_VINTR_SET_VALID 0xaa
-
-/* vintr_get_state()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_VINTR_GET_STATE
- * ARG0: device handle
- * ARG1: device ino
- * RET0: status
- * RET1: state
- */
-#define HV_FAST_VINTR_GET_STATE 0xab
-
-/* vintr_set_state()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_VINTR_SET_STATE
- * ARG0: device handle
- * ARG1: device ino
- * ARG2: state
- * RET0: status
- */
-#define HV_FAST_VINTR_SET_STATE 0xac
-
-/* vintr_get_target()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_VINTR_GET_TARGET
- * ARG0: device handle
- * ARG1: device ino
- * RET0: status
- * RET1: cpuid
- */
-#define HV_FAST_VINTR_GET_TARGET 0xad
-
-/* vintr_set_target()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_VINTR_SET_TARGET
- * ARG0: device handle
- * ARG1: device ino
- * ARG2: cpuid
- * RET0: status
- */
-#define HV_FAST_VINTR_SET_TARGET 0xae
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
- unsigned long dev_ino,
- unsigned long *cookie);
-extern unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle,
- unsigned long dev_ino,
- unsigned long cookie);
-extern unsigned long sun4v_vintr_get_valid(unsigned long dev_handle,
- unsigned long dev_ino,
- unsigned long *valid);
-extern unsigned long sun4v_vintr_set_valid(unsigned long dev_handle,
- unsigned long dev_ino,
- unsigned long valid);
-extern unsigned long sun4v_vintr_get_state(unsigned long dev_handle,
- unsigned long dev_ino,
- unsigned long *state);
-extern unsigned long sun4v_vintr_set_state(unsigned long dev_handle,
- unsigned long dev_ino,
- unsigned long state);
-extern unsigned long sun4v_vintr_get_target(unsigned long dev_handle,
- unsigned long dev_ino,
- unsigned long *cpuid);
-extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
- unsigned long dev_ino,
- unsigned long cpuid);
-#endif
-
-/* PCI IO services.
- *
- * See the terminology descriptions in the device interrupt services
- * section above as those apply here too. Here are terminology
- * definitions specific to these PCI IO services:
- *
- * tsbnum TSB number. Indentifies which io-tsb is used.
- * For this version of the specification, tsbnum
- * must be zero.
- *
- * tsbindex TSB index. Identifies which entry in the TSB
- * is used. The first entry is zero.
- *
- * tsbid A 64-bit aligned data structure which contains
- * a tsbnum and a tsbindex. Bits 63:32 contain the
- * tsbnum and bits 31:00 contain the tsbindex.
- *
- * Use the HV_PCI_TSBID() macro to construct such
- * values.
- *
- * io_attributes IO attributes for IOMMU mappings. One of more
- * of the attritbute bits are stores in a 64-bit
- * value. The values are defined below.
- *
- * r_addr 64-bit real address
- *
- * pci_device PCI device address. A PCI device address identifies
- * a specific device on a specific PCI bus segment.
- * A PCI device address ia a 32-bit unsigned integer
- * with the following format:
- *
- * 00000000.bbbbbbbb.dddddfff.00000000
- *
- * Use the HV_PCI_DEVICE_BUILD() macro to construct
- * such values.
- *
- * pci_config_offset
- * PCI configureation space offset. For conventional
- * PCI a value between 0 and 255. For extended
- * configuration space, a value between 0 and 4095.
- *
- * Note: For PCI configuration space accesses, the offset
- * must be aligned to the access size.
- *
- * error_flag A return value which specifies if the action succeeded
- * or failed. 0 means no error, non-0 means some error
- * occurred while performing the service.
- *
- * io_sync_direction
- * Direction definition for pci_dma_sync(), defined
- * below in HV_PCI_SYNC_*.
- *
- * io_page_list A list of io_page_addresses, an io_page_address is
- * a real address.
- *
- * io_page_list_p A pointer to an io_page_list.
- *
- * "size based byte swap" - Some functions do size based byte swapping
- * which allows sw to access pointers and
- * counters in native form when the processor
- * operates in a different endianness than the
- * IO bus. Size-based byte swapping converts a
- * multi-byte field between big-endian and
- * little-endian format.
- */
-
-#define HV_PCI_MAP_ATTR_READ 0x01
-#define HV_PCI_MAP_ATTR_WRITE 0x02
-
-#define HV_PCI_DEVICE_BUILD(b,d,f) \
- ((((b) & 0xff) << 16) | \
- (((d) & 0x1f) << 11) | \
- (((f) & 0x07) << 8))
-
-#define HV_PCI_TSBID(__tsb_num, __tsb_index) \
- ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index)))
-
-#define HV_PCI_SYNC_FOR_DEVICE 0x01
-#define HV_PCI_SYNC_FOR_CPU 0x02
-
-/* pci_iommu_map()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_IOMMU_MAP
- * ARG0: devhandle
- * ARG1: tsbid
- * ARG2: #ttes
- * ARG3: io_attributes
- * ARG4: io_page_list_p
- * RET0: status
- * RET1: #ttes mapped
- * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex/io_attributes
- * EBADALIGN Improperly aligned real address
- * ENORADDR Invalid real address
- *
- * Create IOMMU mappings in the sun4v device defined by the given
- * devhandle. The mappings are created in the TSB defined by the
- * tsbnum component of the given tsbid. The first mapping is created
- * in the TSB i ndex defined by the tsbindex component of the given tsbid.
- * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
- * the second at tsbnum, tsbindex + 1, etc.
- *
- * All mappings are created with the attributes defined by the io_attributes
- * argument. The page mapping addresses are described in the io_page_list
- * defined by the given io_page_list_p, which is a pointer to the io_page_list.
- * The first entry in the io_page_list is the address for the first iotte, the
- * 2nd for the 2nd iotte, and so on.
- *
- * Each io_page_address in the io_page_list must be appropriately aligned.
- * #ttes must be greater than zero. For this version of the spec, the tsbnum
- * component of the given tsbid must be zero.
- *
- * Returns the actual number of mappings creates, which may be less than
- * or equal to the argument #ttes. If the function returns a value which
- * is less than the #ttes, the caller may continus to call the function with
- * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
- * mapped.
- *
- * Note: This function does not imply an iotte cache flush. The guest must
- * demap an entry before re-mapping it.
- */
-#define HV_FAST_PCI_IOMMU_MAP 0xb0
-
-/* pci_iommu_demap()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_IOMMU_DEMAP
- * ARG0: devhandle
- * ARG1: tsbid
- * ARG2: #ttes
- * RET0: status
- * RET1: #ttes demapped
- * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
- *
- * Demap and flush IOMMU mappings in the device defined by the given
- * devhandle. Demaps up to #ttes entries in the TSB defined by the tsbnum
- * component of the given tsbid, starting at the TSB index defined by the
- * tsbindex component of the given tsbid.
- *
- * For this version of the spec, the tsbnum of the given tsbid must be zero.
- * #ttes must be greater than zero.
- *
- * Returns the actual number of ttes demapped, which may be less than or equal
- * to the argument #ttes. If #ttes demapped is less than #ttes, the caller
- * may continue to call this function with updated tsbid and #ttes arguments
- * until all pages are demapped.
- *
- * Note: Entries do not have to be mapped to be demapped. A demap of an
- * unmapped page will flush the entry from the tte cache.
- */
-#define HV_FAST_PCI_IOMMU_DEMAP 0xb1
-
-/* pci_iommu_getmap()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_IOMMU_GETMAP
- * ARG0: devhandle
- * ARG1: tsbid
- * RET0: status
- * RET1: io_attributes
- * RET2: real address
- * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
- * ENOMAP Mapping is not valid, no translation exists
- *
- * Read and return the mapping in the device described by the given devhandle
- * and tsbid. If successful, the io_attributes shall be returned in RET1
- * and the page address of the mapping shall be returned in RET2.
- *
- * For this version of the spec, the tsbnum component of the given tsbid
- * must be zero.
- */
-#define HV_FAST_PCI_IOMMU_GETMAP 0xb2
-
-/* pci_iommu_getbypass()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_IOMMU_GETBYPASS
- * ARG0: devhandle
- * ARG1: real address
- * ARG2: io_attributes
- * RET0: status
- * RET1: io_addr
- * ERRORS: EINVAL Invalid devhandle/io_attributes
- * ENORADDR Invalid real address
- * ENOTSUPPORTED Function not supported in this implementation.
- *
- * Create a "special" mapping in the device described by the given devhandle,
- * for the given real address and attributes. Return the IO address in RET1
- * if successful.
- */
-#define HV_FAST_PCI_IOMMU_GETBYPASS 0xb3
-
-/* pci_config_get()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_CONFIG_GET
- * ARG0: devhandle
- * ARG1: pci_device
- * ARG2: pci_config_offset
- * ARG3: size
- * RET0: status
- * RET1: error_flag
- * RET2: data
- * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
- * EBADALIGN pci_config_offset not size aligned
- * ENOACCESS Access to this offset is not permitted
- *
- * Read PCI configuration space for the adapter described by the given
- * devhandle. Read size (1, 2, or 4) bytes of data from the given
- * pci_device, at pci_config_offset from the beginning of the device's
- * configuration space. If there was no error, RET1 is set to zero and
- * RET2 is set to the data read. Insignificant bits in RET2 are not
- * guarenteed to have any specific value and therefore must be ignored.
- *
- * The data returned in RET2 is size based byte swapped.
- *
- * If an error occurs during the read, set RET1 to a non-zero value. The
- * given pci_config_offset must be 'size' aligned.
- */
-#define HV_FAST_PCI_CONFIG_GET 0xb4
-
-/* pci_config_put()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_CONFIG_PUT
- * ARG0: devhandle
- * ARG1: pci_device
- * ARG2: pci_config_offset
- * ARG3: size
- * ARG4: data
- * RET0: status
- * RET1: error_flag
- * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
- * EBADALIGN pci_config_offset not size aligned
- * ENOACCESS Access to this offset is not permitted
- *
- * Write PCI configuration space for the adapter described by the given
- * devhandle. Write size (1, 2, or 4) bytes of data in a single operation,
- * at pci_config_offset from the beginning of the device's configuration
- * space. The data argument contains the data to be written to configuration
- * space. Prior to writing, the data is size based byte swapped.
- *
- * If an error occurs during the write access, do not generate an error
- * report, do set RET1 to a non-zero value. Otherwise RET1 is zero.
- * The given pci_config_offset must be 'size' aligned.
- *
- * This function is permitted to read from offset zero in the configuration
- * space described by the given pci_device if necessary to ensure that the
- * write access to config space completes.
- */
-#define HV_FAST_PCI_CONFIG_PUT 0xb5
-
-/* pci_peek()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_PEEK
- * ARG0: devhandle
- * ARG1: real address
- * ARG2: size
- * RET0: status
- * RET1: error_flag
- * RET2: data
- * ERRORS: EINVAL Invalid devhandle or size
- * EBADALIGN Improperly aligned real address
- * ENORADDR Bad real address
- * ENOACCESS Guest access prohibited
- *
- * Attempt to read the IO address given by the given devhandle, real address,
- * and size. Size must be 1, 2, 4, or 8. The read is performed as a single
- * access operation using the given size. If an error occurs when reading
- * from the given location, do not generate an error report, but return a
- * non-zero value in RET1. If the read was successful, return zero in RET1
- * and return the actual data read in RET2. The data returned is size based
- * byte swapped.
- *
- * Non-significant bits in RET2 are not guarenteed to have any specific value
- * and therefore must be ignored. If RET1 is returned as non-zero, the data
- * value is not guarenteed to have any specific value and should be ignored.
- *
- * The caller must have permission to read from the given devhandle, real
- * address, which must be an IO address. The argument real address must be a
- * size aligned address.
- *
- * The hypervisor implementation of this function must block access to any
- * IO address that the guest does not have explicit permission to access.
- */
-#define HV_FAST_PCI_PEEK 0xb6
-
-/* pci_poke()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_POKE
- * ARG0: devhandle
- * ARG1: real address
- * ARG2: size
- * ARG3: data
- * ARG4: pci_device
- * RET0: status
- * RET1: error_flag
- * ERRORS: EINVAL Invalid devhandle, size, or pci_device
- * EBADALIGN Improperly aligned real address
- * ENORADDR Bad real address
- * ENOACCESS Guest access prohibited
- * ENOTSUPPORTED Function is not supported by implementation
- *
- * Attempt to write data to the IO address given by the given devhandle,
- * real address, and size. Size must be 1, 2, 4, or 8. The write is
- * performed as a single access operation using the given size. Prior to
- * writing the data is size based swapped.
- *
- * If an error occurs when writing to the given location, do not generate an
- * error report, but return a non-zero value in RET1. If the write was
- * successful, return zero in RET1.
- *
- * pci_device describes the configuration address of the device being
- * written to. The implementation may safely read from offset 0 with
- * the configuration space of the device described by devhandle and
- * pci_device in order to guarantee that the write portion of the operation
- * completes
- *
- * Any error that occurs due to the read shall be reported using the normal
- * error reporting mechanisms .. the read error is not suppressed.
- *
- * The caller must have permission to write to the given devhandle, real
- * address, which must be an IO address. The argument real address must be a
- * size aligned address. The caller must have permission to read from
- * the given devhandle, pci_device cofiguration space offset 0.
- *
- * The hypervisor implementation of this function must block access to any
- * IO address that the guest does not have explicit permission to access.
- */
-#define HV_FAST_PCI_POKE 0xb7
-
-/* pci_dma_sync()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_DMA_SYNC
- * ARG0: devhandle
- * ARG1: real address
- * ARG2: size
- * ARG3: io_sync_direction
- * RET0: status
- * RET1: #synced
- * ERRORS: EINVAL Invalid devhandle or io_sync_direction
- * ENORADDR Bad real address
- *
- * Synchronize a memory region described by the given real address and size,
- * for the device defined by the given devhandle using the direction(s)
- * defined by the given io_sync_direction. The argument size is the size of
- * the memory region in bytes.
- *
- * Return the actual number of bytes synchronized in the return value #synced,
- * which may be less than or equal to the argument size. If the return
- * value #synced is less than size, the caller must continue to call this
- * function with updated real address and size arguments until the entire
- * memory region is synchronized.
- */
-#define HV_FAST_PCI_DMA_SYNC 0xb8
-
-/* PCI MSI services. */
-
-#define HV_MSITYPE_MSI32 0x00
-#define HV_MSITYPE_MSI64 0x01
-
-#define HV_MSIQSTATE_IDLE 0x00
-#define HV_MSIQSTATE_ERROR 0x01
-
-#define HV_MSIQ_INVALID 0x00
-#define HV_MSIQ_VALID 0x01
-
-#define HV_MSISTATE_IDLE 0x00
-#define HV_MSISTATE_DELIVERED 0x01
-
-#define HV_MSIVALID_INVALID 0x00
-#define HV_MSIVALID_VALID 0x01
-
-#define HV_PCIE_MSGTYPE_PME_MSG 0x18
-#define HV_PCIE_MSGTYPE_PME_ACK_MSG 0x1b
-#define HV_PCIE_MSGTYPE_CORR_MSG 0x30
-#define HV_PCIE_MSGTYPE_NONFATAL_MSG 0x31
-#define HV_PCIE_MSGTYPE_FATAL_MSG 0x33
-
-#define HV_MSG_INVALID 0x00
-#define HV_MSG_VALID 0x01
-
-/* pci_msiq_conf()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSIQ_CONF
- * ARG0: devhandle
- * ARG1: msiqid
- * ARG2: real address
- * ARG3: number of entries
- * RET0: status
- * ERRORS: EINVAL Invalid devhandle, msiqid or nentries
- * EBADALIGN Improperly aligned real address
- * ENORADDR Bad real address
- *
- * Configure the MSI queue given by the devhandle and msiqid arguments,
- * and to be placed at the given real address and be of the given
- * number of entries. The real address must be aligned exactly to match
- * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry
- * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ
- * Head and Tail are initialized so that the MSI-EQ is 'empty'.
- *
- * Implementation Note: Certain implementations have fixed sized queues. In
- * that case, number of entries must contain the correct
- * value.
- */
-#define HV_FAST_PCI_MSIQ_CONF 0xc0
-
-/* pci_msiq_info()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSIQ_INFO
- * ARG0: devhandle
- * ARG1: msiqid
- * RET0: status
- * RET1: real address
- * RET2: number of entries
- * ERRORS: EINVAL Invalid devhandle or msiqid
- *
- * Return the configuration information for the MSI queue described
- * by the given devhandle and msiqid. The base address of the queue
- * is returned in ARG1 and the number of entries is returned in ARG2.
- * If the queue is unconfigured, the real address is undefined and the
- * number of entries will be returned as zero.
- */
-#define HV_FAST_PCI_MSIQ_INFO 0xc1
-
-/* pci_msiq_getvalid()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
- * ARG0: devhandle
- * ARG1: msiqid
- * RET0: status
- * RET1: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
- * ERRORS: EINVAL Invalid devhandle or msiqid
- *
- * Get the valid state of the MSI-EQ described by the given devhandle and
- * msiqid.
- */
-#define HV_FAST_PCI_MSIQ_GETVALID 0xc2
-
-/* pci_msiq_setvalid()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSIQ_SETVALID
- * ARG0: devhandle
- * ARG1: msiqid
- * ARG2: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
- * RET0: status
- * ERRORS: EINVAL Invalid devhandle or msiqid or msiqvalid
- * value or MSI EQ is uninitialized
- *
- * Set the valid state of the MSI-EQ described by the given devhandle and
- * msiqid to the given msiqvalid.
- */
-#define HV_FAST_PCI_MSIQ_SETVALID 0xc3
-
-/* pci_msiq_getstate()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSIQ_GETSTATE
- * ARG0: devhandle
- * ARG1: msiqid
- * RET0: status
- * RET1: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
- * ERRORS: EINVAL Invalid devhandle or msiqid
- *
- * Get the state of the MSI-EQ described by the given devhandle and
- * msiqid.
- */
-#define HV_FAST_PCI_MSIQ_GETSTATE 0xc4
-
-/* pci_msiq_getvalid()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
- * ARG0: devhandle
- * ARG1: msiqid
- * ARG2: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
- * RET0: status
- * ERRORS: EINVAL Invalid devhandle or msiqid or msiqstate
- * value or MSI EQ is uninitialized
- *
- * Set the state of the MSI-EQ described by the given devhandle and
- * msiqid to the given msiqvalid.
- */
-#define HV_FAST_PCI_MSIQ_SETSTATE 0xc5
-
-/* pci_msiq_gethead()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSIQ_GETHEAD
- * ARG0: devhandle
- * ARG1: msiqid
- * RET0: status
- * RET1: msiqhead
- * ERRORS: EINVAL Invalid devhandle or msiqid
- *
- * Get the current MSI EQ queue head for the MSI-EQ described by the
- * given devhandle and msiqid.
- */
-#define HV_FAST_PCI_MSIQ_GETHEAD 0xc6
-
-/* pci_msiq_sethead()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSIQ_SETHEAD
- * ARG0: devhandle
- * ARG1: msiqid
- * ARG2: msiqhead
- * RET0: status
- * ERRORS: EINVAL Invalid devhandle or msiqid or msiqhead,
- * or MSI EQ is uninitialized
- *
- * Set the current MSI EQ queue head for the MSI-EQ described by the
- * given devhandle and msiqid.
- */
-#define HV_FAST_PCI_MSIQ_SETHEAD 0xc7
-
-/* pci_msiq_gettail()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSIQ_GETTAIL
- * ARG0: devhandle
- * ARG1: msiqid
- * RET0: status
- * RET1: msiqtail
- * ERRORS: EINVAL Invalid devhandle or msiqid
- *
- * Get the current MSI EQ queue tail for the MSI-EQ described by the
- * given devhandle and msiqid.
- */
-#define HV_FAST_PCI_MSIQ_GETTAIL 0xc8
-
-/* pci_msi_getvalid()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSI_GETVALID
- * ARG0: devhandle
- * ARG1: msinum
- * RET0: status
- * RET1: msivalidstate
- * ERRORS: EINVAL Invalid devhandle or msinum
- *
- * Get the current valid/enabled state for the MSI defined by the
- * given devhandle and msinum.
- */
-#define HV_FAST_PCI_MSI_GETVALID 0xc9
-
-/* pci_msi_setvalid()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSI_SETVALID
- * ARG0: devhandle
- * ARG1: msinum
- * ARG2: msivalidstate
- * RET0: status
- * ERRORS: EINVAL Invalid devhandle or msinum or msivalidstate
- *
- * Set the current valid/enabled state for the MSI defined by the
- * given devhandle and msinum.
- */
-#define HV_FAST_PCI_MSI_SETVALID 0xca
-
-/* pci_msi_getmsiq()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSI_GETMSIQ
- * ARG0: devhandle
- * ARG1: msinum
- * RET0: status
- * RET1: msiqid
- * ERRORS: EINVAL Invalid devhandle or msinum or MSI is unbound
- *
- * Get the MSI EQ that the MSI defined by the given devhandle and
- * msinum is bound to.
- */
-#define HV_FAST_PCI_MSI_GETMSIQ 0xcb
-
-/* pci_msi_setmsiq()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSI_SETMSIQ
- * ARG0: devhandle
- * ARG1: msinum
- * ARG2: msitype
- * ARG3: msiqid
- * RET0: status
- * ERRORS: EINVAL Invalid devhandle or msinum or msiqid
- *
- * Set the MSI EQ that the MSI defined by the given devhandle and
- * msinum is bound to.
- */
-#define HV_FAST_PCI_MSI_SETMSIQ 0xcc
-
-/* pci_msi_getstate()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSI_GETSTATE
- * ARG0: devhandle
- * ARG1: msinum
- * RET0: status
- * RET1: msistate
- * ERRORS: EINVAL Invalid devhandle or msinum
- *
- * Get the state of the MSI defined by the given devhandle and msinum.
- * If not initialized, return HV_MSISTATE_IDLE.
- */
-#define HV_FAST_PCI_MSI_GETSTATE 0xcd
-
-/* pci_msi_setstate()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSI_SETSTATE
- * ARG0: devhandle
- * ARG1: msinum
- * ARG2: msistate
- * RET0: status
- * ERRORS: EINVAL Invalid devhandle or msinum or msistate
- *
- * Set the state of the MSI defined by the given devhandle and msinum.
- */
-#define HV_FAST_PCI_MSI_SETSTATE 0xce
-
-/* pci_msg_getmsiq()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSG_GETMSIQ
- * ARG0: devhandle
- * ARG1: msgtype
- * RET0: status
- * RET1: msiqid
- * ERRORS: EINVAL Invalid devhandle or msgtype
- *
- * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
- */
-#define HV_FAST_PCI_MSG_GETMSIQ 0xd0
-
-/* pci_msg_setmsiq()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSG_SETMSIQ
- * ARG0: devhandle
- * ARG1: msgtype
- * ARG2: msiqid
- * RET0: status
- * ERRORS: EINVAL Invalid devhandle, msgtype, or msiqid
- *
- * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
- */
-#define HV_FAST_PCI_MSG_SETMSIQ 0xd1
-
-/* pci_msg_getvalid()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSG_GETVALID
- * ARG0: devhandle
- * ARG1: msgtype
- * RET0: status
- * RET1: msgvalidstate
- * ERRORS: EINVAL Invalid devhandle or msgtype
- *
- * Get the valid/enabled state of the MSG defined by the given
- * devhandle and msgtype.
- */
-#define HV_FAST_PCI_MSG_GETVALID 0xd2
-
-/* pci_msg_setvalid()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_PCI_MSG_SETVALID
- * ARG0: devhandle
- * ARG1: msgtype
- * ARG2: msgvalidstate
- * RET0: status
- * ERRORS: EINVAL Invalid devhandle or msgtype or msgvalidstate
- *
- * Set the valid/enabled state of the MSG defined by the given
- * devhandle and msgtype.
- */
-#define HV_FAST_PCI_MSG_SETVALID 0xd3
-
-/* Logical Domain Channel services. */
-
-#define LDC_CHANNEL_DOWN 0
-#define LDC_CHANNEL_UP 1
-#define LDC_CHANNEL_RESETTING 2
-
-/* ldc_tx_qconf()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_TX_QCONF
- * ARG0: channel ID
- * ARG1: real address base of queue
- * ARG2: num entries in queue
- * RET0: status
- *
- * Configure transmit queue for the LDC endpoint specified by the
- * given channel ID, to be placed at the given real address, and
- * be of the given num entries. Num entries must be a power of two.
- * The real address base of the queue must be aligned on the queue
- * size. Each queue entry is 64-bytes, so for example, a 32 entry
- * queue must be aligned on a 2048 byte real address boundary.
- *
- * Upon configuration of a valid transmit queue the head and tail
- * pointers are set to a hypervisor specific identical value indicating
- * that the queue initially is empty.
- *
- * The endpoint's transmit queue is un-configured if num entries is zero.
- *
- * The maximum number of entries for each queue for a specific cpu may be
- * determined from the machine description. A transmit queue may be
- * specified even in the event that the LDC is down (peer endpoint has no
- * receive queue specified). Transmission will begin as soon as the peer
- * endpoint defines a receive queue.
- *
- * It is recommended that a guest wait for a transmit queue to empty prior
- * to reconfiguring it, or un-configuring it. Re or un-configuring of a
- * non-empty transmit queue behaves exactly as defined above, however it
- * is undefined as to how many of the pending entries in the original queue
- * will be delivered prior to the re-configuration taking effect.
- * Furthermore, as the queue configuration causes a reset of the head and
- * tail pointers there is no way for a guest to determine how many entries
- * have been sent after the configuration operation.
- */
-#define HV_FAST_LDC_TX_QCONF 0xe0
-
-/* ldc_tx_qinfo()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_TX_QINFO
- * ARG0: channel ID
- * RET0: status
- * RET1: real address base of queue
- * RET2: num entries in queue
- *
- * Return the configuration info for the transmit queue of LDC endpoint
- * defined by the given channel ID. The real address is the currently
- * defined real address base of the defined queue, and num entries is the
- * size of the queue in terms of number of entries.
- *
- * If the specified channel ID is a valid endpoint number, but no transmit
- * queue has been defined this service will return success, but with num
- * entries set to zero and the real address will have an undefined value.
- */
-#define HV_FAST_LDC_TX_QINFO 0xe1
-
-/* ldc_tx_get_state()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_TX_GET_STATE
- * ARG0: channel ID
- * RET0: status
- * RET1: head offset
- * RET2: tail offset
- * RET3: channel state
- *
- * Return the transmit state, and the head and tail queue pointers, for
- * the transmit queue of the LDC endpoint defined by the given channel ID.
- * The head and tail values are the byte offset of the head and tail
- * positions of the transmit queue for the specified endpoint.
- */
-#define HV_FAST_LDC_TX_GET_STATE 0xe2
-
-/* ldc_tx_set_qtail()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_TX_SET_QTAIL
- * ARG0: channel ID
- * ARG1: tail offset
- * RET0: status
- *
- * Update the tail pointer for the transmit queue associated with the LDC
- * endpoint defined by the given channel ID. The tail offset specified
- * must be aligned on a 64 byte boundary, and calculated so as to increase
- * the number of pending entries on the transmit queue. Any attempt to
- * decrease the number of pending transmit queue entires is considered
- * an invalid tail offset and will result in an EINVAL error.
- *
- * Since the tail of the transmit queue may not be moved backwards, the
- * transmit queue may be flushed by configuring a new transmit queue,
- * whereupon the hypervisor will configure the initial transmit head and
- * tail pointers to be equal.
- */
-#define HV_FAST_LDC_TX_SET_QTAIL 0xe3
-
-/* ldc_rx_qconf()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_RX_QCONF
- * ARG0: channel ID
- * ARG1: real address base of queue
- * ARG2: num entries in queue
- * RET0: status
- *
- * Configure receive queue for the LDC endpoint specified by the
- * given channel ID, to be placed at the given real address, and
- * be of the given num entries. Num entries must be a power of two.
- * The real address base of the queue must be aligned on the queue
- * size. Each queue entry is 64-bytes, so for example, a 32 entry
- * queue must be aligned on a 2048 byte real address boundary.
- *
- * The endpoint's transmit queue is un-configured if num entries is zero.
- *
- * If a valid receive queue is specified for a local endpoint the LDC is
- * in the up state for the purpose of transmission to this endpoint.
- *
- * The maximum number of entries for each queue for a specific cpu may be
- * determined from the machine description.
- *
- * As receive queue configuration causes a reset of the queue's head and
- * tail pointers there is no way for a gues to determine how many entries
- * have been received between a preceeding ldc_get_rx_state() API call
- * and the completion of the configuration operation. It should be noted
- * that datagram delivery is not guarenteed via domain channels anyway,
- * and therefore any higher protocol should be resilient to datagram
- * loss if necessary. However, to overcome this specific race potential
- * it is recommended, for example, that a higher level protocol be employed
- * to ensure either retransmission, or ensure that no datagrams are pending
- * on the peer endpoint's transmit queue prior to the configuration process.
- */
-#define HV_FAST_LDC_RX_QCONF 0xe4
-
-/* ldc_rx_qinfo()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_RX_QINFO
- * ARG0: channel ID
- * RET0: status
- * RET1: real address base of queue
- * RET2: num entries in queue
- *
- * Return the configuration info for the receive queue of LDC endpoint
- * defined by the given channel ID. The real address is the currently
- * defined real address base of the defined queue, and num entries is the
- * size of the queue in terms of number of entries.
- *
- * If the specified channel ID is a valid endpoint number, but no receive
- * queue has been defined this service will return success, but with num
- * entries set to zero and the real address will have an undefined value.
- */
-#define HV_FAST_LDC_RX_QINFO 0xe5
-
-/* ldc_rx_get_state()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_RX_GET_STATE
- * ARG0: channel ID
- * RET0: status
- * RET1: head offset
- * RET2: tail offset
- * RET3: channel state
- *
- * Return the receive state, and the head and tail queue pointers, for
- * the receive queue of the LDC endpoint defined by the given channel ID.
- * The head and tail values are the byte offset of the head and tail
- * positions of the receive queue for the specified endpoint.
- */
-#define HV_FAST_LDC_RX_GET_STATE 0xe6
-
-/* ldc_rx_set_qhead()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_RX_SET_QHEAD
- * ARG0: channel ID
- * ARG1: head offset
- * RET0: status
- *
- * Update the head pointer for the receive queue associated with the LDC
- * endpoint defined by the given channel ID. The head offset specified
- * must be aligned on a 64 byte boundary, and calculated so as to decrease
- * the number of pending entries on the receive queue. Any attempt to
- * increase the number of pending receive queue entires is considered
- * an invalid head offset and will result in an EINVAL error.
- *
- * The receive queue may be flushed by setting the head offset equal
- * to the current tail offset.
- */
-#define HV_FAST_LDC_RX_SET_QHEAD 0xe7
-
-/* LDC Map Table Entry. Each slot is defined by a translation table
- * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
- * hypervisor invalidation cookie.
- */
-#define LDC_MTE_PADDR 0x0fffffffffffe000 /* pa[55:13] */
-#define LDC_MTE_COPY_W 0x0000000000000400 /* copy write access */
-#define LDC_MTE_COPY_R 0x0000000000000200 /* copy read access */
-#define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */
-#define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access */
-#define LDC_MTE_EXEC 0x0000000000000040 /* execute */
-#define LDC_MTE_WRITE 0x0000000000000020 /* read */
-#define LDC_MTE_READ 0x0000000000000010 /* write */
-#define LDC_MTE_SZALL 0x000000000000000f /* page size bits */
-#define LDC_MTE_SZ16GB 0x0000000000000007 /* 16GB page */
-#define LDC_MTE_SZ2GB 0x0000000000000006 /* 2GB page */
-#define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page */
-#define LDC_MTE_SZ32MB 0x0000000000000004 /* 32MB page */
-#define LDC_MTE_SZ4MB 0x0000000000000003 /* 4MB page */
-#define LDC_MTE_SZ512K 0x0000000000000002 /* 512K page */
-#define LDC_MTE_SZ64K 0x0000000000000001 /* 64K page */
-#define LDC_MTE_SZ8K 0x0000000000000000 /* 8K page */
-
-#ifndef __ASSEMBLY__
-struct ldc_mtable_entry {
- unsigned long mte;
- unsigned long cookie;
-};
-#endif
-
-/* ldc_set_map_table()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_SET_MAP_TABLE
- * ARG0: channel ID
- * ARG1: table real address
- * ARG2: num entries
- * RET0: status
- *
- * Register the MTE table at the given table real address, with the
- * specified num entries, for the LDC indicated by the given channel
- * ID.
- */
-#define HV_FAST_LDC_SET_MAP_TABLE 0xea
-
-/* ldc_get_map_table()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_GET_MAP_TABLE
- * ARG0: channel ID
- * RET0: status
- * RET1: table real address
- * RET2: num entries
- *
- * Return the configuration of the current mapping table registered
- * for the given channel ID.
- */
-#define HV_FAST_LDC_GET_MAP_TABLE 0xeb
-
-#define LDC_COPY_IN 0
-#define LDC_COPY_OUT 1
-
-/* ldc_copy()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_COPY
- * ARG0: channel ID
- * ARG1: LDC_COPY_* direction code
- * ARG2: target real address
- * ARG3: local real address
- * ARG4: length in bytes
- * RET0: status
- * RET1: actual length in bytes
- */
-#define HV_FAST_LDC_COPY 0xec
-
-#define LDC_MEM_READ 1
-#define LDC_MEM_WRITE 2
-#define LDC_MEM_EXEC 4
-
-/* ldc_mapin()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_MAPIN
- * ARG0: channel ID
- * ARG1: cookie
- * RET0: status
- * RET1: real address
- * RET2: LDC_MEM_* permissions
- */
-#define HV_FAST_LDC_MAPIN 0xed
-
-/* ldc_unmap()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_UNMAP
- * ARG0: real address
- * RET0: status
- */
-#define HV_FAST_LDC_UNMAP 0xee
-
-/* ldc_revoke()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_LDC_REVOKE
- * ARG0: channel ID
- * ARG1: cookie
- * ARG2: ldc_mtable_entry cookie
- * RET0: status
- */
-#define HV_FAST_LDC_REVOKE 0xef
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
- unsigned long ra,
- unsigned long num_entries);
-extern unsigned long sun4v_ldc_tx_qinfo(unsigned long channel,
- unsigned long *ra,
- unsigned long *num_entries);
-extern unsigned long sun4v_ldc_tx_get_state(unsigned long channel,
- unsigned long *head_off,
- unsigned long *tail_off,
- unsigned long *chan_state);
-extern unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel,
- unsigned long tail_off);
-extern unsigned long sun4v_ldc_rx_qconf(unsigned long channel,
- unsigned long ra,
- unsigned long num_entries);
-extern unsigned long sun4v_ldc_rx_qinfo(unsigned long channel,
- unsigned long *ra,
- unsigned long *num_entries);
-extern unsigned long sun4v_ldc_rx_get_state(unsigned long channel,
- unsigned long *head_off,
- unsigned long *tail_off,
- unsigned long *chan_state);
-extern unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel,
- unsigned long head_off);
-extern unsigned long sun4v_ldc_set_map_table(unsigned long channel,
- unsigned long ra,
- unsigned long num_entries);
-extern unsigned long sun4v_ldc_get_map_table(unsigned long channel,
- unsigned long *ra,
- unsigned long *num_entries);
-extern unsigned long sun4v_ldc_copy(unsigned long channel,
- unsigned long dir_code,
- unsigned long tgt_raddr,
- unsigned long lcl_raddr,
- unsigned long len,
- unsigned long *actual_len);
-extern unsigned long sun4v_ldc_mapin(unsigned long channel,
- unsigned long cookie,
- unsigned long *ra,
- unsigned long *perm);
-extern unsigned long sun4v_ldc_unmap(unsigned long ra);
-extern unsigned long sun4v_ldc_revoke(unsigned long channel,
- unsigned long cookie,
- unsigned long mte_cookie);
-#endif
-
-/* Performance counter services. */
-
-#define HV_PERF_JBUS_PERF_CTRL_REG 0x00
-#define HV_PERF_JBUS_PERF_CNT_REG 0x01
-#define HV_PERF_DRAM_PERF_CTRL_REG_0 0x02
-#define HV_PERF_DRAM_PERF_CNT_REG_0 0x03
-#define HV_PERF_DRAM_PERF_CTRL_REG_1 0x04
-#define HV_PERF_DRAM_PERF_CNT_REG_1 0x05
-#define HV_PERF_DRAM_PERF_CTRL_REG_2 0x06
-#define HV_PERF_DRAM_PERF_CNT_REG_2 0x07
-#define HV_PERF_DRAM_PERF_CTRL_REG_3 0x08
-#define HV_PERF_DRAM_PERF_CNT_REG_3 0x09
-
-/* get_perfreg()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_GET_PERFREG
- * ARG0: performance reg number
- * RET0: status
- * RET1: performance reg value
- * ERRORS: EINVAL Invalid performance register number
- * ENOACCESS No access allowed to performance counters
- *
- * Read the value of the given DRAM/JBUS performance counter/control register.
- */
-#define HV_FAST_GET_PERFREG 0x100
-
-/* set_perfreg()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_SET_PERFREG
- * ARG0: performance reg number
- * ARG1: performance reg value
- * RET0: status
- * ERRORS: EINVAL Invalid performance register number
- * ENOACCESS No access allowed to performance counters
- *
- * Write the given performance reg value to the given DRAM/JBUS
- * performance counter/control register.
- */
-#define HV_FAST_SET_PERFREG 0x101
-
-/* MMU statistics services.
- *
- * The hypervisor maintains MMU statistics and privileged code provides
- * a buffer where these statistics can be collected. It is continually
- * updated once configured. The layout is as follows:
- */
-#ifndef __ASSEMBLY__
-struct hv_mmu_statistics {
- unsigned long immu_tsb_hits_ctx0_8k_tte;
- unsigned long immu_tsb_ticks_ctx0_8k_tte;
- unsigned long immu_tsb_hits_ctx0_64k_tte;
- unsigned long immu_tsb_ticks_ctx0_64k_tte;
- unsigned long __reserved1[2];
- unsigned long immu_tsb_hits_ctx0_4mb_tte;
- unsigned long immu_tsb_ticks_ctx0_4mb_tte;
- unsigned long __reserved2[2];
- unsigned long immu_tsb_hits_ctx0_256mb_tte;
- unsigned long immu_tsb_ticks_ctx0_256mb_tte;
- unsigned long __reserved3[4];
- unsigned long immu_tsb_hits_ctxnon0_8k_tte;
- unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
- unsigned long immu_tsb_hits_ctxnon0_64k_tte;
- unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
- unsigned long __reserved4[2];
- unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
- unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
- unsigned long __reserved5[2];
- unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
- unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
- unsigned long __reserved6[4];
- unsigned long dmmu_tsb_hits_ctx0_8k_tte;
- unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
- unsigned long dmmu_tsb_hits_ctx0_64k_tte;
- unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
- unsigned long __reserved7[2];
- unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
- unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
- unsigned long __reserved8[2];
- unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
- unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
- unsigned long __reserved9[4];
- unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
- unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
- unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
- unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
- unsigned long __reserved10[2];
- unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
- unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
- unsigned long __reserved11[2];
- unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
- unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
- unsigned long __reserved12[4];
-};
-#endif
-
-/* mmustat_conf()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMUSTAT_CONF
- * ARG0: real address
- * RET0: status
- * RET1: real address
- * ERRORS: ENORADDR Invalid real address
- * EBADALIGN Real address not aligned on 64-byte boundary
- * EBADTRAP API not supported on this processor
- *
- * Enable MMU statistic gathering using the buffer at the given real
- * address on the current virtual CPU. The new buffer real address
- * is given in ARG1, and the previously specified buffer real address
- * is returned in RET1, or is returned as zero for the first invocation.
- *
- * If the passed in real address argument is zero, this will disable
- * MMU statistic collection on the current virtual CPU. If an error is
- * returned then no statistics are collected.
- *
- * The buffer contents should be initialized to all zeros before being
- * given to the hypervisor or else the statistics will be meaningless.
- */
-#define HV_FAST_MMUSTAT_CONF 0x102
-
-/* mmustat_info()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_MMUSTAT_INFO
- * RET0: status
- * RET1: real address
- * ERRORS: EBADTRAP API not supported on this processor
- *
- * Return the current state and real address of the currently configured
- * MMU statistics buffer on the current virtual CPU.
- */
-#define HV_FAST_MMUSTAT_INFO 0x103
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_mmustat_conf(unsigned long ra, unsigned long *orig_ra);
-extern unsigned long sun4v_mmustat_info(unsigned long *ra);
-#endif
-
-/* NCS crypto services */
-
-/* ncs_request() sub-function numbers */
-#define HV_NCS_QCONF 0x01
-#define HV_NCS_QTAIL_UPDATE 0x02
-
-#ifndef __ASSEMBLY__
-struct hv_ncs_queue_entry {
- /* MAU Control Register */
- unsigned long mau_control;
-#define MAU_CONTROL_INV_PARITY 0x0000000000002000
-#define MAU_CONTROL_STRAND 0x0000000000001800
-#define MAU_CONTROL_BUSY 0x0000000000000400
-#define MAU_CONTROL_INT 0x0000000000000200
-#define MAU_CONTROL_OP 0x00000000000001c0
-#define MAU_CONTROL_OP_SHIFT 6
-#define MAU_OP_LOAD_MA_MEMORY 0x0
-#define MAU_OP_STORE_MA_MEMORY 0x1
-#define MAU_OP_MODULAR_MULT 0x2
-#define MAU_OP_MODULAR_REDUCE 0x3
-#define MAU_OP_MODULAR_EXP_LOOP 0x4
-#define MAU_CONTROL_LEN 0x000000000000003f
-#define MAU_CONTROL_LEN_SHIFT 0
-
- /* Real address of bytes to load or store bytes
- * into/out-of the MAU.
- */
- unsigned long mau_mpa;
-
- /* Modular Arithmetic MA Offset Register. */
- unsigned long mau_ma;
-
- /* Modular Arithmetic N Prime Register. */
- unsigned long mau_np;
-};
-
-struct hv_ncs_qconf_arg {
- unsigned long mid; /* MAU ID, 1 per core on Niagara */
- unsigned long base; /* Real address base of queue */
- unsigned long end; /* Real address end of queue */
- unsigned long num_ents; /* Number of entries in queue */
-};
-
-struct hv_ncs_qtail_update_arg {
- unsigned long mid; /* MAU ID, 1 per core on Niagara */
- unsigned long tail; /* New tail index to use */
- unsigned long syncflag; /* only SYNCFLAG_SYNC is implemented */
-#define HV_NCS_SYNCFLAG_SYNC 0x00
-#define HV_NCS_SYNCFLAG_ASYNC 0x01
-};
-#endif
-
-/* ncs_request()
- * TRAP: HV_FAST_TRAP
- * FUNCTION: HV_FAST_NCS_REQUEST
- * ARG0: NCS sub-function
- * ARG1: sub-function argument real address
- * ARG2: size in bytes of sub-function argument
- * RET0: status
- *
- * The MAU chip of the Niagara processor is not directly accessible
- * to privileged code, instead it is programmed indirectly via this
- * hypervisor API.
- *
- * The interfaces defines a queue of MAU operations to perform.
- * Privileged code registers a queue with the hypervisor by invoking
- * this HVAPI with the HV_NCS_QCONF sub-function, which defines the
- * base, end, and number of entries of the queue. Each queue entry
- * contains a MAU register struct block.
- *
- * The privileged code then proceeds to add entries to the queue and
- * then invoke the HV_NCS_QTAIL_UPDATE sub-function. Since only
- * synchronous operations are supported by the current hypervisor,
- * HV_NCS_QTAIL_UPDATE will run all the pending queue entries to
- * completion and return HV_EOK, or return an error code.
- *
- * The real address of the sub-function argument must be aligned on at
- * least an 8-byte boundary.
- *
- * The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte
- * offset, into the queue and must be less than or equal the 'num_ents'
- * argument given in the HV_NCS_QCONF call.
- */
-#define HV_FAST_NCS_REQUEST 0x110
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_ncs_request(unsigned long request,
- unsigned long arg_ra,
- unsigned long arg_size);
-#endif
-
-#define HV_FAST_FIRE_GET_PERFREG 0x120
-#define HV_FAST_FIRE_SET_PERFREG 0x121
-
-/* Function numbers for HV_CORE_TRAP. */
-#define HV_CORE_SET_VER 0x00
-#define HV_CORE_PUTCHAR 0x01
-#define HV_CORE_EXIT 0x02
-#define HV_CORE_GET_VER 0x03
-
-/* Hypervisor API groups for use with HV_CORE_SET_VER and
- * HV_CORE_GET_VER.
- */
-#define HV_GRP_SUN4V 0x0000
-#define HV_GRP_CORE 0x0001
-#define HV_GRP_INTR 0x0002
-#define HV_GRP_SOFT_STATE 0x0003
-#define HV_GRP_PCI 0x0100
-#define HV_GRP_LDOM 0x0101
-#define HV_GRP_SVC_CHAN 0x0102
-#define HV_GRP_NCS 0x0103
-#define HV_GRP_RNG 0x0104
-#define HV_GRP_NIAG_PERF 0x0200
-#define HV_GRP_FIRE_PERF 0x0201
-#define HV_GRP_N2_CPU 0x0202
-#define HV_GRP_NIU 0x0204
-#define HV_GRP_VF_CPU 0x0205
-#define HV_GRP_DIAG 0x0300
-
-#ifndef __ASSEMBLY__
-extern unsigned long sun4v_get_version(unsigned long group,
- unsigned long *major,
- unsigned long *minor);
-extern unsigned long sun4v_set_version(unsigned long group,
- unsigned long major,
- unsigned long minor,
- unsigned long *actual_minor);
-
-extern int sun4v_hvapi_register(unsigned long group, unsigned long major,
- unsigned long *minor);
-extern void sun4v_hvapi_unregister(unsigned long group);
-extern int sun4v_hvapi_get(unsigned long group,
- unsigned long *major,
- unsigned long *minor);
-extern void sun4v_hvapi_init(void);
-#endif
-
-#endif /* !(_SPARC64_HYPERVISOR_H) */
+++ /dev/null
-/* ide.h: SPARC PCI specific IDE glue.
- *
- * Copyright (C) 1997 David S. Miller (davem@davemloft.net)
- * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
- * Adaptation from sparc64 version to sparc by Pete Zaitcev.
- */
-
-#ifndef _SPARC_IDE_H
-#define _SPARC_IDE_H
-
-#ifdef __KERNEL__
-
-#include <asm/io.h>
-#ifdef CONFIG_SPARC64
-#include <asm/pgalloc.h>
-#include <asm/spitfire.h>
-#include <asm/cacheflush.h>
-#include <asm/page.h>
-#else
-#include <asm/pgtable.h>
-#include <asm/psr.h>
-#endif
-
-#define __ide_insl(data_reg, buffer, wcount) \
- __ide_insw(data_reg, buffer, (wcount)<<1)
-#define __ide_outsl(data_reg, buffer, wcount) \
- __ide_outsw(data_reg, buffer, (wcount)<<1)
-
-/* On sparc, I/O ports and MMIO registers are accessed identically. */
-#define __ide_mm_insw __ide_insw
-#define __ide_mm_insl __ide_insl
-#define __ide_mm_outsw __ide_outsw
-#define __ide_mm_outsl __ide_outsl
-
-static inline void __ide_insw(void __iomem *port, void *dst, u32 count)
-{
-#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
- unsigned long end = (unsigned long)dst + (count << 1);
-#endif
- u16 *ps = dst;
- u32 *pi;
-
- if(((unsigned long)ps) & 0x2) {
- *ps++ = __raw_readw(port);
- count--;
- }
- pi = (u32 *)ps;
- while(count >= 2) {
- u32 w;
-
- w = __raw_readw(port) << 16;
- w |= __raw_readw(port);
- *pi++ = w;
- count -= 2;
- }
- ps = (u16 *)pi;
- if(count)
- *ps++ = __raw_readw(port);
-
-#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
- __flush_dcache_range((unsigned long)dst, end);
-#endif
-}
-
-static inline void __ide_outsw(void __iomem *port, const void *src, u32 count)
-{
-#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
- unsigned long end = (unsigned long)src + (count << 1);
-#endif
- const u16 *ps = src;
- const u32 *pi;
-
- if(((unsigned long)src) & 0x2) {
- __raw_writew(*ps++, port);
- count--;
- }
- pi = (const u32 *)ps;
- while(count >= 2) {
- u32 w;
-
- w = *pi++;
- __raw_writew((w >> 16), port);
- __raw_writew(w, port);
- count -= 2;
- }
- ps = (const u16 *)pi;
- if(count)
- __raw_writew(*ps, port);
-
-#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
- __flush_dcache_range((unsigned long)src, end);
-#endif
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* _SPARC_IDE_H */
+++ /dev/null
-/*
- * idprom.h: Macros and defines for idprom routines
- *
- * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_IDPROM_H
-#define _SPARC_IDPROM_H
-
-#include <linux/types.h>
-
-struct idprom {
- u8 id_format; /* Format identifier (always 0x01) */
- u8 id_machtype; /* Machine type */
- u8 id_ethaddr[6]; /* Hardware ethernet address */
- s32 id_date; /* Date of manufacture */
- u32 id_sernum:24; /* Unique serial number */
- u8 id_cksum; /* Checksum - xor of the data bytes */
- u8 reserved[16];
-};
-
-extern struct idprom *idprom;
-extern void idprom_init(void);
-
-#endif /* !(_SPARC_IDPROM_H) */
+++ /dev/null
-#ifndef _SPARC64_INTR_QUEUE_H
-#define _SPARC64_INTR_QUEUE_H
-
-/* Sun4v interrupt queue registers, accessed via ASI_QUEUE. */
-
-#define INTRQ_CPU_MONDO_HEAD 0x3c0 /* CPU mondo head */
-#define INTRQ_CPU_MONDO_TAIL 0x3c8 /* CPU mondo tail */
-#define INTRQ_DEVICE_MONDO_HEAD 0x3d0 /* Device mondo head */
-#define INTRQ_DEVICE_MONDO_TAIL 0x3d8 /* Device mondo tail */
-#define INTRQ_RESUM_MONDO_HEAD 0x3e0 /* Resumable error mondo head */
-#define INTRQ_RESUM_MONDO_TAIL 0x3e8 /* Resumable error mondo tail */
-#define INTRQ_NONRESUM_MONDO_HEAD 0x3f0 /* Non-resumable error mondo head */
-#define INTRQ_NONRESUM_MONDO_TAIL 0x3f8 /* Non-resumable error mondo head */
-
-#endif /* !(_SPARC64_INTR_QUEUE_H) */
+++ /dev/null
-/* io-unit.h: Definitions for the sun4d IO-UNIT.
- *
- * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-#ifndef _SPARC_IO_UNIT_H
-#define _SPARC_IO_UNIT_H
-
-#include <linux/spinlock.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-
-/* The io-unit handles all virtual to physical address translations
- * that occur between the SBUS and physical memory. Access by
- * the cpu to IO registers and similar go over the xdbus so are
- * translated by the on chip SRMMU. The io-unit and the srmmu do
- * not need to have the same translations at all, in fact most
- * of the time the translations they handle are a disjunct set.
- * Basically the io-unit handles all dvma sbus activity.
- */
-
-/* AIEEE, unlike the nice sun4m, these monsters have
- fixed DMA range 64M */
-
-#define IOUNIT_DMA_BASE 0xfc000000 /* TOP - 64M */
-#define IOUNIT_DMA_SIZE 0x04000000 /* 64M */
-/* We use last 1M for sparc_dvma_malloc */
-#define IOUNIT_DVMA_SIZE 0x00100000 /* 1M */
-
-/* The format of an iopte in the external page tables */
-#define IOUPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
-#define IOUPTE_CACHE 0x00000080 /* Cached (in Viking/MXCC) */
-/* XXX Jakub, find out how to program SBUS streaming cache on XDBUS/sun4d.
- * XXX Actually, all you should need to do is find out where the registers
- * XXX are and copy over the sparc64 implementation I wrote. There may be
- * XXX some horrible hwbugs though, so be careful. -DaveM
- */
-#define IOUPTE_STREAM 0x00000040 /* Translation can use streaming cache */
-#define IOUPTE_INTRA 0x00000008 /* SBUS direct slot->slot transfer */
-#define IOUPTE_WRITE 0x00000004 /* Writeable */
-#define IOUPTE_VALID 0x00000002 /* IOPTE is valid */
-#define IOUPTE_PARITY 0x00000001 /* Parity is checked during DVMA */
-
-struct iounit_struct {
- unsigned long bmap[(IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 3)) / sizeof(unsigned long)];
- spinlock_t lock;
- iopte_t *page_table;
- unsigned long rotor[3];
- unsigned long limit[4];
-};
-
-#define IOUNIT_BMAP1_START 0x00000000
-#define IOUNIT_BMAP1_END (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 1))
-#define IOUNIT_BMAP2_START IOUNIT_BMAP1_END
-#define IOUNIT_BMAP2_END IOUNIT_BMAP2_START + (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 2))
-#define IOUNIT_BMAPM_START IOUNIT_BMAP2_END
-#define IOUNIT_BMAPM_END ((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT)
-
-extern __u32 iounit_map_dma_init(struct sbus_bus *, int);
-#define iounit_map_dma_finish(sbus, addr, len) mmu_release_scsi_one(addr, len, sbus)
-extern __u32 iounit_map_dma_page(__u32, void *, struct sbus_bus *);
-
-#endif /* !(_SPARC_IO_UNIT_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_IO_H
-#define ___ASM_SPARC_IO_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/io_64.h>
-#else
-#include <asm-sparc/io_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef __SPARC_IO_H
-#define __SPARC_IO_H
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/ioport.h> /* struct resource */
-
-#include <asm/page.h> /* IO address mapping routines need this */
-#include <asm/system.h>
-
-#define page_to_phys(page) (((page) - mem_map) << PAGE_SHIFT)
-
-static inline u32 flip_dword (u32 l)
-{
- return ((l&0xff)<<24) | (((l>>8)&0xff)<<16) | (((l>>16)&0xff)<<8)| ((l>>24)&0xff);
-}
-
-static inline u16 flip_word (u16 w)
-{
- return ((w&0xff) << 8) | ((w>>8)&0xff);
-}
-
-#define mmiowb()
-
-/*
- * Memory mapped I/O to PCI
- */
-
-static inline u8 __raw_readb(const volatile void __iomem *addr)
-{
- return *(__force volatile u8 *)addr;
-}
-
-static inline u16 __raw_readw(const volatile void __iomem *addr)
-{
- return *(__force volatile u16 *)addr;
-}
-
-static inline u32 __raw_readl(const volatile void __iomem *addr)
-{
- return *(__force volatile u32 *)addr;
-}
-
-static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
-{
- *(__force volatile u8 *)addr = b;
-}
-
-static inline void __raw_writew(u16 w, volatile void __iomem *addr)
-{
- *(__force volatile u16 *)addr = w;
-}
-
-static inline void __raw_writel(u32 l, volatile void __iomem *addr)
-{
- *(__force volatile u32 *)addr = l;
-}
-
-static inline u8 __readb(const volatile void __iomem *addr)
-{
- return *(__force volatile u8 *)addr;
-}
-
-static inline u16 __readw(const volatile void __iomem *addr)
-{
- return flip_word(*(__force volatile u16 *)addr);
-}
-
-static inline u32 __readl(const volatile void __iomem *addr)
-{
- return flip_dword(*(__force volatile u32 *)addr);
-}
-
-static inline void __writeb(u8 b, volatile void __iomem *addr)
-{
- *(__force volatile u8 *)addr = b;
-}
-
-static inline void __writew(u16 w, volatile void __iomem *addr)
-{
- *(__force volatile u16 *)addr = flip_word(w);
-}
-
-static inline void __writel(u32 l, volatile void __iomem *addr)
-{
- *(__force volatile u32 *)addr = flip_dword(l);
-}
-
-#define readb(__addr) __readb(__addr)
-#define readw(__addr) __readw(__addr)
-#define readl(__addr) __readl(__addr)
-#define readb_relaxed(__addr) readb(__addr)
-#define readw_relaxed(__addr) readw(__addr)
-#define readl_relaxed(__addr) readl(__addr)
-
-#define writeb(__b, __addr) __writeb((__b),(__addr))
-#define writew(__w, __addr) __writew((__w),(__addr))
-#define writel(__l, __addr) __writel((__l),(__addr))
-
-/*
- * I/O space operations
- *
- * Arrangement on a Sun is somewhat complicated.
- *
- * First of all, we want to use standard Linux drivers
- * for keyboard, PC serial, etc. These drivers think
- * they access I/O space and use inb/outb.
- * On the other hand, EBus bridge accepts PCI *memory*
- * cycles and converts them into ISA *I/O* cycles.
- * Ergo, we want inb & outb to generate PCI memory cycles.
- *
- * If we want to issue PCI *I/O* cycles, we do this
- * with a low 64K fixed window in PCIC. This window gets
- * mapped somewhere into virtual kernel space and we
- * can use inb/outb again.
- */
-#define inb_local(__addr) __readb((void __iomem *)(unsigned long)(__addr))
-#define inb(__addr) __readb((void __iomem *)(unsigned long)(__addr))
-#define inw(__addr) __readw((void __iomem *)(unsigned long)(__addr))
-#define inl(__addr) __readl((void __iomem *)(unsigned long)(__addr))
-
-#define outb_local(__b, __addr) __writeb(__b, (void __iomem *)(unsigned long)(__addr))
-#define outb(__b, __addr) __writeb(__b, (void __iomem *)(unsigned long)(__addr))
-#define outw(__w, __addr) __writew(__w, (void __iomem *)(unsigned long)(__addr))
-#define outl(__l, __addr) __writel(__l, (void __iomem *)(unsigned long)(__addr))
-
-#define inb_p(__addr) inb(__addr)
-#define outb_p(__b, __addr) outb(__b, __addr)
-#define inw_p(__addr) inw(__addr)
-#define outw_p(__w, __addr) outw(__w, __addr)
-#define inl_p(__addr) inl(__addr)
-#define outl_p(__l, __addr) outl(__l, __addr)
-
-void outsb(unsigned long addr, const void *src, unsigned long cnt);
-void outsw(unsigned long addr, const void *src, unsigned long cnt);
-void outsl(unsigned long addr, const void *src, unsigned long cnt);
-void insb(unsigned long addr, void *dst, unsigned long count);
-void insw(unsigned long addr, void *dst, unsigned long count);
-void insl(unsigned long addr, void *dst, unsigned long count);
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * SBus accessors.
- *
- * SBus has only one, memory mapped, I/O space.
- * We do not need to flip bytes for SBus of course.
- */
-static inline u8 _sbus_readb(const volatile void __iomem *addr)
-{
- return *(__force volatile u8 *)addr;
-}
-
-static inline u16 _sbus_readw(const volatile void __iomem *addr)
-{
- return *(__force volatile u16 *)addr;
-}
-
-static inline u32 _sbus_readl(const volatile void __iomem *addr)
-{
- return *(__force volatile u32 *)addr;
-}
-
-static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
-{
- *(__force volatile u8 *)addr = b;
-}
-
-static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
-{
- *(__force volatile u16 *)addr = w;
-}
-
-static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
-{
- *(__force volatile u32 *)addr = l;
-}
-
-/*
- * The only reason for #define's is to hide casts to unsigned long.
- */
-#define sbus_readb(__addr) _sbus_readb(__addr)
-#define sbus_readw(__addr) _sbus_readw(__addr)
-#define sbus_readl(__addr) _sbus_readl(__addr)
-#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr)
-#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr)
-#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
-
-static inline void sbus_memset_io(volatile void __iomem *__dst, int c, __kernel_size_t n)
-{
- while(n--) {
- sbus_writeb(c, __dst);
- __dst++;
- }
-}
-
-static inline void
-_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
-{
- volatile void __iomem *d = dst;
-
- while (n--) {
- writeb(c, d);
- d++;
- }
-}
-
-#define memset_io(d,c,sz) _memset_io(d,c,sz)
-
-static inline void
-_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
-{
- char *d = dst;
-
- while (n--) {
- char tmp = readb(src);
- *d++ = tmp;
- src++;
- }
-}
-
-#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
-
-static inline void
-_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
-{
- const char *s = src;
- volatile void __iomem *d = dst;
-
- while (n--) {
- char tmp = *s++;
- writeb(tmp, d);
- d++;
- }
-}
-
-#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
-
-#ifdef __KERNEL__
-
-/*
- * Bus number may be embedded in the higher bits of the physical address.
- * This is why we have no bus number argument to ioremap().
- */
-extern void __iomem *ioremap(unsigned long offset, unsigned long size);
-#define ioremap_nocache(X,Y) ioremap((X),(Y))
-#define ioremap_wc(X,Y) ioremap((X),(Y))
-extern void iounmap(volatile void __iomem *addr);
-
-#define ioread8(X) readb(X)
-#define ioread16(X) readw(X)
-#define ioread32(X) readl(X)
-#define iowrite8(val,X) writeb(val,X)
-#define iowrite16(val,X) writew(val,X)
-#define iowrite32(val,X) writel(val,X)
-
-static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
-{
- insb((unsigned long __force)port, buf, count);
-}
-static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
-{
- insw((unsigned long __force)port, buf, count);
-}
-
-static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
-{
- insl((unsigned long __force)port, buf, count);
-}
-
-static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
-{
- outsb((unsigned long __force)port, buf, count);
-}
-
-static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
-{
- outsw((unsigned long __force)port, buf, count);
-}
-
-static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
-{
- outsl((unsigned long __force)port, buf, count);
-}
-
-/* Create a virtual mapping cookie for an IO port range */
-extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
-extern void ioport_unmap(void __iomem *);
-
-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
-struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
-extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
-
-/*
- * Bus number may be in res->flags... somewhere.
- */
-extern void __iomem *sbus_ioremap(struct resource *res, unsigned long offset,
- unsigned long size, char *name);
-extern void sbus_iounmap(volatile void __iomem *vaddr, unsigned long size);
-
-
-/*
- * At the moment, we do not use CMOS_READ anywhere outside of rtc.c,
- * so rtc_port is static in it. This should not change unless a new
- * hardware pops up.
- */
-#define RTC_PORT(x) (rtc_port + (x))
-#define RTC_ALWAYS_BCD 0
-
-#endif
-
-#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p) __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p) p
-
-#endif /* !(__SPARC_IO_H) */
+++ /dev/null
-#ifndef __SPARC64_IO_H
-#define __SPARC64_IO_H
-
-#include <linux/kernel.h>
-#include <linux/compiler.h>
-#include <linux/types.h>
-
-#include <asm/page.h> /* IO address mapping routines need this */
-#include <asm/system.h>
-#include <asm/asi.h>
-
-/* PC crapola... */
-#define __SLOW_DOWN_IO do { } while (0)
-#define SLOW_DOWN_IO do { } while (0)
-
-/* BIO layer definitions. */
-extern unsigned long kern_base, kern_size;
-#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
-
-static inline u8 _inb(unsigned long addr)
-{
- u8 ret;
-
- __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
-
- return ret;
-}
-
-static inline u16 _inw(unsigned long addr)
-{
- u16 ret;
-
- __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
-
- return ret;
-}
-
-static inline u32 _inl(unsigned long addr)
-{
- u32 ret;
-
- __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
-
- return ret;
-}
-
-static inline void _outb(u8 b, unsigned long addr)
-{
- __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
- : /* no outputs */
- : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
-}
-
-static inline void _outw(u16 w, unsigned long addr)
-{
- __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
- : /* no outputs */
- : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
-}
-
-static inline void _outl(u32 l, unsigned long addr)
-{
- __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
- : /* no outputs */
- : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
-}
-
-#define inb(__addr) (_inb((unsigned long)(__addr)))
-#define inw(__addr) (_inw((unsigned long)(__addr)))
-#define inl(__addr) (_inl((unsigned long)(__addr)))
-#define outb(__b, __addr) (_outb((u8)(__b), (unsigned long)(__addr)))
-#define outw(__w, __addr) (_outw((u16)(__w), (unsigned long)(__addr)))
-#define outl(__l, __addr) (_outl((u32)(__l), (unsigned long)(__addr)))
-
-#define inb_p(__addr) inb(__addr)
-#define outb_p(__b, __addr) outb(__b, __addr)
-#define inw_p(__addr) inw(__addr)
-#define outw_p(__w, __addr) outw(__w, __addr)
-#define inl_p(__addr) inl(__addr)
-#define outl_p(__l, __addr) outl(__l, __addr)
-
-extern void outsb(unsigned long, const void *, unsigned long);
-extern void outsw(unsigned long, const void *, unsigned long);
-extern void outsl(unsigned long, const void *, unsigned long);
-extern void insb(unsigned long, void *, unsigned long);
-extern void insw(unsigned long, void *, unsigned long);
-extern void insl(unsigned long, void *, unsigned long);
-
-static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
-{
- insb((unsigned long __force)port, buf, count);
-}
-static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
-{
- insw((unsigned long __force)port, buf, count);
-}
-
-static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
-{
- insl((unsigned long __force)port, buf, count);
-}
-
-static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
-{
- outsb((unsigned long __force)port, buf, count);
-}
-
-static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
-{
- outsw((unsigned long __force)port, buf, count);
-}
-
-static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
-{
- outsl((unsigned long __force)port, buf, count);
-}
-
-/* Memory functions, same as I/O accesses on Ultra. */
-static inline u8 _readb(const volatile void __iomem *addr)
-{ u8 ret;
-
- __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
- return ret;
-}
-
-static inline u16 _readw(const volatile void __iomem *addr)
-{ u16 ret;
-
- __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
-
- return ret;
-}
-
-static inline u32 _readl(const volatile void __iomem *addr)
-{ u32 ret;
-
- __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
-
- return ret;
-}
-
-static inline u64 _readq(const volatile void __iomem *addr)
-{ u64 ret;
-
- __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
-
- return ret;
-}
-
-static inline void _writeb(u8 b, volatile void __iomem *addr)
-{
- __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
- : /* no outputs */
- : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
-}
-
-static inline void _writew(u16 w, volatile void __iomem *addr)
-{
- __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
- : /* no outputs */
- : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
-}
-
-static inline void _writel(u32 l, volatile void __iomem *addr)
-{
- __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
- : /* no outputs */
- : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
-}
-
-static inline void _writeq(u64 q, volatile void __iomem *addr)
-{
- __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
- : /* no outputs */
- : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
- : "memory");
-}
-
-#define readb(__addr) _readb(__addr)
-#define readw(__addr) _readw(__addr)
-#define readl(__addr) _readl(__addr)
-#define readq(__addr) _readq(__addr)
-#define readb_relaxed(__addr) _readb(__addr)
-#define readw_relaxed(__addr) _readw(__addr)
-#define readl_relaxed(__addr) _readl(__addr)
-#define readq_relaxed(__addr) _readq(__addr)
-#define writeb(__b, __addr) _writeb(__b, __addr)
-#define writew(__w, __addr) _writew(__w, __addr)
-#define writel(__l, __addr) _writel(__l, __addr)
-#define writeq(__q, __addr) _writeq(__q, __addr)
-
-/* Now versions without byte-swapping. */
-static inline u8 _raw_readb(unsigned long addr)
-{
- u8 ret;
-
- __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-
- return ret;
-}
-
-static inline u16 _raw_readw(unsigned long addr)
-{
- u16 ret;
-
- __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-
- return ret;
-}
-
-static inline u32 _raw_readl(unsigned long addr)
-{
- u32 ret;
-
- __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-
- return ret;
-}
-
-static inline u64 _raw_readq(unsigned long addr)
-{
- u64 ret;
-
- __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-
- return ret;
-}
-
-static inline void _raw_writeb(u8 b, unsigned long addr)
-{
- __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
- : /* no outputs */
- : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-}
-
-static inline void _raw_writew(u16 w, unsigned long addr)
-{
- __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
- : /* no outputs */
- : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-}
-
-static inline void _raw_writel(u32 l, unsigned long addr)
-{
- __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
- : /* no outputs */
- : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-}
-
-static inline void _raw_writeq(u64 q, unsigned long addr)
-{
- __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
- : /* no outputs */
- : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-}
-
-#define __raw_readb(__addr) (_raw_readb((unsigned long)(__addr)))
-#define __raw_readw(__addr) (_raw_readw((unsigned long)(__addr)))
-#define __raw_readl(__addr) (_raw_readl((unsigned long)(__addr)))
-#define __raw_readq(__addr) (_raw_readq((unsigned long)(__addr)))
-#define __raw_writeb(__b, __addr) (_raw_writeb((u8)(__b), (unsigned long)(__addr)))
-#define __raw_writew(__w, __addr) (_raw_writew((u16)(__w), (unsigned long)(__addr)))
-#define __raw_writel(__l, __addr) (_raw_writel((u32)(__l), (unsigned long)(__addr)))
-#define __raw_writeq(__q, __addr) (_raw_writeq((u64)(__q), (unsigned long)(__addr)))
-
-/* Valid I/O Space regions are anywhere, because each PCI bus supported
- * can live in an arbitrary area of the physical address range.
- */
-#define IO_SPACE_LIMIT 0xffffffffffffffffUL
-
-/* Now, SBUS variants, only difference from PCI is that we do
- * not use little-endian ASIs.
- */
-static inline u8 _sbus_readb(const volatile void __iomem *addr)
-{
- u8 ret;
-
- __asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
- : "memory");
-
- return ret;
-}
-
-static inline u16 _sbus_readw(const volatile void __iomem *addr)
-{
- u16 ret;
-
- __asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
- : "memory");
-
- return ret;
-}
-
-static inline u32 _sbus_readl(const volatile void __iomem *addr)
-{
- u32 ret;
-
- __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
- : "memory");
-
- return ret;
-}
-
-static inline u64 _sbus_readq(const volatile void __iomem *addr)
-{
- u64 ret;
-
- __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
- : "memory");
-
- return ret;
-}
-
-static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
-{
- __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
- : /* no outputs */
- : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
- : "memory");
-}
-
-static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
-{
- __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
- : /* no outputs */
- : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
- : "memory");
-}
-
-static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
-{
- __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
- : /* no outputs */
- : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
- : "memory");
-}
-
-static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
-{
- __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
- : /* no outputs */
- : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
- : "memory");
-}
-
-#define sbus_readb(__addr) _sbus_readb(__addr)
-#define sbus_readw(__addr) _sbus_readw(__addr)
-#define sbus_readl(__addr) _sbus_readl(__addr)
-#define sbus_readq(__addr) _sbus_readq(__addr)
-#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr)
-#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr)
-#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
-#define sbus_writeq(__l, __addr) _sbus_writeq(__l, __addr)
-
-static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
-{
- while(n--) {
- sbus_writeb(c, dst);
- dst++;
- }
-}
-
-#define sbus_memset_io(d,c,sz) _sbus_memset_io(d,c,sz)
-
-static inline void
-_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
-{
- volatile void __iomem *d = dst;
-
- while (n--) {
- writeb(c, d);
- d++;
- }
-}
-
-#define memset_io(d,c,sz) _memset_io(d,c,sz)
-
-static inline void
-_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
-{
- char *d = dst;
-
- while (n--) {
- char tmp = readb(src);
- *d++ = tmp;
- src++;
- }
-}
-
-#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
-
-static inline void
-_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
-{
- const char *s = src;
- volatile void __iomem *d = dst;
-
- while (n--) {
- char tmp = *s++;
- writeb(tmp, d);
- d++;
- }
-}
-
-#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
-
-#define mmiowb()
-
-#ifdef __KERNEL__
-
-/* On sparc64 we have the whole physical IO address space accessible
- * using physically addressed loads and stores, so this does nothing.
- */
-static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
-{
- return (void __iomem *)offset;
-}
-
-#define ioremap_nocache(X,Y) ioremap((X),(Y))
-#define ioremap_wc(X,Y) ioremap((X),(Y))
-
-static inline void iounmap(volatile void __iomem *addr)
-{
-}
-
-#define ioread8(X) readb(X)
-#define ioread16(X) readw(X)
-#define ioread32(X) readl(X)
-#define iowrite8(val,X) writeb(val,X)
-#define iowrite16(val,X) writew(val,X)
-#define iowrite32(val,X) writel(val,X)
-
-/* Create a virtual mapping cookie for an IO port range */
-extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
-extern void ioport_unmap(void __iomem *);
-
-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
-struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
-extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
-
-/* Similarly for SBUS. */
-#define sbus_ioremap(__res, __offset, __size, __name) \
-({ unsigned long __ret; \
- __ret = (__res)->start + (((__res)->flags & 0x1ffUL) << 32UL); \
- __ret += (unsigned long) (__offset); \
- if (! request_region((__ret), (__size), (__name))) \
- __ret = 0UL; \
- (void __iomem *) __ret; \
-})
-
-#define sbus_iounmap(__addr, __size) \
- release_region((unsigned long)(__addr), (__size))
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p) __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p) p
-
-#endif
-
-#endif /* !(__SPARC64_IO_H) */
+++ /dev/null
-#ifndef _SPARC_IOCTL_H
-#define _SPARC_IOCTL_H
-
-/*
- * Our DIR and SIZE overlap in order to simulteneously provide
- * a non-zero _IOC_NONE (for binary compatibility) and
- * 14 bits of size as on i386. Here's the layout:
- *
- * 0xE0000000 DIR
- * 0x80000000 DIR = WRITE
- * 0x40000000 DIR = READ
- * 0x20000000 DIR = NONE
- * 0x3FFF0000 SIZE (overlaps NONE bit)
- * 0x0000FF00 TYPE
- * 0x000000FF NR (CMD)
- */
-
-#define _IOC_NRBITS 8
-#define _IOC_TYPEBITS 8
-#define _IOC_SIZEBITS 13 /* Actually 14, see below. */
-#define _IOC_DIRBITS 3
-
-#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
-#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
-#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
-#define _IOC_XSIZEMASK ((1 << (_IOC_SIZEBITS+1))-1)
-#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
-
-#define _IOC_NRSHIFT 0
-#define _IOC_TYPESHIFT (_IOC_NRSHIFT + _IOC_NRBITS)
-#define _IOC_SIZESHIFT (_IOC_TYPESHIFT + _IOC_TYPEBITS)
-#define _IOC_DIRSHIFT (_IOC_SIZESHIFT + _IOC_SIZEBITS)
-
-#define _IOC_NONE 1U
-#define _IOC_READ 2U
-#define _IOC_WRITE 4U
-
-#define _IOC(dir,type,nr,size) \
- (((dir) << _IOC_DIRSHIFT) | \
- ((type) << _IOC_TYPESHIFT) | \
- ((nr) << _IOC_NRSHIFT) | \
- ((size) << _IOC_SIZESHIFT))
-
-#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
-#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
-#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
-#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
-
-/* Used to decode ioctl numbers in drivers despite the leading underscore... */
-#define _IOC_DIR(nr) \
- ( (((((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) & (_IOC_WRITE|_IOC_READ)) != 0)? \
- (((nr) >> _IOC_DIRSHIFT) & (_IOC_WRITE|_IOC_READ)): \
- (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) )
-#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
-#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
-#define _IOC_SIZE(nr) \
- ((((((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) & (_IOC_WRITE|_IOC_READ)) == 0)? \
- 0: (((nr) >> _IOC_SIZESHIFT) & _IOC_XSIZEMASK))
-
-/* ...and for the PCMCIA and sound. */
-#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
-#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
-#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
-#define IOCSIZE_MASK (_IOC_XSIZEMASK << _IOC_SIZESHIFT)
-#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
-
-#endif /* !(_SPARC_IOCTL_H) */
+++ /dev/null
-#ifndef _ASM_SPARC_IOCTLS_H
-#define _ASM_SPARC_IOCTLS_H
-
-#include <asm/ioctl.h>
-
-/* Big T */
-#define TCGETA _IOR('T', 1, struct termio)
-#define TCSETA _IOW('T', 2, struct termio)
-#define TCSETAW _IOW('T', 3, struct termio)
-#define TCSETAF _IOW('T', 4, struct termio)
-#define TCSBRK _IO('T', 5)
-#define TCXONC _IO('T', 6)
-#define TCFLSH _IO('T', 7)
-#define TCGETS _IOR('T', 8, struct termios)
-#define TCSETS _IOW('T', 9, struct termios)
-#define TCSETSW _IOW('T', 10, struct termios)
-#define TCSETSF _IOW('T', 11, struct termios)
-#define TCGETS2 _IOR('T', 12, struct termios2)
-#define TCSETS2 _IOW('T', 13, struct termios2)
-#define TCSETSW2 _IOW('T', 14, struct termios2)
-#define TCSETSF2 _IOW('T', 15, struct termios2)
-
-/* Note that all the ioctls that are not available in Linux have a
- * double underscore on the front to: a) avoid some programs to
- * think we support some ioctls under Linux (autoconfiguration stuff)
- */
-/* Little t */
-#define TIOCGETD _IOR('t', 0, int)
-#define TIOCSETD _IOW('t', 1, int)
-#define __TIOCHPCL _IO('t', 2) /* SunOS Specific */
-#define __TIOCMODG _IOR('t', 3, int) /* SunOS Specific */
-#define __TIOCMODS _IOW('t', 4, int) /* SunOS Specific */
-#define __TIOCGETP _IOR('t', 8, struct sgttyb) /* SunOS Specific */
-#define __TIOCSETP _IOW('t', 9, struct sgttyb) /* SunOS Specific */
-#define __TIOCSETN _IOW('t', 10, struct sgttyb) /* SunOS Specific */
-#define TIOCEXCL _IO('t', 13)
-#define TIOCNXCL _IO('t', 14)
-#define __TIOCFLUSH _IOW('t', 16, int) /* SunOS Specific */
-#define __TIOCSETC _IOW('t', 17, struct tchars) /* SunOS Specific */
-#define __TIOCGETC _IOR('t', 18, struct tchars) /* SunOS Specific */
-#define __TIOCTCNTL _IOW('t', 32, int) /* SunOS Specific */
-#define __TIOCSIGNAL _IOW('t', 33, int) /* SunOS Specific */
-#define __TIOCSETX _IOW('t', 34, int) /* SunOS Specific */
-#define __TIOCGETX _IOR('t', 35, int) /* SunOS Specific */
-#define TIOCCONS _IO('t', 36)
-#define TIOCGSOFTCAR _IOR('t', 100, int)
-#define TIOCSSOFTCAR _IOW('t', 101, int)
-#define __TIOCUCNTL _IOW('t', 102, int) /* SunOS Specific */
-#define TIOCSWINSZ _IOW('t', 103, struct winsize)
-#define TIOCGWINSZ _IOR('t', 104, struct winsize)
-#define __TIOCREMOTE _IOW('t', 105, int) /* SunOS Specific */
-#define TIOCMGET _IOR('t', 106, int)
-#define TIOCMBIC _IOW('t', 107, int)
-#define TIOCMBIS _IOW('t', 108, int)
-#define TIOCMSET _IOW('t', 109, int)
-#define TIOCSTART _IO('t', 110)
-#define TIOCSTOP _IO('t', 111)
-#define TIOCPKT _IOW('t', 112, int)
-#define TIOCNOTTY _IO('t', 113)
-#define TIOCSTI _IOW('t', 114, char)
-#define TIOCOUTQ _IOR('t', 115, int)
-#define __TIOCGLTC _IOR('t', 116, struct ltchars) /* SunOS Specific */
-#define __TIOCSLTC _IOW('t', 117, struct ltchars) /* SunOS Specific */
-/* 118 is the non-posix setpgrp tty ioctl */
-/* 119 is the non-posix getpgrp tty ioctl */
-#define __TIOCCDTR _IO('t', 120) /* SunOS Specific */
-#define __TIOCSDTR _IO('t', 121) /* SunOS Specific */
-#define TIOCCBRK _IO('t', 122)
-#define TIOCSBRK _IO('t', 123)
-#define __TIOCLGET _IOW('t', 124, int) /* SunOS Specific */
-#define __TIOCLSET _IOW('t', 125, int) /* SunOS Specific */
-#define __TIOCLBIC _IOW('t', 126, int) /* SunOS Specific */
-#define __TIOCLBIS _IOW('t', 127, int) /* SunOS Specific */
-#define __TIOCISPACE _IOR('t', 128, int) /* SunOS Specific */
-#define __TIOCISIZE _IOR('t', 129, int) /* SunOS Specific */
-#define TIOCSPGRP _IOW('t', 130, int)
-#define TIOCGPGRP _IOR('t', 131, int)
-#define TIOCSCTTY _IO('t', 132)
-#define TIOCGSID _IOR('t', 133, int)
-/* Get minor device of a pty master's FD -- Solaris equiv is ISPTM */
-#define TIOCGPTN _IOR('t', 134, unsigned int) /* Get Pty Number */
-#define TIOCSPTLCK _IOW('t', 135, int) /* Lock/unlock PTY */
-
-/* Little f */
-#define FIOCLEX _IO('f', 1)
-#define FIONCLEX _IO('f', 2)
-#define FIOASYNC _IOW('f', 125, int)
-#define FIONBIO _IOW('f', 126, int)
-#define FIONREAD _IOR('f', 127, int)
-#define TIOCINQ FIONREAD
-#define FIOQSIZE _IOR('f', 128, loff_t)
-
-/* SCARY Rutgers local SunOS kernel hackery, perhaps I will support it
- * someday. This is completely bogus, I know...
- */
-#define __TCGETSTAT _IO('T', 200) /* Rutgers specific */
-#define __TCSETSTAT _IO('T', 201) /* Rutgers specific */
-
-/* Linux specific, no SunOS equivalent. */
-#define TIOCLINUX 0x541C
-#define TIOCGSERIAL 0x541E
-#define TIOCSSERIAL 0x541F
-#define TCSBRKP 0x5425
-#define TIOCSERCONFIG 0x5453
-#define TIOCSERGWILD 0x5454
-#define TIOCSERSWILD 0x5455
-#define TIOCGLCKTRMIOS 0x5456
-#define TIOCSLCKTRMIOS 0x5457
-#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
-#define TIOCSERGETLSR 0x5459 /* Get line status register */
-#define TIOCSERGETMULTI 0x545A /* Get multiport config */
-#define TIOCSERSETMULTI 0x545B /* Set multiport config */
-#define TIOCMIWAIT 0x545C /* Wait for change on serial input line(s) */
-#define TIOCGICOUNT 0x545D /* Read serial port inline interrupt counts */
-
-/* Kernel definitions */
-#ifdef __KERNEL__
-#define TIOCGETC __TIOCGETC
-#define TIOCGETP __TIOCGETP
-#define TIOCGLTC __TIOCGLTC
-#define TIOCSLTC __TIOCSLTC
-#define TIOCSETP __TIOCSETP
-#define TIOCSETN __TIOCSETN
-#define TIOCSETC __TIOCSETC
-#endif
-
-/* Used for packet mode */
-#define TIOCPKT_DATA 0
-#define TIOCPKT_FLUSHREAD 1
-#define TIOCPKT_FLUSHWRITE 2
-#define TIOCPKT_STOP 4
-#define TIOCPKT_START 8
-#define TIOCPKT_NOSTOP 16
-#define TIOCPKT_DOSTOP 32
-
-#endif /* !(_ASM_SPARC_IOCTLS_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_IOMMU_H
-#define ___ASM_SPARC_IOMMU_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/iommu_64.h>
-#else
-#include <asm-sparc/iommu_32.h>
-#endif
-#endif
+++ /dev/null
-/* iommu.h: Definitions for the sun4m IOMMU.
- *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- */
-#ifndef _SPARC_IOMMU_H
-#define _SPARC_IOMMU_H
-
-#include <asm/page.h>
-#include <asm/bitext.h>
-
-/* The iommu handles all virtual to physical address translations
- * that occur between the SBUS and physical memory. Access by
- * the cpu to IO registers and similar go over the mbus so are
- * translated by the on chip SRMMU. The iommu and the srmmu do
- * not need to have the same translations at all, in fact most
- * of the time the translations they handle are a disjunct set.
- * Basically the iommu handles all dvma sbus activity.
- */
-
-/* The IOMMU registers occupy three pages in IO space. */
-struct iommu_regs {
- /* First page */
- volatile unsigned long control; /* IOMMU control */
- volatile unsigned long base; /* Physical base of iopte page table */
- volatile unsigned long _unused1[3];
- volatile unsigned long tlbflush; /* write only */
- volatile unsigned long pageflush; /* write only */
- volatile unsigned long _unused2[1017];
- /* Second page */
- volatile unsigned long afsr; /* Async-fault status register */
- volatile unsigned long afar; /* Async-fault physical address */
- volatile unsigned long _unused3[2];
- volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
- volatile unsigned long sbuscfg1;
- volatile unsigned long sbuscfg2;
- volatile unsigned long sbuscfg3;
- volatile unsigned long mfsr; /* Memory-fault status register */
- volatile unsigned long mfar; /* Memory-fault physical address */
- volatile unsigned long _unused4[1014];
- /* Third page */
- volatile unsigned long mid; /* IOMMU module-id */
-};
-
-#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
-#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
-#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
-#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
-#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
-#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
-#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
-#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
-#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
-#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
-#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
-#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
-
-#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
-#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
-#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
-#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
-#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
-#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
-#define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
-#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
-#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
-#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
-
-#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
-#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
-#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
-#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
- produced by this device as pure
- physical. */
-
-#define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
-#define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
-#define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
-#define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
-#define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
- on the even word of the access, low bit
- indicated odd word caused the parity error */
-#define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
-#define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
-#define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
-
-#define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
-#define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
-#define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
-#define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
-#define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
-#define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
-#define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
-
-/* The format of an iopte in the page tables */
-#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
-#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
-#define IOPTE_WRITE 0x00000004 /* Writeable */
-#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
-#define IOPTE_WAZ 0x00000001 /* Write as zeros */
-
-struct iommu_struct {
- struct iommu_regs *regs;
- iopte_t *page_table;
- /* For convenience */
- unsigned long start; /* First managed virtual address */
- unsigned long end; /* Last managed virtual address */
-
- struct bit_map usemap;
-};
-
-static inline void iommu_invalidate(struct iommu_regs *regs)
-{
- regs->tlbflush = 0;
-}
-
-static inline void iommu_invalidate_page(struct iommu_regs *regs, unsigned long ba)
-{
- regs->pageflush = (ba & PAGE_MASK);
-}
-
-#endif /* !(_SPARC_IOMMU_H) */
+++ /dev/null
-/* iommu.h: Definitions for the sun5 IOMMU.
- *
- * Copyright (C) 1996, 1999, 2007 David S. Miller (davem@davemloft.net)
- */
-#ifndef _SPARC64_IOMMU_H
-#define _SPARC64_IOMMU_H
-
-/* The format of an iopte in the page tables. */
-#define IOPTE_VALID 0x8000000000000000UL
-#define IOPTE_64K 0x2000000000000000UL
-#define IOPTE_STBUF 0x1000000000000000UL
-#define IOPTE_INTRA 0x0800000000000000UL
-#define IOPTE_CONTEXT 0x07ff800000000000UL
-#define IOPTE_PAGE 0x00007fffffffe000UL
-#define IOPTE_CACHE 0x0000000000000010UL
-#define IOPTE_WRITE 0x0000000000000002UL
-
-#define IOMMU_NUM_CTXS 4096
-
-struct iommu_arena {
- unsigned long *map;
- unsigned int hint;
- unsigned int limit;
-};
-
-struct iommu {
- spinlock_t lock;
- struct iommu_arena arena;
- void (*flush_all)(struct iommu *);
- iopte_t *page_table;
- u32 page_table_map_base;
- unsigned long iommu_control;
- unsigned long iommu_tsbbase;
- unsigned long iommu_flush;
- unsigned long iommu_flushinv;
- unsigned long iommu_tags;
- unsigned long iommu_ctxflush;
- unsigned long write_complete_reg;
- unsigned long dummy_page;
- unsigned long dummy_page_pa;
- unsigned long ctx_lowest_free;
- DECLARE_BITMAP(ctx_bitmap, IOMMU_NUM_CTXS);
- u32 dma_addr_mask;
-};
-
-struct strbuf {
- int strbuf_enabled;
- unsigned long strbuf_control;
- unsigned long strbuf_pflush;
- unsigned long strbuf_fsync;
- unsigned long strbuf_ctxflush;
- unsigned long strbuf_ctxmatch_base;
- unsigned long strbuf_flushflag_pa;
- volatile unsigned long *strbuf_flushflag;
- volatile unsigned long __flushflag_buf[(64+(64-1)) / sizeof(long)];
-};
-
-extern int iommu_table_init(struct iommu *iommu, int tsbsize,
- u32 dma_offset, u32 dma_addr_mask,
- int numa_node);
-
-#endif /* !(_SPARC64_IOMMU_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_IPCBUF_H
-#define ___ASM_SPARC_IPCBUF_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/ipcbuf_64.h>
-#else
-#include <asm-sparc/ipcbuf_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _SPARC_IPCBUF_H
-#define _SPARC_IPCBUF_H
-
-/*
- * The ipc64_perm structure for sparc architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 32-bit mode
- * - 32-bit seq
- * - 2 miscellaneous 64-bit values (so that this structure matches
- * sparc64 ipc64_perm)
- */
-
-struct ipc64_perm
-{
- __kernel_key_t key;
- __kernel_uid32_t uid;
- __kernel_gid32_t gid;
- __kernel_uid32_t cuid;
- __kernel_gid32_t cgid;
- unsigned short __pad1;
- __kernel_mode_t mode;
- unsigned short __pad2;
- unsigned short seq;
- unsigned long long __unused1;
- unsigned long long __unused2;
-};
-
-#endif /* _SPARC_IPCBUF_H */
+++ /dev/null
-#ifndef _SPARC64_IPCBUF_H
-#define _SPARC64_IPCBUF_H
-
-/*
- * The ipc64_perm structure for sparc64 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 32-bit seq
- * - 2 miscellaneous 64-bit values
- */
-
-struct ipc64_perm
-{
- __kernel_key_t key;
- __kernel_uid_t uid;
- __kernel_gid_t gid;
- __kernel_uid_t cuid;
- __kernel_gid_t cgid;
- __kernel_mode_t mode;
- unsigned short __pad1;
- unsigned short seq;
- unsigned long __unused1;
- unsigned long __unused2;
-};
-
-#endif /* _SPARC64_IPCBUF_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_IRQ_H
-#define ___ASM_SPARC_IRQ_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/irq_64.h>
-#else
-#include <asm-sparc/irq_32.h>
-#endif
-#endif
+++ /dev/null
-/* irq.h: IRQ registers on the Sparc.
- *
- * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
- */
-
-#ifndef _SPARC_IRQ_H
-#define _SPARC_IRQ_H
-
-#include <linux/interrupt.h>
-
-#define NR_IRQS 16
-
-#define irq_canonicalize(irq) (irq)
-
-#endif
+++ /dev/null
-/* irq.h: IRQ registers on the 64-bit Sparc.
- *
- * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
- * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
- */
-
-#ifndef _SPARC64_IRQ_H
-#define _SPARC64_IRQ_H
-
-#include <linux/linkage.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <asm/pil.h>
-#include <asm/ptrace.h>
-
-/* IMAP/ICLR register defines */
-#define IMAP_VALID 0x80000000UL /* IRQ Enabled */
-#define IMAP_TID_UPA 0x7c000000UL /* UPA TargetID */
-#define IMAP_TID_JBUS 0x7c000000UL /* JBUS TargetID */
-#define IMAP_TID_SHIFT 26
-#define IMAP_AID_SAFARI 0x7c000000UL /* Safari AgentID */
-#define IMAP_AID_SHIFT 26
-#define IMAP_NID_SAFARI 0x03e00000UL /* Safari NodeID */
-#define IMAP_NID_SHIFT 21
-#define IMAP_IGN 0x000007c0UL /* IRQ Group Number */
-#define IMAP_INO 0x0000003fUL /* IRQ Number */
-#define IMAP_INR 0x000007ffUL /* Full interrupt number*/
-
-#define ICLR_IDLE 0x00000000UL /* Idle state */
-#define ICLR_TRANSMIT 0x00000001UL /* Transmit state */
-#define ICLR_PENDING 0x00000003UL /* Pending state */
-
-/* The largest number of unique interrupt sources we support.
- * If this needs to ever be larger than 255, you need to change
- * the type of ino_bucket->virt_irq as appropriate.
- *
- * ino_bucket->virt_irq allocation is made during {sun4v_,}build_irq().
- */
-#define NR_IRQS 255
-
-extern void irq_install_pre_handler(int virt_irq,
- void (*func)(unsigned int, void *, void *),
- void *arg1, void *arg2);
-#define irq_canonicalize(irq) (irq)
-extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
-extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
-extern unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino);
-extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
- unsigned int msi_devino_start,
- unsigned int msi_devino_end);
-extern void sun4v_destroy_msi(unsigned int virt_irq);
-extern unsigned int sun4u_build_msi(u32 portid, unsigned int *virt_irq_p,
- unsigned int msi_devino_start,
- unsigned int msi_devino_end,
- unsigned long imap_base,
- unsigned long iclr_base);
-extern void sun4u_destroy_msi(unsigned int virt_irq);
-extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
-
-extern unsigned char virt_irq_alloc(unsigned int dev_handle,
- unsigned int dev_ino);
-#ifdef CONFIG_PCI_MSI
-extern void virt_irq_free(unsigned int virt_irq);
-#endif
-
-extern void __init init_IRQ(void);
-extern void fixup_irqs(void);
-
-static inline void set_softint(unsigned long bits)
-{
- __asm__ __volatile__("wr %0, 0x0, %%set_softint"
- : /* No outputs */
- : "r" (bits));
-}
-
-static inline void clear_softint(unsigned long bits)
-{
- __asm__ __volatile__("wr %0, 0x0, %%clear_softint"
- : /* No outputs */
- : "r" (bits));
-}
-
-static inline unsigned long get_softint(void)
-{
- unsigned long retval;
-
- __asm__ __volatile__("rd %%softint, %0"
- : "=r" (retval));
- return retval;
-}
-
-#endif
+++ /dev/null
-#include <asm-generic/irq_regs.h>
+++ /dev/null
-#ifndef ___ASM_SPARC_IRQFLAGS_H
-#define ___ASM_SPARC_IRQFLAGS_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/irqflags_64.h>
-#else
-#include <asm-sparc/irqflags_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * include/asm-sparc/irqflags.h
- *
- * IRQ flags handling
- *
- * This file gets included from lowlevel asm headers too, to provide
- * wrapped versions of the local_irq_*() APIs, based on the
- * raw_local_irq_*() functions from the lowlevel headers.
- */
-#ifndef _ASM_IRQFLAGS_H
-#define _ASM_IRQFLAGS_H
-
-#ifndef __ASSEMBLY__
-
-extern void raw_local_irq_restore(unsigned long);
-extern unsigned long __raw_local_irq_save(void);
-extern void raw_local_irq_enable(void);
-
-static inline unsigned long getipl(void)
-{
- unsigned long retval;
-
- __asm__ __volatile__("rd %%psr, %0" : "=r" (retval));
- return retval;
-}
-
-#define raw_local_save_flags(flags) ((flags) = getipl())
-#define raw_local_irq_save(flags) ((flags) = __raw_local_irq_save())
-#define raw_local_irq_disable() ((void) __raw_local_irq_save())
-#define raw_irqs_disabled() ((getipl() & PSR_PIL) != 0)
-
-static inline int raw_irqs_disabled_flags(unsigned long flags)
-{
- return ((flags & PSR_PIL) != 0);
-}
-
-#endif /* (__ASSEMBLY__) */
-
-#endif /* !(_ASM_IRQFLAGS_H) */
+++ /dev/null
-/*
- * include/asm-sparc64/irqflags.h
- *
- * IRQ flags handling
- *
- * This file gets included from lowlevel asm headers too, to provide
- * wrapped versions of the local_irq_*() APIs, based on the
- * raw_local_irq_*() functions from the lowlevel headers.
- */
-#ifndef _ASM_IRQFLAGS_H
-#define _ASM_IRQFLAGS_H
-
-#ifndef __ASSEMBLY__
-
-static inline unsigned long __raw_local_save_flags(void)
-{
- unsigned long flags;
-
- __asm__ __volatile__(
- "rdpr %%pil, %0"
- : "=r" (flags)
- );
-
- return flags;
-}
-
-#define raw_local_save_flags(flags) \
- do { (flags) = __raw_local_save_flags(); } while (0)
-
-static inline void raw_local_irq_restore(unsigned long flags)
-{
- __asm__ __volatile__(
- "wrpr %0, %%pil"
- : /* no output */
- : "r" (flags)
- : "memory"
- );
-}
-
-static inline void raw_local_irq_disable(void)
-{
- __asm__ __volatile__(
- "wrpr 15, %%pil"
- : /* no outputs */
- : /* no inputs */
- : "memory"
- );
-}
-
-static inline void raw_local_irq_enable(void)
-{
- __asm__ __volatile__(
- "wrpr 0, %%pil"
- : /* no outputs */
- : /* no inputs */
- : "memory"
- );
-}
-
-static inline int raw_irqs_disabled_flags(unsigned long flags)
-{
- return (flags > 0);
-}
-
-static inline int raw_irqs_disabled(void)
-{
- unsigned long flags = __raw_local_save_flags();
-
- return raw_irqs_disabled_flags(flags);
-}
-
-/*
- * For spinlocks, etc:
- */
-static inline unsigned long __raw_local_irq_save(void)
-{
- unsigned long flags = __raw_local_save_flags();
-
- raw_local_irq_disable();
-
- return flags;
-}
-
-#define raw_local_irq_save(flags) \
- do { (flags) = __raw_local_irq_save(); } while (0)
-
-#endif /* (__ASSEMBLY__) */
-
-#endif /* !(_ASM_IRQFLAGS_H) */
+++ /dev/null
-/*
- * jsflash.h: OS Flash SIMM support for JavaStations.
- *
- * Copyright (C) 1999 Pete Zaitcev
- */
-
-#ifndef _SPARC_JSFLASH_H
-#define _SPARC_JSFLASH_H
-
-#ifndef _SPARC_TYPES_H
-#include <asm/types.h>
-#endif
-
-/*
- * Semantics of the offset is a full address.
- * Hardcode it or get it from probe ioctl.
- *
- * We use full bus address, so that we would be
- * automatically compatible with possible future systems.
- */
-
-#define JSFLASH_IDENT (('F'<<8)|54)
-struct jsflash_ident_arg {
- __u64 off; /* 0x20000000 is included */
- __u32 size;
- char name[32]; /* With trailing zero */
-};
-
-#define JSFLASH_ERASE (('F'<<8)|55)
-/* Put 0 as argument, may be flags or sector number... */
-
-#define JSFLASH_PROGRAM (('F'<<8)|56)
-struct jsflash_program_arg {
- __u64 data; /* char* for sparc and sparc64 */
- __u64 off;
- __u32 size;
-};
-
-#endif /* _SPARC_JSFLASH_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_KDEBUG_H
-#define ___ASM_SPARC_KDEBUG_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/kdebug_64.h>
-#else
-#include <asm-sparc/kdebug_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * kdebug.h: Defines and definitions for debugging the Linux kernel
- * under various kernel debuggers.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-#ifndef _SPARC_KDEBUG_H
-#define _SPARC_KDEBUG_H
-
-#include <asm/openprom.h>
-#include <asm/vaddrs.h>
-
-/* Breakpoints are enter through trap table entry 126. So in sparc assembly
- * if you want to drop into the debugger you do:
- *
- * t DEBUG_BP_TRAP
- */
-
-#define DEBUG_BP_TRAP 126
-
-#ifndef __ASSEMBLY__
-/* The debug vector is passed in %o1 at boot time. It is a pointer to
- * a structure in the debuggers address space. Here is its format.
- */
-
-typedef unsigned int (*debugger_funct)(void);
-
-struct kernel_debug {
- /* First the entry point into the debugger. You jump here
- * to give control over to the debugger.
- */
- unsigned long kdebug_entry;
- unsigned long kdebug_trapme; /* Figure out later... */
- /* The following is the number of pages that the debugger has
- * taken from to total pool.
- */
- unsigned long *kdebug_stolen_pages;
- /* Ok, after you remap yourself and/or change the trap table
- * from what you were left with at boot time you have to call
- * this synchronization function so the debugger can check out
- * what you have done.
- */
- debugger_funct teach_debugger;
-}; /* I think that is it... */
-
-extern struct kernel_debug *linux_dbvec;
-
-/* Use this macro in C-code to enter the debugger. */
-static inline void sp_enter_debugger(void)
-{
- __asm__ __volatile__("jmpl %0, %%o7\n\t"
- "nop\n\t" : :
- "r" (linux_dbvec) : "o7", "memory");
-}
-
-#define SP_ENTER_DEBUGGER do { \
- if((linux_dbvec!=0) && ((*(short *)linux_dbvec)!=-1)) \
- sp_enter_debugger(); \
- } while(0)
-
-enum die_val {
- DIE_UNUSED,
-};
-
-#endif /* !(__ASSEMBLY__) */
-
-/* Some nice offset defines for assembler code. */
-#define KDEBUG_ENTRY_OFF 0x0
-#define KDEBUG_DUNNO_OFF 0x4
-#define KDEBUG_DUNNO2_OFF 0x8
-#define KDEBUG_TEACH_OFF 0xc
-
-#endif /* !(_SPARC_KDEBUG_H) */
+++ /dev/null
-#ifndef _SPARC64_KDEBUG_H
-#define _SPARC64_KDEBUG_H
-
-struct pt_regs;
-
-extern void bad_trap(struct pt_regs *, long);
-
-/* Grossly misnamed. */
-enum die_val {
- DIE_OOPS = 1,
- DIE_DEBUG, /* ta 0x70 */
- DIE_DEBUG_2, /* ta 0x71 */
- DIE_DIE,
- DIE_TRAP,
- DIE_TRAP_TL1,
- DIE_CALL,
-};
-
-#endif
+++ /dev/null
-#ifndef _SPARC_KGDB_H
-#define _SPARC_KGDB_H
-
-#ifdef CONFIG_SPARC32
-#define BUFMAX 2048
-#else
-#define BUFMAX 4096
-#endif
-
-enum regnames {
- GDB_G0, GDB_G1, GDB_G2, GDB_G3, GDB_G4, GDB_G5, GDB_G6, GDB_G7,
- GDB_O0, GDB_O1, GDB_O2, GDB_O3, GDB_O4, GDB_O5, GDB_SP, GDB_O7,
- GDB_L0, GDB_L1, GDB_L2, GDB_L3, GDB_L4, GDB_L5, GDB_L6, GDB_L7,
- GDB_I0, GDB_I1, GDB_I2, GDB_I3, GDB_I4, GDB_I5, GDB_FP, GDB_I7,
- GDB_F0,
- GDB_F31 = GDB_F0 + 31,
-#ifdef CONFIG_SPARC32
- GDB_Y, GDB_PSR, GDB_WIM, GDB_TBR, GDB_PC, GDB_NPC,
- GDB_FSR, GDB_CSR,
-#else
- GDB_F32 = GDB_F0 + 32,
- GDB_F62 = GDB_F32 + 15,
- GDB_PC, GDB_NPC, GDB_STATE, GDB_FSR, GDB_FPRS, GDB_Y,
-#endif
-};
-
-#ifdef CONFIG_SPARC32
-#define NUMREGBYTES ((GDB_CSR + 1) * 4)
-#else
-#define NUMREGBYTES ((GDB_Y + 1) * 8)
-#endif
-
-extern void arch_kgdb_breakpoint(void);
-
-#define BREAK_INSTR_SIZE 4
-#define CACHE_FLUSH_IS_SAFE 1
-
-#endif /* _SPARC_KGDB_H */
+++ /dev/null
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-/* Dummy header just to define km_type. None of this
- * is actually used on sparc. -DaveM
- */
-
-enum km_type {
- KM_BOUNCE_READ,
- KM_SKB_SUNRPC_DATA,
- KM_SKB_DATA_SOFTIRQ,
- KM_USER0,
- KM_USER1,
- KM_BIO_SRC_IRQ,
- KM_BIO_DST_IRQ,
- KM_PTE0,
- KM_PTE1,
- KM_IRQ0,
- KM_IRQ1,
- KM_SOFTIRQ0,
- KM_SOFTIRQ1,
- KM_TYPE_NR
-};
-
-#endif
+++ /dev/null
-#ifndef _SPARC64_KPROBES_H
-#define _SPARC64_KPROBES_H
-
-#include <linux/types.h>
-#include <linux/percpu.h>
-
-typedef u32 kprobe_opcode_t;
-
-#define BREAKPOINT_INSTRUCTION 0x91d02070 /* ta 0x70 */
-#define BREAKPOINT_INSTRUCTION_2 0x91d02071 /* ta 0x71 */
-#define MAX_INSN_SIZE 2
-
-#define kretprobe_blacklist_size 0
-
-#define arch_remove_kprobe(p) do {} while (0)
-
-#define flush_insn_slot(p) \
-do { flushi(&(p)->ainsn.insn[0]); \
- flushi(&(p)->ainsn.insn[1]); \
-} while (0)
-
-void kretprobe_trampoline(void);
-
-/* Architecture specific copy of original instruction*/
-struct arch_specific_insn {
- /* copy of the original instruction */
- kprobe_opcode_t insn[MAX_INSN_SIZE];
-};
-
-struct prev_kprobe {
- struct kprobe *kp;
- unsigned long status;
- unsigned long orig_tnpc;
- unsigned long orig_tstate_pil;
-};
-
-/* per-cpu kprobe control block */
-struct kprobe_ctlblk {
- unsigned long kprobe_status;
- unsigned long kprobe_orig_tnpc;
- unsigned long kprobe_orig_tstate_pil;
- struct pt_regs jprobe_saved_regs;
- struct prev_kprobe prev_kprobe;
-};
-
-extern int kprobe_exceptions_notify(struct notifier_block *self,
- unsigned long val, void *data);
-extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
-#endif /* _SPARC64_KPROBES_H */
+++ /dev/null
-#ifndef _SPARC64_LDC_H
-#define _SPARC64_LDC_H
-
-#include <asm/hypervisor.h>
-
-extern int ldom_domaining_enabled;
-extern void ldom_set_var(const char *var, const char *value);
-extern void ldom_reboot(const char *boot_command);
-extern void ldom_power_off(void);
-
-/* The event handler will be evoked when link state changes
- * or data becomes available on the receive side.
- *
- * For non-RAW links, if the LDC_EVENT_RESET event arrives the
- * driver should reset all of it's internal state and reinvoke
- * ldc_connect() to try and bring the link up again.
- *
- * For RAW links, ldc_connect() is not used. Instead the driver
- * just waits for the LDC_EVENT_UP event.
- */
-struct ldc_channel_config {
- void (*event)(void *arg, int event);
-
- u32 mtu;
- unsigned int rx_irq;
- unsigned int tx_irq;
- u8 mode;
-#define LDC_MODE_RAW 0x00
-#define LDC_MODE_UNRELIABLE 0x01
-#define LDC_MODE_RESERVED 0x02
-#define LDC_MODE_STREAM 0x03
-
- u8 debug;
-#define LDC_DEBUG_HS 0x01
-#define LDC_DEBUG_STATE 0x02
-#define LDC_DEBUG_RX 0x04
-#define LDC_DEBUG_TX 0x08
-#define LDC_DEBUG_DATA 0x10
-};
-
-#define LDC_EVENT_RESET 0x01
-#define LDC_EVENT_UP 0x02
-#define LDC_EVENT_DATA_READY 0x04
-
-#define LDC_STATE_INVALID 0x00
-#define LDC_STATE_INIT 0x01
-#define LDC_STATE_BOUND 0x02
-#define LDC_STATE_READY 0x03
-#define LDC_STATE_CONNECTED 0x04
-
-struct ldc_channel;
-
-/* Allocate state for a channel. */
-extern struct ldc_channel *ldc_alloc(unsigned long id,
- const struct ldc_channel_config *cfgp,
- void *event_arg);
-
-/* Shut down and free state for a channel. */
-extern void ldc_free(struct ldc_channel *lp);
-
-/* Register TX and RX queues of the link with the hypervisor. */
-extern int ldc_bind(struct ldc_channel *lp, const char *name);
-
-/* For non-RAW protocols we need to complete a handshake before
- * communication can proceed. ldc_connect() does that, if the
- * handshake completes successfully, an LDC_EVENT_UP event will
- * be sent up to the driver.
- */
-extern int ldc_connect(struct ldc_channel *lp);
-extern int ldc_disconnect(struct ldc_channel *lp);
-
-extern int ldc_state(struct ldc_channel *lp);
-
-/* Read and write operations. Only valid when the link is up. */
-extern int ldc_write(struct ldc_channel *lp, const void *buf,
- unsigned int size);
-extern int ldc_read(struct ldc_channel *lp, void *buf, unsigned int size);
-
-#define LDC_MAP_SHADOW 0x01
-#define LDC_MAP_DIRECT 0x02
-#define LDC_MAP_IO 0x04
-#define LDC_MAP_R 0x08
-#define LDC_MAP_W 0x10
-#define LDC_MAP_X 0x20
-#define LDC_MAP_RW (LDC_MAP_R | LDC_MAP_W)
-#define LDC_MAP_RWX (LDC_MAP_R | LDC_MAP_W | LDC_MAP_X)
-#define LDC_MAP_ALL 0x03f
-
-struct ldc_trans_cookie {
- u64 cookie_addr;
- u64 cookie_size;
-};
-
-struct scatterlist;
-extern int ldc_map_sg(struct ldc_channel *lp,
- struct scatterlist *sg, int num_sg,
- struct ldc_trans_cookie *cookies, int ncookies,
- unsigned int map_perm);
-
-extern int ldc_map_single(struct ldc_channel *lp,
- void *buf, unsigned int len,
- struct ldc_trans_cookie *cookies, int ncookies,
- unsigned int map_perm);
-
-extern void ldc_unmap(struct ldc_channel *lp, struct ldc_trans_cookie *cookies,
- int ncookies);
-
-extern int ldc_copy(struct ldc_channel *lp, int copy_dir,
- void *buf, unsigned int len, unsigned long offset,
- struct ldc_trans_cookie *cookies, int ncookies);
-
-static inline int ldc_get_dring_entry(struct ldc_channel *lp,
- void *buf, unsigned int len,
- unsigned long offset,
- struct ldc_trans_cookie *cookies,
- int ncookies)
-{
- return ldc_copy(lp, LDC_COPY_IN, buf, len, offset, cookies, ncookies);
-}
-
-static inline int ldc_put_dring_entry(struct ldc_channel *lp,
- void *buf, unsigned int len,
- unsigned long offset,
- struct ldc_trans_cookie *cookies,
- int ncookies)
-{
- return ldc_copy(lp, LDC_COPY_OUT, buf, len, offset, cookies, ncookies);
-}
-
-extern void *ldc_alloc_exp_dring(struct ldc_channel *lp, unsigned int len,
- struct ldc_trans_cookie *cookies,
- int *ncookies, unsigned int map_perm);
-
-extern void ldc_free_exp_dring(struct ldc_channel *lp, void *buf,
- unsigned int len,
- struct ldc_trans_cookie *cookies, int ncookies);
-
-#endif /* _SPARC64_LDC_H */
+++ /dev/null
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-/* Nothing to see here... */
-
-#endif
+++ /dev/null
-#ifndef _SPARC64_LMB_H
-#define _SPARC64_LMB_H
-
-#include <asm/oplib.h>
-
-#define LMB_DBG(fmt...) prom_printf(fmt)
-
-#define LMB_REAL_LIMIT 0
-
-#endif /* !(_SPARC64_LMB_H) */
+++ /dev/null
-#ifndef _SPARC_LOCAL_H
-#define _SPARC_LOCAL_H
-
-#include <asm-generic/local.h>
-
-#endif
+++ /dev/null
-#ifndef _SPARC64_LSU_H
-#define _SPARC64_LSU_H
-
-#include <linux/const.h>
-
-/* LSU Control Register */
-#define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
-#define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/
-#define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/
-#define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/
-#define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/
-#define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/
-#define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables. */
-#define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable. */
-#define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable. */
-#define LSU_CONTROL_DC _AC(0x0000000000000002,UL) /* Data cache enable. */
-#define LSU_CONTROL_IC _AC(0x0000000000000001,UL) /* Instruction cache enable.*/
-
-#endif /* !(_SPARC64_LSU_H) */
+++ /dev/null
-/*
- * machines.h: Defines for taking apart the machine type value in the
- * idprom and determining the kind of machine we are on.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-#ifndef _SPARC_MACHINES_H
-#define _SPARC_MACHINES_H
-
-struct Sun_Machine_Models {
- char *name;
- unsigned char id_machtype;
-};
-
-/* Current number of machines we know about that has an IDPROM
- * machtype entry including one entry for the 0x80 OBP machines.
- */
-#define NUM_SUN_MACHINES 15
-
-/* The machine type in the idprom area looks like this:
- *
- * ---------------
- * | ARCH | MACH |
- * ---------------
- * 7 4 3 0
- *
- * The ARCH field determines the architecture line (sun4, sun4c, etc).
- * The MACH field determines the machine make within that architecture.
- */
-
-#define SM_ARCH_MASK 0xf0
-#define SM_SUN4 0x20
-#define SM_SUN4C 0x50
-#define SM_SUN4M 0x70
-#define SM_SUN4M_OBP 0x80
-
-#define SM_TYP_MASK 0x0f
-/* Sun4 machines */
-#define SM_4_260 0x01 /* Sun 4/200 series */
-#define SM_4_110 0x02 /* Sun 4/100 series */
-#define SM_4_330 0x03 /* Sun 4/300 series */
-#define SM_4_470 0x04 /* Sun 4/400 series */
-
-/* Sun4c machines Full Name - PROM NAME */
-#define SM_4C_SS1 0x01 /* Sun4c SparcStation 1 - Sun 4/60 */
-#define SM_4C_IPC 0x02 /* Sun4c SparcStation IPC - Sun 4/40 */
-#define SM_4C_SS1PLUS 0x03 /* Sun4c SparcStation 1+ - Sun 4/65 */
-#define SM_4C_SLC 0x04 /* Sun4c SparcStation SLC - Sun 4/20 */
-#define SM_4C_SS2 0x05 /* Sun4c SparcStation 2 - Sun 4/75 */
-#define SM_4C_ELC 0x06 /* Sun4c SparcStation ELC - Sun 4/25 */
-#define SM_4C_IPX 0x07 /* Sun4c SparcStation IPX - Sun 4/50 */
-
-/* Sun4m machines, these predate the OpenBoot. These values only mean
- * something if the value in the ARCH field is SM_SUN4M, if it is
- * SM_SUN4M_OBP then you have the following situation:
- * 1) You either have a sun4d, a sun4e, or a recently made sun4m.
- * 2) You have to consult OpenBoot to determine which machine this is.
- */
-#define SM_4M_SS60 0x01 /* Sun4m SparcSystem 600 */
-#define SM_4M_SS50 0x02 /* Sun4m SparcStation 10 */
-#define SM_4M_SS40 0x03 /* Sun4m SparcStation 5 */
-
-/* Sun4d machines -- N/A */
-/* Sun4e machines -- N/A */
-/* Sun4u machines -- N/A */
-
-#endif /* !(_SPARC_MACHINES_H) */
+++ /dev/null
-/*
- * mbus.h: Various defines for MBUS modules.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_MBUS_H
-#define _SPARC_MBUS_H
-
-#include <asm/ross.h> /* HyperSparc stuff */
-#include <asm/cypress.h> /* Cypress Chips */
-#include <asm/viking.h> /* Ugh, bug city... */
-
-enum mbus_module {
- HyperSparc = 0,
- Cypress = 1,
- Cypress_vE = 2,
- Cypress_vD = 3,
- Swift_ok = 4,
- Swift_bad_c = 5,
- Swift_lots_o_bugs = 6,
- Tsunami = 7,
- Viking_12 = 8,
- Viking_2x = 9,
- Viking_30 = 10,
- Viking_35 = 11,
- Viking_new = 12,
- TurboSparc = 13,
- SRMMU_INVAL_MOD = 14,
-};
-
-extern enum mbus_module srmmu_modtype;
-extern unsigned int viking_rev, swift_rev, cypress_rev;
-
-/* HW Mbus module bugs we have to deal with */
-#define HWBUG_COPYBACK_BROKEN 0x00000001
-#define HWBUG_ASIFLUSH_BROKEN 0x00000002
-#define HWBUG_VACFLUSH_BITROT 0x00000004
-#define HWBUG_KERN_ACCBROKEN 0x00000008
-#define HWBUG_KERN_CBITBROKEN 0x00000010
-#define HWBUG_MODIFIED_BITROT 0x00000020
-#define HWBUG_PC_BADFAULT_ADDR 0x00000040
-#define HWBUG_SUPERSCALAR_BAD 0x00000080
-#define HWBUG_PACINIT_BITROT 0x00000100
-
-/* First the module type values. To find out which you have, just load
- * the mmu control register from ASI_M_MMUREG alternate address space and
- * shift the value right 28 bits.
- */
-/* IMPL field means the company which produced the chip. */
-#define MBUS_VIKING 0x4 /* bleech, Texas Instruments Module */
-#define MBUS_LSI 0x3 /* LSI Logics */
-#define MBUS_ROSS 0x1 /* Ross is nice */
-#define MBUS_FMI 0x0 /* Fujitsu Microelectronics/Swift */
-
-/* Ross Module versions */
-#define ROSS_604_REV_CDE 0x0 /* revisions c, d, and e */
-#define ROSS_604_REV_F 0x1 /* revision f */
-#define ROSS_605 0xf /* revision a, a.1, and a.2 */
-#define ROSS_605_REV_B 0xe /* revision b */
-
-/* TI Viking Module versions */
-#define VIKING_REV_12 0x1 /* Version 1.2 or SPARCclassic's CPU */
-#define VIKING_REV_2 0x2 /* Version 2.1, 2.2, 2.3, and 2.4 */
-#define VIKING_REV_30 0x3 /* Version 3.0 */
-#define VIKING_REV_35 0x4 /* Version 3.5 */
-
-/* LSI Logics. */
-#define LSI_L64815 0x0
-
-/* Fujitsu */
-#define FMI_AURORA 0x4 /* MB8690x, a Swift module... */
-#define FMI_TURBO 0x5 /* MB86907, a TurboSparc module... */
-
-/* For multiprocessor support we need to be able to obtain the CPU id and
- * the MBUS Module id.
- */
-
-/* The CPU ID is encoded in the trap base register, 20 bits to the left of
- * bit zero, with 2 bits being significant.
- */
-#define TBR_ID_SHIFT 20
-
-static inline int get_cpuid(void)
-{
- register int retval;
- __asm__ __volatile__("rd %%tbr, %0\n\t"
- "srl %0, %1, %0\n\t" :
- "=r" (retval) :
- "i" (TBR_ID_SHIFT));
- return (retval & 3);
-}
-
-static inline int get_modid(void)
-{
- return (get_cpuid() | 0x8);
-}
-
-
-#endif /* !(_SPARC_MBUS_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_MC146818RTC_H
-#define ___ASM_SPARC_MC146818RTC_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/mc146818rtc_64.h>
-#else
-#include <asm-sparc/mc146818rtc_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * Machine dependent access functions for RTC registers.
- */
-#ifndef __ASM_SPARC_MC146818RTC_H
-#define __ASM_SPARC_MC146818RTC_H
-
-#include <asm/io.h>
-
-#ifndef RTC_PORT
-#define RTC_PORT(x) (0x70 + (x))
-#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
-#endif
-
-/*
- * The yet supported machines all access the RTC index register via
- * an ISA port access but the way to access the date register differs ...
- */
-#define CMOS_READ(addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-inb_p(RTC_PORT(1)); \
-})
-#define CMOS_WRITE(val, addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-outb_p((val),RTC_PORT(1)); \
-})
-
-#define RTC_IRQ 8
-
-#endif /* __ASM_SPARC_MC146818RTC_H */
+++ /dev/null
-/*
- * Machine dependent access functions for RTC registers.
- */
-#ifndef __ASM_SPARC64_MC146818RTC_H
-#define __ASM_SPARC64_MC146818RTC_H
-
-#include <asm/io.h>
-
-#ifndef RTC_PORT
-#ifdef CONFIG_PCI
-extern unsigned long ds1287_regs;
-#else
-#define ds1287_regs (0UL)
-#endif
-#define RTC_PORT(x) (ds1287_regs + (x))
-#define RTC_ALWAYS_BCD 0
-#endif
-
-/*
- * The yet supported machines all access the RTC index register via
- * an ISA port access but the way to access the date register differs ...
- */
-#define CMOS_READ(addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-inb_p(RTC_PORT(1)); \
-})
-#define CMOS_WRITE(val, addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-outb_p((val),RTC_PORT(1)); \
-})
-
-#define RTC_IRQ 8
-
-#endif /* __ASM_SPARC64_MC146818RTC_H */
+++ /dev/null
-#ifndef _SPARC64_MDESC_H
-#define _SPARC64_MDESC_H
-
-#include <linux/types.h>
-#include <linux/cpumask.h>
-#include <asm/prom.h>
-
-struct mdesc_handle;
-
-/* Machine description operations are to be surrounded by grab and
- * release calls. The mdesc_handle returned from the grab is
- * the first argument to all of the operational calls that work
- * on mdescs.
- */
-extern struct mdesc_handle *mdesc_grab(void);
-extern void mdesc_release(struct mdesc_handle *);
-
-#define MDESC_NODE_NULL (~(u64)0)
-
-extern u64 mdesc_node_by_name(struct mdesc_handle *handle,
- u64 from_node, const char *name);
-#define mdesc_for_each_node_by_name(__hdl, __node, __name) \
- for (__node = mdesc_node_by_name(__hdl, MDESC_NODE_NULL, __name); \
- (__node) != MDESC_NODE_NULL; \
- __node = mdesc_node_by_name(__hdl, __node, __name))
-
-/* Access to property values returned from mdesc_get_property() are
- * only valid inside of a mdesc_grab()/mdesc_release() sequence.
- * Once mdesc_release() is called, the memory backed up by these
- * pointers may reference freed up memory.
- *
- * Therefore callers must make copies of any property values
- * they need.
- *
- * These same rules apply to mdesc_node_name().
- */
-extern const void *mdesc_get_property(struct mdesc_handle *handle,
- u64 node, const char *name, int *lenp);
-extern const char *mdesc_node_name(struct mdesc_handle *hp, u64 node);
-
-/* MD arc iteration, the standard sequence is:
- *
- * unsigned long arc;
- * mdesc_for_each_arc(arc, handle, node, MDESC_ARC_TYPE_{FWD,BACK}) {
- * unsigned long target = mdesc_arc_target(handle, arc);
- * ...
- * }
- */
-
-#define MDESC_ARC_TYPE_FWD "fwd"
-#define MDESC_ARC_TYPE_BACK "back"
-
-extern u64 mdesc_next_arc(struct mdesc_handle *handle, u64 from,
- const char *arc_type);
-#define mdesc_for_each_arc(__arc, __hdl, __node, __type) \
- for (__arc = mdesc_next_arc(__hdl, __node, __type); \
- (__arc) != MDESC_NODE_NULL; \
- __arc = mdesc_next_arc(__hdl, __arc, __type))
-
-extern u64 mdesc_arc_target(struct mdesc_handle *hp, u64 arc);
-
-extern void mdesc_update(void);
-
-struct mdesc_notifier_client {
- void (*add)(struct mdesc_handle *handle, u64 node);
- void (*remove)(struct mdesc_handle *handle, u64 node);
-
- const char *node_name;
- struct mdesc_notifier_client *next;
-};
-
-extern void mdesc_register_notifier(struct mdesc_notifier_client *client);
-
-extern void mdesc_fill_in_cpu_data(cpumask_t mask);
-
-extern void sun4v_mdesc_init(void);
-
-#endif
+++ /dev/null
-#ifndef _SPARC_MEMREG_H
-#define _SPARC_MEMREG_H
-/* memreg.h: Definitions of the values found in the synchronous
- * and asynchronous memory error registers when a fault
- * occurs on the sun4c.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-/* First the synchronous error codes, these are usually just
- * normal page faults.
- */
-
-#define SUN4C_SYNC_WDRESET 0x0001 /* watchdog reset */
-#define SUN4C_SYNC_SIZE 0x0002 /* bad access size? whuz this? */
-#define SUN4C_SYNC_PARITY 0x0008 /* bad ram chips caused a parity error */
-#define SUN4C_SYNC_SBUS 0x0010 /* the SBUS had some problems... */
-#define SUN4C_SYNC_NOMEM 0x0020 /* translation to non-existent ram */
-#define SUN4C_SYNC_PROT 0x0040 /* access violated pte protections */
-#define SUN4C_SYNC_NPRESENT 0x0080 /* pte said that page was not present */
-#define SUN4C_SYNC_BADWRITE 0x8000 /* while writing something went bogus */
-
-#define SUN4C_SYNC_BOLIXED \
- (SUN4C_SYNC_WDRESET | SUN4C_SYNC_SIZE | SUN4C_SYNC_SBUS | \
- SUN4C_SYNC_NOMEM | SUN4C_SYNC_PARITY)
-
-/* Now the asynchronous error codes, these are almost always produced
- * by the cache writing things back to memory and getting a bad translation.
- * Bad DVMA transactions can cause these faults too.
- */
-
-#define SUN4C_ASYNC_BADDVMA 0x0010 /* error during DVMA access */
-#define SUN4C_ASYNC_NOMEM 0x0020 /* write back pointed to bad phys addr */
-#define SUN4C_ASYNC_BADWB 0x0080 /* write back points to non-present page */
-
-/* Memory parity error register with associated bit constants. */
-#ifndef __ASSEMBLY__
-extern __volatile__ unsigned long __iomem *sun4c_memerr_reg;
-#endif
-
-#define SUN4C_MPE_ERROR 0x80 /* Parity error detected. (ro) */
-#define SUN4C_MPE_MULTI 0x40 /* Multiple parity errors detected. (ro) */
-#define SUN4C_MPE_TEST 0x20 /* Write inverse parity. (rw) */
-#define SUN4C_MPE_CHECK 0x10 /* Enable parity checking. (rw) */
-#define SUN4C_MPE_ERR00 0x08 /* Parity error in bits 0-7. (ro) */
-#define SUN4C_MPE_ERR08 0x04 /* Parity error in bits 8-15. (ro) */
-#define SUN4C_MPE_ERR16 0x02 /* Parity error in bits 16-23. (ro) */
-#define SUN4C_MPE_ERR24 0x01 /* Parity error in bits 24-31. (ro) */
-#define SUN4C_MPE_ERRS 0x0F /* Bit mask for the error bits. (ro) */
-
-#endif /* !(_SPARC_MEMREG_H) */
+++ /dev/null
-#ifndef __SPARC_MMAN_H__
-#define __SPARC_MMAN_H__
-
-#include <asm-generic/mman.h>
-
-/* SunOS'ified... */
-
-#define MAP_RENAME MAP_ANONYMOUS /* In SunOS terminology */
-#define MAP_NORESERVE 0x40 /* don't reserve swap pages */
-#define MAP_INHERIT 0x80 /* SunOS doesn't do this, but... */
-#define MAP_LOCKED 0x100 /* lock the mapping */
-#define _MAP_NEW 0x80000000 /* Binary compatibility is fun... */
-
-#define MAP_GROWSDOWN 0x0200 /* stack-like segment */
-#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
-#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
-
-#define MCL_CURRENT 0x2000 /* lock all currently mapped pages */
-#define MCL_FUTURE 0x4000 /* lock all additions to address space */
-
-#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
-#define MAP_NONBLOCK 0x10000 /* do not block on IO */
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-#define arch_mmap_check(addr,len,flags) sparc_mmap_check(addr,len)
-int sparc_mmap_check(unsigned long addr, unsigned long len);
-#endif
-#endif
-
-#endif /* __SPARC_MMAN_H__ */
+++ /dev/null
-#ifndef ___ASM_SPARC_MMU_H
-#define ___ASM_SPARC_MMU_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/mmu_64.h>
-#else
-#include <asm-sparc/mmu_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef __MMU_H
-#define __MMU_H
-
-/* Default "unsigned long" context */
-typedef unsigned long mm_context_t;
-
-#endif
+++ /dev/null
-#ifndef __MMU_H
-#define __MMU_H
-
-#include <linux/const.h>
-#include <asm/page.h>
-#include <asm/hypervisor.h>
-
-#define CTX_NR_BITS 13
-
-#define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
-
-/* UltraSPARC-III+ and later have a feature whereby you can
- * select what page size the various Data-TLB instances in the
- * chip. In order to gracefully support this, we put the version
- * field in a spot outside of the areas of the context register
- * where this parameter is specified.
- */
-#define CTX_VERSION_SHIFT 22
-#define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT)
-
-#define CTX_PGSZ_8KB _AC(0x0,UL)
-#define CTX_PGSZ_64KB _AC(0x1,UL)
-#define CTX_PGSZ_512KB _AC(0x2,UL)
-#define CTX_PGSZ_4MB _AC(0x3,UL)
-#define CTX_PGSZ_BITS _AC(0x7,UL)
-#define CTX_PGSZ0_NUC_SHIFT 61
-#define CTX_PGSZ1_NUC_SHIFT 58
-#define CTX_PGSZ0_SHIFT 16
-#define CTX_PGSZ1_SHIFT 19
-#define CTX_PGSZ_MASK ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \
- (CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))
-
-#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
-#define CTX_PGSZ_BASE CTX_PGSZ_8KB
-#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
-#define CTX_PGSZ_BASE CTX_PGSZ_64KB
-#else
-#error No page size specified in kernel configuration
-#endif
-
-#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
-#define CTX_PGSZ_HUGE CTX_PGSZ_4MB
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
-#define CTX_PGSZ_HUGE CTX_PGSZ_512KB
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
-#define CTX_PGSZ_HUGE CTX_PGSZ_64KB
-#endif
-
-#define CTX_PGSZ_KERN CTX_PGSZ_4MB
-
-/* Thus, when running on UltraSPARC-III+ and later, we use the following
- * PRIMARY_CONTEXT register values for the kernel context.
- */
-#define CTX_CHEETAH_PLUS_NUC \
- ((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \
- (CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT))
-
-#define CTX_CHEETAH_PLUS_CTX0 \
- ((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \
- (CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT))
-
-/* If you want "the TLB context number" use CTX_NR_MASK. If you
- * want "the bits I program into the context registers" use
- * CTX_HW_MASK.
- */
-#define CTX_NR_MASK TAG_CONTEXT_BITS
-#define CTX_HW_MASK (CTX_NR_MASK | CTX_PGSZ_MASK)
-
-#define CTX_FIRST_VERSION ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL))
-#define CTX_VALID(__ctx) \
- (!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
-#define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
-#define CTX_NRBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_NR_MASK)
-
-#ifndef __ASSEMBLY__
-
-#define TSB_ENTRY_ALIGNMENT 16
-
-struct tsb {
- unsigned long tag;
- unsigned long pte;
-} __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));
-
-extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte);
-extern void tsb_flush(unsigned long ent, unsigned long tag);
-extern void tsb_init(struct tsb *tsb, unsigned long size);
-
-struct tsb_config {
- struct tsb *tsb;
- unsigned long tsb_rss_limit;
- unsigned long tsb_nentries;
- unsigned long tsb_reg_val;
- unsigned long tsb_map_vaddr;
- unsigned long tsb_map_pte;
-};
-
-#define MM_TSB_BASE 0
-
-#ifdef CONFIG_HUGETLB_PAGE
-#define MM_TSB_HUGE 1
-#define MM_NUM_TSBS 2
-#else
-#define MM_NUM_TSBS 1
-#endif
-
-typedef struct {
- spinlock_t lock;
- unsigned long sparc64_ctx_val;
- unsigned long huge_pte_count;
- struct tsb_config tsb_block[MM_NUM_TSBS];
- struct hv_tsb_descr tsb_descr[MM_NUM_TSBS];
-} mm_context_t;
-
-#endif /* !__ASSEMBLY__ */
-
-#define TSB_CONFIG_TSB 0x00
-#define TSB_CONFIG_RSS_LIMIT 0x08
-#define TSB_CONFIG_NENTRIES 0x10
-#define TSB_CONFIG_REG_VAL 0x18
-#define TSB_CONFIG_MAP_VADDR 0x20
-#define TSB_CONFIG_MAP_PTE 0x28
-
-#endif /* __MMU_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_MMU_CONTEXT_H
-#define ___ASM_SPARC_MMU_CONTEXT_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/mmu_context_64.h>
-#else
-#include <asm-sparc/mmu_context_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef __SPARC_MMU_CONTEXT_H
-#define __SPARC_MMU_CONTEXT_H
-
-#include <asm/btfixup.h>
-
-#ifndef __ASSEMBLY__
-
-#include <asm-generic/mm_hooks.h>
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-/*
- * Initialize a new mmu context. This is invoked when a new
- * address space instance (unique or shared) is instantiated.
- */
-#define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0)
-
-/*
- * Destroy a dead context. This occurs when mmput drops the
- * mm_users count to zero, the mmaps have been released, and
- * all the page tables have been flushed. Our job is to destroy
- * any remaining processor-specific state.
- */
-BTFIXUPDEF_CALL(void, destroy_context, struct mm_struct *)
-
-#define destroy_context(mm) BTFIXUP_CALL(destroy_context)(mm)
-
-/* Switch the current MM context. */
-BTFIXUPDEF_CALL(void, switch_mm, struct mm_struct *, struct mm_struct *, struct task_struct *)
-
-#define switch_mm(old_mm, mm, tsk) BTFIXUP_CALL(switch_mm)(old_mm, mm, tsk)
-
-#define deactivate_mm(tsk,mm) do { } while (0)
-
-/* Activate a new MM instance for the current task. */
-#define activate_mm(active_mm, mm) switch_mm((active_mm), (mm), NULL)
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(__SPARC_MMU_CONTEXT_H) */
+++ /dev/null
-#ifndef __SPARC64_MMU_CONTEXT_H
-#define __SPARC64_MMU_CONTEXT_H
-
-/* Derived heavily from Linus's Alpha/AXP ASN code... */
-
-#ifndef __ASSEMBLY__
-
-#include <linux/spinlock.h>
-#include <asm/system.h>
-#include <asm/spitfire.h>
-#include <asm-generic/mm_hooks.h>
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-extern spinlock_t ctx_alloc_lock;
-extern unsigned long tlb_context_cache;
-extern unsigned long mmu_context_bmap[];
-
-extern void get_new_mmu_context(struct mm_struct *mm);
-#ifdef CONFIG_SMP
-extern void smp_new_mmu_context_version(void);
-#else
-#define smp_new_mmu_context_version() do { } while (0)
-#endif
-
-extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
-extern void destroy_context(struct mm_struct *mm);
-
-extern void __tsb_context_switch(unsigned long pgd_pa,
- struct tsb_config *tsb_base,
- struct tsb_config *tsb_huge,
- unsigned long tsb_descr_pa);
-
-static inline void tsb_context_switch(struct mm_struct *mm)
-{
- __tsb_context_switch(__pa(mm->pgd),
- &mm->context.tsb_block[0],
-#ifdef CONFIG_HUGETLB_PAGE
- (mm->context.tsb_block[1].tsb ?
- &mm->context.tsb_block[1] :
- NULL)
-#else
- NULL
-#endif
- , __pa(&mm->context.tsb_descr[0]));
-}
-
-extern void tsb_grow(struct mm_struct *mm, unsigned long tsb_index, unsigned long mm_rss);
-#ifdef CONFIG_SMP
-extern void smp_tsb_sync(struct mm_struct *mm);
-#else
-#define smp_tsb_sync(__mm) do { } while (0)
-#endif
-
-/* Set MMU context in the actual hardware. */
-#define load_secondary_context(__mm) \
- __asm__ __volatile__( \
- "\n661: stxa %0, [%1] %2\n" \
- " .section .sun4v_1insn_patch, \"ax\"\n" \
- " .word 661b\n" \
- " stxa %0, [%1] %3\n" \
- " .previous\n" \
- " flush %%g6\n" \
- : /* No outputs */ \
- : "r" (CTX_HWBITS((__mm)->context)), \
- "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
-
-extern void __flush_tlb_mm(unsigned long, unsigned long);
-
-/* Switch the current MM context. Interrupts are disabled. */
-static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
-{
- unsigned long ctx_valid, flags;
- int cpu;
-
- if (unlikely(mm == &init_mm))
- return;
-
- spin_lock_irqsave(&mm->context.lock, flags);
- ctx_valid = CTX_VALID(mm->context);
- if (!ctx_valid)
- get_new_mmu_context(mm);
-
- /* We have to be extremely careful here or else we will miss
- * a TSB grow if we switch back and forth between a kernel
- * thread and an address space which has it's TSB size increased
- * on another processor.
- *
- * It is possible to play some games in order to optimize the
- * switch, but the safest thing to do is to unconditionally
- * perform the secondary context load and the TSB context switch.
- *
- * For reference the bad case is, for address space "A":
- *
- * CPU 0 CPU 1
- * run address space A
- * set cpu0's bits in cpu_vm_mask
- * switch to kernel thread, borrow
- * address space A via entry_lazy_tlb
- * run address space A
- * set cpu1's bit in cpu_vm_mask
- * flush_tlb_pending()
- * reset cpu_vm_mask to just cpu1
- * TSB grow
- * run address space A
- * context was valid, so skip
- * TSB context switch
- *
- * At that point cpu0 continues to use a stale TSB, the one from
- * before the TSB grow performed on cpu1. cpu1 did not cross-call
- * cpu0 to update it's TSB because at that point the cpu_vm_mask
- * only had cpu1 set in it.
- */
- load_secondary_context(mm);
- tsb_context_switch(mm);
-
- /* Any time a processor runs a context on an address space
- * for the first time, we must flush that context out of the
- * local TLB.
- */
- cpu = smp_processor_id();
- if (!ctx_valid || !cpu_isset(cpu, mm->cpu_vm_mask)) {
- cpu_set(cpu, mm->cpu_vm_mask);
- __flush_tlb_mm(CTX_HWBITS(mm->context),
- SECONDARY_CONTEXT);
- }
- spin_unlock_irqrestore(&mm->context.lock, flags);
-}
-
-#define deactivate_mm(tsk,mm) do { } while (0)
-
-/* Activate a new MM instance for the current task. */
-static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)
-{
- unsigned long flags;
- int cpu;
-
- spin_lock_irqsave(&mm->context.lock, flags);
- if (!CTX_VALID(mm->context))
- get_new_mmu_context(mm);
- cpu = smp_processor_id();
- if (!cpu_isset(cpu, mm->cpu_vm_mask))
- cpu_set(cpu, mm->cpu_vm_mask);
-
- load_secondary_context(mm);
- __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);
- tsb_context_switch(mm);
- spin_unlock_irqrestore(&mm->context.lock, flags);
-}
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(__SPARC64_MMU_CONTEXT_H) */
+++ /dev/null
-#ifndef _SPARC64_MMZONE_H
-#define _SPARC64_MMZONE_H
-
-#ifdef CONFIG_NEED_MULTIPLE_NODES
-
-extern struct pglist_data *node_data[];
-
-#define NODE_DATA(nid) (node_data[nid])
-#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
-#define node_end_pfn(nid) (NODE_DATA(nid)->node_end_pfn)
-
-extern int numa_cpu_lookup_table[];
-extern cpumask_t numa_cpumask_lookup_table[];
-
-#endif /* CONFIG_NEED_MULTIPLE_NODES */
-
-#endif /* _SPARC64_MMZONE_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_MODULE_H
-#define ___ASM_SPARC_MODULE_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/module_64.h>
-#else
-#include <asm-sparc/module_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _ASM_SPARC_MODULE_H
-#define _ASM_SPARC_MODULE_H
-struct mod_arch_specific { };
-#define Elf_Shdr Elf32_Shdr
-#define Elf_Sym Elf32_Sym
-#define Elf_Ehdr Elf32_Ehdr
-#endif /* _ASM_SPARC_MODULE_H */
+++ /dev/null
-#ifndef _ASM_SPARC64_MODULE_H
-#define _ASM_SPARC64_MODULE_H
-struct mod_arch_specific { };
-#define Elf_Shdr Elf64_Shdr
-#define Elf_Sym Elf64_Sym
-#define Elf_Ehdr Elf64_Ehdr
-#endif /* _ASM_SPARC64_MODULE_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_MOSTEK_H
-#define ___ASM_SPARC_MOSTEK_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/mostek_64.h>
-#else
-#include <asm-sparc/mostek_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * mostek.h: Describes the various Mostek time of day clock registers.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
- * Added intersil code 05/25/98 Chris Davis (cdavis@cois.on.ca)
- */
-
-#ifndef _SPARC_MOSTEK_H
-#define _SPARC_MOSTEK_H
-
-#include <asm/idprom.h>
-#include <asm/io.h>
-
-/* M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
- *
- * Data
- * Address Function
- * Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
- * 7ff - - - - - - - - Year 00-99
- * 7fe 0 0 0 - - - - - Month 01-12
- * 7fd 0 0 - - - - - - Date 01-31
- * 7fc 0 FT 0 0 0 - - - Day 01-07
- * 7fb KS 0 - - - - - - Hours 00-23
- * 7fa 0 - - - - - - - Minutes 00-59
- * 7f9 ST - - - - - - - Seconds 00-59
- * 7f8 W R S - - - - - Control
- *
- * * ST is STOP BIT
- * * W is WRITE BIT
- * * R is READ BIT
- * * S is SIGN BIT
- * * FT is FREQ TEST BIT
- * * KS is KICK START BIT
- */
-
-/* The Mostek 48t02 real time clock and NVRAM chip. The registers
- * other than the control register are in binary coded decimal. Some
- * control bits also live outside the control register.
- */
-#define mostek_read(_addr) readb(_addr)
-#define mostek_write(_addr,_val) writeb(_val, _addr)
-#define MOSTEK_EEPROM 0x0000UL
-#define MOSTEK_IDPROM 0x07d8UL
-#define MOSTEK_CREG 0x07f8UL
-#define MOSTEK_SEC 0x07f9UL
-#define MOSTEK_MIN 0x07faUL
-#define MOSTEK_HOUR 0x07fbUL
-#define MOSTEK_DOW 0x07fcUL
-#define MOSTEK_DOM 0x07fdUL
-#define MOSTEK_MONTH 0x07feUL
-#define MOSTEK_YEAR 0x07ffUL
-
-struct mostek48t02 {
- volatile char eeprom[2008]; /* This is the eeprom, don't touch! */
- struct idprom idprom; /* The idprom lives here. */
- volatile unsigned char creg; /* Control register */
- volatile unsigned char sec; /* Seconds (0-59) */
- volatile unsigned char min; /* Minutes (0-59) */
- volatile unsigned char hour; /* Hour (0-23) */
- volatile unsigned char dow; /* Day of the week (1-7) */
- volatile unsigned char dom; /* Day of the month (1-31) */
- volatile unsigned char month; /* Month of year (1-12) */
- volatile unsigned char year; /* Year (0-99) */
-};
-
-extern spinlock_t mostek_lock;
-extern void __iomem *mstk48t02_regs;
-
-/* Control register values. */
-#define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */
-#define MSTK_CREG_READ 0x40 /* Stop updates to allow a clean read. */
-#define MSTK_CREG_SIGN 0x20 /* Slow/speed clock in calibration mode. */
-
-/* Control bits that live in the other registers. */
-#define MSTK_STOP 0x80 /* Stop the clock oscillator. (sec) */
-#define MSTK_KICK_START 0x80 /* Kick start the clock chip. (hour) */
-#define MSTK_FREQ_TEST 0x40 /* Frequency test mode. (day) */
-
-#define MSTK_YEAR_ZERO 1968 /* If year reg has zero, it is 1968. */
-#define MSTK_CVT_YEAR(yr) ((yr) + MSTK_YEAR_ZERO)
-
-/* Masks that define how much space each value takes up. */
-#define MSTK_SEC_MASK 0x7f
-#define MSTK_MIN_MASK 0x7f
-#define MSTK_HOUR_MASK 0x3f
-#define MSTK_DOW_MASK 0x07
-#define MSTK_DOM_MASK 0x3f
-#define MSTK_MONTH_MASK 0x1f
-#define MSTK_YEAR_MASK 0xffU
-
-/* Binary coded decimal conversion macros. */
-#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
-#define MSTK_DECIMAL_TO_REGVAL(x) ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
-
-/* Generic register set and get macros for internal use. */
-#define MSTK_GET(regs,var,mask) (MSTK_REGVAL_TO_DECIMAL(((struct mostek48t02 *)regs)->var & MSTK_ ## mask ## _MASK))
-#define MSTK_SET(regs,var,value,mask) do { ((struct mostek48t02 *)regs)->var &= ~(MSTK_ ## mask ## _MASK); ((struct mostek48t02 *)regs)->var |= MSTK_DECIMAL_TO_REGVAL(value) & (MSTK_ ## mask ## _MASK); } while (0)
-
-/* Macros to make register access easier on our fingers. These give you
- * the decimal value of the register requested if applicable. You pass
- * the a pointer to a 'struct mostek48t02'.
- */
-#define MSTK_REG_CREG(regs) (((struct mostek48t02 *)regs)->creg)
-#define MSTK_REG_SEC(regs) MSTK_GET(regs,sec,SEC)
-#define MSTK_REG_MIN(regs) MSTK_GET(regs,min,MIN)
-#define MSTK_REG_HOUR(regs) MSTK_GET(regs,hour,HOUR)
-#define MSTK_REG_DOW(regs) MSTK_GET(regs,dow,DOW)
-#define MSTK_REG_DOM(regs) MSTK_GET(regs,dom,DOM)
-#define MSTK_REG_MONTH(regs) MSTK_GET(regs,month,MONTH)
-#define MSTK_REG_YEAR(regs) MSTK_GET(regs,year,YEAR)
-
-#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,sec,value,SEC)
-#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,min,value,MIN)
-#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,hour,value,HOUR)
-#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,dow,value,DOW)
-#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,dom,value,DOM)
-#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,month,value,MONTH)
-#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,year,value,YEAR)
-
-
-/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
- * same (basically) layout of the 48t02 chip except for the extra
- * NVRAM on board (8 KB against the 48t02's 2 KB).
- */
-struct mostek48t08 {
- char offset[6*1024]; /* Magic things may be here, who knows? */
- struct mostek48t02 regs; /* Here is what we are interested in. */
-};
-
-#ifdef CONFIG_SUN4
-enum sparc_clock_type { MSTK48T02, MSTK48T08, \
-INTERSIL, MSTK_INVALID };
-#else
-enum sparc_clock_type { MSTK48T02, MSTK48T08, \
-MSTK_INVALID };
-#endif
-
-#ifdef CONFIG_SUN4
-/* intersil on a sun 4/260 code data from harris doc */
-struct intersil_dt {
- volatile unsigned char int_csec;
- volatile unsigned char int_hour;
- volatile unsigned char int_min;
- volatile unsigned char int_sec;
- volatile unsigned char int_month;
- volatile unsigned char int_day;
- volatile unsigned char int_year;
- volatile unsigned char int_dow;
-};
-
-struct intersil {
- struct intersil_dt clk;
- struct intersil_dt cmp;
- volatile unsigned char int_intr_reg;
- volatile unsigned char int_cmd_reg;
-};
-
-#define INTERSIL_STOP 0x0
-#define INTERSIL_START 0x8
-#define INTERSIL_INTR_DISABLE 0x0
-#define INTERSIL_INTR_ENABLE 0x10
-#define INTERSIL_32K 0x0
-#define INTERSIL_NORMAL 0x0
-#define INTERSIL_24H 0x4
-#define INTERSIL_INT_100HZ 0x2
-
-/* end of intersil info */
-#endif
-
-#endif /* !(_SPARC_MOSTEK_H) */
+++ /dev/null
-/* mostek.h: Describes the various Mostek time of day clock registers.
- *
- * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
- * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
- */
-
-#ifndef _SPARC64_MOSTEK_H
-#define _SPARC64_MOSTEK_H
-
-#include <asm/idprom.h>
-
-/* M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
- *
- * Data
- * Address Function
- * Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
- * 7ff - - - - - - - - Year 00-99
- * 7fe 0 0 0 - - - - - Month 01-12
- * 7fd 0 0 - - - - - - Date 01-31
- * 7fc 0 FT 0 0 0 - - - Day 01-07
- * 7fb KS 0 - - - - - - Hours 00-23
- * 7fa 0 - - - - - - - Minutes 00-59
- * 7f9 ST - - - - - - - Seconds 00-59
- * 7f8 W R S - - - - - Control
- *
- * * ST is STOP BIT
- * * W is WRITE BIT
- * * R is READ BIT
- * * S is SIGN BIT
- * * FT is FREQ TEST BIT
- * * KS is KICK START BIT
- */
-
-/* The Mostek 48t02 real time clock and NVRAM chip. The registers
- * other than the control register are in binary coded decimal. Some
- * control bits also live outside the control register.
- *
- * We now deal with physical addresses for I/O to the chip. -DaveM
- */
-static inline u8 mostek_read(void __iomem *addr)
-{
- u8 ret;
-
- __asm__ __volatile__("lduba [%1] %2, %0"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
- return ret;
-}
-
-static inline void mostek_write(void __iomem *addr, u8 val)
-{
- __asm__ __volatile__("stba %0, [%1] %2"
- : /* no outputs */
- : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-}
-
-#define MOSTEK_EEPROM 0x0000UL
-#define MOSTEK_IDPROM 0x07d8UL
-#define MOSTEK_CREG 0x07f8UL
-#define MOSTEK_SEC 0x07f9UL
-#define MOSTEK_MIN 0x07faUL
-#define MOSTEK_HOUR 0x07fbUL
-#define MOSTEK_DOW 0x07fcUL
-#define MOSTEK_DOM 0x07fdUL
-#define MOSTEK_MONTH 0x07feUL
-#define MOSTEK_YEAR 0x07ffUL
-
-extern spinlock_t mostek_lock;
-extern void __iomem *mstk48t02_regs;
-
-/* Control register values. */
-#define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */
-#define MSTK_CREG_READ 0x40 /* Stop updates to allow a clean read. */
-#define MSTK_CREG_SIGN 0x20 /* Slow/speed clock in calibration mode. */
-
-/* Control bits that live in the other registers. */
-#define MSTK_STOP 0x80 /* Stop the clock oscillator. (sec) */
-#define MSTK_KICK_START 0x80 /* Kick start the clock chip. (hour) */
-#define MSTK_FREQ_TEST 0x40 /* Frequency test mode. (day) */
-
-#define MSTK_YEAR_ZERO 1968 /* If year reg has zero, it is 1968. */
-#define MSTK_CVT_YEAR(yr) ((yr) + MSTK_YEAR_ZERO)
-
-/* Masks that define how much space each value takes up. */
-#define MSTK_SEC_MASK 0x7f
-#define MSTK_MIN_MASK 0x7f
-#define MSTK_HOUR_MASK 0x3f
-#define MSTK_DOW_MASK 0x07
-#define MSTK_DOM_MASK 0x3f
-#define MSTK_MONTH_MASK 0x1f
-#define MSTK_YEAR_MASK 0xffU
-
-/* Binary coded decimal conversion macros. */
-#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
-#define MSTK_DECIMAL_TO_REGVAL(x) ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
-
-/* Generic register set and get macros for internal use. */
-#define MSTK_GET(regs,name) \
- (MSTK_REGVAL_TO_DECIMAL(mostek_read(regs + MOSTEK_ ## name) & MSTK_ ## name ## _MASK))
-#define MSTK_SET(regs,name,value) \
-do { u8 __val = mostek_read(regs + MOSTEK_ ## name); \
- __val &= ~(MSTK_ ## name ## _MASK); \
- __val |= (MSTK_DECIMAL_TO_REGVAL(value) & \
- (MSTK_ ## name ## _MASK)); \
- mostek_write(regs + MOSTEK_ ## name, __val); \
-} while(0)
-
-/* Macros to make register access easier on our fingers. These give you
- * the decimal value of the register requested if applicable. You pass
- * the a pointer to a 'struct mostek48t02'.
- */
-#define MSTK_REG_CREG(regs) (mostek_read((regs) + MOSTEK_CREG))
-#define MSTK_REG_SEC(regs) MSTK_GET(regs,SEC)
-#define MSTK_REG_MIN(regs) MSTK_GET(regs,MIN)
-#define MSTK_REG_HOUR(regs) MSTK_GET(regs,HOUR)
-#define MSTK_REG_DOW(regs) MSTK_GET(regs,DOW)
-#define MSTK_REG_DOM(regs) MSTK_GET(regs,DOM)
-#define MSTK_REG_MONTH(regs) MSTK_GET(regs,MONTH)
-#define MSTK_REG_YEAR(regs) MSTK_GET(regs,YEAR)
-
-#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,SEC,value)
-#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,MIN,value)
-#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,HOUR,value)
-#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,DOW,value)
-#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,DOM,value)
-#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,MONTH,value)
-#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,YEAR,value)
-
-
-/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
- * same (basically) layout of the 48t02 chip except for the extra
- * NVRAM on board (8 KB against the 48t02's 2 KB).
- */
-#define MOSTEK_48T08_OFFSET 0x0000UL /* Lower NVRAM portions */
-#define MOSTEK_48T08_48T02 0x1800UL /* Offset to 48T02 chip */
-
-/* SUN5 systems usually have 48t59 model clock chipsets. But we keep the older
- * clock chip definitions around just in case.
- */
-#define MOSTEK_48T59_OFFSET 0x0000UL /* Lower NVRAM portions */
-#define MOSTEK_48T59_48T02 0x1800UL /* Offset to 48T02 chip */
-
-#endif /* !(_SPARC64_MOSTEK_H) */
+++ /dev/null
-/*
- * mpmbox.h: Interface and defines for the OpenProm mailbox
- * facilities for MP machines under Linux.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_MPMBOX_H
-#define _SPARC_MPMBOX_H
-
-/* The prom allocates, for each CPU on the machine an unsigned
- * byte in physical ram. You probe the device tree prom nodes
- * for these values. The purpose of this byte is to be able to
- * pass messages from one cpu to another.
- */
-
-/* These are the main message types we have to look for in our
- * Cpu mailboxes, based upon these values we decide what course
- * of action to take.
- */
-
-/* The CPU is executing code in the kernel. */
-#define MAILBOX_ISRUNNING 0xf0
-
-/* Another CPU called romvec->pv_exit(), you should call
- * prom_stopcpu() when you see this in your mailbox.
- */
-#define MAILBOX_EXIT 0xfb
-
-/* Another CPU called romvec->pv_enter(), you should call
- * prom_cpuidle() when this is seen.
- */
-#define MAILBOX_GOSPIN 0xfc
-
-/* Another CPU has hit a breakpoint either into kadb or the prom
- * itself. Just like MAILBOX_GOSPIN, you should call prom_cpuidle()
- * at this point.
- */
-#define MAILBOX_BPT_SPIN 0xfd
-
-/* Oh geese, some other nitwit got a damn watchdog reset. The party's
- * over so go call prom_stopcpu().
- */
-#define MAILBOX_WDOG_STOP 0xfe
-
-#ifndef __ASSEMBLY__
-
-/* Handy macro's to determine a cpu's state. */
-
-/* Is the cpu still in Power On Self Test? */
-#define MBOX_POST_P(letter) ((letter) >= 0x00 && (letter) <= 0x7f)
-
-/* Is the cpu at the 'ok' prompt of the PROM? */
-#define MBOX_PROMPROMPT_P(letter) ((letter) >= 0x80 && (letter) <= 0x8f)
-
-/* Is the cpu spinning in the PROM? */
-#define MBOX_PROMSPIN_P(letter) ((letter) >= 0x90 && (letter) <= 0xef)
-
-/* Sanity check... This is junk mail, throw it out. */
-#define MBOX_BOGON_P(letter) ((letter) >= 0xf1 && (letter) <= 0xfa)
-
-/* Is the cpu actively running an application/kernel-code? */
-#define MBOX_RUNNING_P(letter) ((letter) == MAILBOX_ISRUNNING)
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(_SPARC_MPMBOX_H) */
+++ /dev/null
-#ifndef _SPARC_MSGBUF_H
-#define _SPARC_MSGBUF_H
-
-/*
- * The msqid64_ds structure for sparc64 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-#if defined(__sparc__) && defined(__arch64__)
-# define PADDING(x)
-#else
-# define PADDING(x) unsigned int x;
-#endif
-
-
-struct msqid64_ds {
- struct ipc64_perm msg_perm;
- PADDING(__pad1)
- __kernel_time_t msg_stime; /* last msgsnd time */
- PADDING(__pad2)
- __kernel_time_t msg_rtime; /* last msgrcv time */
- PADDING(__pad3)
- __kernel_time_t msg_ctime; /* last change time */
- unsigned long msg_cbytes; /* current number of bytes on queue */
- unsigned long msg_qnum; /* number of messages in queue */
- unsigned long msg_qbytes; /* max number of bytes on queue */
- __kernel_pid_t msg_lspid; /* pid of last msgsnd */
- __kernel_pid_t msg_lrpid; /* last receive pid */
- unsigned long __unused1;
- unsigned long __unused2;
-};
-#undef PADDING
-#endif /* _SPARC_MSGBUF_H */
+++ /dev/null
-/*
- * msi.h: Defines specific to the MBus - Sbus - Interface.
- *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
- */
-
-#ifndef _SPARC_MSI_H
-#define _SPARC_MSI_H
-
-/*
- * Locations of MSI Registers.
- */
-#define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
-
-/*
- * Useful bits in the MSI Registers.
- */
-#define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
-
-
-static inline void msi_set_sync(void)
-{
- __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
- "andn %%g3, %2, %%g3\n\t"
- "sta %%g3, [%0] %1\n\t" : :
- "r" (MSI_MBUS_ARBEN),
- "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
-}
-
-#endif /* !(_SPARC_MSI_H) */
+++ /dev/null
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- */
-
-#include <asm-generic/mutex-dec.h>
+++ /dev/null
-/*
- * mxcc.h: Definitions of the Viking MXCC registers
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_MXCC_H
-#define _SPARC_MXCC_H
-
-/* These registers are accessed through ASI 0x2. */
-#define MXCC_DATSTREAM 0x1C00000 /* Data stream register */
-#define MXCC_SRCSTREAM 0x1C00100 /* Source stream register */
-#define MXCC_DESSTREAM 0x1C00200 /* Destination stream register */
-#define MXCC_RMCOUNT 0x1C00300 /* Count of references and misses */
-#define MXCC_STEST 0x1C00804 /* Internal self-test */
-#define MXCC_CREG 0x1C00A04 /* Control register */
-#define MXCC_SREG 0x1C00B00 /* Status register */
-#define MXCC_RREG 0x1C00C04 /* Reset register */
-#define MXCC_EREG 0x1C00E00 /* Error code register */
-#define MXCC_PREG 0x1C00F04 /* Address port register */
-
-/* Some MXCC constants. */
-#define MXCC_STREAM_SIZE 0x20 /* Size in bytes of one stream r/w */
-
-/* The MXCC Control Register:
- *
- * ----------------------------------------------------------------------
- * | | RRC | RSV |PRE|MCE|PARE|ECE|RSV|
- * ----------------------------------------------------------------------
- * 31 10 9 8-6 5 4 3 2 1-0
- *
- * RRC: Controls what you read from MXCC_RMCOUNT reg.
- * 0=Misses 1=References
- * PRE: Prefetch enable
- * MCE: Multiple Command Enable
- * PARE: Parity enable
- * ECE: External cache enable
- */
-
-#define MXCC_CTL_RRC 0x00000200
-#define MXCC_CTL_PRE 0x00000020
-#define MXCC_CTL_MCE 0x00000010
-#define MXCC_CTL_PARE 0x00000008
-#define MXCC_CTL_ECE 0x00000004
-
-/* The MXCC Error Register:
- *
- * --------------------------------------------------------
- * |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR|
- * --------------------------------------------------------
- * 31 30 29 28 27 26 25 24-15 14-7 6 5-3 2-0
- *
- * ME: Multiple Errors have occurred
- * CE: Cache consistency Error
- * PEW: Parity Error during a Write operation
- * PEE: Parity Error involving the External cache
- * ASE: ASynchronous Error
- * EIV: This register is toast
- * MOPC: MXCC Operation Code for instance causing error
- * ECODE: The Error CODE
- * PRIV: A privileged mode error? 0=no 1=yes
- * HPADDR: High PhysicalADDRess bits (35-32)
- */
-
-#define MXCC_ERR_ME 0x80000000
-#define MXCC_ERR_CE 0x20000000
-#define MXCC_ERR_PEW 0x10000000
-#define MXCC_ERR_PEE 0x08000000
-#define MXCC_ERR_ASE 0x04000000
-#define MXCC_ERR_EIV 0x02000000
-#define MXCC_ERR_MOPC 0x01FF8000
-#define MXCC_ERR_ECODE 0x00007F80
-#define MXCC_ERR_PRIV 0x00000040
-#define MXCC_ERR_HPADDR 0x0000000f
-
-/* The MXCC Port register:
- *
- * -----------------------------------------------------
- * | | MID | |
- * -----------------------------------------------------
- * 31 21 20-18 17 0
- *
- * MID: The moduleID of the cpu your read this from.
- */
-
-#ifndef __ASSEMBLY__
-
-static inline void mxcc_set_stream_src(unsigned long *paddr)
-{
- unsigned long data0 = paddr[0];
- unsigned long data1 = paddr[1];
-
- __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
- "or %%g0, %1, %%g3\n\t"
- "stda %%g2, [%2] %3\n\t" : :
- "r" (data0), "r" (data1),
- "r" (MXCC_SRCSTREAM),
- "i" (ASI_M_MXCC) : "g2", "g3");
-}
-
-static inline void mxcc_set_stream_dst(unsigned long *paddr)
-{
- unsigned long data0 = paddr[0];
- unsigned long data1 = paddr[1];
-
- __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
- "or %%g0, %1, %%g3\n\t"
- "stda %%g2, [%2] %3\n\t" : :
- "r" (data0), "r" (data1),
- "r" (MXCC_DESSTREAM),
- "i" (ASI_M_MXCC) : "g2", "g3");
-}
-
-static inline unsigned long mxcc_get_creg(void)
-{
- unsigned long mxcc_control;
-
- __asm__ __volatile__("set 0xffffffff, %%g2\n\t"
- "set 0xffffffff, %%g3\n\t"
- "stda %%g2, [%1] %2\n\t"
- "lda [%3] %2, %0\n\t" :
- "=r" (mxcc_control) :
- "r" (MXCC_EREG), "i" (ASI_M_MXCC),
- "r" (MXCC_CREG) : "g2", "g3");
- return mxcc_control;
-}
-
-static inline void mxcc_set_creg(unsigned long mxcc_control)
-{
- __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
- "r" (mxcc_control), "r" (MXCC_CREG),
- "i" (ASI_M_MXCC));
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* !(_SPARC_MXCC_H) */
+++ /dev/null
-/* ns87303.h: Configuration Register Description for the
- * National Semiconductor PC87303 (SuperIO).
- *
- * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
- */
-
-#ifndef _SPARC_NS87303_H
-#define _SPARC_NS87303_H 1
-
-/*
- * Control Register Index Values
- */
-#define FER 0x00
-#define FAR 0x01
-#define PTR 0x02
-#define FCR 0x03
-#define PCR 0x04
-#define KRR 0x05
-#define PMC 0x06
-#define TUP 0x07
-#define SID 0x08
-#define ASC 0x09
-#define CS0CF0 0x0a
-#define CS0CF1 0x0b
-#define CS1CF0 0x0c
-#define CS1CF1 0x0d
-
-/* Function Enable Register (FER) bits */
-#define FER_EDM 0x10 /* Encoded Drive and Motor pin information */
-
-/* Function Address Register (FAR) bits */
-#define FAR_LPT_MASK 0x03
-#define FAR_LPTB 0x00
-#define FAR_LPTA 0x01
-#define FAR_LPTC 0x02
-
-/* Power and Test Register (PTR) bits */
-#define PTR_LPTB_IRQ7 0x08
-#define PTR_LEVEL_IRQ 0x80 /* When not ECP/EPP: Use level IRQ */
-#define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controlls direction */
- /* of the parallel port */
-
-/* Function Control Register (FCR) bits */
-#define FCR_LDE 0x10 /* Logical Drive Exchange */
-#define FCR_ZWS_ENA 0x20 /* Enable short host read/write in ECP/EPP */
-
-/* Printer Control Register (PCR) bits */
-#define PCR_EPP_ENABLE 0x01
-#define PCR_EPP_IEEE 0x02 /* Enable EPP Version 1.9 (IEEE 1284) */
-#define PCR_ECP_ENABLE 0x04
-#define PCR_ECP_CLK_ENA 0x08 /* If 0 ECP Clock is stopped on Power down */
-#define PCR_IRQ_POLAR 0x20 /* If 0 IRQ is level high or negative pulse, */
- /* if 1 polarity is inverted */
-#define PCR_IRQ_ODRAIN 0x40 /* If 1, IRQ is open drain */
-
-/* Tape UARTs and Parallel Port Config Register (TUP) bits */
-#define TUP_EPP_TIMO 0x02 /* Enable EPP timeout IRQ */
-
-/* Advanced SuperIO Config Register (ASC) bits */
-#define ASC_LPT_IRQ7 0x01 /* Always use IRQ7 for LPT */
-#define ASC_DRV2_SEL 0x02 /* Logical Drive Exchange controlled by TDR */
-
-#define FER_RESERVED 0x00
-#define FAR_RESERVED 0x00
-#define PTR_RESERVED 0x73
-#define FCR_RESERVED 0xc4
-#define PCR_RESERVED 0x10
-#define KRR_RESERVED 0x00
-#define PMC_RESERVED 0x98
-#define TUP_RESERVED 0xfb
-#define SIP_RESERVED 0x00
-#define ASC_RESERVED 0x18
-#define CS0CF0_RESERVED 0x00
-#define CS0CF1_RESERVED 0x08
-#define CS1CF0_RESERVED 0x00
-#define CS1CF1_RESERVED 0x08
-
-#ifdef __KERNEL__
-
-#include <linux/spinlock.h>
-
-#include <asm/system.h>
-#include <asm/io.h>
-
-extern spinlock_t ns87303_lock;
-
-static inline int ns87303_modify(unsigned long port, unsigned int index,
- unsigned char clr, unsigned char set)
-{
- static unsigned char reserved[] = {
- FER_RESERVED, FAR_RESERVED, PTR_RESERVED, FCR_RESERVED,
- PCR_RESERVED, KRR_RESERVED, PMC_RESERVED, TUP_RESERVED,
- SIP_RESERVED, ASC_RESERVED, CS0CF0_RESERVED, CS0CF1_RESERVED,
- CS1CF0_RESERVED, CS1CF1_RESERVED
- };
- unsigned long flags;
- unsigned char value;
-
- if (index > 0x0d)
- return -EINVAL;
-
- spin_lock_irqsave(&ns87303_lock, flags);
-
- outb(index, port);
- value = inb(port + 1);
- value &= ~(reserved[index] | clr);
- value |= set;
- outb(value, port + 1);
- outb(value, port + 1);
-
- spin_unlock_irqrestore(&ns87303_lock, flags);
-
- return 0;
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* !(_SPARC_NS87303_H) */
+++ /dev/null
-/*
- * obio.h: Some useful locations in 0xFXXXXXXXX PA obio space on sun4d.
- *
- * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
- */
-
-#ifndef _SPARC_OBIO_H
-#define _SPARC_OBIO_H
-
-#include <asm/asi.h>
-
-/* This weird monster likes to use the very upper parts of
- 36bit PA for these things :) */
-
-/* CSR space (for each XDBUS)
- * ------------------------------------------------------------------------
- * | 0xFE | DEVID | | XDBUS ID | |
- * ------------------------------------------------------------------------
- * 35 28 27 20 19 10 9 8 7 0
- */
-
-#define CSR_BASE_ADDR 0xe0000000
-#define CSR_CPU_SHIFT (32 - 4 - 5)
-#define CSR_XDBUS_SHIFT 8
-
-#define CSR_BASE(cpu) (((CSR_BASE_ADDR >> CSR_CPU_SHIFT) + cpu) << CSR_CPU_SHIFT)
-
-/* ECSR space (not for each XDBUS)
- * ------------------------------------------------------------------------
- * | 0xF | DEVID[7:1] | |
- * ------------------------------------------------------------------------
- * 35 32 31 25 24 0
- */
-
-#define ECSR_BASE_ADDR 0x00000000
-#define ECSR_CPU_SHIFT (32 - 5)
-#define ECSR_DEV_SHIFT (32 - 8)
-
-#define ECSR_BASE(cpu) ((cpu) << ECSR_CPU_SHIFT)
-#define ECSR_DEV_BASE(devid) ((devid) << ECSR_DEV_SHIFT)
-
-/* Bus Watcher */
-#define BW_LOCAL_BASE 0xfff00000
-
-#define BW_CID 0x00000000
-#define BW_DBUS_CTRL 0x00000008
-#define BW_DBUS_DATA 0x00000010
-#define BW_CTRL 0x00001000
-#define BW_INTR_TABLE 0x00001040
-#define BW_INTR_TABLE_CLEAR 0x00001080
-#define BW_PRESCALER 0x000010c0
-#define BW_PTIMER_LIMIT 0x00002000
-#define BW_PTIMER_COUNTER2 0x00002004
-#define BW_PTIMER_NDLIMIT 0x00002008
-#define BW_PTIMER_CTRL 0x0000200c
-#define BW_PTIMER_COUNTER 0x00002010
-#define BW_TIMER_LIMIT 0x00003000
-#define BW_TIMER_COUNTER2 0x00003004
-#define BW_TIMER_NDLIMIT 0x00003008
-#define BW_TIMER_CTRL 0x0000300c
-#define BW_TIMER_COUNTER 0x00003010
-
-/* BW Control */
-#define BW_CTRL_USER_TIMER 0x00000004 /* Is User Timer Free run enabled */
-
-/* Boot Bus */
-#define BB_LOCAL_BASE 0xf0000000
-
-#define BB_STAT1 0x00100000
-#define BB_STAT2 0x00120000
-#define BB_STAT3 0x00140000
-#define BB_LEDS 0x002e0000
-
-/* Bits in BB_STAT2 */
-#define BB_STAT2_AC_INTR 0x04 /* Aiee! 5ms and power is gone... */
-#define BB_STAT2_TMP_INTR 0x10 /* My Penguins are burning. Are you able to smell it? */
-#define BB_STAT2_FAN_INTR 0x20 /* My fan refuses to work */
-#define BB_STAT2_PWR_INTR 0x40 /* On SC2000, one of the two ACs died. Ok, we go on... */
-#define BB_STAT2_MASK (BB_STAT2_AC_INTR|BB_STAT2_TMP_INTR|BB_STAT2_FAN_INTR|BB_STAT2_PWR_INTR)
-
-/* Cache Controller */
-#define CC_BASE 0x1F00000
-#define CC_DATSTREAM 0x1F00000 /* Data stream register */
-#define CC_DATSIZE 0x1F0003F /* Size */
-#define CC_SRCSTREAM 0x1F00100 /* Source stream register */
-#define CC_DESSTREAM 0x1F00200 /* Destination stream register */
-#define CC_RMCOUNT 0x1F00300 /* Count of references and misses */
-#define CC_IPEN 0x1F00406 /* Pending Interrupts */
-#define CC_IMSK 0x1F00506 /* Interrupt Mask */
-#define CC_ICLR 0x1F00606 /* Clear pending Interrupts */
-#define CC_IGEN 0x1F00704 /* Generate Interrupt register */
-#define CC_STEST 0x1F00804 /* Internal self-test */
-#define CC_CREG 0x1F00A04 /* Control register */
-#define CC_SREG 0x1F00B00 /* Status register */
-#define CC_RREG 0x1F00C04 /* Reset register */
-#define CC_EREG 0x1F00E00 /* Error code register */
-#define CC_CID 0x1F00F04 /* Component ID */
-
-#ifndef __ASSEMBLY__
-
-static inline int bw_get_intr_mask(int sbus_level)
-{
- int mask;
-
- __asm__ __volatile__ ("lduha [%1] %2, %0" :
- "=r" (mask) :
- "r" (BW_LOCAL_BASE + BW_INTR_TABLE + (sbus_level << 3)),
- "i" (ASI_M_CTL));
- return mask;
-}
-
-static inline void bw_clear_intr_mask(int sbus_level, int mask)
-{
- __asm__ __volatile__ ("stha %0, [%1] %2" : :
- "r" (mask),
- "r" (BW_LOCAL_BASE + BW_INTR_TABLE_CLEAR + (sbus_level << 3)),
- "i" (ASI_M_CTL));
-}
-
-static inline unsigned bw_get_prof_limit(int cpu)
-{
- unsigned limit;
-
- __asm__ __volatile__ ("lda [%1] %2, %0" :
- "=r" (limit) :
- "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
- "i" (ASI_M_CTL));
- return limit;
-}
-
-static inline void bw_set_prof_limit(int cpu, unsigned limit)
-{
- __asm__ __volatile__ ("sta %0, [%1] %2" : :
- "r" (limit),
- "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
- "i" (ASI_M_CTL));
-}
-
-static inline unsigned bw_get_ctrl(int cpu)
-{
- unsigned ctrl;
-
- __asm__ __volatile__ ("lda [%1] %2, %0" :
- "=r" (ctrl) :
- "r" (CSR_BASE(cpu) + BW_CTRL),
- "i" (ASI_M_CTL));
- return ctrl;
-}
-
-static inline void bw_set_ctrl(int cpu, unsigned ctrl)
-{
- __asm__ __volatile__ ("sta %0, [%1] %2" : :
- "r" (ctrl),
- "r" (CSR_BASE(cpu) + BW_CTRL),
- "i" (ASI_M_CTL));
-}
-
-extern unsigned char cpu_leds[32];
-
-static inline void show_leds(int cpuid)
-{
- cpuid &= 0x1e;
- __asm__ __volatile__ ("stba %0, [%1] %2" : :
- "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
- "r" (ECSR_BASE(cpuid) | BB_LEDS),
- "i" (ASI_M_CTL));
-}
-
-static inline unsigned cc_get_ipen(void)
-{
- unsigned pending;
-
- __asm__ __volatile__ ("lduha [%1] %2, %0" :
- "=r" (pending) :
- "r" (CC_IPEN),
- "i" (ASI_M_MXCC));
- return pending;
-}
-
-static inline void cc_set_iclr(unsigned clear)
-{
- __asm__ __volatile__ ("stha %0, [%1] %2" : :
- "r" (clear),
- "r" (CC_ICLR),
- "i" (ASI_M_MXCC));
-}
-
-static inline unsigned cc_get_imsk(void)
-{
- unsigned mask;
-
- __asm__ __volatile__ ("lduha [%1] %2, %0" :
- "=r" (mask) :
- "r" (CC_IMSK),
- "i" (ASI_M_MXCC));
- return mask;
-}
-
-static inline void cc_set_imsk(unsigned mask)
-{
- __asm__ __volatile__ ("stha %0, [%1] %2" : :
- "r" (mask),
- "r" (CC_IMSK),
- "i" (ASI_M_MXCC));
-}
-
-static inline unsigned cc_get_imsk_other(int cpuid)
-{
- unsigned mask;
-
- __asm__ __volatile__ ("lduha [%1] %2, %0" :
- "=r" (mask) :
- "r" (ECSR_BASE(cpuid) | CC_IMSK),
- "i" (ASI_M_CTL));
- return mask;
-}
-
-static inline void cc_set_imsk_other(int cpuid, unsigned mask)
-{
- __asm__ __volatile__ ("stha %0, [%1] %2" : :
- "r" (mask),
- "r" (ECSR_BASE(cpuid) | CC_IMSK),
- "i" (ASI_M_CTL));
-}
-
-static inline void cc_set_igen(unsigned gen)
-{
- __asm__ __volatile__ ("sta %0, [%1] %2" : :
- "r" (gen),
- "r" (CC_IGEN),
- "i" (ASI_M_MXCC));
-}
-
-/* +-------+-------------+-----------+------------------------------------+
- * | bcast | devid | sid | levels mask |
- * +-------+-------------+-----------+------------------------------------+
- * 31 30 23 22 15 14 0
- */
-#define IGEN_MESSAGE(bcast, devid, sid, levels) \
- (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
-
-static inline void sun4d_send_ipi(int cpu, int level)
-{
- cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1)));
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* !(_SPARC_OBIO_H) */
+++ /dev/null
-#ifndef _ASM_SPARC_OF_DEVICE_H
-#define _ASM_SPARC_OF_DEVICE_H
-#ifdef __KERNEL__
-
-#include <linux/device.h>
-#include <linux/of.h>
-#include <linux/mod_devicetable.h>
-#include <asm/openprom.h>
-
-/*
- * The of_device is a kind of "base class" that is a superset of
- * struct device for use by devices attached to an OF node and
- * probed using OF properties.
- */
-struct of_device
-{
- struct device_node *node;
- struct device dev;
- struct resource resource[PROMREG_MAX];
- unsigned int irqs[PROMINTR_MAX];
- int num_irqs;
-
- void *sysdata;
-
- int slot;
- int portid;
- int clock_freq;
-};
-
-extern void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name);
-extern void of_iounmap(struct resource *res, void __iomem *base, unsigned long size);
-
-/* These are just here during the transition */
-#include <linux/of_device.h>
-#include <linux/of_platform.h>
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_SPARC_OF_DEVICE_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_OF_PLATFORM_H
-#define ___ASM_SPARC_OF_PLATFORM_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/of_platform_64.h>
-#else
-#include <asm-sparc/of_platform_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _ASM_SPARC_OF_PLATFORM_H
-#define _ASM_SPARC_OF_PLATFORM_H
-/*
- * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
- * <benh@kernel.crashing.org>
- * Modified for Sparc by merging parts of asm-sparc/of_device.h
- * by Stephen Rothwell
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-/* This is just here during the transition */
-#include <linux/of_platform.h>
-
-extern struct bus_type ebus_bus_type;
-extern struct bus_type sbus_bus_type;
-
-#define of_bus_type of_platform_bus_type /* for compatibility */
-
-#endif /* _ASM_SPARC_OF_PLATFORM_H */
+++ /dev/null
-#ifndef _ASM_SPARC64_OF_PLATFORM_H
-#define _ASM_SPARC64_OF_PLATFORM_H
-/*
- * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
- * <benh@kernel.crashing.org>
- * Modified for Sparc by merging parts of asm-sparc/of_device.h
- * by Stephen Rothwell
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-/* This is just here during the transition */
-#include <linux/of_platform.h>
-
-extern struct bus_type isa_bus_type;
-extern struct bus_type ebus_bus_type;
-extern struct bus_type sbus_bus_type;
-
-#define of_bus_type of_platform_bus_type /* for compatibility */
-
-#endif /* _ASM_SPARC64_OF_PLATFORM_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_OPENPROM_H
-#define ___ASM_SPARC_OPENPROM_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/openprom_64.h>
-#else
-#include <asm-sparc/openprom_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef __SPARC_OPENPROM_H
-#define __SPARC_OPENPROM_H
-
-/* openprom.h: Prom structures and defines for access to the OPENBOOT
- * prom routines and data areas.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-/* Empirical constants... */
-#define LINUX_OPPROM_MAGIC 0x10010407
-
-#ifndef __ASSEMBLY__
-/* V0 prom device operations. */
-struct linux_dev_v0_funcs {
- int (*v0_devopen)(char *device_str);
- int (*v0_devclose)(int dev_desc);
- int (*v0_rdblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
- int (*v0_wrblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
- int (*v0_wrnetdev)(int dev_desc, int num_bytes, char *buf);
- int (*v0_rdnetdev)(int dev_desc, int num_bytes, char *buf);
- int (*v0_rdchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
- int (*v0_wrchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
- int (*v0_seekdev)(int dev_desc, long logical_offst, int from);
-};
-
-/* V2 and later prom device operations. */
-struct linux_dev_v2_funcs {
- int (*v2_inst2pkg)(int d); /* Convert ihandle to phandle */
- char * (*v2_dumb_mem_alloc)(char *va, unsigned sz);
- void (*v2_dumb_mem_free)(char *va, unsigned sz);
-
- /* To map devices into virtual I/O space. */
- char * (*v2_dumb_mmap)(char *virta, int which_io, unsigned paddr, unsigned sz);
- void (*v2_dumb_munmap)(char *virta, unsigned size);
-
- int (*v2_dev_open)(char *devpath);
- void (*v2_dev_close)(int d);
- int (*v2_dev_read)(int d, char *buf, int nbytes);
- int (*v2_dev_write)(int d, char *buf, int nbytes);
- int (*v2_dev_seek)(int d, int hi, int lo);
-
- /* Never issued (multistage load support) */
- void (*v2_wheee2)(void);
- void (*v2_wheee3)(void);
-};
-
-struct linux_mlist_v0 {
- struct linux_mlist_v0 *theres_more;
- char *start_adr;
- unsigned num_bytes;
-};
-
-struct linux_mem_v0 {
- struct linux_mlist_v0 **v0_totphys;
- struct linux_mlist_v0 **v0_prommap;
- struct linux_mlist_v0 **v0_available; /* What we can use */
-};
-
-/* Arguments sent to the kernel from the boot prompt. */
-struct linux_arguments_v0 {
- char *argv[8];
- char args[100];
- char boot_dev[2];
- int boot_dev_ctrl;
- int boot_dev_unit;
- int dev_partition;
- char *kernel_file_name;
- void *aieee1; /* XXX */
-};
-
-/* V2 and up boot things. */
-struct linux_bootargs_v2 {
- char **bootpath;
- char **bootargs;
- int *fd_stdin;
- int *fd_stdout;
-};
-
-/* The top level PROM vector. */
-struct linux_romvec {
- /* Version numbers. */
- unsigned int pv_magic_cookie;
- unsigned int pv_romvers;
- unsigned int pv_plugin_revision;
- unsigned int pv_printrev;
-
- /* Version 0 memory descriptors. */
- struct linux_mem_v0 pv_v0mem;
-
- /* Node operations. */
- struct linux_nodeops *pv_nodeops;
-
- char **pv_bootstr;
- struct linux_dev_v0_funcs pv_v0devops;
-
- char *pv_stdin;
- char *pv_stdout;
-#define PROMDEV_KBD 0 /* input from keyboard */
-#define PROMDEV_SCREEN 0 /* output to screen */
-#define PROMDEV_TTYA 1 /* in/out to ttya */
-#define PROMDEV_TTYB 2 /* in/out to ttyb */
-
- /* Blocking getchar/putchar. NOT REENTRANT! (grr) */
- int (*pv_getchar)(void);
- void (*pv_putchar)(int ch);
-
- /* Non-blocking variants. */
- int (*pv_nbgetchar)(void);
- int (*pv_nbputchar)(int ch);
-
- void (*pv_putstr)(char *str, int len);
-
- /* Miscellany. */
- void (*pv_reboot)(char *bootstr);
- void (*pv_printf)(__const__ char *fmt, ...);
- void (*pv_abort)(void);
- __volatile__ int *pv_ticks;
- void (*pv_halt)(void);
- void (**pv_synchook)(void);
-
- /* Evaluate a forth string, not different proto for V0 and V2->up. */
- union {
- void (*v0_eval)(int len, char *str);
- void (*v2_eval)(char *str);
- } pv_fortheval;
-
- struct linux_arguments_v0 **pv_v0bootargs;
-
- /* Get ether address. */
- unsigned int (*pv_enaddr)(int d, char *enaddr);
-
- struct linux_bootargs_v2 pv_v2bootargs;
- struct linux_dev_v2_funcs pv_v2devops;
-
- int filler[15];
-
- /* This one is sun4c/sun4 only. */
- void (*pv_setctxt)(int ctxt, char *va, int pmeg);
-
- /* Prom version 3 Multiprocessor routines. This stuff is crazy.
- * No joke. Calling these when there is only one cpu probably
- * crashes the machine, have to test this. :-)
- */
-
- /* v3_cpustart() will start the cpu 'whichcpu' in mmu-context
- * 'thiscontext' executing at address 'prog_counter'
- */
- int (*v3_cpustart)(unsigned int whichcpu, int ctxtbl_ptr,
- int thiscontext, char *prog_counter);
-
- /* v3_cpustop() will cause cpu 'whichcpu' to stop executing
- * until a resume cpu call is made.
- */
- int (*v3_cpustop)(unsigned int whichcpu);
-
- /* v3_cpuidle() will idle cpu 'whichcpu' until a stop or
- * resume cpu call is made.
- */
- int (*v3_cpuidle)(unsigned int whichcpu);
-
- /* v3_cpuresume() will resume processor 'whichcpu' executing
- * starting with whatever 'pc' and 'npc' were left at the
- * last 'idle' or 'stop' call.
- */
- int (*v3_cpuresume)(unsigned int whichcpu);
-};
-
-/* Routines for traversing the prom device tree. */
-struct linux_nodeops {
- int (*no_nextnode)(int node);
- int (*no_child)(int node);
- int (*no_proplen)(int node, char *name);
- int (*no_getprop)(int node, char *name, char *val);
- int (*no_setprop)(int node, char *name, char *val, int len);
- char * (*no_nextprop)(int node, char *name);
-};
-
-/* More fun PROM structures for device probing. */
-#define PROMREG_MAX 16
-#define PROMVADDR_MAX 16
-#define PROMINTR_MAX 15
-
-struct linux_prom_registers {
- unsigned int which_io; /* is this in OBIO space? */
- unsigned int phys_addr; /* The physical address of this register */
- unsigned int reg_size; /* How many bytes does this register take up? */
-};
-
-struct linux_prom_irqs {
- int pri; /* IRQ priority */
- int vector; /* This is foobar, what does it do? */
-};
-
-/* Element of the "ranges" vector */
-struct linux_prom_ranges {
- unsigned int ot_child_space;
- unsigned int ot_child_base; /* Bus feels this */
- unsigned int ot_parent_space;
- unsigned int ot_parent_base; /* CPU looks from here */
- unsigned int or_size;
-};
-
-/* Ranges and reg properties are a bit different for PCI. */
-struct linux_prom_pci_registers {
- /*
- * We don't know what information this field contain.
- * We guess, PCI device function is in bits 15:8
- * So, ...
- */
- unsigned int which_io; /* Let it be which_io */
-
- unsigned int phys_hi;
- unsigned int phys_lo;
-
- unsigned int size_hi;
- unsigned int size_lo;
-};
-
-struct linux_prom_pci_ranges {
- unsigned int child_phys_hi; /* Only certain bits are encoded here. */
- unsigned int child_phys_mid;
- unsigned int child_phys_lo;
-
- unsigned int parent_phys_hi;
- unsigned int parent_phys_lo;
-
- unsigned int size_hi;
- unsigned int size_lo;
-};
-
-struct linux_prom_pci_assigned_addresses {
- unsigned int which_io;
-
- unsigned int phys_hi;
- unsigned int phys_lo;
-
- unsigned int size_hi;
- unsigned int size_lo;
-};
-
-struct linux_prom_ebus_ranges {
- unsigned int child_phys_hi;
- unsigned int child_phys_lo;
-
- unsigned int parent_phys_hi;
- unsigned int parent_phys_mid;
- unsigned int parent_phys_lo;
-
- unsigned int size;
-};
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(__SPARC_OPENPROM_H) */
+++ /dev/null
-#ifndef __SPARC64_OPENPROM_H
-#define __SPARC64_OPENPROM_H
-
-/* openprom.h: Prom structures and defines for access to the OPENBOOT
- * prom routines and data areas.
- *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef __ASSEMBLY__
-/* V0 prom device operations. */
-struct linux_dev_v0_funcs {
- int (*v0_devopen)(char *device_str);
- int (*v0_devclose)(int dev_desc);
- int (*v0_rdblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
- int (*v0_wrblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
- int (*v0_wrnetdev)(int dev_desc, int num_bytes, char *buf);
- int (*v0_rdnetdev)(int dev_desc, int num_bytes, char *buf);
- int (*v0_rdchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
- int (*v0_wrchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
- int (*v0_seekdev)(int dev_desc, long logical_offst, int from);
-};
-
-/* V2 and later prom device operations. */
-struct linux_dev_v2_funcs {
- int (*v2_inst2pkg)(int d); /* Convert ihandle to phandle */
- char * (*v2_dumb_mem_alloc)(char *va, unsigned sz);
- void (*v2_dumb_mem_free)(char *va, unsigned sz);
-
- /* To map devices into virtual I/O space. */
- char * (*v2_dumb_mmap)(char *virta, int which_io, unsigned paddr, unsigned sz);
- void (*v2_dumb_munmap)(char *virta, unsigned size);
-
- int (*v2_dev_open)(char *devpath);
- void (*v2_dev_close)(int d);
- int (*v2_dev_read)(int d, char *buf, int nbytes);
- int (*v2_dev_write)(int d, char *buf, int nbytes);
- int (*v2_dev_seek)(int d, int hi, int lo);
-
- /* Never issued (multistage load support) */
- void (*v2_wheee2)(void);
- void (*v2_wheee3)(void);
-};
-
-struct linux_mlist_v0 {
- struct linux_mlist_v0 *theres_more;
- unsigned start_adr;
- unsigned num_bytes;
-};
-
-struct linux_mem_v0 {
- struct linux_mlist_v0 **v0_totphys;
- struct linux_mlist_v0 **v0_prommap;
- struct linux_mlist_v0 **v0_available; /* What we can use */
-};
-
-/* Arguments sent to the kernel from the boot prompt. */
-struct linux_arguments_v0 {
- char *argv[8];
- char args[100];
- char boot_dev[2];
- int boot_dev_ctrl;
- int boot_dev_unit;
- int dev_partition;
- char *kernel_file_name;
- void *aieee1; /* XXX */
-};
-
-/* V2 and up boot things. */
-struct linux_bootargs_v2 {
- char **bootpath;
- char **bootargs;
- int *fd_stdin;
- int *fd_stdout;
-};
-
-/* The top level PROM vector. */
-struct linux_romvec {
- /* Version numbers. */
- unsigned int pv_magic_cookie;
- unsigned int pv_romvers;
- unsigned int pv_plugin_revision;
- unsigned int pv_printrev;
-
- /* Version 0 memory descriptors. */
- struct linux_mem_v0 pv_v0mem;
-
- /* Node operations. */
- struct linux_nodeops *pv_nodeops;
-
- char **pv_bootstr;
- struct linux_dev_v0_funcs pv_v0devops;
-
- char *pv_stdin;
- char *pv_stdout;
-#define PROMDEV_KBD 0 /* input from keyboard */
-#define PROMDEV_SCREEN 0 /* output to screen */
-#define PROMDEV_TTYA 1 /* in/out to ttya */
-#define PROMDEV_TTYB 2 /* in/out to ttyb */
-
- /* Blocking getchar/putchar. NOT REENTRANT! (grr) */
- int (*pv_getchar)(void);
- void (*pv_putchar)(int ch);
-
- /* Non-blocking variants. */
- int (*pv_nbgetchar)(void);
- int (*pv_nbputchar)(int ch);
-
- void (*pv_putstr)(char *str, int len);
-
- /* Miscellany. */
- void (*pv_reboot)(char *bootstr);
- void (*pv_printf)(__const__ char *fmt, ...);
- void (*pv_abort)(void);
- __volatile__ int *pv_ticks;
- void (*pv_halt)(void);
- void (**pv_synchook)(void);
-
- /* Evaluate a forth string, not different proto for V0 and V2->up. */
- union {
- void (*v0_eval)(int len, char *str);
- void (*v2_eval)(char *str);
- } pv_fortheval;
-
- struct linux_arguments_v0 **pv_v0bootargs;
-
- /* Get ether address. */
- unsigned int (*pv_enaddr)(int d, char *enaddr);
-
- struct linux_bootargs_v2 pv_v2bootargs;
- struct linux_dev_v2_funcs pv_v2devops;
-
- int filler[15];
-
- /* This one is sun4c/sun4 only. */
- void (*pv_setctxt)(int ctxt, char *va, int pmeg);
-
- /* Prom version 3 Multiprocessor routines. This stuff is crazy.
- * No joke. Calling these when there is only one cpu probably
- * crashes the machine, have to test this. :-)
- */
-
- /* v3_cpustart() will start the cpu 'whichcpu' in mmu-context
- * 'thiscontext' executing at address 'prog_counter'
- */
- int (*v3_cpustart)(unsigned int whichcpu, int ctxtbl_ptr,
- int thiscontext, char *prog_counter);
-
- /* v3_cpustop() will cause cpu 'whichcpu' to stop executing
- * until a resume cpu call is made.
- */
- int (*v3_cpustop)(unsigned int whichcpu);
-
- /* v3_cpuidle() will idle cpu 'whichcpu' until a stop or
- * resume cpu call is made.
- */
- int (*v3_cpuidle)(unsigned int whichcpu);
-
- /* v3_cpuresume() will resume processor 'whichcpu' executing
- * starting with whatever 'pc' and 'npc' were left at the
- * last 'idle' or 'stop' call.
- */
- int (*v3_cpuresume)(unsigned int whichcpu);
-};
-
-/* Routines for traversing the prom device tree. */
-struct linux_nodeops {
- int (*no_nextnode)(int node);
- int (*no_child)(int node);
- int (*no_proplen)(int node, char *name);
- int (*no_getprop)(int node, char *name, char *val);
- int (*no_setprop)(int node, char *name, char *val, int len);
- char * (*no_nextprop)(int node, char *name);
-};
-
-/* More fun PROM structures for device probing. */
-#define PROMREG_MAX 24
-#define PROMVADDR_MAX 16
-#define PROMINTR_MAX 32
-
-struct linux_prom_registers {
- unsigned which_io; /* hi part of physical address */
- unsigned phys_addr; /* The physical address of this register */
- int reg_size; /* How many bytes does this register take up? */
-};
-
-struct linux_prom64_registers {
- unsigned long phys_addr;
- unsigned long reg_size;
-};
-
-struct linux_prom_irqs {
- int pri; /* IRQ priority */
- int vector; /* This is foobar, what does it do? */
-};
-
-/* Element of the "ranges" vector */
-struct linux_prom_ranges {
- unsigned int ot_child_space;
- unsigned int ot_child_base; /* Bus feels this */
- unsigned int ot_parent_space;
- unsigned int ot_parent_base; /* CPU looks from here */
- unsigned int or_size;
-};
-
-struct linux_prom64_ranges {
- unsigned long ot_child_base; /* Bus feels this */
- unsigned long ot_parent_base; /* CPU looks from here */
- unsigned long or_size;
-};
-
-/* Ranges and reg properties are a bit different for PCI. */
-struct linux_prom_pci_registers {
- unsigned int phys_hi;
- unsigned int phys_mid;
- unsigned int phys_lo;
-
- unsigned int size_hi;
- unsigned int size_lo;
-};
-
-struct linux_prom_pci_ranges {
- unsigned int child_phys_hi; /* Only certain bits are encoded here. */
- unsigned int child_phys_mid;
- unsigned int child_phys_lo;
-
- unsigned int parent_phys_hi;
- unsigned int parent_phys_lo;
-
- unsigned int size_hi;
- unsigned int size_lo;
-};
-
-struct linux_prom_pci_intmap {
- unsigned int phys_hi;
- unsigned int phys_mid;
- unsigned int phys_lo;
-
- unsigned int interrupt;
-
- int cnode;
- unsigned int cinterrupt;
-};
-
-struct linux_prom_pci_intmask {
- unsigned int phys_hi;
- unsigned int phys_mid;
- unsigned int phys_lo;
- unsigned int interrupt;
-};
-
-struct linux_prom_ebus_ranges {
- unsigned int child_phys_hi;
- unsigned int child_phys_lo;
-
- unsigned int parent_phys_hi;
- unsigned int parent_phys_mid;
- unsigned int parent_phys_lo;
-
- unsigned int size;
-};
-
-struct linux_prom_ebus_intmap {
- unsigned int phys_hi;
- unsigned int phys_lo;
-
- unsigned int interrupt;
-
- int cnode;
- unsigned int cinterrupt;
-};
-
-struct linux_prom_ebus_intmask {
- unsigned int phys_hi;
- unsigned int phys_lo;
- unsigned int interrupt;
-};
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(__SPARC64_OPENPROM_H) */
+++ /dev/null
-#ifndef _SPARC_OPENPROMIO_H
-#define _SPARC_OPENPROMIO_H
-
-#include <linux/compiler.h>
-#include <linux/ioctl.h>
-#include <linux/types.h>
-
-/*
- * SunOS and Solaris /dev/openprom definitions. The ioctl values
- * were chosen to be exactly equal to the SunOS equivalents.
- */
-
-struct openpromio
-{
- u_int oprom_size; /* Actual size of the oprom_array. */
- char oprom_array[1]; /* Holds property names and values. */
-};
-
-#define OPROMMAXPARAM 4096 /* Maximum size of oprom_array. */
-
-#define OPROMGETOPT 0x20004F01
-#define OPROMSETOPT 0x20004F02
-#define OPROMNXTOPT 0x20004F03
-#define OPROMSETOPT2 0x20004F04
-#define OPROMNEXT 0x20004F05
-#define OPROMCHILD 0x20004F06
-#define OPROMGETPROP 0x20004F07
-#define OPROMNXTPROP 0x20004F08
-#define OPROMU2P 0x20004F09
-#define OPROMGETCONS 0x20004F0A
-#define OPROMGETFBNAME 0x20004F0B
-#define OPROMGETBOOTARGS 0x20004F0C
-/* Linux extensions */ /* Arguments in oprom_array: */
-#define OPROMSETCUR 0x20004FF0 /* int node - Sets current node */
-#define OPROMPCI2NODE 0x20004FF1 /* int pci_bus, pci_devfn - Sets current node to PCI device's node */
-#define OPROMPATH2NODE 0x20004FF2 /* char path[] - Set current node from fully qualified PROM path */
-
-/*
- * Return values from OPROMGETCONS:
- */
-
-#define OPROMCONS_NOT_WSCONS 0
-#define OPROMCONS_STDIN_IS_KBD 0x1 /* stdin device is kbd */
-#define OPROMCONS_STDOUT_IS_FB 0x2 /* stdout is a framebuffer */
-#define OPROMCONS_OPENPROM 0x4 /* supports openboot */
-
-
-/*
- * NetBSD/OpenBSD /dev/openprom definitions.
- */
-
-struct opiocdesc
-{
- int op_nodeid; /* PROM Node ID (value-result) */
- int op_namelen; /* Length of op_name. */
- char __user *op_name; /* Pointer to the property name. */
- int op_buflen; /* Length of op_buf (value-result) */
- char __user *op_buf; /* Pointer to buffer. */
-};
-
-#define OPIOCGET _IOWR('O', 1, struct opiocdesc)
-#define OPIOCSET _IOW('O', 2, struct opiocdesc)
-#define OPIOCNEXTPROP _IOWR('O', 3, struct opiocdesc)
-#define OPIOCGETOPTNODE _IOR('O', 4, int)
-#define OPIOCGETNEXT _IOWR('O', 5, int)
-#define OPIOCGETCHILD _IOWR('O', 6, int)
-
-#endif /* _SPARC_OPENPROMIO_H */
-
+++ /dev/null
-#ifndef ___ASM_SPARC_OPLIB_H
-#define ___ASM_SPARC_OPLIB_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/oplib_64.h>
-#else
-#include <asm-sparc/oplib_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * oplib.h: Describes the interface and available routines in the
- * Linux Prom library.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef __SPARC_OPLIB_H
-#define __SPARC_OPLIB_H
-
-#include <asm/openprom.h>
-#include <linux/spinlock.h>
-#include <linux/compiler.h>
-
-/* The master romvec pointer... */
-extern struct linux_romvec *romvec;
-
-/* Enumeration to describe the prom major version we have detected. */
-enum prom_major_version {
- PROM_V0, /* Original sun4c V0 prom */
- PROM_V2, /* sun4c and early sun4m V2 prom */
- PROM_V3, /* sun4m and later, up to sun4d/sun4e machines V3 */
- PROM_P1275, /* IEEE compliant ISA based Sun PROM, only sun4u */
- PROM_SUN4, /* Old sun4 proms are totally different, but we'll shoehorn it to make it fit */
-};
-
-extern enum prom_major_version prom_vers;
-/* Revision, and firmware revision. */
-extern unsigned int prom_rev, prom_prev;
-
-/* Root node of the prom device tree, this stays constant after
- * initialization is complete.
- */
-extern int prom_root_node;
-
-/* Pointer to prom structure containing the device tree traversal
- * and usage utility functions. Only prom-lib should use these,
- * users use the interface defined by the library only!
- */
-extern struct linux_nodeops *prom_nodeops;
-
-/* The functions... */
-
-/* You must call prom_init() before using any of the library services,
- * preferably as early as possible. Pass it the romvec pointer.
- */
-extern void prom_init(struct linux_romvec *rom_ptr);
-
-/* Boot argument acquisition, returns the boot command line string. */
-extern char *prom_getbootargs(void);
-
-/* Device utilities. */
-
-/* Map and unmap devices in IO space at virtual addresses. Note that the
- * virtual address you pass is a request and the prom may put your mappings
- * somewhere else, so check your return value as that is where your new
- * mappings really are!
- *
- * Another note, these are only available on V2 or higher proms!
- */
-extern char *prom_mapio(char *virt_hint, int io_space, unsigned int phys_addr, unsigned int num_bytes);
-extern void prom_unmapio(char *virt_addr, unsigned int num_bytes);
-
-/* Device operations. */
-
-/* Open the device described by the passed string. Note, that the format
- * of the string is different on V0 vs. V2->higher proms. The caller must
- * know what he/she is doing! Returns the device descriptor, an int.
- */
-extern int prom_devopen(char *device_string);
-
-/* Close a previously opened device described by the passed integer
- * descriptor.
- */
-extern int prom_devclose(int device_handle);
-
-/* Do a seek operation on the device described by the passed integer
- * descriptor.
- */
-extern void prom_seek(int device_handle, unsigned int seek_hival,
- unsigned int seek_lowval);
-
-/* Miscellaneous routines, don't really fit in any category per se. */
-
-/* Reboot the machine with the command line passed. */
-extern void prom_reboot(char *boot_command);
-
-/* Evaluate the forth string passed. */
-extern void prom_feval(char *forth_string);
-
-/* Enter the prom, with possibility of continuation with the 'go'
- * command in newer proms.
- */
-extern void prom_cmdline(void);
-
-/* Enter the prom, with no chance of continuation for the stand-alone
- * which calls this.
- */
-extern void prom_halt(void) __attribute__ ((noreturn));
-
-/* Set the PROM 'sync' callback function to the passed function pointer.
- * When the user gives the 'sync' command at the prom prompt while the
- * kernel is still active, the prom will call this routine.
- *
- * XXX The arguments are different on V0 vs. V2->higher proms, grrr! XXX
- */
-typedef void (*sync_func_t)(void);
-extern void prom_setsync(sync_func_t func_ptr);
-
-/* Acquire the IDPROM of the root node in the prom device tree. This
- * gets passed a buffer where you would like it stuffed. The return value
- * is the format type of this idprom or 0xff on error.
- */
-extern unsigned char prom_get_idprom(char *idp_buffer, int idpbuf_size);
-
-/* Get the prom major version. */
-extern int prom_version(void);
-
-/* Get the prom plugin revision. */
-extern int prom_getrev(void);
-
-/* Get the prom firmware revision. */
-extern int prom_getprev(void);
-
-/* Character operations to/from the console.... */
-
-/* Non-blocking get character from console. */
-extern int prom_nbgetchar(void);
-
-/* Non-blocking put character to console. */
-extern int prom_nbputchar(char character);
-
-/* Blocking get character from console. */
-extern char prom_getchar(void);
-
-/* Blocking put character to console. */
-extern void prom_putchar(char character);
-
-/* Prom's internal routines, don't use in kernel/boot code. */
-extern void prom_printf(char *fmt, ...);
-extern void prom_write(const char *buf, unsigned int len);
-
-/* Multiprocessor operations... */
-
-/* Start the CPU with the given device tree node, context table, and context
- * at the passed program counter.
- */
-extern int prom_startcpu(int cpunode, struct linux_prom_registers *context_table,
- int context, char *program_counter);
-
-/* Stop the CPU with the passed device tree node. */
-extern int prom_stopcpu(int cpunode);
-
-/* Idle the CPU with the passed device tree node. */
-extern int prom_idlecpu(int cpunode);
-
-/* Re-Start the CPU with the passed device tree node. */
-extern int prom_restartcpu(int cpunode);
-
-/* PROM memory allocation facilities... */
-
-/* Allocated at possibly the given virtual address a chunk of the
- * indicated size.
- */
-extern char *prom_alloc(char *virt_hint, unsigned int size);
-
-/* Free a previously allocated chunk. */
-extern void prom_free(char *virt_addr, unsigned int size);
-
-/* Sun4/sun4c specific memory-management startup hook. */
-
-/* Map the passed segment in the given context at the passed
- * virtual address.
- */
-extern void prom_putsegment(int context, unsigned long virt_addr,
- int physical_segment);
-
-
-/* PROM device tree traversal functions... */
-
-#ifdef PROMLIB_INTERNAL
-
-/* Internal version of prom_getchild. */
-extern int __prom_getchild(int parent_node);
-
-/* Internal version of prom_getsibling. */
-extern int __prom_getsibling(int node);
-
-#endif
-
-
-/* Get the child node of the given node, or zero if no child exists. */
-extern int prom_getchild(int parent_node);
-
-/* Get the next sibling node of the given node, or zero if no further
- * siblings exist.
- */
-extern int prom_getsibling(int node);
-
-/* Get the length, at the passed node, of the given property type.
- * Returns -1 on error (ie. no such property at this node).
- */
-extern int prom_getproplen(int thisnode, char *property);
-
-/* Fetch the requested property using the given buffer. Returns
- * the number of bytes the prom put into your buffer or -1 on error.
- */
-extern int __must_check prom_getproperty(int thisnode, char *property,
- char *prop_buffer, int propbuf_size);
-
-/* Acquire an integer property. */
-extern int prom_getint(int node, char *property);
-
-/* Acquire an integer property, with a default value. */
-extern int prom_getintdefault(int node, char *property, int defval);
-
-/* Acquire a boolean property, 0=FALSE 1=TRUE. */
-extern int prom_getbool(int node, char *prop);
-
-/* Acquire a string property, null string on error. */
-extern void prom_getstring(int node, char *prop, char *buf, int bufsize);
-
-/* Does the passed node have the given "name"? YES=1 NO=0 */
-extern int prom_nodematch(int thisnode, char *name);
-
-/* Search all siblings starting at the passed node for "name" matching
- * the given string. Returns the node on success, zero on failure.
- */
-extern int prom_searchsiblings(int node_start, char *name);
-
-/* Return the first property type, as a string, for the given node.
- * Returns a null string on error.
- */
-extern char *prom_firstprop(int node, char *buffer);
-
-/* Returns the next property after the passed property for the given
- * node. Returns null string on failure.
- */
-extern char *prom_nextprop(int node, char *prev_property, char *buffer);
-
-/* Returns phandle of the path specified */
-extern int prom_finddevice(char *name);
-
-/* Returns 1 if the specified node has given property. */
-extern int prom_node_has_property(int node, char *property);
-
-/* Set the indicated property at the given node with the passed value.
- * Returns the number of bytes of your value that the prom took.
- */
-extern int prom_setprop(int node, char *prop_name, char *prop_value,
- int value_size);
-
-extern int prom_pathtoinode(char *path);
-extern int prom_inst2pkg(int);
-
-/* Dorking with Bus ranges... */
-
-/* Apply promlib probes OBIO ranges to registers. */
-extern void prom_apply_obio_ranges(struct linux_prom_registers *obioregs, int nregs);
-
-/* Apply ranges of any prom node (and optionally parent node as well) to registers. */
-extern void prom_apply_generic_ranges(int node, int parent,
- struct linux_prom_registers *sbusregs, int nregs);
-
-/* CPU probing helpers. */
-int cpu_find_by_instance(int instance, int *prom_node, int *mid);
-int cpu_find_by_mid(int mid, int *prom_node);
-int cpu_get_hwmid(int prom_node);
-
-extern spinlock_t prom_lock;
-
-#endif /* !(__SPARC_OPLIB_H) */
+++ /dev/null
-/* oplib.h: Describes the interface and available routines in the
- * Linux Prom library.
- *
- * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
- * Copyright (C) 1996 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-
-#ifndef __SPARC64_OPLIB_H
-#define __SPARC64_OPLIB_H
-
-#include <asm/openprom.h>
-
-/* OBP version string. */
-extern char prom_version[];
-
-/* Root node of the prom device tree, this stays constant after
- * initialization is complete.
- */
-extern int prom_root_node;
-
-/* PROM stdin and stdout */
-extern int prom_stdin, prom_stdout;
-
-/* /chosen node of the prom device tree, this stays constant after
- * initialization is complete.
- */
-extern int prom_chosen_node;
-
-/* Helper values and strings in arch/sparc64/kernel/head.S */
-extern const char prom_peer_name[];
-extern const char prom_compatible_name[];
-extern const char prom_root_compatible[];
-extern const char prom_cpu_compatible[];
-extern const char prom_finddev_name[];
-extern const char prom_chosen_path[];
-extern const char prom_cpu_path[];
-extern const char prom_getprop_name[];
-extern const char prom_mmu_name[];
-extern const char prom_callmethod_name[];
-extern const char prom_translate_name[];
-extern const char prom_map_name[];
-extern const char prom_unmap_name[];
-extern int prom_mmu_ihandle_cache;
-extern unsigned int prom_boot_mapped_pc;
-extern unsigned int prom_boot_mapping_mode;
-extern unsigned long prom_boot_mapping_phys_high, prom_boot_mapping_phys_low;
-
-struct linux_mlist_p1275 {
- struct linux_mlist_p1275 *theres_more;
- unsigned long start_adr;
- unsigned long num_bytes;
-};
-
-struct linux_mem_p1275 {
- struct linux_mlist_p1275 **p1275_totphys;
- struct linux_mlist_p1275 **p1275_prommap;
- struct linux_mlist_p1275 **p1275_available; /* What we can use */
-};
-
-/* The functions... */
-
-/* You must call prom_init() before using any of the library services,
- * preferably as early as possible. Pass it the romvec pointer.
- */
-extern void prom_init(void *cif_handler, void *cif_stack);
-
-/* Boot argument acquisition, returns the boot command line string. */
-extern char *prom_getbootargs(void);
-
-/* Device utilities. */
-
-/* Device operations. */
-
-/* Open the device described by the passed string. Note, that the format
- * of the string is different on V0 vs. V2->higher proms. The caller must
- * know what he/she is doing! Returns the device descriptor, an int.
- */
-extern int prom_devopen(const char *device_string);
-
-/* Close a previously opened device described by the passed integer
- * descriptor.
- */
-extern int prom_devclose(int device_handle);
-
-/* Do a seek operation on the device described by the passed integer
- * descriptor.
- */
-extern void prom_seek(int device_handle, unsigned int seek_hival,
- unsigned int seek_lowval);
-
-/* Miscellaneous routines, don't really fit in any category per se. */
-
-/* Reboot the machine with the command line passed. */
-extern void prom_reboot(const char *boot_command);
-
-/* Evaluate the forth string passed. */
-extern void prom_feval(const char *forth_string);
-
-/* Enter the prom, with possibility of continuation with the 'go'
- * command in newer proms.
- */
-extern void prom_cmdline(void);
-
-/* Enter the prom, with no chance of continuation for the stand-alone
- * which calls this.
- */
-extern void prom_halt(void) __attribute__ ((noreturn));
-
-/* Halt and power-off the machine. */
-extern void prom_halt_power_off(void) __attribute__ ((noreturn));
-
-/* Set the PROM 'sync' callback function to the passed function pointer.
- * When the user gives the 'sync' command at the prom prompt while the
- * kernel is still active, the prom will call this routine.
- *
- */
-typedef int (*callback_func_t)(long *cmd);
-extern void prom_setcallback(callback_func_t func_ptr);
-
-/* Acquire the IDPROM of the root node in the prom device tree. This
- * gets passed a buffer where you would like it stuffed. The return value
- * is the format type of this idprom or 0xff on error.
- */
-extern unsigned char prom_get_idprom(char *idp_buffer, int idpbuf_size);
-
-/* Character operations to/from the console.... */
-
-/* Non-blocking get character from console. */
-extern int prom_nbgetchar(void);
-
-/* Non-blocking put character to console. */
-extern int prom_nbputchar(char character);
-
-/* Blocking get character from console. */
-extern char prom_getchar(void);
-
-/* Blocking put character to console. */
-extern void prom_putchar(char character);
-
-/* Prom's internal routines, don't use in kernel/boot code. */
-extern void prom_printf(const char *fmt, ...);
-extern void prom_write(const char *buf, unsigned int len);
-
-/* Multiprocessor operations... */
-#ifdef CONFIG_SMP
-/* Start the CPU with the given device tree node at the passed program
- * counter with the given arg passed in via register %o0.
- */
-extern void prom_startcpu(int cpunode, unsigned long pc, unsigned long arg);
-
-/* Start the CPU with the given cpu ID at the passed program
- * counter with the given arg passed in via register %o0.
- */
-extern void prom_startcpu_cpuid(int cpuid, unsigned long pc, unsigned long arg);
-
-/* Stop the CPU with the given cpu ID. */
-extern void prom_stopcpu_cpuid(int cpuid);
-
-/* Stop the current CPU. */
-extern void prom_stopself(void);
-
-/* Idle the current CPU. */
-extern void prom_idleself(void);
-
-/* Resume the CPU with the passed device tree node. */
-extern void prom_resumecpu(int cpunode);
-#endif
-
-/* Power management interfaces. */
-
-/* Put the current CPU to sleep. */
-extern void prom_sleepself(void);
-
-/* Put the entire system to sleep. */
-extern int prom_sleepsystem(void);
-
-/* Initiate a wakeup event. */
-extern int prom_wakeupsystem(void);
-
-/* MMU and memory related OBP interfaces. */
-
-/* Get unique string identifying SIMM at given physical address. */
-extern int prom_getunumber(int syndrome_code,
- unsigned long phys_addr,
- char *buf, int buflen);
-
-/* Retain physical memory to the caller across soft resets. */
-extern unsigned long prom_retain(const char *name,
- unsigned long pa_low, unsigned long pa_high,
- long size, long align);
-
-/* Load explicit I/D TLB entries into the calling processor. */
-extern long prom_itlb_load(unsigned long index,
- unsigned long tte_data,
- unsigned long vaddr);
-
-extern long prom_dtlb_load(unsigned long index,
- unsigned long tte_data,
- unsigned long vaddr);
-
-/* Map/Unmap client program address ranges. First the format of
- * the mapping mode argument.
- */
-#define PROM_MAP_WRITE 0x0001 /* Writable */
-#define PROM_MAP_READ 0x0002 /* Readable - sw */
-#define PROM_MAP_EXEC 0x0004 /* Executable - sw */
-#define PROM_MAP_LOCKED 0x0010 /* Locked, use i/dtlb load calls for this instead */
-#define PROM_MAP_CACHED 0x0020 /* Cacheable in both L1 and L2 caches */
-#define PROM_MAP_SE 0x0040 /* Side-Effects */
-#define PROM_MAP_GLOB 0x0080 /* Global */
-#define PROM_MAP_IE 0x0100 /* Invert-Endianness */
-#define PROM_MAP_DEFAULT (PROM_MAP_WRITE | PROM_MAP_READ | PROM_MAP_EXEC | PROM_MAP_CACHED)
-
-extern int prom_map(int mode, unsigned long size,
- unsigned long vaddr, unsigned long paddr);
-extern void prom_unmap(unsigned long size, unsigned long vaddr);
-
-
-/* PROM device tree traversal functions... */
-
-#ifdef PROMLIB_INTERNAL
-
-/* Internal version of prom_getchild. */
-extern int __prom_getchild(int parent_node);
-
-/* Internal version of prom_getsibling. */
-extern int __prom_getsibling(int node);
-
-#endif
-
-/* Get the child node of the given node, or zero if no child exists. */
-extern int prom_getchild(int parent_node);
-
-/* Get the next sibling node of the given node, or zero if no further
- * siblings exist.
- */
-extern int prom_getsibling(int node);
-
-/* Get the length, at the passed node, of the given property type.
- * Returns -1 on error (ie. no such property at this node).
- */
-extern int prom_getproplen(int thisnode, const char *property);
-
-/* Fetch the requested property using the given buffer. Returns
- * the number of bytes the prom put into your buffer or -1 on error.
- */
-extern int prom_getproperty(int thisnode, const char *property,
- char *prop_buffer, int propbuf_size);
-
-/* Acquire an integer property. */
-extern int prom_getint(int node, const char *property);
-
-/* Acquire an integer property, with a default value. */
-extern int prom_getintdefault(int node, const char *property, int defval);
-
-/* Acquire a boolean property, 0=FALSE 1=TRUE. */
-extern int prom_getbool(int node, const char *prop);
-
-/* Acquire a string property, null string on error. */
-extern void prom_getstring(int node, const char *prop, char *buf, int bufsize);
-
-/* Does the passed node have the given "name"? YES=1 NO=0 */
-extern int prom_nodematch(int thisnode, const char *name);
-
-/* Search all siblings starting at the passed node for "name" matching
- * the given string. Returns the node on success, zero on failure.
- */
-extern int prom_searchsiblings(int node_start, const char *name);
-
-/* Return the first property type, as a string, for the given node.
- * Returns a null string on error. Buffer should be at least 32B long.
- */
-extern char *prom_firstprop(int node, char *buffer);
-
-/* Returns the next property after the passed property for the given
- * node. Returns null string on failure. Buffer should be at least 32B long.
- */
-extern char *prom_nextprop(int node, const char *prev_property, char *buffer);
-
-/* Returns 1 if the specified node has given property. */
-extern int prom_node_has_property(int node, const char *property);
-
-/* Returns phandle of the path specified */
-extern int prom_finddevice(const char *name);
-
-/* Set the indicated property at the given node with the passed value.
- * Returns the number of bytes of your value that the prom took.
- */
-extern int prom_setprop(int node, const char *prop_name, char *prop_value,
- int value_size);
-
-extern int prom_pathtoinode(const char *path);
-extern int prom_inst2pkg(int);
-extern int prom_service_exists(const char *service_name);
-extern void prom_sun4v_guest_soft_state(void);
-
-extern int prom_ihandle2path(int handle, char *buffer, int bufsize);
-
-/* Client interface level routines. */
-extern long p1275_cmd(const char *, long, ...);
-
-#if 0
-#define P1275_SIZE(x) ((((long)((x) / 32)) << 32) | (x))
-#else
-#define P1275_SIZE(x) x
-#endif
-
-/* We support at most 16 input and 1 output argument */
-#define P1275_ARG_NUMBER 0
-#define P1275_ARG_IN_STRING 1
-#define P1275_ARG_OUT_BUF 2
-#define P1275_ARG_OUT_32B 3
-#define P1275_ARG_IN_FUNCTION 4
-#define P1275_ARG_IN_BUF 5
-#define P1275_ARG_IN_64B 6
-
-#define P1275_IN(x) ((x) & 0xf)
-#define P1275_OUT(x) (((x) << 4) & 0xf0)
-#define P1275_INOUT(i,o) (P1275_IN(i)|P1275_OUT(o))
-#define P1275_ARG(n,x) ((x) << ((n)*3 + 8))
-
-#endif /* !(__SPARC64_OPLIB_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_PAGE_H
-#define ___ASM_SPARC_PAGE_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/page_64.h>
-#else
-#include <asm-sparc/page_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * page.h: Various defines and such for MMU operations on the Sparc for
- * the Linux kernel.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_PAGE_H
-#define _SPARC_PAGE_H
-
-#ifdef CONFIG_SUN4
-#define PAGE_SHIFT 13
-#else
-#define PAGE_SHIFT 12
-#endif
-#ifndef __ASSEMBLY__
-/* I have my suspicions... -DaveM */
-#define PAGE_SIZE (1UL << PAGE_SHIFT)
-#else
-#define PAGE_SIZE (1 << PAGE_SHIFT)
-#endif
-#define PAGE_MASK (~(PAGE_SIZE-1))
-
-#include <asm/btfixup.h>
-
-#ifndef __ASSEMBLY__
-
-#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
-#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE)
-#define clear_user_page(addr, vaddr, page) \
- do { clear_page(addr); \
- sparc_flush_page_to_ram(page); \
- } while (0)
-#define copy_user_page(to, from, vaddr, page) \
- do { copy_page(to, from); \
- sparc_flush_page_to_ram(page); \
- } while (0)
-
-/* The following structure is used to hold the physical
- * memory configuration of the machine. This is filled in
- * prom_meminit() and is later used by mem_init() to set up
- * mem_map[]. We statically allocate SPARC_PHYS_BANKS+1 of
- * these structs, this is arbitrary. The entry after the
- * last valid one has num_bytes==0.
- */
-struct sparc_phys_banks {
- unsigned long base_addr;
- unsigned long num_bytes;
-};
-
-#define SPARC_PHYS_BANKS 32
-
-extern struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1];
-
-/* Cache alias structure. Entry is valid if context != -1. */
-struct cache_palias {
- unsigned long vaddr;
- int context;
-};
-
-/* passing structs on the Sparc slow us down tremendously... */
-
-/* #define STRICT_MM_TYPECHECKS */
-
-#ifdef STRICT_MM_TYPECHECKS
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long iopte; } iopte_t;
-typedef struct { unsigned long pmdv[16]; } pmd_t;
-typedef struct { unsigned long pgd; } pgd_t;
-typedef struct { unsigned long ctxd; } ctxd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct { unsigned long iopgprot; } iopgprot_t;
-
-#define pte_val(x) ((x).pte)
-#define iopte_val(x) ((x).iopte)
-#define pmd_val(x) ((x).pmdv[0])
-#define pgd_val(x) ((x).pgd)
-#define ctxd_val(x) ((x).ctxd)
-#define pgprot_val(x) ((x).pgprot)
-#define iopgprot_val(x) ((x).iopgprot)
-
-#define __pte(x) ((pte_t) { (x) } )
-#define __iopte(x) ((iopte_t) { (x) } )
-/* #define __pmd(x) ((pmd_t) { (x) } ) */ /* XXX procedure with loop */
-#define __pgd(x) ((pgd_t) { (x) } )
-#define __ctxd(x) ((ctxd_t) { (x) } )
-#define __pgprot(x) ((pgprot_t) { (x) } )
-#define __iopgprot(x) ((iopgprot_t) { (x) } )
-
-#else
-/*
- * .. while these make it easier on the compiler
- */
-typedef unsigned long pte_t;
-typedef unsigned long iopte_t;
-typedef struct { unsigned long pmdv[16]; } pmd_t;
-typedef unsigned long pgd_t;
-typedef unsigned long ctxd_t;
-typedef unsigned long pgprot_t;
-typedef unsigned long iopgprot_t;
-
-#define pte_val(x) (x)
-#define iopte_val(x) (x)
-#define pmd_val(x) ((x).pmdv[0])
-#define pgd_val(x) (x)
-#define ctxd_val(x) (x)
-#define pgprot_val(x) (x)
-#define iopgprot_val(x) (x)
-
-#define __pte(x) (x)
-#define __iopte(x) (x)
-/* #define __pmd(x) (x) */ /* XXX later */
-#define __pgd(x) (x)
-#define __ctxd(x) (x)
-#define __pgprot(x) (x)
-#define __iopgprot(x) (x)
-
-#endif
-
-typedef struct page *pgtable_t;
-
-extern unsigned long sparc_unmapped_base;
-
-BTFIXUPDEF_SETHI(sparc_unmapped_base)
-
-#define TASK_UNMAPPED_BASE BTFIXUP_SETHI(sparc_unmapped_base)
-
-#else /* !(__ASSEMBLY__) */
-
-#define __pgprot(x) (x)
-
-#endif /* !(__ASSEMBLY__) */
-
-#define PAGE_OFFSET 0xf0000000
-#ifndef __ASSEMBLY__
-extern unsigned long phys_base;
-extern unsigned long pfn_base;
-#endif
-#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + phys_base)
-#define __va(x) ((void *)((unsigned long) (x) - phys_base + PAGE_OFFSET))
-
-#define virt_to_phys __pa
-#define phys_to_virt __va
-
-#define ARCH_PFN_OFFSET (pfn_base)
-#define virt_to_page(kaddr) (mem_map + ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT)))
-
-#define pfn_valid(pfn) (((pfn) >= (pfn_base)) && (((pfn)-(pfn_base)) < max_mapnr))
-#define virt_addr_valid(kaddr) ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT) < max_mapnr)
-
-#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/page.h>
-
-#endif /* _SPARC_PAGE_H */
+++ /dev/null
-#ifndef _SPARC64_PAGE_H
-#define _SPARC64_PAGE_H
-
-#include <linux/const.h>
-
-#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
-#define PAGE_SHIFT 13
-#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
-#define PAGE_SHIFT 16
-#else
-#error No page size specified in kernel configuration
-#endif
-
-#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK (~(PAGE_SIZE-1))
-
-/* Flushing for D-cache alias handling is only needed if
- * the page size is smaller than 16K.
- */
-#if PAGE_SHIFT < 14
-#define DCACHE_ALIASING_POSSIBLE
-#endif
-
-#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
-#define HPAGE_SHIFT 22
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
-#define HPAGE_SHIFT 19
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
-#define HPAGE_SHIFT 16
-#endif
-
-#ifdef CONFIG_HUGETLB_PAGE
-#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
-#define HPAGE_MASK (~(HPAGE_SIZE - 1UL))
-#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
-#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
-#endif
-
-#ifndef __ASSEMBLY__
-
-extern void _clear_page(void *page);
-#define clear_page(X) _clear_page((void *)(X))
-struct page;
-extern void clear_user_page(void *addr, unsigned long vaddr, struct page *page);
-#define copy_page(X,Y) memcpy((void *)(X), (void *)(Y), PAGE_SIZE)
-extern void copy_user_page(void *to, void *from, unsigned long vaddr, struct page *topage);
-
-/* Unlike sparc32, sparc64's parameter passing API is more
- * sane in that structures which as small enough are passed
- * in registers instead of on the stack. Thus, setting
- * STRICT_MM_TYPECHECKS does not generate worse code so
- * let's enable it to get the type checking.
- */
-
-#define STRICT_MM_TYPECHECKS
-
-#ifdef STRICT_MM_TYPECHECKS
-/* These are used to make use of C type-checking.. */
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long iopte; } iopte_t;
-typedef struct { unsigned int pmd; } pmd_t;
-typedef struct { unsigned int pgd; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-
-#define pte_val(x) ((x).pte)
-#define iopte_val(x) ((x).iopte)
-#define pmd_val(x) ((x).pmd)
-#define pgd_val(x) ((x).pgd)
-#define pgprot_val(x) ((x).pgprot)
-
-#define __pte(x) ((pte_t) { (x) } )
-#define __iopte(x) ((iopte_t) { (x) } )
-#define __pmd(x) ((pmd_t) { (x) } )
-#define __pgd(x) ((pgd_t) { (x) } )
-#define __pgprot(x) ((pgprot_t) { (x) } )
-
-#else
-/* .. while these make it easier on the compiler */
-typedef unsigned long pte_t;
-typedef unsigned long iopte_t;
-typedef unsigned int pmd_t;
-typedef unsigned int pgd_t;
-typedef unsigned long pgprot_t;
-
-#define pte_val(x) (x)
-#define iopte_val(x) (x)
-#define pmd_val(x) (x)
-#define pgd_val(x) (x)
-#define pgprot_val(x) (x)
-
-#define __pte(x) (x)
-#define __iopte(x) (x)
-#define __pmd(x) (x)
-#define __pgd(x) (x)
-#define __pgprot(x) (x)
-
-#endif /* (STRICT_MM_TYPECHECKS) */
-
-typedef struct page *pgtable_t;
-
-#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_32BIT) ? \
- (_AC(0x0000000070000000,UL)) : \
- (_AC(0xfffff80000000000,UL) + (1UL << 32UL)))
-
-#include <asm-generic/memory_model.h>
-
-#endif /* !(__ASSEMBLY__) */
-
-/* We used to stick this into a hard-coded global register (%g4)
- * but that does not make sense anymore.
- */
-#define PAGE_OFFSET _AC(0xFFFFF80000000000,UL)
-
-#ifndef __ASSEMBLY__
-
-#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
-#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
-
-#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
-
-#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr)>>PAGE_SHIFT)
-
-#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
-
-#define virt_to_phys __pa
-#define phys_to_virt __va
-
-#endif /* !(__ASSEMBLY__) */
-
-#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/page.h>
-
-#endif /* _SPARC64_PAGE_H */
+++ /dev/null
-#ifndef _ASMSPARC_PARAM_H
-#define _ASMSPARC_PARAM_H
-
-#ifdef __KERNEL__
-# define HZ CONFIG_HZ /* Internal kernel timer frequency */
-# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
-# define CLOCKS_PER_SEC (USER_HZ)
-#endif
-
-#ifndef HZ
-#define HZ 100
-#endif
-
-#define EXEC_PAGESIZE 8192 /* Thanks for sun4's we carry baggage... */
-
-#ifndef NOGROUP
-#define NOGROUP (-1)
-#endif
-
-#define MAXHOSTNAMELEN 64 /* max length of hostname */
-
-#endif
+++ /dev/null
-/* parport.h: sparc64 specific parport initialization and dma.
- *
- * Copyright (C) 1999 Eddie C. Dost (ecd@skynet.be)
- */
-
-#ifndef _ASM_SPARC64_PARPORT_H
-#define _ASM_SPARC64_PARPORT_H 1
-
-#include <asm/ebus.h>
-#include <asm/ns87303.h>
-#include <asm/of_device.h>
-#include <asm/prom.h>
-
-#define PARPORT_PC_MAX_PORTS PARPORT_MAX
-
-/*
- * While sparc64 doesn't have an ISA DMA API, we provide something that looks
- * close enough to make parport_pc happy
- */
-#define HAS_DMA
-
-static DEFINE_SPINLOCK(dma_spin_lock);
-
-#define claim_dma_lock() \
-({ unsigned long flags; \
- spin_lock_irqsave(&dma_spin_lock, flags); \
- flags; \
-})
-
-#define release_dma_lock(__flags) \
- spin_unlock_irqrestore(&dma_spin_lock, __flags);
-
-static struct sparc_ebus_info {
- struct ebus_dma_info info;
- unsigned int addr;
- unsigned int count;
- int lock;
-
- struct parport *port;
-} sparc_ebus_dmas[PARPORT_PC_MAX_PORTS];
-
-static DECLARE_BITMAP(dma_slot_map, PARPORT_PC_MAX_PORTS);
-
-static inline int request_dma(unsigned int dmanr, const char *device_id)
-{
- if (dmanr >= PARPORT_PC_MAX_PORTS)
- return -EINVAL;
- if (xchg(&sparc_ebus_dmas[dmanr].lock, 1) != 0)
- return -EBUSY;
- return 0;
-}
-
-static inline void free_dma(unsigned int dmanr)
-{
- if (dmanr >= PARPORT_PC_MAX_PORTS) {
- printk(KERN_WARNING "Trying to free DMA%d\n", dmanr);
- return;
- }
- if (xchg(&sparc_ebus_dmas[dmanr].lock, 0) == 0) {
- printk(KERN_WARNING "Trying to free free DMA%d\n", dmanr);
- return;
- }
-}
-
-static inline void enable_dma(unsigned int dmanr)
-{
- ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 1);
-
- if (ebus_dma_request(&sparc_ebus_dmas[dmanr].info,
- sparc_ebus_dmas[dmanr].addr,
- sparc_ebus_dmas[dmanr].count))
- BUG();
-}
-
-static inline void disable_dma(unsigned int dmanr)
-{
- ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 0);
-}
-
-static inline void clear_dma_ff(unsigned int dmanr)
-{
- /* nothing */
-}
-
-static inline void set_dma_mode(unsigned int dmanr, char mode)
-{
- ebus_dma_prepare(&sparc_ebus_dmas[dmanr].info, (mode != DMA_MODE_WRITE));
-}
-
-static inline void set_dma_addr(unsigned int dmanr, unsigned int addr)
-{
- sparc_ebus_dmas[dmanr].addr = addr;
-}
-
-static inline void set_dma_count(unsigned int dmanr, unsigned int count)
-{
- sparc_ebus_dmas[dmanr].count = count;
-}
-
-static inline unsigned int get_dma_residue(unsigned int dmanr)
-{
- return ebus_dma_residue(&sparc_ebus_dmas[dmanr].info);
-}
-
-static int __devinit ecpp_probe(struct of_device *op, const struct of_device_id *match)
-{
- unsigned long base = op->resource[0].start;
- unsigned long config = op->resource[1].start;
- unsigned long d_base = op->resource[2].start;
- unsigned long d_len;
- struct device_node *parent;
- struct parport *p;
- int slot, err;
-
- parent = op->node->parent;
- if (!strcmp(parent->name, "dma")) {
- p = parport_pc_probe_port(base, base + 0x400,
- op->irqs[0], PARPORT_DMA_NOFIFO,
- op->dev.parent->parent);
- if (!p)
- return -ENOMEM;
- dev_set_drvdata(&op->dev, p);
- return 0;
- }
-
- for (slot = 0; slot < PARPORT_PC_MAX_PORTS; slot++) {
- if (!test_and_set_bit(slot, dma_slot_map))
- break;
- }
- err = -ENODEV;
- if (slot >= PARPORT_PC_MAX_PORTS)
- goto out_err;
-
- spin_lock_init(&sparc_ebus_dmas[slot].info.lock);
-
- d_len = (op->resource[2].end - d_base) + 1UL;
- sparc_ebus_dmas[slot].info.regs =
- of_ioremap(&op->resource[2], 0, d_len, "ECPP DMA");
-
- if (!sparc_ebus_dmas[slot].info.regs)
- goto out_clear_map;
-
- sparc_ebus_dmas[slot].info.flags = 0;
- sparc_ebus_dmas[slot].info.callback = NULL;
- sparc_ebus_dmas[slot].info.client_cookie = NULL;
- sparc_ebus_dmas[slot].info.irq = 0xdeadbeef;
- strcpy(sparc_ebus_dmas[slot].info.name, "parport");
- if (ebus_dma_register(&sparc_ebus_dmas[slot].info))
- goto out_unmap_regs;
-
- ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 1);
-
- /* Configure IRQ to Push Pull, Level Low */
- /* Enable ECP, set bit 2 of the CTR first */
- outb(0x04, base + 0x02);
- ns87303_modify(config, PCR,
- PCR_EPP_ENABLE |
- PCR_IRQ_ODRAIN,
- PCR_ECP_ENABLE |
- PCR_ECP_CLK_ENA |
- PCR_IRQ_POLAR);
-
- /* CTR bit 5 controls direction of port */
- ns87303_modify(config, PTR,
- 0, PTR_LPT_REG_DIR);
-
- p = parport_pc_probe_port(base, base + 0x400,
- op->irqs[0],
- slot,
- op->dev.parent);
- err = -ENOMEM;
- if (!p)
- goto out_disable_irq;
-
- dev_set_drvdata(&op->dev, p);
-
- return 0;
-
-out_disable_irq:
- ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 0);
- ebus_dma_unregister(&sparc_ebus_dmas[slot].info);
-
-out_unmap_regs:
- of_iounmap(&op->resource[2], sparc_ebus_dmas[slot].info.regs, d_len);
-
-out_clear_map:
- clear_bit(slot, dma_slot_map);
-
-out_err:
- return err;
-}
-
-static int __devexit ecpp_remove(struct of_device *op)
-{
- struct parport *p = dev_get_drvdata(&op->dev);
- int slot = p->dma;
-
- parport_pc_unregister_port(p);
-
- if (slot != PARPORT_DMA_NOFIFO) {
- unsigned long d_base = op->resource[2].start;
- unsigned long d_len;
-
- d_len = (op->resource[2].end - d_base) + 1UL;
-
- ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 0);
- ebus_dma_unregister(&sparc_ebus_dmas[slot].info);
- of_iounmap(&op->resource[2],
- sparc_ebus_dmas[slot].info.regs,
- d_len);
- clear_bit(slot, dma_slot_map);
- }
-
- return 0;
-}
-
-static struct of_device_id ecpp_match[] = {
- {
- .name = "ecpp",
- },
- {
- .name = "parallel",
- .compatible = "ecpp",
- },
- {
- .name = "parallel",
- .compatible = "ns87317-ecpp",
- },
- {},
-};
-
-static struct of_platform_driver ecpp_driver = {
- .name = "ecpp",
- .match_table = ecpp_match,
- .probe = ecpp_probe,
- .remove = __devexit_p(ecpp_remove),
-};
-
-static int parport_pc_find_nonpci_ports(int autoirq, int autodma)
-{
- of_register_driver(&ecpp_driver, &of_bus_type);
-
- return 0;
-}
-
-#endif /* !(_ASM_SPARC64_PARPORT_H */
+++ /dev/null
-/*
- *
- * pbm.h: PCI bus module pseudo driver software state
- * Adopted from sparc64 by V. Roganov and G. Raiko
- *
- * Original header:
- * pbm.h: U2P PCI bus module pseudo driver software state.
- *
- * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
- *
- * To put things into perspective, consider sparc64 with a few PCI controllers.
- * Each type would have an own structure, with instances related one to one.
- * We have only pcic on sparc, but we want to be compatible with sparc64 pbm.h.
- * All three represent different abstractions.
- * pci_bus - Linux PCI subsystem view of a PCI bus (including bridged buses)
- * pbm - Arch-specific view of a PCI bus (sparc or sparc64)
- * pcic - Chip-specific information for PCIC.
- */
-
-#ifndef __SPARC_PBM_H
-#define __SPARC_PBM_H
-
-#include <linux/pci.h>
-#include <asm/oplib.h>
-#include <asm/prom.h>
-
-struct linux_pbm_info {
- int prom_node;
- char prom_name[64];
- /* struct linux_prom_pci_ranges pbm_ranges[PROMREG_MAX]; */
- /* int num_pbm_ranges; */
-
- /* Now things for the actual PCI bus probes. */
- unsigned int pci_first_busno; /* Can it be nonzero? */
- struct pci_bus *pci_bus; /* Was inline, MJ allocs now */
-};
-
-/* PCI devices which are not bridges have this placed in their pci_dev
- * sysdata member. This makes OBP aware PCI device drivers easier to
- * code.
- */
-struct pcidev_cookie {
- struct linux_pbm_info *pbm;
- struct device_node *prom_node;
-};
-
-#endif /* !(__SPARC_PBM_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_PCI_H
-#define ___ASM_SPARC_PCI_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/pci_64.h>
-#else
-#include <asm-sparc/pci_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef __SPARC_PCI_H
-#define __SPARC_PCI_H
-
-#ifdef __KERNEL__
-
-/* Can be used to override the logic in pci_scan_bus for skipping
- * already-configured bus numbers - to be used for buggy BIOSes
- * or architectures with incomplete PCI setup by the loader.
- */
-#define pcibios_assign_all_busses() 0
-#define pcibios_scan_all_fns(a, b) 0
-
-#define PCIBIOS_MIN_IO 0UL
-#define PCIBIOS_MIN_MEM 0UL
-
-#define PCI_IRQ_NONE 0xffffffff
-
-static inline void pcibios_set_master(struct pci_dev *dev)
-{
- /* No special bus mastering setup handling */
-}
-
-static inline void pcibios_penalize_isa_irq(int irq, int active)
-{
- /* We don't do dynamic PCI IRQ allocation */
-}
-
-/* Dynamic DMA mapping stuff.
- */
-#define PCI_DMA_BUS_IS_PHYS (0)
-
-#include <asm/scatterlist.h>
-
-struct pci_dev;
-
-/* Allocate and map kernel buffer using consistent mode DMA for a device.
- * hwdev should be valid struct pci_dev pointer for PCI devices.
- */
-extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle);
-
-/* Free and unmap a consistent DMA buffer.
- * cpu_addr is what was returned from pci_alloc_consistent,
- * size must be the same as what as passed into pci_alloc_consistent,
- * and likewise dma_addr must be the same as what *dma_addrp was set to.
- *
- * References to the memory and mappings assosciated with cpu_addr/dma_addr
- * past this call are illegal.
- */
-extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle);
-
-/* Map a single buffer of the indicated size for DMA in streaming mode.
- * The 32-bit bus address to use is returned.
- *
- * Once the device is given the dma address, the device owns this memory
- * until either pci_unmap_single or pci_dma_sync_single_for_cpu is performed.
- */
-extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction);
-
-/* Unmap a single streaming mode DMA translation. The dma_addr and size
- * must match what was provided for in a previous pci_map_single call. All
- * other usages are undefined.
- *
- * After this call, reads by the cpu to the buffer are guaranteed to see
- * whatever the device wrote there.
- */
-extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction);
-
-/* pci_unmap_{single,page} is not a nop, thus... */
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
- dma_addr_t ADDR_NAME;
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
- __u32 LEN_NAME;
-#define pci_unmap_addr(PTR, ADDR_NAME) \
- ((PTR)->ADDR_NAME)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
- (((PTR)->ADDR_NAME) = (VAL))
-#define pci_unmap_len(PTR, LEN_NAME) \
- ((PTR)->LEN_NAME)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
- (((PTR)->LEN_NAME) = (VAL))
-
-/*
- * Same as above, only with pages instead of mapped addresses.
- */
-extern dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page,
- unsigned long offset, size_t size, int direction);
-extern void pci_unmap_page(struct pci_dev *hwdev,
- dma_addr_t dma_address, size_t size, int direction);
-
-/* Map a set of buffers described by scatterlist in streaming
- * mode for DMA. This is the scather-gather version of the
- * above pci_map_single interface. Here the scatter gather list
- * elements are each tagged with the appropriate dma address
- * and length. They are obtained via sg_dma_{address,length}(SG).
- *
- * NOTE: An implementation may be able to use a smaller number of
- * DMA address/length pairs than there are SG table elements.
- * (for example via virtual mapping capabilities)
- * The routine returns the number of addr/length pairs actually
- * used, at most nents.
- *
- * Device ownership issues as mentioned above for pci_map_single are
- * the same here.
- */
-extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction);
-
-/* Unmap a set of streaming mode DMA translations.
- * Again, cpu read rules concerning calls here are the same as for
- * pci_unmap_single() above.
- */
-extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nhwents, int direction);
-
-/* Make physical memory consistent for a single
- * streaming mode DMA translation after a transfer.
- *
- * If you perform a pci_map_single() but wish to interrogate the
- * buffer using the cpu, yet do not wish to teardown the PCI dma
- * mapping, you must call this function before doing so. At the
- * next point you give the PCI dma address back to the card, you
- * must first perform a pci_dma_sync_for_device, and then the device
- * again owns the buffer.
- */
-extern void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
-extern void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
-
-/* Make physical memory consistent for a set of streaming
- * mode DMA translations after a transfer.
- *
- * The same as pci_dma_sync_single_* but for a scatter-gather list,
- * same rules and usage.
- */
-extern void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
-extern void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
-
-/* Return whether the given PCI device DMA address mask can
- * be supported properly. For example, if your device can
- * only drive the low 24-bits during PCI bus mastering, then
- * you would pass 0x00ffffff as the mask to this function.
- */
-static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
-{
- return 1;
-}
-
-#ifdef CONFIG_PCI
-static inline void pci_dma_burst_advice(struct pci_dev *pdev,
- enum pci_dma_burst_strategy *strat,
- unsigned long *strategy_parameter)
-{
- *strat = PCI_DMA_BURST_INFINITY;
- *strategy_parameter = ~0UL;
-}
-#endif
-
-#define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0)
-
-static inline int pci_dma_mapping_error(struct pci_dev *pdev,
- dma_addr_t dma_addr)
-{
- return (dma_addr == PCI_DMA_ERROR_CODE);
-}
-
-struct device_node;
-extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
-
-#endif /* __KERNEL__ */
-
-/* generic pci stuff */
-#include <asm-generic/pci.h>
-
-#endif /* __SPARC_PCI_H */
+++ /dev/null
-#ifndef __SPARC64_PCI_H
-#define __SPARC64_PCI_H
-
-#ifdef __KERNEL__
-
-#include <linux/dma-mapping.h>
-
-/* Can be used to override the logic in pci_scan_bus for skipping
- * already-configured bus numbers - to be used for buggy BIOSes
- * or architectures with incomplete PCI setup by the loader.
- */
-#define pcibios_assign_all_busses() 0
-#define pcibios_scan_all_fns(a, b) 0
-
-#define PCIBIOS_MIN_IO 0UL
-#define PCIBIOS_MIN_MEM 0UL
-
-#define PCI_IRQ_NONE 0xffffffff
-
-#define PCI_CACHE_LINE_BYTES 64
-
-static inline void pcibios_set_master(struct pci_dev *dev)
-{
- /* No special bus mastering setup handling */
-}
-
-static inline void pcibios_penalize_isa_irq(int irq, int active)
-{
- /* We don't do dynamic PCI IRQ allocation */
-}
-
-/* The PCI address space does not equal the physical memory
- * address space. The networking and block device layers use
- * this boolean for bounce buffer decisions.
- */
-#define PCI_DMA_BUS_IS_PHYS (0)
-
-static inline void *pci_alloc_consistent(struct pci_dev *pdev, size_t size,
- dma_addr_t *dma_handle)
-{
- return dma_alloc_coherent(&pdev->dev, size, dma_handle, GFP_ATOMIC);
-}
-
-static inline void pci_free_consistent(struct pci_dev *pdev, size_t size,
- void *vaddr, dma_addr_t dma_handle)
-{
- return dma_free_coherent(&pdev->dev, size, vaddr, dma_handle);
-}
-
-static inline dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr,
- size_t size, int direction)
-{
- return dma_map_single(&pdev->dev, ptr, size,
- (enum dma_data_direction) direction);
-}
-
-static inline void pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr,
- size_t size, int direction)
-{
- dma_unmap_single(&pdev->dev, dma_addr, size,
- (enum dma_data_direction) direction);
-}
-
-#define pci_map_page(dev, page, off, size, dir) \
- pci_map_single(dev, (page_address(page) + (off)), size, dir)
-#define pci_unmap_page(dev,addr,sz,dir) \
- pci_unmap_single(dev,addr,sz,dir)
-
-/* pci_unmap_{single,page} is not a nop, thus... */
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
- dma_addr_t ADDR_NAME;
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
- __u32 LEN_NAME;
-#define pci_unmap_addr(PTR, ADDR_NAME) \
- ((PTR)->ADDR_NAME)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
- (((PTR)->ADDR_NAME) = (VAL))
-#define pci_unmap_len(PTR, LEN_NAME) \
- ((PTR)->LEN_NAME)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
- (((PTR)->LEN_NAME) = (VAL))
-
-static inline int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sg,
- int nents, int direction)
-{
- return dma_map_sg(&pdev->dev, sg, nents,
- (enum dma_data_direction) direction);
-}
-
-static inline void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sg,
- int nents, int direction)
-{
- dma_unmap_sg(&pdev->dev, sg, nents,
- (enum dma_data_direction) direction);
-}
-
-static inline void pci_dma_sync_single_for_cpu(struct pci_dev *pdev,
- dma_addr_t dma_handle,
- size_t size, int direction)
-{
- dma_sync_single_for_cpu(&pdev->dev, dma_handle, size,
- (enum dma_data_direction) direction);
-}
-
-static inline void pci_dma_sync_single_for_device(struct pci_dev *pdev,
- dma_addr_t dma_handle,
- size_t size, int direction)
-{
- /* No flushing needed to sync cpu writes to the device. */
-}
-
-static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev,
- struct scatterlist *sg,
- int nents, int direction)
-{
- dma_sync_sg_for_cpu(&pdev->dev, sg, nents,
- (enum dma_data_direction) direction);
-}
-
-static inline void pci_dma_sync_sg_for_device(struct pci_dev *pdev,
- struct scatterlist *sg,
- int nelems, int direction)
-{
- /* No flushing needed to sync cpu writes to the device. */
-}
-
-/* Return whether the given PCI device DMA address mask can
- * be supported properly. For example, if your device can
- * only drive the low 24-bits during PCI bus mastering, then
- * you would pass 0x00ffffff as the mask to this function.
- */
-extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
-
-/* PCI IOMMU mapping bypass support. */
-
-/* PCI 64-bit addressing works for all slots on all controller
- * types on sparc64. However, it requires that the device
- * can drive enough of the 64 bits.
- */
-#define PCI64_REQUIRED_MASK (~(dma64_addr_t)0)
-#define PCI64_ADDR_BASE 0xfffc000000000000UL
-
-static inline int pci_dma_mapping_error(struct pci_dev *pdev,
- dma_addr_t dma_addr)
-{
- return dma_mapping_error(&pdev->dev, dma_addr);
-}
-
-#ifdef CONFIG_PCI
-static inline void pci_dma_burst_advice(struct pci_dev *pdev,
- enum pci_dma_burst_strategy *strat,
- unsigned long *strategy_parameter)
-{
- unsigned long cacheline_size;
- u8 byte;
-
- pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
- if (byte == 0)
- cacheline_size = 1024;
- else
- cacheline_size = (int) byte * 4;
-
- *strat = PCI_DMA_BURST_BOUNDARY;
- *strategy_parameter = cacheline_size;
-}
-#endif
-
-/* Return the index of the PCI controller for device PDEV. */
-
-extern int pci_domain_nr(struct pci_bus *bus);
-static inline int pci_proc_domain(struct pci_bus *bus)
-{
- return 1;
-}
-
-/* Platform support for /proc/bus/pci/X/Y mmap()s. */
-
-#define HAVE_PCI_MMAP
-#define HAVE_ARCH_PCI_GET_UNMAPPED_AREA
-#define get_pci_unmapped_area get_fb_unmapped_area
-
-extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
- enum pci_mmap_state mmap_state,
- int write_combine);
-
-extern void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
- struct resource *res);
-
-extern void
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
- struct pci_bus_region *region);
-
-extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *);
-
-static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
-{
- return PCI_IRQ_NONE;
-}
-
-struct device_node;
-extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
-
-#define HAVE_ARCH_PCI_RESOURCE_TO_USER
-extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
- const struct resource *rsrc,
- resource_size_t *start, resource_size_t *end);
-#endif /* __KERNEL__ */
-
-#endif /* __SPARC64_PCI_H */
+++ /dev/null
-/*
- * pcic.h: JavaEngine 1 specific PCI definitions.
- *
- * Copyright (C) 1998 V. Roganov and G. Raiko
- */
-
-#ifndef __SPARC_PCIC_H
-#define __SPARC_PCIC_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-#include <linux/smp.h>
-#include <linux/pci.h>
-#include <linux/ioport.h>
-#include <asm/pbm.h>
-
-struct linux_pcic {
- void __iomem *pcic_regs;
- unsigned long pcic_io;
- void __iomem *pcic_config_space_addr;
- void __iomem *pcic_config_space_data;
- struct resource pcic_res_regs;
- struct resource pcic_res_io;
- struct resource pcic_res_cfg_addr;
- struct resource pcic_res_cfg_data;
- struct linux_pbm_info pbm;
- struct pcic_ca2irq *pcic_imap;
- int pcic_imdim;
-};
-
-extern int pcic_probe(void);
-/* Erm... MJ redefined pcibios_present() so that it does not work early. */
-extern int pcic_present(void);
-extern void sun4m_pci_init_IRQ(void);
-
-#endif
-
-/* Size of PCI I/O space which we relocate. */
-#define PCI_SPACE_SIZE 0x1000000 /* 16 MB */
-
-/* PCIC Register Set. */
-#define PCI_DIAGNOSTIC_0 0x40 /* 32 bits */
-#define PCI_SIZE_0 0x44 /* 32 bits */
-#define PCI_SIZE_1 0x48 /* 32 bits */
-#define PCI_SIZE_2 0x4c /* 32 bits */
-#define PCI_SIZE_3 0x50 /* 32 bits */
-#define PCI_SIZE_4 0x54 /* 32 bits */
-#define PCI_SIZE_5 0x58 /* 32 bits */
-#define PCI_PIO_CONTROL 0x60 /* 8 bits */
-#define PCI_DVMA_CONTROL 0x62 /* 8 bits */
-#define PCI_DVMA_CONTROL_INACTIVITY_REQ (1<<0)
-#define PCI_DVMA_CONTROL_IOTLB_ENABLE (1<<0)
-#define PCI_DVMA_CONTROL_IOTLB_DISABLE 0
-#define PCI_DVMA_CONTROL_INACTIVITY_ACK (1<<4)
-#define PCI_INTERRUPT_CONTROL 0x63 /* 8 bits */
-#define PCI_CPU_INTERRUPT_PENDING 0x64 /* 32 bits */
-#define PCI_DIAGNOSTIC_1 0x68 /* 16 bits */
-#define PCI_SOFTWARE_INT_CLEAR 0x6a /* 16 bits */
-#define PCI_SOFTWARE_INT_SET 0x6e /* 16 bits */
-#define PCI_SYS_INT_PENDING 0x70 /* 32 bits */
-#define PCI_SYS_INT_PENDING_PIO 0x40000000
-#define PCI_SYS_INT_PENDING_DMA 0x20000000
-#define PCI_SYS_INT_PENDING_PCI 0x10000000
-#define PCI_SYS_INT_PENDING_APSR 0x08000000
-#define PCI_SYS_INT_TARGET_MASK 0x74 /* 32 bits */
-#define PCI_SYS_INT_TARGET_MASK_CLEAR 0x78 /* 32 bits */
-#define PCI_SYS_INT_TARGET_MASK_SET 0x7c /* 32 bits */
-#define PCI_SYS_INT_PENDING_CLEAR 0x83 /* 8 bits */
-#define PCI_SYS_INT_PENDING_CLEAR_ALL 0x80
-#define PCI_SYS_INT_PENDING_CLEAR_PIO 0x40
-#define PCI_SYS_INT_PENDING_CLEAR_DMA 0x20
-#define PCI_SYS_INT_PENDING_CLEAR_PCI 0x10
-#define PCI_IOTLB_CONTROL 0x84 /* 8 bits */
-#define PCI_INT_SELECT_LO 0x88 /* 16 bits */
-#define PCI_ARBITRATION_SELECT 0x8a /* 16 bits */
-#define PCI_INT_SELECT_HI 0x8c /* 16 bits */
-#define PCI_HW_INT_OUTPUT 0x8e /* 16 bits */
-#define PCI_IOTLB_RAM_INPUT 0x90 /* 32 bits */
-#define PCI_IOTLB_CAM_INPUT 0x94 /* 32 bits */
-#define PCI_IOTLB_RAM_OUTPUT 0x98 /* 32 bits */
-#define PCI_IOTLB_CAM_OUTPUT 0x9c /* 32 bits */
-#define PCI_SMBAR0 0xa0 /* 8 bits */
-#define PCI_MSIZE0 0xa1 /* 8 bits */
-#define PCI_PMBAR0 0xa2 /* 8 bits */
-#define PCI_SMBAR1 0xa4 /* 8 bits */
-#define PCI_MSIZE1 0xa5 /* 8 bits */
-#define PCI_PMBAR1 0xa6 /* 8 bits */
-#define PCI_SIBAR 0xa8 /* 8 bits */
-#define PCI_SIBAR_ADDRESS_MASK 0xf
-#define PCI_ISIZE 0xa9 /* 8 bits */
-#define PCI_ISIZE_16M 0xf
-#define PCI_ISIZE_32M 0xe
-#define PCI_ISIZE_64M 0xc
-#define PCI_ISIZE_128M 0x8
-#define PCI_ISIZE_256M 0x0
-#define PCI_PIBAR 0xaa /* 8 bits */
-#define PCI_CPU_COUNTER_LIMIT_HI 0xac /* 32 bits */
-#define PCI_CPU_COUNTER_LIMIT_LO 0xb0 /* 32 bits */
-#define PCI_CPU_COUNTER_LIMIT 0xb4 /* 32 bits */
-#define PCI_SYS_LIMIT 0xb8 /* 32 bits */
-#define PCI_SYS_COUNTER 0xbc /* 32 bits */
-#define PCI_SYS_COUNTER_OVERFLOW (1<<31) /* Limit reached */
-#define PCI_SYS_LIMIT_PSEUDO 0xc0 /* 32 bits */
-#define PCI_USER_TIMER_CONTROL 0xc4 /* 8 bits */
-#define PCI_USER_TIMER_CONFIG 0xc5 /* 8 bits */
-#define PCI_COUNTER_IRQ 0xc6 /* 8 bits */
-#define PCI_COUNTER_IRQ_SET(sys_irq, cpu_irq) ((((sys_irq) & 0xf) << 4) | \
- ((cpu_irq) & 0xf))
-#define PCI_COUNTER_IRQ_SYS(v) (((v) >> 4) & 0xf)
-#define PCI_COUNTER_IRQ_CPU(v) ((v) & 0xf)
-#define PCI_PIO_ERROR_COMMAND 0xc7 /* 8 bits */
-#define PCI_PIO_ERROR_ADDRESS 0xc8 /* 32 bits */
-#define PCI_IOTLB_ERROR_ADDRESS 0xcc /* 32 bits */
-#define PCI_SYS_STATUS 0xd0 /* 8 bits */
-#define PCI_SYS_STATUS_RESET_ENABLE (1<<0)
-#define PCI_SYS_STATUS_RESET (1<<1)
-#define PCI_SYS_STATUS_WATCHDOG_RESET (1<<4)
-#define PCI_SYS_STATUS_PCI_RESET (1<<5)
-#define PCI_SYS_STATUS_PCI_RESET_ENABLE (1<<6)
-#define PCI_SYS_STATUS_PCI_SATTELITE_MODE (1<<7)
-
-#endif /* !(__SPARC_PCIC_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_PERCPU_H
-#define ___ASM_SPARC_PERCPU_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/percpu_64.h>
-#else
-#include <asm-sparc/percpu_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef __ARCH_SPARC_PERCPU__
-#define __ARCH_SPARC_PERCPU__
-
-#include <asm-generic/percpu.h>
-
-#endif /* __ARCH_SPARC_PERCPU__ */
+++ /dev/null
-#ifndef __ARCH_SPARC64_PERCPU__
-#define __ARCH_SPARC64_PERCPU__
-
-#include <linux/compiler.h>
-
-register unsigned long __local_per_cpu_offset asm("g5");
-
-#ifdef CONFIG_SMP
-
-extern void real_setup_per_cpu_areas(void);
-
-extern unsigned long __per_cpu_base;
-extern unsigned long __per_cpu_shift;
-#define __per_cpu_offset(__cpu) \
- (__per_cpu_base + ((unsigned long)(__cpu) << __per_cpu_shift))
-#define per_cpu_offset(x) (__per_cpu_offset(x))
-
-#define __my_cpu_offset __local_per_cpu_offset
-
-#else /* ! SMP */
-
-#define real_setup_per_cpu_areas() do { } while (0)
-
-#endif /* SMP */
-
-#include <asm-generic/percpu.h>
-
-#endif /* __ARCH_SPARC64_PERCPU__ */
+++ /dev/null
-/*----------------------------------------
- PERFORMANCE INSTRUMENTATION
- Guillaume Thouvenin 08/10/98
- David S. Miller 10/06/98
- ---------------------------------------*/
-#ifndef PERF_COUNTER_API
-#define PERF_COUNTER_API
-
-/* sys_perfctr() interface. First arg is operation code
- * from enumeration below. The meaning of further arguments
- * are determined by the operation code.
- *
- * int sys_perfctr(int opcode, unsigned long arg0,
- * unsigned long arg1, unsigned long arg2)
- *
- * Pointers which are passed by the user are pointers to 64-bit
- * integers.
- *
- * Once enabled, performance counter state is retained until the
- * process either exits or performs an exec. That is, performance
- * counters remain enabled for fork/clone children.
- */
-enum perfctr_opcode {
- /* Enable UltraSparc performance counters, ARG0 is pointer
- * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
- * to 64-bit accumulator for D1 counter. ARG2 is a pointer to
- * the initial PCR register value to use.
- */
- PERFCTR_ON,
-
- /* Disable UltraSparc performance counters. The PCR is written
- * with zero and the user counter accumulator pointers and
- * working PCR register value are forgotten.
- */
- PERFCTR_OFF,
-
- /* Add current D0 and D1 PIC values into user pointers given
- * in PERFCTR_ON operation. The PIC is cleared before returning.
- */
- PERFCTR_READ,
-
- /* Clear the PIC register. */
- PERFCTR_CLRPIC,
-
- /* Begin using a new PCR value, the pointer to which is passed
- * in ARG0. The PIC is also cleared after the new PCR value is
- * written.
- */
- PERFCTR_SETPCR,
-
- /* Store in pointer given in ARG0 the current PCR register value
- * being used.
- */
- PERFCTR_GETPCR
-};
-
-/* I don't want the kernel's namespace to be polluted with this
- * stuff when this file is included. --DaveM
- */
-#ifndef __KERNEL__
-
-#define PRIV 0x00000001
-#define SYS 0x00000002
-#define USR 0x00000004
-
-/* Pic.S0 Selection Bit Field Encoding, Ultra-I/II */
-#define CYCLE_CNT 0x00000000
-#define INSTR_CNT 0x00000010
-#define DISPATCH0_IC_MISS 0x00000020
-#define DISPATCH0_STOREBUF 0x00000030
-#define IC_REF 0x00000080
-#define DC_RD 0x00000090
-#define DC_WR 0x000000A0
-#define LOAD_USE 0x000000B0
-#define EC_REF 0x000000C0
-#define EC_WRITE_HIT_RDO 0x000000D0
-#define EC_SNOOP_INV 0x000000E0
-#define EC_RD_HIT 0x000000F0
-
-/* Pic.S0 Selection Bit Field Encoding, Ultra-III */
-#define US3_CYCLE_CNT 0x00000000
-#define US3_INSTR_CNT 0x00000010
-#define US3_DISPATCH0_IC_MISS 0x00000020
-#define US3_DISPATCH0_BR_TGT 0x00000030
-#define US3_DISPATCH0_2ND_BR 0x00000040
-#define US3_RSTALL_STOREQ 0x00000050
-#define US3_RSTALL_IU_USE 0x00000060
-#define US3_IC_REF 0x00000080
-#define US3_DC_RD 0x00000090
-#define US3_DC_WR 0x000000a0
-#define US3_EC_REF 0x000000c0
-#define US3_EC_WR_HIT_RTO 0x000000d0
-#define US3_EC_SNOOP_INV 0x000000e0
-#define US3_EC_RD_MISS 0x000000f0
-#define US3_PC_PORT0_RD 0x00000100
-#define US3_SI_SNOOP 0x00000110
-#define US3_SI_CIQ_FLOW 0x00000120
-#define US3_SI_OWNED 0x00000130
-#define US3_SW_COUNT_0 0x00000140
-#define US3_IU_BR_MISS_TAKEN 0x00000150
-#define US3_IU_BR_COUNT_TAKEN 0x00000160
-#define US3_DISP_RS_MISPRED 0x00000170
-#define US3_FA_PIPE_COMPL 0x00000180
-#define US3_MC_READS_0 0x00000200
-#define US3_MC_READS_1 0x00000210
-#define US3_MC_READS_2 0x00000220
-#define US3_MC_READS_3 0x00000230
-#define US3_MC_STALLS_0 0x00000240
-#define US3_MC_STALLS_2 0x00000250
-
-/* Pic.S1 Selection Bit Field Encoding, Ultra-I/II */
-#define CYCLE_CNT_D1 0x00000000
-#define INSTR_CNT_D1 0x00000800
-#define DISPATCH0_IC_MISPRED 0x00001000
-#define DISPATCH0_FP_USE 0x00001800
-#define IC_HIT 0x00004000
-#define DC_RD_HIT 0x00004800
-#define DC_WR_HIT 0x00005000
-#define LOAD_USE_RAW 0x00005800
-#define EC_HIT 0x00006000
-#define EC_WB 0x00006800
-#define EC_SNOOP_CB 0x00007000
-#define EC_IT_HIT 0x00007800
-
-/* Pic.S1 Selection Bit Field Encoding, Ultra-III */
-#define US3_CYCLE_CNT_D1 0x00000000
-#define US3_INSTR_CNT_D1 0x00000800
-#define US3_DISPATCH0_MISPRED 0x00001000
-#define US3_IC_MISS_CANCELLED 0x00001800
-#define US3_RE_ENDIAN_MISS 0x00002000
-#define US3_RE_FPU_BYPASS 0x00002800
-#define US3_RE_DC_MISS 0x00003000
-#define US3_RE_EC_MISS 0x00003800
-#define US3_IC_MISS 0x00004000
-#define US3_DC_RD_MISS 0x00004800
-#define US3_DC_WR_MISS 0x00005000
-#define US3_RSTALL_FP_USE 0x00005800
-#define US3_EC_MISSES 0x00006000
-#define US3_EC_WB 0x00006800
-#define US3_EC_SNOOP_CB 0x00007000
-#define US3_EC_IC_MISS 0x00007800
-#define US3_RE_PC_MISS 0x00008000
-#define US3_ITLB_MISS 0x00008800
-#define US3_DTLB_MISS 0x00009000
-#define US3_WC_MISS 0x00009800
-#define US3_WC_SNOOP_CB 0x0000a000
-#define US3_WC_SCRUBBED 0x0000a800
-#define US3_WC_WB_WO_READ 0x0000b000
-#define US3_PC_SOFT_HIT 0x0000c000
-#define US3_PC_SNOOP_INV 0x0000c800
-#define US3_PC_HARD_HIT 0x0000d000
-#define US3_PC_PORT1_RD 0x0000d800
-#define US3_SW_COUNT_1 0x0000e000
-#define US3_IU_STAT_BR_MIS_UNTAKEN 0x0000e800
-#define US3_IU_STAT_BR_COUNT_UNTAKEN 0x0000f000
-#define US3_PC_MS_MISSES 0x0000f800
-#define US3_MC_WRITES_0 0x00010800
-#define US3_MC_WRITES_1 0x00011000
-#define US3_MC_WRITES_2 0x00011800
-#define US3_MC_WRITES_3 0x00012000
-#define US3_MC_STALLS_1 0x00012800
-#define US3_MC_STALLS_3 0x00013000
-#define US3_RE_RAW_MISS 0x00013800
-#define US3_FM_PIPE_COMPLETION 0x00014000
-
-struct vcounter_struct {
- unsigned long long vcnt0;
- unsigned long long vcnt1;
-};
-
-#endif /* !(__KERNEL__) */
-
-#endif /* !(PERF_COUNTER_API) */
+++ /dev/null
-#ifndef ___ASM_SPARC_PGALLOC_H
-#define ___ASM_SPARC_PGALLOC_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/pgalloc_64.h>
-#else
-#include <asm-sparc/pgalloc_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _SPARC_PGALLOC_H
-#define _SPARC_PGALLOC_H
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-
-#include <asm/page.h>
-#include <asm/btfixup.h>
-
-struct page;
-
-extern struct pgtable_cache_struct {
- unsigned long *pgd_cache;
- unsigned long *pte_cache;
- unsigned long pgtable_cache_sz;
- unsigned long pgd_cache_sz;
-} pgt_quicklists;
-#define pgd_quicklist (pgt_quicklists.pgd_cache)
-#define pmd_quicklist ((unsigned long *)0)
-#define pte_quicklist (pgt_quicklists.pte_cache)
-#define pgtable_cache_size (pgt_quicklists.pgtable_cache_sz)
-#define pgd_cache_size (pgt_quicklists.pgd_cache_sz)
-
-extern void check_pgt_cache(void);
-BTFIXUPDEF_CALL(void, do_check_pgt_cache, int, int)
-#define do_check_pgt_cache(low,high) BTFIXUP_CALL(do_check_pgt_cache)(low,high)
-
-BTFIXUPDEF_CALL(pgd_t *, get_pgd_fast, void)
-#define get_pgd_fast() BTFIXUP_CALL(get_pgd_fast)()
-
-BTFIXUPDEF_CALL(void, free_pgd_fast, pgd_t *)
-#define free_pgd_fast(pgd) BTFIXUP_CALL(free_pgd_fast)(pgd)
-
-#define pgd_free(mm, pgd) free_pgd_fast(pgd)
-#define pgd_alloc(mm) get_pgd_fast()
-
-BTFIXUPDEF_CALL(void, pgd_set, pgd_t *, pmd_t *)
-#define pgd_set(pgdp,pmdp) BTFIXUP_CALL(pgd_set)(pgdp,pmdp)
-#define pgd_populate(MM, PGD, PMD) pgd_set(PGD, PMD)
-
-BTFIXUPDEF_CALL(pmd_t *, pmd_alloc_one, struct mm_struct *, unsigned long)
-#define pmd_alloc_one(mm, address) BTFIXUP_CALL(pmd_alloc_one)(mm, address)
-
-BTFIXUPDEF_CALL(void, free_pmd_fast, pmd_t *)
-#define free_pmd_fast(pmd) BTFIXUP_CALL(free_pmd_fast)(pmd)
-
-#define pmd_free(mm, pmd) free_pmd_fast(pmd)
-#define __pmd_free_tlb(tlb, pmd) pmd_free((tlb)->mm, pmd)
-
-BTFIXUPDEF_CALL(void, pmd_populate, pmd_t *, struct page *)
-#define pmd_populate(MM, PMD, PTE) BTFIXUP_CALL(pmd_populate)(PMD, PTE)
-#define pmd_pgtable(pmd) pmd_page(pmd)
-BTFIXUPDEF_CALL(void, pmd_set, pmd_t *, pte_t *)
-#define pmd_populate_kernel(MM, PMD, PTE) BTFIXUP_CALL(pmd_set)(PMD, PTE)
-
-BTFIXUPDEF_CALL(pgtable_t , pte_alloc_one, struct mm_struct *, unsigned long)
-#define pte_alloc_one(mm, address) BTFIXUP_CALL(pte_alloc_one)(mm, address)
-BTFIXUPDEF_CALL(pte_t *, pte_alloc_one_kernel, struct mm_struct *, unsigned long)
-#define pte_alloc_one_kernel(mm, addr) BTFIXUP_CALL(pte_alloc_one_kernel)(mm, addr)
-
-BTFIXUPDEF_CALL(void, free_pte_fast, pte_t *)
-#define pte_free_kernel(mm, pte) BTFIXUP_CALL(free_pte_fast)(pte)
-
-BTFIXUPDEF_CALL(void, pte_free, pgtable_t )
-#define pte_free(mm, pte) BTFIXUP_CALL(pte_free)(pte)
-#define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, pte)
-
-#endif /* _SPARC_PGALLOC_H */
+++ /dev/null
-#ifndef _SPARC64_PGALLOC_H
-#define _SPARC64_PGALLOC_H
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/quicklist.h>
-
-#include <asm/spitfire.h>
-#include <asm/cpudata.h>
-#include <asm/cacheflush.h>
-#include <asm/page.h>
-
-/* Page table allocation/freeing. */
-
-static inline pgd_t *pgd_alloc(struct mm_struct *mm)
-{
- return quicklist_alloc(0, GFP_KERNEL, NULL);
-}
-
-static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
- quicklist_free(0, NULL, pgd);
-}
-
-#define pud_populate(MM, PUD, PMD) pud_set(PUD, PMD)
-
-static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
-{
- return quicklist_alloc(0, GFP_KERNEL, NULL);
-}
-
-static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
-{
- quicklist_free(0, NULL, pmd);
-}
-
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
- unsigned long address)
-{
- return quicklist_alloc(0, GFP_KERNEL, NULL);
-}
-
-static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
- unsigned long address)
-{
- struct page *page;
- void *pg;
-
- pg = quicklist_alloc(0, GFP_KERNEL, NULL);
- if (!pg)
- return NULL;
- page = virt_to_page(pg);
- pgtable_page_ctor(page);
- return page;
-}
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
- quicklist_free(0, NULL, pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
-{
- pgtable_page_dtor(ptepage);
- quicklist_free_page(0, NULL, ptepage);
-}
-
-
-#define pmd_populate_kernel(MM, PMD, PTE) pmd_set(PMD, PTE)
-#define pmd_populate(MM,PMD,PTE_PAGE) \
- pmd_populate_kernel(MM,PMD,page_address(PTE_PAGE))
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-static inline void check_pgt_cache(void)
-{
- quicklist_trim(0, NULL, 25, 16);
-}
-
-#endif /* _SPARC64_PGALLOC_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_PGTABLE_H
-#define ___ASM_SPARC_PGTABLE_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/pgtable_64.h>
-#else
-#include <asm-sparc/pgtable_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _SPARC_PGTABLE_H
-#define _SPARC_PGTABLE_H
-
-/* asm-sparc/pgtable.h: Defines and functions used to work
- * with Sparc page tables.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-
-#ifndef __ASSEMBLY__
-#include <asm-generic/4level-fixup.h>
-
-#include <linux/spinlock.h>
-#include <linux/swap.h>
-#include <asm/types.h>
-#ifdef CONFIG_SUN4
-#include <asm/pgtsun4.h>
-#else
-#include <asm/pgtsun4c.h>
-#endif
-#include <asm/pgtsrmmu.h>
-#include <asm/vac-ops.h>
-#include <asm/oplib.h>
-#include <asm/btfixup.h>
-#include <asm/system.h>
-
-
-struct vm_area_struct;
-struct page;
-
-extern void load_mmu(void);
-extern unsigned long calc_highpages(void);
-
-BTFIXUPDEF_SIMM13(pgdir_shift)
-BTFIXUPDEF_SETHI(pgdir_size)
-BTFIXUPDEF_SETHI(pgdir_mask)
-
-BTFIXUPDEF_SIMM13(ptrs_per_pmd)
-BTFIXUPDEF_SIMM13(ptrs_per_pgd)
-BTFIXUPDEF_SIMM13(user_ptrs_per_pgd)
-
-#define pte_ERROR(e) __builtin_trap()
-#define pmd_ERROR(e) __builtin_trap()
-#define pgd_ERROR(e) __builtin_trap()
-
-BTFIXUPDEF_INT(page_none)
-BTFIXUPDEF_INT(page_copy)
-BTFIXUPDEF_INT(page_readonly)
-BTFIXUPDEF_INT(page_kernel)
-
-#define PMD_SHIFT SUN4C_PMD_SHIFT
-#define PMD_SIZE (1UL << PMD_SHIFT)
-#define PMD_MASK (~(PMD_SIZE-1))
-#define PMD_ALIGN(__addr) (((__addr) + ~PMD_MASK) & PMD_MASK)
-#define PGDIR_SHIFT BTFIXUP_SIMM13(pgdir_shift)
-#define PGDIR_SIZE BTFIXUP_SETHI(pgdir_size)
-#define PGDIR_MASK BTFIXUP_SETHI(pgdir_mask)
-#define PTRS_PER_PTE 1024
-#define PTRS_PER_PMD BTFIXUP_SIMM13(ptrs_per_pmd)
-#define PTRS_PER_PGD BTFIXUP_SIMM13(ptrs_per_pgd)
-#define USER_PTRS_PER_PGD BTFIXUP_SIMM13(user_ptrs_per_pgd)
-#define FIRST_USER_ADDRESS 0
-#define PTE_SIZE (PTRS_PER_PTE*4)
-
-#define PAGE_NONE __pgprot(BTFIXUP_INT(page_none))
-extern pgprot_t PAGE_SHARED;
-#define PAGE_COPY __pgprot(BTFIXUP_INT(page_copy))
-#define PAGE_READONLY __pgprot(BTFIXUP_INT(page_readonly))
-
-extern unsigned long page_kernel;
-
-#ifdef MODULE
-#define PAGE_KERNEL page_kernel
-#else
-#define PAGE_KERNEL __pgprot(BTFIXUP_INT(page_kernel))
-#endif
-
-/* Top-level page directory */
-extern pgd_t swapper_pg_dir[1024];
-
-extern void paging_init(void);
-
-/* Page table for 0-4MB for everybody, on the Sparc this
- * holds the same as on the i386.
- */
-extern pte_t pg0[1024];
-extern pte_t pg1[1024];
-extern pte_t pg2[1024];
-extern pte_t pg3[1024];
-
-extern unsigned long ptr_in_current_pgd;
-
-/* Here is a trick, since mmap.c need the initializer elements for
- * protection_map[] to be constant at compile time, I set the following
- * to all zeros. I set it to the real values after I link in the
- * appropriate MMU page table routines at boot time.
- */
-#define __P000 __pgprot(0)
-#define __P001 __pgprot(0)
-#define __P010 __pgprot(0)
-#define __P011 __pgprot(0)
-#define __P100 __pgprot(0)
-#define __P101 __pgprot(0)
-#define __P110 __pgprot(0)
-#define __P111 __pgprot(0)
-
-#define __S000 __pgprot(0)
-#define __S001 __pgprot(0)
-#define __S010 __pgprot(0)
-#define __S011 __pgprot(0)
-#define __S100 __pgprot(0)
-#define __S101 __pgprot(0)
-#define __S110 __pgprot(0)
-#define __S111 __pgprot(0)
-
-extern int num_contexts;
-
-/* First physical page can be anywhere, the following is needed so that
- * va-->pa and vice versa conversions work properly without performance
- * hit for all __pa()/__va() operations.
- */
-extern unsigned long phys_base;
-extern unsigned long pfn_base;
-
-/*
- * BAD_PAGETABLE is used when we need a bogus page-table, while
- * BAD_PAGE is used for a bogus page.
- *
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-extern pte_t * __bad_pagetable(void);
-extern pte_t __bad_page(void);
-extern unsigned long empty_zero_page;
-
-#define BAD_PAGETABLE __bad_pagetable()
-#define BAD_PAGE __bad_page()
-#define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))
-
-/*
- */
-BTFIXUPDEF_CALL_CONST(struct page *, pmd_page, pmd_t)
-BTFIXUPDEF_CALL_CONST(unsigned long, pgd_page_vaddr, pgd_t)
-
-#define pmd_page(pmd) BTFIXUP_CALL(pmd_page)(pmd)
-#define pgd_page_vaddr(pgd) BTFIXUP_CALL(pgd_page_vaddr)(pgd)
-
-BTFIXUPDEF_SETHI(none_mask)
-BTFIXUPDEF_CALL_CONST(int, pte_present, pte_t)
-BTFIXUPDEF_CALL(void, pte_clear, pte_t *)
-
-static inline int pte_none(pte_t pte)
-{
- return !(pte_val(pte) & ~BTFIXUP_SETHI(none_mask));
-}
-
-#define pte_present(pte) BTFIXUP_CALL(pte_present)(pte)
-#define pte_clear(mm,addr,pte) BTFIXUP_CALL(pte_clear)(pte)
-
-BTFIXUPDEF_CALL_CONST(int, pmd_bad, pmd_t)
-BTFIXUPDEF_CALL_CONST(int, pmd_present, pmd_t)
-BTFIXUPDEF_CALL(void, pmd_clear, pmd_t *)
-
-static inline int pmd_none(pmd_t pmd)
-{
- return !(pmd_val(pmd) & ~BTFIXUP_SETHI(none_mask));
-}
-
-#define pmd_bad(pmd) BTFIXUP_CALL(pmd_bad)(pmd)
-#define pmd_present(pmd) BTFIXUP_CALL(pmd_present)(pmd)
-#define pmd_clear(pmd) BTFIXUP_CALL(pmd_clear)(pmd)
-
-BTFIXUPDEF_CALL_CONST(int, pgd_none, pgd_t)
-BTFIXUPDEF_CALL_CONST(int, pgd_bad, pgd_t)
-BTFIXUPDEF_CALL_CONST(int, pgd_present, pgd_t)
-BTFIXUPDEF_CALL(void, pgd_clear, pgd_t *)
-
-#define pgd_none(pgd) BTFIXUP_CALL(pgd_none)(pgd)
-#define pgd_bad(pgd) BTFIXUP_CALL(pgd_bad)(pgd)
-#define pgd_present(pgd) BTFIXUP_CALL(pgd_present)(pgd)
-#define pgd_clear(pgd) BTFIXUP_CALL(pgd_clear)(pgd)
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-BTFIXUPDEF_HALF(pte_writei)
-BTFIXUPDEF_HALF(pte_dirtyi)
-BTFIXUPDEF_HALF(pte_youngi)
-
-static int pte_write(pte_t pte) __attribute_const__;
-static inline int pte_write(pte_t pte)
-{
- return pte_val(pte) & BTFIXUP_HALF(pte_writei);
-}
-
-static int pte_dirty(pte_t pte) __attribute_const__;
-static inline int pte_dirty(pte_t pte)
-{
- return pte_val(pte) & BTFIXUP_HALF(pte_dirtyi);
-}
-
-static int pte_young(pte_t pte) __attribute_const__;
-static inline int pte_young(pte_t pte)
-{
- return pte_val(pte) & BTFIXUP_HALF(pte_youngi);
-}
-
-/*
- * The following only work if pte_present() is not true.
- */
-BTFIXUPDEF_HALF(pte_filei)
-
-static int pte_file(pte_t pte) __attribute_const__;
-static inline int pte_file(pte_t pte)
-{
- return pte_val(pte) & BTFIXUP_HALF(pte_filei);
-}
-
-static inline int pte_special(pte_t pte)
-{
- return 0;
-}
-
-/*
- */
-BTFIXUPDEF_HALF(pte_wrprotecti)
-BTFIXUPDEF_HALF(pte_mkcleani)
-BTFIXUPDEF_HALF(pte_mkoldi)
-
-static pte_t pte_wrprotect(pte_t pte) __attribute_const__;
-static inline pte_t pte_wrprotect(pte_t pte)
-{
- return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_wrprotecti));
-}
-
-static pte_t pte_mkclean(pte_t pte) __attribute_const__;
-static inline pte_t pte_mkclean(pte_t pte)
-{
- return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkcleani));
-}
-
-static pte_t pte_mkold(pte_t pte) __attribute_const__;
-static inline pte_t pte_mkold(pte_t pte)
-{
- return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkoldi));
-}
-
-BTFIXUPDEF_CALL_CONST(pte_t, pte_mkwrite, pte_t)
-BTFIXUPDEF_CALL_CONST(pte_t, pte_mkdirty, pte_t)
-BTFIXUPDEF_CALL_CONST(pte_t, pte_mkyoung, pte_t)
-
-#define pte_mkwrite(pte) BTFIXUP_CALL(pte_mkwrite)(pte)
-#define pte_mkdirty(pte) BTFIXUP_CALL(pte_mkdirty)(pte)
-#define pte_mkyoung(pte) BTFIXUP_CALL(pte_mkyoung)(pte)
-
-#define pte_mkspecial(pte) (pte)
-
-#define pfn_pte(pfn, prot) mk_pte(pfn_to_page(pfn), prot)
-
-BTFIXUPDEF_CALL(unsigned long, pte_pfn, pte_t)
-#define pte_pfn(pte) BTFIXUP_CALL(pte_pfn)(pte)
-#define pte_page(pte) pfn_to_page(pte_pfn(pte))
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-BTFIXUPDEF_CALL_CONST(pte_t, mk_pte, struct page *, pgprot_t)
-
-BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_phys, unsigned long, pgprot_t)
-BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_io, unsigned long, pgprot_t, int)
-BTFIXUPDEF_CALL_CONST(pgprot_t, pgprot_noncached, pgprot_t)
-
-#define mk_pte(page,pgprot) BTFIXUP_CALL(mk_pte)(page,pgprot)
-#define mk_pte_phys(page,pgprot) BTFIXUP_CALL(mk_pte_phys)(page,pgprot)
-#define mk_pte_io(page,pgprot,space) BTFIXUP_CALL(mk_pte_io)(page,pgprot,space)
-
-#define pgprot_noncached(pgprot) BTFIXUP_CALL(pgprot_noncached)(pgprot)
-
-BTFIXUPDEF_INT(pte_modify_mask)
-
-static pte_t pte_modify(pte_t pte, pgprot_t newprot) __attribute_const__;
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
- return __pte((pte_val(pte) & BTFIXUP_INT(pte_modify_mask)) |
- pgprot_val(newprot));
-}
-
-#define pgd_index(address) ((address) >> PGDIR_SHIFT)
-
-/* to find an entry in a page-table-directory */
-#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/* Find an entry in the second-level page table.. */
-BTFIXUPDEF_CALL(pmd_t *, pmd_offset, pgd_t *, unsigned long)
-#define pmd_offset(dir,addr) BTFIXUP_CALL(pmd_offset)(dir,addr)
-
-/* Find an entry in the third-level page table.. */
-BTFIXUPDEF_CALL(pte_t *, pte_offset_kernel, pmd_t *, unsigned long)
-#define pte_offset_kernel(dir,addr) BTFIXUP_CALL(pte_offset_kernel)(dir,addr)
-
-/*
- * This shortcut works on sun4m (and sun4d) because the nocache area is static,
- * and sun4c is guaranteed to have no highmem anyway.
- */
-#define pte_offset_map(d, a) pte_offset_kernel(d,a)
-#define pte_offset_map_nested(d, a) pte_offset_kernel(d,a)
-
-#define pte_unmap(pte) do{}while(0)
-#define pte_unmap_nested(pte) do{}while(0)
-
-/* Certain architectures need to do special things when pte's
- * within a page table are directly modified. Thus, the following
- * hook is made available.
- */
-
-BTFIXUPDEF_CALL(void, set_pte, pte_t *, pte_t)
-
-#define set_pte(ptep,pteval) BTFIXUP_CALL(set_pte)(ptep,pteval)
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-
-struct seq_file;
-BTFIXUPDEF_CALL(void, mmu_info, struct seq_file *)
-
-#define mmu_info(p) BTFIXUP_CALL(mmu_info)(p)
-
-/* Fault handler stuff... */
-#define FAULT_CODE_PROT 0x1
-#define FAULT_CODE_WRITE 0x2
-#define FAULT_CODE_USER 0x4
-
-BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t)
-
-#define update_mmu_cache(vma,addr,pte) BTFIXUP_CALL(update_mmu_cache)(vma,addr,pte)
-
-BTFIXUPDEF_CALL(void, sparc_mapiorange, unsigned int, unsigned long,
- unsigned long, unsigned int)
-BTFIXUPDEF_CALL(void, sparc_unmapiorange, unsigned long, unsigned int)
-#define sparc_mapiorange(bus,pa,va,len) BTFIXUP_CALL(sparc_mapiorange)(bus,pa,va,len)
-#define sparc_unmapiorange(va,len) BTFIXUP_CALL(sparc_unmapiorange)(va,len)
-
-extern int invalid_segment;
-
-/* Encode and de-code a swap entry */
-BTFIXUPDEF_CALL(unsigned long, __swp_type, swp_entry_t)
-BTFIXUPDEF_CALL(unsigned long, __swp_offset, swp_entry_t)
-BTFIXUPDEF_CALL(swp_entry_t, __swp_entry, unsigned long, unsigned long)
-
-#define __swp_type(__x) BTFIXUP_CALL(__swp_type)(__x)
-#define __swp_offset(__x) BTFIXUP_CALL(__swp_offset)(__x)
-#define __swp_entry(__type,__off) BTFIXUP_CALL(__swp_entry)(__type,__off)
-
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-/* file-offset-in-pte helpers */
-BTFIXUPDEF_CALL(unsigned long, pte_to_pgoff, pte_t pte);
-BTFIXUPDEF_CALL(pte_t, pgoff_to_pte, unsigned long pgoff);
-
-#define pte_to_pgoff(pte) BTFIXUP_CALL(pte_to_pgoff)(pte)
-#define pgoff_to_pte(off) BTFIXUP_CALL(pgoff_to_pte)(off)
-
-/*
- * This is made a constant because mm/fremap.c required a constant.
- * Note that layout of these bits is different between sun4c.c and srmmu.c.
- */
-#define PTE_FILE_MAX_BITS 24
-
-/*
- */
-struct ctx_list {
- struct ctx_list *next;
- struct ctx_list *prev;
- unsigned int ctx_number;
- struct mm_struct *ctx_mm;
-};
-
-extern struct ctx_list *ctx_list_pool; /* Dynamically allocated */
-extern struct ctx_list ctx_free; /* Head of free list */
-extern struct ctx_list ctx_used; /* Head of used contexts list */
-
-#define NO_CONTEXT -1
-
-static inline void remove_from_ctx_list(struct ctx_list *entry)
-{
- entry->next->prev = entry->prev;
- entry->prev->next = entry->next;
-}
-
-static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
-{
- entry->next = head;
- (entry->prev = head->prev)->next = entry;
- head->prev = entry;
-}
-#define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
-#define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
-
-static inline unsigned long
-__get_phys (unsigned long addr)
-{
- switch (sparc_cpu_model){
- case sun4:
- case sun4c:
- return sun4c_get_pte (addr) << PAGE_SHIFT;
- case sun4m:
- case sun4d:
- return ((srmmu_get_pte (addr) & 0xffffff00) << 4);
- default:
- return 0;
- }
-}
-
-static inline int
-__get_iospace (unsigned long addr)
-{
- switch (sparc_cpu_model){
- case sun4:
- case sun4c:
- return -1; /* Don't check iospace on sun4c */
- case sun4m:
- case sun4d:
- return (srmmu_get_pte (addr) >> 28);
- default:
- return -1;
- }
-}
-
-extern unsigned long *sparc_valid_addr_bitmap;
-
-/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
-#define kern_addr_valid(addr) \
- (test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap))
-
-extern int io_remap_pfn_range(struct vm_area_struct *vma,
- unsigned long from, unsigned long pfn,
- unsigned long size, pgprot_t prot);
-
-/*
- * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
- * its high 4 bits. These macros/functions put it there or get it from there.
- */
-#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
-#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
-#define GET_PFN(pfn) (pfn & 0x0fffffffUL)
-
-#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
-#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
-({ \
- int __changed = !pte_same(*(__ptep), __entry); \
- if (__changed) { \
- set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
- flush_tlb_page(__vma, __address); \
- } \
- (sparc_cpu_model == sun4c) || __changed; \
-})
-
-#include <asm-generic/pgtable.h>
-
-#endif /* !(__ASSEMBLY__) */
-
-#define VMALLOC_START 0xfe600000
-/* XXX Alter this when I get around to fixing sun4c - Anton */
-#define VMALLOC_END 0xffc00000
-
-
-/* We provide our own get_unmapped_area to cope with VA holes for userland */
-#define HAVE_ARCH_UNMAPPED_AREA
-
-/*
- * No page table caches to initialise
- */
-#define pgtable_cache_init() do { } while (0)
-
-#endif /* !(_SPARC_PGTABLE_H) */
+++ /dev/null
-/*
- * pgtable.h: SpitFire page table operations.
- *
- * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
- * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-
-#ifndef _SPARC64_PGTABLE_H
-#define _SPARC64_PGTABLE_H
-
-/* This file contains the functions and defines necessary to modify and use
- * the SpitFire page tables.
- */
-
-#include <asm-generic/pgtable-nopud.h>
-
-#include <linux/compiler.h>
-#include <linux/const.h>
-#include <asm/types.h>
-#include <asm/spitfire.h>
-#include <asm/asi.h>
-#include <asm/system.h>
-#include <asm/page.h>
-#include <asm/processor.h>
-
-/* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
- * The page copy blockops can use 0x6000000 to 0x8000000.
- * The TSB is mapped in the 0x8000000 to 0xa000000 range.
- * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
- * The vmalloc area spans 0x100000000 to 0x200000000.
- * Since modules need to be in the lowest 32-bits of the address space,
- * we place them right before the OBP area from 0x10000000 to 0xf0000000.
- * There is a single static kernel PMD which maps from 0x0 to address
- * 0x400000000.
- */
-#define TLBTEMP_BASE _AC(0x0000000006000000,UL)
-#define TSBMAP_BASE _AC(0x0000000008000000,UL)
-#define MODULES_VADDR _AC(0x0000000010000000,UL)
-#define MODULES_LEN _AC(0x00000000e0000000,UL)
-#define MODULES_END _AC(0x00000000f0000000,UL)
-#define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
-#define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
-#define VMALLOC_START _AC(0x0000000100000000,UL)
-#define VMALLOC_END _AC(0x0000000200000000,UL)
-#define VMEMMAP_BASE _AC(0x0000000200000000,UL)
-
-#define vmemmap ((struct page *)VMEMMAP_BASE)
-
-/* XXX All of this needs to be rethought so we can take advantage
- * XXX cheetah's full 64-bit virtual address space, ie. no more hole
- * XXX in the middle like on spitfire. -DaveM
- */
-/*
- * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
- * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
- * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
- * table is a single page long). The next higher PMD_BITS determine pmd#
- * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
- * since the pmd entries are 4 bytes, and each pmd page is a single page
- * long). Finally, the higher few bits determine pgde#.
- */
-
-/* PMD_SHIFT determines the size of the area a second-level page
- * table can map
- */
-#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
-#define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
-#define PMD_MASK (~(PMD_SIZE-1))
-#define PMD_BITS (PAGE_SHIFT - 2)
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
-#define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
-#define PGDIR_MASK (~(PGDIR_SIZE-1))
-#define PGDIR_BITS (PAGE_SHIFT - 2)
-
-#ifndef __ASSEMBLY__
-
-#include <linux/sched.h>
-
-/* Entries per page directory level. */
-#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
-#define PTRS_PER_PMD (1UL << PMD_BITS)
-#define PTRS_PER_PGD (1UL << PGDIR_BITS)
-
-/* Kernel has a separate 44bit address space. */
-#define FIRST_USER_ADDRESS 0
-
-#define pte_ERROR(e) __builtin_trap()
-#define pmd_ERROR(e) __builtin_trap()
-#define pgd_ERROR(e) __builtin_trap()
-
-#endif /* !(__ASSEMBLY__) */
-
-/* PTE bits which are the same in SUN4U and SUN4V format. */
-#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
-#define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
-
-/* SUN4U pte bits... */
-#define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
-#define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
-#define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
-#define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
-#define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
-#define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
-#define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
-#define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
-#define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
-#define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
-#define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */
-#define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
-#define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
-#define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
-#define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
-#define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
-#define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
-#define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */
-#define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
-#define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
-#define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
-#define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
-#define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
-#define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
-#define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
-#define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
-#define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
-#define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
-
-/* SUN4V pte bits... */
-#define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
-#define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
-#define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
-#define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
-#define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
-#define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
-#define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
-#define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
-#define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
-#define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
-#define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
-#define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
-#define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
-#define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
-#define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
-#define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */
-#define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
-#define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
-#define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
-#define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
-#define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
-#define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
-#define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
-#define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
-#define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
-#define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
-#define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */
-
-#if PAGE_SHIFT == 13
-#define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
-#define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
-#elif PAGE_SHIFT == 16
-#define _PAGE_SZBITS_4U _PAGE_SZ64K_4U
-#define _PAGE_SZBITS_4V _PAGE_SZ64K_4V
-#else
-#error Wrong PAGE_SHIFT specified
-#endif
-
-#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
-#define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
-#define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
-#define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U
-#define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
-#define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U
-#define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V
-#endif
-
-/* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
-#define __P000 __pgprot(0)
-#define __P001 __pgprot(0)
-#define __P010 __pgprot(0)
-#define __P011 __pgprot(0)
-#define __P100 __pgprot(0)
-#define __P101 __pgprot(0)
-#define __P110 __pgprot(0)
-#define __P111 __pgprot(0)
-
-#define __S000 __pgprot(0)
-#define __S001 __pgprot(0)
-#define __S010 __pgprot(0)
-#define __S011 __pgprot(0)
-#define __S100 __pgprot(0)
-#define __S101 __pgprot(0)
-#define __S110 __pgprot(0)
-#define __S111 __pgprot(0)
-
-#ifndef __ASSEMBLY__
-
-extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
-
-extern unsigned long pte_sz_bits(unsigned long size);
-
-extern pgprot_t PAGE_KERNEL;
-extern pgprot_t PAGE_KERNEL_LOCKED;
-extern pgprot_t PAGE_COPY;
-extern pgprot_t PAGE_SHARED;
-
-/* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
-extern unsigned long _PAGE_IE;
-extern unsigned long _PAGE_E;
-extern unsigned long _PAGE_CACHE;
-
-extern unsigned long pg_iobits;
-extern unsigned long _PAGE_ALL_SZ_BITS;
-extern unsigned long _PAGE_SZBITS;
-
-extern struct page *mem_map_zero;
-#define ZERO_PAGE(vaddr) (mem_map_zero)
-
-/* PFNs are real physical page numbers. However, mem_map only begins to record
- * per-page information starting at pfn_base. This is to handle systems where
- * the first physical page in the machine is at some huge physical address,
- * such as 4GB. This is common on a partitioned E10000, for example.
- */
-static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
-{
- unsigned long paddr = pfn << PAGE_SHIFT;
- unsigned long sz_bits;
-
- sz_bits = 0UL;
- if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) {
- __asm__ __volatile__(
- "\n661: sethi %%uhi(%1), %0\n"
- " sllx %0, 32, %0\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " mov %2, %0\n"
- " nop\n"
- " .previous\n"
- : "=r" (sz_bits)
- : "i" (_PAGE_SZBITS_4U), "i" (_PAGE_SZBITS_4V));
- }
- return __pte(paddr | sz_bits | pgprot_val(prot));
-}
-#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
-
-/* This one can be done with two shifts. */
-static inline unsigned long pte_pfn(pte_t pte)
-{
- unsigned long ret;
-
- __asm__ __volatile__(
- "\n661: sllx %1, %2, %0\n"
- " srlx %0, %3, %0\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " sllx %1, %4, %0\n"
- " srlx %0, %5, %0\n"
- " .previous\n"
- : "=r" (ret)
- : "r" (pte_val(pte)),
- "i" (21), "i" (21 + PAGE_SHIFT),
- "i" (8), "i" (8 + PAGE_SHIFT));
-
- return ret;
-}
-#define pte_page(x) pfn_to_page(pte_pfn(x))
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
-{
- unsigned long mask, tmp;
-
- /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347)
- * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8)
- *
- * Even if we use negation tricks the result is still a 6
- * instruction sequence, so don't try to play fancy and just
- * do the most straightforward implementation.
- *
- * Note: We encode this into 3 sun4v 2-insn patch sequences.
- */
-
- __asm__ __volatile__(
- "\n661: sethi %%uhi(%2), %1\n"
- " sethi %%hi(%2), %0\n"
- "\n662: or %1, %%ulo(%2), %1\n"
- " or %0, %%lo(%2), %0\n"
- "\n663: sllx %1, 32, %1\n"
- " or %0, %1, %0\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " sethi %%uhi(%3), %1\n"
- " sethi %%hi(%3), %0\n"
- " .word 662b\n"
- " or %1, %%ulo(%3), %1\n"
- " or %0, %%lo(%3), %0\n"
- " .word 663b\n"
- " sllx %1, 32, %1\n"
- " or %0, %1, %0\n"
- " .previous\n"
- : "=r" (mask), "=r" (tmp)
- : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
- _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U |
- _PAGE_SZBITS_4U),
- "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
- _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V |
- _PAGE_SZBITS_4V));
-
- return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
-}
-
-static inline pte_t pgoff_to_pte(unsigned long off)
-{
- off <<= PAGE_SHIFT;
-
- __asm__ __volatile__(
- "\n661: or %0, %2, %0\n"
- " .section .sun4v_1insn_patch, \"ax\"\n"
- " .word 661b\n"
- " or %0, %3, %0\n"
- " .previous\n"
- : "=r" (off)
- : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
-
- return __pte(off);
-}
-
-static inline pgprot_t pgprot_noncached(pgprot_t prot)
-{
- unsigned long val = pgprot_val(prot);
-
- __asm__ __volatile__(
- "\n661: andn %0, %2, %0\n"
- " or %0, %3, %0\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " andn %0, %4, %0\n"
- " or %0, %5, %0\n"
- " .previous\n"
- : "=r" (val)
- : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
- "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
-
- return __pgprot(val);
-}
-/* Various pieces of code check for platform support by ifdef testing
- * on "pgprot_noncached". That's broken and should be fixed, but for
- * now...
- */
-#define pgprot_noncached pgprot_noncached
-
-#ifdef CONFIG_HUGETLB_PAGE
-static inline pte_t pte_mkhuge(pte_t pte)
-{
- unsigned long mask;
-
- __asm__ __volatile__(
- "\n661: sethi %%uhi(%1), %0\n"
- " sllx %0, 32, %0\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " mov %2, %0\n"
- " nop\n"
- " .previous\n"
- : "=r" (mask)
- : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
-
- return __pte(pte_val(pte) | mask);
-}
-#endif
-
-static inline pte_t pte_mkdirty(pte_t pte)
-{
- unsigned long val = pte_val(pte), tmp;
-
- __asm__ __volatile__(
- "\n661: or %0, %3, %0\n"
- " nop\n"
- "\n662: nop\n"
- " nop\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " sethi %%uhi(%4), %1\n"
- " sllx %1, 32, %1\n"
- " .word 662b\n"
- " or %1, %%lo(%4), %1\n"
- " or %0, %1, %0\n"
- " .previous\n"
- : "=r" (val), "=r" (tmp)
- : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
- "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
-
- return __pte(val);
-}
-
-static inline pte_t pte_mkclean(pte_t pte)
-{
- unsigned long val = pte_val(pte), tmp;
-
- __asm__ __volatile__(
- "\n661: andn %0, %3, %0\n"
- " nop\n"
- "\n662: nop\n"
- " nop\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " sethi %%uhi(%4), %1\n"
- " sllx %1, 32, %1\n"
- " .word 662b\n"
- " or %1, %%lo(%4), %1\n"
- " andn %0, %1, %0\n"
- " .previous\n"
- : "=r" (val), "=r" (tmp)
- : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
- "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
-
- return __pte(val);
-}
-
-static inline pte_t pte_mkwrite(pte_t pte)
-{
- unsigned long val = pte_val(pte), mask;
-
- __asm__ __volatile__(
- "\n661: mov %1, %0\n"
- " nop\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " sethi %%uhi(%2), %0\n"
- " sllx %0, 32, %0\n"
- " .previous\n"
- : "=r" (mask)
- : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
-
- return __pte(val | mask);
-}
-
-static inline pte_t pte_wrprotect(pte_t pte)
-{
- unsigned long val = pte_val(pte), tmp;
-
- __asm__ __volatile__(
- "\n661: andn %0, %3, %0\n"
- " nop\n"
- "\n662: nop\n"
- " nop\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " sethi %%uhi(%4), %1\n"
- " sllx %1, 32, %1\n"
- " .word 662b\n"
- " or %1, %%lo(%4), %1\n"
- " andn %0, %1, %0\n"
- " .previous\n"
- : "=r" (val), "=r" (tmp)
- : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
- "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
-
- return __pte(val);
-}
-
-static inline pte_t pte_mkold(pte_t pte)
-{
- unsigned long mask;
-
- __asm__ __volatile__(
- "\n661: mov %1, %0\n"
- " nop\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " sethi %%uhi(%2), %0\n"
- " sllx %0, 32, %0\n"
- " .previous\n"
- : "=r" (mask)
- : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
-
- mask |= _PAGE_R;
-
- return __pte(pte_val(pte) & ~mask);
-}
-
-static inline pte_t pte_mkyoung(pte_t pte)
-{
- unsigned long mask;
-
- __asm__ __volatile__(
- "\n661: mov %1, %0\n"
- " nop\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " sethi %%uhi(%2), %0\n"
- " sllx %0, 32, %0\n"
- " .previous\n"
- : "=r" (mask)
- : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
-
- mask |= _PAGE_R;
-
- return __pte(pte_val(pte) | mask);
-}
-
-static inline pte_t pte_mkspecial(pte_t pte)
-{
- return pte;
-}
-
-static inline unsigned long pte_young(pte_t pte)
-{
- unsigned long mask;
-
- __asm__ __volatile__(
- "\n661: mov %1, %0\n"
- " nop\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " sethi %%uhi(%2), %0\n"
- " sllx %0, 32, %0\n"
- " .previous\n"
- : "=r" (mask)
- : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
-
- return (pte_val(pte) & mask);
-}
-
-static inline unsigned long pte_dirty(pte_t pte)
-{
- unsigned long mask;
-
- __asm__ __volatile__(
- "\n661: mov %1, %0\n"
- " nop\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " sethi %%uhi(%2), %0\n"
- " sllx %0, 32, %0\n"
- " .previous\n"
- : "=r" (mask)
- : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
-
- return (pte_val(pte) & mask);
-}
-
-static inline unsigned long pte_write(pte_t pte)
-{
- unsigned long mask;
-
- __asm__ __volatile__(
- "\n661: mov %1, %0\n"
- " nop\n"
- " .section .sun4v_2insn_patch, \"ax\"\n"
- " .word 661b\n"
- " sethi %%uhi(%2), %0\n"
- " sllx %0, 32, %0\n"
- " .previous\n"
- : "=r" (mask)
- : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
-
- return (pte_val(pte) & mask);
-}
-
-static inline unsigned long pte_exec(pte_t pte)
-{
- unsigned long mask;
-
- __asm__ __volatile__(
- "\n661: sethi %%hi(%1), %0\n"
- " .section .sun4v_1insn_patch, \"ax\"\n"
- " .word 661b\n"
- " mov %2, %0\n"
- " .previous\n"
- : "=r" (mask)
- : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
-
- return (pte_val(pte) & mask);
-}
-
-static inline unsigned long pte_file(pte_t pte)
-{
- unsigned long val = pte_val(pte);
-
- __asm__ __volatile__(
- "\n661: and %0, %2, %0\n"
- " .section .sun4v_1insn_patch, \"ax\"\n"
- " .word 661b\n"
- " and %0, %3, %0\n"
- " .previous\n"
- : "=r" (val)
- : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
-
- return val;
-}
-
-static inline unsigned long pte_present(pte_t pte)
-{
- unsigned long val = pte_val(pte);
-
- __asm__ __volatile__(
- "\n661: and %0, %2, %0\n"
- " .section .sun4v_1insn_patch, \"ax\"\n"
- " .word 661b\n"
- " and %0, %3, %0\n"
- " .previous\n"
- : "=r" (val)
- : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
-
- return val;
-}
-
-static inline int pte_special(pte_t pte)
-{
- return 0;
-}
-
-#define pmd_set(pmdp, ptep) \
- (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
-#define pud_set(pudp, pmdp) \
- (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
-#define __pmd_page(pmd) \
- ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
-#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
-#define pud_page_vaddr(pud) \
- ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
-#define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud))
-#define pmd_none(pmd) (!pmd_val(pmd))
-#define pmd_bad(pmd) (0)
-#define pmd_present(pmd) (pmd_val(pmd) != 0U)
-#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U)
-#define pud_none(pud) (!pud_val(pud))
-#define pud_bad(pud) (0)
-#define pud_present(pud) (pud_val(pud) != 0U)
-#define pud_clear(pudp) (pud_val(*(pudp)) = 0U)
-
-/* Same in both SUN4V and SUN4U. */
-#define pte_none(pte) (!pte_val(pte))
-
-/* to find an entry in a page-table-directory. */
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
-#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/* Find an entry in the second-level page table.. */
-#define pmd_offset(pudp, address) \
- ((pmd_t *) pud_page_vaddr(*(pudp)) + \
- (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
-
-/* Find an entry in the third-level page table.. */
-#define pte_index(dir, address) \
- ((pte_t *) __pmd_page(*(dir)) + \
- ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
-#define pte_offset_kernel pte_index
-#define pte_offset_map pte_index
-#define pte_offset_map_nested pte_index
-#define pte_unmap(pte) do { } while (0)
-#define pte_unmap_nested(pte) do { } while (0)
-
-/* Actual page table PTE updates. */
-extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
-
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
-{
- pte_t orig = *ptep;
-
- *ptep = pte;
-
- /* It is more efficient to let flush_tlb_kernel_range()
- * handle init_mm tlb flushes.
- *
- * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
- * and SUN4V pte layout, so this inline test is fine.
- */
- if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
- tlb_batch_add(mm, addr, ptep, orig);
-}
-
-#define pte_clear(mm,addr,ptep) \
- set_pte_at((mm), (addr), (ptep), __pte(0UL))
-
-#ifdef DCACHE_ALIASING_POSSIBLE
-#define __HAVE_ARCH_MOVE_PTE
-#define move_pte(pte, prot, old_addr, new_addr) \
-({ \
- pte_t newpte = (pte); \
- if (tlb_type != hypervisor && pte_present(pte)) { \
- unsigned long this_pfn = pte_pfn(pte); \
- \
- if (pfn_valid(this_pfn) && \
- (((old_addr) ^ (new_addr)) & (1 << 13))) \
- flush_dcache_page_all(current->mm, \
- pfn_to_page(this_pfn)); \
- } \
- newpte; \
-})
-#endif
-
-extern pgd_t swapper_pg_dir[2048];
-extern pmd_t swapper_low_pmd_dir[2048];
-
-extern void paging_init(void);
-extern unsigned long find_ecache_flush_span(unsigned long size);
-
-/* These do nothing with the way I have things setup. */
-#define mmu_lockarea(vaddr, len) (vaddr)
-#define mmu_unlockarea(vaddr, len) do { } while(0)
-
-struct vm_area_struct;
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
-
-/* Encode and de-code a swap entry */
-#define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
-#define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
-#define __swp_entry(type, offset) \
- ( (swp_entry_t) \
- { \
- (((long)(type) << PAGE_SHIFT) | \
- ((long)(offset) << (PAGE_SHIFT + 8UL))) \
- } )
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-/* File offset in PTE support. */
-extern unsigned long pte_file(pte_t);
-#define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
-extern pte_t pgoff_to_pte(unsigned long);
-#define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
-
-extern unsigned long *sparc64_valid_addr_bitmap;
-
-/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
-#define kern_addr_valid(addr) \
- (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
-
-extern int page_in_phys_avail(unsigned long paddr);
-
-extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
- unsigned long pfn,
- unsigned long size, pgprot_t prot);
-
-/*
- * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
- * its high 4 bits. These macros/functions put it there or get it from there.
- */
-#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
-#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
-#define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
-
-#include <asm-generic/pgtable.h>
-
-/* We provide our own get_unmapped_area to cope with VA holes and
- * SHM area cache aliasing for userland.
- */
-#define HAVE_ARCH_UNMAPPED_AREA
-#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
-
-/* We provide a special get_unmapped_area for framebuffer mmaps to try and use
- * the largest alignment possible such that larget PTEs can be used.
- */
-extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
- unsigned long, unsigned long,
- unsigned long);
-#define HAVE_ARCH_FB_UNMAPPED_AREA
-
-extern void pgtable_cache_init(void);
-extern void sun4v_register_fault_status(void);
-extern void sun4v_ktsb_register(void);
-extern void __init cheetah_ecache_flush_init(void);
-extern void sun4v_patch_tlb_handlers(void);
-
-extern unsigned long cmdline_memory_size;
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(_SPARC64_PGTABLE_H) */
+++ /dev/null
-/*
- * pgtsrmmu.h: SRMMU page table defines and code.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_PGTSRMMU_H
-#define _SPARC_PGTSRMMU_H
-
-#include <asm/page.h>
-
-#ifdef __ASSEMBLY__
-#include <asm/thread_info.h> /* TI_UWINMASK for WINDOW_FLUSH */
-#endif
-
-/* Number of contexts is implementation-dependent; 64k is the most we support */
-#define SRMMU_MAX_CONTEXTS 65536
-
-/* PMD_SHIFT determines the size of the area a second-level page table entry can map */
-#define SRMMU_REAL_PMD_SHIFT 18
-#define SRMMU_REAL_PMD_SIZE (1UL << SRMMU_REAL_PMD_SHIFT)
-#define SRMMU_REAL_PMD_MASK (~(SRMMU_REAL_PMD_SIZE-1))
-#define SRMMU_REAL_PMD_ALIGN(__addr) (((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK)
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define SRMMU_PGDIR_SHIFT 24
-#define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT)
-#define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1))
-#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
-
-#define SRMMU_REAL_PTRS_PER_PTE 64
-#define SRMMU_REAL_PTRS_PER_PMD 64
-#define SRMMU_PTRS_PER_PGD 256
-
-#define SRMMU_REAL_PTE_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PTE*4)
-#define SRMMU_PMD_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PMD*4)
-#define SRMMU_PGD_TABLE_SIZE (SRMMU_PTRS_PER_PGD*4)
-
-/*
- * To support pagetables in highmem, Linux introduces APIs which
- * return struct page* and generally manipulate page tables when
- * they are not mapped into kernel space. Our hardware page tables
- * are smaller than pages. We lump hardware tabes into big, page sized
- * software tables.
- *
- * PMD_SHIFT determines the size of the area a second-level page table entry
- * can map, and our pmd_t is 16 times larger than normal. The values which
- * were once defined here are now generic for 4c and srmmu, so they're
- * found in pgtable.h.
- */
-#define SRMMU_PTRS_PER_PMD 4
-
-/* Definition of the values in the ET field of PTD's and PTE's */
-#define SRMMU_ET_MASK 0x3
-#define SRMMU_ET_INVALID 0x0
-#define SRMMU_ET_PTD 0x1
-#define SRMMU_ET_PTE 0x2
-#define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */
-
-/* Physical page extraction from PTP's and PTE's. */
-#define SRMMU_CTX_PMASK 0xfffffff0
-#define SRMMU_PTD_PMASK 0xfffffff0
-#define SRMMU_PTE_PMASK 0xffffff00
-
-/* The pte non-page bits. Some notes:
- * 1) cache, dirty, valid, and ref are frobbable
- * for both supervisor and user pages.
- * 2) exec and write will only give the desired effect
- * on user pages
- * 3) use priv and priv_readonly for changing the
- * characteristics of supervisor ptes
- */
-#define SRMMU_CACHE 0x80
-#define SRMMU_DIRTY 0x40
-#define SRMMU_REF 0x20
-#define SRMMU_NOREAD 0x10
-#define SRMMU_EXEC 0x08
-#define SRMMU_WRITE 0x04
-#define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */
-#define SRMMU_PRIV 0x1c
-#define SRMMU_PRIV_RDONLY 0x18
-
-#define SRMMU_FILE 0x40 /* Implemented in software */
-
-#define SRMMU_PTE_FILE_SHIFT 8 /* == 32-PTE_FILE_MAX_BITS */
-
-#define SRMMU_CHG_MASK (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
-
-/* SRMMU swap entry encoding
- *
- * We use 5 bits for the type and 19 for the offset. This gives us
- * 32 swapfiles of 4GB each. Encoding looks like:
- *
- * oooooooooooooooooootttttRRRRRRRR
- * fedcba9876543210fedcba9876543210
- *
- * The bottom 8 bits are reserved for protection and status bits, especially
- * FILE and PRESENT.
- */
-#define SRMMU_SWP_TYPE_MASK 0x1f
-#define SRMMU_SWP_TYPE_SHIFT SRMMU_PTE_FILE_SHIFT
-#define SRMMU_SWP_OFF_MASK 0x7ffff
-#define SRMMU_SWP_OFF_SHIFT (SRMMU_PTE_FILE_SHIFT + 5)
-
-/* Some day I will implement true fine grained access bits for
- * user pages because the SRMMU gives us the capabilities to
- * enforce all the protection levels that vma's can have.
- * XXX But for now...
- */
-#define SRMMU_PAGE_NONE __pgprot(SRMMU_CACHE | \
- SRMMU_PRIV | SRMMU_REF)
-#define SRMMU_PAGE_SHARED __pgprot(SRMMU_VALID | SRMMU_CACHE | \
- SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
-#define SRMMU_PAGE_COPY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
- SRMMU_EXEC | SRMMU_REF)
-#define SRMMU_PAGE_RDONLY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
- SRMMU_EXEC | SRMMU_REF)
-#define SRMMU_PAGE_KERNEL __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
- SRMMU_DIRTY | SRMMU_REF)
-
-/* SRMMU Register addresses in ASI 0x4. These are valid for all
- * current SRMMU implementations that exist.
- */
-#define SRMMU_CTRL_REG 0x00000000
-#define SRMMU_CTXTBL_PTR 0x00000100
-#define SRMMU_CTX_REG 0x00000200
-#define SRMMU_FAULT_STATUS 0x00000300
-#define SRMMU_FAULT_ADDR 0x00000400
-
-#define WINDOW_FLUSH(tmp1, tmp2) \
- mov 0, tmp1; \
-98: ld [%g6 + TI_UWINMASK], tmp2; \
- orcc %g0, tmp2, %g0; \
- add tmp1, 1, tmp1; \
- bne 98b; \
- save %sp, -64, %sp; \
-99: subcc tmp1, 1, tmp1; \
- bne 99b; \
- restore %g0, %g0, %g0;
-
-#ifndef __ASSEMBLY__
-
-/* This makes sense. Honest it does - Anton */
-/* XXX Yes but it's ugly as sin. FIXME. -KMW */
-extern void *srmmu_nocache_pool;
-#define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
-#define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
-#define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
-
-/* Accessing the MMU control register. */
-static inline unsigned int srmmu_get_mmureg(void)
-{
- unsigned int retval;
- __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
- "=r" (retval) :
- "i" (ASI_M_MMUREGS));
- return retval;
-}
-
-static inline void srmmu_set_mmureg(unsigned long regval)
-{
- __asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
- "r" (regval), "i" (ASI_M_MMUREGS) : "memory");
-
-}
-
-static inline void srmmu_set_ctable_ptr(unsigned long paddr)
-{
- paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
- __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
- "r" (paddr), "r" (SRMMU_CTXTBL_PTR),
- "i" (ASI_M_MMUREGS) :
- "memory");
-}
-
-static inline unsigned long srmmu_get_ctable_ptr(void)
-{
- unsigned int retval;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t" :
- "=r" (retval) :
- "r" (SRMMU_CTXTBL_PTR),
- "i" (ASI_M_MMUREGS));
- return (retval & SRMMU_CTX_PMASK) << 4;
-}
-
-static inline void srmmu_set_context(int context)
-{
- __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
- "r" (context), "r" (SRMMU_CTX_REG),
- "i" (ASI_M_MMUREGS) : "memory");
-}
-
-static inline int srmmu_get_context(void)
-{
- register int retval;
- __asm__ __volatile__("lda [%1] %2, %0\n\t" :
- "=r" (retval) :
- "r" (SRMMU_CTX_REG),
- "i" (ASI_M_MMUREGS));
- return retval;
-}
-
-static inline unsigned int srmmu_get_fstatus(void)
-{
- unsigned int retval;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t" :
- "=r" (retval) :
- "r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS));
- return retval;
-}
-
-static inline unsigned int srmmu_get_faddr(void)
-{
- unsigned int retval;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t" :
- "=r" (retval) :
- "r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS));
- return retval;
-}
-
-/* This is guaranteed on all SRMMU's. */
-static inline void srmmu_flush_whole_tlb(void)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
- "r" (0x400), /* Flush entire TLB!! */
- "i" (ASI_M_FLUSH_PROBE) : "memory");
-
-}
-
-/* These flush types are not available on all chips... */
-static inline void srmmu_flush_tlb_ctx(void)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
- "r" (0x300), /* Flush TLB ctx.. */
- "i" (ASI_M_FLUSH_PROBE) : "memory");
-
-}
-
-static inline void srmmu_flush_tlb_region(unsigned long addr)
-{
- addr &= SRMMU_PGDIR_MASK;
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
- "r" (addr | 0x200), /* Flush TLB region.. */
- "i" (ASI_M_FLUSH_PROBE) : "memory");
-
-}
-
-
-static inline void srmmu_flush_tlb_segment(unsigned long addr)
-{
- addr &= SRMMU_REAL_PMD_MASK;
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
- "r" (addr | 0x100), /* Flush TLB segment.. */
- "i" (ASI_M_FLUSH_PROBE) : "memory");
-
-}
-
-static inline void srmmu_flush_tlb_page(unsigned long page)
-{
- page &= PAGE_MASK;
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
- "r" (page), /* Flush TLB page.. */
- "i" (ASI_M_FLUSH_PROBE) : "memory");
-
-}
-
-static inline unsigned long srmmu_hwprobe(unsigned long vaddr)
-{
- unsigned long retval;
-
- vaddr &= PAGE_MASK;
- __asm__ __volatile__("lda [%1] %2, %0\n\t" :
- "=r" (retval) :
- "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
-
- return retval;
-}
-
-static inline int
-srmmu_get_pte (unsigned long addr)
-{
- register unsigned long entry;
-
- __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
- "=r" (entry):
- "r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
- return entry;
-}
-
-extern unsigned long (*srmmu_read_physical)(unsigned long paddr);
-extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word);
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(_SPARC_PGTSRMMU_H) */
+++ /dev/null
-/*
- * pgtsun4.h: Sun4 specific pgtable.h defines and code.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-#ifndef _SPARC_PGTSUN4C_H
-#define _SPARC_PGTSUN4C_H
-
-#include <asm/contregs.h>
-
-/* PMD_SHIFT determines the size of the area a second-level page table can map */
-#define SUN4C_PMD_SHIFT 23
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define SUN4C_PGDIR_SHIFT 23
-#define SUN4C_PGDIR_SIZE (1UL << SUN4C_PGDIR_SHIFT)
-#define SUN4C_PGDIR_MASK (~(SUN4C_PGDIR_SIZE-1))
-#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
-
-/* To represent how the sun4c mmu really lays things out. */
-#define SUN4C_REAL_PGDIR_SHIFT 18
-#define SUN4C_REAL_PGDIR_SIZE (1UL << SUN4C_REAL_PGDIR_SHIFT)
-#define SUN4C_REAL_PGDIR_MASK (~(SUN4C_REAL_PGDIR_SIZE-1))
-#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
-
-/* 19 bit PFN on sun4 */
-#define SUN4C_PFN_MASK 0x7ffff
-
-/* Don't increase these unless the structures in sun4c.c are fixed */
-#define SUN4C_MAX_SEGMAPS 256
-#define SUN4C_MAX_CONTEXTS 16
-
-/*
- * To be efficient, and not have to worry about allocating such
- * a huge pgd, we make the kernel sun4c tables each hold 1024
- * entries and the pgd similarly just like the i386 tables.
- */
-#define SUN4C_PTRS_PER_PTE 1024
-#define SUN4C_PTRS_PER_PMD 1
-#define SUN4C_PTRS_PER_PGD 1024
-
-/*
- * Sparc SUN4C pte fields.
- */
-#define _SUN4C_PAGE_VALID 0x80000000
-#define _SUN4C_PAGE_SILENT_READ 0x80000000 /* synonym */
-#define _SUN4C_PAGE_DIRTY 0x40000000
-#define _SUN4C_PAGE_SILENT_WRITE 0x40000000 /* synonym */
-#define _SUN4C_PAGE_PRIV 0x20000000 /* privileged page */
-#define _SUN4C_PAGE_NOCACHE 0x10000000 /* non-cacheable page */
-#define _SUN4C_PAGE_PRESENT 0x08000000 /* implemented in software */
-#define _SUN4C_PAGE_IO 0x04000000 /* I/O page */
-#define _SUN4C_PAGE_FILE 0x02000000 /* implemented in software */
-#define _SUN4C_PAGE_READ 0x00800000 /* implemented in software */
-#define _SUN4C_PAGE_WRITE 0x00400000 /* implemented in software */
-#define _SUN4C_PAGE_ACCESSED 0x00200000 /* implemented in software */
-#define _SUN4C_PAGE_MODIFIED 0x00100000 /* implemented in software */
-
-#define _SUN4C_READABLE (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
- _SUN4C_PAGE_ACCESSED)
-#define _SUN4C_WRITEABLE (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
- _SUN4C_PAGE_MODIFIED)
-
-#define _SUN4C_PAGE_CHG_MASK (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
-
-#define SUN4C_PAGE_NONE __pgprot(_SUN4C_PAGE_PRESENT)
-#define SUN4C_PAGE_SHARED __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
- _SUN4C_PAGE_WRITE)
-#define SUN4C_PAGE_COPY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
-#define SUN4C_PAGE_READONLY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
-#define SUN4C_PAGE_KERNEL __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
- _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
-
-/* SUN4C swap entry encoding
- *
- * We use 5 bits for the type and 19 for the offset. This gives us
- * 32 swapfiles of 4GB each. Encoding looks like:
- *
- * RRRRRRRRooooooooooooooooooottttt
- * fedcba9876543210fedcba9876543210
- *
- * The top 8 bits are reserved for protection and status bits, especially
- * FILE and PRESENT.
- */
-#define SUN4C_SWP_TYPE_MASK 0x1f
-#define SUN4C_SWP_OFF_MASK 0x7ffff
-#define SUN4C_SWP_OFF_SHIFT 5
-
-#ifndef __ASSEMBLY__
-
-static inline unsigned long sun4c_get_synchronous_error(void)
-{
- unsigned long sync_err;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t" :
- "=r" (sync_err) :
- "r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
- return sync_err;
-}
-
-static inline unsigned long sun4c_get_synchronous_address(void)
-{
- unsigned long sync_addr;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t" :
- "=r" (sync_addr) :
- "r" (AC_SYNC_VA), "i" (ASI_CONTROL));
- return sync_addr;
-}
-
-/* SUN4 pte, segmap, and context manipulation */
-static inline unsigned long sun4c_get_segmap(unsigned long addr)
-{
- register unsigned long entry;
-
- __asm__ __volatile__("\n\tlduha [%1] %2, %0\n\t" :
- "=r" (entry) :
- "r" (addr), "i" (ASI_SEGMAP));
- return entry;
-}
-
-static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
-{
- __asm__ __volatile__("\n\tstha %1, [%0] %2; nop; nop; nop;\n\t" : :
- "r" (addr), "r" (entry),
- "i" (ASI_SEGMAP)
- : "memory");
-}
-
-static inline unsigned long sun4c_get_pte(unsigned long addr)
-{
- register unsigned long entry;
-
- __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" :
- "=r" (entry) :
- "r" (addr), "i" (ASI_PTE));
- return entry;
-}
-
-static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
-{
- __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
- "r" (addr),
- "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
- : "memory");
-}
-
-static inline int sun4c_get_context(void)
-{
- register int ctx;
-
- __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
- "=r" (ctx) :
- "r" (AC_CONTEXT), "i" (ASI_CONTROL));
-
- return ctx;
-}
-
-static inline int sun4c_set_context(int ctx)
-{
- __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
- "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
- : "memory");
-
- return ctx;
-}
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(_SPARC_PGTSUN4_H) */
+++ /dev/null
-/*
- * pgtsun4c.h: Sun4c specific pgtable.h defines and code.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-#ifndef _SPARC_PGTSUN4C_H
-#define _SPARC_PGTSUN4C_H
-
-#include <asm/contregs.h>
-
-/* PMD_SHIFT determines the size of the area a second-level page table can map */
-#define SUN4C_PMD_SHIFT 22
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define SUN4C_PGDIR_SHIFT 22
-#define SUN4C_PGDIR_SIZE (1UL << SUN4C_PGDIR_SHIFT)
-#define SUN4C_PGDIR_MASK (~(SUN4C_PGDIR_SIZE-1))
-#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
-
-/* To represent how the sun4c mmu really lays things out. */
-#define SUN4C_REAL_PGDIR_SHIFT 18
-#define SUN4C_REAL_PGDIR_SIZE (1UL << SUN4C_REAL_PGDIR_SHIFT)
-#define SUN4C_REAL_PGDIR_MASK (~(SUN4C_REAL_PGDIR_SIZE-1))
-#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
-
-/* 16 bit PFN on sun4c */
-#define SUN4C_PFN_MASK 0xffff
-
-/* Don't increase these unless the structures in sun4c.c are fixed */
-#define SUN4C_MAX_SEGMAPS 256
-#define SUN4C_MAX_CONTEXTS 16
-
-/*
- * To be efficient, and not have to worry about allocating such
- * a huge pgd, we make the kernel sun4c tables each hold 1024
- * entries and the pgd similarly just like the i386 tables.
- */
-#define SUN4C_PTRS_PER_PTE 1024
-#define SUN4C_PTRS_PER_PMD 1
-#define SUN4C_PTRS_PER_PGD 1024
-
-/*
- * Sparc SUN4C pte fields.
- */
-#define _SUN4C_PAGE_VALID 0x80000000
-#define _SUN4C_PAGE_SILENT_READ 0x80000000 /* synonym */
-#define _SUN4C_PAGE_DIRTY 0x40000000
-#define _SUN4C_PAGE_SILENT_WRITE 0x40000000 /* synonym */
-#define _SUN4C_PAGE_PRIV 0x20000000 /* privileged page */
-#define _SUN4C_PAGE_NOCACHE 0x10000000 /* non-cacheable page */
-#define _SUN4C_PAGE_PRESENT 0x08000000 /* implemented in software */
-#define _SUN4C_PAGE_IO 0x04000000 /* I/O page */
-#define _SUN4C_PAGE_FILE 0x02000000 /* implemented in software */
-#define _SUN4C_PAGE_READ 0x00800000 /* implemented in software */
-#define _SUN4C_PAGE_WRITE 0x00400000 /* implemented in software */
-#define _SUN4C_PAGE_ACCESSED 0x00200000 /* implemented in software */
-#define _SUN4C_PAGE_MODIFIED 0x00100000 /* implemented in software */
-
-#define _SUN4C_READABLE (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
- _SUN4C_PAGE_ACCESSED)
-#define _SUN4C_WRITEABLE (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
- _SUN4C_PAGE_MODIFIED)
-
-#define _SUN4C_PAGE_CHG_MASK (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
-
-#define SUN4C_PAGE_NONE __pgprot(_SUN4C_PAGE_PRESENT)
-#define SUN4C_PAGE_SHARED __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
- _SUN4C_PAGE_WRITE)
-#define SUN4C_PAGE_COPY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
-#define SUN4C_PAGE_READONLY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
-#define SUN4C_PAGE_KERNEL __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
- _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
-
-/* SUN4C swap entry encoding
- *
- * We use 5 bits for the type and 19 for the offset. This gives us
- * 32 swapfiles of 4GB each. Encoding looks like:
- *
- * RRRRRRRRooooooooooooooooooottttt
- * fedcba9876543210fedcba9876543210
- *
- * The top 8 bits are reserved for protection and status bits, especially
- * FILE and PRESENT.
- */
-#define SUN4C_SWP_TYPE_MASK 0x1f
-#define SUN4C_SWP_OFF_MASK 0x7ffff
-#define SUN4C_SWP_OFF_SHIFT 5
-
-#ifndef __ASSEMBLY__
-
-static inline unsigned long sun4c_get_synchronous_error(void)
-{
- unsigned long sync_err;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t" :
- "=r" (sync_err) :
- "r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
- return sync_err;
-}
-
-static inline unsigned long sun4c_get_synchronous_address(void)
-{
- unsigned long sync_addr;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t" :
- "=r" (sync_addr) :
- "r" (AC_SYNC_VA), "i" (ASI_CONTROL));
- return sync_addr;
-}
-
-/* SUN4C pte, segmap, and context manipulation */
-static inline unsigned long sun4c_get_segmap(unsigned long addr)
-{
- register unsigned long entry;
-
- __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
- "=r" (entry) :
- "r" (addr), "i" (ASI_SEGMAP));
-
- return entry;
-}
-
-static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
-{
-
- __asm__ __volatile__("\n\tstba %1, [%0] %2; nop; nop; nop;\n\t" : :
- "r" (addr), "r" (entry),
- "i" (ASI_SEGMAP)
- : "memory");
-}
-
-static inline unsigned long sun4c_get_pte(unsigned long addr)
-{
- register unsigned long entry;
-
- __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" :
- "=r" (entry) :
- "r" (addr), "i" (ASI_PTE));
- return entry;
-}
-
-static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
-{
- __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
- "r" (addr),
- "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
- : "memory");
-}
-
-static inline int sun4c_get_context(void)
-{
- register int ctx;
-
- __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
- "=r" (ctx) :
- "r" (AC_CONTEXT), "i" (ASI_CONTROL));
-
- return ctx;
-}
-
-static inline int sun4c_set_context(int ctx)
-{
- __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
- "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
- : "memory");
-
- return ctx;
-}
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(_SPARC_PGTSUN4C_H) */
+++ /dev/null
-#ifndef _SPARC64_PIL_H
-#define _SPARC64_PIL_H
-
-/* To avoid some locking problems, we hard allocate certain PILs
- * for SMP cross call messages that must do a etrap/rtrap.
- *
- * A local_irq_disable() does not block the cross call delivery, so
- * when SMP locking is an issue we reschedule the event into a PIL
- * interrupt which is blocked by local_irq_disable().
- *
- * In fact any XCALL which has to etrap/rtrap has a problem because
- * it is difficult to prevent rtrap from running BH's, and that would
- * need to be done if the XCALL arrived while %pil==15.
- */
-#define PIL_SMP_CALL_FUNC 1
-#define PIL_SMP_RECEIVE_SIGNAL 2
-#define PIL_SMP_CAPTURE 3
-#define PIL_SMP_CTX_NEW_VERSION 4
-#define PIL_DEVICE_IRQ 5
-#define PIL_SMP_CALL_FUNC_SNGL 6
-
-#endif /* !(_SPARC64_PIL_H) */
+++ /dev/null
-#ifndef __SPARC_POLL_H
-#define __SPARC_POLL_H
-
-#define POLLWRNORM POLLOUT
-#define POLLWRBAND 256
-#define POLLMSG 512
-#define POLLREMOVE 1024
-#define POLLRDHUP 2048
-
-#include <asm-generic/poll.h>
-
-#endif
+++ /dev/null
-#ifndef ___ASM_SPARC_POSIX_TYPES_H
-#define ___ASM_SPARC_POSIX_TYPES_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/posix_types_64.h>
-#else
-#include <asm-sparc/posix_types_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef __ARCH_SPARC_POSIX_TYPES_H
-#define __ARCH_SPARC_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned int __kernel_size_t;
-typedef int __kernel_ssize_t;
-typedef long int __kernel_ptrdiff_t;
-typedef long __kernel_time_t;
-typedef long __kernel_suseconds_t;
-typedef long __kernel_clock_t;
-typedef int __kernel_pid_t;
-typedef unsigned short __kernel_ipc_pid_t;
-typedef unsigned short __kernel_uid_t;
-typedef unsigned short __kernel_gid_t;
-typedef unsigned long __kernel_ino_t;
-typedef unsigned short __kernel_mode_t;
-typedef unsigned short __kernel_umode_t;
-typedef short __kernel_nlink_t;
-typedef long __kernel_daddr_t;
-typedef long __kernel_off_t;
-typedef char * __kernel_caddr_t;
-typedef unsigned short __kernel_uid16_t;
-typedef unsigned short __kernel_gid16_t;
-typedef unsigned int __kernel_uid32_t;
-typedef unsigned int __kernel_gid32_t;
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-typedef unsigned short __kernel_old_dev_t;
-typedef int __kernel_clockid_t;
-typedef int __kernel_timer_t;
-
-#ifdef __GNUC__
-typedef long long __kernel_loff_t;
-#endif
-
-typedef struct {
- int val[2];
-} __kernel_fsid_t;
-
-#if defined(__KERNEL__)
-
-#undef __FD_SET
-static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
-}
-
-#undef __FD_CLR
-static inline void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
-}
-
-#undef __FD_ISSET
-static inline int __FD_ISSET(unsigned long fd, __const__ __kernel_fd_set *p)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
-}
-
-/*
- * This will unroll the loop for the normal constant cases (8 or 32 longs,
- * for 256 and 1024-bit fd_sets respectively)
- */
-#undef __FD_ZERO
-static inline void __FD_ZERO(__kernel_fd_set *p)
-{
- unsigned long *tmp = p->fds_bits;
- int i;
-
- if (__builtin_constant_p(__FDSET_LONGS)) {
- switch (__FDSET_LONGS) {
- case 32:
- tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
- tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
- tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
- tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
- tmp[16] = 0; tmp[17] = 0; tmp[18] = 0; tmp[19] = 0;
- tmp[20] = 0; tmp[21] = 0; tmp[22] = 0; tmp[23] = 0;
- tmp[24] = 0; tmp[25] = 0; tmp[26] = 0; tmp[27] = 0;
- tmp[28] = 0; tmp[29] = 0; tmp[30] = 0; tmp[31] = 0;
- return;
- case 16:
- tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
- tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
- tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
- tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
- return;
- case 8:
- tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
- tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
- return;
- case 4:
- tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
- return;
- }
- }
- i = __FDSET_LONGS;
- while (i) {
- i--;
- *tmp = 0;
- tmp++;
- }
-}
-
-#endif /* defined(__KERNEL__) */
-
-#endif /* !(__ARCH_SPARC_POSIX_TYPES_H) */
+++ /dev/null
-#ifndef __ARCH_SPARC64_POSIX_TYPES_H
-#define __ARCH_SPARC64_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned long __kernel_size_t;
-typedef long __kernel_ssize_t;
-typedef long __kernel_ptrdiff_t;
-typedef long __kernel_time_t;
-typedef long __kernel_clock_t;
-typedef int __kernel_pid_t;
-typedef int __kernel_ipc_pid_t;
-typedef unsigned int __kernel_uid_t;
-typedef unsigned int __kernel_gid_t;
-typedef unsigned long __kernel_ino_t;
-typedef unsigned int __kernel_mode_t;
-typedef unsigned short __kernel_umode_t;
-typedef unsigned int __kernel_nlink_t;
-typedef int __kernel_daddr_t;
-typedef long __kernel_off_t;
-typedef char * __kernel_caddr_t;
-typedef unsigned short __kernel_uid16_t;
-typedef unsigned short __kernel_gid16_t;
-typedef int __kernel_clockid_t;
-typedef int __kernel_timer_t;
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-typedef __kernel_uid_t __kernel_uid32_t;
-typedef __kernel_gid_t __kernel_gid32_t;
-
-typedef unsigned int __kernel_old_dev_t;
-
-/* Note this piece of asymmetry from the v9 ABI. */
-typedef int __kernel_suseconds_t;
-
-#ifdef __GNUC__
-typedef long long __kernel_loff_t;
-#endif
-
-typedef struct {
- int val[2];
-} __kernel_fsid_t;
-
-#if defined(__KERNEL__)
-
-#undef __FD_SET
-static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
-}
-
-#undef __FD_CLR
-static inline void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
-}
-
-#undef __FD_ISSET
-static inline int __FD_ISSET(unsigned long fd, __const__ __kernel_fd_set *p)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
-}
-
-/*
- * This will unroll the loop for the normal constant cases (8 or 32 longs,
- * for 256 and 1024-bit fd_sets respectively)
- */
-#undef __FD_ZERO
-static inline void __FD_ZERO(__kernel_fd_set *p)
-{
- unsigned long *tmp = p->fds_bits;
- int i;
-
- if (__builtin_constant_p(__FDSET_LONGS)) {
- switch (__FDSET_LONGS) {
- case 32:
- tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
- tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
- tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
- tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
- tmp[16] = 0; tmp[17] = 0; tmp[18] = 0; tmp[19] = 0;
- tmp[20] = 0; tmp[21] = 0; tmp[22] = 0; tmp[23] = 0;
- tmp[24] = 0; tmp[25] = 0; tmp[26] = 0; tmp[27] = 0;
- tmp[28] = 0; tmp[29] = 0; tmp[30] = 0; tmp[31] = 0;
- return;
- case 16:
- tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
- tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
- tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
- tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
- return;
- case 8:
- tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
- tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
- return;
- case 4:
- tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
- return;
- }
- }
- i = __FDSET_LONGS;
- while (i) {
- i--;
- *tmp = 0;
- tmp++;
- }
-}
-
-#endif /* defined(__KERNEL__) */
-
-#endif /* !(__ARCH_SPARC64_POSIX_TYPES_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_PROCESSOR_H
-#define ___ASM_SPARC_PROCESSOR_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/processor_64.h>
-#else
-#include <asm-sparc/processor_32.h>
-#endif
-#endif
+++ /dev/null
-/* include/asm-sparc/processor.h
- *
- * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef __ASM_SPARC_PROCESSOR_H
-#define __ASM_SPARC_PROCESSOR_H
-
-/*
- * Sparc32 implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ void *pc; __asm__("sethi %%hi(1f), %0; or %0, %%lo(1f), %0;\n1:" : "=r" (pc)); pc; })
-
-#include <asm/psr.h>
-#include <asm/ptrace.h>
-#include <asm/head.h>
-#include <asm/signal.h>
-#include <asm/btfixup.h>
-#include <asm/page.h>
-
-/*
- * The sparc has no problems with write protection
- */
-#define wp_works_ok 1
-#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
-
-/* Whee, this is STACK_TOP + PAGE_SIZE and the lowest kernel address too...
- * That one page is used to protect kernel from intruders, so that
- * we can make our access_ok test faster
- */
-#define TASK_SIZE PAGE_OFFSET
-#ifdef __KERNEL__
-#define STACK_TOP (PAGE_OFFSET - PAGE_SIZE)
-#define STACK_TOP_MAX STACK_TOP
-#endif /* __KERNEL__ */
-
-struct task_struct;
-
-#ifdef __KERNEL__
-struct fpq {
- unsigned long *insn_addr;
- unsigned long insn;
-};
-#endif
-
-typedef struct {
- int seg;
-} mm_segment_t;
-
-/* The Sparc processor specific thread struct. */
-struct thread_struct {
- struct pt_regs *kregs;
- unsigned int _pad1;
-
- /* Special child fork kpsr/kwim values. */
- unsigned long fork_kpsr __attribute__ ((aligned (8)));
- unsigned long fork_kwim;
-
- /* Floating point regs */
- unsigned long float_regs[32] __attribute__ ((aligned (8)));
- unsigned long fsr;
- unsigned long fpqdepth;
- struct fpq fpqueue[16];
- unsigned long flags;
- mm_segment_t current_ds;
-};
-
-#define SPARC_FLAG_KTHREAD 0x1 /* task is a kernel thread */
-#define SPARC_FLAG_UNALIGNED 0x2 /* is allowed to do unaligned accesses */
-
-#define INIT_THREAD { \
- .flags = SPARC_FLAG_KTHREAD, \
- .current_ds = KERNEL_DS, \
-}
-
-/* Return saved PC of a blocked thread. */
-extern unsigned long thread_saved_pc(struct task_struct *t);
-
-/* Do necessary setup to start up a newly executed thread. */
-static inline void start_thread(struct pt_regs * regs, unsigned long pc,
- unsigned long sp)
-{
- register unsigned long zero asm("g1");
-
- regs->psr = (regs->psr & (PSR_CWP)) | PSR_S;
- regs->pc = ((pc & (~3)) - 4);
- regs->npc = regs->pc + 4;
- regs->y = 0;
- zero = 0;
- __asm__ __volatile__("std\t%%g0, [%0 + %3 + 0x00]\n\t"
- "std\t%%g0, [%0 + %3 + 0x08]\n\t"
- "std\t%%g0, [%0 + %3 + 0x10]\n\t"
- "std\t%%g0, [%0 + %3 + 0x18]\n\t"
- "std\t%%g0, [%0 + %3 + 0x20]\n\t"
- "std\t%%g0, [%0 + %3 + 0x28]\n\t"
- "std\t%%g0, [%0 + %3 + 0x30]\n\t"
- "st\t%1, [%0 + %3 + 0x38]\n\t"
- "st\t%%g0, [%0 + %3 + 0x3c]"
- : /* no outputs */
- : "r" (regs),
- "r" (sp - sizeof(struct reg_window)),
- "r" (zero),
- "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))
- : "memory");
-}
-
-/* Free all resources held by a thread. */
-#define release_thread(tsk) do { } while(0)
-extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
-
-/* Prepare to copy thread state - unlazy all lazy status */
-#define prepare_to_copy(tsk) do { } while (0)
-
-extern unsigned long get_wchan(struct task_struct *);
-
-#define KSTK_EIP(tsk) ((tsk)->thread.kregs->pc)
-#define KSTK_ESP(tsk) ((tsk)->thread.kregs->u_regs[UREG_FP])
-
-#ifdef __KERNEL__
-
-extern struct task_struct *last_task_used_math;
-
-#define cpu_relax() barrier()
-
-#endif
-
-#endif /* __ASM_SPARC_PROCESSOR_H */
+++ /dev/null
-/*
- * include/asm-sparc64/processor.h
- *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef __ASM_SPARC64_PROCESSOR_H
-#define __ASM_SPARC64_PROCESSOR_H
-
-/*
- * Sparc64 implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; })
-
-#include <asm/asi.h>
-#include <asm/pstate.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-
-/* The sparc has no problems with write protection */
-#define wp_works_ok 1
-#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
-
-/*
- * User lives in his very own context, and cannot reference us. Note
- * that TASK_SIZE is a misnomer, it really gives maximum user virtual
- * address that the kernel will allocate out.
- *
- * XXX No longer using virtual page tables, kill this upper limit...
- */
-#define VA_BITS 44
-#ifndef __ASSEMBLY__
-#define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
-#else
-#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
-#endif
-
-#define TASK_SIZE ((unsigned long)-VPTE_SIZE)
-#define TASK_SIZE_OF(tsk) \
- (test_tsk_thread_flag(tsk,TIF_32BIT) ? \
- (1UL << 32UL) : TASK_SIZE)
-#ifdef __KERNEL__
-
-#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
-#define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL))
-
-#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
- STACK_TOP32 : STACK_TOP64)
-
-#define STACK_TOP_MAX STACK_TOP64
-
-#endif
-
-#ifndef __ASSEMBLY__
-
-typedef struct {
- unsigned char seg;
-} mm_segment_t;
-
-/* The Sparc processor specific thread struct. */
-/* XXX This should die, everything can go into thread_info now. */
-struct thread_struct {
-#ifdef CONFIG_DEBUG_SPINLOCK
- /* How many spinlocks held by this thread.
- * Used with spin lock debugging to catch tasks
- * sleeping illegally with locks held.
- */
- int smp_lock_count;
- unsigned int smp_lock_pc;
-#else
- int dummy; /* f'in gcc bug... */
-#endif
-};
-
-#endif /* !(__ASSEMBLY__) */
-
-#ifndef CONFIG_DEBUG_SPINLOCK
-#define INIT_THREAD { \
- 0, \
-}
-#else /* CONFIG_DEBUG_SPINLOCK */
-#define INIT_THREAD { \
-/* smp_lock_count, smp_lock_pc, */ \
- 0, 0, \
-}
-#endif /* !(CONFIG_DEBUG_SPINLOCK) */
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-/* Return saved PC of a blocked thread. */
-struct task_struct;
-extern unsigned long thread_saved_pc(struct task_struct *);
-
-/* On Uniprocessor, even in RMO processes see TSO semantics */
-#ifdef CONFIG_SMP
-#define TSTATE_INITIAL_MM TSTATE_TSO
-#else
-#define TSTATE_INITIAL_MM TSTATE_RMO
-#endif
-
-/* Do necessary setup to start up a newly executed thread. */
-#define start_thread(regs, pc, sp) \
-do { \
- unsigned long __asi = ASI_PNF; \
- regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \
- regs->tpc = ((pc & (~3)) - 4); \
- regs->tnpc = regs->tpc + 4; \
- regs->y = 0; \
- set_thread_wstate(1 << 3); \
- if (current_thread_info()->utraps) { \
- if (*(current_thread_info()->utraps) < 2) \
- kfree(current_thread_info()->utraps); \
- else \
- (*(current_thread_info()->utraps))--; \
- current_thread_info()->utraps = NULL; \
- } \
- __asm__ __volatile__( \
- "stx %%g0, [%0 + %2 + 0x00]\n\t" \
- "stx %%g0, [%0 + %2 + 0x08]\n\t" \
- "stx %%g0, [%0 + %2 + 0x10]\n\t" \
- "stx %%g0, [%0 + %2 + 0x18]\n\t" \
- "stx %%g0, [%0 + %2 + 0x20]\n\t" \
- "stx %%g0, [%0 + %2 + 0x28]\n\t" \
- "stx %%g0, [%0 + %2 + 0x30]\n\t" \
- "stx %%g0, [%0 + %2 + 0x38]\n\t" \
- "stx %%g0, [%0 + %2 + 0x40]\n\t" \
- "stx %%g0, [%0 + %2 + 0x48]\n\t" \
- "stx %%g0, [%0 + %2 + 0x50]\n\t" \
- "stx %%g0, [%0 + %2 + 0x58]\n\t" \
- "stx %%g0, [%0 + %2 + 0x60]\n\t" \
- "stx %%g0, [%0 + %2 + 0x68]\n\t" \
- "stx %1, [%0 + %2 + 0x70]\n\t" \
- "stx %%g0, [%0 + %2 + 0x78]\n\t" \
- "wrpr %%g0, (1 << 3), %%wstate\n\t" \
- : \
- : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
- "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
-} while (0)
-
-#define start_thread32(regs, pc, sp) \
-do { \
- unsigned long __asi = ASI_PNF; \
- pc &= 0x00000000ffffffffUL; \
- sp &= 0x00000000ffffffffUL; \
- regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \
- regs->tpc = ((pc & (~3)) - 4); \
- regs->tnpc = regs->tpc + 4; \
- regs->y = 0; \
- set_thread_wstate(2 << 3); \
- if (current_thread_info()->utraps) { \
- if (*(current_thread_info()->utraps) < 2) \
- kfree(current_thread_info()->utraps); \
- else \
- (*(current_thread_info()->utraps))--; \
- current_thread_info()->utraps = NULL; \
- } \
- __asm__ __volatile__( \
- "stx %%g0, [%0 + %2 + 0x00]\n\t" \
- "stx %%g0, [%0 + %2 + 0x08]\n\t" \
- "stx %%g0, [%0 + %2 + 0x10]\n\t" \
- "stx %%g0, [%0 + %2 + 0x18]\n\t" \
- "stx %%g0, [%0 + %2 + 0x20]\n\t" \
- "stx %%g0, [%0 + %2 + 0x28]\n\t" \
- "stx %%g0, [%0 + %2 + 0x30]\n\t" \
- "stx %%g0, [%0 + %2 + 0x38]\n\t" \
- "stx %%g0, [%0 + %2 + 0x40]\n\t" \
- "stx %%g0, [%0 + %2 + 0x48]\n\t" \
- "stx %%g0, [%0 + %2 + 0x50]\n\t" \
- "stx %%g0, [%0 + %2 + 0x58]\n\t" \
- "stx %%g0, [%0 + %2 + 0x60]\n\t" \
- "stx %%g0, [%0 + %2 + 0x68]\n\t" \
- "stx %1, [%0 + %2 + 0x70]\n\t" \
- "stx %%g0, [%0 + %2 + 0x78]\n\t" \
- "wrpr %%g0, (2 << 3), %%wstate\n\t" \
- : \
- : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
- "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
-} while (0)
-
-/* Free all resources held by a thread. */
-#define release_thread(tsk) do { } while (0)
-
-/* Prepare to copy thread state - unlazy all lazy status */
-#define prepare_to_copy(tsk) do { } while (0)
-
-extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
-
-extern unsigned long get_wchan(struct task_struct *task);
-
-#define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
-#define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc)
-#define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP])
-
-#define cpu_relax() barrier()
-
-/* Prefetch support. This is tuned for UltraSPARC-III and later.
- * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
- * a shallower prefetch queue than later chips.
- */
-#define ARCH_HAS_PREFETCH
-#define ARCH_HAS_PREFETCHW
-#define ARCH_HAS_SPINLOCK_PREFETCH
-
-static inline void prefetch(const void *x)
-{
- /* We do not use the read prefetch mnemonic because that
- * prefetches into the prefetch-cache which only is accessible
- * by floating point operations in UltraSPARC-III and later.
- * By contrast, "#one_write" prefetches into the L2 cache
- * in shared state.
- */
- __asm__ __volatile__("prefetch [%0], #one_write"
- : /* no outputs */
- : "r" (x));
-}
-
-static inline void prefetchw(const void *x)
-{
- /* The most optimal prefetch to use for writes is
- * "#n_writes". This brings the cacheline into the
- * L2 cache in "owned" state.
- */
- __asm__ __volatile__("prefetch [%0], #n_writes"
- : /* no outputs */
- : "r" (x));
-}
-
-#define spin_lock_prefetch(x) prefetchw(x)
-
-#define HAVE_ARCH_PICK_MMAP_LAYOUT
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
+++ /dev/null
-#ifndef _SPARC_PROM_H
-#define _SPARC_PROM_H
-#ifdef __KERNEL__
-
-/*
- * Definitions for talking to the Open Firmware PROM on
- * Power Macintosh computers.
- *
- * Copyright (C) 1996-2005 Paul Mackerras.
- *
- * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp.
- * Updates for SPARC by David S. Miller
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/types.h>
-#include <linux/proc_fs.h>
-#include <asm/atomic.h>
-
-#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 2
-#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1
-
-#define of_compat_cmp(s1, s2, l) strncmp((s1), (s2), (l))
-#define of_prop_cmp(s1, s2) strcasecmp((s1), (s2))
-#define of_node_cmp(s1, s2) strcmp((s1), (s2))
-
-typedef u32 phandle;
-typedef u32 ihandle;
-
-struct property {
- char *name;
- int length;
- void *value;
- struct property *next;
- unsigned long _flags;
- unsigned int unique_id;
-};
-
-struct of_irq_controller;
-struct device_node {
- const char *name;
- const char *type;
- phandle node;
- char *path_component_name;
- char *full_name;
-
- struct property *properties;
- struct property *deadprops; /* removed properties */
- struct device_node *parent;
- struct device_node *child;
- struct device_node *sibling;
- struct device_node *next; /* next device of same type */
- struct device_node *allnext; /* next in list of all nodes */
- struct proc_dir_entry *pde; /* this node's proc directory */
- struct kref kref;
- unsigned long _flags;
- void *data;
- unsigned int unique_id;
-
- struct of_irq_controller *irq_trans;
-};
-
-struct of_irq_controller {
- unsigned int (*irq_build)(struct device_node *, unsigned int, void *);
- void *data;
-};
-
-#define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags)
-#define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags)
-
-extern struct device_node *of_find_node_by_cpuid(int cpuid);
-extern int of_set_property(struct device_node *node, const char *name, void *val, int len);
-extern int of_getintprop_default(struct device_node *np,
- const char *name,
- int def);
-extern int of_find_in_proplist(const char *list, const char *match, int len);
-#ifdef CONFIG_NUMA
-extern int of_node_to_nid(struct device_node *dp);
-#else
-#define of_node_to_nid(dp) (-1)
-#endif
-
-extern void prom_build_devicetree(void);
-
-/* Dummy ref counting routines - to be implemented later */
-static inline struct device_node *of_node_get(struct device_node *node)
-{
- return node;
-}
-static inline void of_node_put(struct device_node *node)
-{
-}
-
-/*
- * NB: This is here while we transition from using asm/prom.h
- * to linux/of.h
- */
-#include <linux/of.h>
-
-extern struct device_node *of_console_device;
-extern char *of_console_path;
-extern char *of_console_options;
-
-#endif /* __KERNEL__ */
-#endif /* _SPARC_PROM_H */
+++ /dev/null
-/*
- * psr.h: This file holds the macros for masking off various parts of
- * the processor status register on the Sparc. This is valid
- * for Version 8. On the V9 this is renamed to the PSTATE
- * register and its members are accessed as fields like
- * PSTATE.PRIV for the current CPU privilege level.
- *
- * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef __LINUX_SPARC_PSR_H
-#define __LINUX_SPARC_PSR_H
-
-/* The Sparc PSR fields are laid out as the following:
- *
- * ------------------------------------------------------------------------
- * | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP |
- * | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 |
- * ------------------------------------------------------------------------
- */
-#define PSR_CWP 0x0000001f /* current window pointer */
-#define PSR_ET 0x00000020 /* enable traps field */
-#define PSR_PS 0x00000040 /* previous privilege level */
-#define PSR_S 0x00000080 /* current privilege level */
-#define PSR_PIL 0x00000f00 /* processor interrupt level */
-#define PSR_EF 0x00001000 /* enable floating point */
-#define PSR_EC 0x00002000 /* enable co-processor */
-#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
-#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
-#define PSR_ICC 0x00f00000 /* integer condition codes */
-#define PSR_C 0x00100000 /* carry bit */
-#define PSR_V 0x00200000 /* overflow bit */
-#define PSR_Z 0x00400000 /* zero bit */
-#define PSR_N 0x00800000 /* negative bit */
-#define PSR_VERS 0x0f000000 /* cpu-version field */
-#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-/* Get the %psr register. */
-static inline unsigned int get_psr(void)
-{
- unsigned int psr;
- __asm__ __volatile__(
- "rd %%psr, %0\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- : "=r" (psr)
- : /* no inputs */
- : "memory");
-
- return psr;
-}
-
-static inline void put_psr(unsigned int new_psr)
-{
- __asm__ __volatile__(
- "wr %0, 0x0, %%psr\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- : /* no outputs */
- : "r" (new_psr)
- : "memory", "cc");
-}
-
-/* Get the %fsr register. Be careful, make sure the floating point
- * enable bit is set in the %psr when you execute this or you will
- * incur a trap.
- */
-
-extern unsigned int fsr_storage;
-
-static inline unsigned int get_fsr(void)
-{
- unsigned int fsr = 0;
-
- __asm__ __volatile__(
- "st %%fsr, %1\n\t"
- "ld %1, %0\n\t"
- : "=r" (fsr)
- : "m" (fsr_storage));
-
- return fsr;
-}
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* (__KERNEL__) */
-
-#endif /* !(__LINUX_SPARC_PSR_H) */
+++ /dev/null
-#ifndef _SPARC64_PSRCOMPAT_H
-#define _SPARC64_PSRCOMPAT_H
-
-#include <asm/pstate.h>
-
-/* Old 32-bit PSR fields for the compatibility conversion code. */
-#define PSR_CWP 0x0000001f /* current window pointer */
-#define PSR_ET 0x00000020 /* enable traps field */
-#define PSR_PS 0x00000040 /* previous privilege level */
-#define PSR_S 0x00000080 /* current privilege level */
-#define PSR_PIL 0x00000f00 /* processor interrupt level */
-#define PSR_EF 0x00001000 /* enable floating point */
-#define PSR_EC 0x00002000 /* enable co-processor */
-#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
-#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
-#define PSR_ICC 0x00f00000 /* integer condition codes */
-#define PSR_C 0x00100000 /* carry bit */
-#define PSR_V 0x00200000 /* overflow bit */
-#define PSR_Z 0x00400000 /* zero bit */
-#define PSR_N 0x00800000 /* negative bit */
-#define PSR_VERS 0x0f000000 /* cpu-version field */
-#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
-
-#define PSR_V8PLUS 0xff000000 /* fake impl/ver, meaning a 64bit CPU is present */
-#define PSR_XCC 0x000f0000 /* if PSR_V8PLUS, this is %xcc */
-
-static inline unsigned int tstate_to_psr(unsigned long tstate)
-{
- return ((tstate & TSTATE_CWP) |
- PSR_S |
- ((tstate & TSTATE_ICC) >> 12) |
- ((tstate & TSTATE_XCC) >> 20) |
- ((tstate & TSTATE_SYSCALL) ? PSR_SYSCALL : 0) |
- PSR_V8PLUS);
-}
-
-static inline unsigned long psr_to_tstate_icc(unsigned int psr)
-{
- unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12;
- if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS)
- tstate |= ((unsigned long)(psr & PSR_XCC)) << 20;
- return tstate;
-}
-
-#endif /* !(_SPARC64_PSRCOMPAT_H) */
+++ /dev/null
-#ifndef _SPARC64_PSTATE_H
-#define _SPARC64_PSTATE_H
-
-#include <linux/const.h>
-
-/* The V9 PSTATE Register (with SpitFire extensions).
- *
- * -----------------------------------------------------------------------
- * | Resv | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG |
- * -----------------------------------------------------------------------
- * 63 12 11 10 9 8 7 6 5 4 3 2 1 0
- */
-#define PSTATE_IG _AC(0x0000000000000800,UL) /* Interrupt Globals. */
-#define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals. */
-#define PSTATE_CLE _AC(0x0000000000000200,UL) /* Current Little Endian.*/
-#define PSTATE_TLE _AC(0x0000000000000100,UL) /* Trap Little Endian. */
-#define PSTATE_MM _AC(0x00000000000000c0,UL) /* Memory Model. */
-#define PSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder */
-#define PSTATE_PSO _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder */
-#define PSTATE_RMO _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/
-#define PSTATE_RED _AC(0x0000000000000020,UL) /* Reset Error Debug. */
-#define PSTATE_PEF _AC(0x0000000000000010,UL) /* Floating Point Enable.*/
-#define PSTATE_AM _AC(0x0000000000000008,UL) /* Address Mask. */
-#define PSTATE_PRIV _AC(0x0000000000000004,UL) /* Privilege. */
-#define PSTATE_IE _AC(0x0000000000000002,UL) /* Interrupt Enable. */
-#define PSTATE_AG _AC(0x0000000000000001,UL) /* Alternate Globals. */
-
-/* The V9 TSTATE Register (with SpitFire and Linux extensions).
- *
- * ---------------------------------------------------------------------
- * | Resv | GL | CCR | ASI | %pil | PSTATE | Resv | CWP |
- * ---------------------------------------------------------------------
- * 63 43 42 40 39 32 31 24 23 20 19 8 7 5 4 0
- */
-#define TSTATE_GL _AC(0x0000070000000000,UL) /* Global reg level */
-#define TSTATE_CCR _AC(0x000000ff00000000,UL) /* Condition Codes. */
-#define TSTATE_XCC _AC(0x000000f000000000,UL) /* Condition Codes. */
-#define TSTATE_XNEG _AC(0x0000008000000000,UL) /* %xcc Negative. */
-#define TSTATE_XZERO _AC(0x0000004000000000,UL) /* %xcc Zero. */
-#define TSTATE_XOVFL _AC(0x0000002000000000,UL) /* %xcc Overflow. */
-#define TSTATE_XCARRY _AC(0x0000001000000000,UL) /* %xcc Carry. */
-#define TSTATE_ICC _AC(0x0000000f00000000,UL) /* Condition Codes. */
-#define TSTATE_INEG _AC(0x0000000800000000,UL) /* %icc Negative. */
-#define TSTATE_IZERO _AC(0x0000000400000000,UL) /* %icc Zero. */
-#define TSTATE_IOVFL _AC(0x0000000200000000,UL) /* %icc Overflow. */
-#define TSTATE_ICARRY _AC(0x0000000100000000,UL) /* %icc Carry. */
-#define TSTATE_ASI _AC(0x00000000ff000000,UL) /* AddrSpace ID. */
-#define TSTATE_PIL _AC(0x0000000000f00000,UL) /* %pil (Linux traps)*/
-#define TSTATE_PSTATE _AC(0x00000000000fff00,UL) /* PSTATE. */
-#define TSTATE_IG _AC(0x0000000000080000,UL) /* Interrupt Globals.*/
-#define TSTATE_MG _AC(0x0000000000040000,UL) /* MMU Globals. */
-#define TSTATE_CLE _AC(0x0000000000020000,UL) /* CurrLittleEndian. */
-#define TSTATE_TLE _AC(0x0000000000010000,UL) /* TrapLittleEndian. */
-#define TSTATE_MM _AC(0x000000000000c000,UL) /* Memory Model. */
-#define TSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TSO */
-#define TSTATE_PSO _AC(0x0000000000004000,UL) /* MM: PSO */
-#define TSTATE_RMO _AC(0x0000000000008000,UL) /* MM: RMO */
-#define TSTATE_RED _AC(0x0000000000002000,UL) /* Reset Error Debug.*/
-#define TSTATE_PEF _AC(0x0000000000001000,UL) /* FPU Enable. */
-#define TSTATE_AM _AC(0x0000000000000800,UL) /* Address Mask. */
-#define TSTATE_PRIV _AC(0x0000000000000400,UL) /* Privilege. */
-#define TSTATE_IE _AC(0x0000000000000200,UL) /* Interrupt Enable. */
-#define TSTATE_AG _AC(0x0000000000000100,UL) /* Alternate Globals.*/
-#define TSTATE_SYSCALL _AC(0x0000000000000020,UL) /* in syscall trap */
-#define TSTATE_CWP _AC(0x000000000000001f,UL) /* Curr Win-Pointer. */
-
-/* Floating-Point Registers State Register.
- *
- * --------------------------------
- * | Resv | FEF | DU | DL |
- * --------------------------------
- * 63 3 2 1 0
- */
-#define FPRS_FEF _AC(0x0000000000000004,UL) /* FPU Enable. */
-#define FPRS_DU _AC(0x0000000000000002,UL) /* Dirty Upper. */
-#define FPRS_DL _AC(0x0000000000000001,UL) /* Dirty Lower. */
-
-/* Version Register.
- *
- * ------------------------------------------------------
- * | MANUF | IMPL | MASK | Resv | MAXTL | Resv | MAXWIN |
- * ------------------------------------------------------
- * 63 48 47 32 31 24 23 16 15 8 7 5 4 0
- */
-#define VERS_MANUF _AC(0xffff000000000000,UL) /* Manufacturer. */
-#define VERS_IMPL _AC(0x0000ffff00000000,UL) /* Implementation. */
-#define VERS_MASK _AC(0x00000000ff000000,UL) /* Mask Set Revision.*/
-#define VERS_MAXTL _AC(0x000000000000ff00,UL) /* Max Trap Level. */
-#define VERS_MAXWIN _AC(0x000000000000001f,UL) /* Max RegWindow Idx.*/
-
-#endif /* !(_SPARC64_PSTATE_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_PTRACE_H
-#define ___ASM_SPARC_PTRACE_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/ptrace_64.h>
-#else
-#include <asm-sparc/ptrace_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _SPARC_PTRACE_H
-#define _SPARC_PTRACE_H
-
-#include <asm/psr.h>
-
-/* This struct defines the way the registers are stored on the
- * stack during a system call and basically all traps.
- */
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-struct pt_regs {
- unsigned long psr;
- unsigned long pc;
- unsigned long npc;
- unsigned long y;
- unsigned long u_regs[16]; /* globals and ins */
-};
-
-#define UREG_G0 0
-#define UREG_G1 1
-#define UREG_G2 2
-#define UREG_G3 3
-#define UREG_G4 4
-#define UREG_G5 5
-#define UREG_G6 6
-#define UREG_G7 7
-#define UREG_I0 8
-#define UREG_I1 9
-#define UREG_I2 10
-#define UREG_I3 11
-#define UREG_I4 12
-#define UREG_I5 13
-#define UREG_I6 14
-#define UREG_I7 15
-#define UREG_WIM UREG_G0
-#define UREG_FADDR UREG_G0
-#define UREG_FP UREG_I6
-#define UREG_RETPC UREG_I7
-
-static inline bool pt_regs_is_syscall(struct pt_regs *regs)
-{
- return (regs->psr & PSR_SYSCALL);
-}
-
-static inline bool pt_regs_clear_syscall(struct pt_regs *regs)
-{
- return (regs->psr &= ~PSR_SYSCALL);
-}
-
-/* A register window */
-struct reg_window {
- unsigned long locals[8];
- unsigned long ins[8];
-};
-
-/* A Sparc stack frame */
-struct sparc_stackf {
- unsigned long locals[8];
- unsigned long ins[6];
- struct sparc_stackf *fp;
- unsigned long callers_pc;
- char *structptr;
- unsigned long xargs[6];
- unsigned long xxargs[1];
-};
-
-#define TRACEREG_SZ sizeof(struct pt_regs)
-#define STACKFRAME_SZ sizeof(struct sparc_stackf)
-
-#ifdef __KERNEL__
-
-#define user_mode(regs) (!((regs)->psr & PSR_PS))
-#define instruction_pointer(regs) ((regs)->pc)
-unsigned long profile_pc(struct pt_regs *);
-extern void show_regs(struct pt_regs *);
-#endif
-
-#else /* __ASSEMBLY__ */
-/* For assembly code. */
-#define TRACEREG_SZ 0x50
-#define STACKFRAME_SZ 0x60
-#endif
-
-/*
- * The asm-offsets.h is a generated file, so we cannot include it.
- * It may be OK for glibc headers, but it's utterly pointless for C code.
- * The assembly code using those offsets has to include it explicitly.
- */
-/* #include <asm/asm-offsets.h> */
-
-/* These are for pt_regs. */
-#define PT_PSR 0x0
-#define PT_PC 0x4
-#define PT_NPC 0x8
-#define PT_Y 0xc
-#define PT_G0 0x10
-#define PT_WIM PT_G0
-#define PT_G1 0x14
-#define PT_G2 0x18
-#define PT_G3 0x1c
-#define PT_G4 0x20
-#define PT_G5 0x24
-#define PT_G6 0x28
-#define PT_G7 0x2c
-#define PT_I0 0x30
-#define PT_I1 0x34
-#define PT_I2 0x38
-#define PT_I3 0x3c
-#define PT_I4 0x40
-#define PT_I5 0x44
-#define PT_I6 0x48
-#define PT_FP PT_I6
-#define PT_I7 0x4c
-
-/* Reg_window offsets */
-#define RW_L0 0x00
-#define RW_L1 0x04
-#define RW_L2 0x08
-#define RW_L3 0x0c
-#define RW_L4 0x10
-#define RW_L5 0x14
-#define RW_L6 0x18
-#define RW_L7 0x1c
-#define RW_I0 0x20
-#define RW_I1 0x24
-#define RW_I2 0x28
-#define RW_I3 0x2c
-#define RW_I4 0x30
-#define RW_I5 0x34
-#define RW_I6 0x38
-#define RW_I7 0x3c
-
-/* Stack_frame offsets */
-#define SF_L0 0x00
-#define SF_L1 0x04
-#define SF_L2 0x08
-#define SF_L3 0x0c
-#define SF_L4 0x10
-#define SF_L5 0x14
-#define SF_L6 0x18
-#define SF_L7 0x1c
-#define SF_I0 0x20
-#define SF_I1 0x24
-#define SF_I2 0x28
-#define SF_I3 0x2c
-#define SF_I4 0x30
-#define SF_I5 0x34
-#define SF_FP 0x38
-#define SF_PC 0x3c
-#define SF_RETP 0x40
-#define SF_XARG0 0x44
-#define SF_XARG1 0x48
-#define SF_XARG2 0x4c
-#define SF_XARG3 0x50
-#define SF_XARG4 0x54
-#define SF_XARG5 0x58
-#define SF_XXARG 0x5c
-
-/* Stuff for the ptrace system call */
-#define PTRACE_SPARC_DETACH 11
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-#define PTRACE_GETFPREGS 14
-#define PTRACE_SETFPREGS 15
-#define PTRACE_READDATA 16
-#define PTRACE_WRITEDATA 17
-#define PTRACE_READTEXT 18
-#define PTRACE_WRITETEXT 19
-#define PTRACE_GETFPAREGS 20
-#define PTRACE_SETFPAREGS 21
-
-#endif /* !(_SPARC_PTRACE_H) */
+++ /dev/null
-#ifndef _SPARC64_PTRACE_H
-#define _SPARC64_PTRACE_H
-
-#include <asm/pstate.h>
-
-/* This struct defines the way the registers are stored on the
- * stack during a system call and basically all traps.
- */
-
-/* This magic value must have the low 9 bits clear,
- * as that is where we encode the %tt value, see below.
- */
-#define PT_REGS_MAGIC 0x57ac6c00
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-struct pt_regs {
- unsigned long u_regs[16]; /* globals and ins */
- unsigned long tstate;
- unsigned long tpc;
- unsigned long tnpc;
- unsigned int y;
-
- /* We encode a magic number, PT_REGS_MAGIC, along
- * with the %tt (trap type) register value at trap
- * entry time. The magic number allows us to identify
- * accurately a trap stack frame in the stack
- * unwinder, and the %tt value allows us to test
- * things like "in a system call" etc. for an arbitray
- * process.
- *
- * The PT_REGS_MAGIC is choosen such that it can be
- * loaded completely using just a sethi instruction.
- */
- unsigned int magic;
-};
-
-static inline int pt_regs_trap_type(struct pt_regs *regs)
-{
- return regs->magic & 0x1ff;
-}
-
-static inline bool pt_regs_is_syscall(struct pt_regs *regs)
-{
- return (regs->tstate & TSTATE_SYSCALL);
-}
-
-static inline bool pt_regs_clear_syscall(struct pt_regs *regs)
-{
- return (regs->tstate &= ~TSTATE_SYSCALL);
-}
-
-struct pt_regs32 {
- unsigned int psr;
- unsigned int pc;
- unsigned int npc;
- unsigned int y;
- unsigned int u_regs[16]; /* globals and ins */
-};
-
-#define UREG_G0 0
-#define UREG_G1 1
-#define UREG_G2 2
-#define UREG_G3 3
-#define UREG_G4 4
-#define UREG_G5 5
-#define UREG_G6 6
-#define UREG_G7 7
-#define UREG_I0 8
-#define UREG_I1 9
-#define UREG_I2 10
-#define UREG_I3 11
-#define UREG_I4 12
-#define UREG_I5 13
-#define UREG_I6 14
-#define UREG_I7 15
-#define UREG_FP UREG_I6
-#define UREG_RETPC UREG_I7
-
-/* A V9 register window */
-struct reg_window {
- unsigned long locals[8];
- unsigned long ins[8];
-};
-
-/* A 32-bit register window. */
-struct reg_window32 {
- unsigned int locals[8];
- unsigned int ins[8];
-};
-
-/* A V9 Sparc stack frame */
-struct sparc_stackf {
- unsigned long locals[8];
- unsigned long ins[6];
- struct sparc_stackf *fp;
- unsigned long callers_pc;
- char *structptr;
- unsigned long xargs[6];
- unsigned long xxargs[1];
-};
-
-/* A 32-bit Sparc stack frame */
-struct sparc_stackf32 {
- unsigned int locals[8];
- unsigned int ins[6];
- unsigned int fp;
- unsigned int callers_pc;
- unsigned int structptr;
- unsigned int xargs[6];
- unsigned int xxargs[1];
-};
-
-struct sparc_trapf {
- unsigned long locals[8];
- unsigned long ins[8];
- unsigned long _unused;
- struct pt_regs *regs;
-};
-
-#define TRACEREG_SZ sizeof(struct pt_regs)
-#define STACKFRAME_SZ sizeof(struct sparc_stackf)
-
-#define TRACEREG32_SZ sizeof(struct pt_regs32)
-#define STACKFRAME32_SZ sizeof(struct sparc_stackf32)
-
-#ifdef __KERNEL__
-
-struct global_reg_snapshot {
- unsigned long tstate;
- unsigned long tpc;
- unsigned long tnpc;
- unsigned long o7;
- unsigned long i7;
- struct thread_info *thread;
- unsigned long pad1;
- unsigned long pad2;
-};
-
-#define __ARCH_WANT_COMPAT_SYS_PTRACE
-
-#define force_successful_syscall_return() \
-do { current_thread_info()->syscall_noerror = 1; \
-} while (0)
-#define user_mode(regs) (!((regs)->tstate & TSTATE_PRIV))
-#define instruction_pointer(regs) ((regs)->tpc)
-#define regs_return_value(regs) ((regs)->u_regs[UREG_I0])
-#ifdef CONFIG_SMP
-extern unsigned long profile_pc(struct pt_regs *);
-#else
-#define profile_pc(regs) instruction_pointer(regs)
-#endif
-extern void show_regs(struct pt_regs *);
-extern void __show_regs(struct pt_regs *);
-#endif
-
-#else /* __ASSEMBLY__ */
-/* For assembly code. */
-#define TRACEREG_SZ 0xa0
-#define STACKFRAME_SZ 0xc0
-
-#define TRACEREG32_SZ 0x50
-#define STACKFRAME32_SZ 0x60
-#endif
-
-#ifdef __KERNEL__
-#define STACK_BIAS 2047
-#endif
-
-/* These are for pt_regs. */
-#define PT_V9_G0 0x00
-#define PT_V9_G1 0x08
-#define PT_V9_G2 0x10
-#define PT_V9_G3 0x18
-#define PT_V9_G4 0x20
-#define PT_V9_G5 0x28
-#define PT_V9_G6 0x30
-#define PT_V9_G7 0x38
-#define PT_V9_I0 0x40
-#define PT_V9_I1 0x48
-#define PT_V9_I2 0x50
-#define PT_V9_I3 0x58
-#define PT_V9_I4 0x60
-#define PT_V9_I5 0x68
-#define PT_V9_I6 0x70
-#define PT_V9_FP PT_V9_I6
-#define PT_V9_I7 0x78
-#define PT_V9_TSTATE 0x80
-#define PT_V9_TPC 0x88
-#define PT_V9_TNPC 0x90
-#define PT_V9_Y 0x98
-#define PT_V9_MAGIC 0x9c
-#define PT_TSTATE PT_V9_TSTATE
-#define PT_TPC PT_V9_TPC
-#define PT_TNPC PT_V9_TNPC
-
-/* These for pt_regs32. */
-#define PT_PSR 0x0
-#define PT_PC 0x4
-#define PT_NPC 0x8
-#define PT_Y 0xc
-#define PT_G0 0x10
-#define PT_WIM PT_G0
-#define PT_G1 0x14
-#define PT_G2 0x18
-#define PT_G3 0x1c
-#define PT_G4 0x20
-#define PT_G5 0x24
-#define PT_G6 0x28
-#define PT_G7 0x2c
-#define PT_I0 0x30
-#define PT_I1 0x34
-#define PT_I2 0x38
-#define PT_I3 0x3c
-#define PT_I4 0x40
-#define PT_I5 0x44
-#define PT_I6 0x48
-#define PT_FP PT_I6
-#define PT_I7 0x4c
-
-/* Reg_window offsets */
-#define RW_V9_L0 0x00
-#define RW_V9_L1 0x08
-#define RW_V9_L2 0x10
-#define RW_V9_L3 0x18
-#define RW_V9_L4 0x20
-#define RW_V9_L5 0x28
-#define RW_V9_L6 0x30
-#define RW_V9_L7 0x38
-#define RW_V9_I0 0x40
-#define RW_V9_I1 0x48
-#define RW_V9_I2 0x50
-#define RW_V9_I3 0x58
-#define RW_V9_I4 0x60
-#define RW_V9_I5 0x68
-#define RW_V9_I6 0x70
-#define RW_V9_I7 0x78
-
-#define RW_L0 0x00
-#define RW_L1 0x04
-#define RW_L2 0x08
-#define RW_L3 0x0c
-#define RW_L4 0x10
-#define RW_L5 0x14
-#define RW_L6 0x18
-#define RW_L7 0x1c
-#define RW_I0 0x20
-#define RW_I1 0x24
-#define RW_I2 0x28
-#define RW_I3 0x2c
-#define RW_I4 0x30
-#define RW_I5 0x34
-#define RW_I6 0x38
-#define RW_I7 0x3c
-
-/* Stack_frame offsets */
-#define SF_V9_L0 0x00
-#define SF_V9_L1 0x08
-#define SF_V9_L2 0x10
-#define SF_V9_L3 0x18
-#define SF_V9_L4 0x20
-#define SF_V9_L5 0x28
-#define SF_V9_L6 0x30
-#define SF_V9_L7 0x38
-#define SF_V9_I0 0x40
-#define SF_V9_I1 0x48
-#define SF_V9_I2 0x50
-#define SF_V9_I3 0x58
-#define SF_V9_I4 0x60
-#define SF_V9_I5 0x68
-#define SF_V9_FP 0x70
-#define SF_V9_PC 0x78
-#define SF_V9_RETP 0x80
-#define SF_V9_XARG0 0x88
-#define SF_V9_XARG1 0x90
-#define SF_V9_XARG2 0x98
-#define SF_V9_XARG3 0xa0
-#define SF_V9_XARG4 0xa8
-#define SF_V9_XARG5 0xb0
-#define SF_V9_XXARG 0xb8
-
-#define SF_L0 0x00
-#define SF_L1 0x04
-#define SF_L2 0x08
-#define SF_L3 0x0c
-#define SF_L4 0x10
-#define SF_L5 0x14
-#define SF_L6 0x18
-#define SF_L7 0x1c
-#define SF_I0 0x20
-#define SF_I1 0x24
-#define SF_I2 0x28
-#define SF_I3 0x2c
-#define SF_I4 0x30
-#define SF_I5 0x34
-#define SF_FP 0x38
-#define SF_PC 0x3c
-#define SF_RETP 0x40
-#define SF_XARG0 0x44
-#define SF_XARG1 0x48
-#define SF_XARG2 0x4c
-#define SF_XARG3 0x50
-#define SF_XARG4 0x54
-#define SF_XARG5 0x58
-#define SF_XXARG 0x5c
-
-#ifdef __KERNEL__
-
-/* global_reg_snapshot offsets */
-#define GR_SNAP_TSTATE 0x00
-#define GR_SNAP_TPC 0x08
-#define GR_SNAP_TNPC 0x10
-#define GR_SNAP_O7 0x18
-#define GR_SNAP_I7 0x20
-#define GR_SNAP_THREAD 0x28
-#define GR_SNAP_PAD1 0x30
-#define GR_SNAP_PAD2 0x38
-
-#endif /* __KERNEL__ */
-
-/* Stuff for the ptrace system call */
-#define PTRACE_SPARC_DETACH 11
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-#define PTRACE_GETFPREGS 14
-#define PTRACE_SETFPREGS 15
-#define PTRACE_READDATA 16
-#define PTRACE_WRITEDATA 17
-#define PTRACE_READTEXT 18
-#define PTRACE_WRITETEXT 19
-#define PTRACE_GETFPAREGS 20
-#define PTRACE_SETFPAREGS 21
-
-/* There are for debugging 64-bit processes, either from a 32 or 64 bit
- * parent. Thus their complements are for debugging 32-bit processes only.
- */
-
-#define PTRACE_GETREGS64 22
-#define PTRACE_SETREGS64 23
-/* PTRACE_SYSCALL is 24 */
-#define PTRACE_GETFPREGS64 25
-#define PTRACE_SETFPREGS64 26
-
-#endif /* !(_SPARC64_PTRACE_H) */
+++ /dev/null
-#ifndef _SPARC64_REBOOT_H
-#define _SPARC64_REBOOT_H
-
-extern void machine_alt_power_off(void);
-
-#endif /* _SPARC64_REBOOT_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_REG_H
-#define ___ASM_SPARC_REG_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/reg_64.h>
-#else
-#include <asm-sparc/reg_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * linux/include/asm-sparc/reg.h
- * Layout of the registers as expected by gdb on the Sparc
- * we should replace the user.h definitions with those in
- * this file, we don't even use the other
- * -miguel
- *
- * The names of the structures, constants and aliases in this file
- * have the same names as the sunos ones, some programs rely on these
- * names (gdb for example).
- *
- */
-
-#ifndef __SPARC_REG_H
-#define __SPARC_REG_H
-
-struct regs {
- int r_psr;
-#define r_ps r_psr
- int r_pc;
- int r_npc;
- int r_y;
- int r_g1;
- int r_g2;
- int r_g3;
- int r_g4;
- int r_g5;
- int r_g6;
- int r_g7;
- int r_o0;
- int r_o1;
- int r_o2;
- int r_o3;
- int r_o4;
- int r_o5;
- int r_o6;
- int r_o7;
-};
-
-struct fpq {
- unsigned long *addr;
- unsigned long instr;
-};
-
-struct fq {
- union {
- double whole;
- struct fpq fpq;
- } FQu;
-};
-
-#define FPU_REGS_TYPE unsigned int
-#define FPU_FSR_TYPE unsigned
-
-struct fp_status {
- union {
- FPU_REGS_TYPE Fpu_regs[32];
- double Fpu_dregs[16];
- } fpu_fr;
- FPU_FSR_TYPE Fpu_fsr;
- unsigned Fpu_flags;
- unsigned Fpu_extra;
- unsigned Fpu_qcnt;
- struct fq Fpu_q[16];
-};
-
-#define fpu_regs f_fpstatus.fpu_fr.Fpu_regs
-#define fpu_dregs f_fpstatus.fpu_fr.Fpu_dregs
-#define fpu_fsr f_fpstatus.Fpu_fsr
-#define fpu_flags f_fpstatus.Fpu_flags
-#define fpu_extra f_fpstatus.Fpu_extra
-#define fpu_q f_fpstatus.Fpu_q
-#define fpu_qcnt f_fpstatus.Fpu_qcnt
-
-struct fpu {
- struct fp_status f_fpstatus;
-};
-
-#endif /* __SPARC_REG_H */
+++ /dev/null
-/*
- * linux/asm-sparc64/reg.h
- * Layout of the registers as expected by gdb on the Sparc
- * we should replace the user.h definitions with those in
- * this file, we don't even use the other
- * -miguel
- *
- * The names of the structures, constants and aliases in this file
- * have the same names as the sunos ones, some programs rely on these
- * names (gdb for example).
- *
- */
-
-#ifndef __SPARC64_REG_H
-#define __SPARC64_REG_H
-
-struct regs {
- unsigned long r_g1;
- unsigned long r_g2;
- unsigned long r_g3;
- unsigned long r_g4;
- unsigned long r_g5;
- unsigned long r_g6;
- unsigned long r_g7;
- unsigned long r_o0;
- unsigned long r_o1;
- unsigned long r_o2;
- unsigned long r_o3;
- unsigned long r_o4;
- unsigned long r_o5;
- unsigned long r_o6;
- unsigned long r_o7;
- unsigned long __pad;
- unsigned long r_tstate;
- unsigned long r_tpc;
- unsigned long r_tnpc;
- unsigned int r_y;
- unsigned int r_fprs;
-};
-
-#define FPU_REGS_TYPE unsigned int
-#define FPU_FSR_TYPE unsigned long
-
-struct fp_status {
- unsigned long fpu_fr[32];
- unsigned long Fpu_fsr;
-};
-
-struct fpu {
- struct fp_status f_fpstatus;
-};
-
-#define fpu_regs f_fpstatus.fpu_fr
-#define fpu_fsr f_fpstatus.Fpu_fsr
-
-#endif /* __SPARC64_REG_H */
+++ /dev/null
-/*
- * resource.h: Resource definitions.
- *
- * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_RESOURCE_H
-#define _SPARC_RESOURCE_H
-
-/*
- * These two resource limit IDs have a Sparc/Linux-specific ordering,
- * the rest comes from the generic header:
- */
-#define RLIMIT_NOFILE 6 /* max number of open files */
-#define RLIMIT_NPROC 7 /* max number of processes */
-
-#if defined(__sparc__) && defined(__arch64__)
-/* Use generic version */
-#else
-/*
- * SuS says limits have to be unsigned.
- * We make this unsigned, but keep the
- * old value for compatibility:
- */
-#define RLIM_INFINITY 0x7fffffff
-#endif
-
-#include <asm-generic/resource.h>
-
-#endif /* !(_SPARC_RESOURCE_H) */
+++ /dev/null
-/*
- * ross.h: Ross module specific definitions and defines.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_ROSS_H
-#define _SPARC_ROSS_H
-
-#include <asm/asi.h>
-#include <asm/page.h>
-
-/* Ross made Hypersparcs have a %psr 'impl' field of '0001'. The 'vers'
- * field has '1111'.
- */
-
-/* The MMU control register fields on the HyperSparc.
- *
- * -----------------------------------------------------------------
- * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
- * -----------------------------------------------------------------
- * 31 24 23-22 21 20 19 18-15 14 13 12 11 10 9 8 7-2 1 0
- *
- * Phew, lots of fields there ;-)
- *
- * CWR: Cache Wrapping Enabled, if one cache wrapping is on.
- * SE: Snoop Enable, turns on bus snooping for cache activity if one.
- * WBE: Write Buffer Enable, one turns it on.
- * MID: The ModuleID of the chip for MBus transactions.
- * BM: Boot-Mode. One indicates the MMU is in boot mode.
- * C: Indicates whether accesses are cachable while the MMU is
- * disabled.
- * CS: Cache Size -- 0 = 128k, 1 = 256k
- * MR: Memory Reflection, one indicates that the memory bus connected
- * to the MBus supports memory reflection.
- * CM: Cache Mode -- 0 = write-through, 1 = copy-back
- * CE: Cache Enable -- 0 = no caching, 1 = cache is on
- * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
- * 1 = faults from supervisor mode do not generate traps
- * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
- */
-
-#define HYPERSPARC_CWENABLE 0x00200000
-#define HYPERSPARC_SBENABLE 0x00100000
-#define HYPERSPARC_WBENABLE 0x00080000
-#define HYPERSPARC_MIDMASK 0x00078000
-#define HYPERSPARC_BMODE 0x00004000
-#define HYPERSPARC_ACENABLE 0x00002000
-#define HYPERSPARC_CSIZE 0x00001000
-#define HYPERSPARC_MRFLCT 0x00000800
-#define HYPERSPARC_CMODE 0x00000400
-#define HYPERSPARC_CENABLE 0x00000100
-#define HYPERSPARC_NFAULT 0x00000002
-#define HYPERSPARC_MENABLE 0x00000001
-
-
-/* The ICCR instruction cache register on the HyperSparc.
- *
- * -----------------------------------------------
- * | | FTD | ICE |
- * -----------------------------------------------
- * 31 1 0
- *
- * This register is accessed using the V8 'wrasr' and 'rdasr'
- * opcodes, since not all assemblers understand them and those
- * that do use different semantics I will just hard code the
- * instruction with a '.word' statement.
- *
- * FTD: If set to one flush instructions executed during an
- * instruction cache hit occurs, the corresponding line
- * for said cache-hit is invalidated. If FTD is zero,
- * an unimplemented 'flush' trap will occur when any
- * flush is executed by the processor.
- *
- * ICE: If set to one, the instruction cache is enabled. If
- * zero, the cache will not be used for instruction fetches.
- *
- * All other bits are read as zeros, and writes to them have no
- * effect.
- *
- * Wheee, not many assemblers understand the %iccr register nor
- * the generic asr r/w instructions.
- *
- * 1000 0011 0100 0111 1100 0000 0000 0000 ! rd %iccr, %g1
- *
- * 0x 8 3 4 7 c 0 0 0 ! 0x8347c000
- *
- * 1011 1111 1000 0000 0110 0000 0000 0000 ! wr %g1, 0x0, %iccr
- *
- * 0x b f 8 0 6 0 0 0 ! 0xbf806000
- *
- */
-
-#define HYPERSPARC_ICCR_FTD 0x00000002
-#define HYPERSPARC_ICCR_ICE 0x00000001
-
-#ifndef __ASSEMBLY__
-
-static inline unsigned int get_ross_icr(void)
-{
- unsigned int icreg;
-
- __asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */
- "mov %%g1, %0\n\t"
- : "=r" (icreg)
- : /* no inputs */
- : "g1", "memory");
-
- return icreg;
-}
-
-static inline void put_ross_icr(unsigned int icreg)
-{
- __asm__ __volatile__("or %%g0, %0, %%g1\n\t"
- ".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- : /* no outputs */
- : "r" (icreg)
- : "g1", "memory");
-
- return;
-}
-
-/* HyperSparc specific cache flushing. */
-
-/* This is for the on-chip instruction cache. */
-static inline void hyper_flush_whole_icache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_FLUSH_IWHOLE)
- : "memory");
- return;
-}
-
-extern int vac_cache_size;
-extern int vac_line_size;
-
-static inline void hyper_clear_all_tags(void)
-{
- unsigned long addr;
-
- for(addr = 0; addr < vac_cache_size; addr += vac_line_size)
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_DATAC_TAG)
- : "memory");
-}
-
-static inline void hyper_flush_unconditional_combined(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_FLUSH_CTX)
- : "memory");
-}
-
-static inline void hyper_flush_cache_user(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_FLUSH_USER)
- : "memory");
-}
-
-static inline void hyper_flush_cache_page(unsigned long page)
-{
- unsigned long end;
-
- page &= PAGE_MASK;
- end = page + PAGE_SIZE;
- while (page < end) {
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (page), "i" (ASI_M_FLUSH_PAGE)
- : "memory");
- page += vac_line_size;
- }
-}
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(_SPARC_ROSS_H) */
+++ /dev/null
-/*
- * rtc.h: Definitions for access to the Mostek real time clock
- *
- * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
- */
-
-#ifndef _RTC_H
-#define _RTC_H
-
-#include <linux/ioctl.h>
-
-struct rtc_time
-{
- int sec; /* Seconds (0-59) */
- int min; /* Minutes (0-59) */
- int hour; /* Hour (0-23) */
- int dow; /* Day of the week (1-7) */
- int dom; /* Day of the month (1-31) */
- int month; /* Month of year (1-12) */
- int year; /* Year (0-99) */
-};
-
-#define RTCGET _IOR('p', 20, struct rtc_time)
-#define RTCSET _IOW('p', 21, struct rtc_time)
-
-#endif
+++ /dev/null
-/* rwsem-const.h: RW semaphore counter constants. */
-#ifndef _SPARC64_RWSEM_CONST_H
-#define _SPARC64_RWSEM_CONST_H
-
-#define RWSEM_UNLOCKED_VALUE 0x00000000
-#define RWSEM_ACTIVE_BIAS 0x00000001
-#define RWSEM_ACTIVE_MASK 0x0000ffff
-#define RWSEM_WAITING_BIAS 0xffff0000
-#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
-#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
-
-#endif /* _SPARC64_RWSEM_CONST_H */
+++ /dev/null
-/*
- * rwsem.h: R/W semaphores implemented using CAS
- *
- * Written by David S. Miller (davem@redhat.com), 2001.
- * Derived from asm-i386/rwsem.h
- */
-#ifndef _SPARC64_RWSEM_H
-#define _SPARC64_RWSEM_H
-
-#ifndef _LINUX_RWSEM_H
-#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
-#endif
-
-#ifdef __KERNEL__
-
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <asm/rwsem-const.h>
-
-struct rwsem_waiter;
-
-struct rw_semaphore {
- signed int count;
- spinlock_t wait_lock;
- struct list_head wait_list;
-#ifdef CONFIG_DEBUG_LOCK_ALLOC
- struct lockdep_map dep_map;
-#endif
-};
-
-#ifdef CONFIG_DEBUG_LOCK_ALLOC
-# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
-#else
-# define __RWSEM_DEP_MAP_INIT(lockname)
-#endif
-
-#define __RWSEM_INITIALIZER(name) \
-{ RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) \
- __RWSEM_DEP_MAP_INIT(name) }
-
-#define DECLARE_RWSEM(name) \
- struct rw_semaphore name = __RWSEM_INITIALIZER(name)
-
-extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
- struct lock_class_key *key);
-
-#define init_rwsem(sem) \
-do { \
- static struct lock_class_key __key; \
- \
- __init_rwsem((sem), #sem, &__key); \
-} while (0)
-
-extern void __down_read(struct rw_semaphore *sem);
-extern int __down_read_trylock(struct rw_semaphore *sem);
-extern void __down_write(struct rw_semaphore *sem);
-extern int __down_write_trylock(struct rw_semaphore *sem);
-extern void __up_read(struct rw_semaphore *sem);
-extern void __up_write(struct rw_semaphore *sem);
-extern void __downgrade_write(struct rw_semaphore *sem);
-
-static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
-{
- __down_write(sem);
-}
-
-static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
-{
- return atomic_add_return(delta, (atomic_t *)(&sem->count));
-}
-
-static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
-{
- atomic_add(delta, (atomic_t *)(&sem->count));
-}
-
-static inline int rwsem_is_locked(struct rw_semaphore *sem)
-{
- return (sem->count != 0);
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* _SPARC64_RWSEM_H */
+++ /dev/null
-/*
- * sbi.h: SBI (Sbus Interface on sun4d) definitions
- *
- * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
- */
-
-#ifndef _SPARC_SBI_H
-#define _SPARC_SBI_H
-
-#include <asm/obio.h>
-
-/* SBI */
-struct sbi_regs {
-/* 0x0000 */ u32 cid; /* Component ID */
-/* 0x0004 */ u32 ctl; /* Control */
-/* 0x0008 */ u32 status; /* Status */
- u32 _unused1;
-
-/* 0x0010 */ u32 cfg0; /* Slot0 config reg */
-/* 0x0014 */ u32 cfg1; /* Slot1 config reg */
-/* 0x0018 */ u32 cfg2; /* Slot2 config reg */
-/* 0x001c */ u32 cfg3; /* Slot3 config reg */
-
-/* 0x0020 */ u32 stb0; /* Streaming buf control for slot 0 */
-/* 0x0024 */ u32 stb1; /* Streaming buf control for slot 1 */
-/* 0x0028 */ u32 stb2; /* Streaming buf control for slot 2 */
-/* 0x002c */ u32 stb3; /* Streaming buf control for slot 3 */
-
-/* 0x0030 */ u32 intr_state; /* Interrupt state */
-/* 0x0034 */ u32 intr_tid; /* Interrupt target ID */
-/* 0x0038 */ u32 intr_diag; /* Interrupt diagnostics */
-};
-
-#define SBI_CID 0x02800000
-#define SBI_CTL 0x02800004
-#define SBI_STATUS 0x02800008
-#define SBI_CFG0 0x02800010
-#define SBI_CFG1 0x02800014
-#define SBI_CFG2 0x02800018
-#define SBI_CFG3 0x0280001c
-#define SBI_STB0 0x02800020
-#define SBI_STB1 0x02800024
-#define SBI_STB2 0x02800028
-#define SBI_STB3 0x0280002c
-#define SBI_INTR_STATE 0x02800030
-#define SBI_INTR_TID 0x02800034
-#define SBI_INTR_DIAG 0x02800038
-
-/* Burst bits for 8, 16, 32, 64 are in cfgX registers at bits 2, 3, 4, 5 respectively */
-#define SBI_CFG_BURST_MASK 0x0000001e
-
-/* How to make devid from sbi no */
-#define SBI2DEVID(sbino) ((sbino<<4)|2)
-
-/* intr_state has 4 bits for slots 0 .. 3 and these bits are repeated for each sbus irq level
- *
- * +-------+-------+-------+-------+-------+-------+-------+-------+
- * SBUS IRQ LEVEL | 7 | 6 | 5 | 4 | 3 | 2 | 1 | |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Reser |
- * SLOT # |3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0| ved |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------+
- * Bits 31 27 23 19 15 11 7 3 0
- */
-
-
-#ifndef __ASSEMBLY__
-
-static inline int acquire_sbi(int devid, int mask)
-{
- __asm__ __volatile__ ("swapa [%2] %3, %0" :
- "=r" (mask) :
- "0" (mask),
- "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
- "i" (ASI_M_CTL));
- return mask;
-}
-
-static inline void release_sbi(int devid, int mask)
-{
- __asm__ __volatile__ ("sta %0, [%1] %2" : :
- "r" (mask),
- "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
- "i" (ASI_M_CTL));
-}
-
-static inline void set_sbi_tid(int devid, int targetid)
-{
- __asm__ __volatile__ ("sta %0, [%1] %2" : :
- "r" (targetid),
- "r" (ECSR_DEV_BASE(devid) | SBI_INTR_TID),
- "i" (ASI_M_CTL));
-}
-
-static inline int get_sbi_ctl(int devid, int cfgno)
-{
- int cfg;
-
- __asm__ __volatile__ ("lda [%1] %2, %0" :
- "=r" (cfg) :
- "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
- "i" (ASI_M_CTL));
- return cfg;
-}
-
-static inline void set_sbi_ctl(int devid, int cfgno, int cfg)
-{
- __asm__ __volatile__ ("sta %0, [%1] %2" : :
- "r" (cfg),
- "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
- "i" (ASI_M_CTL));
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* !(_SPARC_SBI_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_SBUS_H
-#define ___ASM_SPARC_SBUS_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/sbus_64.h>
-#else
-#include <asm-sparc/sbus_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * sbus.h: Defines for the Sun SBus.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_SBUS_H
-#define _SPARC_SBUS_H
-
-#include <linux/dma-mapping.h>
-#include <linux/ioport.h>
-
-#include <asm/oplib.h>
-#include <asm/prom.h>
-#include <asm/of_device.h>
-#include <asm/scatterlist.h>
-
-/* We scan which devices are on the SBus using the PROM node device
- * tree. SBus devices are described in two different ways. You can
- * either get an absolute address at which to access the device, or
- * you can get a SBus 'slot' number and an offset within that slot.
- */
-
-/* The base address at which to calculate device OBIO addresses. */
-#define SUN_SBUS_BVADDR 0xf8000000
-#define SBUS_OFF_MASK 0x01ffffff
-
-/* These routines are used to calculate device address from slot
- * numbers + offsets, and vice versa.
- */
-
-static inline unsigned long sbus_devaddr(int slotnum, unsigned long offset)
-{
- return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<25)+(offset));
-}
-
-static inline int sbus_dev_slot(unsigned long dev_addr)
-{
- return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>25);
-}
-
-struct sbus_bus;
-
-/* Linux SBUS device tables */
-struct sbus_dev {
- struct of_device ofdev;
- struct sbus_bus *bus;
- struct sbus_dev *next;
- struct sbus_dev *child;
- struct sbus_dev *parent;
- int prom_node;
- char prom_name[64];
- int slot;
-
- struct resource resource[PROMREG_MAX];
-
- struct linux_prom_registers reg_addrs[PROMREG_MAX];
- int num_registers;
-
- struct linux_prom_ranges device_ranges[PROMREG_MAX];
- int num_device_ranges;
-
- unsigned int irqs[4];
- int num_irqs;
-};
-#define to_sbus_device(d) container_of(d, struct sbus_dev, ofdev.dev)
-
-/* This struct describes the SBus(s) found on this machine. */
-struct sbus_bus {
- struct of_device ofdev;
- struct sbus_dev *devices; /* Link to devices on this SBus */
- struct sbus_bus *next; /* next SBus, if more than one SBus */
- int prom_node; /* PROM device tree node for this SBus */
- char prom_name[64]; /* Usually "sbus" or "sbi" */
- int clock_freq;
-
- struct linux_prom_ranges sbus_ranges[PROMREG_MAX];
- int num_sbus_ranges;
-
- int devid;
- int board;
-};
-#define to_sbus(d) container_of(d, struct sbus_bus, ofdev.dev)
-
-extern struct sbus_bus *sbus_root;
-
-static inline int
-sbus_is_slave(struct sbus_dev *dev)
-{
- /* XXX Have to write this for sun4c's */
- return 0;
-}
-
-/* Device probing routines could find these handy */
-#define for_each_sbus(bus) \
- for((bus) = sbus_root; (bus); (bus)=(bus)->next)
-
-#define for_each_sbusdev(device, bus) \
- for((device) = (bus)->devices; (device); (device)=(device)->next)
-
-#define for_all_sbusdev(device, bus) \
- for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \
- for ((device) = (bus)->devices; (device); (device) = (device)->next)
-
-/* Driver DVMA interfaces. */
-#define sbus_can_dma_64bit(sdev) (0) /* actually, sparc_cpu_model==sun4d */
-#define sbus_can_burst64(sdev) (0) /* actually, sparc_cpu_model==sun4d */
-extern void sbus_set_sbus64(struct sbus_dev *, int);
-extern void sbus_fill_device_irq(struct sbus_dev *);
-
-/* These yield IOMMU mappings in consistent mode. */
-extern void *sbus_alloc_consistent(struct sbus_dev *, long, u32 *dma_addrp);
-extern void sbus_free_consistent(struct sbus_dev *, long, void *, u32);
-void prom_adjust_ranges(struct linux_prom_ranges *, int,
- struct linux_prom_ranges *, int);
-
-#define SBUS_DMA_BIDIRECTIONAL DMA_BIDIRECTIONAL
-#define SBUS_DMA_TODEVICE DMA_TO_DEVICE
-#define SBUS_DMA_FROMDEVICE DMA_FROM_DEVICE
-#define SBUS_DMA_NONE DMA_NONE
-
-/* All the rest use streaming mode mappings. */
-extern dma_addr_t sbus_map_single(struct sbus_dev *, void *, size_t, int);
-extern void sbus_unmap_single(struct sbus_dev *, dma_addr_t, size_t, int);
-extern int sbus_map_sg(struct sbus_dev *, struct scatterlist *, int, int);
-extern void sbus_unmap_sg(struct sbus_dev *, struct scatterlist *, int, int);
-
-/* Finally, allow explicit synchronization of streamable mappings. */
-extern void sbus_dma_sync_single_for_cpu(struct sbus_dev *, dma_addr_t, size_t, int);
-#define sbus_dma_sync_single sbus_dma_sync_single_for_cpu
-extern void sbus_dma_sync_single_for_device(struct sbus_dev *, dma_addr_t, size_t, int);
-extern void sbus_dma_sync_sg_for_cpu(struct sbus_dev *, struct scatterlist *, int, int);
-#define sbus_dma_sync_sg sbus_dma_sync_sg_for_cpu
-extern void sbus_dma_sync_sg_for_device(struct sbus_dev *, struct scatterlist *, int, int);
-
-/* Eric Brower (ebrower@usa.net)
- * Translate SBus interrupt levels to ino values--
- * this is used when converting sbus "interrupts" OBP
- * node values to "intr" node values, and is platform
- * dependent. If only we could call OBP with
- * "sbus-intr>cpu (sbint -- ino)" from kernel...
- * See .../drivers/sbus/sbus.c for details.
- */
-BTFIXUPDEF_CALL(unsigned int, sbint_to_irq, struct sbus_dev *sdev, unsigned int)
-#define sbint_to_irq(sdev, sbint) BTFIXUP_CALL(sbint_to_irq)(sdev, sbint)
-
-extern void sbus_arch_bus_ranges_init(struct device_node *, struct sbus_bus *);
-extern void sbus_setup_iommu(struct sbus_bus *, struct device_node *);
-extern void sbus_setup_arch_props(struct sbus_bus *, struct device_node *);
-extern int sbus_arch_preinit(void);
-extern void sbus_arch_postinit(void);
-
-#endif /* !(_SPARC_SBUS_H) */
+++ /dev/null
-/* sbus.h: Defines for the Sun SBus.
- *
- * Copyright (C) 1996, 1999, 2007 David S. Miller (davem@davemloft.net)
- */
-
-#ifndef _SPARC64_SBUS_H
-#define _SPARC64_SBUS_H
-
-#include <linux/dma-mapping.h>
-#include <linux/ioport.h>
-
-#include <asm/oplib.h>
-#include <asm/prom.h>
-#include <asm/of_device.h>
-#include <asm/iommu.h>
-#include <asm/scatterlist.h>
-
-/* We scan which devices are on the SBus using the PROM node device
- * tree. SBus devices are described in two different ways. You can
- * either get an absolute address at which to access the device, or
- * you can get a SBus 'slot' number and an offset within that slot.
- */
-
-/* The base address at which to calculate device OBIO addresses. */
-#define SUN_SBUS_BVADDR 0x00000000
-#define SBUS_OFF_MASK 0x0fffffff
-
-/* These routines are used to calculate device address from slot
- * numbers + offsets, and vice versa.
- */
-
-static inline unsigned long sbus_devaddr(int slotnum, unsigned long offset)
-{
- return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<28)+(offset));
-}
-
-static inline int sbus_dev_slot(unsigned long dev_addr)
-{
- return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>28);
-}
-
-struct sbus_bus;
-
-/* Linux SBUS device tables */
-struct sbus_dev {
- struct of_device ofdev;
- struct sbus_bus *bus;
- struct sbus_dev *next;
- struct sbus_dev *child;
- struct sbus_dev *parent;
- int prom_node;
- char prom_name[64];
- int slot;
-
- struct resource resource[PROMREG_MAX];
-
- struct linux_prom_registers reg_addrs[PROMREG_MAX];
- int num_registers;
-
- struct linux_prom_ranges device_ranges[PROMREG_MAX];
- int num_device_ranges;
-
- unsigned int irqs[4];
- int num_irqs;
-};
-#define to_sbus_device(d) container_of(d, struct sbus_dev, ofdev.dev)
-
-/* This struct describes the SBus(s) found on this machine. */
-struct sbus_bus {
- struct of_device ofdev;
- struct sbus_dev *devices; /* Tree of SBUS devices */
- struct sbus_bus *next; /* Next SBUS in system */
- int prom_node; /* OBP node of SBUS */
- char prom_name[64]; /* Usually "sbus" or "sbi" */
- int clock_freq;
-
- struct linux_prom_ranges sbus_ranges[PROMREG_MAX];
- int num_sbus_ranges;
-
- int portid;
-};
-#define to_sbus(d) container_of(d, struct sbus_bus, ofdev.dev)
-
-extern struct sbus_bus *sbus_root;
-
-/* Device probing routines could find these handy */
-#define for_each_sbus(bus) \
- for((bus) = sbus_root; (bus); (bus)=(bus)->next)
-
-#define for_each_sbusdev(device, bus) \
- for((device) = (bus)->devices; (device); (device)=(device)->next)
-
-#define for_all_sbusdev(device, bus) \
- for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \
- for ((device) = (bus)->devices; (device); (device) = (device)->next)
-
-/* Driver DVMA interfaces. */
-#define sbus_can_dma_64bit(sdev) (1)
-#define sbus_can_burst64(sdev) (1)
-extern void sbus_set_sbus64(struct sbus_dev *, int);
-extern void sbus_fill_device_irq(struct sbus_dev *);
-
-static inline void *sbus_alloc_consistent(struct sbus_dev *sdev , size_t size,
- dma_addr_t *dma_handle)
-{
- return dma_alloc_coherent(&sdev->ofdev.dev, size,
- dma_handle, GFP_ATOMIC);
-}
-
-static inline void sbus_free_consistent(struct sbus_dev *sdev, size_t size,
- void *vaddr, dma_addr_t dma_handle)
-{
- return dma_free_coherent(&sdev->ofdev.dev, size, vaddr, dma_handle);
-}
-
-#define SBUS_DMA_BIDIRECTIONAL DMA_BIDIRECTIONAL
-#define SBUS_DMA_TODEVICE DMA_TO_DEVICE
-#define SBUS_DMA_FROMDEVICE DMA_FROM_DEVICE
-#define SBUS_DMA_NONE DMA_NONE
-
-/* All the rest use streaming mode mappings. */
-static inline dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr,
- size_t size, int direction)
-{
- return dma_map_single(&sdev->ofdev.dev, ptr, size,
- (enum dma_data_direction) direction);
-}
-
-static inline void sbus_unmap_single(struct sbus_dev *sdev,
- dma_addr_t dma_addr, size_t size,
- int direction)
-{
- dma_unmap_single(&sdev->ofdev.dev, dma_addr, size,
- (enum dma_data_direction) direction);
-}
-
-static inline int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg,
- int nents, int direction)
-{
- return dma_map_sg(&sdev->ofdev.dev, sg, nents,
- (enum dma_data_direction) direction);
-}
-
-static inline void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg,
- int nents, int direction)
-{
- dma_unmap_sg(&sdev->ofdev.dev, sg, nents,
- (enum dma_data_direction) direction);
-}
-
-/* Finally, allow explicit synchronization of streamable mappings. */
-static inline void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev,
- dma_addr_t dma_handle,
- size_t size, int direction)
-{
- dma_sync_single_for_cpu(&sdev->ofdev.dev, dma_handle, size,
- (enum dma_data_direction) direction);
-}
-#define sbus_dma_sync_single sbus_dma_sync_single_for_cpu
-
-static inline void sbus_dma_sync_single_for_device(struct sbus_dev *sdev,
- dma_addr_t dma_handle,
- size_t size, int direction)
-{
- /* No flushing needed to sync cpu writes to the device. */
-}
-
-static inline void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev,
- struct scatterlist *sg,
- int nents, int direction)
-{
- dma_sync_sg_for_cpu(&sdev->ofdev.dev, sg, nents,
- (enum dma_data_direction) direction);
-}
-#define sbus_dma_sync_sg sbus_dma_sync_sg_for_cpu
-
-static inline void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev,
- struct scatterlist *sg,
- int nents, int direction)
-{
- /* No flushing needed to sync cpu writes to the device. */
-}
-
-extern void sbus_arch_bus_ranges_init(struct device_node *, struct sbus_bus *);
-extern void sbus_setup_iommu(struct sbus_bus *, struct device_node *);
-extern void sbus_setup_arch_props(struct sbus_bus *, struct device_node *);
-extern int sbus_arch_preinit(void);
-extern void sbus_arch_postinit(void);
-
-#endif /* !(_SPARC64_SBUS_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_SCATTERLIST_H
-#define ___ASM_SPARC_SCATTERLIST_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/scatterlist_64.h>
-#else
-#include <asm-sparc/scatterlist_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _SPARC_SCATTERLIST_H
-#define _SPARC_SCATTERLIST_H
-
-#include <linux/types.h>
-
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
- unsigned long sg_magic;
-#endif
- unsigned long page_link;
- unsigned int offset;
-
- unsigned int length;
-
- __u32 dvma_address; /* A place to hang host-specific addresses at. */
- __u32 dvma_length;
-};
-
-#define sg_dma_address(sg) ((sg)->dvma_address)
-#define sg_dma_len(sg) ((sg)->dvma_length)
-
-#define ISA_DMA_THRESHOLD (~0UL)
-
-#define ARCH_HAS_SG_CHAIN
-
-#endif /* !(_SPARC_SCATTERLIST_H) */
+++ /dev/null
-#ifndef _SPARC64_SCATTERLIST_H
-#define _SPARC64_SCATTERLIST_H
-
-#include <asm/page.h>
-#include <asm/types.h>
-
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
- unsigned long sg_magic;
-#endif
- unsigned long page_link;
- unsigned int offset;
-
- unsigned int length;
-
- dma_addr_t dma_address;
- __u32 dma_length;
-};
-
-#define sg_dma_address(sg) ((sg)->dma_address)
-#define sg_dma_len(sg) ((sg)->dma_length)
-
-#define ISA_DMA_THRESHOLD (~0UL)
-
-#define ARCH_HAS_SG_CHAIN
-
-#endif /* !(_SPARC64_SCATTERLIST_H) */
+++ /dev/null
-#ifndef _SPARC64_SCRATCHPAD_H
-#define _SPARC64_SCRATCHPAD_H
-
-/* Sun4v scratchpad registers, accessed via ASI_SCRATCHPAD. */
-
-#define SCRATCHPAD_MMU_MISS 0x00 /* Shared with OBP - set by OBP */
-#define SCRATCHPAD_CPUID 0x08 /* Shared with OBP - set by hypervisor */
-#define SCRATCHPAD_UTSBREG1 0x10
-#define SCRATCHPAD_UTSBREG2 0x18
- /* 0x20 and 0x28, hypervisor only... */
-#define SCRATCHPAD_UNUSED1 0x30
-#define SCRATCHPAD_UNUSED2 0x38 /* Reserved for OBP */
-
-#endif /* !(_SPARC64_SCRATCHPAD_H) */
+++ /dev/null
-#ifndef _ASM_SECCOMP_H
-
-#include <linux/thread_info.h> /* already defines TIF_32BIT */
-
-#ifndef TIF_32BIT
-#error "unexpected TIF_32BIT on sparc64"
-#endif
-
-#include <linux/unistd.h>
-
-#define __NR_seccomp_read __NR_read
-#define __NR_seccomp_write __NR_write
-#define __NR_seccomp_exit __NR_exit
-#define __NR_seccomp_sigreturn __NR_rt_sigreturn
-
-#define __NR_seccomp_read_32 __NR_read
-#define __NR_seccomp_write_32 __NR_write
-#define __NR_seccomp_exit_32 __NR_exit
-#define __NR_seccomp_sigreturn_32 __NR_sigreturn
-
-#endif /* _ASM_SECCOMP_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_SECTIONS_H
-#define ___ASM_SPARC_SECTIONS_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/sections_64.h>
-#else
-#include <asm-sparc/sections_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _SPARC_SECTIONS_H
-#define _SPARC_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-#endif
+++ /dev/null
-#ifndef _SPARC64_SECTIONS_H
-#define _SPARC64_SECTIONS_H
-
-/* nothing to see, move along */
-#include <asm-generic/sections.h>
-
-extern char _start[];
-
-#endif
+++ /dev/null
-#ifndef _SPARC_SEMBUF_H
-#define _SPARC_SEMBUF_H
-
-/*
- * The semid64_ds structure for sparc architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-#if defined(__sparc__) && defined(__arch64__)
-# define PADDING(x)
-#else
-# define PADDING(x) unsigned int x;
-#endif
-
-struct semid64_ds {
- struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
- PADDING(__pad1)
- __kernel_time_t sem_otime; /* last semop time */
- PADDING(__pad2)
- __kernel_time_t sem_ctime; /* last change time */
- unsigned long sem_nsems; /* no. of semaphores in array */
- unsigned long __unused1;
- unsigned long __unused2;
-};
-#undef PADDING
-
-#endif /* _SPARC64_SEMBUF_H */
+++ /dev/null
-/*
- * Just a place holder.
- */
-
-#ifndef _SPARC_SETUP_H
-#define _SPARC_SETUP_H
-
-#if defined(__sparc__) && defined(__arch64__)
-# define COMMAND_LINE_SIZE 2048
-#else
-# define COMMAND_LINE_SIZE 256
-#endif
-
-#endif /* _SPARC_SETUP_H */
+++ /dev/null
-#ifndef _SPARC64_SFAFSR_H
-#define _SPARC64_SFAFSR_H
-
-#include <linux/const.h>
-
-/* Spitfire Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
-
-#define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT)
-#define SFAFSR_ME_SHIFT 32
-#define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT)
-#define SFAFSR_PRIV_SHIFT 31
-#define SFAFSR_ISAP (_AC(1,UL) << SFAFSR_ISAP_SHIFT)
-#define SFAFSR_ISAP_SHIFT 30
-#define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT)
-#define SFAFSR_ETP_SHIFT 29
-#define SFAFSR_IVUE (_AC(1,UL) << SFAFSR_IVUE_SHIFT)
-#define SFAFSR_IVUE_SHIFT 28
-#define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT)
-#define SFAFSR_TO_SHIFT 27
-#define SFAFSR_BERR (_AC(1,UL) << SFAFSR_BERR_SHIFT)
-#define SFAFSR_BERR_SHIFT 26
-#define SFAFSR_LDP (_AC(1,UL) << SFAFSR_LDP_SHIFT)
-#define SFAFSR_LDP_SHIFT 25
-#define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT)
-#define SFAFSR_CP_SHIFT 24
-#define SFAFSR_WP (_AC(1,UL) << SFAFSR_WP_SHIFT)
-#define SFAFSR_WP_SHIFT 23
-#define SFAFSR_EDP (_AC(1,UL) << SFAFSR_EDP_SHIFT)
-#define SFAFSR_EDP_SHIFT 22
-#define SFAFSR_UE (_AC(1,UL) << SFAFSR_UE_SHIFT)
-#define SFAFSR_UE_SHIFT 21
-#define SFAFSR_CE (_AC(1,UL) << SFAFSR_CE_SHIFT)
-#define SFAFSR_CE_SHIFT 20
-#define SFAFSR_ETS (_AC(0xf,UL) << SFAFSR_ETS_SHIFT)
-#define SFAFSR_ETS_SHIFT 16
-#define SFAFSR_PSYND (_AC(0xffff,UL) << SFAFSR_PSYND_SHIFT)
-#define SFAFSR_PSYND_SHIFT 0
-
-/* UDB Error Register, ASI=0x7f VA<63:0>=0x0(High),0x18(Low) for read
- * ASI=0x77 VA<63:0>=0x0(High),0x18(Low) for write
- */
-
-#define UDBE_UE (_AC(1,UL) << 9)
-#define UDBE_CE (_AC(1,UL) << 8)
-#define UDBE_E_SYNDR (_AC(0xff,UL) << 0)
-
-/* The trap handlers for asynchronous errors encode the AFSR and
- * other pieces of information into a 64-bit argument for C code
- * encoded as follows:
- *
- * -----------------------------------------------
- * | UDB_H | UDB_L | TL>1 | TT | AFSR |
- * -----------------------------------------------
- * 63 54 53 44 42 41 33 32 0
- *
- * The AFAR is passed in unchanged.
- */
-#define SFSTAT_UDBH_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
-#define SFSTAT_UDBH_SHIFT 54
-#define SFSTAT_UDBL_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
-#define SFSTAT_UDBL_SHIFT 44
-#define SFSTAT_TL_GT_ONE (_AC(1,UL) << SFSTAT_TL_GT_ONE_SHIFT)
-#define SFSTAT_TL_GT_ONE_SHIFT 42
-#define SFSTAT_TRAP_TYPE (_AC(0x1FF,UL) << SFSTAT_TRAP_TYPE_SHIFT)
-#define SFSTAT_TRAP_TYPE_SHIFT 33
-#define SFSTAT_AFSR_MASK (_AC(0x1ffffffff,UL) << SFSTAT_AFSR_SHIFT)
-#define SFSTAT_AFSR_SHIFT 0
-
-/* ESTATE Error Enable Register, ASI=0x4b VA<63:0>=0x0 */
-#define ESTATE_ERR_CE 0x1 /* Correctable errors */
-#define ESTATE_ERR_NCE 0x2 /* TO, BERR, LDP, ETP, EDP, WP, UE, IVUE */
-#define ESTATE_ERR_ISAP 0x4 /* System address parity error */
-#define ESTATE_ERR_ALL (ESTATE_ERR_CE | \
- ESTATE_ERR_NCE | \
- ESTATE_ERR_ISAP)
-
-/* The various trap types that report using the above state. */
-#define TRAP_TYPE_IAE 0x09 /* Instruction Access Error */
-#define TRAP_TYPE_DAE 0x32 /* Data Access Error */
-#define TRAP_TYPE_CEE 0x63 /* Correctable ECC Error */
-
-#endif /* _SPARC64_SFAFSR_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_SFP_MACHINE_H
-#define ___ASM_SPARC_SFP_MACHINE_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/sfp-machine_64.h>
-#else
-#include <asm-sparc/sfp-machine_32.h>
-#endif
-#endif
+++ /dev/null
-/* Machine-dependent software floating-point definitions.
- Sparc userland (_Q_*) version.
- Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Richard Henderson (rth@cygnus.com),
- Jakub Jelinek (jj@ultra.linux.cz),
- David S. Miller (davem@redhat.com) and
- Peter Maydell (pmaydell@chiark.greenend.org.uk).
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Library General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Library General Public License for more details.
-
- You should have received a copy of the GNU Library General Public
- License along with the GNU C Library; see the file COPYING.LIB. If
- not, write to the Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-
-#ifndef _SFP_MACHINE_H
-#define _SFP_MACHINE_H
-
-
-#define _FP_W_TYPE_SIZE 32
-#define _FP_W_TYPE unsigned long
-#define _FP_WS_TYPE signed long
-#define _FP_I_TYPE long
-
-#define _FP_MUL_MEAT_S(R,X,Y) \
- _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
-#define _FP_MUL_MEAT_D(R,X,Y) \
- _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
-#define _FP_MUL_MEAT_Q(R,X,Y) \
- _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
-
-#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv(S,R,X,Y)
-#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
-#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
-
-#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
-#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
-#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
-#define _FP_NANSIGN_S 0
-#define _FP_NANSIGN_D 0
-#define _FP_NANSIGN_Q 0
-
-#define _FP_KEEPNANFRACP 1
-
-/* If one NaN is signaling and the other is not,
- * we choose that one, otherwise we choose X.
- */
-/* For _Qp_* and _Q_*, this should prefer X, for
- * CPU instruction emulation this should prefer Y.
- * (see SPAMv9 B.2.2 section).
- */
-#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
- do { \
- if ((_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs) \
- && !(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)) \
- { \
- R##_s = X##_s; \
- _FP_FRAC_COPY_##wc(R,X); \
- } \
- else \
- { \
- R##_s = Y##_s; \
- _FP_FRAC_COPY_##wc(R,Y); \
- } \
- R##_c = FP_CLS_NAN; \
- } while (0)
-
-/* Some assembly to speed things up. */
-#define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
- __asm__ ("addcc %r7,%8,%2\n\t" \
- "addxcc %r5,%6,%1\n\t" \
- "addx %r3,%4,%0\n" \
- : "=r" ((USItype)(r2)), \
- "=&r" ((USItype)(r1)), \
- "=&r" ((USItype)(r0)) \
- : "%rJ" ((USItype)(x2)), \
- "rI" ((USItype)(y2)), \
- "%rJ" ((USItype)(x1)), \
- "rI" ((USItype)(y1)), \
- "%rJ" ((USItype)(x0)), \
- "rI" ((USItype)(y0)) \
- : "cc")
-
-#define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
- __asm__ ("subcc %r7,%8,%2\n\t" \
- "subxcc %r5,%6,%1\n\t" \
- "subx %r3,%4,%0\n" \
- : "=r" ((USItype)(r2)), \
- "=&r" ((USItype)(r1)), \
- "=&r" ((USItype)(r0)) \
- : "%rJ" ((USItype)(x2)), \
- "rI" ((USItype)(y2)), \
- "%rJ" ((USItype)(x1)), \
- "rI" ((USItype)(y1)), \
- "%rJ" ((USItype)(x0)), \
- "rI" ((USItype)(y0)) \
- : "cc")
-
-#define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
- do { \
- /* We need to fool gcc, as we need to pass more than 10 \
- input/outputs. */ \
- register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2"); \
- __asm__ __volatile__ ( \
- "addcc %r8,%9,%1\n\t" \
- "addxcc %r6,%7,%0\n\t" \
- "addxcc %r4,%5,%%g2\n\t" \
- "addx %r2,%3,%%g1\n\t" \
- : "=&r" ((USItype)(r1)), \
- "=&r" ((USItype)(r0)) \
- : "%rJ" ((USItype)(x3)), \
- "rI" ((USItype)(y3)), \
- "%rJ" ((USItype)(x2)), \
- "rI" ((USItype)(y2)), \
- "%rJ" ((USItype)(x1)), \
- "rI" ((USItype)(y1)), \
- "%rJ" ((USItype)(x0)), \
- "rI" ((USItype)(y0)) \
- : "cc", "g1", "g2"); \
- __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2)); \
- r3 = _t1; r2 = _t2; \
- } while (0)
-
-#define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
- do { \
- /* We need to fool gcc, as we need to pass more than 10 \
- input/outputs. */ \
- register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2"); \
- __asm__ __volatile__ ( \
- "subcc %r8,%9,%1\n\t" \
- "subxcc %r6,%7,%0\n\t" \
- "subxcc %r4,%5,%%g2\n\t" \
- "subx %r2,%3,%%g1\n\t" \
- : "=&r" ((USItype)(r1)), \
- "=&r" ((USItype)(r0)) \
- : "%rJ" ((USItype)(x3)), \
- "rI" ((USItype)(y3)), \
- "%rJ" ((USItype)(x2)), \
- "rI" ((USItype)(y2)), \
- "%rJ" ((USItype)(x1)), \
- "rI" ((USItype)(y1)), \
- "%rJ" ((USItype)(x0)), \
- "rI" ((USItype)(y0)) \
- : "cc", "g1", "g2"); \
- __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2)); \
- r3 = _t1; r2 = _t2; \
- } while (0)
-
-#define __FP_FRAC_DEC_3(x2,x1,x0,y2,y1,y0) __FP_FRAC_SUB_3(x2,x1,x0,x2,x1,x0,y2,y1,y0)
-
-#define __FP_FRAC_DEC_4(x3,x2,x1,x0,y3,y2,y1,y0) __FP_FRAC_SUB_4(x3,x2,x1,x0,x3,x2,x1,x0,y3,y2,y1,y0)
-
-#define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i) \
- __asm__ ("addcc %3,%4,%3\n\t" \
- "addxcc %2,%%g0,%2\n\t" \
- "addxcc %1,%%g0,%1\n\t" \
- "addx %0,%%g0,%0\n\t" \
- : "=&r" ((USItype)(x3)), \
- "=&r" ((USItype)(x2)), \
- "=&r" ((USItype)(x1)), \
- "=&r" ((USItype)(x0)) \
- : "rI" ((USItype)(i)), \
- "0" ((USItype)(x3)), \
- "1" ((USItype)(x2)), \
- "2" ((USItype)(x1)), \
- "3" ((USItype)(x0)) \
- : "cc")
-
-#ifndef CONFIG_SMP
-extern struct task_struct *last_task_used_math;
-#endif
-
-/* Obtain the current rounding mode. */
-#ifndef FP_ROUNDMODE
-#ifdef CONFIG_SMP
-#define FP_ROUNDMODE ((current->thread.fsr >> 30) & 0x3)
-#else
-#define FP_ROUNDMODE ((last_task_used_math->thread.fsr >> 30) & 0x3)
-#endif
-#endif
-
-/* Exception flags. */
-#define FP_EX_INVALID (1 << 4)
-#define FP_EX_OVERFLOW (1 << 3)
-#define FP_EX_UNDERFLOW (1 << 2)
-#define FP_EX_DIVZERO (1 << 1)
-#define FP_EX_INEXACT (1 << 0)
-
-#define FP_HANDLE_EXCEPTIONS return _fex
-
-#ifdef CONFIG_SMP
-#define FP_INHIBIT_RESULTS ((current->thread.fsr >> 23) & _fex)
-#else
-#define FP_INHIBIT_RESULTS ((last_task_used_math->thread.fsr >> 23) & _fex)
-#endif
-
-#ifdef CONFIG_SMP
-#define FP_TRAPPING_EXCEPTIONS ((current->thread.fsr >> 23) & 0x1f)
-#else
-#define FP_TRAPPING_EXCEPTIONS ((last_task_used_math->thread.fsr >> 23) & 0x1f)
-#endif
-
-#endif
+++ /dev/null
-/* Machine-dependent software floating-point definitions.
- Sparc64 kernel version.
- Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Richard Henderson (rth@cygnus.com),
- Jakub Jelinek (jj@ultra.linux.cz) and
- David S. Miller (davem@redhat.com).
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Library General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Library General Public License for more details.
-
- You should have received a copy of the GNU Library General Public
- License along with the GNU C Library; see the file COPYING.LIB. If
- not, write to the Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-
-#ifndef _SFP_MACHINE_H
-#define _SFP_MACHINE_H
-
-#define _FP_W_TYPE_SIZE 64
-#define _FP_W_TYPE unsigned long
-#define _FP_WS_TYPE signed long
-#define _FP_I_TYPE long
-
-#define _FP_MUL_MEAT_S(R,X,Y) \
- _FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y)
-#define _FP_MUL_MEAT_D(R,X,Y) \
- _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
-#define _FP_MUL_MEAT_Q(R,X,Y) \
- _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
-
-#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm)
-#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y)
-#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
-
-#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
-#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1)
-#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1
-#define _FP_NANSIGN_S 0
-#define _FP_NANSIGN_D 0
-#define _FP_NANSIGN_Q 0
-
-#define _FP_KEEPNANFRACP 1
-
-/* If one NaN is signaling and the other is not,
- * we choose that one, otherwise we choose X.
- */
-/* For _Qp_* and _Q_*, this should prefer X, for
- * CPU instruction emulation this should prefer Y.
- * (see SPAMv9 B.2.2 section).
- */
-#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
- do { \
- if ((_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs) \
- && !(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)) \
- { \
- R##_s = X##_s; \
- _FP_FRAC_COPY_##wc(R,X); \
- } \
- else \
- { \
- R##_s = Y##_s; \
- _FP_FRAC_COPY_##wc(R,Y); \
- } \
- R##_c = FP_CLS_NAN; \
- } while (0)
-
-/* Obtain the current rounding mode. */
-#ifndef FP_ROUNDMODE
-#define FP_ROUNDMODE ((current_thread_info()->xfsr[0] >> 30) & 0x3)
-#endif
-
-/* Exception flags. */
-#define FP_EX_INVALID (1 << 4)
-#define FP_EX_OVERFLOW (1 << 3)
-#define FP_EX_UNDERFLOW (1 << 2)
-#define FP_EX_DIVZERO (1 << 1)
-#define FP_EX_INEXACT (1 << 0)
-
-#define FP_HANDLE_EXCEPTIONS return _fex
-
-#define FP_INHIBIT_RESULTS ((current_thread_info()->xfsr[0] >> 23) & _fex)
-
-#define FP_TRAPPING_EXCEPTIONS ((current_thread_info()->xfsr[0] >> 23) & 0x1f)
-
-#endif
+++ /dev/null
-#ifndef _SPARC_SHMBUF_H
-#define _SPARC_SHMBUF_H
-
-/*
- * The shmid64_ds structure for sparc architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-#if defined(__sparc__) && defined(__arch64__)
-# define PADDING(x)
-#else
-# define PADDING(x) unsigned int x;
-#endif
-
-struct shmid64_ds {
- struct ipc64_perm shm_perm; /* operation perms */
- PADDING(__pad1)
- __kernel_time_t shm_atime; /* last attach time */
- PADDING(__pad2)
- __kernel_time_t shm_dtime; /* last detach time */
- PADDING(__pad3)
- __kernel_time_t shm_ctime; /* last change time */
- size_t shm_segsz; /* size of segment (bytes) */
- __kernel_pid_t shm_cpid; /* pid of creator */
- __kernel_pid_t shm_lpid; /* pid of last operator */
- unsigned long shm_nattch; /* no. of current attaches */
- unsigned long __unused1;
- unsigned long __unused2;
-};
-
-struct shminfo64 {
- unsigned long shmmax;
- unsigned long shmmin;
- unsigned long shmmni;
- unsigned long shmseg;
- unsigned long shmall;
- unsigned long __unused1;
- unsigned long __unused2;
- unsigned long __unused3;
- unsigned long __unused4;
-};
-
-#undef PADDING
-
-#endif /* _SPARC_SHMBUF_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_SHMPARAM_H
-#define ___ASM_SPARC_SHMPARAM_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/shmparam_64.h>
-#else
-#include <asm-sparc/shmparam_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _ASMSPARC_SHMPARAM_H
-#define _ASMSPARC_SHMPARAM_H
-
-#define __ARCH_FORCE_SHMLBA 1
-
-extern int vac_cache_size;
-#define SHMLBA (vac_cache_size ? vac_cache_size : \
- (sparc_cpu_model == sun4c ? (64 * 1024) : \
- (sparc_cpu_model == sun4 ? (128 * 1024) : PAGE_SIZE)))
-
-#endif /* _ASMSPARC_SHMPARAM_H */
+++ /dev/null
-#ifndef _ASMSPARC64_SHMPARAM_H
-#define _ASMSPARC64_SHMPARAM_H
-
-#include <asm/spitfire.h>
-
-#define __ARCH_FORCE_SHMLBA 1
-/* attach addr a multiple of this */
-#define SHMLBA ((PAGE_SIZE > L1DCACHE_SIZE) ? PAGE_SIZE : L1DCACHE_SIZE)
-
-#endif /* _ASMSPARC64_SHMPARAM_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_SIGCONTEXT_H
-#define ___ASM_SPARC_SIGCONTEXT_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/sigcontext_64.h>
-#else
-#include <asm-sparc/sigcontext_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef __SPARC_SIGCONTEXT_H
-#define __SPARC_SIGCONTEXT_H
-
-#ifdef __KERNEL__
-#include <asm/ptrace.h>
-
-#ifndef __ASSEMBLY__
-
-#define __SUNOS_MAXWIN 31
-
-/* This is what SunOS does, so shall I. */
-struct sigcontext {
- int sigc_onstack; /* state to restore */
- int sigc_mask; /* sigmask to restore */
- int sigc_sp; /* stack pointer */
- int sigc_pc; /* program counter */
- int sigc_npc; /* next program counter */
- int sigc_psr; /* for condition codes etc */
- int sigc_g1; /* User uses these two registers */
- int sigc_o0; /* within the trampoline code. */
-
- /* Now comes information regarding the users window set
- * at the time of the signal.
- */
- int sigc_oswins; /* outstanding windows */
-
- /* stack ptrs for each regwin buf */
- char *sigc_spbuf[__SUNOS_MAXWIN];
-
- /* Windows to restore after signal */
- struct {
- unsigned long locals[8];
- unsigned long ins[8];
- } sigc_wbuf[__SUNOS_MAXWIN];
-};
-
-typedef struct {
- struct {
- unsigned long psr;
- unsigned long pc;
- unsigned long npc;
- unsigned long y;
- unsigned long u_regs[16]; /* globals and ins */
- } si_regs;
- int si_mask;
-} __siginfo_t;
-
-typedef struct {
- unsigned long si_float_regs [32];
- unsigned long si_fsr;
- unsigned long si_fpqdepth;
- struct {
- unsigned long *insn_addr;
- unsigned long insn;
- } si_fpqueue [16];
-} __siginfo_fpu_t;
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* (__KERNEL__) */
-
-#endif /* !(__SPARC_SIGCONTEXT_H) */
+++ /dev/null
-#ifndef __SPARC64_SIGCONTEXT_H
-#define __SPARC64_SIGCONTEXT_H
-
-#ifdef __KERNEL__
-#include <asm/ptrace.h>
-#endif
-
-#ifndef __ASSEMBLY__
-
-#ifdef __KERNEL__
-
-#define __SUNOS_MAXWIN 31
-
-/* This is what SunOS does, so shall I unless we use new 32bit signals or rt signals. */
-struct sigcontext32 {
- int sigc_onstack; /* state to restore */
- int sigc_mask; /* sigmask to restore */
- int sigc_sp; /* stack pointer */
- int sigc_pc; /* program counter */
- int sigc_npc; /* next program counter */
- int sigc_psr; /* for condition codes etc */
- int sigc_g1; /* User uses these two registers */
- int sigc_o0; /* within the trampoline code. */
-
- /* Now comes information regarding the users window set
- * at the time of the signal.
- */
- int sigc_oswins; /* outstanding windows */
-
- /* stack ptrs for each regwin buf */
- unsigned sigc_spbuf[__SUNOS_MAXWIN];
-
- /* Windows to restore after signal */
- struct reg_window32 sigc_wbuf[__SUNOS_MAXWIN];
-};
-
-#endif
-
-#ifdef __KERNEL__
-
-/* This is what we use for 32bit new non-rt signals. */
-
-typedef struct {
- struct {
- unsigned int psr;
- unsigned int pc;
- unsigned int npc;
- unsigned int y;
- unsigned int u_regs[16]; /* globals and ins */
- } si_regs;
- int si_mask;
-} __siginfo32_t;
-
-#endif
-
-typedef struct {
- unsigned int si_float_regs [64];
- unsigned long si_fsr;
- unsigned long si_gsr;
- unsigned long si_fprs;
-} __siginfo_fpu_t;
-
-/* This is what SunOS doesn't, so we have to write this alone
- and do it properly. */
-struct sigcontext {
- /* The size of this array has to match SI_MAX_SIZE from siginfo.h */
- char sigc_info[128];
- struct {
- unsigned long u_regs[16]; /* globals and ins */
- unsigned long tstate;
- unsigned long tpc;
- unsigned long tnpc;
- unsigned int y;
- unsigned int fprs;
- } sigc_regs;
- __siginfo_fpu_t * sigc_fpu_save;
- struct {
- void * ss_sp;
- int ss_flags;
- unsigned long ss_size;
- } sigc_stack;
- unsigned long sigc_mask;
-};
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(__SPARC64_SIGCONTEXT_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_SIGINFO_H
-#define ___ASM_SPARC_SIGINFO_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/siginfo_64.h>
-#else
-#include <asm-sparc/siginfo_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _SPARC_SIGINFO_H
-#define _SPARC_SIGINFO_H
-
-#define __ARCH_SI_UID_T unsigned int
-#define __ARCH_SI_TRAPNO
-
-#include <asm-generic/siginfo.h>
-
-#define SI_NOINFO 32767 /* no information in siginfo_t */
-
-/*
- * SIGEMT si_codes
- */
-#define EMT_TAGOVF (__SI_FAULT|1) /* tag overflow */
-#define NSIGEMT 1
-
-#endif /* !(_SPARC_SIGINFO_H) */
+++ /dev/null
-#ifndef _SPARC64_SIGINFO_H
-#define _SPARC64_SIGINFO_H
-
-#define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3)
-
-#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
-#define __ARCH_SI_TRAPNO
-#define __ARCH_SI_BAND_T int
-
-#include <asm-generic/siginfo.h>
-
-#ifdef __KERNEL__
-
-#include <linux/compat.h>
-
-#ifdef CONFIG_COMPAT
-
-struct compat_siginfo;
-
-#endif /* CONFIG_COMPAT */
-
-#endif /* __KERNEL__ */
-
-#define SI_NOINFO 32767 /* no information in siginfo_t */
-
-/*
- * SIGEMT si_codes
- */
-#define EMT_TAGOVF (__SI_FAULT|1) /* tag overflow */
-#define NSIGEMT 1
-
-#endif
+++ /dev/null
-#ifndef ___ASM_SPARC_SIGNAL_H
-#define ___ASM_SPARC_SIGNAL_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/signal_64.h>
-#else
-#include <asm-sparc/signal_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _ASMSPARC_SIGNAL_H
-#define _ASMSPARC_SIGNAL_H
-
-#include <asm/sigcontext.h>
-#include <linux/compiler.h>
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-#include <linux/personality.h>
-#include <linux/types.h>
-#endif
-#endif
-
-/* On the Sparc the signal handlers get passed a 'sub-signal' code
- * for certain signal types, which we document here.
- */
-#define SIGHUP 1
-#define SIGINT 2
-#define SIGQUIT 3
-#define SIGILL 4
-#define SUBSIG_STACK 0
-#define SUBSIG_ILLINST 2
-#define SUBSIG_PRIVINST 3
-#define SUBSIG_BADTRAP(t) (0x80 + (t))
-
-#define SIGTRAP 5
-#define SIGABRT 6
-#define SIGIOT 6
-
-#define SIGEMT 7
-#define SUBSIG_TAG 10
-
-#define SIGFPE 8
-#define SUBSIG_FPDISABLED 0x400
-#define SUBSIG_FPERROR 0x404
-#define SUBSIG_FPINTOVFL 0x001
-#define SUBSIG_FPSTSIG 0x002
-#define SUBSIG_IDIVZERO 0x014
-#define SUBSIG_FPINEXACT 0x0c4
-#define SUBSIG_FPDIVZERO 0x0c8
-#define SUBSIG_FPUNFLOW 0x0cc
-#define SUBSIG_FPOPERROR 0x0d0
-#define SUBSIG_FPOVFLOW 0x0d4
-
-#define SIGKILL 9
-#define SIGBUS 10
-#define SUBSIG_BUSTIMEOUT 1
-#define SUBSIG_ALIGNMENT 2
-#define SUBSIG_MISCERROR 5
-
-#define SIGSEGV 11
-#define SUBSIG_NOMAPPING 3
-#define SUBSIG_PROTECTION 4
-#define SUBSIG_SEGERROR 5
-
-#define SIGSYS 12
-
-#define SIGPIPE 13
-#define SIGALRM 14
-#define SIGTERM 15
-#define SIGURG 16
-
-/* SunOS values which deviate from the Linux/i386 ones */
-#define SIGSTOP 17
-#define SIGTSTP 18
-#define SIGCONT 19
-#define SIGCHLD 20
-#define SIGTTIN 21
-#define SIGTTOU 22
-#define SIGIO 23
-#define SIGPOLL SIGIO /* SysV name for SIGIO */
-#define SIGXCPU 24
-#define SIGXFSZ 25
-#define SIGVTALRM 26
-#define SIGPROF 27
-#define SIGWINCH 28
-#define SIGLOST 29
-#define SIGPWR SIGLOST
-#define SIGUSR1 30
-#define SIGUSR2 31
-
-/* Most things should be clean enough to redefine this at will, if care
- * is taken to make libc match.
- */
-
-#define __OLD_NSIG 32
-#define __NEW_NSIG 64
-#define _NSIG_BPW 32
-#define _NSIG_WORDS (__NEW_NSIG / _NSIG_BPW)
-
-#define SIGRTMIN 32
-#define SIGRTMAX __NEW_NSIG
-
-#if defined(__KERNEL__) || defined(__WANT_POSIX1B_SIGNALS__)
-#define _NSIG __NEW_NSIG
-#define __new_sigset_t sigset_t
-#define __new_sigaction sigaction
-#define __old_sigset_t old_sigset_t
-#define __old_sigaction old_sigaction
-#else
-#define _NSIG __OLD_NSIG
-#define __old_sigset_t sigset_t
-#define __old_sigaction sigaction
-#endif
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned long __old_sigset_t;
-
-typedef struct {
- unsigned long sig[_NSIG_WORDS];
-} __new_sigset_t;
-
-
-#ifdef __KERNEL__
-/* A SunOS sigstack */
-struct sigstack {
- char *the_stack;
- int cur_status;
-};
-#endif
-
-/* Sigvec flags */
-#define _SV_SSTACK 1u /* This signal handler should use sig-stack */
-#define _SV_INTR 2u /* Sig return should not restart system call */
-#define _SV_RESET 4u /* Set handler to SIG_DFL upon taken signal */
-#define _SV_IGNCHILD 8u /* Do not send SIGCHLD */
-
-/*
- * sa_flags values: SA_STACK is not currently supported, but will allow the
- * usage of signal stacks by using the (now obsolete) sa_restorer field in
- * the sigaction structure as a stack pointer. This is now possible due to
- * the changes in signal handling. LBT 010493.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- */
-#define SA_NOCLDSTOP _SV_IGNCHILD
-#define SA_STACK _SV_SSTACK
-#define SA_ONSTACK _SV_SSTACK
-#define SA_RESTART _SV_INTR
-#define SA_ONESHOT _SV_RESET
-#define SA_NOMASK 0x20u
-#define SA_NOCLDWAIT 0x100u
-#define SA_SIGINFO 0x200u
-
-#define SIG_BLOCK 0x01 /* for blocking signals */
-#define SIG_UNBLOCK 0x02 /* for unblocking signals */
-#define SIG_SETMASK 0x04 /* for setting the signal mask */
-
-/*
- * sigaltstack controls
- */
-#define SS_ONSTACK 1
-#define SS_DISABLE 2
-
-#define MINSIGSTKSZ 4096
-#define SIGSTKSZ 16384
-
-#ifdef __KERNEL__
-/*
- * DJHR
- * SA_STATIC_ALLOC is used for the SPARC system to indicate that this
- * interrupt handler's irq structure should be statically allocated
- * by the request_irq routine.
- * The alternative is that arch/sparc/kernel/irq.c has carnal knowledge
- * of interrupt usage and that sucks. Also without a flag like this
- * it may be possible for the free_irq routine to attempt to free
- * statically allocated data.. which is NOT GOOD.
- *
- */
-#define SA_STATIC_ALLOC 0x8000
-#endif
-
-#include <asm-generic/signal.h>
-
-#ifdef __KERNEL__
-struct __new_sigaction {
- __sighandler_t sa_handler;
- unsigned long sa_flags;
- void (*sa_restorer)(void); /* Not used by Linux/SPARC */
- __new_sigset_t sa_mask;
-};
-
-struct k_sigaction {
- struct __new_sigaction sa;
- void __user *ka_restorer;
-};
-
-struct __old_sigaction {
- __sighandler_t sa_handler;
- __old_sigset_t sa_mask;
- unsigned long sa_flags;
- void (*sa_restorer) (void); /* not used by Linux/SPARC */
-};
-
-typedef struct sigaltstack {
- void __user *ss_sp;
- int ss_flags;
- size_t ss_size;
-} stack_t;
-
-#define ptrace_signal_deliver(regs, cookie) do { } while (0)
-
-#endif /* !(__KERNEL__) */
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(_ASMSPARC_SIGNAL_H) */
+++ /dev/null
-#ifndef _ASMSPARC64_SIGNAL_H
-#define _ASMSPARC64_SIGNAL_H
-
-#include <asm/sigcontext.h>
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-#include <linux/personality.h>
-#include <linux/types.h>
-#endif
-#endif
-
-/* On the Sparc the signal handlers get passed a 'sub-signal' code
- * for certain signal types, which we document here.
- */
-#define SIGHUP 1
-#define SIGINT 2
-#define SIGQUIT 3
-#define SIGILL 4
-#define SUBSIG_STACK 0
-#define SUBSIG_ILLINST 2
-#define SUBSIG_PRIVINST 3
-#define SUBSIG_BADTRAP(t) (0x80 + (t))
-
-#define SIGTRAP 5
-#define SIGABRT 6
-#define SIGIOT 6
-
-#define SIGEMT 7
-#define SUBSIG_TAG 10
-
-#define SIGFPE 8
-#define SUBSIG_FPDISABLED 0x400
-#define SUBSIG_FPERROR 0x404
-#define SUBSIG_FPINTOVFL 0x001
-#define SUBSIG_FPSTSIG 0x002
-#define SUBSIG_IDIVZERO 0x014
-#define SUBSIG_FPINEXACT 0x0c4
-#define SUBSIG_FPDIVZERO 0x0c8
-#define SUBSIG_FPUNFLOW 0x0cc
-#define SUBSIG_FPOPERROR 0x0d0
-#define SUBSIG_FPOVFLOW 0x0d4
-
-#define SIGKILL 9
-#define SIGBUS 10
-#define SUBSIG_BUSTIMEOUT 1
-#define SUBSIG_ALIGNMENT 2
-#define SUBSIG_MISCERROR 5
-
-#define SIGSEGV 11
-#define SUBSIG_NOMAPPING 3
-#define SUBSIG_PROTECTION 4
-#define SUBSIG_SEGERROR 5
-
-#define SIGSYS 12
-
-#define SIGPIPE 13
-#define SIGALRM 14
-#define SIGTERM 15
-#define SIGURG 16
-
-/* SunOS values which deviate from the Linux/i386 ones */
-#define SIGSTOP 17
-#define SIGTSTP 18
-#define SIGCONT 19
-#define SIGCHLD 20
-#define SIGTTIN 21
-#define SIGTTOU 22
-#define SIGIO 23
-#define SIGPOLL SIGIO /* SysV name for SIGIO */
-#define SIGXCPU 24
-#define SIGXFSZ 25
-#define SIGVTALRM 26
-#define SIGPROF 27
-#define SIGWINCH 28
-#define SIGLOST 29
-#define SIGPWR SIGLOST
-#define SIGUSR1 30
-#define SIGUSR2 31
-
-/* Most things should be clean enough to redefine this at will, if care
- is taken to make libc match. */
-
-#define __OLD_NSIG 32
-#define __NEW_NSIG 64
-#define _NSIG_BPW 64
-#define _NSIG_WORDS (__NEW_NSIG / _NSIG_BPW)
-
-#define SIGRTMIN 32
-#define SIGRTMAX __NEW_NSIG
-
-#if defined(__KERNEL__) || defined(__WANT_POSIX1B_SIGNALS__)
-#define _NSIG __NEW_NSIG
-#define __new_sigset_t sigset_t
-#define __new_sigaction sigaction
-#define __new_sigaction32 sigaction32
-#define __old_sigset_t old_sigset_t
-#define __old_sigaction old_sigaction
-#define __old_sigaction32 old_sigaction32
-#else
-#define _NSIG __OLD_NSIG
-#define NSIG _NSIG
-#define __old_sigset_t sigset_t
-#define __old_sigaction sigaction
-#define __old_sigaction32 sigaction32
-#endif
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned long __old_sigset_t; /* at least 32 bits */
-
-typedef struct {
- unsigned long sig[_NSIG_WORDS];
-} __new_sigset_t;
-
-/* A SunOS sigstack */
-struct sigstack {
- /* XXX 32-bit pointers pinhead XXX */
- char *the_stack;
- int cur_status;
-};
-
-/* Sigvec flags */
-#define _SV_SSTACK 1u /* This signal handler should use sig-stack */
-#define _SV_INTR 2u /* Sig return should not restart system call */
-#define _SV_RESET 4u /* Set handler to SIG_DFL upon taken signal */
-#define _SV_IGNCHILD 8u /* Do not send SIGCHLD */
-
-/*
- * sa_flags values: SA_STACK is not currently supported, but will allow the
- * usage of signal stacks by using the (now obsolete) sa_restorer field in
- * the sigaction structure as a stack pointer. This is now possible due to
- * the changes in signal handling. LBT 010493.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- */
-#define SA_NOCLDSTOP _SV_IGNCHILD
-#define SA_STACK _SV_SSTACK
-#define SA_ONSTACK _SV_SSTACK
-#define SA_RESTART _SV_INTR
-#define SA_ONESHOT _SV_RESET
-#define SA_NOMASK 0x20u
-#define SA_NOCLDWAIT 0x100u
-#define SA_SIGINFO 0x200u
-
-
-#define SIG_BLOCK 0x01 /* for blocking signals */
-#define SIG_UNBLOCK 0x02 /* for unblocking signals */
-#define SIG_SETMASK 0x04 /* for setting the signal mask */
-
-/*
- * sigaltstack controls
- */
-#define SS_ONSTACK 1
-#define SS_DISABLE 2
-
-#define MINSIGSTKSZ 4096
-#define SIGSTKSZ 16384
-
-#include <asm-generic/signal.h>
-
-struct __new_sigaction {
- __sighandler_t sa_handler;
- unsigned long sa_flags;
- __sigrestore_t sa_restorer; /* not used by Linux/SPARC yet */
- __new_sigset_t sa_mask;
-};
-
-struct __old_sigaction {
- __sighandler_t sa_handler;
- __old_sigset_t sa_mask;
- unsigned long sa_flags;
- void (*sa_restorer)(void); /* not used by Linux/SPARC yet */
-};
-
-typedef struct sigaltstack {
- void __user *ss_sp;
- int ss_flags;
- size_t ss_size;
-} stack_t;
-
-#ifdef __KERNEL__
-
-struct k_sigaction {
- struct __new_sigaction sa;
- void __user *ka_restorer;
-};
-
-#define ptrace_signal_deliver(regs, cookie) do { } while (0)
-
-#endif /* !(__KERNEL__) */
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(_ASMSPARC64_SIGNAL_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_SMP_H
-#define ___ASM_SPARC_SMP_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/smp_64.h>
-#else
-#include <asm-sparc/smp_32.h>
-#endif
-#endif
+++ /dev/null
-/* smp.h: Sparc specific SMP stuff.
- *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_SMP_H
-#define _SPARC_SMP_H
-
-#include <linux/threads.h>
-#include <asm/head.h>
-#include <asm/btfixup.h>
-
-#ifndef __ASSEMBLY__
-
-#include <linux/cpumask.h>
-
-#endif /* __ASSEMBLY__ */
-
-#ifdef CONFIG_SMP
-
-#ifndef __ASSEMBLY__
-
-#include <asm/ptrace.h>
-#include <asm/asi.h>
-#include <asm/atomic.h>
-
-/*
- * Private routines/data
- */
-
-extern unsigned char boot_cpu_id;
-extern cpumask_t phys_cpu_present_map;
-#define cpu_possible_map phys_cpu_present_map
-
-typedef void (*smpfunc_t)(unsigned long, unsigned long, unsigned long,
- unsigned long, unsigned long);
-
-/*
- * General functions that each host system must provide.
- */
-
-void sun4m_init_smp(void);
-void sun4d_init_smp(void);
-
-void smp_callin(void);
-void smp_boot_cpus(void);
-void smp_store_cpu_info(int);
-
-struct seq_file;
-void smp_bogo(struct seq_file *);
-void smp_info(struct seq_file *);
-
-BTFIXUPDEF_CALL(void, smp_cross_call, smpfunc_t, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long)
-BTFIXUPDEF_CALL(int, __hard_smp_processor_id, void)
-BTFIXUPDEF_BLACKBOX(hard_smp_processor_id)
-BTFIXUPDEF_BLACKBOX(load_current)
-
-#define smp_cross_call(func,arg1,arg2,arg3,arg4,arg5) BTFIXUP_CALL(smp_cross_call)(func,arg1,arg2,arg3,arg4,arg5)
-
-static inline void xc0(smpfunc_t func) { smp_cross_call(func, 0, 0, 0, 0, 0); }
-static inline void xc1(smpfunc_t func, unsigned long arg1)
-{ smp_cross_call(func, arg1, 0, 0, 0, 0); }
-static inline void xc2(smpfunc_t func, unsigned long arg1, unsigned long arg2)
-{ smp_cross_call(func, arg1, arg2, 0, 0, 0); }
-static inline void xc3(smpfunc_t func, unsigned long arg1, unsigned long arg2,
- unsigned long arg3)
-{ smp_cross_call(func, arg1, arg2, arg3, 0, 0); }
-static inline void xc4(smpfunc_t func, unsigned long arg1, unsigned long arg2,
- unsigned long arg3, unsigned long arg4)
-{ smp_cross_call(func, arg1, arg2, arg3, arg4, 0); }
-static inline void xc5(smpfunc_t func, unsigned long arg1, unsigned long arg2,
- unsigned long arg3, unsigned long arg4, unsigned long arg5)
-{ smp_cross_call(func, arg1, arg2, arg3, arg4, arg5); }
-
-static inline int smp_call_function(void (*func)(void *info), void *info, int wait)
-{
- xc1((smpfunc_t)func, (unsigned long)info);
- return 0;
-}
-
-static inline int cpu_logical_map(int cpu)
-{
- return cpu;
-}
-
-static inline int hard_smp4m_processor_id(void)
-{
- int cpuid;
-
- __asm__ __volatile__("rd %%tbr, %0\n\t"
- "srl %0, 12, %0\n\t"
- "and %0, 3, %0\n\t" :
- "=&r" (cpuid));
- return cpuid;
-}
-
-static inline int hard_smp4d_processor_id(void)
-{
- int cpuid;
-
- __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
- "=&r" (cpuid) : "i" (ASI_M_VIKING_TMP1));
- return cpuid;
-}
-
-#ifndef MODULE
-static inline int hard_smp_processor_id(void)
-{
- int cpuid;
-
- /* Black box - sun4m
- __asm__ __volatile__("rd %%tbr, %0\n\t"
- "srl %0, 12, %0\n\t"
- "and %0, 3, %0\n\t" :
- "=&r" (cpuid));
- - sun4d
- __asm__ __volatile__("lda [%g0] ASI_M_VIKING_TMP1, %0\n\t"
- "nop; nop" :
- "=&r" (cpuid));
- See btfixup.h and btfixupprep.c to understand how a blackbox works.
- */
- __asm__ __volatile__("sethi %%hi(___b_hard_smp_processor_id), %0\n\t"
- "sethi %%hi(boot_cpu_id), %0\n\t"
- "ldub [%0 + %%lo(boot_cpu_id)], %0\n\t" :
- "=&r" (cpuid));
- return cpuid;
-}
-#else
-static inline int hard_smp_processor_id(void)
-{
- int cpuid;
-
- __asm__ __volatile__("mov %%o7, %%g1\n\t"
- "call ___f___hard_smp_processor_id\n\t"
- " nop\n\t"
- "mov %%g2, %0\n\t" : "=r"(cpuid) : : "g1", "g2");
- return cpuid;
-}
-#endif
-
-#define raw_smp_processor_id() (current_thread_info()->cpu)
-
-#define prof_multiplier(__cpu) cpu_data(__cpu).multiplier
-#define prof_counter(__cpu) cpu_data(__cpu).counter
-
-void smp_setup_cpu_possible_map(void);
-
-#endif /* !(__ASSEMBLY__) */
-
-/* Sparc specific messages. */
-#define MSG_CROSS_CALL 0x0005 /* run func on cpus */
-
-/* Empirical PROM processor mailbox constants. If the per-cpu mailbox
- * contains something other than one of these then the ipi is from
- * Linux's active_kernel_processor. This facility exists so that
- * the boot monitor can capture all the other cpus when one catches
- * a watchdog reset or the user enters the monitor using L1-A keys.
- */
-#define MBOX_STOPCPU 0xFB
-#define MBOX_IDLECPU 0xFC
-#define MBOX_IDLECPU2 0xFD
-#define MBOX_STOPCPU2 0xFE
-
-#else /* SMP */
-
-#define hard_smp_processor_id() 0
-#define smp_setup_cpu_possible_map() do { } while (0)
-
-#endif /* !(SMP) */
-
-#define NO_PROC_ID 0xFF
-
-#endif /* !(_SPARC_SMP_H) */
+++ /dev/null
-/* smp.h: Sparc64 specific SMP stuff.
- *
- * Copyright (C) 1996, 2008 David S. Miller (davem@davemloft.net)
- */
-
-#ifndef _SPARC64_SMP_H
-#define _SPARC64_SMP_H
-
-#include <linux/threads.h>
-#include <asm/asi.h>
-#include <asm/starfire.h>
-#include <asm/spitfire.h>
-
-#ifndef __ASSEMBLY__
-
-#include <linux/cpumask.h>
-#include <linux/cache.h>
-
-#endif /* !(__ASSEMBLY__) */
-
-#ifdef CONFIG_SMP
-
-#ifndef __ASSEMBLY__
-
-/*
- * Private routines/data
- */
-
-#include <linux/bitops.h>
-#include <asm/atomic.h>
-#include <asm/percpu.h>
-
-DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
-extern cpumask_t cpu_core_map[NR_CPUS];
-extern int sparc64_multi_core;
-
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi(cpumask_t mask);
-
-/*
- * General functions that each host system must provide.
- */
-
-extern int hard_smp_processor_id(void);
-#define raw_smp_processor_id() (current_thread_info()->cpu)
-
-extern void smp_fill_in_sib_core_maps(void);
-extern void cpu_play_dead(void);
-
-extern void smp_fetch_global_regs(void);
-
-#ifdef CONFIG_HOTPLUG_CPU
-extern int __cpu_disable(void);
-extern void __cpu_die(unsigned int cpu);
-#endif
-
-#endif /* !(__ASSEMBLY__) */
-
-#else
-
-#define hard_smp_processor_id() 0
-#define smp_fill_in_sib_core_maps() do { } while (0)
-#define smp_fetch_global_regs() do { } while (0)
-
-#endif /* !(CONFIG_SMP) */
-
-#endif /* !(_SPARC64_SMP_H) */
+++ /dev/null
-/*
- * smpprim.h: SMP locking primitives on the Sparc
- *
- * God knows we won't be actually using this code for some time
- * but I thought I'd write it since I knew how.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef __SPARC_SMPPRIM_H
-#define __SPARC_SMPPRIM_H
-
-/* Test and set the unsigned byte at ADDR to 1. Returns the previous
- * value. On the Sparc we use the ldstub instruction since it is
- * atomic.
- */
-
-static inline __volatile__ char test_and_set(void *addr)
-{
- char state = 0;
-
- __asm__ __volatile__("ldstub [%0], %1 ! test_and_set\n\t"
- "=r" (addr), "=r" (state) :
- "0" (addr), "1" (state) : "memory");
-
- return state;
-}
-
-/* Initialize a spin-lock. */
-static inline __volatile__ smp_initlock(void *spinlock)
-{
- /* Unset the lock. */
- *((unsigned char *) spinlock) = 0;
-
- return;
-}
-
-/* This routine spins until it acquires the lock at ADDR. */
-static inline __volatile__ smp_lock(void *addr)
-{
- while(test_and_set(addr) == 0xff)
- ;
-
- /* We now have the lock */
- return;
-}
-
-/* This routine releases the lock at ADDR. */
-static inline __volatile__ smp_unlock(void *addr)
-{
- *((unsigned char *) addr) = 0;
-}
-
-#endif /* !(__SPARC_SMPPRIM_H) */
+++ /dev/null
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockopt(2) */
-#define SOL_SOCKET 0xffff
-
-#define SO_DEBUG 0x0001
-#define SO_PASSCRED 0x0002
-#define SO_REUSEADDR 0x0004
-#define SO_KEEPALIVE 0x0008
-#define SO_DONTROUTE 0x0010
-#define SO_BROADCAST 0x0020
-#define SO_PEERCRED 0x0040
-#define SO_LINGER 0x0080
-#define SO_OOBINLINE 0x0100
-/* To add :#define SO_REUSEPORT 0x0200 */
-#define SO_BSDCOMPAT 0x0400
-#define SO_RCVLOWAT 0x0800
-#define SO_SNDLOWAT 0x1000
-#define SO_RCVTIMEO 0x2000
-#define SO_SNDTIMEO 0x4000
-#define SO_ACCEPTCONN 0x8000
-
-#define SO_SNDBUF 0x1001
-#define SO_RCVBUF 0x1002
-#define SO_SNDBUFFORCE 0x100a
-#define SO_RCVBUFFORCE 0x100b
-#define SO_ERROR 0x1007
-#define SO_TYPE 0x1008
-
-/* Linux specific, keep the same. */
-#define SO_NO_CHECK 0x000b
-#define SO_PRIORITY 0x000c
-
-#define SO_BINDTODEVICE 0x000d
-
-#define SO_ATTACH_FILTER 0x001a
-#define SO_DETACH_FILTER 0x001b
-
-#define SO_PEERNAME 0x001c
-#define SO_TIMESTAMP 0x001d
-#define SCM_TIMESTAMP SO_TIMESTAMP
-
-#define SO_PEERSEC 0x001e
-#define SO_PASSSEC 0x001f
-#define SO_TIMESTAMPNS 0x0021
-#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
-
-#define SO_MARK 0x0022
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION 0x5001
-#define SO_SECURITY_ENCRYPTION_TRANSPORT 0x5002
-#define SO_SECURITY_ENCRYPTION_NETWORK 0x5004
-
-#endif /* _ASM_SOCKET_H */
+++ /dev/null
-#ifndef _ASM_SPARC_SOCKIOS_H
-#define _ASM_SPARC_SOCKIOS_H
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN 0x8901
-#define SIOCSPGRP 0x8902
-#define FIOGETOWN 0x8903
-#define SIOCGPGRP 0x8904
-#define SIOCATMARK 0x8905
-#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
-#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
-
-#endif /* !(_ASM_SPARC_SOCKIOS_H) */
-
+++ /dev/null
-#ifndef _SPARC64_SPARSEMEM_H
-#define _SPARC64_SPARSEMEM_H
-
-#ifdef __KERNEL__
-
-#define SECTION_SIZE_BITS 30
-#define MAX_PHYSADDR_BITS 42
-#define MAX_PHYSMEM_BITS 42
-
-#endif /* !(__KERNEL__) */
-
-#endif /* !(_SPARC64_SPARSEMEM_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_SPINLOCK_H
-#define ___ASM_SPARC_SPINLOCK_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/spinlock_64.h>
-#else
-#include <asm-sparc/spinlock_32.h>
-#endif
-#endif
+++ /dev/null
-/* spinlock.h: 32-bit Sparc spinlock support.
- *
- * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef __SPARC_SPINLOCK_H
-#define __SPARC_SPINLOCK_H
-
-#include <linux/threads.h> /* For NR_CPUS */
-
-#ifndef __ASSEMBLY__
-
-#include <asm/psr.h>
-
-#define __raw_spin_is_locked(lock) (*((volatile unsigned char *)(lock)) != 0)
-
-#define __raw_spin_unlock_wait(lock) \
- do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
-
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
-{
- __asm__ __volatile__(
- "\n1:\n\t"
- "ldstub [%0], %%g2\n\t"
- "orcc %%g2, 0x0, %%g0\n\t"
- "bne,a 2f\n\t"
- " ldub [%0], %%g2\n\t"
- ".subsection 2\n"
- "2:\n\t"
- "orcc %%g2, 0x0, %%g0\n\t"
- "bne,a 2b\n\t"
- " ldub [%0], %%g2\n\t"
- "b,a 1b\n\t"
- ".previous\n"
- : /* no outputs */
- : "r" (lock)
- : "g2", "memory", "cc");
-}
-
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
-{
- unsigned int result;
- __asm__ __volatile__("ldstub [%1], %0"
- : "=r" (result)
- : "r" (lock)
- : "memory");
- return (result == 0);
-}
-
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
-{
- __asm__ __volatile__("stb %%g0, [%0]" : : "r" (lock) : "memory");
-}
-
-/* Read-write spinlocks, allowing multiple readers
- * but only one writer.
- *
- * NOTE! it is quite common to have readers in interrupts
- * but no interrupt writers. For those circumstances we
- * can "mix" irq-safe locks - any writer needs to get a
- * irq-safe write-lock, but readers can get non-irqsafe
- * read-locks.
- *
- * XXX This might create some problems with my dual spinlock
- * XXX scheme, deadlocks etc. -DaveM
- *
- * Sort of like atomic_t's on Sparc, but even more clever.
- *
- * ------------------------------------
- * | 24-bit counter | wlock | raw_rwlock_t
- * ------------------------------------
- * 31 8 7 0
- *
- * wlock signifies the one writer is in or somebody is updating
- * counter. For a writer, if he successfully acquires the wlock,
- * but counter is non-zero, he has to release the lock and wait,
- * till both counter and wlock are zero.
- *
- * Unfortunately this scheme limits us to ~16,000,000 cpus.
- */
-static inline void __read_lock(raw_rwlock_t *rw)
-{
- register raw_rwlock_t *lp asm("g1");
- lp = rw;
- __asm__ __volatile__(
- "mov %%o7, %%g4\n\t"
- "call ___rw_read_enter\n\t"
- " ldstub [%%g1 + 3], %%g2\n"
- : /* no outputs */
- : "r" (lp)
- : "g2", "g4", "memory", "cc");
-}
-
-#define __raw_read_lock(lock) \
-do { unsigned long flags; \
- local_irq_save(flags); \
- __read_lock(lock); \
- local_irq_restore(flags); \
-} while(0)
-
-static inline void __read_unlock(raw_rwlock_t *rw)
-{
- register raw_rwlock_t *lp asm("g1");
- lp = rw;
- __asm__ __volatile__(
- "mov %%o7, %%g4\n\t"
- "call ___rw_read_exit\n\t"
- " ldstub [%%g1 + 3], %%g2\n"
- : /* no outputs */
- : "r" (lp)
- : "g2", "g4", "memory", "cc");
-}
-
-#define __raw_read_unlock(lock) \
-do { unsigned long flags; \
- local_irq_save(flags); \
- __read_unlock(lock); \
- local_irq_restore(flags); \
-} while(0)
-
-static inline void __raw_write_lock(raw_rwlock_t *rw)
-{
- register raw_rwlock_t *lp asm("g1");
- lp = rw;
- __asm__ __volatile__(
- "mov %%o7, %%g4\n\t"
- "call ___rw_write_enter\n\t"
- " ldstub [%%g1 + 3], %%g2\n"
- : /* no outputs */
- : "r" (lp)
- : "g2", "g4", "memory", "cc");
- *(volatile __u32 *)&lp->lock = ~0U;
-}
-
-static inline int __raw_write_trylock(raw_rwlock_t *rw)
-{
- unsigned int val;
-
- __asm__ __volatile__("ldstub [%1 + 3], %0"
- : "=r" (val)
- : "r" (&rw->lock)
- : "memory");
-
- if (val == 0) {
- val = rw->lock & ~0xff;
- if (val)
- ((volatile u8*)&rw->lock)[3] = 0;
- else
- *(volatile u32*)&rw->lock = ~0U;
- }
-
- return (val == 0);
-}
-
-static inline int __read_trylock(raw_rwlock_t *rw)
-{
- register raw_rwlock_t *lp asm("g1");
- register int res asm("o0");
- lp = rw;
- __asm__ __volatile__(
- "mov %%o7, %%g4\n\t"
- "call ___rw_read_try\n\t"
- " ldstub [%%g1 + 3], %%g2\n"
- : "=r" (res)
- : "r" (lp)
- : "g2", "g4", "memory", "cc");
- return res;
-}
-
-#define __raw_read_trylock(lock) \
-({ unsigned long flags; \
- int res; \
- local_irq_save(flags); \
- res = __read_trylock(lock); \
- local_irq_restore(flags); \
- res; \
-})
-
-#define __raw_write_unlock(rw) do { (rw)->lock = 0; } while(0)
-
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
-
-#define _raw_spin_relax(lock) cpu_relax()
-#define _raw_read_relax(lock) cpu_relax()
-#define _raw_write_relax(lock) cpu_relax()
-
-#define __raw_read_can_lock(rw) (!((rw)->lock & 0xff))
-#define __raw_write_can_lock(rw) (!(rw)->lock)
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* __SPARC_SPINLOCK_H */
+++ /dev/null
-/* spinlock.h: 64-bit Sparc spinlock support.
- *
- * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef __SPARC64_SPINLOCK_H
-#define __SPARC64_SPINLOCK_H
-
-#include <linux/threads.h> /* For NR_CPUS */
-
-#ifndef __ASSEMBLY__
-
-/* To get debugging spinlocks which detect and catch
- * deadlock situations, set CONFIG_DEBUG_SPINLOCK
- * and rebuild your kernel.
- */
-
-/* All of these locking primitives are expected to work properly
- * even in an RMO memory model, which currently is what the kernel
- * runs in.
- *
- * There is another issue. Because we play games to save cycles
- * in the non-contention case, we need to be extra careful about
- * branch targets into the "spinning" code. They live in their
- * own section, but the newer V9 branches have a shorter range
- * than the traditional 32-bit sparc branch variants. The rule
- * is that the branches that go into and out of the spinner sections
- * must be pre-V9 branches.
- */
-
-#define __raw_spin_is_locked(lp) ((lp)->lock != 0)
-
-#define __raw_spin_unlock_wait(lp) \
- do { rmb(); \
- } while((lp)->lock)
-
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
-{
- unsigned long tmp;
-
- __asm__ __volatile__(
-"1: ldstub [%1], %0\n"
-" membar #StoreLoad | #StoreStore\n"
-" brnz,pn %0, 2f\n"
-" nop\n"
-" .subsection 2\n"
-"2: ldub [%1], %0\n"
-" membar #LoadLoad\n"
-" brnz,pt %0, 2b\n"
-" nop\n"
-" ba,a,pt %%xcc, 1b\n"
-" .previous"
- : "=&r" (tmp)
- : "r" (lock)
- : "memory");
-}
-
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
-{
- unsigned long result;
-
- __asm__ __volatile__(
-" ldstub [%1], %0\n"
-" membar #StoreLoad | #StoreStore"
- : "=r" (result)
- : "r" (lock)
- : "memory");
-
- return (result == 0UL);
-}
-
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
-{
- __asm__ __volatile__(
-" membar #StoreStore | #LoadStore\n"
-" stb %%g0, [%0]"
- : /* No outputs */
- : "r" (lock)
- : "memory");
-}
-
-static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
-{
- unsigned long tmp1, tmp2;
-
- __asm__ __volatile__(
-"1: ldstub [%2], %0\n"
-" membar #StoreLoad | #StoreStore\n"
-" brnz,pn %0, 2f\n"
-" nop\n"
-" .subsection 2\n"
-"2: rdpr %%pil, %1\n"
-" wrpr %3, %%pil\n"
-"3: ldub [%2], %0\n"
-" membar #LoadLoad\n"
-" brnz,pt %0, 3b\n"
-" nop\n"
-" ba,pt %%xcc, 1b\n"
-" wrpr %1, %%pil\n"
-" .previous"
- : "=&r" (tmp1), "=&r" (tmp2)
- : "r"(lock), "r"(flags)
- : "memory");
-}
-
-/* Multi-reader locks, these are much saner than the 32-bit Sparc ones... */
-
-static void inline __read_lock(raw_rwlock_t *lock)
-{
- unsigned long tmp1, tmp2;
-
- __asm__ __volatile__ (
-"1: ldsw [%2], %0\n"
-" brlz,pn %0, 2f\n"
-"4: add %0, 1, %1\n"
-" cas [%2], %0, %1\n"
-" cmp %0, %1\n"
-" membar #StoreLoad | #StoreStore\n"
-" bne,pn %%icc, 1b\n"
-" nop\n"
-" .subsection 2\n"
-"2: ldsw [%2], %0\n"
-" membar #LoadLoad\n"
-" brlz,pt %0, 2b\n"
-" nop\n"
-" ba,a,pt %%xcc, 4b\n"
-" .previous"
- : "=&r" (tmp1), "=&r" (tmp2)
- : "r" (lock)
- : "memory");
-}
-
-static int inline __read_trylock(raw_rwlock_t *lock)
-{
- int tmp1, tmp2;
-
- __asm__ __volatile__ (
-"1: ldsw [%2], %0\n"
-" brlz,a,pn %0, 2f\n"
-" mov 0, %0\n"
-" add %0, 1, %1\n"
-" cas [%2], %0, %1\n"
-" cmp %0, %1\n"
-" membar #StoreLoad | #StoreStore\n"
-" bne,pn %%icc, 1b\n"
-" mov 1, %0\n"
-"2:"
- : "=&r" (tmp1), "=&r" (tmp2)
- : "r" (lock)
- : "memory");
-
- return tmp1;
-}
-
-static void inline __read_unlock(raw_rwlock_t *lock)
-{
- unsigned long tmp1, tmp2;
-
- __asm__ __volatile__(
-" membar #StoreLoad | #LoadLoad\n"
-"1: lduw [%2], %0\n"
-" sub %0, 1, %1\n"
-" cas [%2], %0, %1\n"
-" cmp %0, %1\n"
-" bne,pn %%xcc, 1b\n"
-" nop"
- : "=&r" (tmp1), "=&r" (tmp2)
- : "r" (lock)
- : "memory");
-}
-
-static void inline __write_lock(raw_rwlock_t *lock)
-{
- unsigned long mask, tmp1, tmp2;
-
- mask = 0x80000000UL;
-
- __asm__ __volatile__(
-"1: lduw [%2], %0\n"
-" brnz,pn %0, 2f\n"
-"4: or %0, %3, %1\n"
-" cas [%2], %0, %1\n"
-" cmp %0, %1\n"
-" membar #StoreLoad | #StoreStore\n"
-" bne,pn %%icc, 1b\n"
-" nop\n"
-" .subsection 2\n"
-"2: lduw [%2], %0\n"
-" membar #LoadLoad\n"
-" brnz,pt %0, 2b\n"
-" nop\n"
-" ba,a,pt %%xcc, 4b\n"
-" .previous"
- : "=&r" (tmp1), "=&r" (tmp2)
- : "r" (lock), "r" (mask)
- : "memory");
-}
-
-static void inline __write_unlock(raw_rwlock_t *lock)
-{
- __asm__ __volatile__(
-" membar #LoadStore | #StoreStore\n"
-" stw %%g0, [%0]"
- : /* no outputs */
- : "r" (lock)
- : "memory");
-}
-
-static int inline __write_trylock(raw_rwlock_t *lock)
-{
- unsigned long mask, tmp1, tmp2, result;
-
- mask = 0x80000000UL;
-
- __asm__ __volatile__(
-" mov 0, %2\n"
-"1: lduw [%3], %0\n"
-" brnz,pn %0, 2f\n"
-" or %0, %4, %1\n"
-" cas [%3], %0, %1\n"
-" cmp %0, %1\n"
-" membar #StoreLoad | #StoreStore\n"
-" bne,pn %%icc, 1b\n"
-" nop\n"
-" mov 1, %2\n"
-"2:"
- : "=&r" (tmp1), "=&r" (tmp2), "=&r" (result)
- : "r" (lock), "r" (mask)
- : "memory");
-
- return result;
-}
-
-#define __raw_read_lock(p) __read_lock(p)
-#define __raw_read_trylock(p) __read_trylock(p)
-#define __raw_read_unlock(p) __read_unlock(p)
-#define __raw_write_lock(p) __write_lock(p)
-#define __raw_write_unlock(p) __write_unlock(p)
-#define __raw_write_trylock(p) __write_trylock(p)
-
-#define __raw_read_can_lock(rw) (!((rw)->lock & 0x80000000UL))
-#define __raw_write_can_lock(rw) (!(rw)->lock)
-
-#define _raw_spin_relax(lock) cpu_relax()
-#define _raw_read_relax(lock) cpu_relax()
-#define _raw_write_relax(lock) cpu_relax()
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(__SPARC64_SPINLOCK_H) */
+++ /dev/null
-#ifndef __SPARC_SPINLOCK_TYPES_H
-#define __SPARC_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-typedef struct {
- volatile unsigned char lock;
-} raw_spinlock_t;
-
-#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
-
-typedef struct {
- volatile unsigned int lock;
-} raw_rwlock_t;
-
-#define __RAW_RW_LOCK_UNLOCKED { 0 }
-
-#endif
+++ /dev/null
-/* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
- *
- * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
- */
-
-#ifndef _SPARC64_SPITFIRE_H
-#define _SPARC64_SPITFIRE_H
-
-#include <asm/asi.h>
-
-/* The following register addresses are accessible via ASI_DMMU
- * and ASI_IMMU, that is there is a distinct and unique copy of
- * each these registers for each TLB.
- */
-#define TSB_TAG_TARGET 0x0000000000000000 /* All chips */
-#define TLB_SFSR 0x0000000000000018 /* All chips */
-#define TSB_REG 0x0000000000000028 /* All chips */
-#define TLB_TAG_ACCESS 0x0000000000000030 /* All chips */
-#define VIRT_WATCHPOINT 0x0000000000000038 /* All chips */
-#define PHYS_WATCHPOINT 0x0000000000000040 /* All chips */
-#define TSB_EXTENSION_P 0x0000000000000048 /* Ultra-III and later */
-#define TSB_EXTENSION_S 0x0000000000000050 /* Ultra-III and later, D-TLB only */
-#define TSB_EXTENSION_N 0x0000000000000058 /* Ultra-III and later */
-#define TLB_TAG_ACCESS_EXT 0x0000000000000060 /* Ultra-III+ and later */
-
-/* These registers only exist as one entity, and are accessed
- * via ASI_DMMU only.
- */
-#define PRIMARY_CONTEXT 0x0000000000000008
-#define SECONDARY_CONTEXT 0x0000000000000010
-#define DMMU_SFAR 0x0000000000000020
-#define VIRT_WATCHPOINT 0x0000000000000038
-#define PHYS_WATCHPOINT 0x0000000000000040
-
-#define SPITFIRE_HIGHEST_LOCKED_TLBENT (64 - 1)
-#define CHEETAH_HIGHEST_LOCKED_TLBENT (16 - 1)
-
-#define L1DCACHE_SIZE 0x4000
-
-#define SUN4V_CHIP_INVALID 0x00
-#define SUN4V_CHIP_NIAGARA1 0x01
-#define SUN4V_CHIP_NIAGARA2 0x02
-#define SUN4V_CHIP_UNKNOWN 0xff
-
-#ifndef __ASSEMBLY__
-
-enum ultra_tlb_layout {
- spitfire = 0,
- cheetah = 1,
- cheetah_plus = 2,
- hypervisor = 3,
-};
-
-extern enum ultra_tlb_layout tlb_type;
-
-extern int sun4v_chip_type;
-
-extern int cheetah_pcache_forced_on;
-extern void cheetah_enable_pcache(void);
-
-#define sparc64_highest_locked_tlbent() \
- (tlb_type == spitfire ? \
- SPITFIRE_HIGHEST_LOCKED_TLBENT : \
- CHEETAH_HIGHEST_LOCKED_TLBENT)
-
-extern int num_kernel_image_mappings;
-
-/* The data cache is write through, so this just invalidates the
- * specified line.
- */
-static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
-{
- __asm__ __volatile__("stxa %0, [%1] %2\n\t"
- "membar #Sync"
- : /* No outputs */
- : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
-}
-
-/* The instruction cache lines are flushed with this, but note that
- * this does not flush the pipeline. It is possible for a line to
- * get flushed but stale instructions to still be in the pipeline,
- * a flush instruction (to any address) is sufficient to handle
- * this issue after the line is invalidated.
- */
-static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
-{
- __asm__ __volatile__("stxa %0, [%1] %2\n\t"
- "membar #Sync"
- : /* No outputs */
- : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
-}
-
-static inline unsigned long spitfire_get_dtlb_data(int entry)
-{
- unsigned long data;
-
- __asm__ __volatile__("ldxa [%1] %2, %0"
- : "=r" (data)
- : "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS));
-
- /* Clear TTE diag bits. */
- data &= ~0x0003fe0000000000UL;
-
- return data;
-}
-
-static inline unsigned long spitfire_get_dtlb_tag(int entry)
-{
- unsigned long tag;
-
- __asm__ __volatile__("ldxa [%1] %2, %0"
- : "=r" (tag)
- : "r" (entry << 3), "i" (ASI_DTLB_TAG_READ));
- return tag;
-}
-
-static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
-{
- __asm__ __volatile__("stxa %0, [%1] %2\n\t"
- "membar #Sync"
- : /* No outputs */
- : "r" (data), "r" (entry << 3),
- "i" (ASI_DTLB_DATA_ACCESS));
-}
-
-static inline unsigned long spitfire_get_itlb_data(int entry)
-{
- unsigned long data;
-
- __asm__ __volatile__("ldxa [%1] %2, %0"
- : "=r" (data)
- : "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS));
-
- /* Clear TTE diag bits. */
- data &= ~0x0003fe0000000000UL;
-
- return data;
-}
-
-static inline unsigned long spitfire_get_itlb_tag(int entry)
-{
- unsigned long tag;
-
- __asm__ __volatile__("ldxa [%1] %2, %0"
- : "=r" (tag)
- : "r" (entry << 3), "i" (ASI_ITLB_TAG_READ));
- return tag;
-}
-
-static inline void spitfire_put_itlb_data(int entry, unsigned long data)
-{
- __asm__ __volatile__("stxa %0, [%1] %2\n\t"
- "membar #Sync"
- : /* No outputs */
- : "r" (data), "r" (entry << 3),
- "i" (ASI_ITLB_DATA_ACCESS));
-}
-
-static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
-{
- __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
- "membar #Sync"
- : /* No outputs */
- : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
-}
-
-static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
-{
- __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
- "membar #Sync"
- : /* No outputs */
- : "r" (page | 0x20), "i" (ASI_IMMU_DEMAP));
-}
-
-/* Cheetah has "all non-locked" tlb flushes. */
-static inline void cheetah_flush_dtlb_all(void)
-{
- __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
- "membar #Sync"
- : /* No outputs */
- : "r" (0x80), "i" (ASI_DMMU_DEMAP));
-}
-
-static inline void cheetah_flush_itlb_all(void)
-{
- __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
- "membar #Sync"
- : /* No outputs */
- : "r" (0x80), "i" (ASI_IMMU_DEMAP));
-}
-
-/* Cheetah has a 4-tlb layout so direct access is a bit different.
- * The first two TLBs are fully assosciative, hold 16 entries, and are
- * used only for locked and >8K sized translations. One exists for
- * data accesses and one for instruction accesses.
- *
- * The third TLB is for data accesses to 8K non-locked translations, is
- * 2 way assosciative, and holds 512 entries. The fourth TLB is for
- * instruction accesses to 8K non-locked translations, is 2 way
- * assosciative, and holds 128 entries.
- *
- * Cheetah has some bug where bogus data can be returned from
- * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
- * the problem for me. -DaveM
- */
-static inline unsigned long cheetah_get_ldtlb_data(int entry)
-{
- unsigned long data;
-
- __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
- "ldxa [%1] %2, %0"
- : "=r" (data)
- : "r" ((0 << 16) | (entry << 3)),
- "i" (ASI_DTLB_DATA_ACCESS));
-
- return data;
-}
-
-static inline unsigned long cheetah_get_litlb_data(int entry)
-{
- unsigned long data;
-
- __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
- "ldxa [%1] %2, %0"
- : "=r" (data)
- : "r" ((0 << 16) | (entry << 3)),
- "i" (ASI_ITLB_DATA_ACCESS));
-
- return data;
-}
-
-static inline unsigned long cheetah_get_ldtlb_tag(int entry)
-{
- unsigned long tag;
-
- __asm__ __volatile__("ldxa [%1] %2, %0"
- : "=r" (tag)
- : "r" ((0 << 16) | (entry << 3)),
- "i" (ASI_DTLB_TAG_READ));
-
- return tag;
-}
-
-static inline unsigned long cheetah_get_litlb_tag(int entry)
-{
- unsigned long tag;
-
- __asm__ __volatile__("ldxa [%1] %2, %0"
- : "=r" (tag)
- : "r" ((0 << 16) | (entry << 3)),
- "i" (ASI_ITLB_TAG_READ));
-
- return tag;
-}
-
-static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
-{
- __asm__ __volatile__("stxa %0, [%1] %2\n\t"
- "membar #Sync"
- : /* No outputs */
- : "r" (data),
- "r" ((0 << 16) | (entry << 3)),
- "i" (ASI_DTLB_DATA_ACCESS));
-}
-
-static inline void cheetah_put_litlb_data(int entry, unsigned long data)
-{
- __asm__ __volatile__("stxa %0, [%1] %2\n\t"
- "membar #Sync"
- : /* No outputs */
- : "r" (data),
- "r" ((0 << 16) | (entry << 3)),
- "i" (ASI_ITLB_DATA_ACCESS));
-}
-
-static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
-{
- unsigned long data;
-
- __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
- "ldxa [%1] %2, %0"
- : "=r" (data)
- : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS));
-
- return data;
-}
-
-static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
-{
- unsigned long tag;
-
- __asm__ __volatile__("ldxa [%1] %2, %0"
- : "=r" (tag)
- : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ));
- return tag;
-}
-
-static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
-{
- __asm__ __volatile__("stxa %0, [%1] %2\n\t"
- "membar #Sync"
- : /* No outputs */
- : "r" (data),
- "r" ((tlb << 16) | (entry << 3)),
- "i" (ASI_DTLB_DATA_ACCESS));
-}
-
-static inline unsigned long cheetah_get_itlb_data(int entry)
-{
- unsigned long data;
-
- __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
- "ldxa [%1] %2, %0"
- : "=r" (data)
- : "r" ((2 << 16) | (entry << 3)),
- "i" (ASI_ITLB_DATA_ACCESS));
-
- return data;
-}
-
-static inline unsigned long cheetah_get_itlb_tag(int entry)
-{
- unsigned long tag;
-
- __asm__ __volatile__("ldxa [%1] %2, %0"
- : "=r" (tag)
- : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ));
- return tag;
-}
-
-static inline void cheetah_put_itlb_data(int entry, unsigned long data)
-{
- __asm__ __volatile__("stxa %0, [%1] %2\n\t"
- "membar #Sync"
- : /* No outputs */
- : "r" (data), "r" ((2 << 16) | (entry << 3)),
- "i" (ASI_ITLB_DATA_ACCESS));
-}
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(_SPARC64_SPITFIRE_H) */
+++ /dev/null
-#ifndef _SPARC64_SSTATE_H
-#define _SPARC64_SSTATE_H
-
-extern void sstate_booting(void);
-extern void sstate_running(void);
-extern void sstate_halt(void);
-extern void sstate_poweroff(void);
-extern void sstate_panic(void);
-extern void sstate_reboot(void);
-
-extern void sun4v_sstate_init(void);
-
-#endif /* _SPARC64_SSTATE_H */
+++ /dev/null
-#ifndef _SPARC64_STACKTRACE_H
-#define _SPARC64_STACKTRACE_H
-
-extern void stack_trace_flush(void);
-
-#endif /* _SPARC64_STACKTRACE_H */
+++ /dev/null
-/*
- * starfire.h: Group all starfire specific code together.
- *
- * Copyright (C) 2000 Anton Blanchard (anton@samba.org)
- */
-
-#ifndef _SPARC64_STARFIRE_H
-#define _SPARC64_STARFIRE_H
-
-#ifndef __ASSEMBLY__
-
-extern int this_is_starfire;
-
-extern void check_if_starfire(void);
-extern void starfire_cpu_setup(void);
-extern int starfire_hard_smp_processor_id(void);
-extern void starfire_hookup(int);
-extern unsigned int starfire_translate(unsigned long imap, unsigned int upaid);
-
-#endif
-#endif
+++ /dev/null
-#ifndef ___ASM_SPARC_STAT_H
-#define ___ASM_SPARC_STAT_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/stat_64.h>
-#else
-#include <asm-sparc/stat_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _SPARC_STAT_H
-#define _SPARC_STAT_H
-
-#include <linux/types.h>
-
-struct __old_kernel_stat {
- unsigned short st_dev;
- unsigned short st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned long st_size;
- unsigned long st_atime;
- unsigned long st_mtime;
- unsigned long st_ctime;
-};
-
-struct stat {
- unsigned short st_dev;
- unsigned long st_ino;
- unsigned short st_mode;
- short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- long st_size;
- long st_atime;
- unsigned long st_atime_nsec;
- long st_mtime;
- unsigned long st_mtime_nsec;
- long st_ctime;
- unsigned long st_ctime_nsec;
- long st_blksize;
- long st_blocks;
- unsigned long __unused4[2];
-};
-
-#define STAT_HAVE_NSEC 1
-
-struct stat64 {
- unsigned long long st_dev;
-
- unsigned long long st_ino;
-
- unsigned int st_mode;
- unsigned int st_nlink;
-
- unsigned int st_uid;
- unsigned int st_gid;
-
- unsigned long long st_rdev;
-
- unsigned char __pad3[8];
-
- long long st_size;
- unsigned int st_blksize;
-
- unsigned char __pad4[8];
- unsigned int st_blocks;
-
- unsigned int st_atime;
- unsigned int st_atime_nsec;
-
- unsigned int st_mtime;
- unsigned int st_mtime_nsec;
-
- unsigned int st_ctime;
- unsigned int st_ctime_nsec;
-
- unsigned int __unused4;
- unsigned int __unused5;
-};
-
-#endif
+++ /dev/null
-#ifndef _SPARC64_STAT_H
-#define _SPARC64_STAT_H
-
-#include <linux/types.h>
-
-struct stat {
- unsigned st_dev;
- ino_t st_ino;
- mode_t st_mode;
- short st_nlink;
- uid_t st_uid;
- gid_t st_gid;
- unsigned st_rdev;
- off_t st_size;
- time_t st_atime;
- time_t st_mtime;
- time_t st_ctime;
- off_t st_blksize;
- off_t st_blocks;
- unsigned long __unused4[2];
-};
-
-struct stat64 {
- unsigned long st_dev;
- unsigned long st_ino;
- unsigned long st_nlink;
-
- unsigned int st_mode;
- unsigned int st_uid;
- unsigned int st_gid;
- unsigned int __pad0;
-
- unsigned long st_rdev;
- long st_size;
- long st_blksize;
- long st_blocks;
-
- unsigned long st_atime;
- unsigned long st_atime_nsec;
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
- long __unused[3];
-};
-
-#endif
+++ /dev/null
-#ifndef ___ASM_SPARC_STATFS_H
-#define ___ASM_SPARC_STATFS_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/statfs_64.h>
-#else
-#include <asm-sparc/statfs_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _SPARC_STATFS_H
-#define _SPARC_STATFS_H
-
-#include <asm-generic/statfs.h>
-
-#endif
+++ /dev/null
-#ifndef _SPARC64_STATFS_H
-#define _SPARC64_STATFS_H
-
-#ifndef __KERNEL_STRICT_NAMES
-
-#include <linux/types.h>
-
-typedef __kernel_fsid_t fsid_t;
-
-#endif
-
-struct statfs {
- long f_type;
- long f_bsize;
- long f_blocks;
- long f_bfree;
- long f_bavail;
- long f_files;
- long f_ffree;
- __kernel_fsid_t f_fsid;
- long f_namelen;
- long f_frsize;
- long f_spare[5];
-};
-
-struct statfs64 {
- long f_type;
- long f_bsize;
- long f_blocks;
- long f_bfree;
- long f_bavail;
- long f_files;
- long f_ffree;
- __kernel_fsid_t f_fsid;
- long f_namelen;
- long f_frsize;
- long f_spare[5];
-};
-
-struct compat_statfs64 {
- __u32 f_type;
- __u32 f_bsize;
- __u64 f_blocks;
- __u64 f_bfree;
- __u64 f_bavail;
- __u64 f_files;
- __u64 f_ffree;
- __kernel_fsid_t f_fsid;
- __u32 f_namelen;
- __u32 f_frsize;
- __u32 f_spare[5];
-};
-
-#endif
+++ /dev/null
-#ifndef ___ASM_SPARC_STRING_H
-#define ___ASM_SPARC_STRING_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/string_64.h>
-#else
-#include <asm-sparc/string_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * string.h: External definitions for optimized assembly string
- * routines for the Linux Kernel.
- *
- * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-
-#ifndef __SPARC_STRING_H__
-#define __SPARC_STRING_H__
-
-#include <asm/page.h>
-
-/* Really, userland/ksyms should not see any of this stuff. */
-
-#ifdef __KERNEL__
-
-extern void __memmove(void *,const void *,__kernel_size_t);
-extern __kernel_size_t __memcpy(void *,const void *,__kernel_size_t);
-extern __kernel_size_t __memset(void *,int,__kernel_size_t);
-
-#ifndef EXPORT_SYMTAB_STROPS
-
-/* First the mem*() things. */
-#define __HAVE_ARCH_MEMMOVE
-#undef memmove
-#define memmove(_to, _from, _n) \
-({ \
- void *_t = (_to); \
- __memmove(_t, (_from), (_n)); \
- _t; \
-})
-
-#define __HAVE_ARCH_MEMCPY
-
-static inline void *__constant_memcpy(void *to, const void *from, __kernel_size_t n)
-{
- extern void __copy_1page(void *, const void *);
-
- if(n <= 32) {
- __builtin_memcpy(to, from, n);
- } else if (((unsigned int) to & 7) != 0) {
- /* Destination is not aligned on the double-word boundary */
- __memcpy(to, from, n);
- } else {
- switch(n) {
- case PAGE_SIZE:
- __copy_1page(to, from);
- break;
- default:
- __memcpy(to, from, n);
- break;
- }
- }
- return to;
-}
-
-static inline void *__nonconstant_memcpy(void *to, const void *from, __kernel_size_t n)
-{
- __memcpy(to, from, n);
- return to;
-}
-
-#undef memcpy
-#define memcpy(t, f, n) \
-(__builtin_constant_p(n) ? \
- __constant_memcpy((t),(f),(n)) : \
- __nonconstant_memcpy((t),(f),(n)))
-
-#define __HAVE_ARCH_MEMSET
-
-static inline void *__constant_c_and_count_memset(void *s, char c, __kernel_size_t count)
-{
- extern void bzero_1page(void *);
- extern __kernel_size_t __bzero(void *, __kernel_size_t);
-
- if(!c) {
- if(count == PAGE_SIZE)
- bzero_1page(s);
- else
- __bzero(s, count);
- } else {
- __memset(s, c, count);
- }
- return s;
-}
-
-static inline void *__constant_c_memset(void *s, char c, __kernel_size_t count)
-{
- extern __kernel_size_t __bzero(void *, __kernel_size_t);
-
- if(!c)
- __bzero(s, count);
- else
- __memset(s, c, count);
- return s;
-}
-
-static inline void *__nonconstant_memset(void *s, char c, __kernel_size_t count)
-{
- __memset(s, c, count);
- return s;
-}
-
-#undef memset
-#define memset(s, c, count) \
-(__builtin_constant_p(c) ? (__builtin_constant_p(count) ? \
- __constant_c_and_count_memset((s), (c), (count)) : \
- __constant_c_memset((s), (c), (count))) \
- : __nonconstant_memset((s), (c), (count)))
-
-#define __HAVE_ARCH_MEMSCAN
-
-#undef memscan
-#define memscan(__arg0, __char, __arg2) \
-({ \
- extern void *__memscan_zero(void *, size_t); \
- extern void *__memscan_generic(void *, int, size_t); \
- void *__retval, *__addr = (__arg0); \
- size_t __size = (__arg2); \
- \
- if(__builtin_constant_p(__char) && !(__char)) \
- __retval = __memscan_zero(__addr, __size); \
- else \
- __retval = __memscan_generic(__addr, (__char), __size); \
- \
- __retval; \
-})
-
-#define __HAVE_ARCH_MEMCMP
-extern int memcmp(const void *,const void *,__kernel_size_t);
-
-/* Now the str*() stuff... */
-#define __HAVE_ARCH_STRLEN
-extern __kernel_size_t strlen(const char *);
-
-#define __HAVE_ARCH_STRNCMP
-
-extern int __strncmp(const char *, const char *, __kernel_size_t);
-
-static inline int __constant_strncmp(const char *src, const char *dest, __kernel_size_t count)
-{
- register int retval;
- switch(count) {
- case 0: return 0;
- case 1: return (src[0] - dest[0]);
- case 2: retval = (src[0] - dest[0]);
- if(!retval && src[0])
- retval = (src[1] - dest[1]);
- return retval;
- case 3: retval = (src[0] - dest[0]);
- if(!retval && src[0]) {
- retval = (src[1] - dest[1]);
- if(!retval && src[1])
- retval = (src[2] - dest[2]);
- }
- return retval;
- case 4: retval = (src[0] - dest[0]);
- if(!retval && src[0]) {
- retval = (src[1] - dest[1]);
- if(!retval && src[1]) {
- retval = (src[2] - dest[2]);
- if (!retval && src[2])
- retval = (src[3] - dest[3]);
- }
- }
- return retval;
- case 5: retval = (src[0] - dest[0]);
- if(!retval && src[0]) {
- retval = (src[1] - dest[1]);
- if(!retval && src[1]) {
- retval = (src[2] - dest[2]);
- if (!retval && src[2]) {
- retval = (src[3] - dest[3]);
- if (!retval && src[3])
- retval = (src[4] - dest[4]);
- }
- }
- }
- return retval;
- default:
- retval = (src[0] - dest[0]);
- if(!retval && src[0]) {
- retval = (src[1] - dest[1]);
- if(!retval && src[1]) {
- retval = (src[2] - dest[2]);
- if(!retval && src[2])
- retval = __strncmp(src+3,dest+3,count-3);
- }
- }
- return retval;
- }
-}
-
-#undef strncmp
-#define strncmp(__arg0, __arg1, __arg2) \
-(__builtin_constant_p(__arg2) ? \
- __constant_strncmp(__arg0, __arg1, __arg2) : \
- __strncmp(__arg0, __arg1, __arg2))
-
-#endif /* !EXPORT_SYMTAB_STROPS */
-
-#endif /* __KERNEL__ */
-
-#endif /* !(__SPARC_STRING_H__) */
+++ /dev/null
-/*
- * string.h: External definitions for optimized assembly string
- * routines for the Linux Kernel.
- *
- * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1996,1997,1999 Jakub Jelinek (jakub@redhat.com)
- */
-
-#ifndef __SPARC64_STRING_H__
-#define __SPARC64_STRING_H__
-
-/* Really, userland/ksyms should not see any of this stuff. */
-
-#ifdef __KERNEL__
-
-#include <asm/asi.h>
-
-extern void *__memset(void *,int,__kernel_size_t);
-
-#ifndef EXPORT_SYMTAB_STROPS
-
-/* First the mem*() things. */
-#define __HAVE_ARCH_MEMMOVE
-extern void *memmove(void *, const void *, __kernel_size_t);
-
-#define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *, const void *, __kernel_size_t);
-
-#define __HAVE_ARCH_MEMSET
-extern void *__builtin_memset(void *,int,__kernel_size_t);
-
-static inline void *__constant_memset(void *s, int c, __kernel_size_t count)
-{
- extern __kernel_size_t __bzero(void *, __kernel_size_t);
-
- if (!c) {
- __bzero(s, count);
- return s;
- } else
- return __memset(s, c, count);
-}
-
-#undef memset
-#define memset(s, c, count) \
-((__builtin_constant_p(count) && (count) <= 32) ? \
- __builtin_memset((s), (c), (count)) : \
- (__builtin_constant_p(c) ? \
- __constant_memset((s), (c), (count)) : \
- __memset((s), (c), (count))))
-
-#define __HAVE_ARCH_MEMSCAN
-
-#undef memscan
-#define memscan(__arg0, __char, __arg2) \
-({ \
- extern void *__memscan_zero(void *, size_t); \
- extern void *__memscan_generic(void *, int, size_t); \
- void *__retval, *__addr = (__arg0); \
- size_t __size = (__arg2); \
- \
- if(__builtin_constant_p(__char) && !(__char)) \
- __retval = __memscan_zero(__addr, __size); \
- else \
- __retval = __memscan_generic(__addr, (__char), __size); \
- \
- __retval; \
-})
-
-#define __HAVE_ARCH_MEMCMP
-extern int memcmp(const void *,const void *,__kernel_size_t);
-
-/* Now the str*() stuff... */
-#define __HAVE_ARCH_STRLEN
-extern __kernel_size_t strlen(const char *);
-
-#define __HAVE_ARCH_STRNCMP
-extern int strncmp(const char *, const char *, __kernel_size_t);
-
-#endif /* !EXPORT_SYMTAB_STROPS */
-
-#endif /* __KERNEL__ */
-
-#endif /* !(__SPARC64_STRING_H__) */
+++ /dev/null
-/*
- * sun4paddr.h: Various physical addresses on sun4 machines
- *
- * Copyright (C) 1997 Anton Blanchard (anton@progsoc.uts.edu.au)
- * Copyright (C) 1998 Chris Davis (cdavis@cois.on.ca)
- *
- * Now supports more sun4's
- */
-
-#ifndef _SPARC_SUN4PADDR_H
-#define _SPARC_SUN4PADDR_H
-
-#define SUN4_IE_PHYSADDR 0xf5000000
-#define SUN4_UNUSED_PHYSADDR 0
-
-/* these work for me */
-#define SUN4_200_MEMREG_PHYSADDR 0xf4000000
-#define SUN4_200_CLOCK_PHYSADDR 0xf3000000
-#define SUN4_200_BWTWO_PHYSADDR 0xfd000000
-#define SUN4_200_ETH_PHYSADDR 0xf6000000
-#define SUN4_200_SI_PHYSADDR 0xff200000
-
-/* these were here before */
-#define SUN4_300_MEMREG_PHYSADDR 0xf4000000
-#define SUN4_300_CLOCK_PHYSADDR 0xf2000000
-#define SUN4_300_TIMER_PHYSADDR 0xef000000
-#define SUN4_300_ETH_PHYSADDR 0xf9000000
-#define SUN4_300_BWTWO_PHYSADDR 0xfb400000
-#define SUN4_300_DMA_PHYSADDR 0xfa001000
-#define SUN4_300_ESP_PHYSADDR 0xfa000000
-
-/* Are these right? */
-#define SUN4_400_MEMREG_PHYSADDR 0xf4000000
-#define SUN4_400_CLOCK_PHYSADDR 0xf2000000
-#define SUN4_400_TIMER_PHYSADDR 0xef000000
-#define SUN4_400_ETH_PHYSADDR 0xf9000000
-#define SUN4_400_BWTWO_PHYSADDR 0xfb400000
-#define SUN4_400_DMA_PHYSADDR 0xfa001000
-#define SUN4_400_ESP_PHYSADDR 0xfa000000
-
-/*
- these are the actual values set and used in the code. Unused items set
- to SUN_UNUSED_PHYSADDR
- */
-
-extern int sun4_memreg_physaddr; /* memory register (ecc?) */
-extern int sun4_clock_physaddr; /* system clock */
-extern int sun4_timer_physaddr; /* timer, where applicable */
-extern int sun4_eth_physaddr; /* onboard ethernet (ie/le) */
-extern int sun4_si_physaddr; /* sun3 scsi adapter */
-extern int sun4_bwtwo_physaddr; /* onboard bw2 */
-extern int sun4_dma_physaddr; /* scsi dma */
-extern int sun4_esp_physaddr; /* esp scsi */
-extern int sun4_ie_physaddr; /* interrupt enable */
-
-#endif /* !(_SPARC_SUN4PADDR_H) */
+++ /dev/null
-/*
- * sun4prom.h -- interface to sun4 PROM monitor. We don't use most of this,
- * so most of these are just placeholders.
- */
-
-#ifndef _SUN4PROM_H_
-#define _SUN4PROM_H_
-
-/*
- * Although this looks similar to an romvec for a OpenProm machine, it is
- * actually closer to what was used in the Sun2 and Sun3.
- *
- * V2 entries exist only in version 2 PROMs and later, V3 in version 3 and later.
- *
- * Many of the function prototypes are guesses. Some are certainly wrong.
- * Use with care.
- */
-
-typedef struct {
- char *initSP; /* Initial system stack ptr */
- void (*startmon)(void); /* Initial PC for hardware */
- int *diagberr; /* Bus err handler for diags */
- struct linux_arguments_v0 **bootParam; /* Info for bootstrapped pgm */
- unsigned int *memorysize; /* Usable memory in bytes */
- unsigned char (*getchar)(void); /* Get char from input device */
- void (*putchar)(char); /* Put char to output device */
- int (*mayget)(void); /* Maybe get char, or -1 */
- int (*mayput)(int); /* Maybe put char, or -1 */
- unsigned char *echo; /* Should getchar echo? */
- unsigned char *insource; /* Input source selector */
- unsigned char *outsink; /* Output sink selector */
- int (*getkey)(void); /* Get next key if one exists */
- void (*initgetkey)(void); /* Initialize get key */
- unsigned int *translation; /* Kbd translation selector */
- unsigned char *keybid; /* Keyboard ID byte */
- int *screen_x; /* V2: Screen x pos (r/o) */
- int *screen_y; /* V2: Screen y pos (r/o) */
- struct keybuf *keybuf; /* Up/down keycode buffer */
- char *monid; /* Monitor version ID */
- void (*fbwritechar)(char); /* Write a character to FB */
- int *fbAddr; /* Address of frame buffer */
- char **font; /* Font table for FB */
- void (*fbwritestr)(char *); /* Write string to FB */
- void (*reboot)(char *); /* e.g. reboot("sd()vmlinux") */
- unsigned char *linebuf; /* The line input buffer */
- unsigned char **lineptr; /* Cur pointer into linebuf */
- int *linesize; /* length of line in linebuf */
- void (*getline)(char *); /* Get line from user */
- unsigned char (*getnextchar)(void); /* Get next char from linebuf */
- unsigned char (*peeknextchar)(void); /* Peek at next char */
- int *fbthere; /* =1 if frame buffer there */
- int (*getnum)(void); /* Grab hex num from line */
- int (*printf)(char *, ...); /* See prom_printf() instead */
- void (*printhex)(int); /* Format N digits in hex */
- unsigned char *leds; /* RAM copy of LED register */
- void (*setLEDs)(unsigned char *); /* Sets LED's and RAM copy */
- void (*NMIaddr)(void *); /* Addr for level 7 vector */
- void (*abortentry)(void); /* Entry for keyboard abort */
- int *nmiclock; /* Counts up in msec */
- int *FBtype; /* Frame buffer type */
- unsigned int romvecversion; /* Version number for this romvec */
- struct globram *globram; /* monitor global variables ??? */
- void * kbdaddr; /* Addr of keyboard in use */
- int *keyrinit; /* ms before kbd repeat */
- unsigned char *keyrtick; /* ms between repetitions */
- unsigned int *memoryavail; /* V1: Main mem usable size */
- long *resetaddr; /* where to jump on a reset */
- long *resetmap; /* pgmap entry for resetaddr */
- void (*exittomon)(void); /* Exit from user program */
- unsigned char **memorybitmap; /* V1: &{0 or &bits} */
- void (*setcxsegmap)(int ctxt, char *va, int pmeg); /* Set seg in any context */
- void (**vector_cmd)(void *); /* V2: Handler for 'v' cmd */
- unsigned long *expectedtrapsig; /* V3: Location of the expected trap signal */
- unsigned long *trapvectorbasetable; /* V3: Address of the trap vector table */
- int unused1;
- int unused2;
- int unused3;
- int unused4;
-} linux_sun4_romvec;
-
-extern linux_sun4_romvec *sun4_romvec;
-
-#endif /* _SUN4PROM_H_ */
+++ /dev/null
-/*
- * include/asm-sparc/sunbpp.h
- */
-
-#ifndef _ASM_SPARC_SUNBPP_H
-#define _ASM_SPARC_SUNBPP_H
-
-struct bpp_regs {
- /* DMA registers */
- __volatile__ __u32 p_csr; /* DMA Control/Status Register */
- __volatile__ __u32 p_addr; /* Address Register */
- __volatile__ __u32 p_bcnt; /* Byte Count Register */
- __volatile__ __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */
- /* Parallel Port registers */
- __volatile__ __u16 p_hcr; /* Hardware Configuration Register */
- __volatile__ __u16 p_ocr; /* Operation Configuration Register */
- __volatile__ __u8 p_dr; /* Parallel Data Register */
- __volatile__ __u8 p_tcr; /* Transfer Control Register */
- __volatile__ __u8 p_or; /* Output Register */
- __volatile__ __u8 p_ir; /* Input Register */
- __volatile__ __u16 p_icr; /* Interrupt Control Register */
-};
-
-/* P_HCR. Time is in increments of SBus clock. */
-#define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
-#define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
-#define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
-
-/* P_OCR. */
-#define P_OCR_MEM_CLR 0x8000
-#define P_OCR_DATA_SRC 0x4000 /* ) */
-#define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
-#define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
-#define P_OCR_ACK_DSEL 0x0800 /* ) */
-#define P_OCR_EN_DIAG 0x0400
-#define P_OCR_BUSY_OP 0x0200 /* Busy operation */
-#define P_OCR_ACK_OP 0x0100 /* Ack operation */
-#define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
-#define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
-#define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
-#define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
-
-/* P_TCR */
-#define P_TCR_DIR 0x08
-#define P_TCR_BUSY 0x04
-#define P_TCR_ACK 0x02
-#define P_TCR_DS 0x01 /* Strobe */
-
-/* P_OR */
-#define P_OR_V3 0x20 /* ) */
-#define P_OR_V2 0x10 /* ) on Zebra only */
-#define P_OR_V1 0x08 /* ) */
-#define P_OR_INIT 0x04
-#define P_OR_AFXN 0x02 /* Auto Feed */
-#define P_OR_SLCT_IN 0x01
-
-/* P_IR */
-#define P_IR_PE 0x04
-#define P_IR_SLCT 0x02
-#define P_IR_ERR 0x01
-
-/* P_ICR */
-#define P_DS_IRQ 0x8000 /* RW1 */
-#define P_ACK_IRQ 0x4000 /* RW1 */
-#define P_BUSY_IRQ 0x2000 /* RW1 */
-#define P_PE_IRQ 0x1000 /* RW1 */
-#define P_SLCT_IRQ 0x0800 /* RW1 */
-#define P_ERR_IRQ 0x0400 /* RW1 */
-#define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
-#define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
-#define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
-#define P_BUSY_IRQ_EN 0x0040 /* RW */
-#define P_PE_IRP 0x0020 /* RW 1= rising edge */
-#define P_PE_IRQ_EN 0x0010 /* RW */
-#define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
-#define P_SLCT_IRQ_EN 0x0004 /* RW */
-#define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
-#define P_ERR_IRQ_EN 0x0001 /* RW */
-
-#endif /* !(_ASM_SPARC_SUNBPP_H) */
+++ /dev/null
-/* swift.h: Specific definitions for the _broken_ Swift SRMMU
- * MMU module.
- *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_SWIFT_H
-#define _SPARC_SWIFT_H
-
-/* Swift is so brain damaged, here is the mmu control register. */
-#define SWIFT_ST 0x00800000 /* SW tablewalk enable */
-#define SWIFT_WP 0x00400000 /* Watchpoint enable */
-
-/* Branch folding (buggy, disable on production systems!) */
-#define SWIFT_BF 0x00200000
-#define SWIFT_PMC 0x00180000 /* Page mode control */
-#define SWIFT_PE 0x00040000 /* Parity enable */
-#define SWIFT_PC 0x00020000 /* Parity control */
-#define SWIFT_AP 0x00010000 /* Graphics page mode control (TCX/SX) */
-#define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
-#define SWIFT_BM 0x00004000 /* Boot mode */
-#define SWIFT_RC 0x00003c00 /* DRAM refresh control */
-#define SWIFT_IE 0x00000200 /* Instruction cache enable */
-#define SWIFT_DE 0x00000100 /* Data cache enable */
-#define SWIFT_SA 0x00000080 /* Store Allocate */
-#define SWIFT_NF 0x00000002 /* No fault mode */
-#define SWIFT_EN 0x00000001 /* MMU enable */
-
-/* Bits [13:5] select one of 512 instruction cache tags */
-static inline void swift_inv_insn_tag(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_TXTC_TAG)
- : "memory");
-}
-
-/* Bits [12:4] select one of 512 data cache tags */
-static inline void swift_inv_data_tag(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_DATAC_TAG)
- : "memory");
-}
-
-static inline void swift_flush_dcache(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x2000; addr += 0x10)
- swift_inv_data_tag(addr);
-}
-
-static inline void swift_flush_icache(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x4000; addr += 0x20)
- swift_inv_insn_tag(addr);
-}
-
-static inline void swift_idflash_clear(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x2000; addr += 0x10) {
- swift_inv_insn_tag(addr<<1);
- swift_inv_data_tag(addr);
- }
-}
-
-/* Swift is so broken, it isn't even safe to use the following. */
-static inline void swift_flush_page(unsigned long page)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (page), "i" (ASI_M_FLUSH_PAGE)
- : "memory");
-}
-
-static inline void swift_flush_segment(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_FLUSH_SEG)
- : "memory");
-}
-
-static inline void swift_flush_region(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_FLUSH_REGION)
- : "memory");
-}
-
-static inline void swift_flush_context(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_FLUSH_CTX)
- : "memory");
-}
-
-#endif /* !(_SPARC_SWIFT_H) */
+++ /dev/null
-#ifndef _SPARC64_SYSCALLS_H
-#define _SPARC64_SYSCALLS_H
-
-struct pt_regs;
-
-extern asmlinkage long sparc_do_fork(unsigned long clone_flags,
- unsigned long stack_start,
- struct pt_regs *regs,
- unsigned long stack_size);
-
-extern asmlinkage int sparc_execve(struct pt_regs *regs);
-
-#endif /* _SPARC64_SYSCALLS_H */
+++ /dev/null
-/*
- * sysen.h: Bit fields within the "System Enable" register accessed via
- * the ASI_CONTROL address space at address AC_SYSENABLE.
- *
- * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_SYSEN_H
-#define _SPARC_SYSEN_H
-
-#define SENABLE_DVMA 0x20 /* enable dvma transfers */
-#define SENABLE_CACHE 0x10 /* enable VAC cache */
-#define SENABLE_RESET 0x04 /* reset whole machine, danger Will Robinson */
-
-#endif /* _SPARC_SYSEN_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_SYSTEM_H
-#define ___ASM_SPARC_SYSTEM_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/system_64.h>
-#else
-#include <asm-sparc/system_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef __SPARC_SYSTEM_H
-#define __SPARC_SYSTEM_H
-
-#include <linux/kernel.h>
-#include <linux/threads.h> /* NR_CPUS */
-#include <linux/thread_info.h>
-
-#include <asm/page.h>
-#include <asm/psr.h>
-#include <asm/ptrace.h>
-#include <asm/btfixup.h>
-#include <asm/smp.h>
-
-#ifndef __ASSEMBLY__
-
-#include <linux/irqflags.h>
-
-/*
- * Sparc (general) CPU types
- */
-enum sparc_cpu {
- sun4 = 0x00,
- sun4c = 0x01,
- sun4m = 0x02,
- sun4d = 0x03,
- sun4e = 0x04,
- sun4u = 0x05, /* V8 ploos ploos */
- sun_unknown = 0x06,
- ap1000 = 0x07, /* almost a sun4m */
-};
-
-/* Really, userland should not be looking at any of this... */
-#ifdef __KERNEL__
-
-extern enum sparc_cpu sparc_cpu_model;
-
-#ifndef CONFIG_SUN4
-#define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
-#define ARCH_SUN4 0
-#else
-#define ARCH_SUN4C_SUN4 1
-#define ARCH_SUN4 1
-#endif
-
-#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
-
-extern char reboot_command[];
-
-extern struct thread_info *current_set[NR_CPUS];
-
-extern unsigned long empty_bad_page;
-extern unsigned long empty_bad_page_table;
-extern unsigned long empty_zero_page;
-
-extern void sun_do_break(void);
-extern int serial_console;
-extern int stop_a_enabled;
-
-static inline int con_is_present(void)
-{
- return serial_console ? 0 : 1;
-}
-
-/* When a context switch happens we must flush all user windows so that
- * the windows of the current process are flushed onto its stack. This
- * way the windows are all clean for the next process and the stack
- * frames are up to date.
- */
-extern void flush_user_windows(void);
-extern void kill_user_windows(void);
-extern void synchronize_user_stack(void);
-extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
- void *fpqueue, unsigned long *fpqdepth);
-
-#ifdef CONFIG_SMP
-#define SWITCH_ENTER(prv) \
- do { \
- if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
- put_psr(get_psr() | PSR_EF); \
- fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
- &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
- clear_tsk_thread_flag(prv, TIF_USEDFPU); \
- (prv)->thread.kregs->psr &= ~PSR_EF; \
- } \
- } while(0)
-
-#define SWITCH_DO_LAZY_FPU(next) /* */
-#else
-#define SWITCH_ENTER(prv) /* */
-#define SWITCH_DO_LAZY_FPU(nxt) \
- do { \
- if (last_task_used_math != (nxt)) \
- (nxt)->thread.kregs->psr&=~PSR_EF; \
- } while(0)
-#endif
-
-extern void flushw_all(void);
-
-/*
- * Flush windows so that the VM switch which follows
- * would not pull the stack from under us.
- *
- * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
- * XXX WTF is the above comment? Found in late teen 2.4.x.
- */
-#define prepare_arch_switch(next) do { \
- __asm__ __volatile__( \
- ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
- "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
- "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
- "save %sp, -0x40, %sp\n\t" \
- "restore; restore; restore; restore; restore; restore; restore"); \
-} while(0)
-
- /* Much care has gone into this code, do not touch it.
- *
- * We need to loadup regs l0/l1 for the newly forked child
- * case because the trap return path relies on those registers
- * holding certain values, gcc is told that they are clobbered.
- * Gcc needs registers for 3 values in and 1 value out, so we
- * clobber every non-fixed-usage register besides l2/l3/o4/o5. -DaveM
- *
- * Hey Dave, that do not touch sign is too much of an incentive
- * - Anton & Pete
- */
-#define switch_to(prev, next, last) do { \
- SWITCH_ENTER(prev); \
- SWITCH_DO_LAZY_FPU(next); \
- cpu_set(smp_processor_id(), next->active_mm->cpu_vm_mask); \
- __asm__ __volatile__( \
- "sethi %%hi(here - 0x8), %%o7\n\t" \
- "mov %%g6, %%g3\n\t" \
- "or %%o7, %%lo(here - 0x8), %%o7\n\t" \
- "rd %%psr, %%g4\n\t" \
- "std %%sp, [%%g6 + %4]\n\t" \
- "rd %%wim, %%g5\n\t" \
- "wr %%g4, 0x20, %%psr\n\t" \
- "nop\n\t" \
- "std %%g4, [%%g6 + %3]\n\t" \
- "ldd [%2 + %3], %%g4\n\t" \
- "mov %2, %%g6\n\t" \
- ".globl patchme_store_new_current\n" \
-"patchme_store_new_current:\n\t" \
- "st %2, [%1]\n\t" \
- "wr %%g4, 0x20, %%psr\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- "nop\n\t" /* LEON needs all 3 nops: load to %sp depends on CWP. */ \
- "ldd [%%g6 + %4], %%sp\n\t" \
- "wr %%g5, 0x0, %%wim\n\t" \
- "ldd [%%sp + 0x00], %%l0\n\t" \
- "ldd [%%sp + 0x38], %%i6\n\t" \
- "wr %%g4, 0x0, %%psr\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- "jmpl %%o7 + 0x8, %%g0\n\t" \
- " ld [%%g3 + %5], %0\n\t" \
- "here:\n" \
- : "=&r" (last) \
- : "r" (&(current_set[hard_smp_processor_id()])), \
- "r" (task_thread_info(next)), \
- "i" (TI_KPSR), \
- "i" (TI_KSP), \
- "i" (TI_TASK) \
- : "g1", "g2", "g3", "g4", "g5", "g7", \
- "l0", "l1", "l3", "l4", "l5", "l6", "l7", \
- "i0", "i1", "i2", "i3", "i4", "i5", \
- "o0", "o1", "o2", "o3", "o7"); \
- } while(0)
-
-/* XXX Change this if we ever use a PSO mode kernel. */
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-#define rmb() mb()
-#define wmb() mb()
-#define read_barrier_depends() do { } while(0)
-#define set_mb(__var, __value) do { __var = __value; mb(); } while(0)
-#define smp_mb() __asm__ __volatile__("":::"memory")
-#define smp_rmb() __asm__ __volatile__("":::"memory")
-#define smp_wmb() __asm__ __volatile__("":::"memory")
-#define smp_read_barrier_depends() do { } while(0)
-
-#define nop() __asm__ __volatile__ ("nop")
-
-/* This has special calling conventions */
-#ifndef CONFIG_SMP
-BTFIXUPDEF_CALL(void, ___xchg32, void)
-#endif
-
-static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
-{
-#ifdef CONFIG_SMP
- __asm__ __volatile__("swap [%2], %0"
- : "=&r" (val)
- : "0" (val), "r" (m)
- : "memory");
- return val;
-#else
- register unsigned long *ptr asm("g1");
- register unsigned long ret asm("g2");
-
- ptr = (unsigned long *) m;
- ret = val;
-
- /* Note: this is magic and the nop there is
- really needed. */
- __asm__ __volatile__(
- "mov %%o7, %%g4\n\t"
- "call ___f____xchg32\n\t"
- " nop\n\t"
- : "=&r" (ret)
- : "0" (ret), "r" (ptr)
- : "g3", "g4", "g7", "memory", "cc");
-
- return ret;
-#endif
-}
-
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-
-extern void __xchg_called_with_bad_pointer(void);
-
-static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int size)
-{
- switch (size) {
- case 4:
- return xchg_u32(ptr, x);
- };
- __xchg_called_with_bad_pointer();
- return x;
-}
-
-/* Emulate cmpxchg() the same way we emulate atomics,
- * by hashing the object address and indexing into an array
- * of spinlocks to get a bit of performance...
- *
- * See arch/sparc/lib/atomic32.c for implementation.
- *
- * Cribbed from <asm-parisc/atomic.h>
- */
-#define __HAVE_ARCH_CMPXCHG 1
-
-/* bug catcher for when unsupported size is used - won't link */
-extern void __cmpxchg_called_with_bad_pointer(void);
-/* we only need to support cmpxchg of a u32 on sparc */
-extern unsigned long __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_);
-
-/* don't worry...optimizer will get rid of most of this */
-static inline unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
-{
- switch (size) {
- case 4:
- return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_);
- default:
- __cmpxchg_called_with_bad_pointer();
- break;
- }
- return old;
-}
-
-#define cmpxchg(ptr, o, n) \
-({ \
- __typeof__(*(ptr)) _o_ = (o); \
- __typeof__(*(ptr)) _n_ = (n); \
- (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
- (unsigned long)_n_, sizeof(*(ptr))); \
-})
-
-#include <asm-generic/cmpxchg-local.h>
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
- (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASSEMBLY__ */
-
-#define arch_align_stack(x) (x)
-
-#endif /* !(__SPARC_SYSTEM_H) */
+++ /dev/null
-#ifndef __SPARC64_SYSTEM_H
-#define __SPARC64_SYSTEM_H
-
-#include <asm/ptrace.h>
-#include <asm/processor.h>
-#include <asm/visasm.h>
-
-#ifndef __ASSEMBLY__
-
-#include <linux/irqflags.h>
-#include <asm-generic/cmpxchg-local.h>
-
-/*
- * Sparc (general) CPU types
- */
-enum sparc_cpu {
- sun4 = 0x00,
- sun4c = 0x01,
- sun4m = 0x02,
- sun4d = 0x03,
- sun4e = 0x04,
- sun4u = 0x05, /* V8 ploos ploos */
- sun_unknown = 0x06,
- ap1000 = 0x07, /* almost a sun4m */
-};
-
-#define sparc_cpu_model sun4u
-
-/* This cannot ever be a sun4c nor sun4 :) That's just history. */
-#define ARCH_SUN4C_SUN4 0
-#define ARCH_SUN4 0
-
-extern char reboot_command[];
-
-/* These are here in an effort to more fully work around Spitfire Errata
- * #51. Essentially, if a memory barrier occurs soon after a mispredicted
- * branch, the chip can stop executing instructions until a trap occurs.
- * Therefore, if interrupts are disabled, the chip can hang forever.
- *
- * It used to be believed that the memory barrier had to be right in the
- * delay slot, but a case has been traced recently wherein the memory barrier
- * was one instruction after the branch delay slot and the chip still hung.
- * The offending sequence was the following in sym_wakeup_done() of the
- * sym53c8xx_2 driver:
- *
- * call sym_ccb_from_dsa, 0
- * movge %icc, 0, %l0
- * brz,pn %o0, .LL1303
- * mov %o0, %l2
- * membar #LoadLoad
- *
- * The branch has to be mispredicted for the bug to occur. Therefore, we put
- * the memory barrier explicitly into a "branch always, predicted taken"
- * delay slot to avoid the problem case.
- */
-#define membar_safe(type) \
-do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
- " membar " type "\n" \
- "1:\n" \
- : : : "memory"); \
-} while (0)
-
-#define mb() \
- membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
-#define rmb() \
- membar_safe("#LoadLoad")
-#define wmb() \
- membar_safe("#StoreStore")
-#define membar_storeload() \
- membar_safe("#StoreLoad")
-#define membar_storeload_storestore() \
- membar_safe("#StoreLoad | #StoreStore")
-#define membar_storeload_loadload() \
- membar_safe("#StoreLoad | #LoadLoad")
-#define membar_storestore_loadstore() \
- membar_safe("#StoreStore | #LoadStore")
-
-#endif
-
-#define nop() __asm__ __volatile__ ("nop")
-
-#define read_barrier_depends() do { } while(0)
-#define set_mb(__var, __value) \
- do { __var = __value; membar_storeload_storestore(); } while(0)
-
-#ifdef CONFIG_SMP
-#define smp_mb() mb()
-#define smp_rmb() rmb()
-#define smp_wmb() wmb()
-#define smp_read_barrier_depends() read_barrier_depends()
-#else
-#define smp_mb() __asm__ __volatile__("":::"memory")
-#define smp_rmb() __asm__ __volatile__("":::"memory")
-#define smp_wmb() __asm__ __volatile__("":::"memory")
-#define smp_read_barrier_depends() do { } while(0)
-#endif
-
-#define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
-
-#define flushw_all() __asm__ __volatile__("flushw")
-
-/* Performance counter register access. */
-#define read_pcr(__p) __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
-#define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
-#define read_pic(__p) __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
-
-/* Blackbird errata workaround. See commentary in
- * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
- * for more information.
- */
-#define reset_pic() \
- __asm__ __volatile__("ba,pt %xcc, 99f\n\t" \
- ".align 64\n" \
- "99:wr %g0, 0x0, %pic\n\t" \
- "rd %pic, %g0")
-
-#ifndef __ASSEMBLY__
-
-extern void sun_do_break(void);
-extern int stop_a_enabled;
-
-extern void fault_in_user_windows(void);
-extern void synchronize_user_stack(void);
-
-extern void __flushw_user(void);
-#define flushw_user() __flushw_user()
-
-#define flush_user_windows flushw_user
-#define flush_register_windows flushw_all
-
-/* Don't hold the runqueue lock over context switch */
-#define __ARCH_WANT_UNLOCKED_CTXSW
-#define prepare_arch_switch(next) \
-do { \
- flushw_all(); \
-} while (0)
-
- /* See what happens when you design the chip correctly?
- *
- * We tell gcc we clobber all non-fixed-usage registers except
- * for l0/l1. It will use one for 'next' and the other to hold
- * the output value of 'last'. 'next' is not referenced again
- * past the invocation of switch_to in the scheduler, so we need
- * not preserve it's value. Hairy, but it lets us remove 2 loads
- * and 2 stores in this critical code path. -DaveM
- */
-#define switch_to(prev, next, last) \
-do { if (test_thread_flag(TIF_PERFCTR)) { \
- unsigned long __tmp; \
- read_pcr(__tmp); \
- current_thread_info()->pcr_reg = __tmp; \
- read_pic(__tmp); \
- current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
- current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
- } \
- flush_tlb_pending(); \
- save_and_clear_fpu(); \
- /* If you are tempted to conditionalize the following */ \
- /* so that ASI is only written if it changes, think again. */ \
- __asm__ __volatile__("wr %%g0, %0, %%asi" \
- : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
- trap_block[current_thread_info()->cpu].thread = \
- task_thread_info(next); \
- __asm__ __volatile__( \
- "mov %%g4, %%g7\n\t" \
- "stx %%i6, [%%sp + 2047 + 0x70]\n\t" \
- "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \
- "rdpr %%wstate, %%o5\n\t" \
- "stx %%o6, [%%g6 + %6]\n\t" \
- "stb %%o5, [%%g6 + %5]\n\t" \
- "rdpr %%cwp, %%o5\n\t" \
- "stb %%o5, [%%g6 + %8]\n\t" \
- "mov %4, %%g6\n\t" \
- "ldub [%4 + %8], %%g1\n\t" \
- "wrpr %%g1, %%cwp\n\t" \
- "ldx [%%g6 + %6], %%o6\n\t" \
- "ldub [%%g6 + %5], %%o5\n\t" \
- "ldub [%%g6 + %7], %%o7\n\t" \
- "wrpr %%o5, 0x0, %%wstate\n\t" \
- "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \
- "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \
- "ldx [%%g6 + %9], %%g4\n\t" \
- "brz,pt %%o7, switch_to_pc\n\t" \
- " mov %%g7, %0\n\t" \
- "sethi %%hi(ret_from_syscall), %%g1\n\t" \
- "jmpl %%g1 + %%lo(ret_from_syscall), %%g0\n\t" \
- " nop\n\t" \
- ".globl switch_to_pc\n\t" \
- "switch_to_pc:\n\t" \
- : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \
- "=r" (__local_per_cpu_offset) \
- : "0" (task_thread_info(next)), \
- "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \
- "i" (TI_CWP), "i" (TI_TASK) \
- : "cc", \
- "g1", "g2", "g3", "g7", \
- "l1", "l2", "l3", "l4", "l5", "l6", "l7", \
- "i0", "i1", "i2", "i3", "i4", "i5", \
- "o0", "o1", "o2", "o3", "o4", "o5", "o7"); \
- /* If you fuck with this, update ret_from_syscall code too. */ \
- if (test_thread_flag(TIF_PERFCTR)) { \
- write_pcr(current_thread_info()->pcr_reg); \
- reset_pic(); \
- } \
-} while(0)
-
-static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
-{
- unsigned long tmp1, tmp2;
-
- __asm__ __volatile__(
-" membar #StoreLoad | #LoadLoad\n"
-" mov %0, %1\n"
-"1: lduw [%4], %2\n"
-" cas [%4], %2, %0\n"
-" cmp %2, %0\n"
-" bne,a,pn %%icc, 1b\n"
-" mov %1, %0\n"
-" membar #StoreLoad | #StoreStore\n"
- : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
- : "0" (val), "r" (m)
- : "cc", "memory");
- return val;
-}
-
-static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
-{
- unsigned long tmp1, tmp2;
-
- __asm__ __volatile__(
-" membar #StoreLoad | #LoadLoad\n"
-" mov %0, %1\n"
-"1: ldx [%4], %2\n"
-" casx [%4], %2, %0\n"
-" cmp %2, %0\n"
-" bne,a,pn %%xcc, 1b\n"
-" mov %1, %0\n"
-" membar #StoreLoad | #StoreStore\n"
- : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
- : "0" (val), "r" (m)
- : "cc", "memory");
- return val;
-}
-
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-
-extern void __xchg_called_with_bad_pointer(void);
-
-static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
- int size)
-{
- switch (size) {
- case 4:
- return xchg32(ptr, x);
- case 8:
- return xchg64(ptr, x);
- };
- __xchg_called_with_bad_pointer();
- return x;
-}
-
-extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
-
-/*
- * Atomic compare and exchange. Compare OLD with MEM, if identical,
- * store NEW in MEM. Return the initial value in MEM. Success is
- * indicated by comparing RETURN with OLD.
- */
-
-#define __HAVE_ARCH_CMPXCHG 1
-
-static inline unsigned long
-__cmpxchg_u32(volatile int *m, int old, int new)
-{
- __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
- "cas [%2], %3, %0\n\t"
- "membar #StoreLoad | #StoreStore"
- : "=&r" (new)
- : "0" (new), "r" (m), "r" (old)
- : "memory");
-
- return new;
-}
-
-static inline unsigned long
-__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
-{
- __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
- "casx [%2], %3, %0\n\t"
- "membar #StoreLoad | #StoreStore"
- : "=&r" (new)
- : "0" (new), "r" (m), "r" (old)
- : "memory");
-
- return new;
-}
-
-/* This function doesn't exist, so you'll get a linker error
- if something tries to do an invalid cmpxchg(). */
-extern void __cmpxchg_called_with_bad_pointer(void);
-
-static inline unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
-{
- switch (size) {
- case 4:
- return __cmpxchg_u32(ptr, old, new);
- case 8:
- return __cmpxchg_u64(ptr, old, new);
- }
- __cmpxchg_called_with_bad_pointer();
- return old;
-}
-
-#define cmpxchg(ptr,o,n) \
- ({ \
- __typeof__(*(ptr)) _o_ = (o); \
- __typeof__(*(ptr)) _n_ = (n); \
- (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
- (unsigned long)_n_, sizeof(*(ptr))); \
- })
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-
-static inline unsigned long __cmpxchg_local(volatile void *ptr,
- unsigned long old,
- unsigned long new, int size)
-{
- switch (size) {
- case 4:
- case 8: return __cmpxchg(ptr, old, new, size);
- default:
- return __cmpxchg_local_generic(ptr, old, new, size);
- }
-
- return old;
-}
-
-#define cmpxchg_local(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
- (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) \
- ({ \
- BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
- cmpxchg_local((ptr), (o), (n)); \
- })
-
-#endif /* !(__ASSEMBLY__) */
-
-#define arch_align_stack(x) (x)
-
-#endif /* !(__SPARC64_SYSTEM_H) */
+++ /dev/null
-#ifndef _SPARC_TERMBITS_H
-#define _SPARC_TERMBITS_H
-
-#include <linux/posix_types.h>
-
-typedef unsigned char cc_t;
-typedef unsigned int speed_t;
-
-#if defined(__sparc__) && defined(__arch64__)
-typedef unsigned int tcflag_t;
-#else
-typedef unsigned long tcflag_t;
-#endif
-
-#define NCC 8
-struct termio {
- unsigned short c_iflag; /* input mode flags */
- unsigned short c_oflag; /* output mode flags */
- unsigned short c_cflag; /* control mode flags */
- unsigned short c_lflag; /* local mode flags */
- unsigned char c_line; /* line discipline */
- unsigned char c_cc[NCC]; /* control characters */
-};
-
-#define NCCS 17
-struct termios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
-#ifdef __KERNEL__
-#define SIZEOF_USER_TERMIOS sizeof (struct termios) - (2*sizeof (cc_t))
- cc_t _x_cc[2]; /* We need them to hold vmin/vtime */
-#endif
-};
-
-struct termios2 {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- cc_t _x_cc[2]; /* padding to match ktermios */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-struct ktermios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- cc_t _x_cc[2]; /* We need them to hold vmin/vtime */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VEOL 5
-#define VEOL2 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-
-
-
-#define VSUSP 10
-#define VDSUSP 11 /* SunOS POSIX nicety I do believe... */
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-
-/* Kernel keeps vmin/vtime separated, user apps assume vmin/vtime is
- * shared with eof/eol
- */
-#ifdef __KERNEL__
-#define VMIN 16
-#define VTIME 17
-#else
-#define VMIN VEOF
-#define VTIME VEOL
-#endif
-
-/* c_iflag bits */
-#define IGNBRK 0x00000001
-#define BRKINT 0x00000002
-#define IGNPAR 0x00000004
-#define PARMRK 0x00000008
-#define INPCK 0x00000010
-#define ISTRIP 0x00000020
-#define INLCR 0x00000040
-#define IGNCR 0x00000080
-#define ICRNL 0x00000100
-#define IUCLC 0x00000200
-#define IXON 0x00000400
-#define IXANY 0x00000800
-#define IXOFF 0x00001000
-#define IMAXBEL 0x00002000
-#define IUTF8 0x00004000
-
-/* c_oflag bits */
-#define OPOST 0x00000001
-#define OLCUC 0x00000002
-#define ONLCR 0x00000004
-#define OCRNL 0x00000008
-#define ONOCR 0x00000010
-#define ONLRET 0x00000020
-#define OFILL 0x00000040
-#define OFDEL 0x00000080
-#define NLDLY 0x00000100
-#define NL0 0x00000000
-#define NL1 0x00000100
-#define CRDLY 0x00000600
-#define CR0 0x00000000
-#define CR1 0x00000200
-#define CR2 0x00000400
-#define CR3 0x00000600
-#define TABDLY 0x00001800
-#define TAB0 0x00000000
-#define TAB1 0x00000800
-#define TAB2 0x00001000
-#define TAB3 0x00001800
-#define XTABS 0x00001800
-#define BSDLY 0x00002000
-#define BS0 0x00000000
-#define BS1 0x00002000
-#define VTDLY 0x00004000
-#define VT0 0x00000000
-#define VT1 0x00004000
-#define FFDLY 0x00008000
-#define FF0 0x00000000
-#define FF1 0x00008000
-#define PAGEOUT 0x00010000 /* SUNOS specific */
-#define WRAP 0x00020000 /* SUNOS specific */
-
-/* c_cflag bit meaning */
-#define CBAUD 0x0000100f
-#define B0 0x00000000 /* hang up */
-#define B50 0x00000001
-#define B75 0x00000002
-#define B110 0x00000003
-#define B134 0x00000004
-#define B150 0x00000005
-#define B200 0x00000006
-#define B300 0x00000007
-#define B600 0x00000008
-#define B1200 0x00000009
-#define B1800 0x0000000a
-#define B2400 0x0000000b
-#define B4800 0x0000000c
-#define B9600 0x0000000d
-#define B19200 0x0000000e
-#define B38400 0x0000000f
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE 0x00000030
-#define CS5 0x00000000
-#define CS6 0x00000010
-#define CS7 0x00000020
-#define CS8 0x00000030
-#define CSTOPB 0x00000040
-#define CREAD 0x00000080
-#define PARENB 0x00000100
-#define PARODD 0x00000200
-#define HUPCL 0x00000400
-#define CLOCAL 0x00000800
-#define CBAUDEX 0x00001000
-/* We'll never see these speeds with the Zilogs, but for completeness... */
-#define BOTHER 0x00001000
-#define B57600 0x00001001
-#define B115200 0x00001002
-#define B230400 0x00001003
-#define B460800 0x00001004
-/* This is what we can do with the Zilogs. */
-#define B76800 0x00001005
-/* This is what we can do with the SAB82532. */
-#define B153600 0x00001006
-#define B307200 0x00001007
-#define B614400 0x00001008
-#define B921600 0x00001009
-/* And these are the rest... */
-#define B500000 0x0000100a
-#define B576000 0x0000100b
-#define B1000000 0x0000100c
-#define B1152000 0x0000100d
-#define B1500000 0x0000100e
-#define B2000000 0x0000100f
-/* These have totally bogus values and nobody uses them
- so far. Later on we'd have to use say 0x10000x and
- adjust CBAUD constant and drivers accordingly.
-#define B2500000 0x00001010
-#define B3000000 0x00001011
-#define B3500000 0x00001012
-#define B4000000 0x00001013 */
-#define CIBAUD 0x100f0000 /* input baud rate (not used) */
-#define CMSPAR 0x40000000 /* mark or space (stick) parity */
-#define CRTSCTS 0x80000000 /* flow control */
-
-#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
-
-/* c_lflag bits */
-#define ISIG 0x00000001
-#define ICANON 0x00000002
-#define XCASE 0x00000004
-#define ECHO 0x00000008
-#define ECHOE 0x00000010
-#define ECHOK 0x00000020
-#define ECHONL 0x00000040
-#define NOFLSH 0x00000080
-#define TOSTOP 0x00000100
-#define ECHOCTL 0x00000200
-#define ECHOPRT 0x00000400
-#define ECHOKE 0x00000800
-#define DEFECHO 0x00001000 /* SUNOS thing, what is it? */
-#define FLUSHO 0x00002000
-#define PENDIN 0x00004000
-#define IEXTEN 0x00008000
-
-/* modem lines */
-#define TIOCM_LE 0x001
-#define TIOCM_DTR 0x002
-#define TIOCM_RTS 0x004
-#define TIOCM_ST 0x008
-#define TIOCM_SR 0x010
-#define TIOCM_CTS 0x020
-#define TIOCM_CAR 0x040
-#define TIOCM_RNG 0x080
-#define TIOCM_DSR 0x100
-#define TIOCM_CD TIOCM_CAR
-#define TIOCM_RI TIOCM_RNG
-#define TIOCM_OUT1 0x2000
-#define TIOCM_OUT2 0x4000
-#define TIOCM_LOOP 0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
-
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF 0
-#define TCOON 1
-#define TCIOFF 2
-#define TCION 3
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH 0
-#define TCOFLUSH 1
-#define TCIOFLUSH 2
-
-/* tcsetattr uses these */
-#define TCSANOW 0
-#define TCSADRAIN 1
-#define TCSAFLUSH 2
-
-#endif /* !(_SPARC_TERMBITS_H) */
+++ /dev/null
-#ifndef _SPARC_TERMIOS_H
-#define _SPARC_TERMIOS_H
-
-#include <asm/ioctls.h>
-#include <asm/termbits.h>
-
-#if defined(__KERNEL__) || defined(__DEFINE_BSD_TERMIOS)
-struct sgttyb {
- char sg_ispeed;
- char sg_ospeed;
- char sg_erase;
- char sg_kill;
- short sg_flags;
-};
-
-struct tchars {
- char t_intrc;
- char t_quitc;
- char t_startc;
- char t_stopc;
- char t_eofc;
- char t_brkc;
-};
-
-struct ltchars {
- char t_suspc;
- char t_dsuspc;
- char t_rprntc;
- char t_flushc;
- char t_werasc;
- char t_lnextc;
-};
-#endif /* __KERNEL__ */
-
-struct winsize {
- unsigned short ws_row;
- unsigned short ws_col;
- unsigned short ws_xpixel;
- unsigned short ws_ypixel;
-};
-
-#ifdef __KERNEL__
-#include <linux/module.h>
-
-/*
- * c_cc characters in the termio structure. Oh, how I love being
- * backwardly compatible. Notice that character 4 and 5 are
- * interpreted differently depending on whether ICANON is set in
- * c_lflag. If it's set, they are used as _VEOF and _VEOL, otherwise
- * as _VMIN and V_TIME. This is for compatibility with OSF/1 (which
- * is compatible with sysV)...
- */
-#define _VMIN 4
-#define _VTIME 5
-
-/* intr=^C quit=^\ erase=del kill=^U
- eof=^D eol=\0 eol2=\0 sxtc=\0
- start=^Q stop=^S susp=^Z dsusp=^Y
- reprint=^R discard=^U werase=^W lnext=^V
- vmin=\1 vtime=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\000\000\000\021\023\032\031\022\025\027\026\001"
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
- unsigned short tmp; \
- int err; \
- err = get_user(tmp, &(termio)->c_iflag); \
- (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \
- err |= get_user(tmp, &(termio)->c_oflag); \
- (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \
- err |= get_user(tmp, &(termio)->c_cflag); \
- (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \
- err |= get_user(tmp, &(termio)->c_lflag); \
- (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \
- err |= copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
- err; \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- *
- * Note the "fun" _VMIN overloading.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
- int err; \
- err = put_user((termios)->c_iflag, &(termio)->c_iflag); \
- err |= put_user((termios)->c_oflag, &(termio)->c_oflag); \
- err |= put_user((termios)->c_cflag, &(termio)->c_cflag); \
- err |= put_user((termios)->c_lflag, &(termio)->c_lflag); \
- err |= put_user((termios)->c_line, &(termio)->c_line); \
- err |= copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
- if (!((termios)->c_lflag & ICANON)) { \
- err |= put_user((termios)->c_cc[VMIN], &(termio)->c_cc[_VMIN]); \
- err |= put_user((termios)->c_cc[VTIME], &(termio)->c_cc[_VTIME]); \
- } \
- err; \
-})
-
-#define user_termios_to_kernel_termios(k, u) \
-({ \
- int err; \
- err = get_user((k)->c_iflag, &(u)->c_iflag); \
- err |= get_user((k)->c_oflag, &(u)->c_oflag); \
- err |= get_user((k)->c_cflag, &(u)->c_cflag); \
- err |= get_user((k)->c_lflag, &(u)->c_lflag); \
- err |= get_user((k)->c_line, &(u)->c_line); \
- err |= copy_from_user((k)->c_cc, (u)->c_cc, NCCS); \
- if ((k)->c_lflag & ICANON) { \
- err |= get_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
- err |= get_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
- } else { \
- err |= get_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \
- err |= get_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
- } \
- err |= get_user((k)->c_ispeed, &(u)->c_ispeed); \
- err |= get_user((k)->c_ospeed, &(u)->c_ospeed); \
- err; \
-})
-
-#define kernel_termios_to_user_termios(u, k) \
-({ \
- int err; \
- err = put_user((k)->c_iflag, &(u)->c_iflag); \
- err |= put_user((k)->c_oflag, &(u)->c_oflag); \
- err |= put_user((k)->c_cflag, &(u)->c_cflag); \
- err |= put_user((k)->c_lflag, &(u)->c_lflag); \
- err |= put_user((k)->c_line, &(u)->c_line); \
- err |= copy_to_user((u)->c_cc, (k)->c_cc, NCCS); \
- if (!((k)->c_lflag & ICANON)) { \
- err |= put_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \
- err |= put_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
- } else { \
- err |= put_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
- err |= put_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
- } \
- err |= put_user((k)->c_ispeed, &(u)->c_ispeed); \
- err |= put_user((k)->c_ospeed, &(u)->c_ospeed); \
- err; \
-})
-
-#define user_termios_to_kernel_termios_1(k, u) \
-({ \
- int err; \
- err = get_user((k)->c_iflag, &(u)->c_iflag); \
- err |= get_user((k)->c_oflag, &(u)->c_oflag); \
- err |= get_user((k)->c_cflag, &(u)->c_cflag); \
- err |= get_user((k)->c_lflag, &(u)->c_lflag); \
- err |= get_user((k)->c_line, &(u)->c_line); \
- err |= copy_from_user((k)->c_cc, (u)->c_cc, NCCS); \
- if ((k)->c_lflag & ICANON) { \
- err |= get_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
- err |= get_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
- } else { \
- err |= get_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \
- err |= get_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
- } \
- err; \
-})
-
-#define kernel_termios_to_user_termios_1(u, k) \
-({ \
- int err; \
- err = put_user((k)->c_iflag, &(u)->c_iflag); \
- err |= put_user((k)->c_oflag, &(u)->c_oflag); \
- err |= put_user((k)->c_cflag, &(u)->c_cflag); \
- err |= put_user((k)->c_lflag, &(u)->c_lflag); \
- err |= put_user((k)->c_line, &(u)->c_line); \
- err |= copy_to_user((u)->c_cc, (k)->c_cc, NCCS); \
- if (!((k)->c_lflag & ICANON)) { \
- err |= put_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \
- err |= put_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
- } else { \
- err |= put_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
- err |= put_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
- } \
- err; \
-})
-
-#endif /* __KERNEL__ */
-
-#endif /* _SPARC_TERMIOS_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_THREAD_INFO_H
-#define ___ASM_SPARC_THREAD_INFO_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/thread_info_64.h>
-#else
-#include <asm-sparc/thread_info_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * thread_info.h: sparc low-level thread information
- * adapted from the ppc version by Pete Zaitcev, which was
- * adapted from the i386 version by Paul Mackerras
- *
- * Copyright (C) 2002 David Howells (dhowells@redhat.com)
- * Copyright (c) 2002 Pete Zaitcev (zaitcev@yahoo.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-
-#include <asm/btfixup.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-
-/*
- * Low level task data.
- *
- * If you change this, change the TI_* offsets below to match.
- */
-#define NSWINS 8
-struct thread_info {
- unsigned long uwinmask;
- struct task_struct *task; /* main task structure */
- struct exec_domain *exec_domain; /* execution domain */
- unsigned long flags; /* low level flags */
- int cpu; /* cpu we're on */
- int preempt_count; /* 0 => preemptable,
- <0 => BUG */
- int softirq_count;
- int hardirq_count;
-
- /* Context switch saved kernel state. */
- unsigned long ksp; /* ... ksp __attribute__ ((aligned (8))); */
- unsigned long kpc;
- unsigned long kpsr;
- unsigned long kwim;
-
- /* A place to store user windows and stack pointers
- * when the stack needs inspection.
- */
- struct reg_window reg_window[NSWINS]; /* align for ldd! */
- unsigned long rwbuf_stkptrs[NSWINS];
- unsigned long w_saved;
-
- struct restart_block restart_block;
-};
-
-/*
- * macros/functions for gaining access to the thread information structure
- *
- * preempt_count needs to be 1 initially, until the scheduler is functional.
- */
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .uwinmask = 0, \
- .task = &tsk, \
- .exec_domain = &default_exec_domain, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = 1, \
- .restart_block = { \
- .fn = do_no_restart_syscall, \
- }, \
-}
-
-#define init_thread_info (init_thread_union.thread_info)
-#define init_stack (init_thread_union.stack)
-
-/* how to get the thread information struct from C */
-register struct thread_info *current_thread_info_reg asm("g6");
-#define current_thread_info() (current_thread_info_reg)
-
-/*
- * thread information allocation
- */
-#if PAGE_SHIFT == 13
-#define THREAD_INFO_ORDER 0
-#else /* PAGE_SHIFT */
-#define THREAD_INFO_ORDER 1
-#endif
-
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-
-BTFIXUPDEF_CALL(struct thread_info *, alloc_thread_info, void)
-#define alloc_thread_info(tsk) BTFIXUP_CALL(alloc_thread_info)()
-
-BTFIXUPDEF_CALL(void, free_thread_info, struct thread_info *)
-#define free_thread_info(ti) BTFIXUP_CALL(free_thread_info)(ti)
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Size of kernel stack for each process.
- * Observe the order of get_free_pages() in alloc_thread_info().
- * The sun4 has 8K stack too, because it's short on memory, and 16K is a waste.
- */
-#define THREAD_SIZE 8192
-
-/*
- * Offsets in thread_info structure, used in assembly code
- * The "#define REGWIN_SZ 0x40" was abolished, so no multiplications.
- */
-#define TI_UWINMASK 0x00 /* uwinmask */
-#define TI_TASK 0x04
-#define TI_EXECDOMAIN 0x08 /* exec_domain */
-#define TI_FLAGS 0x0c
-#define TI_CPU 0x10
-#define TI_PREEMPT 0x14 /* preempt_count */
-#define TI_SOFTIRQ 0x18 /* softirq_count */
-#define TI_HARDIRQ 0x1c /* hardirq_count */
-#define TI_KSP 0x20 /* ksp */
-#define TI_KPC 0x24 /* kpc (ldd'ed with kpc) */
-#define TI_KPSR 0x28 /* kpsr */
-#define TI_KWIM 0x2c /* kwim (ldd'ed with kpsr) */
-#define TI_REG_WINDOW 0x30
-#define TI_RWIN_SPTRS 0x230
-#define TI_W_SAVED 0x250
-/* #define TI_RESTART_BLOCK 0x25n */ /* Nobody cares */
-
-#define PREEMPT_ACTIVE 0x4000000
-
-/*
- * thread information flag bit numbers
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-/* flag bit 1 is available */
-#define TIF_SIGPENDING 2 /* signal pending */
-#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
-#define TIF_RESTORE_SIGMASK 4 /* restore signal mask in do_signal() */
-#define TIF_USEDFPU 8 /* FPU was used by this task
- * this quantum (SMP) */
-#define TIF_POLLING_NRFLAG 9 /* true if poll_idle() is polling
- * TIF_NEED_RESCHED */
-#define TIF_MEMDIE 10
-
-/* as above, but as bit values */
-#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
-#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
-#define _TIF_USEDFPU (1<<TIF_USEDFPU)
-#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
+++ /dev/null
-/* thread_info.h: sparc64 low-level thread information
- *
- * Copyright (C) 2002 David S. Miller (davem@redhat.com)
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#ifdef __KERNEL__
-
-#define NSWINS 7
-
-#define TI_FLAG_BYTE_FAULT_CODE 0
-#define TI_FLAG_FAULT_CODE_SHIFT 56
-#define TI_FLAG_BYTE_WSTATE 1
-#define TI_FLAG_WSTATE_SHIFT 48
-#define TI_FLAG_BYTE_CWP 2
-#define TI_FLAG_CWP_SHIFT 40
-#define TI_FLAG_BYTE_CURRENT_DS 3
-#define TI_FLAG_CURRENT_DS_SHIFT 32
-#define TI_FLAG_BYTE_FPDEPTH 4
-#define TI_FLAG_FPDEPTH_SHIFT 24
-#define TI_FLAG_BYTE_WSAVED 5
-#define TI_FLAG_WSAVED_SHIFT 16
-
-#include <asm/page.h>
-
-#ifndef __ASSEMBLY__
-
-#include <asm/ptrace.h>
-#include <asm/types.h>
-
-struct task_struct;
-struct exec_domain;
-
-struct thread_info {
- /* D$ line 1 */
- struct task_struct *task;
- unsigned long flags;
- __u8 fpsaved[7];
- __u8 status;
- unsigned long ksp;
-
- /* D$ line 2 */
- unsigned long fault_address;
- struct pt_regs *kregs;
- struct exec_domain *exec_domain;
- int preempt_count; /* 0 => preemptable, <0 => BUG */
- __u8 new_child;
- __u8 syscall_noerror;
- __u16 cpu;
-
- unsigned long *utraps;
-
- struct reg_window reg_window[NSWINS];
- unsigned long rwbuf_stkptrs[NSWINS];
-
- unsigned long gsr[7];
- unsigned long xfsr[7];
-
- __u64 __user *user_cntd0;
- __u64 __user *user_cntd1;
- __u64 kernel_cntd0, kernel_cntd1;
- __u64 pcr_reg;
-
- struct restart_block restart_block;
-
- struct pt_regs *kern_una_regs;
- unsigned int kern_una_insn;
-
- unsigned long fpregs[0] __attribute__ ((aligned(64)));
-};
-
-#endif /* !(__ASSEMBLY__) */
-
-/* offsets into the thread_info struct for assembly code access */
-#define TI_TASK 0x00000000
-#define TI_FLAGS 0x00000008
-#define TI_FAULT_CODE (TI_FLAGS + TI_FLAG_BYTE_FAULT_CODE)
-#define TI_WSTATE (TI_FLAGS + TI_FLAG_BYTE_WSTATE)
-#define TI_CWP (TI_FLAGS + TI_FLAG_BYTE_CWP)
-#define TI_CURRENT_DS (TI_FLAGS + TI_FLAG_BYTE_CURRENT_DS)
-#define TI_FPDEPTH (TI_FLAGS + TI_FLAG_BYTE_FPDEPTH)
-#define TI_WSAVED (TI_FLAGS + TI_FLAG_BYTE_WSAVED)
-#define TI_FPSAVED 0x00000010
-#define TI_KSP 0x00000018
-#define TI_FAULT_ADDR 0x00000020
-#define TI_KREGS 0x00000028
-#define TI_EXEC_DOMAIN 0x00000030
-#define TI_PRE_COUNT 0x00000038
-#define TI_NEW_CHILD 0x0000003c
-#define TI_SYS_NOERROR 0x0000003d
-#define TI_CPU 0x0000003e
-#define TI_UTRAPS 0x00000040
-#define TI_REG_WINDOW 0x00000048
-#define TI_RWIN_SPTRS 0x000003c8
-#define TI_GSR 0x00000400
-#define TI_XFSR 0x00000438
-#define TI_USER_CNTD0 0x00000470
-#define TI_USER_CNTD1 0x00000478
-#define TI_KERN_CNTD0 0x00000480
-#define TI_KERN_CNTD1 0x00000488
-#define TI_PCR 0x00000490
-#define TI_RESTART_BLOCK 0x00000498
-#define TI_KUNA_REGS 0x000004c0
-#define TI_KUNA_INSN 0x000004c8
-#define TI_FPREGS 0x00000500
-
-/* We embed this in the uppermost byte of thread_info->flags */
-#define FAULT_CODE_WRITE 0x01 /* Write access, implies D-TLB */
-#define FAULT_CODE_DTLB 0x02 /* Miss happened in D-TLB */
-#define FAULT_CODE_ITLB 0x04 /* Miss happened in I-TLB */
-#define FAULT_CODE_WINFIXUP 0x08 /* Miss happened during spill/fill */
-#define FAULT_CODE_BLKCOMMIT 0x10 /* Use blk-commit ASI in copy_page */
-
-#if PAGE_SHIFT == 13
-#define THREAD_SIZE (2*PAGE_SIZE)
-#define THREAD_SHIFT (PAGE_SHIFT + 1)
-#else /* PAGE_SHIFT == 13 */
-#define THREAD_SIZE PAGE_SIZE
-#define THREAD_SHIFT PAGE_SHIFT
-#endif /* PAGE_SHIFT == 13 */
-
-#define PREEMPT_ACTIVE 0x4000000
-
-/*
- * macros/functions for gaining access to the thread information structure
- *
- * preempt_count needs to be 1 initially, until the scheduler is functional.
- */
-#ifndef __ASSEMBLY__
-
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = ((unsigned long)ASI_P) << TI_FLAG_CURRENT_DS_SHIFT, \
- .exec_domain = &default_exec_domain, \
- .preempt_count = 1, \
- .restart_block = { \
- .fn = do_no_restart_syscall, \
- }, \
-}
-
-#define init_thread_info (init_thread_union.thread_info)
-#define init_stack (init_thread_union.stack)
-
-/* how to get the thread information struct from C */
-register struct thread_info *current_thread_info_reg asm("g6");
-#define current_thread_info() (current_thread_info_reg)
-
-/* thread information allocation */
-#if PAGE_SHIFT == 13
-#define __THREAD_INFO_ORDER 1
-#else /* PAGE_SHIFT == 13 */
-#define __THREAD_INFO_ORDER 0
-#endif /* PAGE_SHIFT == 13 */
-
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-
-#ifdef CONFIG_DEBUG_STACK_USAGE
-#define alloc_thread_info(tsk) \
-({ \
- struct thread_info *ret; \
- \
- ret = (struct thread_info *) \
- __get_free_pages(GFP_KERNEL, __THREAD_INFO_ORDER); \
- if (ret) \
- memset(ret, 0, PAGE_SIZE<<__THREAD_INFO_ORDER); \
- ret; \
-})
-#else
-#define alloc_thread_info(tsk) \
- ((struct thread_info *)__get_free_pages(GFP_KERNEL, __THREAD_INFO_ORDER))
-#endif
-
-#define free_thread_info(ti) \
- free_pages((unsigned long)(ti),__THREAD_INFO_ORDER)
-
-#define __thread_flag_byte_ptr(ti) \
- ((unsigned char *)(&((ti)->flags)))
-#define __cur_thread_flag_byte_ptr __thread_flag_byte_ptr(current_thread_info())
-
-#define get_thread_fault_code() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FAULT_CODE])
-#define set_thread_fault_code(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FAULT_CODE] = (val))
-#define get_thread_wstate() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSTATE])
-#define set_thread_wstate(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSTATE] = (val))
-#define get_thread_cwp() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CWP])
-#define set_thread_cwp(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CWP] = (val))
-#define get_thread_current_ds() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CURRENT_DS])
-#define set_thread_current_ds(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CURRENT_DS] = (val))
-#define get_thread_fpdepth() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FPDEPTH])
-#define set_thread_fpdepth(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FPDEPTH] = (val))
-#define get_thread_wsaved() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSAVED])
-#define set_thread_wsaved(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSAVED] = (val))
-
-#endif /* !(__ASSEMBLY__) */
-
-/*
- * Thread information flags, only 16 bits are available as we encode
- * other values into the upper 6 bytes.
- *
- * On trap return we need to test several values:
- *
- * user: need_resched, notify_resume, sigpending, wsaved, perfctr
- * kernel: fpdepth
- *
- * So to check for work in the kernel case we simply load the fpdepth
- * byte out of the flags and test it. For the user case we encode the
- * lower 3 bytes of flags as follows:
- * ----------------------------------------
- * | wsaved | flags byte 1 | flags byte 2 |
- * ----------------------------------------
- * This optimizes the user test into:
- * ldx [%g6 + TI_FLAGS], REG1
- * sethi %hi(_TIF_USER_WORK_MASK), REG2
- * or REG2, %lo(_TIF_USER_WORK_MASK), REG2
- * andcc REG1, REG2, %g0
- * be,pt no_work_to_do
- * nop
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-/* flags bit 1 is available */
-#define TIF_SIGPENDING 2 /* signal pending */
-#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
-#define TIF_PERFCTR 4 /* performance counters active */
-#define TIF_UNALIGNED 5 /* allowed to do unaligned accesses */
-/* flag bit 6 is available */
-#define TIF_32BIT 7 /* 32-bit binary */
-/* flag bit 8 is available */
-#define TIF_SECCOMP 9 /* secure computing */
-#define TIF_SYSCALL_AUDIT 10 /* syscall auditing active */
-/* flag bit 11 is available */
-/* NOTE: Thread flags >= 12 should be ones we have no interest
- * in using in assembly, else we can't use the mask as
- * an immediate value in instructions such as andcc.
- */
-#define TIF_ABI_PENDING 12
-#define TIF_MEMDIE 13
-#define TIF_POLLING_NRFLAG 14
-
-#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
-#define _TIF_PERFCTR (1<<TIF_PERFCTR)
-#define _TIF_UNALIGNED (1<<TIF_UNALIGNED)
-#define _TIF_32BIT (1<<TIF_32BIT)
-#define _TIF_SECCOMP (1<<TIF_SECCOMP)
-#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
-#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
-#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
-
-#define _TIF_USER_WORK_MASK ((0xff << TI_FLAG_WSAVED_SHIFT) | \
- (_TIF_SIGPENDING | \
- _TIF_NEED_RESCHED | _TIF_PERFCTR))
-
-/*
- * Thread-synchronous status.
- *
- * This is different from the flags in that nobody else
- * ever touches our thread-synchronous status, so we don't
- * have to worry about atomic accesses.
- *
- * Note that there are only 8 bits available.
- */
-#define TS_RESTORE_SIGMASK 0x0001 /* restore signal mask in do_signal() */
-
-#ifndef __ASSEMBLY__
-#define HAVE_SET_RESTORE_SIGMASK 1
-static inline void set_restore_sigmask(void)
-{
- struct thread_info *ti = current_thread_info();
- ti->status |= TS_RESTORE_SIGMASK;
- set_bit(TIF_SIGPENDING, &ti->flags);
-}
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_TIMER_H
-#define ___ASM_SPARC_TIMER_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/timer_64.h>
-#else
-#include <asm-sparc/timer_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * timer.h: Definitions for the timer chips on the Sparc.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-
-#ifndef _SPARC_TIMER_H
-#define _SPARC_TIMER_H
-
-#include <asm/system.h> /* For SUN4M_NCPUS */
-#include <asm/sun4paddr.h>
-#include <asm/btfixup.h>
-
-/* Timer structures. The interrupt timer has two properties which
- * are the counter (which is handled in do_timer in sched.c) and the limit.
- * This limit is where the timer's counter 'wraps' around. Oddly enough,
- * the sun4c timer when it hits the limit wraps back to 1 and not zero
- * thus when calculating the value at which it will fire a microsecond you
- * must adjust by one. Thanks SUN for designing such great hardware ;(
- */
-
-/* Note that I am only going to use the timer that interrupts at
- * Sparc IRQ 10. There is another one available that can fire at
- * IRQ 14. Currently it is left untouched, we keep the PROM's limit
- * register value and let the prom take these interrupts. This allows
- * L1-A to work.
- */
-
-struct sun4c_timer_info {
- __volatile__ unsigned int cur_count10;
- __volatile__ unsigned int timer_limit10;
- __volatile__ unsigned int cur_count14;
- __volatile__ unsigned int timer_limit14;
-};
-
-#define SUN4C_TIMER_PHYSADDR 0xf3000000
-#ifdef CONFIG_SUN4
-#define SUN_TIMER_PHYSADDR SUN4_300_TIMER_PHYSADDR
-#else
-#define SUN_TIMER_PHYSADDR SUN4C_TIMER_PHYSADDR
-#endif
-
-/* A sun4m has two blocks of registers which are probably of the same
- * structure. LSI Logic's L64851 is told to _decrement_ from the limit
- * value. Aurora behaves similarly but its limit value is compacted in
- * other fashion (it's wider). Documented fields are defined here.
- */
-
-/* As with the interrupt register, we have two classes of timer registers
- * which are per-cpu and master. Per-cpu timers only hit that cpu and are
- * only level 14 ticks, master timer hits all cpus and is level 10.
- */
-
-#define SUN4M_PRM_CNT_L 0x80000000
-#define SUN4M_PRM_CNT_LVALUE 0x7FFFFC00
-
-struct sun4m_timer_percpu_info {
- __volatile__ unsigned int l14_timer_limit; /* Initial value is 0x009c4000 */
- __volatile__ unsigned int l14_cur_count;
-
- /* This register appears to be write only and/or inaccessible
- * on Uni-Processor sun4m machines.
- */
- __volatile__ unsigned int l14_limit_noclear; /* Data access error is here */
-
- __volatile__ unsigned int cntrl; /* =1 after POST on Aurora */
- __volatile__ unsigned char space[PAGE_SIZE - 16];
-};
-
-struct sun4m_timer_regs {
- struct sun4m_timer_percpu_info cpu_timers[SUN4M_NCPUS];
- volatile unsigned int l10_timer_limit;
- volatile unsigned int l10_cur_count;
-
- /* Again, this appears to be write only and/or inaccessible
- * on uni-processor sun4m machines.
- */
- volatile unsigned int l10_limit_noclear;
-
- /* This register too, it must be magic. */
- volatile unsigned int foobar;
-
- volatile unsigned int cfg; /* equals zero at boot time... */
-};
-
-#define SUN4D_PRM_CNT_L 0x80000000
-#define SUN4D_PRM_CNT_LVALUE 0x7FFFFC00
-
-struct sun4d_timer_regs {
- volatile unsigned int l10_timer_limit;
- volatile unsigned int l10_cur_countx;
- volatile unsigned int l10_limit_noclear;
- volatile unsigned int ctrl;
- volatile unsigned int l10_cur_count;
-};
-
-extern struct sun4d_timer_regs *sun4d_timers;
-
-extern __volatile__ unsigned int *master_l10_counter;
-extern __volatile__ unsigned int *master_l10_limit;
-
-/* FIXME: Make do_[gs]ettimeofday btfixup calls */
-BTFIXUPDEF_CALL(int, bus_do_settimeofday, struct timespec *tv)
-#define bus_do_settimeofday(tv) BTFIXUP_CALL(bus_do_settimeofday)(tv)
-
-#endif /* !(_SPARC_TIMER_H) */
+++ /dev/null
-/* timer.h: System timer definitions for sun5.
- *
- * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net)
- */
-
-#ifndef _SPARC64_TIMER_H
-#define _SPARC64_TIMER_H
-
-#include <linux/types.h>
-#include <linux/init.h>
-
-struct sparc64_tick_ops {
- unsigned long (*get_tick)(void);
- int (*add_compare)(unsigned long);
- unsigned long softint_mask;
- void (*disable_irq)(void);
-
- void (*init_tick)(void);
- unsigned long (*add_tick)(unsigned long);
-
- char *name;
-};
-
-extern struct sparc64_tick_ops *tick_ops;
-
-extern unsigned long sparc64_get_clock_tick(unsigned int cpu);
-extern void __devinit setup_sparc64_timer(void);
-extern void __init time_init(void);
-
-#endif /* _SPARC64_TIMER_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_TIMEX_H
-#define ___ASM_SPARC_TIMEX_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/timex_64.h>
-#else
-#include <asm-sparc/timex_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * linux/include/asm-sparc/timex.h
- *
- * sparc architecture timex specifications
- */
-#ifndef _ASMsparc_TIMEX_H
-#define _ASMsparc_TIMEX_H
-
-#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
-
-/* XXX Maybe do something better at some point... -DaveM */
-typedef unsigned long cycles_t;
-#define get_cycles() (0)
-
-#endif
+++ /dev/null
-/*
- * linux/include/asm-sparc64/timex.h
- *
- * sparc64 architecture timex specifications
- */
-#ifndef _ASMsparc64_TIMEX_H
-#define _ASMsparc64_TIMEX_H
-
-#include <asm/timer.h>
-
-#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
-
-/* Getting on the cycle counter on sparc64. */
-typedef unsigned long cycles_t;
-#define get_cycles() tick_ops->get_tick()
-
-#define ARCH_HAS_READ_CURRENT_TIMER
-
-#endif
+++ /dev/null
-#ifndef ___ASM_SPARC_TLB_H
-#define ___ASM_SPARC_TLB_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/tlb_64.h>
-#else
-#include <asm-sparc/tlb_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _SPARC_TLB_H
-#define _SPARC_TLB_H
-
-#define tlb_start_vma(tlb, vma) \
-do { \
- flush_cache_range(vma, vma->vm_start, vma->vm_end); \
-} while (0)
-
-#define tlb_end_vma(tlb, vma) \
-do { \
- flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
-} while (0)
-
-#define __tlb_remove_tlb_entry(tlb, pte, address) \
- do { } while (0)
-
-#define tlb_flush(tlb) \
-do { \
- flush_tlb_mm((tlb)->mm); \
-} while (0)
-
-#include <asm-generic/tlb.h>
-
-#endif /* _SPARC_TLB_H */
+++ /dev/null
-#ifndef _SPARC64_TLB_H
-#define _SPARC64_TLB_H
-
-#include <linux/swap.h>
-#include <linux/pagemap.h>
-#include <asm/pgalloc.h>
-#include <asm/tlbflush.h>
-#include <asm/mmu_context.h>
-
-#define TLB_BATCH_NR 192
-
-/*
- * For UP we don't need to worry about TLB flush
- * and page free order so much..
- */
-#ifdef CONFIG_SMP
- #define FREE_PTE_NR 506
- #define tlb_fast_mode(bp) ((bp)->pages_nr == ~0U)
-#else
- #define FREE_PTE_NR 1
- #define tlb_fast_mode(bp) 1
-#endif
-
-struct mmu_gather {
- struct mm_struct *mm;
- unsigned int pages_nr;
- unsigned int need_flush;
- unsigned int fullmm;
- unsigned int tlb_nr;
- unsigned long vaddrs[TLB_BATCH_NR];
- struct page *pages[FREE_PTE_NR];
-};
-
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
-
-#ifdef CONFIG_SMP
-extern void smp_flush_tlb_pending(struct mm_struct *,
- unsigned long, unsigned long *);
-#endif
-
-extern void __flush_tlb_pending(unsigned long, unsigned long, unsigned long *);
-extern void flush_tlb_pending(void);
-
-static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
-{
- struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
-
- BUG_ON(mp->tlb_nr);
-
- mp->mm = mm;
- mp->pages_nr = num_online_cpus() > 1 ? 0U : ~0U;
- mp->fullmm = full_mm_flush;
-
- return mp;
-}
-
-
-static inline void tlb_flush_mmu(struct mmu_gather *mp)
-{
- if (mp->need_flush) {
- free_pages_and_swap_cache(mp->pages, mp->pages_nr);
- mp->pages_nr = 0;
- mp->need_flush = 0;
- }
-
-}
-
-#ifdef CONFIG_SMP
-extern void smp_flush_tlb_mm(struct mm_struct *mm);
-#define do_flush_tlb_mm(mm) smp_flush_tlb_mm(mm)
-#else
-#define do_flush_tlb_mm(mm) __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT)
-#endif
-
-static inline void tlb_finish_mmu(struct mmu_gather *mp, unsigned long start, unsigned long end)
-{
- tlb_flush_mmu(mp);
-
- if (mp->fullmm)
- mp->fullmm = 0;
- else
- flush_tlb_pending();
-
- /* keep the page table cache within bounds */
- check_pgt_cache();
-
- put_cpu_var(mmu_gathers);
-}
-
-static inline void tlb_remove_page(struct mmu_gather *mp, struct page *page)
-{
- if (tlb_fast_mode(mp)) {
- free_page_and_swap_cache(page);
- return;
- }
- mp->need_flush = 1;
- mp->pages[mp->pages_nr++] = page;
- if (mp->pages_nr >= FREE_PTE_NR)
- tlb_flush_mmu(mp);
-}
-
-#define tlb_remove_tlb_entry(mp,ptep,addr) do { } while (0)
-#define pte_free_tlb(mp, ptepage) pte_free((mp)->mm, ptepage)
-#define pmd_free_tlb(mp, pmdp) pmd_free((mp)->mm, pmdp)
-#define pud_free_tlb(tlb,pudp) __pud_free_tlb(tlb,pudp)
-
-#define tlb_migrate_finish(mm) do { } while (0)
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-
-#endif /* _SPARC64_TLB_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_TLBFLUSH_H
-#define ___ASM_SPARC_TLBFLUSH_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/tlbflush_64.h>
-#else
-#include <asm-sparc/tlbflush_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _SPARC_TLBFLUSH_H
-#define _SPARC_TLBFLUSH_H
-
-#include <linux/mm.h>
-// #include <asm/processor.h>
-
-/*
- * TLB flushing:
- *
- * - flush_tlb() flushes the current mm struct TLBs XXX Exists?
- * - flush_tlb_all() flushes all processes TLBs
- * - flush_tlb_mm(mm) flushes the specified mm context TLB's
- * - flush_tlb_page(vma, vmaddr) flushes one page
- * - flush_tlb_range(vma, start, end) flushes a range of pages
- * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
- */
-
-#ifdef CONFIG_SMP
-
-BTFIXUPDEF_CALL(void, local_flush_tlb_all, void)
-BTFIXUPDEF_CALL(void, local_flush_tlb_mm, struct mm_struct *)
-BTFIXUPDEF_CALL(void, local_flush_tlb_range, struct vm_area_struct *, unsigned long, unsigned long)
-BTFIXUPDEF_CALL(void, local_flush_tlb_page, struct vm_area_struct *, unsigned long)
-
-#define local_flush_tlb_all() BTFIXUP_CALL(local_flush_tlb_all)()
-#define local_flush_tlb_mm(mm) BTFIXUP_CALL(local_flush_tlb_mm)(mm)
-#define local_flush_tlb_range(vma,start,end) BTFIXUP_CALL(local_flush_tlb_range)(vma,start,end)
-#define local_flush_tlb_page(vma,addr) BTFIXUP_CALL(local_flush_tlb_page)(vma,addr)
-
-extern void smp_flush_tlb_all(void);
-extern void smp_flush_tlb_mm(struct mm_struct *mm);
-extern void smp_flush_tlb_range(struct vm_area_struct *vma,
- unsigned long start,
- unsigned long end);
-extern void smp_flush_tlb_page(struct vm_area_struct *mm, unsigned long page);
-
-#endif /* CONFIG_SMP */
-
-BTFIXUPDEF_CALL(void, flush_tlb_all, void)
-BTFIXUPDEF_CALL(void, flush_tlb_mm, struct mm_struct *)
-BTFIXUPDEF_CALL(void, flush_tlb_range, struct vm_area_struct *, unsigned long, unsigned long)
-BTFIXUPDEF_CALL(void, flush_tlb_page, struct vm_area_struct *, unsigned long)
-
-#define flush_tlb_all() BTFIXUP_CALL(flush_tlb_all)()
-#define flush_tlb_mm(mm) BTFIXUP_CALL(flush_tlb_mm)(mm)
-#define flush_tlb_range(vma,start,end) BTFIXUP_CALL(flush_tlb_range)(vma,start,end)
-#define flush_tlb_page(vma,addr) BTFIXUP_CALL(flush_tlb_page)(vma,addr)
-
-// #define flush_tlb() flush_tlb_mm(current->active_mm) /* XXX Sure? */
-
-/*
- * This is a kludge, until I know better. --zaitcev XXX
- */
-static inline void flush_tlb_kernel_range(unsigned long start,
- unsigned long end)
-{
- flush_tlb_all();
-}
-
-#endif /* _SPARC_TLBFLUSH_H */
+++ /dev/null
-#ifndef _SPARC64_TLBFLUSH_H
-#define _SPARC64_TLBFLUSH_H
-
-#include <linux/mm.h>
-#include <asm/mmu_context.h>
-
-/* TSB flush operations. */
-struct mmu_gather;
-extern void flush_tsb_kernel_range(unsigned long start, unsigned long end);
-extern void flush_tsb_user(struct mmu_gather *mp);
-
-/* TLB flush operations. */
-
-extern void flush_tlb_pending(void);
-
-#define flush_tlb_range(vma,start,end) \
- do { (void)(start); flush_tlb_pending(); } while (0)
-#define flush_tlb_page(vma,addr) flush_tlb_pending()
-#define flush_tlb_mm(mm) flush_tlb_pending()
-
-/* Local cpu only. */
-extern void __flush_tlb_all(void);
-
-extern void __flush_tlb_kernel_range(unsigned long start, unsigned long end);
-
-#ifndef CONFIG_SMP
-
-#define flush_tlb_kernel_range(start,end) \
-do { flush_tsb_kernel_range(start,end); \
- __flush_tlb_kernel_range(start,end); \
-} while (0)
-
-#else /* CONFIG_SMP */
-
-extern void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end);
-
-#define flush_tlb_kernel_range(start, end) \
-do { flush_tsb_kernel_range(start,end); \
- smp_flush_tlb_kernel_range(start, end); \
-} while (0)
-
-#endif /* ! CONFIG_SMP */
-
-#endif /* _SPARC64_TLBFLUSH_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_TOPOLOGY_H
-#define ___ASM_SPARC_TOPOLOGY_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/topology_64.h>
-#else
-#include <asm-sparc/topology_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _ASM_SPARC_TOPOLOGY_H
-#define _ASM_SPARC_TOPOLOGY_H
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_SPARC_TOPOLOGY_H */
+++ /dev/null
-#ifndef _ASM_SPARC64_TOPOLOGY_H
-#define _ASM_SPARC64_TOPOLOGY_H
-
-#ifdef CONFIG_NUMA
-
-#include <asm/mmzone.h>
-
-static inline int cpu_to_node(int cpu)
-{
- return numa_cpu_lookup_table[cpu];
-}
-
-#define parent_node(node) (node)
-
-static inline cpumask_t node_to_cpumask(int node)
-{
- return numa_cpumask_lookup_table[node];
-}
-
-/* Returns a pointer to the cpumask of CPUs on Node 'node'. */
-#define node_to_cpumask_ptr(v, node) \
- cpumask_t *v = &(numa_cpumask_lookup_table[node])
-
-#define node_to_cpumask_ptr_next(v, node) \
- v = &(numa_cpumask_lookup_table[node])
-
-static inline int node_to_first_cpu(int node)
-{
- cpumask_t tmp;
- tmp = node_to_cpumask(node);
- return first_cpu(tmp);
-}
-
-struct pci_bus;
-#ifdef CONFIG_PCI
-extern int pcibus_to_node(struct pci_bus *pbus);
-#else
-static inline int pcibus_to_node(struct pci_bus *pbus)
-{
- return -1;
-}
-#endif
-
-#define pcibus_to_cpumask(bus) \
- (pcibus_to_node(bus) == -1 ? \
- CPU_MASK_ALL : \
- node_to_cpumask(pcibus_to_node(bus)))
-
-#define SD_NODE_INIT (struct sched_domain) { \
- .min_interval = 8, \
- .max_interval = 32, \
- .busy_factor = 32, \
- .imbalance_pct = 125, \
- .cache_nice_tries = 2, \
- .busy_idx = 3, \
- .idle_idx = 2, \
- .newidle_idx = 0, \
- .wake_idx = 1, \
- .forkexec_idx = 1, \
- .flags = SD_LOAD_BALANCE \
- | SD_BALANCE_FORK \
- | SD_BALANCE_EXEC \
- | SD_SERIALIZE \
- | SD_WAKE_BALANCE, \
- .last_balance = jiffies, \
- .balance_interval = 1, \
-}
-
-#else /* CONFIG_NUMA */
-
-#include <asm-generic/topology.h>
-
-#endif /* !(CONFIG_NUMA) */
-
-#ifdef CONFIG_SMP
-#define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id)
-#define topology_core_id(cpu) (cpu_data(cpu).core_id)
-#define topology_core_siblings(cpu) (cpu_core_map[cpu])
-#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu))
-#define mc_capable() (sparc64_multi_core)
-#define smt_capable() (sparc64_multi_core)
-#endif /* CONFIG_SMP */
-
-#define cpu_coregroup_map(cpu) (cpu_core_map[cpu])
-
-#endif /* _ASM_SPARC64_TOPOLOGY_H */
+++ /dev/null
-/*
- * traps.h: Format of entries for the Sparc trap table.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_TRAPS_H
-#define _SPARC_TRAPS_H
-
-#define NUM_SPARC_TRAPS 255
-
-#ifndef __ASSEMBLY__
-
-/* This is for V8 compliant Sparc CPUS */
-struct tt_entry {
- unsigned long inst_one;
- unsigned long inst_two;
- unsigned long inst_three;
- unsigned long inst_four;
-};
-
-/* We set this to _start in system setup. */
-extern struct tt_entry *sparc_ttable;
-
-static inline unsigned long get_tbr(void)
-{
- unsigned long tbr;
-
- __asm__ __volatile__("rd %%tbr, %0\n\t" : "=r" (tbr));
- return tbr;
-}
-
-#endif /* !(__ASSEMBLY__) */
-
-/* For patching the trap table at boot time, we need to know how to
- * form various common Sparc instructions. Thus these macros...
- */
-
-#define SPARC_MOV_CONST_L3(const) (0xa6102000 | (const&0xfff))
-
-/* The following assumes that the branch lies before the place we
- * are branching to. This is the case for a trap vector...
- * You have been warned.
- */
-#define SPARC_BRANCH(dest_addr, inst_addr) \
- (0x10800000 | (((dest_addr-inst_addr)>>2)&0x3fffff))
-
-#define SPARC_RD_PSR_L0 (0xa1480000)
-#define SPARC_RD_WIM_L3 (0xa7500000)
-#define SPARC_NOP (0x01000000)
-
-/* Various interesting trap levels. */
-/* First, hardware traps. */
-#define SP_TRAP_TFLT 0x1 /* Text fault */
-#define SP_TRAP_II 0x2 /* Illegal Instruction */
-#define SP_TRAP_PI 0x3 /* Privileged Instruction */
-#define SP_TRAP_FPD 0x4 /* Floating Point Disabled */
-#define SP_TRAP_WOVF 0x5 /* Window Overflow */
-#define SP_TRAP_WUNF 0x6 /* Window Underflow */
-#define SP_TRAP_MNA 0x7 /* Memory Address Unaligned */
-#define SP_TRAP_FPE 0x8 /* Floating Point Exception */
-#define SP_TRAP_DFLT 0x9 /* Data Fault */
-#define SP_TRAP_TOF 0xa /* Tag Overflow */
-#define SP_TRAP_WDOG 0xb /* Watchpoint Detected */
-#define SP_TRAP_IRQ1 0x11 /* IRQ level 1 */
-#define SP_TRAP_IRQ2 0x12 /* IRQ level 2 */
-#define SP_TRAP_IRQ3 0x13 /* IRQ level 3 */
-#define SP_TRAP_IRQ4 0x14 /* IRQ level 4 */
-#define SP_TRAP_IRQ5 0x15 /* IRQ level 5 */
-#define SP_TRAP_IRQ6 0x16 /* IRQ level 6 */
-#define SP_TRAP_IRQ7 0x17 /* IRQ level 7 */
-#define SP_TRAP_IRQ8 0x18 /* IRQ level 8 */
-#define SP_TRAP_IRQ9 0x19 /* IRQ level 9 */
-#define SP_TRAP_IRQ10 0x1a /* IRQ level 10 */
-#define SP_TRAP_IRQ11 0x1b /* IRQ level 11 */
-#define SP_TRAP_IRQ12 0x1c /* IRQ level 12 */
-#define SP_TRAP_IRQ13 0x1d /* IRQ level 13 */
-#define SP_TRAP_IRQ14 0x1e /* IRQ level 14 */
-#define SP_TRAP_IRQ15 0x1f /* IRQ level 15 Non-maskable */
-#define SP_TRAP_RACC 0x20 /* Register Access Error ??? */
-#define SP_TRAP_IACC 0x21 /* Instruction Access Error */
-#define SP_TRAP_CPDIS 0x24 /* Co-Processor Disabled */
-#define SP_TRAP_BADFL 0x25 /* Unimplemented Flush Instruction */
-#define SP_TRAP_CPEXP 0x28 /* Co-Processor Exception */
-#define SP_TRAP_DACC 0x29 /* Data Access Error */
-#define SP_TRAP_DIVZ 0x2a /* Divide By Zero */
-#define SP_TRAP_DSTORE 0x2b /* Data Store Error ??? */
-#define SP_TRAP_DMM 0x2c /* Data Access MMU Miss ??? */
-#define SP_TRAP_IMM 0x3c /* Instruction Access MMU Miss ??? */
-
-/* Now the Software Traps... */
-#define SP_TRAP_SUNOS 0x80 /* SunOS System Call */
-#define SP_TRAP_SBPT 0x81 /* Software Breakpoint */
-#define SP_TRAP_SDIVZ 0x82 /* Software Divide-by-Zero trap */
-#define SP_TRAP_FWIN 0x83 /* Flush Windows */
-#define SP_TRAP_CWIN 0x84 /* Clean Windows */
-#define SP_TRAP_RCHK 0x85 /* Range Check */
-#define SP_TRAP_FUNA 0x86 /* Fix Unaligned Access */
-#define SP_TRAP_IOWFL 0x87 /* Integer Overflow */
-#define SP_TRAP_SOLARIS 0x88 /* Solaris System Call */
-#define SP_TRAP_NETBSD 0x89 /* NetBSD System Call */
-#define SP_TRAP_LINUX 0x90 /* Linux System Call */
-
-/* Names used for compatibility with SunOS */
-#define ST_SYSCALL 0x00
-#define ST_BREAKPOINT 0x01
-#define ST_DIV0 0x02
-#define ST_FLUSH_WINDOWS 0x03
-#define ST_CLEAN_WINDOWS 0x04
-#define ST_RANGE_CHECK 0x05
-#define ST_FIX_ALIGN 0x06
-#define ST_INT_OVERFLOW 0x07
-
-/* Special traps... */
-#define SP_TRAP_KBPT1 0xfe /* KADB/PROM Breakpoint one */
-#define SP_TRAP_KBPT2 0xff /* KADB/PROM Breakpoint two */
-
-/* Handy Macros */
-/* Is this a trap we never expect to get? */
-#define BAD_TRAP_P(level) \
- ((level > SP_TRAP_WDOG && level < SP_TRAP_IRQ1) || \
- (level > SP_TRAP_IACC && level < SP_TRAP_CPDIS) || \
- (level > SP_TRAP_BADFL && level < SP_TRAP_CPEXP) || \
- (level > SP_TRAP_DMM && level < SP_TRAP_IMM) || \
- (level > SP_TRAP_IMM && level < SP_TRAP_SUNOS) || \
- (level > SP_TRAP_LINUX && level < SP_TRAP_KBPT1))
-
-/* Is this a Hardware trap? */
-#define HW_TRAP_P(level) ((level > 0) && (level < SP_TRAP_SUNOS))
-
-/* Is this a Software trap? */
-#define SW_TRAP_P(level) ((level >= SP_TRAP_SUNOS) && (level <= SP_TRAP_KBPT2))
-
-/* Is this a system call for some OS we know about? */
-#define SCALL_TRAP_P(level) ((level == SP_TRAP_SUNOS) || \
- (level == SP_TRAP_SOLARIS) || \
- (level == SP_TRAP_NETBSD) || \
- (level == SP_TRAP_LINUX))
-
-#endif /* !(_SPARC_TRAPS_H) */
+++ /dev/null
-#ifndef _SPARC64_TSB_H
-#define _SPARC64_TSB_H
-
-/* The sparc64 TSB is similar to the powerpc hashtables. It's a
- * power-of-2 sized table of TAG/PTE pairs. The cpu precomputes
- * pointers into this table for 8K and 64K page sizes, and also a
- * comparison TAG based upon the virtual address and context which
- * faults.
- *
- * TLB miss trap handler software does the actual lookup via something
- * of the form:
- *
- * ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
- * ldxa [%g0] ASI_{D,I}MMU, %g6
- * sllx %g6, 22, %g6
- * srlx %g6, 22, %g6
- * ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4
- * cmp %g4, %g6
- * bne,pn %xcc, tsb_miss_{d,i}tlb
- * mov FAULT_CODE_{D,I}TLB, %g3
- * stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN
- * retry
- *
- *
- * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
- * PTE. The TAG is of the same layout as the TLB TAG TARGET mmu
- * register which is:
- *
- * -------------------------------------------------
- * | - | CONTEXT | - | VADDR bits 63:22 |
- * -------------------------------------------------
- * 63 61 60 48 47 42 41 0
- *
- * But actually, since we use per-mm TSB's, we zero out the CONTEXT
- * field.
- *
- * Like the powerpc hashtables we need to use locking in order to
- * synchronize while we update the entries. PTE updates need locking
- * as well.
- *
- * We need to carefully choose a lock bits for the TSB entry. We
- * choose to use bit 47 in the tag. Also, since we never map anything
- * at page zero in context zero, we use zero as an invalid tag entry.
- * When the lock bit is set, this forces a tag comparison failure.
- */
-
-#define TSB_TAG_LOCK_BIT 47
-#define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32))
-
-#define TSB_TAG_INVALID_BIT 46
-#define TSB_TAG_INVALID_HIGH (1 << (TSB_TAG_INVALID_BIT - 32))
-
-#define TSB_MEMBAR membar #StoreStore
-
-/* Some cpus support physical address quad loads. We want to use
- * those if possible so we don't need to hard-lock the TSB mapping
- * into the TLB. We encode some instruction patching in order to
- * support this.
- *
- * The kernel TSB is locked into the TLB by virtue of being in the
- * kernel image, so we don't play these games for swapper_tsb access.
- */
-#ifndef __ASSEMBLY__
-struct tsb_ldquad_phys_patch_entry {
- unsigned int addr;
- unsigned int sun4u_insn;
- unsigned int sun4v_insn;
-};
-extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
- __tsb_ldquad_phys_patch_end;
-
-struct tsb_phys_patch_entry {
- unsigned int addr;
- unsigned int insn;
-};
-extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
-#endif
-#define TSB_LOAD_QUAD(TSB, REG) \
-661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
- .section .tsb_ldquad_phys_patch, "ax"; \
- .word 661b; \
- ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
- ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
- .previous
-
-#define TSB_LOAD_TAG_HIGH(TSB, REG) \
-661: lduwa [TSB] ASI_N, REG; \
- .section .tsb_phys_patch, "ax"; \
- .word 661b; \
- lduwa [TSB] ASI_PHYS_USE_EC, REG; \
- .previous
-
-#define TSB_LOAD_TAG(TSB, REG) \
-661: ldxa [TSB] ASI_N, REG; \
- .section .tsb_phys_patch, "ax"; \
- .word 661b; \
- ldxa [TSB] ASI_PHYS_USE_EC, REG; \
- .previous
-
-#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
-661: casa [TSB] ASI_N, REG1, REG2; \
- .section .tsb_phys_patch, "ax"; \
- .word 661b; \
- casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
- .previous
-
-#define TSB_CAS_TAG(TSB, REG1, REG2) \
-661: casxa [TSB] ASI_N, REG1, REG2; \
- .section .tsb_phys_patch, "ax"; \
- .word 661b; \
- casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
- .previous
-
-#define TSB_STORE(ADDR, VAL) \
-661: stxa VAL, [ADDR] ASI_N; \
- .section .tsb_phys_patch, "ax"; \
- .word 661b; \
- stxa VAL, [ADDR] ASI_PHYS_USE_EC; \
- .previous
-
-#define TSB_LOCK_TAG(TSB, REG1, REG2) \
-99: TSB_LOAD_TAG_HIGH(TSB, REG1); \
- sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
- andcc REG1, REG2, %g0; \
- bne,pn %icc, 99b; \
- nop; \
- TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
- cmp REG1, REG2; \
- bne,pn %icc, 99b; \
- nop; \
- TSB_MEMBAR
-
-#define TSB_WRITE(TSB, TTE, TAG) \
- add TSB, 0x8, TSB; \
- TSB_STORE(TSB, TTE); \
- sub TSB, 0x8, TSB; \
- TSB_MEMBAR; \
- TSB_STORE(TSB, TAG);
-
-#define KTSB_LOAD_QUAD(TSB, REG) \
- ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG;
-
-#define KTSB_STORE(ADDR, VAL) \
- stxa VAL, [ADDR] ASI_N;
-
-#define KTSB_LOCK_TAG(TSB, REG1, REG2) \
-99: lduwa [TSB] ASI_N, REG1; \
- sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
- andcc REG1, REG2, %g0; \
- bne,pn %icc, 99b; \
- nop; \
- casa [TSB] ASI_N, REG1, REG2;\
- cmp REG1, REG2; \
- bne,pn %icc, 99b; \
- nop; \
- TSB_MEMBAR
-
-#define KTSB_WRITE(TSB, TTE, TAG) \
- add TSB, 0x8, TSB; \
- stxa TTE, [TSB] ASI_N; \
- sub TSB, 0x8, TSB; \
- TSB_MEMBAR; \
- stxa TAG, [TSB] ASI_N;
-
- /* Do a kernel page table walk. Leaves physical PTE pointer in
- * REG1. Jumps to FAIL_LABEL on early page table walk termination.
- * VADDR will not be clobbered, but REG2 will.
- */
-#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \
- sethi %hi(swapper_pg_dir), REG1; \
- or REG1, %lo(swapper_pg_dir), REG1; \
- sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
- srlx REG2, 64 - PAGE_SHIFT, REG2; \
- andn REG2, 0x3, REG2; \
- lduw [REG1 + REG2], REG1; \
- brz,pn REG1, FAIL_LABEL; \
- sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
- srlx REG2, 64 - PAGE_SHIFT, REG2; \
- sllx REG1, 11, REG1; \
- andn REG2, 0x3, REG2; \
- lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
- brz,pn REG1, FAIL_LABEL; \
- sllx VADDR, 64 - PMD_SHIFT, REG2; \
- srlx REG2, 64 - PAGE_SHIFT, REG2; \
- sllx REG1, 11, REG1; \
- andn REG2, 0x7, REG2; \
- add REG1, REG2, REG1;
-
- /* Do a user page table walk in MMU globals. Leaves physical PTE
- * pointer in REG1. Jumps to FAIL_LABEL on early page table walk
- * termination. Physical base of page tables is in PHYS_PGD which
- * will not be modified.
- *
- * VADDR will not be clobbered, but REG1 and REG2 will.
- */
-#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \
- sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
- srlx REG2, 64 - PAGE_SHIFT, REG2; \
- andn REG2, 0x3, REG2; \
- lduwa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
- brz,pn REG1, FAIL_LABEL; \
- sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
- srlx REG2, 64 - PAGE_SHIFT, REG2; \
- sllx REG1, 11, REG1; \
- andn REG2, 0x3, REG2; \
- lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
- brz,pn REG1, FAIL_LABEL; \
- sllx VADDR, 64 - PMD_SHIFT, REG2; \
- srlx REG2, 64 - PAGE_SHIFT, REG2; \
- sllx REG1, 11, REG1; \
- andn REG2, 0x7, REG2; \
- add REG1, REG2, REG1;
-
-/* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0.
- * If no entry is found, FAIL_LABEL will be branched to. On success
- * the resulting PTE value will be left in REG1. VADDR is preserved
- * by this routine.
- */
-#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
- sethi %hi(prom_trans), REG1; \
- or REG1, %lo(prom_trans), REG1; \
-97: ldx [REG1 + 0x00], REG2; \
- brz,pn REG2, FAIL_LABEL; \
- nop; \
- ldx [REG1 + 0x08], REG3; \
- add REG2, REG3, REG3; \
- cmp REG2, VADDR; \
- bgu,pt %xcc, 98f; \
- cmp VADDR, REG3; \
- bgeu,pt %xcc, 98f; \
- ldx [REG1 + 0x10], REG3; \
- sub VADDR, REG2, REG2; \
- ba,pt %xcc, 99f; \
- add REG3, REG2, REG1; \
-98: ba,pt %xcc, 97b; \
- add REG1, (3 * 8), REG1; \
-99:
-
- /* We use a 32K TSB for the whole kernel, this allows to
- * handle about 16MB of modules and vmalloc mappings without
- * incurring many hash conflicts.
- */
-#define KERNEL_TSB_SIZE_BYTES (32 * 1024)
-#define KERNEL_TSB_NENTRIES \
- (KERNEL_TSB_SIZE_BYTES / 16)
-#define KERNEL_TSB4M_NENTRIES 4096
-
- /* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL
- * on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries
- * and the found TTE will be left in REG1. REG3 and REG4 must
- * be an even/odd pair of registers.
- *
- * VADDR and TAG will be preserved and not clobbered by this macro.
- */
-#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
- sethi %hi(swapper_tsb), REG1; \
- or REG1, %lo(swapper_tsb), REG1; \
- srlx VADDR, PAGE_SHIFT, REG2; \
- and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
- sllx REG2, 4, REG2; \
- add REG1, REG2, REG2; \
- KTSB_LOAD_QUAD(REG2, REG3); \
- cmp REG3, TAG; \
- be,a,pt %xcc, OK_LABEL; \
- mov REG4, REG1;
-
-#ifndef CONFIG_DEBUG_PAGEALLOC
- /* This version uses a trick, the TAG is already (VADDR >> 22) so
- * we can make use of that for the index computation.
- */
-#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
- sethi %hi(swapper_4m_tsb), REG1; \
- or REG1, %lo(swapper_4m_tsb), REG1; \
- and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
- sllx REG2, 4, REG2; \
- add REG1, REG2, REG2; \
- KTSB_LOAD_QUAD(REG2, REG3); \
- cmp REG3, TAG; \
- be,a,pt %xcc, OK_LABEL; \
- mov REG4, REG1;
-#endif
-
-#endif /* !(_SPARC64_TSB_H) */
+++ /dev/null
-/*
- * tsunami.h: Module specific definitions for Tsunami V8 Sparcs
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_TSUNAMI_H
-#define _SPARC_TSUNAMI_H
-
-#include <asm/asi.h>
-
-/* The MMU control register on the Tsunami:
- *
- * -----------------------------------------------------------------------
- * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME|
- * -----------------------------------------------------------------------
- * 31 24 23 22 21 20 19-18 17 16 14 13-12 11 10-9 8 7 6-2 1 0
- *
- * SW: Enable Software Table Walks 0=off 1=on
- * AV: Address View bit
- * DV: Data View bit
- * MV: Memory View bit
- * PC: Parity Control
- * ITD: ITBR disable
- * ALC: Alternate Cacheable
- * PE: Parity Enable 0=off 1=on
- * RC: Refresh Control
- * IE: Instruction cache Enable 0=off 1=on
- * DE: Data cache Enable 0=off 1=on
- * NF: No Fault, same as all other SRMMUs
- * ME: MMU Enable, same as all other SRMMUs
- */
-
-#define TSUNAMI_SW 0x00800000
-#define TSUNAMI_AV 0x00400000
-#define TSUNAMI_DV 0x00200000
-#define TSUNAMI_MV 0x00100000
-#define TSUNAMI_PC 0x00020000
-#define TSUNAMI_ITD 0x00010000
-#define TSUNAMI_ALC 0x00008000
-#define TSUNAMI_PE 0x00001000
-#define TSUNAMI_RCMASK 0x00000C00
-#define TSUNAMI_IENAB 0x00000200
-#define TSUNAMI_DENAB 0x00000100
-#define TSUNAMI_NF 0x00000002
-#define TSUNAMI_ME 0x00000001
-
-static inline void tsunami_flush_icache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_IC_FLCLEAR)
- : "memory");
-}
-
-static inline void tsunami_flush_dcache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_DC_FLCLEAR)
- : "memory");
-}
-
-#endif /* !(_SPARC_TSUNAMI_H) */
+++ /dev/null
-#ifndef _SPARC64_TTABLE_H
-#define _SPARC64_TTABLE_H
-
-#include <asm/utrap.h>
-
-#ifdef __ASSEMBLY__
-#include <asm/thread_info.h>
-#endif
-
-#define BOOT_KERNEL b sparc64_boot; nop; nop; nop; nop; nop; nop; nop;
-
-/* We need a "cleaned" instruction... */
-#define CLEAN_WINDOW \
- rdpr %cleanwin, %l0; add %l0, 1, %l0; \
- wrpr %l0, 0x0, %cleanwin; \
- clr %o0; clr %o1; clr %o2; clr %o3; \
- clr %o4; clr %o5; clr %o6; clr %o7; \
- clr %l0; clr %l1; clr %l2; clr %l3; \
- clr %l4; clr %l5; clr %l6; clr %l7; \
- retry; \
- nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
-
-#define TRAP(routine) \
- sethi %hi(109f), %g7; \
- ba,pt %xcc, etrap; \
-109: or %g7, %lo(109b), %g7; \
- call routine; \
- add %sp, PTREGS_OFF, %o0; \
- ba,pt %xcc, rtrap; \
- nop; \
- nop;
-
-#define TRAP_7INSNS(routine) \
- sethi %hi(109f), %g7; \
- ba,pt %xcc, etrap; \
-109: or %g7, %lo(109b), %g7; \
- call routine; \
- add %sp, PTREGS_OFF, %o0; \
- ba,pt %xcc, rtrap; \
- nop;
-
-#define TRAP_SAVEFPU(routine) \
- sethi %hi(109f), %g7; \
- ba,pt %xcc, do_fptrap; \
-109: or %g7, %lo(109b), %g7; \
- call routine; \
- add %sp, PTREGS_OFF, %o0; \
- ba,pt %xcc, rtrap; \
- nop; \
- nop;
-
-#define TRAP_NOSAVE(routine) \
- ba,pt %xcc, routine; \
- nop; \
- nop; nop; nop; nop; nop; nop;
-
-#define TRAP_NOSAVE_7INSNS(routine) \
- ba,pt %xcc, routine; \
- nop; \
- nop; nop; nop; nop; nop;
-
-#define TRAPTL1(routine) \
- sethi %hi(109f), %g7; \
- ba,pt %xcc, etraptl1; \
-109: or %g7, %lo(109b), %g7; \
- call routine; \
- add %sp, PTREGS_OFF, %o0; \
- ba,pt %xcc, rtrap; \
- nop; \
- nop;
-
-#define TRAP_ARG(routine, arg) \
- sethi %hi(109f), %g7; \
- ba,pt %xcc, etrap; \
-109: or %g7, %lo(109b), %g7; \
- add %sp, PTREGS_OFF, %o0; \
- call routine; \
- mov arg, %o1; \
- ba,pt %xcc, rtrap; \
- nop;
-
-#define TRAPTL1_ARG(routine, arg) \
- sethi %hi(109f), %g7; \
- ba,pt %xcc, etraptl1; \
-109: or %g7, %lo(109b), %g7; \
- add %sp, PTREGS_OFF, %o0; \
- call routine; \
- mov arg, %o1; \
- ba,pt %xcc, rtrap; \
- nop;
-
-#define SYSCALL_TRAP(routine, systbl) \
- rdpr %pil, %g2; \
- mov TSTATE_SYSCALL, %g3; \
- sethi %hi(109f), %g7; \
- ba,pt %xcc, etrap_syscall; \
-109: or %g7, %lo(109b), %g7; \
- sethi %hi(systbl), %l7; \
- ba,pt %xcc, routine; \
- or %l7, %lo(systbl), %l7;
-
-#define TRAP_UTRAP(handler,lvl) \
- mov handler, %g3; \
- ba,pt %xcc, utrap_trap; \
- mov lvl, %g4; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop;
-
-#ifdef CONFIG_COMPAT
-#define LINUX_32BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall32, sys_call_table32)
-#else
-#define LINUX_32BIT_SYSCALL_TRAP BTRAP(0x110)
-#endif
-#define LINUX_64BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall, sys_call_table64)
-#define GETCC_TRAP TRAP(getcc)
-#define SETCC_TRAP TRAP(setcc)
-#define BREAKPOINT_TRAP TRAP(breakpoint_trap)
-
-#ifdef CONFIG_TRACE_IRQFLAGS
-
-#define TRAP_IRQ(routine, level) \
- rdpr %pil, %g2; \
- wrpr %g0, 15, %pil; \
- sethi %hi(1f-4), %g7; \
- ba,pt %xcc, etrap_irq; \
- or %g7, %lo(1f-4), %g7; \
- nop; \
- nop; \
- nop; \
- .subsection 2; \
-1: call trace_hardirqs_off; \
- nop; \
- mov level, %o0; \
- call routine; \
- add %sp, PTREGS_OFF, %o1; \
- ba,a,pt %xcc, rtrap_irq; \
- .previous;
-
-#else
-
-#define TRAP_IRQ(routine, level) \
- rdpr %pil, %g2; \
- wrpr %g0, 15, %pil; \
- ba,pt %xcc, etrap_irq; \
- rd %pc, %g7; \
- mov level, %o0; \
- call routine; \
- add %sp, PTREGS_OFF, %o1; \
- ba,a,pt %xcc, rtrap_irq;
-
-#endif
-
-#define TRAP_IVEC TRAP_NOSAVE(do_ivec)
-
-#define BTRAP(lvl) TRAP_ARG(bad_trap, lvl)
-
-#define BTRAPTL1(lvl) TRAPTL1_ARG(bad_trap_tl1, lvl)
-
-#define FLUSH_WINDOW_TRAP \
- ba,pt %xcc, etrap; \
- rd %pc, %g7; \
- flushw; \
- ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1; \
- add %l1, 4, %l2; \
- stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]; \
- ba,pt %xcc, rtrap; \
- stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC];
-
-#ifdef CONFIG_KPROBES
-#define KPROBES_TRAP(lvl) TRAP_IRQ(kprobe_trap, lvl)
-#else
-#define KPROBES_TRAP(lvl) TRAP_ARG(bad_trap, lvl)
-#endif
-
-#ifdef CONFIG_KGDB
-#define KGDB_TRAP(lvl) TRAP_IRQ(kgdb_trap, lvl)
-#else
-#define KGDB_TRAP(lvl) TRAP_ARG(bad_trap, lvl)
-#endif
-
-#define SUN4V_ITSB_MISS \
- ldxa [%g0] ASI_SCRATCHPAD, %g2; \
- ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4; \
- ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5; \
- srlx %g4, 22, %g6; \
- ba,pt %xcc, sun4v_itsb_miss; \
- nop; \
- nop; \
- nop;
-
-#define SUN4V_DTSB_MISS \
- ldxa [%g0] ASI_SCRATCHPAD, %g2; \
- ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4; \
- ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5; \
- srlx %g4, 22, %g6; \
- ba,pt %xcc, sun4v_dtsb_miss; \
- nop; \
- nop; \
- nop;
-
-/* Before touching these macros, you owe it to yourself to go and
- * see how arch/sparc64/kernel/winfixup.S works... -DaveM
- *
- * For the user cases we used to use the %asi register, but
- * it turns out that the "wr xxx, %asi" costs ~5 cycles, so
- * now we use immediate ASI loads and stores instead. Kudos
- * to Greg Onufer for pointing out this performance anomaly.
- *
- * Further note that we cannot use the g2, g4, g5, and g7 alternate
- * globals in the spill routines, check out the save instruction in
- * arch/sparc64/kernel/etrap.S to see what I mean about g2, and
- * g4/g5 are the globals which are preserved by etrap processing
- * for the caller of it. The g7 register is the return pc for
- * etrap. Finally, g6 is the current thread register so we cannot
- * us it in the spill handlers either. Most of these rules do not
- * apply to fill processing, only g6 is not usable.
- */
-
-/* Normal kernel spill */
-#define SPILL_0_NORMAL \
- stx %l0, [%sp + STACK_BIAS + 0x00]; \
- stx %l1, [%sp + STACK_BIAS + 0x08]; \
- stx %l2, [%sp + STACK_BIAS + 0x10]; \
- stx %l3, [%sp + STACK_BIAS + 0x18]; \
- stx %l4, [%sp + STACK_BIAS + 0x20]; \
- stx %l5, [%sp + STACK_BIAS + 0x28]; \
- stx %l6, [%sp + STACK_BIAS + 0x30]; \
- stx %l7, [%sp + STACK_BIAS + 0x38]; \
- stx %i0, [%sp + STACK_BIAS + 0x40]; \
- stx %i1, [%sp + STACK_BIAS + 0x48]; \
- stx %i2, [%sp + STACK_BIAS + 0x50]; \
- stx %i3, [%sp + STACK_BIAS + 0x58]; \
- stx %i4, [%sp + STACK_BIAS + 0x60]; \
- stx %i5, [%sp + STACK_BIAS + 0x68]; \
- stx %i6, [%sp + STACK_BIAS + 0x70]; \
- stx %i7, [%sp + STACK_BIAS + 0x78]; \
- saved; retry; nop; nop; nop; nop; nop; nop; \
- nop; nop; nop; nop; nop; nop; nop; nop;
-
-#define SPILL_0_NORMAL_ETRAP \
-etrap_kernel_spill: \
- stx %l0, [%sp + STACK_BIAS + 0x00]; \
- stx %l1, [%sp + STACK_BIAS + 0x08]; \
- stx %l2, [%sp + STACK_BIAS + 0x10]; \
- stx %l3, [%sp + STACK_BIAS + 0x18]; \
- stx %l4, [%sp + STACK_BIAS + 0x20]; \
- stx %l5, [%sp + STACK_BIAS + 0x28]; \
- stx %l6, [%sp + STACK_BIAS + 0x30]; \
- stx %l7, [%sp + STACK_BIAS + 0x38]; \
- stx %i0, [%sp + STACK_BIAS + 0x40]; \
- stx %i1, [%sp + STACK_BIAS + 0x48]; \
- stx %i2, [%sp + STACK_BIAS + 0x50]; \
- stx %i3, [%sp + STACK_BIAS + 0x58]; \
- stx %i4, [%sp + STACK_BIAS + 0x60]; \
- stx %i5, [%sp + STACK_BIAS + 0x68]; \
- stx %i6, [%sp + STACK_BIAS + 0x70]; \
- stx %i7, [%sp + STACK_BIAS + 0x78]; \
- saved; \
- sub %g1, 2, %g1; \
- ba,pt %xcc, etrap_save; \
- wrpr %g1, %cwp; \
- nop; nop; nop; nop; nop; nop; nop; nop; \
- nop; nop; nop; nop;
-
-/* Normal 64bit spill */
-#define SPILL_1_GENERIC(ASI) \
- add %sp, STACK_BIAS + 0x00, %g1; \
- stxa %l0, [%g1 + %g0] ASI; \
- mov 0x08, %g3; \
- stxa %l1, [%g1 + %g3] ASI; \
- add %g1, 0x10, %g1; \
- stxa %l2, [%g1 + %g0] ASI; \
- stxa %l3, [%g1 + %g3] ASI; \
- add %g1, 0x10, %g1; \
- stxa %l4, [%g1 + %g0] ASI; \
- stxa %l5, [%g1 + %g3] ASI; \
- add %g1, 0x10, %g1; \
- stxa %l6, [%g1 + %g0] ASI; \
- stxa %l7, [%g1 + %g3] ASI; \
- add %g1, 0x10, %g1; \
- stxa %i0, [%g1 + %g0] ASI; \
- stxa %i1, [%g1 + %g3] ASI; \
- add %g1, 0x10, %g1; \
- stxa %i2, [%g1 + %g0] ASI; \
- stxa %i3, [%g1 + %g3] ASI; \
- add %g1, 0x10, %g1; \
- stxa %i4, [%g1 + %g0] ASI; \
- stxa %i5, [%g1 + %g3] ASI; \
- add %g1, 0x10, %g1; \
- stxa %i6, [%g1 + %g0] ASI; \
- stxa %i7, [%g1 + %g3] ASI; \
- saved; \
- retry; nop; nop; \
- b,a,pt %xcc, spill_fixup_dax; \
- b,a,pt %xcc, spill_fixup_mna; \
- b,a,pt %xcc, spill_fixup;
-
-#define SPILL_1_GENERIC_ETRAP \
-etrap_user_spill_64bit: \
- stxa %l0, [%sp + STACK_BIAS + 0x00] %asi; \
- stxa %l1, [%sp + STACK_BIAS + 0x08] %asi; \
- stxa %l2, [%sp + STACK_BIAS + 0x10] %asi; \
- stxa %l3, [%sp + STACK_BIAS + 0x18] %asi; \
- stxa %l4, [%sp + STACK_BIAS + 0x20] %asi; \
- stxa %l5, [%sp + STACK_BIAS + 0x28] %asi; \
- stxa %l6, [%sp + STACK_BIAS + 0x30] %asi; \
- stxa %l7, [%sp + STACK_BIAS + 0x38] %asi; \
- stxa %i0, [%sp + STACK_BIAS + 0x40] %asi; \
- stxa %i1, [%sp + STACK_BIAS + 0x48] %asi; \
- stxa %i2, [%sp + STACK_BIAS + 0x50] %asi; \
- stxa %i3, [%sp + STACK_BIAS + 0x58] %asi; \
- stxa %i4, [%sp + STACK_BIAS + 0x60] %asi; \
- stxa %i5, [%sp + STACK_BIAS + 0x68] %asi; \
- stxa %i6, [%sp + STACK_BIAS + 0x70] %asi; \
- stxa %i7, [%sp + STACK_BIAS + 0x78] %asi; \
- saved; \
- sub %g1, 2, %g1; \
- ba,pt %xcc, etrap_save; \
- wrpr %g1, %cwp; \
- nop; nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- ba,a,pt %xcc, etrap_spill_fixup_64bit; \
- ba,a,pt %xcc, etrap_spill_fixup_64bit; \
- ba,a,pt %xcc, etrap_spill_fixup_64bit;
-
-#define SPILL_1_GENERIC_ETRAP_FIXUP \
-etrap_spill_fixup_64bit: \
- ldub [%g6 + TI_WSAVED], %g1; \
- sll %g1, 3, %g3; \
- add %g6, %g3, %g3; \
- stx %sp, [%g3 + TI_RWIN_SPTRS]; \
- sll %g1, 7, %g3; \
- add %g6, %g3, %g3; \
- stx %l0, [%g3 + TI_REG_WINDOW + 0x00]; \
- stx %l1, [%g3 + TI_REG_WINDOW + 0x08]; \
- stx %l2, [%g3 + TI_REG_WINDOW + 0x10]; \
- stx %l3, [%g3 + TI_REG_WINDOW + 0x18]; \
- stx %l4, [%g3 + TI_REG_WINDOW + 0x20]; \
- stx %l5, [%g3 + TI_REG_WINDOW + 0x28]; \
- stx %l6, [%g3 + TI_REG_WINDOW + 0x30]; \
- stx %l7, [%g3 + TI_REG_WINDOW + 0x38]; \
- stx %i0, [%g3 + TI_REG_WINDOW + 0x40]; \
- stx %i1, [%g3 + TI_REG_WINDOW + 0x48]; \
- stx %i2, [%g3 + TI_REG_WINDOW + 0x50]; \
- stx %i3, [%g3 + TI_REG_WINDOW + 0x58]; \
- stx %i4, [%g3 + TI_REG_WINDOW + 0x60]; \
- stx %i5, [%g3 + TI_REG_WINDOW + 0x68]; \
- stx %i6, [%g3 + TI_REG_WINDOW + 0x70]; \
- stx %i7, [%g3 + TI_REG_WINDOW + 0x78]; \
- add %g1, 1, %g1; \
- stb %g1, [%g6 + TI_WSAVED]; \
- saved; \
- rdpr %cwp, %g1; \
- sub %g1, 2, %g1; \
- ba,pt %xcc, etrap_save; \
- wrpr %g1, %cwp; \
- nop; nop; nop
-
-/* Normal 32bit spill */
-#define SPILL_2_GENERIC(ASI) \
- srl %sp, 0, %sp; \
- stwa %l0, [%sp + %g0] ASI; \
- mov 0x04, %g3; \
- stwa %l1, [%sp + %g3] ASI; \
- add %sp, 0x08, %g1; \
- stwa %l2, [%g1 + %g0] ASI; \
- stwa %l3, [%g1 + %g3] ASI; \
- add %g1, 0x08, %g1; \
- stwa %l4, [%g1 + %g0] ASI; \
- stwa %l5, [%g1 + %g3] ASI; \
- add %g1, 0x08, %g1; \
- stwa %l6, [%g1 + %g0] ASI; \
- stwa %l7, [%g1 + %g3] ASI; \
- add %g1, 0x08, %g1; \
- stwa %i0, [%g1 + %g0] ASI; \
- stwa %i1, [%g1 + %g3] ASI; \
- add %g1, 0x08, %g1; \
- stwa %i2, [%g1 + %g0] ASI; \
- stwa %i3, [%g1 + %g3] ASI; \
- add %g1, 0x08, %g1; \
- stwa %i4, [%g1 + %g0] ASI; \
- stwa %i5, [%g1 + %g3] ASI; \
- add %g1, 0x08, %g1; \
- stwa %i6, [%g1 + %g0] ASI; \
- stwa %i7, [%g1 + %g3] ASI; \
- saved; \
- retry; nop; nop; \
- b,a,pt %xcc, spill_fixup_dax; \
- b,a,pt %xcc, spill_fixup_mna; \
- b,a,pt %xcc, spill_fixup;
-
-#define SPILL_2_GENERIC_ETRAP \
-etrap_user_spill_32bit: \
- srl %sp, 0, %sp; \
- stwa %l0, [%sp + 0x00] %asi; \
- stwa %l1, [%sp + 0x04] %asi; \
- stwa %l2, [%sp + 0x08] %asi; \
- stwa %l3, [%sp + 0x0c] %asi; \
- stwa %l4, [%sp + 0x10] %asi; \
- stwa %l5, [%sp + 0x14] %asi; \
- stwa %l6, [%sp + 0x18] %asi; \
- stwa %l7, [%sp + 0x1c] %asi; \
- stwa %i0, [%sp + 0x20] %asi; \
- stwa %i1, [%sp + 0x24] %asi; \
- stwa %i2, [%sp + 0x28] %asi; \
- stwa %i3, [%sp + 0x2c] %asi; \
- stwa %i4, [%sp + 0x30] %asi; \
- stwa %i5, [%sp + 0x34] %asi; \
- stwa %i6, [%sp + 0x38] %asi; \
- stwa %i7, [%sp + 0x3c] %asi; \
- saved; \
- sub %g1, 2, %g1; \
- ba,pt %xcc, etrap_save; \
- wrpr %g1, %cwp; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- ba,a,pt %xcc, etrap_spill_fixup_32bit; \
- ba,a,pt %xcc, etrap_spill_fixup_32bit; \
- ba,a,pt %xcc, etrap_spill_fixup_32bit;
-
-#define SPILL_2_GENERIC_ETRAP_FIXUP \
-etrap_spill_fixup_32bit: \
- ldub [%g6 + TI_WSAVED], %g1; \
- sll %g1, 3, %g3; \
- add %g6, %g3, %g3; \
- stx %sp, [%g3 + TI_RWIN_SPTRS]; \
- sll %g1, 7, %g3; \
- add %g6, %g3, %g3; \
- stw %l0, [%g3 + TI_REG_WINDOW + 0x00]; \
- stw %l1, [%g3 + TI_REG_WINDOW + 0x04]; \
- stw %l2, [%g3 + TI_REG_WINDOW + 0x08]; \
- stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]; \
- stw %l4, [%g3 + TI_REG_WINDOW + 0x10]; \
- stw %l5, [%g3 + TI_REG_WINDOW + 0x14]; \
- stw %l6, [%g3 + TI_REG_WINDOW + 0x18]; \
- stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]; \
- stw %i0, [%g3 + TI_REG_WINDOW + 0x20]; \
- stw %i1, [%g3 + TI_REG_WINDOW + 0x24]; \
- stw %i2, [%g3 + TI_REG_WINDOW + 0x28]; \
- stw %i3, [%g3 + TI_REG_WINDOW + 0x2c]; \
- stw %i4, [%g3 + TI_REG_WINDOW + 0x30]; \
- stw %i5, [%g3 + TI_REG_WINDOW + 0x34]; \
- stw %i6, [%g3 + TI_REG_WINDOW + 0x38]; \
- stw %i7, [%g3 + TI_REG_WINDOW + 0x3c]; \
- add %g1, 1, %g1; \
- stb %g1, [%g6 + TI_WSAVED]; \
- saved; \
- rdpr %cwp, %g1; \
- sub %g1, 2, %g1; \
- ba,pt %xcc, etrap_save; \
- wrpr %g1, %cwp; \
- nop; nop; nop
-
-#define SPILL_1_NORMAL SPILL_1_GENERIC(ASI_AIUP)
-#define SPILL_2_NORMAL SPILL_2_GENERIC(ASI_AIUP)
-#define SPILL_3_NORMAL SPILL_0_NORMAL
-#define SPILL_4_NORMAL SPILL_0_NORMAL
-#define SPILL_5_NORMAL SPILL_0_NORMAL
-#define SPILL_6_NORMAL SPILL_0_NORMAL
-#define SPILL_7_NORMAL SPILL_0_NORMAL
-
-#define SPILL_0_OTHER SPILL_0_NORMAL
-#define SPILL_1_OTHER SPILL_1_GENERIC(ASI_AIUS)
-#define SPILL_2_OTHER SPILL_2_GENERIC(ASI_AIUS)
-#define SPILL_3_OTHER SPILL_3_NORMAL
-#define SPILL_4_OTHER SPILL_4_NORMAL
-#define SPILL_5_OTHER SPILL_5_NORMAL
-#define SPILL_6_OTHER SPILL_6_NORMAL
-#define SPILL_7_OTHER SPILL_7_NORMAL
-
-/* Normal kernel fill */
-#define FILL_0_NORMAL \
- ldx [%sp + STACK_BIAS + 0x00], %l0; \
- ldx [%sp + STACK_BIAS + 0x08], %l1; \
- ldx [%sp + STACK_BIAS + 0x10], %l2; \
- ldx [%sp + STACK_BIAS + 0x18], %l3; \
- ldx [%sp + STACK_BIAS + 0x20], %l4; \
- ldx [%sp + STACK_BIAS + 0x28], %l5; \
- ldx [%sp + STACK_BIAS + 0x30], %l6; \
- ldx [%sp + STACK_BIAS + 0x38], %l7; \
- ldx [%sp + STACK_BIAS + 0x40], %i0; \
- ldx [%sp + STACK_BIAS + 0x48], %i1; \
- ldx [%sp + STACK_BIAS + 0x50], %i2; \
- ldx [%sp + STACK_BIAS + 0x58], %i3; \
- ldx [%sp + STACK_BIAS + 0x60], %i4; \
- ldx [%sp + STACK_BIAS + 0x68], %i5; \
- ldx [%sp + STACK_BIAS + 0x70], %i6; \
- ldx [%sp + STACK_BIAS + 0x78], %i7; \
- restored; retry; nop; nop; nop; nop; nop; nop; \
- nop; nop; nop; nop; nop; nop; nop; nop;
-
-#define FILL_0_NORMAL_RTRAP \
-kern_rtt_fill: \
- rdpr %cwp, %g1; \
- sub %g1, 1, %g1; \
- wrpr %g1, %cwp; \
- ldx [%sp + STACK_BIAS + 0x00], %l0; \
- ldx [%sp + STACK_BIAS + 0x08], %l1; \
- ldx [%sp + STACK_BIAS + 0x10], %l2; \
- ldx [%sp + STACK_BIAS + 0x18], %l3; \
- ldx [%sp + STACK_BIAS + 0x20], %l4; \
- ldx [%sp + STACK_BIAS + 0x28], %l5; \
- ldx [%sp + STACK_BIAS + 0x30], %l6; \
- ldx [%sp + STACK_BIAS + 0x38], %l7; \
- ldx [%sp + STACK_BIAS + 0x40], %i0; \
- ldx [%sp + STACK_BIAS + 0x48], %i1; \
- ldx [%sp + STACK_BIAS + 0x50], %i2; \
- ldx [%sp + STACK_BIAS + 0x58], %i3; \
- ldx [%sp + STACK_BIAS + 0x60], %i4; \
- ldx [%sp + STACK_BIAS + 0x68], %i5; \
- ldx [%sp + STACK_BIAS + 0x70], %i6; \
- ldx [%sp + STACK_BIAS + 0x78], %i7; \
- restored; \
- add %g1, 1, %g1; \
- ba,pt %xcc, kern_rtt_restore; \
- wrpr %g1, %cwp; \
- nop; nop; nop; nop; nop; \
- nop; nop; nop; nop;
-
-
-/* Normal 64bit fill */
-#define FILL_1_GENERIC(ASI) \
- add %sp, STACK_BIAS + 0x00, %g1; \
- ldxa [%g1 + %g0] ASI, %l0; \
- mov 0x08, %g2; \
- mov 0x10, %g3; \
- ldxa [%g1 + %g2] ASI, %l1; \
- mov 0x18, %g5; \
- ldxa [%g1 + %g3] ASI, %l2; \
- ldxa [%g1 + %g5] ASI, %l3; \
- add %g1, 0x20, %g1; \
- ldxa [%g1 + %g0] ASI, %l4; \
- ldxa [%g1 + %g2] ASI, %l5; \
- ldxa [%g1 + %g3] ASI, %l6; \
- ldxa [%g1 + %g5] ASI, %l7; \
- add %g1, 0x20, %g1; \
- ldxa [%g1 + %g0] ASI, %i0; \
- ldxa [%g1 + %g2] ASI, %i1; \
- ldxa [%g1 + %g3] ASI, %i2; \
- ldxa [%g1 + %g5] ASI, %i3; \
- add %g1, 0x20, %g1; \
- ldxa [%g1 + %g0] ASI, %i4; \
- ldxa [%g1 + %g2] ASI, %i5; \
- ldxa [%g1 + %g3] ASI, %i6; \
- ldxa [%g1 + %g5] ASI, %i7; \
- restored; \
- retry; nop; nop; nop; nop; \
- b,a,pt %xcc, fill_fixup_dax; \
- b,a,pt %xcc, fill_fixup_mna; \
- b,a,pt %xcc, fill_fixup;
-
-#define FILL_1_GENERIC_RTRAP \
-user_rtt_fill_64bit: \
- ldxa [%sp + STACK_BIAS + 0x00] %asi, %l0; \
- ldxa [%sp + STACK_BIAS + 0x08] %asi, %l1; \
- ldxa [%sp + STACK_BIAS + 0x10] %asi, %l2; \
- ldxa [%sp + STACK_BIAS + 0x18] %asi, %l3; \
- ldxa [%sp + STACK_BIAS + 0x20] %asi, %l4; \
- ldxa [%sp + STACK_BIAS + 0x28] %asi, %l5; \
- ldxa [%sp + STACK_BIAS + 0x30] %asi, %l6; \
- ldxa [%sp + STACK_BIAS + 0x38] %asi, %l7; \
- ldxa [%sp + STACK_BIAS + 0x40] %asi, %i0; \
- ldxa [%sp + STACK_BIAS + 0x48] %asi, %i1; \
- ldxa [%sp + STACK_BIAS + 0x50] %asi, %i2; \
- ldxa [%sp + STACK_BIAS + 0x58] %asi, %i3; \
- ldxa [%sp + STACK_BIAS + 0x60] %asi, %i4; \
- ldxa [%sp + STACK_BIAS + 0x68] %asi, %i5; \
- ldxa [%sp + STACK_BIAS + 0x70] %asi, %i6; \
- ldxa [%sp + STACK_BIAS + 0x78] %asi, %i7; \
- ba,pt %xcc, user_rtt_pre_restore; \
- restored; \
- nop; nop; nop; nop; nop; nop; \
- nop; nop; nop; nop; nop; \
- ba,a,pt %xcc, user_rtt_fill_fixup; \
- ba,a,pt %xcc, user_rtt_fill_fixup; \
- ba,a,pt %xcc, user_rtt_fill_fixup;
-
-
-/* Normal 32bit fill */
-#define FILL_2_GENERIC(ASI) \
- srl %sp, 0, %sp; \
- lduwa [%sp + %g0] ASI, %l0; \
- mov 0x04, %g2; \
- mov 0x08, %g3; \
- lduwa [%sp + %g2] ASI, %l1; \
- mov 0x0c, %g5; \
- lduwa [%sp + %g3] ASI, %l2; \
- lduwa [%sp + %g5] ASI, %l3; \
- add %sp, 0x10, %g1; \
- lduwa [%g1 + %g0] ASI, %l4; \
- lduwa [%g1 + %g2] ASI, %l5; \
- lduwa [%g1 + %g3] ASI, %l6; \
- lduwa [%g1 + %g5] ASI, %l7; \
- add %g1, 0x10, %g1; \
- lduwa [%g1 + %g0] ASI, %i0; \
- lduwa [%g1 + %g2] ASI, %i1; \
- lduwa [%g1 + %g3] ASI, %i2; \
- lduwa [%g1 + %g5] ASI, %i3; \
- add %g1, 0x10, %g1; \
- lduwa [%g1 + %g0] ASI, %i4; \
- lduwa [%g1 + %g2] ASI, %i5; \
- lduwa [%g1 + %g3] ASI, %i6; \
- lduwa [%g1 + %g5] ASI, %i7; \
- restored; \
- retry; nop; nop; nop; nop; \
- b,a,pt %xcc, fill_fixup_dax; \
- b,a,pt %xcc, fill_fixup_mna; \
- b,a,pt %xcc, fill_fixup;
-
-#define FILL_2_GENERIC_RTRAP \
-user_rtt_fill_32bit: \
- srl %sp, 0, %sp; \
- lduwa [%sp + 0x00] %asi, %l0; \
- lduwa [%sp + 0x04] %asi, %l1; \
- lduwa [%sp + 0x08] %asi, %l2; \
- lduwa [%sp + 0x0c] %asi, %l3; \
- lduwa [%sp + 0x10] %asi, %l4; \
- lduwa [%sp + 0x14] %asi, %l5; \
- lduwa [%sp + 0x18] %asi, %l6; \
- lduwa [%sp + 0x1c] %asi, %l7; \
- lduwa [%sp + 0x20] %asi, %i0; \
- lduwa [%sp + 0x24] %asi, %i1; \
- lduwa [%sp + 0x28] %asi, %i2; \
- lduwa [%sp + 0x2c] %asi, %i3; \
- lduwa [%sp + 0x30] %asi, %i4; \
- lduwa [%sp + 0x34] %asi, %i5; \
- lduwa [%sp + 0x38] %asi, %i6; \
- lduwa [%sp + 0x3c] %asi, %i7; \
- ba,pt %xcc, user_rtt_pre_restore; \
- restored; \
- nop; nop; nop; nop; nop; \
- nop; nop; nop; nop; nop; \
- ba,a,pt %xcc, user_rtt_fill_fixup; \
- ba,a,pt %xcc, user_rtt_fill_fixup; \
- ba,a,pt %xcc, user_rtt_fill_fixup;
-
-
-#define FILL_1_NORMAL FILL_1_GENERIC(ASI_AIUP)
-#define FILL_2_NORMAL FILL_2_GENERIC(ASI_AIUP)
-#define FILL_3_NORMAL FILL_0_NORMAL
-#define FILL_4_NORMAL FILL_0_NORMAL
-#define FILL_5_NORMAL FILL_0_NORMAL
-#define FILL_6_NORMAL FILL_0_NORMAL
-#define FILL_7_NORMAL FILL_0_NORMAL
-
-#define FILL_0_OTHER FILL_0_NORMAL
-#define FILL_1_OTHER FILL_1_GENERIC(ASI_AIUS)
-#define FILL_2_OTHER FILL_2_GENERIC(ASI_AIUS)
-#define FILL_3_OTHER FILL_3_NORMAL
-#define FILL_4_OTHER FILL_4_NORMAL
-#define FILL_5_OTHER FILL_5_NORMAL
-#define FILL_6_OTHER FILL_6_NORMAL
-#define FILL_7_OTHER FILL_7_NORMAL
-
-#endif /* !(_SPARC64_TTABLE_H) */
+++ /dev/null
-/*
- * turbosparc.h: Defines specific to the TurboSparc module.
- * This is SRMMU stuff.
- *
- * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-#ifndef _SPARC_TURBOSPARC_H
-#define _SPARC_TURBOSPARC_H
-
-#include <asm/asi.h>
-#include <asm/pgtsrmmu.h>
-
-/* Bits in the SRMMU control register for TurboSparc modules.
- *
- * -------------------------------------------------------------------
- * |impl-vers| RSV| PMC |PE|PC| RSV |BM| RFR |IC|DC|PSO|RSV|ICS|NF|ME|
- * -------------------------------------------------------------------
- * 31 24 23-21 20-19 18 17 16-15 14 13-10 9 8 7 6-3 2 1 0
- *
- * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
- *
- * This indicates whether the TurboSparc is in boot-mode or not.
- *
- * IC: Instruction Cache -- 0 = off, 1 = on
- * DC: Data Cache -- 0 = off, 1 = 0n
- *
- * These bits enable the on-cpu TurboSparc split I/D caches.
- *
- * ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache
- * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
- * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
- *
- */
-
-#define TURBOSPARC_MMUENABLE 0x00000001
-#define TURBOSPARC_NOFAULT 0x00000002
-#define TURBOSPARC_ICSNOOP 0x00000004
-#define TURBOSPARC_PSO 0x00000080
-#define TURBOSPARC_DCENABLE 0x00000100 /* Enable data cache */
-#define TURBOSPARC_ICENABLE 0x00000200 /* Enable instruction cache */
-#define TURBOSPARC_BMODE 0x00004000
-#define TURBOSPARC_PARITYODD 0x00020000 /* Parity odd, if enabled */
-#define TURBOSPARC_PCENABLE 0x00040000 /* Enable parity checking */
-
-/* Bits in the CPU configuration register for TurboSparc modules.
- *
- * -------------------------------------------------------
- * |IOClk|SNP|AXClk| RAH | WS | RSV |SBC|WT|uS2|SE|SCC|
- * -------------------------------------------------------
- * 31 30 29-28 27-26 25-23 22-8 7-6 5 4 3 2-0
- *
- */
-
-#define TURBOSPARC_SCENABLE 0x00000008 /* Secondary cache enable */
-#define TURBOSPARC_uS2 0x00000010 /* Swift compatibility mode */
-#define TURBOSPARC_WTENABLE 0x00000020 /* Write thru for dcache */
-#define TURBOSPARC_SNENABLE 0x40000000 /* DVMA snoop enable */
-
-#ifndef __ASSEMBLY__
-
-/* Bits [13:5] select one of 512 instruction cache tags */
-static inline void turbosparc_inv_insn_tag(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_TXTC_TAG)
- : "memory");
-}
-
-/* Bits [13:5] select one of 512 data cache tags */
-static inline void turbosparc_inv_data_tag(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_DATAC_TAG)
- : "memory");
-}
-
-static inline void turbosparc_flush_icache(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x4000; addr += 0x20)
- turbosparc_inv_insn_tag(addr);
-}
-
-static inline void turbosparc_flush_dcache(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x4000; addr += 0x20)
- turbosparc_inv_data_tag(addr);
-}
-
-static inline void turbosparc_idflash_clear(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x4000; addr += 0x20) {
- turbosparc_inv_insn_tag(addr);
- turbosparc_inv_data_tag(addr);
- }
-}
-
-static inline void turbosparc_set_ccreg(unsigned long regval)
-{
- __asm__ __volatile__("sta %0, [%1] %2\n\t"
- : /* no outputs */
- : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS)
- : "memory");
-}
-
-static inline unsigned long turbosparc_get_ccreg(void)
-{
- unsigned long regval;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (regval)
- : "r" (0x600), "i" (ASI_M_MMUREGS));
- return regval;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* !(_SPARC_TURBOSPARC_H) */
+++ /dev/null
-#ifndef _SPARC_TYPES_H
-#define _SPARC_TYPES_H
-/*
- * This file is never included by application software unless
- * explicitly requested (e.g., via linux/types.h) in which case the
- * application is Linux specific so (user-) name space pollution is
- * not a major issue. However, for interoperability, libraries still
- * need to be careful to avoid a name clashes.
- */
-
-#if defined(__sparc__) && defined(__arch64__)
-
-/*** SPARC 64 bit ***/
-#include <asm-generic/int-l64.h>
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned short umode_t;
-
-#endif /* __ASSEMBLY__ */
-
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG 64
-
-#ifndef __ASSEMBLY__
-
-/* Dma addresses come in generic and 64-bit flavours. */
-
-typedef u32 dma_addr_t;
-typedef u64 dma64_addr_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-#else
-
-/*** SPARC 32 bit ***/
-#include <asm-generic/int-ll64.h>
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned short umode_t;
-
-#endif /* __ASSEMBLY__ */
-
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG 32
-
-#ifndef __ASSEMBLY__
-
-typedef u32 dma_addr_t;
-typedef u32 dma64_addr_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif /* defined(__sparc__) && defined(__arch64__) */
-
-#endif /* defined(_SPARC_TYPES_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_UACCESS_H
-#define ___ASM_SPARC_UACCESS_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/uaccess_64.h>
-#else
-#include <asm-sparc/uaccess_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * uaccess.h: User space memore access functions.
- *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-#ifndef _ASM_UACCESS_H
-#define _ASM_UACCESS_H
-
-#ifdef __KERNEL__
-#include <linux/compiler.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/errno.h>
-#include <asm/vac-ops.h>
-#endif
-
-#ifndef __ASSEMBLY__
-
-/* Sparc is not segmented, however we need to be able to fool access_ok()
- * when doing system calls from kernel mode legitimately.
- *
- * "For historical reasons, these macros are grossly misnamed." -Linus
- */
-
-#define KERNEL_DS ((mm_segment_t) { 0 })
-#define USER_DS ((mm_segment_t) { -1 })
-
-#define VERIFY_READ 0
-#define VERIFY_WRITE 1
-
-#define get_ds() (KERNEL_DS)
-#define get_fs() (current->thread.current_ds)
-#define set_fs(val) ((current->thread.current_ds) = (val))
-
-#define segment_eq(a,b) ((a).seg == (b).seg)
-
-/* We have there a nice not-mapped page at PAGE_OFFSET - PAGE_SIZE, so that this test
- * can be fairly lightweight.
- * No one can read/write anything from userland in the kernel space by setting
- * large size and address near to PAGE_OFFSET - a fault will break his intentions.
- */
-#define __user_ok(addr, size) ({ (void)(size); (addr) < STACK_TOP; })
-#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS))
-#define __access_ok(addr,size) (__user_ok((addr) & get_fs().seg,(size)))
-#define access_ok(type, addr, size) \
- ({ (void)(type); __access_ok((unsigned long)(addr), size); })
-
-/*
- * The exception table consists of pairs of addresses: the first is the
- * address of an instruction that is allowed to fault, and the second is
- * the address at which the program should continue. No registers are
- * modified, so it is entirely up to the continuation code to figure out
- * what to do.
- *
- * All the routines below use bits of fixup code that are out of line
- * with the main instruction path. This means when everything is well,
- * we don't even have to jump over them. Further, they do not intrude
- * on our cache or tlb entries.
- *
- * There is a special way how to put a range of potentially faulting
- * insns (like twenty ldd/std's with now intervening other instructions)
- * You specify address of first in insn and 0 in fixup and in the next
- * exception_table_entry you specify last potentially faulting insn + 1
- * and in fixup the routine which should handle the fault.
- * That fixup code will get
- * (faulting_insn_address - first_insn_in_the_range_address)/4
- * in %g2 (ie. index of the faulting instruction in the range).
- */
-
-struct exception_table_entry
-{
- unsigned long insn, fixup;
-};
-
-/* Returns 0 if exception not found and fixup otherwise. */
-extern unsigned long search_extables_range(unsigned long addr, unsigned long *g2);
-
-extern void __ret_efault(void);
-
-/* Uh, these should become the main single-value transfer routines..
- * They automatically use the right size if we just have the right
- * pointer type..
- *
- * This gets kind of ugly. We want to return _two_ values in "get_user()"
- * and yet we don't want to do any pointers, because that is too much
- * of a performance impact. Thus we have a few rather ugly macros here,
- * and hide all the ugliness from the user.
- */
-#define put_user(x,ptr) ({ \
-unsigned long __pu_addr = (unsigned long)(ptr); \
-__chk_user_ptr(ptr); \
-__put_user_check((__typeof__(*(ptr)))(x),__pu_addr,sizeof(*(ptr))); })
-
-#define get_user(x,ptr) ({ \
-unsigned long __gu_addr = (unsigned long)(ptr); \
-__chk_user_ptr(ptr); \
-__get_user_check((x),__gu_addr,sizeof(*(ptr)),__typeof__(*(ptr))); })
-
-/*
- * The "__xxx" versions do not do address space checking, useful when
- * doing multiple accesses to the same area (the user has to do the
- * checks by hand with "access_ok()")
- */
-#define __put_user(x,ptr) __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
-#define __get_user(x,ptr) __get_user_nocheck((x),(ptr),sizeof(*(ptr)),__typeof__(*(ptr)))
-
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) ((struct __large_struct __user *)(x))
-
-#define __put_user_check(x,addr,size) ({ \
-register int __pu_ret; \
-if (__access_ok(addr,size)) { \
-switch (size) { \
-case 1: __put_user_asm(x,b,addr,__pu_ret); break; \
-case 2: __put_user_asm(x,h,addr,__pu_ret); break; \
-case 4: __put_user_asm(x,,addr,__pu_ret); break; \
-case 8: __put_user_asm(x,d,addr,__pu_ret); break; \
-default: __pu_ret = __put_user_bad(); break; \
-} } else { __pu_ret = -EFAULT; } __pu_ret; })
-
-#define __put_user_nocheck(x,addr,size) ({ \
-register int __pu_ret; \
-switch (size) { \
-case 1: __put_user_asm(x,b,addr,__pu_ret); break; \
-case 2: __put_user_asm(x,h,addr,__pu_ret); break; \
-case 4: __put_user_asm(x,,addr,__pu_ret); break; \
-case 8: __put_user_asm(x,d,addr,__pu_ret); break; \
-default: __pu_ret = __put_user_bad(); break; \
-} __pu_ret; })
-
-#define __put_user_asm(x,size,addr,ret) \
-__asm__ __volatile__( \
- "/* Put user asm, inline. */\n" \
-"1:\t" "st"#size " %1, %2\n\t" \
- "clr %0\n" \
-"2:\n\n\t" \
- ".section .fixup,#alloc,#execinstr\n\t" \
- ".align 4\n" \
-"3:\n\t" \
- "b 2b\n\t" \
- " mov %3, %0\n\t" \
- ".previous\n\n\t" \
- ".section __ex_table,#alloc\n\t" \
- ".align 4\n\t" \
- ".word 1b, 3b\n\t" \
- ".previous\n\n\t" \
- : "=&r" (ret) : "r" (x), "m" (*__m(addr)), \
- "i" (-EFAULT))
-
-extern int __put_user_bad(void);
-
-#define __get_user_check(x,addr,size,type) ({ \
-register int __gu_ret; \
-register unsigned long __gu_val; \
-if (__access_ok(addr,size)) { \
-switch (size) { \
-case 1: __get_user_asm(__gu_val,ub,addr,__gu_ret); break; \
-case 2: __get_user_asm(__gu_val,uh,addr,__gu_ret); break; \
-case 4: __get_user_asm(__gu_val,,addr,__gu_ret); break; \
-case 8: __get_user_asm(__gu_val,d,addr,__gu_ret); break; \
-default: __gu_val = 0; __gu_ret = __get_user_bad(); break; \
-} } else { __gu_val = 0; __gu_ret = -EFAULT; } x = (type) __gu_val; __gu_ret; })
-
-#define __get_user_check_ret(x,addr,size,type,retval) ({ \
-register unsigned long __gu_val __asm__ ("l1"); \
-if (__access_ok(addr,size)) { \
-switch (size) { \
-case 1: __get_user_asm_ret(__gu_val,ub,addr,retval); break; \
-case 2: __get_user_asm_ret(__gu_val,uh,addr,retval); break; \
-case 4: __get_user_asm_ret(__gu_val,,addr,retval); break; \
-case 8: __get_user_asm_ret(__gu_val,d,addr,retval); break; \
-default: if (__get_user_bad()) return retval; \
-} x = (type) __gu_val; } else return retval; })
-
-#define __get_user_nocheck(x,addr,size,type) ({ \
-register int __gu_ret; \
-register unsigned long __gu_val; \
-switch (size) { \
-case 1: __get_user_asm(__gu_val,ub,addr,__gu_ret); break; \
-case 2: __get_user_asm(__gu_val,uh,addr,__gu_ret); break; \
-case 4: __get_user_asm(__gu_val,,addr,__gu_ret); break; \
-case 8: __get_user_asm(__gu_val,d,addr,__gu_ret); break; \
-default: __gu_val = 0; __gu_ret = __get_user_bad(); break; \
-} x = (type) __gu_val; __gu_ret; })
-
-#define __get_user_nocheck_ret(x,addr,size,type,retval) ({ \
-register unsigned long __gu_val __asm__ ("l1"); \
-switch (size) { \
-case 1: __get_user_asm_ret(__gu_val,ub,addr,retval); break; \
-case 2: __get_user_asm_ret(__gu_val,uh,addr,retval); break; \
-case 4: __get_user_asm_ret(__gu_val,,addr,retval); break; \
-case 8: __get_user_asm_ret(__gu_val,d,addr,retval); break; \
-default: if (__get_user_bad()) return retval; \
-} x = (type) __gu_val; })
-
-#define __get_user_asm(x,size,addr,ret) \
-__asm__ __volatile__( \
- "/* Get user asm, inline. */\n" \
-"1:\t" "ld"#size " %2, %1\n\t" \
- "clr %0\n" \
-"2:\n\n\t" \
- ".section .fixup,#alloc,#execinstr\n\t" \
- ".align 4\n" \
-"3:\n\t" \
- "clr %1\n\t" \
- "b 2b\n\t" \
- " mov %3, %0\n\n\t" \
- ".previous\n\t" \
- ".section __ex_table,#alloc\n\t" \
- ".align 4\n\t" \
- ".word 1b, 3b\n\n\t" \
- ".previous\n\t" \
- : "=&r" (ret), "=&r" (x) : "m" (*__m(addr)), \
- "i" (-EFAULT))
-
-#define __get_user_asm_ret(x,size,addr,retval) \
-if (__builtin_constant_p(retval) && retval == -EFAULT) \
-__asm__ __volatile__( \
- "/* Get user asm ret, inline. */\n" \
-"1:\t" "ld"#size " %1, %0\n\n\t" \
- ".section __ex_table,#alloc\n\t" \
- ".align 4\n\t" \
- ".word 1b,__ret_efault\n\n\t" \
- ".previous\n\t" \
- : "=&r" (x) : "m" (*__m(addr))); \
-else \
-__asm__ __volatile__( \
- "/* Get user asm ret, inline. */\n" \
-"1:\t" "ld"#size " %1, %0\n\n\t" \
- ".section .fixup,#alloc,#execinstr\n\t" \
- ".align 4\n" \
-"3:\n\t" \
- "ret\n\t" \
- " restore %%g0, %2, %%o0\n\n\t" \
- ".previous\n\t" \
- ".section __ex_table,#alloc\n\t" \
- ".align 4\n\t" \
- ".word 1b, 3b\n\n\t" \
- ".previous\n\t" \
- : "=&r" (x) : "m" (*__m(addr)), "i" (retval))
-
-extern int __get_user_bad(void);
-
-extern unsigned long __copy_user(void __user *to, const void __user *from, unsigned long size);
-
-static inline unsigned long copy_to_user(void __user *to, const void *from, unsigned long n)
-{
- if (n && __access_ok((unsigned long) to, n))
- return __copy_user(to, (__force void __user *) from, n);
- else
- return n;
-}
-
-static inline unsigned long __copy_to_user(void __user *to, const void *from, unsigned long n)
-{
- return __copy_user(to, (__force void __user *) from, n);
-}
-
-static inline unsigned long copy_from_user(void *to, const void __user *from, unsigned long n)
-{
- if (n && __access_ok((unsigned long) from, n))
- return __copy_user((__force void __user *) to, from, n);
- else
- return n;
-}
-
-static inline unsigned long __copy_from_user(void *to, const void __user *from, unsigned long n)
-{
- return __copy_user((__force void __user *) to, from, n);
-}
-
-#define __copy_to_user_inatomic __copy_to_user
-#define __copy_from_user_inatomic __copy_from_user
-
-static inline unsigned long __clear_user(void __user *addr, unsigned long size)
-{
- unsigned long ret;
-
- __asm__ __volatile__ (
- ".section __ex_table,#alloc\n\t"
- ".align 4\n\t"
- ".word 1f,3\n\t"
- ".previous\n\t"
- "mov %2, %%o1\n"
- "1:\n\t"
- "call __bzero\n\t"
- " mov %1, %%o0\n\t"
- "mov %%o0, %0\n"
- : "=r" (ret) : "r" (addr), "r" (size) :
- "o0", "o1", "o2", "o3", "o4", "o5", "o7",
- "g1", "g2", "g3", "g4", "g5", "g7", "cc");
-
- return ret;
-}
-
-static inline unsigned long clear_user(void __user *addr, unsigned long n)
-{
- if (n && __access_ok((unsigned long) addr, n))
- return __clear_user(addr, n);
- else
- return n;
-}
-
-extern long __strncpy_from_user(char *dest, const char __user *src, long count);
-
-static inline long strncpy_from_user(char *dest, const char __user *src, long count)
-{
- if (__access_ok((unsigned long) src, count))
- return __strncpy_from_user(dest, src, count);
- else
- return -EFAULT;
-}
-
-extern long __strlen_user(const char __user *);
-extern long __strnlen_user(const char __user *, long len);
-
-static inline long strlen_user(const char __user *str)
-{
- if (!access_ok(VERIFY_READ, str, 0))
- return 0;
- else
- return __strlen_user(str);
-}
-
-static inline long strnlen_user(const char __user *str, long len)
-{
- if (!access_ok(VERIFY_READ, str, 0))
- return 0;
- else
- return __strnlen_user(str, len);
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_UACCESS_H */
+++ /dev/null
-#ifndef _ASM_UACCESS_H
-#define _ASM_UACCESS_H
-
-/*
- * User space memory access functions
- */
-
-#ifdef __KERNEL__
-#include <linux/compiler.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <asm/asi.h>
-#include <asm/system.h>
-#include <asm/spitfire.h>
-#include <asm-generic/uaccess.h>
-#endif
-
-#ifndef __ASSEMBLY__
-
-/*
- * Sparc64 is segmented, though more like the M68K than the I386.
- * We use the secondary ASI to address user memory, which references a
- * completely different VM map, thus there is zero chance of the user
- * doing something queer and tricking us into poking kernel memory.
- *
- * What is left here is basically what is needed for the other parts of
- * the kernel that expect to be able to manipulate, erum, "segments".
- * Or perhaps more properly, permissions.
- *
- * "For historical reasons, these macros are grossly misnamed." -Linus
- */
-
-#define KERNEL_DS ((mm_segment_t) { ASI_P })
-#define USER_DS ((mm_segment_t) { ASI_AIUS }) /* har har har */
-
-#define VERIFY_READ 0
-#define VERIFY_WRITE 1
-
-#define get_fs() ((mm_segment_t) { get_thread_current_ds() })
-#define get_ds() (KERNEL_DS)
-
-#define segment_eq(a,b) ((a).seg == (b).seg)
-
-#define set_fs(val) \
-do { \
- set_thread_current_ds((val).seg); \
- __asm__ __volatile__ ("wr %%g0, %0, %%asi" : : "r" ((val).seg)); \
-} while(0)
-
-static inline int __access_ok(const void __user * addr, unsigned long size)
-{
- return 1;
-}
-
-static inline int access_ok(int type, const void __user * addr, unsigned long size)
-{
- return 1;
-}
-
-/*
- * The exception table consists of pairs of addresses: the first is the
- * address of an instruction that is allowed to fault, and the second is
- * the address at which the program should continue. No registers are
- * modified, so it is entirely up to the continuation code to figure out
- * what to do.
- *
- * All the routines below use bits of fixup code that are out of line
- * with the main instruction path. This means when everything is well,
- * we don't even have to jump over them. Further, they do not intrude
- * on our cache or tlb entries.
- */
-
-struct exception_table_entry {
- unsigned int insn, fixup;
-};
-
-extern void __ret_efault(void);
-extern void __retl_efault(void);
-
-/* Uh, these should become the main single-value transfer routines..
- * They automatically use the right size if we just have the right
- * pointer type..
- *
- * This gets kind of ugly. We want to return _two_ values in "get_user()"
- * and yet we don't want to do any pointers, because that is too much
- * of a performance impact. Thus we have a few rather ugly macros here,
- * and hide all the ugliness from the user.
- */
-#define put_user(x,ptr) ({ \
-unsigned long __pu_addr = (unsigned long)(ptr); \
-__chk_user_ptr(ptr); \
-__put_user_nocheck((__typeof__(*(ptr)))(x),__pu_addr,sizeof(*(ptr))); })
-
-#define get_user(x,ptr) ({ \
-unsigned long __gu_addr = (unsigned long)(ptr); \
-__chk_user_ptr(ptr); \
-__get_user_nocheck((x),__gu_addr,sizeof(*(ptr)),__typeof__(*(ptr))); })
-
-#define __put_user(x,ptr) put_user(x,ptr)
-#define __get_user(x,ptr) get_user(x,ptr)
-
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) ((struct __large_struct *)(x))
-
-#define __put_user_nocheck(data,addr,size) ({ \
-register int __pu_ret; \
-switch (size) { \
-case 1: __put_user_asm(data,b,addr,__pu_ret); break; \
-case 2: __put_user_asm(data,h,addr,__pu_ret); break; \
-case 4: __put_user_asm(data,w,addr,__pu_ret); break; \
-case 8: __put_user_asm(data,x,addr,__pu_ret); break; \
-default: __pu_ret = __put_user_bad(); break; \
-} __pu_ret; })
-
-#define __put_user_asm(x,size,addr,ret) \
-__asm__ __volatile__( \
- "/* Put user asm, inline. */\n" \
-"1:\t" "st"#size "a %1, [%2] %%asi\n\t" \
- "clr %0\n" \
-"2:\n\n\t" \
- ".section .fixup,#alloc,#execinstr\n\t" \
- ".align 4\n" \
-"3:\n\t" \
- "sethi %%hi(2b), %0\n\t" \
- "jmpl %0 + %%lo(2b), %%g0\n\t" \
- " mov %3, %0\n\n\t" \
- ".previous\n\t" \
- ".section __ex_table,\"a\"\n\t" \
- ".align 4\n\t" \
- ".word 1b, 3b\n\t" \
- ".previous\n\n\t" \
- : "=r" (ret) : "r" (x), "r" (__m(addr)), \
- "i" (-EFAULT))
-
-extern int __put_user_bad(void);
-
-#define __get_user_nocheck(data,addr,size,type) ({ \
-register int __gu_ret; \
-register unsigned long __gu_val; \
-switch (size) { \
-case 1: __get_user_asm(__gu_val,ub,addr,__gu_ret); break; \
-case 2: __get_user_asm(__gu_val,uh,addr,__gu_ret); break; \
-case 4: __get_user_asm(__gu_val,uw,addr,__gu_ret); break; \
-case 8: __get_user_asm(__gu_val,x,addr,__gu_ret); break; \
-default: __gu_val = 0; __gu_ret = __get_user_bad(); break; \
-} data = (type) __gu_val; __gu_ret; })
-
-#define __get_user_nocheck_ret(data,addr,size,type,retval) ({ \
-register unsigned long __gu_val __asm__ ("l1"); \
-switch (size) { \
-case 1: __get_user_asm_ret(__gu_val,ub,addr,retval); break; \
-case 2: __get_user_asm_ret(__gu_val,uh,addr,retval); break; \
-case 4: __get_user_asm_ret(__gu_val,uw,addr,retval); break; \
-case 8: __get_user_asm_ret(__gu_val,x,addr,retval); break; \
-default: if (__get_user_bad()) return retval; \
-} data = (type) __gu_val; })
-
-#define __get_user_asm(x,size,addr,ret) \
-__asm__ __volatile__( \
- "/* Get user asm, inline. */\n" \
-"1:\t" "ld"#size "a [%2] %%asi, %1\n\t" \
- "clr %0\n" \
-"2:\n\n\t" \
- ".section .fixup,#alloc,#execinstr\n\t" \
- ".align 4\n" \
-"3:\n\t" \
- "sethi %%hi(2b), %0\n\t" \
- "clr %1\n\t" \
- "jmpl %0 + %%lo(2b), %%g0\n\t" \
- " mov %3, %0\n\n\t" \
- ".previous\n\t" \
- ".section __ex_table,\"a\"\n\t" \
- ".align 4\n\t" \
- ".word 1b, 3b\n\n\t" \
- ".previous\n\t" \
- : "=r" (ret), "=r" (x) : "r" (__m(addr)), \
- "i" (-EFAULT))
-
-#define __get_user_asm_ret(x,size,addr,retval) \
-if (__builtin_constant_p(retval) && retval == -EFAULT) \
-__asm__ __volatile__( \
- "/* Get user asm ret, inline. */\n" \
-"1:\t" "ld"#size "a [%1] %%asi, %0\n\n\t" \
- ".section __ex_table,\"a\"\n\t" \
- ".align 4\n\t" \
- ".word 1b,__ret_efault\n\n\t" \
- ".previous\n\t" \
- : "=r" (x) : "r" (__m(addr))); \
-else \
-__asm__ __volatile__( \
- "/* Get user asm ret, inline. */\n" \
-"1:\t" "ld"#size "a [%1] %%asi, %0\n\n\t" \
- ".section .fixup,#alloc,#execinstr\n\t" \
- ".align 4\n" \
-"3:\n\t" \
- "ret\n\t" \
- " restore %%g0, %2, %%o0\n\n\t" \
- ".previous\n\t" \
- ".section __ex_table,\"a\"\n\t" \
- ".align 4\n\t" \
- ".word 1b, 3b\n\n\t" \
- ".previous\n\t" \
- : "=r" (x) : "r" (__m(addr)), "i" (retval))
-
-extern int __get_user_bad(void);
-
-extern unsigned long __must_check ___copy_from_user(void *to,
- const void __user *from,
- unsigned long size);
-extern unsigned long copy_from_user_fixup(void *to, const void __user *from,
- unsigned long size);
-static inline unsigned long __must_check
-copy_from_user(void *to, const void __user *from, unsigned long size)
-{
- unsigned long ret = ___copy_from_user(to, from, size);
-
- if (unlikely(ret))
- ret = copy_from_user_fixup(to, from, size);
- return ret;
-}
-#define __copy_from_user copy_from_user
-
-extern unsigned long __must_check ___copy_to_user(void __user *to,
- const void *from,
- unsigned long size);
-extern unsigned long copy_to_user_fixup(void __user *to, const void *from,
- unsigned long size);
-static inline unsigned long __must_check
-copy_to_user(void __user *to, const void *from, unsigned long size)
-{
- unsigned long ret = ___copy_to_user(to, from, size);
-
- if (unlikely(ret))
- ret = copy_to_user_fixup(to, from, size);
- return ret;
-}
-#define __copy_to_user copy_to_user
-
-extern unsigned long __must_check ___copy_in_user(void __user *to,
- const void __user *from,
- unsigned long size);
-extern unsigned long copy_in_user_fixup(void __user *to, void __user *from,
- unsigned long size);
-static inline unsigned long __must_check
-copy_in_user(void __user *to, void __user *from, unsigned long size)
-{
- unsigned long ret = ___copy_in_user(to, from, size);
-
- if (unlikely(ret))
- ret = copy_in_user_fixup(to, from, size);
- return ret;
-}
-#define __copy_in_user copy_in_user
-
-extern unsigned long __must_check __clear_user(void __user *, unsigned long);
-
-#define clear_user __clear_user
-
-extern long __must_check __strncpy_from_user(char *dest, const char __user *src, long count);
-
-#define strncpy_from_user __strncpy_from_user
-
-extern long __strlen_user(const char __user *);
-extern long __strnlen_user(const char __user *, long len);
-
-#define strlen_user __strlen_user
-#define strnlen_user __strnlen_user
-#define __copy_to_user_inatomic __copy_to_user
-#define __copy_from_user_inatomic __copy_from_user
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_UACCESS_H */
+++ /dev/null
-/*
- * uctx.h: Sparc64 {set,get}context() register state layouts.
- *
- * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef __SPARC64_UCTX_H
-#define __SPARC64_UCTX_H
-
-#define MC_TSTATE 0
-#define MC_PC 1
-#define MC_NPC 2
-#define MC_Y 3
-#define MC_G1 4
-#define MC_G2 5
-#define MC_G3 6
-#define MC_G4 7
-#define MC_G5 8
-#define MC_G6 9
-#define MC_G7 10
-#define MC_O0 11
-#define MC_O1 12
-#define MC_O2 13
-#define MC_O3 14
-#define MC_O4 15
-#define MC_O5 16
-#define MC_O6 17
-#define MC_O7 18
-#define MC_NGREG 19
-
-typedef unsigned long mc_greg_t;
-typedef mc_greg_t mc_gregset_t[MC_NGREG];
-
-#define MC_MAXFPQ 16
-struct mc_fq {
- unsigned long *mcfq_addr;
- unsigned int mcfq_insn;
-};
-
-struct mc_fpu {
- union {
- unsigned int sregs[32];
- unsigned long dregs[32];
- long double qregs[16];
- } mcfpu_fregs;
- unsigned long mcfpu_fsr;
- unsigned long mcfpu_fprs;
- unsigned long mcfpu_gsr;
- struct mc_fq *mcfpu_fq;
- unsigned char mcfpu_qcnt;
- unsigned char mcfpu_qentsz;
- unsigned char mcfpu_enab;
-};
-typedef struct mc_fpu mc_fpu_t;
-
-typedef struct {
- mc_gregset_t mc_gregs;
- mc_greg_t mc_fp;
- mc_greg_t mc_i7;
- mc_fpu_t mc_fpregs;
-} mcontext_t;
-
-struct ucontext {
- struct ucontext *uc_link;
- unsigned long uc_flags;
- sigset_t uc_sigmask;
- mcontext_t uc_mcontext;
-};
-typedef struct ucontext ucontext_t;
-
-#endif /* __SPARC64_UCTX_H */
+++ /dev/null
-#ifndef _ASM_SPARC_UNALIGNED_H
-#define _ASM_SPARC_UNALIGNED_H
-
-#include <linux/unaligned/be_struct.h>
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/generic.h>
-#define get_unaligned __get_unaligned_be
-#define put_unaligned __put_unaligned_be
-
-#endif /* _ASM_SPARC_UNALIGNED_H */
+++ /dev/null
-#ifndef ___ASM_SPARC_UNISTD_H
-#define ___ASM_SPARC_UNISTD_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/unistd_64.h>
-#else
-#include <asm-sparc/unistd_32.h>
-#endif
-#endif
+++ /dev/null
-#ifndef _SPARC_UNISTD_H
-#define _SPARC_UNISTD_H
-
-/*
- * System calls under the Sparc.
- *
- * Don't be scared by the ugly clobbers, it is the only way I can
- * think of right now to force the arguments into fixed registers
- * before the trap into the system call with gcc 'asm' statements.
- *
- * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
- *
- * SunOS compatibility based upon preliminary work which is:
- *
- * Copyright (C) 1995 Adrian M. Rodriguez (adrian@remus.rutgers.edu)
- */
-
-#define __NR_restart_syscall 0 /* Linux Specific */
-#define __NR_exit 1 /* Common */
-#define __NR_fork 2 /* Common */
-#define __NR_read 3 /* Common */
-#define __NR_write 4 /* Common */
-#define __NR_open 5 /* Common */
-#define __NR_close 6 /* Common */
-#define __NR_wait4 7 /* Common */
-#define __NR_creat 8 /* Common */
-#define __NR_link 9 /* Common */
-#define __NR_unlink 10 /* Common */
-#define __NR_execv 11 /* SunOS Specific */
-#define __NR_chdir 12 /* Common */
-#define __NR_chown 13 /* Common */
-#define __NR_mknod 14 /* Common */
-#define __NR_chmod 15 /* Common */
-#define __NR_lchown 16 /* Common */
-#define __NR_brk 17 /* Common */
-#define __NR_perfctr 18 /* Performance counter operations */
-#define __NR_lseek 19 /* Common */
-#define __NR_getpid 20 /* Common */
-#define __NR_capget 21 /* Linux Specific */
-#define __NR_capset 22 /* Linux Specific */
-#define __NR_setuid 23 /* Implemented via setreuid in SunOS */
-#define __NR_getuid 24 /* Common */
-#define __NR_vmsplice 25 /* ENOSYS under SunOS */
-#define __NR_ptrace 26 /* Common */
-#define __NR_alarm 27 /* Implemented via setitimer in SunOS */
-#define __NR_sigaltstack 28 /* Common */
-#define __NR_pause 29 /* Is sigblock(0)->sigpause() in SunOS */
-#define __NR_utime 30 /* Implemented via utimes() under SunOS */
-#define __NR_lchown32 31 /* Linux sparc32 specific */
-#define __NR_fchown32 32 /* Linux sparc32 specific */
-#define __NR_access 33 /* Common */
-#define __NR_nice 34 /* Implemented via get/setpriority() in SunOS */
-#define __NR_chown32 35 /* Linux sparc32 specific */
-#define __NR_sync 36 /* Common */
-#define __NR_kill 37 /* Common */
-#define __NR_stat 38 /* Common */
-#define __NR_sendfile 39 /* Linux Specific */
-#define __NR_lstat 40 /* Common */
-#define __NR_dup 41 /* Common */
-#define __NR_pipe 42 /* Common */
-#define __NR_times 43 /* Implemented via getrusage() in SunOS */
-#define __NR_getuid32 44 /* Linux sparc32 specific */
-#define __NR_umount2 45 /* Linux Specific */
-#define __NR_setgid 46 /* Implemented via setregid() in SunOS */
-#define __NR_getgid 47 /* Common */
-#define __NR_signal 48 /* Implemented via sigvec() in SunOS */
-#define __NR_geteuid 49 /* SunOS calls getuid() */
-#define __NR_getegid 50 /* SunOS calls getgid() */
-#define __NR_acct 51 /* Common */
-/* #define __NR_memory_ordering 52 Linux sparc64 specific */
-#define __NR_getgid32 53 /* Linux sparc32 specific */
-#define __NR_ioctl 54 /* Common */
-#define __NR_reboot 55 /* Common */
-#define __NR_mmap2 56 /* Linux sparc32 Specific */
-#define __NR_symlink 57 /* Common */
-#define __NR_readlink 58 /* Common */
-#define __NR_execve 59 /* Common */
-#define __NR_umask 60 /* Common */
-#define __NR_chroot 61 /* Common */
-#define __NR_fstat 62 /* Common */
-#define __NR_fstat64 63 /* Linux Specific */
-#define __NR_getpagesize 64 /* Common */
-#define __NR_msync 65 /* Common in newer 1.3.x revs... */
-#define __NR_vfork 66 /* Common */
-#define __NR_pread64 67 /* Linux Specific */
-#define __NR_pwrite64 68 /* Linux Specific */
-#define __NR_geteuid32 69 /* Linux sparc32, sbrk under SunOS */
-#define __NR_getegid32 70 /* Linux sparc32, sstk under SunOS */
-#define __NR_mmap 71 /* Common */
-#define __NR_setreuid32 72 /* Linux sparc32, vadvise under SunOS */
-#define __NR_munmap 73 /* Common */
-#define __NR_mprotect 74 /* Common */
-#define __NR_madvise 75 /* Common */
-#define __NR_vhangup 76 /* Common */
-#define __NR_truncate64 77 /* Linux sparc32 Specific */
-#define __NR_mincore 78 /* Common */
-#define __NR_getgroups 79 /* Common */
-#define __NR_setgroups 80 /* Common */
-#define __NR_getpgrp 81 /* Common */
-#define __NR_setgroups32 82 /* Linux sparc32, setpgrp under SunOS */
-#define __NR_setitimer 83 /* Common */
-#define __NR_ftruncate64 84 /* Linux sparc32 Specific */
-#define __NR_swapon 85 /* Common */
-#define __NR_getitimer 86 /* Common */
-#define __NR_setuid32 87 /* Linux sparc32, gethostname under SunOS */
-#define __NR_sethostname 88 /* Common */
-#define __NR_setgid32 89 /* Linux sparc32, getdtablesize under SunOS */
-#define __NR_dup2 90 /* Common */
-#define __NR_setfsuid32 91 /* Linux sparc32, getdopt under SunOS */
-#define __NR_fcntl 92 /* Common */
-#define __NR_select 93 /* Common */
-#define __NR_setfsgid32 94 /* Linux sparc32, setdopt under SunOS */
-#define __NR_fsync 95 /* Common */
-#define __NR_setpriority 96 /* Common */
-#define __NR_socket 97 /* Common */
-#define __NR_connect 98 /* Common */
-#define __NR_accept 99 /* Common */
-#define __NR_getpriority 100 /* Common */
-#define __NR_rt_sigreturn 101 /* Linux Specific */
-#define __NR_rt_sigaction 102 /* Linux Specific */
-#define __NR_rt_sigprocmask 103 /* Linux Specific */
-#define __NR_rt_sigpending 104 /* Linux Specific */
-#define __NR_rt_sigtimedwait 105 /* Linux Specific */
-#define __NR_rt_sigqueueinfo 106 /* Linux Specific */
-#define __NR_rt_sigsuspend 107 /* Linux Specific */
-#define __NR_setresuid32 108 /* Linux Specific, sigvec under SunOS */
-#define __NR_getresuid32 109 /* Linux Specific, sigblock under SunOS */
-#define __NR_setresgid32 110 /* Linux Specific, sigsetmask under SunOS */
-#define __NR_getresgid32 111 /* Linux Specific, sigpause under SunOS */
-#define __NR_setregid32 112 /* Linux sparc32, sigstack under SunOS */
-#define __NR_recvmsg 113 /* Common */
-#define __NR_sendmsg 114 /* Common */
-#define __NR_getgroups32 115 /* Linux sparc32, vtrace under SunOS */
-#define __NR_gettimeofday 116 /* Common */
-#define __NR_getrusage 117 /* Common */
-#define __NR_getsockopt 118 /* Common */
-#define __NR_getcwd 119 /* Linux Specific */
-#define __NR_readv 120 /* Common */
-#define __NR_writev 121 /* Common */
-#define __NR_settimeofday 122 /* Common */
-#define __NR_fchown 123 /* Common */
-#define __NR_fchmod 124 /* Common */
-#define __NR_recvfrom 125 /* Common */
-#define __NR_setreuid 126 /* Common */
-#define __NR_setregid 127 /* Common */
-#define __NR_rename 128 /* Common */
-#define __NR_truncate 129 /* Common */
-#define __NR_ftruncate 130 /* Common */
-#define __NR_flock 131 /* Common */
-#define __NR_lstat64 132 /* Linux Specific */
-#define __NR_sendto 133 /* Common */
-#define __NR_shutdown 134 /* Common */
-#define __NR_socketpair 135 /* Common */
-#define __NR_mkdir 136 /* Common */
-#define __NR_rmdir 137 /* Common */
-#define __NR_utimes 138 /* SunOS Specific */
-#define __NR_stat64 139 /* Linux Specific */
-#define __NR_sendfile64 140 /* adjtime under SunOS */
-#define __NR_getpeername 141 /* Common */
-#define __NR_futex 142 /* gethostid under SunOS */
-#define __NR_gettid 143 /* ENOSYS under SunOS */
-#define __NR_getrlimit 144 /* Common */
-#define __NR_setrlimit 145 /* Common */
-#define __NR_pivot_root 146 /* Linux Specific, killpg under SunOS */
-#define __NR_prctl 147 /* ENOSYS under SunOS */
-#define __NR_pciconfig_read 148 /* ENOSYS under SunOS */
-#define __NR_pciconfig_write 149 /* ENOSYS under SunOS */
-#define __NR_getsockname 150 /* Common */
-#define __NR_inotify_init 151 /* Linux specific */
-#define __NR_inotify_add_watch 152 /* Linux specific */
-#define __NR_poll 153 /* Common */
-#define __NR_getdents64 154 /* Linux specific */
-#define __NR_fcntl64 155 /* Linux sparc32 Specific */
-#define __NR_inotify_rm_watch 156 /* Linux specific */
-#define __NR_statfs 157 /* Common */
-#define __NR_fstatfs 158 /* Common */
-#define __NR_umount 159 /* Common */
-#define __NR_sched_set_affinity 160 /* Linux specific, async_daemon under SunOS */
-#define __NR_sched_get_affinity 161 /* Linux specific, getfh under SunOS */
-#define __NR_getdomainname 162 /* SunOS Specific */
-#define __NR_setdomainname 163 /* Common */
-/* #define __NR_utrap_install 164 Linux sparc64 specific */
-#define __NR_quotactl 165 /* Common */
-#define __NR_set_tid_address 166 /* Linux specific, exportfs under SunOS */
-#define __NR_mount 167 /* Common */
-#define __NR_ustat 168 /* Common */
-#define __NR_setxattr 169 /* SunOS: semsys */
-#define __NR_lsetxattr 170 /* SunOS: msgsys */
-#define __NR_fsetxattr 171 /* SunOS: shmsys */
-#define __NR_getxattr 172 /* SunOS: auditsys */
-#define __NR_lgetxattr 173 /* SunOS: rfssys */
-#define __NR_getdents 174 /* Common */
-#define __NR_setsid 175 /* Common */
-#define __NR_fchdir 176 /* Common */
-#define __NR_fgetxattr 177 /* SunOS: fchroot */
-#define __NR_listxattr 178 /* SunOS: vpixsys */
-#define __NR_llistxattr 179 /* SunOS: aioread */
-#define __NR_flistxattr 180 /* SunOS: aiowrite */
-#define __NR_removexattr 181 /* SunOS: aiowait */
-#define __NR_lremovexattr 182 /* SunOS: aiocancel */
-#define __NR_sigpending 183 /* Common */
-#define __NR_query_module 184 /* Linux Specific */
-#define __NR_setpgid 185 /* Common */
-#define __NR_fremovexattr 186 /* SunOS: pathconf */
-#define __NR_tkill 187 /* SunOS: fpathconf */
-#define __NR_exit_group 188 /* Linux specific, sysconf undef SunOS */
-#define __NR_uname 189 /* Linux Specific */
-#define __NR_init_module 190 /* Linux Specific */
-#define __NR_personality 191 /* Linux Specific */
-#define __NR_remap_file_pages 192 /* Linux Specific */
-#define __NR_epoll_create 193 /* Linux Specific */
-#define __NR_epoll_ctl 194 /* Linux Specific */
-#define __NR_epoll_wait 195 /* Linux Specific */
-#define __NR_ioprio_set 196 /* Linux Specific */
-#define __NR_getppid 197 /* Linux Specific */
-#define __NR_sigaction 198 /* Linux Specific */
-#define __NR_sgetmask 199 /* Linux Specific */
-#define __NR_ssetmask 200 /* Linux Specific */
-#define __NR_sigsuspend 201 /* Linux Specific */
-#define __NR_oldlstat 202 /* Linux Specific */
-#define __NR_uselib 203 /* Linux Specific */
-#define __NR_readdir 204 /* Linux Specific */
-#define __NR_readahead 205 /* Linux Specific */
-#define __NR_socketcall 206 /* Linux Specific */
-#define __NR_syslog 207 /* Linux Specific */
-#define __NR_lookup_dcookie 208 /* Linux Specific */
-#define __NR_fadvise64 209 /* Linux Specific */
-#define __NR_fadvise64_64 210 /* Linux Specific */
-#define __NR_tgkill 211 /* Linux Specific */
-#define __NR_waitpid 212 /* Linux Specific */
-#define __NR_swapoff 213 /* Linux Specific */
-#define __NR_sysinfo 214 /* Linux Specific */
-#define __NR_ipc 215 /* Linux Specific */
-#define __NR_sigreturn 216 /* Linux Specific */
-#define __NR_clone 217 /* Linux Specific */
-#define __NR_ioprio_get 218 /* Linux Specific */
-#define __NR_adjtimex 219 /* Linux Specific */
-#define __NR_sigprocmask 220 /* Linux Specific */
-#define __NR_create_module 221 /* Linux Specific */
-#define __NR_delete_module 222 /* Linux Specific */
-#define __NR_get_kernel_syms 223 /* Linux Specific */
-#define __NR_getpgid 224 /* Linux Specific */
-#define __NR_bdflush 225 /* Linux Specific */
-#define __NR_sysfs 226 /* Linux Specific */
-#define __NR_afs_syscall 227 /* Linux Specific */
-#define __NR_setfsuid 228 /* Linux Specific */
-#define __NR_setfsgid 229 /* Linux Specific */
-#define __NR__newselect 230 /* Linux Specific */
-#define __NR_time 231 /* Linux Specific */
-#define __NR_splice 232 /* Linux Specific */
-#define __NR_stime 233 /* Linux Specific */
-#define __NR_statfs64 234 /* Linux Specific */
-#define __NR_fstatfs64 235 /* Linux Specific */
-#define __NR__llseek 236 /* Linux Specific */
-#define __NR_mlock 237
-#define __NR_munlock 238
-#define __NR_mlockall 239
-#define __NR_munlockall 240
-#define __NR_sched_setparam 241
-#define __NR_sched_getparam 242
-#define __NR_sched_setscheduler 243
-#define __NR_sched_getscheduler 244
-#define __NR_sched_yield 245
-#define __NR_sched_get_priority_max 246
-#define __NR_sched_get_priority_min 247
-#define __NR_sched_rr_get_interval 248
-#define __NR_nanosleep 249
-#define __NR_mremap 250
-#define __NR__sysctl 251
-#define __NR_getsid 252
-#define __NR_fdatasync 253
-#define __NR_nfsservctl 254
-#define __NR_sync_file_range 255
-#define __NR_clock_settime 256
-#define __NR_clock_gettime 257
-#define __NR_clock_getres 258
-#define __NR_clock_nanosleep 259
-#define __NR_sched_getaffinity 260
-#define __NR_sched_setaffinity 261
-#define __NR_timer_settime 262
-#define __NR_timer_gettime 263
-#define __NR_timer_getoverrun 264
-#define __NR_timer_delete 265
-#define __NR_timer_create 266
-/* #define __NR_vserver 267 Reserved for VSERVER */
-#define __NR_io_setup 268
-#define __NR_io_destroy 269
-#define __NR_io_submit 270
-#define __NR_io_cancel 271
-#define __NR_io_getevents 272
-#define __NR_mq_open 273
-#define __NR_mq_unlink 274
-#define __NR_mq_timedsend 275
-#define __NR_mq_timedreceive 276
-#define __NR_mq_notify 277
-#define __NR_mq_getsetattr 278
-#define __NR_waitid 279
-#define __NR_tee 280
-#define __NR_add_key 281
-#define __NR_request_key 282
-#define __NR_keyctl 283
-#define __NR_openat 284
-#define __NR_mkdirat 285
-#define __NR_mknodat 286
-#define __NR_fchownat 287
-#define __NR_futimesat 288
-#define __NR_fstatat64 289
-#define __NR_unlinkat 290
-#define __NR_renameat 291
-#define __NR_linkat 292
-#define __NR_symlinkat 293
-#define __NR_readlinkat 294
-#define __NR_fchmodat 295
-#define __NR_faccessat 296
-#define __NR_pselect6 297
-#define __NR_ppoll 298
-#define __NR_unshare 299
-#define __NR_set_robust_list 300
-#define __NR_get_robust_list 301
-#define __NR_migrate_pages 302
-#define __NR_mbind 303
-#define __NR_get_mempolicy 304
-#define __NR_set_mempolicy 305
-#define __NR_kexec_load 306
-#define __NR_move_pages 307
-#define __NR_getcpu 308
-#define __NR_epoll_pwait 309
-#define __NR_utimensat 310
-#define __NR_signalfd 311
-#define __NR_timerfd_create 312
-#define __NR_eventfd 313
-#define __NR_fallocate 314
-#define __NR_timerfd_settime 315
-#define __NR_timerfd_gettime 316
-#define __NR_signalfd4 317
-#define __NR_eventfd2 318
-#define __NR_epoll_create1 319
-#define __NR_dup3 320
-#define __NR_pipe2 321
-#define __NR_inotify_init1 322
-
-#define NR_SYSCALLS 323
-
-/* Sparc 32-bit only has the "setresuid32", "getresuid32" variants,
- * it never had the plain ones and there is no value to adding those
- * old versions into the syscall table.
- */
-#define __IGNORE_setresuid
-#define __IGNORE_getresuid
-#define __IGNORE_setresgid
-#define __IGNORE_getresgid
-
-#ifdef __KERNEL__
-#define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGSUSPEND
-
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
-#endif /* __KERNEL__ */
-#endif /* _SPARC_UNISTD_H */
+++ /dev/null
-#ifndef _SPARC64_UNISTD_H
-#define _SPARC64_UNISTD_H
-
-/*
- * System calls under the Sparc.
- *
- * Don't be scared by the ugly clobbers, it is the only way I can
- * think of right now to force the arguments into fixed registers
- * before the trap into the system call with gcc 'asm' statements.
- *
- * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
- *
- * SunOS compatibility based upon preliminary work which is:
- *
- * Copyright (C) 1995 Adrian M. Rodriguez (adrian@remus.rutgers.edu)
- */
-
-#define __NR_restart_syscall 0 /* Linux Specific */
-#define __NR_exit 1 /* Common */
-#define __NR_fork 2 /* Common */
-#define __NR_read 3 /* Common */
-#define __NR_write 4 /* Common */
-#define __NR_open 5 /* Common */
-#define __NR_close 6 /* Common */
-#define __NR_wait4 7 /* Common */
-#define __NR_creat 8 /* Common */
-#define __NR_link 9 /* Common */
-#define __NR_unlink 10 /* Common */
-#define __NR_execv 11 /* SunOS Specific */
-#define __NR_chdir 12 /* Common */
-#define __NR_chown 13 /* Common */
-#define __NR_mknod 14 /* Common */
-#define __NR_chmod 15 /* Common */
-#define __NR_lchown 16 /* Common */
-#define __NR_brk 17 /* Common */
-#define __NR_perfctr 18 /* Performance counter operations */
-#define __NR_lseek 19 /* Common */
-#define __NR_getpid 20 /* Common */
-#define __NR_capget 21 /* Linux Specific */
-#define __NR_capset 22 /* Linux Specific */
-#define __NR_setuid 23 /* Implemented via setreuid in SunOS */
-#define __NR_getuid 24 /* Common */
-#define __NR_vmsplice 25 /* ENOSYS under SunOS */
-#define __NR_ptrace 26 /* Common */
-#define __NR_alarm 27 /* Implemented via setitimer in SunOS */
-#define __NR_sigaltstack 28 /* Common */
-#define __NR_pause 29 /* Is sigblock(0)->sigpause() in SunOS */
-#define __NR_utime 30 /* Implemented via utimes() under SunOS */
-/* #define __NR_lchown32 31 Linux sparc32 specific */
-/* #define __NR_fchown32 32 Linux sparc32 specific */
-#define __NR_access 33 /* Common */
-#define __NR_nice 34 /* Implemented via get/setpriority() in SunOS */
-/* #define __NR_chown32 35 Linux sparc32 specific */
-#define __NR_sync 36 /* Common */
-#define __NR_kill 37 /* Common */
-#define __NR_stat 38 /* Common */
-#define __NR_sendfile 39 /* Linux Specific */
-#define __NR_lstat 40 /* Common */
-#define __NR_dup 41 /* Common */
-#define __NR_pipe 42 /* Common */
-#define __NR_times 43 /* Implemented via getrusage() in SunOS */
-/* #define __NR_getuid32 44 Linux sparc32 specific */
-#define __NR_umount2 45 /* Linux Specific */
-#define __NR_setgid 46 /* Implemented via setregid() in SunOS */
-#define __NR_getgid 47 /* Common */
-#define __NR_signal 48 /* Implemented via sigvec() in SunOS */
-#define __NR_geteuid 49 /* SunOS calls getuid() */
-#define __NR_getegid 50 /* SunOS calls getgid() */
-#define __NR_acct 51 /* Common */
-#define __NR_memory_ordering 52 /* Linux Specific */
-/* #define __NR_getgid32 53 Linux sparc32 specific */
-#define __NR_ioctl 54 /* Common */
-#define __NR_reboot 55 /* Common */
-/* #define __NR_mmap2 56 Linux sparc32 Specific */
-#define __NR_symlink 57 /* Common */
-#define __NR_readlink 58 /* Common */
-#define __NR_execve 59 /* Common */
-#define __NR_umask 60 /* Common */
-#define __NR_chroot 61 /* Common */
-#define __NR_fstat 62 /* Common */
-#define __NR_fstat64 63 /* Linux Specific */
-#define __NR_getpagesize 64 /* Common */
-#define __NR_msync 65 /* Common in newer 1.3.x revs... */
-#define __NR_vfork 66 /* Common */
-#define __NR_pread64 67 /* Linux Specific */
-#define __NR_pwrite64 68 /* Linux Specific */
-/* #define __NR_geteuid32 69 Linux sparc32, sbrk under SunOS */
-/* #define __NR_getegid32 70 Linux sparc32, sstk under SunOS */
-#define __NR_mmap 71 /* Common */
-/* #define __NR_setreuid32 72 Linux sparc32, vadvise under SunOS */
-#define __NR_munmap 73 /* Common */
-#define __NR_mprotect 74 /* Common */
-#define __NR_madvise 75 /* Common */
-#define __NR_vhangup 76 /* Common */
-/* #define __NR_truncate64 77 Linux sparc32 Specific */
-#define __NR_mincore 78 /* Common */
-#define __NR_getgroups 79 /* Common */
-#define __NR_setgroups 80 /* Common */
-#define __NR_getpgrp 81 /* Common */
-/* #define __NR_setgroups32 82 Linux sparc32, setpgrp under SunOS */
-#define __NR_setitimer 83 /* Common */
-/* #define __NR_ftruncate64 84 Linux sparc32 Specific */
-#define __NR_swapon 85 /* Common */
-#define __NR_getitimer 86 /* Common */
-/* #define __NR_setuid32 87 Linux sparc32, gethostname under SunOS */
-#define __NR_sethostname 88 /* Common */
-/* #define __NR_setgid32 89 Linux sparc32, getdtablesize under SunOS */
-#define __NR_dup2 90 /* Common */
-/* #define __NR_setfsuid32 91 Linux sparc32, getdopt under SunOS */
-#define __NR_fcntl 92 /* Common */
-#define __NR_select 93 /* Common */
-/* #define __NR_setfsgid32 94 Linux sparc32, setdopt under SunOS */
-#define __NR_fsync 95 /* Common */
-#define __NR_setpriority 96 /* Common */
-#define __NR_socket 97 /* Common */
-#define __NR_connect 98 /* Common */
-#define __NR_accept 99 /* Common */
-#define __NR_getpriority 100 /* Common */
-#define __NR_rt_sigreturn 101 /* Linux Specific */
-#define __NR_rt_sigaction 102 /* Linux Specific */
-#define __NR_rt_sigprocmask 103 /* Linux Specific */
-#define __NR_rt_sigpending 104 /* Linux Specific */
-#define __NR_rt_sigtimedwait 105 /* Linux Specific */
-#define __NR_rt_sigqueueinfo 106 /* Linux Specific */
-#define __NR_rt_sigsuspend 107 /* Linux Specific */
-#define __NR_setresuid 108 /* Linux Specific, sigvec under SunOS */
-#define __NR_getresuid 109 /* Linux Specific, sigblock under SunOS */
-#define __NR_setresgid 110 /* Linux Specific, sigsetmask under SunOS */
-#define __NR_getresgid 111 /* Linux Specific, sigpause under SunOS */
-/* #define __NR_setregid32 75 Linux sparc32, sigstack under SunOS */
-#define __NR_recvmsg 113 /* Common */
-#define __NR_sendmsg 114 /* Common */
-/* #define __NR_getgroups32 115 Linux sparc32, vtrace under SunOS */
-#define __NR_gettimeofday 116 /* Common */
-#define __NR_getrusage 117 /* Common */
-#define __NR_getsockopt 118 /* Common */
-#define __NR_getcwd 119 /* Linux Specific */
-#define __NR_readv 120 /* Common */
-#define __NR_writev 121 /* Common */
-#define __NR_settimeofday 122 /* Common */
-#define __NR_fchown 123 /* Common */
-#define __NR_fchmod 124 /* Common */
-#define __NR_recvfrom 125 /* Common */
-#define __NR_setreuid 126 /* Common */
-#define __NR_setregid 127 /* Common */
-#define __NR_rename 128 /* Common */
-#define __NR_truncate 129 /* Common */
-#define __NR_ftruncate 130 /* Common */
-#define __NR_flock 131 /* Common */
-#define __NR_lstat64 132 /* Linux Specific */
-#define __NR_sendto 133 /* Common */
-#define __NR_shutdown 134 /* Common */
-#define __NR_socketpair 135 /* Common */
-#define __NR_mkdir 136 /* Common */
-#define __NR_rmdir 137 /* Common */
-#define __NR_utimes 138 /* SunOS Specific */
-#define __NR_stat64 139 /* Linux Specific */
-#define __NR_sendfile64 140 /* adjtime under SunOS */
-#define __NR_getpeername 141 /* Common */
-#define __NR_futex 142 /* gethostid under SunOS */
-#define __NR_gettid 143 /* ENOSYS under SunOS */
-#define __NR_getrlimit 144 /* Common */
-#define __NR_setrlimit 145 /* Common */
-#define __NR_pivot_root 146 /* Linux Specific, killpg under SunOS */
-#define __NR_prctl 147 /* ENOSYS under SunOS */
-#define __NR_pciconfig_read 148 /* ENOSYS under SunOS */
-#define __NR_pciconfig_write 149 /* ENOSYS under SunOS */
-#define __NR_getsockname 150 /* Common */
-#define __NR_inotify_init 151 /* Linux specific */
-#define __NR_inotify_add_watch 152 /* Linux specific */
-#define __NR_poll 153 /* Common */
-#define __NR_getdents64 154 /* Linux specific */
-/* #define __NR_fcntl64 155 Linux sparc32 Specific */
-#define __NR_inotify_rm_watch 156 /* Linux specific */
-#define __NR_statfs 157 /* Common */
-#define __NR_fstatfs 158 /* Common */
-#define __NR_umount 159 /* Common */
-#define __NR_sched_set_affinity 160 /* Linux specific, async_daemon under SunOS */
-#define __NR_sched_get_affinity 161 /* Linux specific, getfh under SunOS */
-#define __NR_getdomainname 162 /* SunOS Specific */
-#define __NR_setdomainname 163 /* Common */
-#define __NR_utrap_install 164 /* SYSV ABI/v9 required */
-#define __NR_quotactl 165 /* Common */
-#define __NR_set_tid_address 166 /* Linux specific, exportfs under SunOS */
-#define __NR_mount 167 /* Common */
-#define __NR_ustat 168 /* Common */
-#define __NR_setxattr 169 /* SunOS: semsys */
-#define __NR_lsetxattr 170 /* SunOS: msgsys */
-#define __NR_fsetxattr 171 /* SunOS: shmsys */
-#define __NR_getxattr 172 /* SunOS: auditsys */
-#define __NR_lgetxattr 173 /* SunOS: rfssys */
-#define __NR_getdents 174 /* Common */
-#define __NR_setsid 175 /* Common */
-#define __NR_fchdir 176 /* Common */
-#define __NR_fgetxattr 177 /* SunOS: fchroot */
-#define __NR_listxattr 178 /* SunOS: vpixsys */
-#define __NR_llistxattr 179 /* SunOS: aioread */
-#define __NR_flistxattr 180 /* SunOS: aiowrite */
-#define __NR_removexattr 181 /* SunOS: aiowait */
-#define __NR_lremovexattr 182 /* SunOS: aiocancel */
-#define __NR_sigpending 183 /* Common */
-#define __NR_query_module 184 /* Linux Specific */
-#define __NR_setpgid 185 /* Common */
-#define __NR_fremovexattr 186 /* SunOS: pathconf */
-#define __NR_tkill 187 /* SunOS: fpathconf */
-#define __NR_exit_group 188 /* Linux specific, sysconf undef SunOS */
-#define __NR_uname 189 /* Linux Specific */
-#define __NR_init_module 190 /* Linux Specific */
-#define __NR_personality 191 /* Linux Specific */
-#define __NR_remap_file_pages 192 /* Linux Specific */
-#define __NR_epoll_create 193 /* Linux Specific */
-#define __NR_epoll_ctl 194 /* Linux Specific */
-#define __NR_epoll_wait 195 /* Linux Specific */
-#define __NR_ioprio_set 196 /* Linux Specific */
-#define __NR_getppid 197 /* Linux Specific */
-#define __NR_sigaction 198 /* Linux Specific */
-#define __NR_sgetmask 199 /* Linux Specific */
-#define __NR_ssetmask 200 /* Linux Specific */
-#define __NR_sigsuspend 201 /* Linux Specific */
-#define __NR_oldlstat 202 /* Linux Specific */
-#define __NR_uselib 203 /* Linux Specific */
-#define __NR_readdir 204 /* Linux Specific */
-#define __NR_readahead 205 /* Linux Specific */
-#define __NR_socketcall 206 /* Linux Specific */
-#define __NR_syslog 207 /* Linux Specific */
-#define __NR_lookup_dcookie 208 /* Linux Specific */
-#define __NR_fadvise64 209 /* Linux Specific */
-#define __NR_fadvise64_64 210 /* Linux Specific */
-#define __NR_tgkill 211 /* Linux Specific */
-#define __NR_waitpid 212 /* Linux Specific */
-#define __NR_swapoff 213 /* Linux Specific */
-#define __NR_sysinfo 214 /* Linux Specific */
-#define __NR_ipc 215 /* Linux Specific */
-#define __NR_sigreturn 216 /* Linux Specific */
-#define __NR_clone 217 /* Linux Specific */
-#define __NR_ioprio_get 218 /* Linux Specific */
-#define __NR_adjtimex 219 /* Linux Specific */
-#define __NR_sigprocmask 220 /* Linux Specific */
-#define __NR_create_module 221 /* Linux Specific */
-#define __NR_delete_module 222 /* Linux Specific */
-#define __NR_get_kernel_syms 223 /* Linux Specific */
-#define __NR_getpgid 224 /* Linux Specific */
-#define __NR_bdflush 225 /* Linux Specific */
-#define __NR_sysfs 226 /* Linux Specific */
-#define __NR_afs_syscall 227 /* Linux Specific */
-#define __NR_setfsuid 228 /* Linux Specific */
-#define __NR_setfsgid 229 /* Linux Specific */
-#define __NR__newselect 230 /* Linux Specific */
-#ifdef __KERNEL__
-#define __NR_time 231 /* Linux sparc32 */
-#endif
-#define __NR_splice 232 /* Linux Specific */
-#define __NR_stime 233 /* Linux Specific */
-#define __NR_statfs64 234 /* Linux Specific */
-#define __NR_fstatfs64 235 /* Linux Specific */
-#define __NR__llseek 236 /* Linux Specific */
-#define __NR_mlock 237
-#define __NR_munlock 238
-#define __NR_mlockall 239
-#define __NR_munlockall 240
-#define __NR_sched_setparam 241
-#define __NR_sched_getparam 242
-#define __NR_sched_setscheduler 243
-#define __NR_sched_getscheduler 244
-#define __NR_sched_yield 245
-#define __NR_sched_get_priority_max 246
-#define __NR_sched_get_priority_min 247
-#define __NR_sched_rr_get_interval 248
-#define __NR_nanosleep 249
-#define __NR_mremap 250
-#define __NR__sysctl 251
-#define __NR_getsid 252
-#define __NR_fdatasync 253
-#define __NR_nfsservctl 254
-#define __NR_sync_file_range 255
-#define __NR_clock_settime 256
-#define __NR_clock_gettime 257
-#define __NR_clock_getres 258
-#define __NR_clock_nanosleep 259
-#define __NR_sched_getaffinity 260
-#define __NR_sched_setaffinity 261
-#define __NR_timer_settime 262
-#define __NR_timer_gettime 263
-#define __NR_timer_getoverrun 264
-#define __NR_timer_delete 265
-#define __NR_timer_create 266
-/* #define __NR_vserver 267 Reserved for VSERVER */
-#define __NR_io_setup 268
-#define __NR_io_destroy 269
-#define __NR_io_submit 270
-#define __NR_io_cancel 271
-#define __NR_io_getevents 272
-#define __NR_mq_open 273
-#define __NR_mq_unlink 274
-#define __NR_mq_timedsend 275
-#define __NR_mq_timedreceive 276
-#define __NR_mq_notify 277
-#define __NR_mq_getsetattr 278
-#define __NR_waitid 279
-#define __NR_tee 280
-#define __NR_add_key 281
-#define __NR_request_key 282
-#define __NR_keyctl 283
-#define __NR_openat 284
-#define __NR_mkdirat 285
-#define __NR_mknodat 286
-#define __NR_fchownat 287
-#define __NR_futimesat 288
-#define __NR_fstatat64 289
-#define __NR_unlinkat 290
-#define __NR_renameat 291
-#define __NR_linkat 292
-#define __NR_symlinkat 293
-#define __NR_readlinkat 294
-#define __NR_fchmodat 295
-#define __NR_faccessat 296
-#define __NR_pselect6 297
-#define __NR_ppoll 298
-#define __NR_unshare 299
-#define __NR_set_robust_list 300
-#define __NR_get_robust_list 301
-#define __NR_migrate_pages 302
-#define __NR_mbind 303
-#define __NR_get_mempolicy 304
-#define __NR_set_mempolicy 305
-#define __NR_kexec_load 306
-#define __NR_move_pages 307
-#define __NR_getcpu 308
-#define __NR_epoll_pwait 309
-#define __NR_utimensat 310
-#define __NR_signalfd 311
-#define __NR_timerfd_create 312
-#define __NR_eventfd 313
-#define __NR_fallocate 314
-#define __NR_timerfd_settime 315
-#define __NR_timerfd_gettime 316
-#define __NR_signalfd4 317
-#define __NR_eventfd2 318
-#define __NR_epoll_create1 319
-#define __NR_dup3 320
-#define __NR_pipe2 321
-#define __NR_inotify_init1 322
-
-#define NR_SYSCALLS 323
-
-#ifdef __KERNEL__
-#define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_COMPAT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGSUSPEND
-#define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
-
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
-#endif /* __KERNEL__ */
-#endif /* _SPARC64_UNISTD_H */
+++ /dev/null
-#ifndef _SPARC64_UPA_H
-#define _SPARC64_UPA_H
-
-#include <asm/asi.h>
-
-/* UPA level registers and defines. */
-
-/* UPA Config Register */
-#define UPA_CONFIG_RESV 0xffffffffc0000000 /* Reserved. */
-#define UPA_CONFIG_PCON 0x000000003fc00000 /* Depth of various sys queues. */
-#define UPA_CONFIG_MID 0x00000000003e0000 /* Module ID. */
-#define UPA_CONFIG_PCAP 0x000000000001ffff /* Port Capabilities. */
-
-/* UPA Port ID Register */
-#define UPA_PORTID_FNP 0xff00000000000000 /* Hardcoded to 0xfc on ultra. */
-#define UPA_PORTID_RESV 0x00fffff800000000 /* Reserved. */
-#define UPA_PORTID_ECCVALID 0x0000000400000000 /* Zero if mod can generate ECC */
-#define UPA_PORTID_ONEREAD 0x0000000200000000 /* Set if mod generates P_RASB */
-#define UPA_PORTID_PINTRDQ 0x0000000180000000 /* # outstanding P_INT_REQ's */
-#define UPA_PORTID_PREQDQ 0x000000007e000000 /* slave-wr's to mod supported */
-#define UPA_PORTID_PREQRD 0x0000000001e00000 /* # incoming P_REQ's supported */
-#define UPA_PORTID_UPACAP 0x00000000001f0000 /* UPA capabilities of mod */
-#define UPA_PORTID_ID 0x000000000000ffff /* Module Identification bits */
-
-/* UPA I/O space accessors */
-#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
-static inline unsigned char _upa_readb(unsigned long addr)
-{
- unsigned char ret;
-
- __asm__ __volatile__("lduba\t[%1] %2, %0\t/* upa_readb */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-
- return ret;
-}
-
-static inline unsigned short _upa_readw(unsigned long addr)
-{
- unsigned short ret;
-
- __asm__ __volatile__("lduha\t[%1] %2, %0\t/* upa_readw */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-
- return ret;
-}
-
-static inline unsigned int _upa_readl(unsigned long addr)
-{
- unsigned int ret;
-
- __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* upa_readl */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-
- return ret;
-}
-
-static inline unsigned long _upa_readq(unsigned long addr)
-{
- unsigned long ret;
-
- __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* upa_readq */"
- : "=r" (ret)
- : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-
- return ret;
-}
-
-static inline void _upa_writeb(unsigned char b, unsigned long addr)
-{
- __asm__ __volatile__("stba\t%0, [%1] %2\t/* upa_writeb */"
- : /* no outputs */
- : "r" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-}
-
-static inline void _upa_writew(unsigned short w, unsigned long addr)
-{
- __asm__ __volatile__("stha\t%0, [%1] %2\t/* upa_writew */"
- : /* no outputs */
- : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-}
-
-static inline void _upa_writel(unsigned int l, unsigned long addr)
-{
- __asm__ __volatile__("stwa\t%0, [%1] %2\t/* upa_writel */"
- : /* no outputs */
- : "r" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-}
-
-static inline void _upa_writeq(unsigned long q, unsigned long addr)
-{
- __asm__ __volatile__("stxa\t%0, [%1] %2\t/* upa_writeq */"
- : /* no outputs */
- : "r" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-}
-
-#define upa_readb(__addr) (_upa_readb((unsigned long)(__addr)))
-#define upa_readw(__addr) (_upa_readw((unsigned long)(__addr)))
-#define upa_readl(__addr) (_upa_readl((unsigned long)(__addr)))
-#define upa_readq(__addr) (_upa_readq((unsigned long)(__addr)))
-#define upa_writeb(__b, __addr) (_upa_writeb((__b), (unsigned long)(__addr)))
-#define upa_writew(__w, __addr) (_upa_writew((__w), (unsigned long)(__addr)))
-#define upa_writel(__l, __addr) (_upa_writel((__l), (unsigned long)(__addr)))
-#define upa_writeq(__q, __addr) (_upa_writeq((__q), (unsigned long)(__addr)))
-#endif /* __KERNEL__ && !__ASSEMBLY__ */
-
-#endif /* !(_SPARC64_UPA_H) */
+++ /dev/null
-#ifndef _SPARC_USER_H
-#define _SPARC_USER_H
-
-/* Nothing to define. */
-
-#endif /* !(_SPARC_USER_H) */
+++ /dev/null
-/*
- * include/asm-sparc64/utrap.h
- *
- * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-
-#ifndef __ASM_SPARC64_UTRAP_H
-#define __ASM_SPARC64_UTRAP_H
-
-#define UT_INSTRUCTION_EXCEPTION 1
-#define UT_INSTRUCTION_ERROR 2
-#define UT_INSTRUCTION_PROTECTION 3
-#define UT_ILLTRAP_INSTRUCTION 4
-#define UT_ILLEGAL_INSTRUCTION 5
-#define UT_PRIVILEGED_OPCODE 6
-#define UT_FP_DISABLED 7
-#define UT_FP_EXCEPTION_IEEE_754 8
-#define UT_FP_EXCEPTION_OTHER 9
-#define UT_TAG_OVERVIEW 10
-#define UT_DIVISION_BY_ZERO 11
-#define UT_DATA_EXCEPTION 12
-#define UT_DATA_ERROR 13
-#define UT_DATA_PROTECTION 14
-#define UT_MEM_ADDRESS_NOT_ALIGNED 15
-#define UT_PRIVILEGED_ACTION 16
-#define UT_ASYNC_DATA_ERROR 17
-#define UT_TRAP_INSTRUCTION_16 18
-#define UT_TRAP_INSTRUCTION_17 19
-#define UT_TRAP_INSTRUCTION_18 20
-#define UT_TRAP_INSTRUCTION_19 21
-#define UT_TRAP_INSTRUCTION_20 22
-#define UT_TRAP_INSTRUCTION_21 23
-#define UT_TRAP_INSTRUCTION_22 24
-#define UT_TRAP_INSTRUCTION_23 25
-#define UT_TRAP_INSTRUCTION_24 26
-#define UT_TRAP_INSTRUCTION_25 27
-#define UT_TRAP_INSTRUCTION_26 28
-#define UT_TRAP_INSTRUCTION_27 29
-#define UT_TRAP_INSTRUCTION_28 30
-#define UT_TRAP_INSTRUCTION_29 31
-#define UT_TRAP_INSTRUCTION_30 32
-#define UT_TRAP_INSTRUCTION_31 33
-
-#define UTH_NOCHANGE (-1)
-
-#ifndef __ASSEMBLY__
-typedef int utrap_entry_t;
-typedef void *utrap_handler_t;
-#endif /* __ASSEMBLY__ */
-
-#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
+++ /dev/null
-#ifndef _SPARC_VAC_OPS_H
-#define _SPARC_VAC_OPS_H
-
-/* vac-ops.h: Inline assembly routines to do operations on the Sparc
- * VAC (virtual address cache) for the sun4c.
- *
- * Copyright (C) 1994, David S. Miller (davem@caip.rutgers.edu)
- */
-
-#include <asm/sysen.h>
-#include <asm/contregs.h>
-#include <asm/asi.h>
-
-/* The SUN4C models have a virtually addressed write-through
- * cache.
- *
- * The cache tags are directly accessible through an ASI and
- * each have the form:
- *
- * ------------------------------------------------------------
- * | MBZ | CONTEXT | WRITE | PRIV | VALID | MBZ | TagID | MBZ |
- * ------------------------------------------------------------
- * 31 25 24 22 21 20 19 18 16 15 2 1 0
- *
- * MBZ: These bits are either unused and/or reserved and should
- * be written as zeroes.
- *
- * CONTEXT: Records the context to which this cache line belongs.
- *
- * WRITE: A copy of the writable bit from the mmu pte access bits.
- *
- * PRIV: A copy of the privileged bit from the pte access bits.
- *
- * VALID: If set, this line is valid, else invalid.
- *
- * TagID: Fourteen bits of tag ID.
- *
- * Every virtual address is seen by the cache like this:
- *
- * ----------------------------------------
- * | RESV | TagID | LINE | BYTE-in-LINE |
- * ----------------------------------------
- * 31 30 29 16 15 4 3 0
- *
- * RESV: Unused/reserved.
- *
- * TagID: Used to match the Tag-ID in that vac tags.
- *
- * LINE: Which line within the cache
- *
- * BYTE-in-LINE: Which byte within the cache line.
- */
-
-/* Sun4c VAC Tags */
-#define S4CVACTAG_CID 0x01c00000
-#define S4CVACTAG_W 0x00200000
-#define S4CVACTAG_P 0x00100000
-#define S4CVACTAG_V 0x00080000
-#define S4CVACTAG_TID 0x0000fffc
-
-/* Sun4c VAC Virtual Address */
-/* These aren't used, why bother? (Anton) */
-#if 0
-#define S4CVACVA_TID 0x3fff0000
-#define S4CVACVA_LINE 0x0000fff0
-#define S4CVACVA_BIL 0x0000000f
-#endif
-
-/* The indexing of cache lines creates a problem. Because the line
- * field of a virtual address extends past the page offset within
- * the virtual address it is possible to have what are called
- * 'bad aliases' which will create inconsistencies. So we must make
- * sure that within a context that if a physical page is mapped
- * more than once, that 'extra' line bits are the same. If this is
- * not the case, and thus is a 'bad alias' we must turn off the
- * cacheable bit in the pte's of all such pages.
- */
-
-#ifdef CONFIG_SUN4
-#define S4CVAC_BADBITS 0x0001e000
-#else
-#define S4CVAC_BADBITS 0x0000f000
-#endif
-
-/* The following is true if vaddr1 and vaddr2 would cause
- * a 'bad alias'.
- */
-#define S4CVAC_BADALIAS(vaddr1, vaddr2) \
- ((((unsigned long) (vaddr1)) ^ ((unsigned long) (vaddr2))) & \
- (S4CVAC_BADBITS))
-
-/* The following structure describes the characteristics of a sun4c
- * VAC as probed from the prom during boot time.
- */
-struct sun4c_vac_props {
- unsigned int num_bytes; /* Size of the cache */
- unsigned int num_lines; /* Number of cache lines */
- unsigned int do_hwflushes; /* Hardware flushing available? */
- enum { VAC_NONE, VAC_WRITE_THROUGH,
- VAC_WRITE_BACK } type; /* What type of VAC? */
- unsigned int linesize; /* Size of each line in bytes */
- unsigned int log2lsize; /* log2(linesize) */
- unsigned int on; /* VAC is enabled */
-};
-
-extern struct sun4c_vac_props sun4c_vacinfo;
-
-/* sun4c_enable_vac() enables the sun4c virtual address cache. */
-static inline void sun4c_enable_vac(void)
-{
- __asm__ __volatile__("lduba [%0] %1, %%g1\n\t"
- "or %%g1, %2, %%g1\n\t"
- "stba %%g1, [%0] %1\n\t"
- : /* no outputs */
- : "r" ((unsigned int) AC_SENABLE),
- "i" (ASI_CONTROL), "i" (SENABLE_CACHE)
- : "g1", "memory");
- sun4c_vacinfo.on = 1;
-}
-
-/* sun4c_disable_vac() disables the virtual address cache. */
-static inline void sun4c_disable_vac(void)
-{
- __asm__ __volatile__("lduba [%0] %1, %%g1\n\t"
- "andn %%g1, %2, %%g1\n\t"
- "stba %%g1, [%0] %1\n\t"
- : /* no outputs */
- : "r" ((unsigned int) AC_SENABLE),
- "i" (ASI_CONTROL), "i" (SENABLE_CACHE)
- : "g1", "memory");
- sun4c_vacinfo.on = 0;
-}
-
-#endif /* !(_SPARC_VAC_OPS_H) */
+++ /dev/null
-#ifndef _SPARC_VADDRS_H
-#define _SPARC_VADDRS_H
-
-#include <asm/head.h>
-
-/*
- * asm-sparc/vaddrs.h: Here we define the virtual addresses at
- * which important things will be mapped.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 2000 Anton Blanchard (anton@samba.org)
- */
-
-#define SRMMU_MAXMEM 0x0c000000
-
-#define SRMMU_NOCACHE_VADDR (KERNBASE + SRMMU_MAXMEM)
- /* = 0x0fc000000 */
-/* XXX Empiricals - this needs to go away - KMW */
-#define SRMMU_MIN_NOCACHE_PAGES (550)
-#define SRMMU_MAX_NOCACHE_PAGES (1280)
-
-/* The following constant is used in mm/srmmu.c::srmmu_nocache_calcsize()
- * to determine the amount of memory that will be reserved as nocache:
- *
- * 256 pages will be taken as nocache per each
- * SRMMU_NOCACHE_ALCRATIO MB of system memory.
- *
- * limits enforced: nocache minimum = 256 pages
- * nocache maximum = 1280 pages
- */
-#define SRMMU_NOCACHE_ALCRATIO 64 /* 256 pages per 64MB of system RAM */
-
-#define SUN4M_IOBASE_VADDR 0xfd000000 /* Base for mapping pages */
-#define IOBASE_VADDR 0xfe000000
-#define IOBASE_END 0xfe600000
-
-/*
- * On the sun4/4c we need a place
- * to reliably map locked down kernel data. This includes the
- * task_struct and kernel stack pages of each process plus the
- * scsi buffers during dvma IO transfers, also the floppy buffers
- * during pseudo dma which runs with traps off (no faults allowed).
- * Some quick calculations yield:
- * NR_TASKS <512> * (3 * PAGE_SIZE) == 0x600000
- * Subtract this from 0xc00000 and you get 0x927C0 of vm left
- * over to map SCSI dvma + floppy pseudo-dma buffers. So be
- * careful if you change NR_TASKS or else there won't be enough
- * room for it all.
- */
-#define SUN4C_LOCK_VADDR 0xff000000
-#define SUN4C_LOCK_END 0xffc00000
-
-#define KADB_DEBUGGER_BEGVM 0xffc00000 /* Where kern debugger is in virt-mem */
-#define KADB_DEBUGGER_ENDVM 0xffd00000
-#define DEBUG_FIRSTVADDR KADB_DEBUGGER_BEGVM
-#define DEBUG_LASTVADDR KADB_DEBUGGER_ENDVM
-
-#define LINUX_OPPROM_BEGVM 0xffd00000
-#define LINUX_OPPROM_ENDVM 0xfff00000
-
-#define DVMA_VADDR 0xfff00000 /* Base area of the DVMA on suns */
-#define DVMA_END 0xfffc0000
-
-#endif /* !(_SPARC_VADDRS_H) */
+++ /dev/null
-/* Copyright (c) 1996 by Manish Vachharajani */
-
-#ifndef _LINUX_VFC_IOCTLS_H_
-#define _LINUX_VFC_IOCTLS_H_
-
- /* IOCTLs */
-#define VFC_IOCTL(a) (('j' << 8) | a)
-#define VFCGCTRL (VFC_IOCTL (0)) /* get vfc attributes */
-#define VFCSCTRL (VFC_IOCTL (1)) /* set vfc attributes */
-#define VFCGVID (VFC_IOCTL (2)) /* get video decoder attributes */
-#define VFCSVID (VFC_IOCTL (3)) /* set video decoder attributes */
-#define VFCHUE (VFC_IOCTL (4)) /* set hue */
-#define VFCPORTCHG (VFC_IOCTL (5)) /* change port */
-#define VFCRDINFO (VFC_IOCTL (6)) /* read info */
-
- /* Options for setting the vfc attributes and status */
-#define MEMPRST 0x1 /* reset FIFO ptr. */
-#define CAPTRCMD 0x2 /* start capture and wait */
-#define DIAGMODE 0x3 /* diag mode */
-#define NORMMODE 0x4 /* normal mode */
-#define CAPTRSTR 0x5 /* start capture */
-#define CAPTRWAIT 0x6 /* wait for capture to finish */
-
-
- /* Options for the decoder */
-#define STD_NTSC 0x1 /* NTSC mode */
-#define STD_PAL 0x2 /* PAL mode */
-#define COLOR_ON 0x3 /* force color ON */
-#define MONO 0x4 /* force color OFF */
-
- /* Values returned by ioctl 2 */
-
-#define NO_LOCK 1
-#define NTSC_COLOR 2
-#define NTSC_NOCOLOR 3
-#define PAL_COLOR 4
-#define PAL_NOCOLOR 5
-
-/* Not too sure what this does yet */
- /* Options for setting Field number */
-#define ODD_FIELD 0x1
-#define EVEN_FIELD 0x0
-#define ACTIVE_ONLY 0x2
-#define NON_ACTIVE 0x0
-
-/* Debug options */
-#define VFC_I2C_SEND 0
-#define VFC_I2C_RECV 1
-
-struct vfc_debug_inout
-{
- unsigned long addr;
- unsigned long ret;
- unsigned long len;
- unsigned char __user *buffer;
-};
-
-#endif /* _LINUX_VFC_IOCTLS_H_ */
+++ /dev/null
-/*
- * Access to VGA videoram
- *
- * (c) 1998 Martin Mares <mj@ucw.cz>
- */
-
-#ifndef _LINUX_ASM_VGA_H_
-#define _LINUX_ASM_VGA_H_
-
-#include <asm/types.h>
-
-#define VT_BUF_HAVE_RW
-
-#undef scr_writew
-#undef scr_readw
-
-static inline void scr_writew(u16 val, u16 *addr)
-{
- BUG_ON((long) addr >= 0);
-
- *addr = val;
-}
-
-static inline u16 scr_readw(const u16 *addr)
-{
- BUG_ON((long) addr >= 0);
-
- return *addr;
-}
-
-#define VGA_MAP_MEM(x,s) (x)
-
-#endif
+++ /dev/null
-/*
- * viking.h: Defines specific to the GNU/Viking MBUS module.
- * This is SRMMU stuff.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-#ifndef _SPARC_VIKING_H
-#define _SPARC_VIKING_H
-
-#include <asm/asi.h>
-#include <asm/mxcc.h>
-#include <asm/pgtsrmmu.h>
-
-/* Bits in the SRMMU control register for GNU/Viking modules.
- *
- * -----------------------------------------------------------
- * |impl-vers| RSV |TC|AC|SP|BM|PC|MBM|SB|IC|DC|PSO|RSV|NF|ME|
- * -----------------------------------------------------------
- * 31 24 23-17 16 15 14 13 12 11 10 9 8 7 6-2 1 0
- *
- * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache
- * 1 = Twalks are cacheable in E-cache
- *
- * GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present
- * and never caches them internally (or so states the docs). Therefore
- * for machines lacking an E-cache (ie. in MBUS mode) this bit must
- * remain cleared.
- *
- * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable
- * 1 = Passthru physical accesses cacheable
- *
- * This indicates whether accesses are cacheable when no cachable bit
- * is present in the pte when the processor is in boot-mode or the
- * access does not need pte's for translation (ie. pass-thru ASI's).
- * "Cachable" is only referring to E-cache (if present) and not the
- * on chip split I/D caches of the GNU/Viking.
- *
- * SP: SnooP Enable -- 0 = bus snooping off, 1 = bus snooping on
- *
- * This enables snooping on the GNU/Viking bus. This must be on
- * for the hardware cache consistency mechanisms of the GNU/Viking
- * to work at all. On non-mxcc GNU/Viking modules the split I/D
- * caches will snoop regardless of whether they are enabled, this
- * takes care of the case where the I or D or both caches are turned
- * off yet still contain valid data. Note also that this bit does
- * not affect GNU/Viking store-buffer snoops, those happen if the
- * store-buffer is enabled no matter what.
- *
- * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
- *
- * This indicates whether the GNU/Viking is in boot-mode or not,
- * if it is then all instruction fetch physical addresses are
- * computed as 0xff0000000 + low 28 bits of requested address.
- * GNU/Viking boot-mode does not affect data accesses. Also,
- * in boot mode instruction accesses bypass the split on chip I/D
- * caches, they may be cached by the GNU/MXCC if present and enabled.
- *
- * MBM: MBus Mode -- 0 = not in MBus mode, 1 = in MBus mode
- *
- * This indicated the GNU/Viking configuration present. If in
- * MBUS mode, the GNU/Viking lacks a GNU/MXCC E-cache. If it is
- * not then the GNU/Viking is on a module VBUS connected directly
- * to a GNU/MXCC cache controller. The GNU/MXCC can be thus connected
- * to either an GNU/MBUS (sun4m) or the packet-switched GNU/XBus (sun4d).
- *
- * SB: StoreBuffer enable -- 0 = store buffer off, 1 = store buffer on
- *
- * The GNU/Viking store buffer allows the chip to continue execution
- * after a store even if the data cannot be placed in one of the
- * caches during that cycle. If disabled, all stores operations
- * occur synchronously.
- *
- * IC: Instruction Cache -- 0 = off, 1 = on
- * DC: Data Cache -- 0 = off, 1 = 0n
- *
- * These bits enable the on-cpu GNU/Viking split I/D caches. Note,
- * as mentioned above, these caches will snoop the bus in GNU/MBUS
- * configurations even when disabled to avoid data corruption.
- *
- * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
- * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
- *
- */
-
-#define VIKING_MMUENABLE 0x00000001
-#define VIKING_NOFAULT 0x00000002
-#define VIKING_PSO 0x00000080
-#define VIKING_DCENABLE 0x00000100 /* Enable data cache */
-#define VIKING_ICENABLE 0x00000200 /* Enable instruction cache */
-#define VIKING_SBENABLE 0x00000400 /* Enable store buffer */
-#define VIKING_MMODE 0x00000800 /* MBUS mode */
-#define VIKING_PCENABLE 0x00001000 /* Enable parity checking */
-#define VIKING_BMODE 0x00002000
-#define VIKING_SPENABLE 0x00004000 /* Enable bus cache snooping */
-#define VIKING_ACENABLE 0x00008000 /* Enable alternate caching */
-#define VIKING_TCENABLE 0x00010000 /* Enable table-walks to be cached */
-#define VIKING_DPENABLE 0x00040000 /* Enable the data prefetcher */
-
-/*
- * GNU/Viking Breakpoint Action Register fields.
- */
-#define VIKING_ACTION_MIX 0x00001000 /* Enable multiple instructions */
-
-/*
- * GNU/Viking Cache Tags.
- */
-#define VIKING_PTAG_VALID 0x01000000 /* Cache block is valid */
-#define VIKING_PTAG_DIRTY 0x00010000 /* Block has been modified */
-#define VIKING_PTAG_SHARED 0x00000100 /* Shared with some other cache */
-
-#ifndef __ASSEMBLY__
-
-static inline void viking_flush_icache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_IC_FLCLEAR)
- : "memory");
-}
-
-static inline void viking_flush_dcache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_DC_FLCLEAR)
- : "memory");
-}
-
-static inline void viking_unlock_icache(void)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (0x80000000), "i" (ASI_M_IC_FLCLEAR)
- : "memory");
-}
-
-static inline void viking_unlock_dcache(void)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (0x80000000), "i" (ASI_M_DC_FLCLEAR)
- : "memory");
-}
-
-static inline void viking_set_bpreg(unsigned long regval)
-{
- __asm__ __volatile__("sta %0, [%%g0] %1\n\t"
- : /* no outputs */
- : "r" (regval), "i" (ASI_M_ACTION)
- : "memory");
-}
-
-static inline unsigned long viking_get_bpreg(void)
-{
- unsigned long regval;
-
- __asm__ __volatile__("lda [%%g0] %1, %0\n\t"
- : "=r" (regval)
- : "i" (ASI_M_ACTION));
- return regval;
-}
-
-static inline void viking_get_dcache_ptag(int set, int block,
- unsigned long *data)
-{
- unsigned long ptag = ((set & 0x7f) << 5) | ((block & 0x3) << 26) |
- 0x80000000;
- unsigned long info, page;
-
- __asm__ __volatile__ ("ldda [%2] %3, %%g2\n\t"
- "or %%g0, %%g2, %0\n\t"
- "or %%g0, %%g3, %1\n\t"
- : "=r" (info), "=r" (page)
- : "r" (ptag), "i" (ASI_M_DATAC_TAG)
- : "g2", "g3");
- data[0] = info;
- data[1] = page;
-}
-
-static inline void viking_mxcc_turn_off_parity(unsigned long *mregp,
- unsigned long *mxcc_cregp)
-{
- unsigned long mreg = *mregp;
- unsigned long mxcc_creg = *mxcc_cregp;
-
- mreg &= ~(VIKING_PCENABLE);
- mxcc_creg &= ~(MXCC_CTL_PARE);
-
- __asm__ __volatile__ ("set 1f, %%g2\n\t"
- "andcc %%g2, 4, %%g0\n\t"
- "bne 2f\n\t"
- " nop\n"
- "1:\n\t"
- "sta %0, [%%g0] %3\n\t"
- "sta %1, [%2] %4\n\t"
- "b 1f\n\t"
- " nop\n\t"
- "nop\n"
- "2:\n\t"
- "sta %0, [%%g0] %3\n\t"
- "sta %1, [%2] %4\n"
- "1:\n\t"
- : /* no output */
- : "r" (mreg), "r" (mxcc_creg),
- "r" (MXCC_CREG), "i" (ASI_M_MMUREGS),
- "i" (ASI_M_MXCC)
- : "g2", "memory", "cc");
- *mregp = mreg;
- *mxcc_cregp = mxcc_creg;
-}
-
-static inline unsigned long viking_hwprobe(unsigned long vaddr)
-{
- unsigned long val;
-
- vaddr &= PAGE_MASK;
- /* Probe all MMU entries. */
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (val)
- : "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
- if (!val)
- return 0;
-
- /* Probe region. */
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (val)
- : "r" (vaddr | 0x200), "i" (ASI_M_FLUSH_PROBE));
- if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
- vaddr &= ~SRMMU_PGDIR_MASK;
- vaddr >>= PAGE_SHIFT;
- return val | (vaddr << 8);
- }
-
- /* Probe segment. */
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (val)
- : "r" (vaddr | 0x100), "i" (ASI_M_FLUSH_PROBE));
- if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
- vaddr &= ~SRMMU_REAL_PMD_MASK;
- vaddr >>= PAGE_SHIFT;
- return val | (vaddr << 8);
- }
-
- /* Probe page. */
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (val)
- : "r" (vaddr), "i" (ASI_M_FLUSH_PROBE));
- return val;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* !(_SPARC_VIKING_H) */
+++ /dev/null
-#ifndef _SPARC64_VIO_H
-#define _SPARC64_VIO_H
-
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/mod_devicetable.h>
-#include <linux/timer.h>
-#include <linux/spinlock.h>
-#include <linux/completion.h>
-#include <linux/list.h>
-#include <linux/log2.h>
-
-#include <asm/ldc.h>
-#include <asm/mdesc.h>
-
-struct vio_msg_tag {
- u8 type;
-#define VIO_TYPE_CTRL 0x01
-#define VIO_TYPE_DATA 0x02
-#define VIO_TYPE_ERR 0x04
-
- u8 stype;
-#define VIO_SUBTYPE_INFO 0x01
-#define VIO_SUBTYPE_ACK 0x02
-#define VIO_SUBTYPE_NACK 0x04
-
- u16 stype_env;
-#define VIO_VER_INFO 0x0001
-#define VIO_ATTR_INFO 0x0002
-#define VIO_DRING_REG 0x0003
-#define VIO_DRING_UNREG 0x0004
-#define VIO_RDX 0x0005
-#define VIO_PKT_DATA 0x0040
-#define VIO_DESC_DATA 0x0041
-#define VIO_DRING_DATA 0x0042
-#define VNET_MCAST_INFO 0x0101
-
- u32 sid;
-};
-
-struct vio_rdx {
- struct vio_msg_tag tag;
- u64 resv[6];
-};
-
-struct vio_ver_info {
- struct vio_msg_tag tag;
- u16 major;
- u16 minor;
- u8 dev_class;
-#define VDEV_NETWORK 0x01
-#define VDEV_NETWORK_SWITCH 0x02
-#define VDEV_DISK 0x03
-#define VDEV_DISK_SERVER 0x04
-
- u8 resv1[3];
- u64 resv2[5];
-};
-
-struct vio_dring_register {
- struct vio_msg_tag tag;
- u64 dring_ident;
- u32 num_descr;
- u32 descr_size;
- u16 options;
-#define VIO_TX_DRING 0x0001
-#define VIO_RX_DRING 0x0002
- u16 resv;
- u32 num_cookies;
- struct ldc_trans_cookie cookies[0];
-};
-
-struct vio_dring_unregister {
- struct vio_msg_tag tag;
- u64 dring_ident;
- u64 resv[5];
-};
-
-/* Data transfer modes */
-#define VIO_PKT_MODE 0x01 /* Packet based transfer */
-#define VIO_DESC_MODE 0x02 /* In-band descriptors */
-#define VIO_DRING_MODE 0x03 /* Descriptor rings */
-
-struct vio_dring_data {
- struct vio_msg_tag tag;
- u64 seq;
- u64 dring_ident;
- u32 start_idx;
- u32 end_idx;
- u8 state;
-#define VIO_DRING_ACTIVE 0x01
-#define VIO_DRING_STOPPED 0x02
-
- u8 __pad1;
- u16 __pad2;
- u32 __pad3;
- u64 __par4[2];
-};
-
-struct vio_dring_hdr {
- u8 state;
-#define VIO_DESC_FREE 0x01
-#define VIO_DESC_READY 0x02
-#define VIO_DESC_ACCEPTED 0x03
-#define VIO_DESC_DONE 0x04
- u8 ack;
-#define VIO_ACK_ENABLE 0x01
-#define VIO_ACK_DISABLE 0x00
-
- u16 __pad1;
- u32 __pad2;
-};
-
-/* VIO disk specific structures and defines */
-struct vio_disk_attr_info {
- struct vio_msg_tag tag;
- u8 xfer_mode;
- u8 vdisk_type;
-#define VD_DISK_TYPE_SLICE 0x01 /* Slice in block device */
-#define VD_DISK_TYPE_DISK 0x02 /* Entire block device */
- u16 resv1;
- u32 vdisk_block_size;
- u64 operations;
- u64 vdisk_size;
- u64 max_xfer_size;
- u64 resv2[2];
-};
-
-struct vio_disk_desc {
- struct vio_dring_hdr hdr;
- u64 req_id;
- u8 operation;
-#define VD_OP_BREAD 0x01 /* Block read */
-#define VD_OP_BWRITE 0x02 /* Block write */
-#define VD_OP_FLUSH 0x03 /* Flush disk contents */
-#define VD_OP_GET_WCE 0x04 /* Get write-cache status */
-#define VD_OP_SET_WCE 0x05 /* Enable/disable write-cache */
-#define VD_OP_GET_VTOC 0x06 /* Get VTOC */
-#define VD_OP_SET_VTOC 0x07 /* Set VTOC */
-#define VD_OP_GET_DISKGEOM 0x08 /* Get disk geometry */
-#define VD_OP_SET_DISKGEOM 0x09 /* Set disk geometry */
-#define VD_OP_SCSICMD 0x0a /* SCSI control command */
-#define VD_OP_GET_DEVID 0x0b /* Get device ID */
-#define VD_OP_GET_EFI 0x0c /* Get EFI */
-#define VD_OP_SET_EFI 0x0d /* Set EFI */
- u8 slice;
- u16 resv1;
- u32 status;
- u64 offset;
- u64 size;
- u32 ncookies;
- u32 resv2;
- struct ldc_trans_cookie cookies[0];
-};
-
-#define VIO_DISK_VNAME_LEN 8
-#define VIO_DISK_ALABEL_LEN 128
-#define VIO_DISK_NUM_PART 8
-
-struct vio_disk_vtoc {
- u8 volume_name[VIO_DISK_VNAME_LEN];
- u16 sector_size;
- u16 num_partitions;
- u8 ascii_label[VIO_DISK_ALABEL_LEN];
- struct {
- u16 id;
- u16 perm_flags;
- u32 resv;
- u64 start_block;
- u64 num_blocks;
- } partitions[VIO_DISK_NUM_PART];
-};
-
-struct vio_disk_geom {
- u16 num_cyl; /* Num data cylinders */
- u16 alt_cyl; /* Num alternate cylinders */
- u16 beg_cyl; /* Cyl off of fixed head area */
- u16 num_hd; /* Num heads */
- u16 num_sec; /* Num sectors */
- u16 ifact; /* Interleave factor */
- u16 apc; /* Alts per cylinder (SCSI) */
- u16 rpm; /* Revolutions per minute */
- u16 phy_cyl; /* Num physical cylinders */
- u16 wr_skip; /* Num sects to skip, writes */
- u16 rd_skip; /* Num sects to skip, writes */
-};
-
-struct vio_disk_devid {
- u16 resv;
- u16 type;
- u32 len;
- char id[0];
-};
-
-struct vio_disk_efi {
- u64 lba;
- u64 len;
- char data[0];
-};
-
-/* VIO net specific structures and defines */
-struct vio_net_attr_info {
- struct vio_msg_tag tag;
- u8 xfer_mode;
- u8 addr_type;
-#define VNET_ADDR_ETHERMAC 0x01
- u16 ack_freq;
- u32 resv1;
- u64 addr;
- u64 mtu;
- u64 resv2[3];
-};
-
-#define VNET_NUM_MCAST 7
-
-struct vio_net_mcast_info {
- struct vio_msg_tag tag;
- u8 set;
- u8 count;
- u8 mcast_addr[VNET_NUM_MCAST * 6];
- u32 resv;
-};
-
-struct vio_net_desc {
- struct vio_dring_hdr hdr;
- u32 size;
- u32 ncookies;
- struct ldc_trans_cookie cookies[0];
-};
-
-#define VIO_MAX_RING_COOKIES 24
-
-struct vio_dring_state {
- u64 ident;
- void *base;
- u64 snd_nxt;
- u64 rcv_nxt;
- u32 entry_size;
- u32 num_entries;
- u32 prod;
- u32 cons;
- u32 pending;
- int ncookies;
- struct ldc_trans_cookie cookies[VIO_MAX_RING_COOKIES];
-};
-
-static inline void *vio_dring_cur(struct vio_dring_state *dr)
-{
- return dr->base + (dr->entry_size * dr->prod);
-}
-
-static inline void *vio_dring_entry(struct vio_dring_state *dr,
- unsigned int index)
-{
- return dr->base + (dr->entry_size * index);
-}
-
-static inline u32 vio_dring_avail(struct vio_dring_state *dr,
- unsigned int ring_size)
-{
- BUILD_BUG_ON(!is_power_of_2(ring_size));
-
- return (dr->pending -
- ((dr->prod - dr->cons) & (ring_size - 1)));
-}
-
-#define VIO_MAX_TYPE_LEN 32
-#define VIO_MAX_COMPAT_LEN 64
-
-struct vio_dev {
- u64 mp;
- struct device_node *dp;
-
- char type[VIO_MAX_TYPE_LEN];
- char compat[VIO_MAX_COMPAT_LEN];
- int compat_len;
-
- u64 dev_no;
-
- unsigned long channel_id;
-
- unsigned int tx_irq;
- unsigned int rx_irq;
-
- struct device dev;
-};
-
-struct vio_driver {
- struct list_head node;
- const struct vio_device_id *id_table;
- int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
- int (*remove)(struct vio_dev *dev);
- void (*shutdown)(struct vio_dev *dev);
- unsigned long driver_data;
- struct device_driver driver;
-};
-
-struct vio_version {
- u16 major;
- u16 minor;
-};
-
-struct vio_driver_state;
-struct vio_driver_ops {
- int (*send_attr)(struct vio_driver_state *vio);
- int (*handle_attr)(struct vio_driver_state *vio, void *pkt);
- void (*handshake_complete)(struct vio_driver_state *vio);
-};
-
-struct vio_completion {
- struct completion com;
- int err;
- int waiting_for;
-};
-
-struct vio_driver_state {
- /* Protects VIO handshake and, optionally, driver private state. */
- spinlock_t lock;
-
- struct ldc_channel *lp;
-
- u32 _peer_sid;
- u32 _local_sid;
- struct vio_dring_state drings[2];
-#define VIO_DRIVER_TX_RING 0
-#define VIO_DRIVER_RX_RING 1
-
- u8 hs_state;
-#define VIO_HS_INVALID 0x00
-#define VIO_HS_GOTVERS 0x01
-#define VIO_HS_GOT_ATTR 0x04
-#define VIO_HS_SENT_DREG 0x08
-#define VIO_HS_SENT_RDX 0x10
-#define VIO_HS_GOT_RDX_ACK 0x20
-#define VIO_HS_GOT_RDX 0x40
-#define VIO_HS_SENT_RDX_ACK 0x80
-#define VIO_HS_COMPLETE (VIO_HS_GOT_RDX_ACK | VIO_HS_SENT_RDX_ACK)
-
- u8 dev_class;
-
- u8 dr_state;
-#define VIO_DR_STATE_TXREG 0x01
-#define VIO_DR_STATE_RXREG 0x02
-#define VIO_DR_STATE_TXREQ 0x10
-#define VIO_DR_STATE_RXREQ 0x20
-
- u8 debug;
-#define VIO_DEBUG_HS 0x01
-#define VIO_DEBUG_DATA 0x02
-
- void *desc_buf;
- unsigned int desc_buf_len;
-
- struct vio_completion *cmp;
-
- struct vio_dev *vdev;
-
- struct timer_list timer;
-
- struct vio_version ver;
-
- struct vio_version *ver_table;
- int ver_table_entries;
-
- char *name;
-
- struct vio_driver_ops *ops;
-};
-
-#define viodbg(TYPE, f, a...) \
-do { if (vio->debug & VIO_DEBUG_##TYPE) \
- printk(KERN_INFO "vio: ID[%lu] " f, \
- vio->vdev->channel_id, ## a); \
-} while (0)
-
-extern int vio_register_driver(struct vio_driver *drv);
-extern void vio_unregister_driver(struct vio_driver *drv);
-
-static inline struct vio_driver *to_vio_driver(struct device_driver *drv)
-{
- return container_of(drv, struct vio_driver, driver);
-}
-
-static inline struct vio_dev *to_vio_dev(struct device *dev)
-{
- return container_of(dev, struct vio_dev, dev);
-}
-
-extern int vio_ldc_send(struct vio_driver_state *vio, void *data, int len);
-extern void vio_link_state_change(struct vio_driver_state *vio, int event);
-extern void vio_conn_reset(struct vio_driver_state *vio);
-extern int vio_control_pkt_engine(struct vio_driver_state *vio, void *pkt);
-extern int vio_validate_sid(struct vio_driver_state *vio,
- struct vio_msg_tag *tp);
-extern u32 vio_send_sid(struct vio_driver_state *vio);
-extern int vio_ldc_alloc(struct vio_driver_state *vio,
- struct ldc_channel_config *base_cfg, void *event_arg);
-extern void vio_ldc_free(struct vio_driver_state *vio);
-extern int vio_driver_init(struct vio_driver_state *vio, struct vio_dev *vdev,
- u8 dev_class, struct vio_version *ver_table,
- int ver_table_size, struct vio_driver_ops *ops,
- char *name);
-
-extern void vio_port_up(struct vio_driver_state *vio);
-
-#endif /* _SPARC64_VIO_H */
+++ /dev/null
-#ifndef _SPARC64_VISASM_H
-#define _SPARC64_VISASM_H
-
-/* visasm.h: FPU saving macros for VIS routines
- *
- * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
- */
-
-#include <asm/pstate.h>
-#include <asm/ptrace.h>
-
-/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
-
-#define VISEntry \
- rd %fprs, %o5; \
- andcc %o5, (FPRS_FEF|FPRS_DU), %g0; \
- be,pt %icc, 297f; \
- sethi %hi(297f), %g7; \
- sethi %hi(VISenter), %g1; \
- jmpl %g1 + %lo(VISenter), %g0; \
- or %g7, %lo(297f), %g7; \
-297: wr %g0, FPRS_FEF, %fprs; \
-
-#define VISExit \
- wr %g0, 0, %fprs;
-
-/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc.
- * Must preserve %o5 between VISEntryHalf and VISExitHalf */
-
-#define VISEntryHalf \
- rd %fprs, %o5; \
- andcc %o5, FPRS_FEF, %g0; \
- be,pt %icc, 297f; \
- sethi %hi(298f), %g7; \
- sethi %hi(VISenterhalf), %g1; \
- jmpl %g1 + %lo(VISenterhalf), %g0; \
- or %g7, %lo(298f), %g7; \
- clr %o5; \
-297: wr %o5, FPRS_FEF, %fprs; \
-298:
-
-#define VISExitHalf \
- wr %o5, 0, %fprs;
-
-#ifndef __ASSEMBLY__
-static inline void save_and_clear_fpu(void) {
- __asm__ __volatile__ (
-" rd %%fprs, %%o5\n"
-" andcc %%o5, %0, %%g0\n"
-" be,pt %%icc, 299f\n"
-" sethi %%hi(298f), %%g7\n"
-" sethi %%hi(VISenter), %%g1\n"
-" jmpl %%g1 + %%lo(VISenter), %%g0\n"
-" or %%g7, %%lo(298f), %%g7\n"
-" 298: wr %%g0, 0, %%fprs\n"
-" 299:\n"
-" " : : "i" (FPRS_FEF|FPRS_DU) :
- "o5", "g1", "g2", "g3", "g7", "cc");
-}
-#endif
-
-#endif /* _SPARC64_ASI_H */
+++ /dev/null
-/*
- *
- * watchdog - Driver interface for the hardware watchdog timers
- * present on Sun Microsystems boardsets
- *
- * Copyright (c) 2000 Eric Brower <ebrower@usa.net>
- *
- */
-
-#ifndef _SPARC64_WATCHDOG_H
-#define _SPARC64_WATCHDOG_H
-
-#include <linux/watchdog.h>
-
-/* Solaris compatibility ioctls--
- * Ref. <linux/watchdog.h> for standard linux watchdog ioctls
- */
-#define WIOCSTART _IO (WATCHDOG_IOCTL_BASE, 10) /* Start Timer */
-#define WIOCSTOP _IO (WATCHDOG_IOCTL_BASE, 11) /* Stop Timer */
-#define WIOCGSTAT _IOR(WATCHDOG_IOCTL_BASE, 12, int)/* Get Timer Status */
-
-/* Status flags from WIOCGSTAT ioctl
- */
-#define WD_FREERUN 0x01 /* timer is running, interrupts disabled */
-#define WD_EXPIRED 0x02 /* timer has expired */
-#define WD_RUNNING 0x04 /* timer is running, interrupts enabled */
-#define WD_STOPPED 0x08 /* timer has not been started */
-#define WD_SERVICED 0x10 /* timer interrupt was serviced */
-
-#endif /* ifndef _SPARC64_WATCHDOG_H */
-
+++ /dev/null
-/*
- * winmacro.h: Window loading-unloading macros.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_WINMACRO_H
-#define _SPARC_WINMACRO_H
-
-#include <asm/ptrace.h>
-
-/* Store the register window onto the 8-byte aligned area starting
- * at %reg. It might be %sp, it might not, we don't care.
- */
-#define STORE_WINDOW(reg) \
- std %l0, [%reg + RW_L0]; \
- std %l2, [%reg + RW_L2]; \
- std %l4, [%reg + RW_L4]; \
- std %l6, [%reg + RW_L6]; \
- std %i0, [%reg + RW_I0]; \
- std %i2, [%reg + RW_I2]; \
- std %i4, [%reg + RW_I4]; \
- std %i6, [%reg + RW_I6];
-
-/* Load a register window from the area beginning at %reg. */
-#define LOAD_WINDOW(reg) \
- ldd [%reg + RW_L0], %l0; \
- ldd [%reg + RW_L2], %l2; \
- ldd [%reg + RW_L4], %l4; \
- ldd [%reg + RW_L6], %l6; \
- ldd [%reg + RW_I0], %i0; \
- ldd [%reg + RW_I2], %i2; \
- ldd [%reg + RW_I4], %i4; \
- ldd [%reg + RW_I6], %i6;
-
-/* Loading and storing struct pt_reg trap frames. */
-#define LOAD_PT_INS(base_reg) \
- ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
- ldd [%base_reg + STACKFRAME_SZ + PT_I2], %i2; \
- ldd [%base_reg + STACKFRAME_SZ + PT_I4], %i4; \
- ldd [%base_reg + STACKFRAME_SZ + PT_I6], %i6;
-
-#define LOAD_PT_GLOBALS(base_reg) \
- ld [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \
- ldd [%base_reg + STACKFRAME_SZ + PT_G2], %g2; \
- ldd [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \
- ldd [%base_reg + STACKFRAME_SZ + PT_G6], %g6;
-
-#define LOAD_PT_YREG(base_reg, scratch) \
- ld [%base_reg + STACKFRAME_SZ + PT_Y], %scratch; \
- wr %scratch, 0x0, %y;
-
-#define LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
- ld [%base_reg + STACKFRAME_SZ + PT_PSR], %pt_psr; \
- ld [%base_reg + STACKFRAME_SZ + PT_PC], %pt_pc; \
- ld [%base_reg + STACKFRAME_SZ + PT_NPC], %pt_npc;
-
-#define LOAD_PT_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \
- LOAD_PT_YREG(base_reg, scratch) \
- LOAD_PT_INS(base_reg) \
- LOAD_PT_GLOBALS(base_reg) \
- LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc)
-
-#define STORE_PT_INS(base_reg) \
- std %i0, [%base_reg + STACKFRAME_SZ + PT_I0]; \
- std %i2, [%base_reg + STACKFRAME_SZ + PT_I2]; \
- std %i4, [%base_reg + STACKFRAME_SZ + PT_I4]; \
- std %i6, [%base_reg + STACKFRAME_SZ + PT_I6];
-
-#define STORE_PT_GLOBALS(base_reg) \
- st %g1, [%base_reg + STACKFRAME_SZ + PT_G1]; \
- std %g2, [%base_reg + STACKFRAME_SZ + PT_G2]; \
- std %g4, [%base_reg + STACKFRAME_SZ + PT_G4]; \
- std %g6, [%base_reg + STACKFRAME_SZ + PT_G6];
-
-#define STORE_PT_YREG(base_reg, scratch) \
- rd %y, %scratch; \
- st %scratch, [%base_reg + STACKFRAME_SZ + PT_Y];
-
-#define STORE_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
- st %pt_psr, [%base_reg + STACKFRAME_SZ + PT_PSR]; \
- st %pt_pc, [%base_reg + STACKFRAME_SZ + PT_PC]; \
- st %pt_npc, [%base_reg + STACKFRAME_SZ + PT_NPC];
-
-#define STORE_PT_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \
- STORE_PT_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \
- STORE_PT_GLOBALS(base_reg) \
- STORE_PT_YREG(base_reg, g_scratch) \
- STORE_PT_INS(base_reg)
-
-#define SAVE_BOLIXED_USER_STACK(cur_reg, scratch) \
- ld [%cur_reg + TI_W_SAVED], %scratch; \
- sll %scratch, 2, %scratch; \
- add %scratch, %cur_reg, %scratch; \
- st %sp, [%scratch + TI_RWIN_SPTRS]; \
- sub %scratch, %cur_reg, %scratch; \
- sll %scratch, 4, %scratch; \
- add %scratch, %cur_reg, %scratch; \
- STORE_WINDOW(scratch + TI_REG_WINDOW); \
- sub %scratch, %cur_reg, %scratch; \
- srl %scratch, 6, %scratch; \
- add %scratch, 1, %scratch; \
- st %scratch, [%cur_reg + TI_W_SAVED];
-
-#ifdef CONFIG_SMP
-#define LOAD_CURRENT4M(dest_reg, idreg) \
- rd %tbr, %idreg; \
- sethi %hi(current_set), %dest_reg; \
- srl %idreg, 10, %idreg; \
- or %dest_reg, %lo(current_set), %dest_reg; \
- and %idreg, 0xc, %idreg; \
- ld [%idreg + %dest_reg], %dest_reg;
-
-#define LOAD_CURRENT4D(dest_reg, idreg) \
- lda [%g0] ASI_M_VIKING_TMP1, %idreg; \
- sethi %hi(C_LABEL(current_set)), %dest_reg; \
- sll %idreg, 2, %idreg; \
- or %dest_reg, %lo(C_LABEL(current_set)), %dest_reg; \
- ld [%idreg + %dest_reg], %dest_reg;
-
-/* Blackbox - take care with this... - check smp4m and smp4d before changing this. */
-#define LOAD_CURRENT(dest_reg, idreg) \
- sethi %hi(___b_load_current), %idreg; \
- sethi %hi(current_set), %dest_reg; \
- sethi %hi(boot_cpu_id4), %idreg; \
- or %dest_reg, %lo(current_set), %dest_reg; \
- ldub [%idreg + %lo(boot_cpu_id4)], %idreg; \
- ld [%idreg + %dest_reg], %dest_reg;
-#else
-#define LOAD_CURRENT(dest_reg, idreg) \
- sethi %hi(current_set), %idreg; \
- ld [%idreg + %lo(current_set)], %dest_reg;
-#endif
-
-#endif /* !(_SPARC_WINMACRO_H) */
+++ /dev/null
-#ifndef ___ASM_SPARC_XOR_H
-#define ___ASM_SPARC_XOR_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm-sparc/xor_64.h>
-#else
-#include <asm-sparc/xor_32.h>
-#endif
-#endif
+++ /dev/null
-/*
- * include/asm-sparc/xor.h
- *
- * Optimized RAID-5 checksumming functions for 32-bit Sparc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * You should have received a copy of the GNU General Public License
- * (for example /usr/src/linux/COPYING); if not, write to the Free
- * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * High speed xor_block operation for RAID4/5 utilizing the
- * ldd/std SPARC instructions.
- *
- * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
- */
-
-static void
-sparc_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
-{
- int lines = bytes / (sizeof (long)) / 8;
-
- do {
- __asm__ __volatile__(
- "ldd [%0 + 0x00], %%g2\n\t"
- "ldd [%0 + 0x08], %%g4\n\t"
- "ldd [%0 + 0x10], %%o0\n\t"
- "ldd [%0 + 0x18], %%o2\n\t"
- "ldd [%1 + 0x00], %%o4\n\t"
- "ldd [%1 + 0x08], %%l0\n\t"
- "ldd [%1 + 0x10], %%l2\n\t"
- "ldd [%1 + 0x18], %%l4\n\t"
- "xor %%g2, %%o4, %%g2\n\t"
- "xor %%g3, %%o5, %%g3\n\t"
- "xor %%g4, %%l0, %%g4\n\t"
- "xor %%g5, %%l1, %%g5\n\t"
- "xor %%o0, %%l2, %%o0\n\t"
- "xor %%o1, %%l3, %%o1\n\t"
- "xor %%o2, %%l4, %%o2\n\t"
- "xor %%o3, %%l5, %%o3\n\t"
- "std %%g2, [%0 + 0x00]\n\t"
- "std %%g4, [%0 + 0x08]\n\t"
- "std %%o0, [%0 + 0x10]\n\t"
- "std %%o2, [%0 + 0x18]\n"
- :
- : "r" (p1), "r" (p2)
- : "g2", "g3", "g4", "g5",
- "o0", "o1", "o2", "o3", "o4", "o5",
- "l0", "l1", "l2", "l3", "l4", "l5");
- p1 += 8;
- p2 += 8;
- } while (--lines > 0);
-}
-
-static void
-sparc_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
- unsigned long *p3)
-{
- int lines = bytes / (sizeof (long)) / 8;
-
- do {
- __asm__ __volatile__(
- "ldd [%0 + 0x00], %%g2\n\t"
- "ldd [%0 + 0x08], %%g4\n\t"
- "ldd [%0 + 0x10], %%o0\n\t"
- "ldd [%0 + 0x18], %%o2\n\t"
- "ldd [%1 + 0x00], %%o4\n\t"
- "ldd [%1 + 0x08], %%l0\n\t"
- "ldd [%1 + 0x10], %%l2\n\t"
- "ldd [%1 + 0x18], %%l4\n\t"
- "xor %%g2, %%o4, %%g2\n\t"
- "xor %%g3, %%o5, %%g3\n\t"
- "ldd [%2 + 0x00], %%o4\n\t"
- "xor %%g4, %%l0, %%g4\n\t"
- "xor %%g5, %%l1, %%g5\n\t"
- "ldd [%2 + 0x08], %%l0\n\t"
- "xor %%o0, %%l2, %%o0\n\t"
- "xor %%o1, %%l3, %%o1\n\t"
- "ldd [%2 + 0x10], %%l2\n\t"
- "xor %%o2, %%l4, %%o2\n\t"
- "xor %%o3, %%l5, %%o3\n\t"
- "ldd [%2 + 0x18], %%l4\n\t"
- "xor %%g2, %%o4, %%g2\n\t"
- "xor %%g3, %%o5, %%g3\n\t"
- "xor %%g4, %%l0, %%g4\n\t"
- "xor %%g5, %%l1, %%g5\n\t"
- "xor %%o0, %%l2, %%o0\n\t"
- "xor %%o1, %%l3, %%o1\n\t"
- "xor %%o2, %%l4, %%o2\n\t"
- "xor %%o3, %%l5, %%o3\n\t"
- "std %%g2, [%0 + 0x00]\n\t"
- "std %%g4, [%0 + 0x08]\n\t"
- "std %%o0, [%0 + 0x10]\n\t"
- "std %%o2, [%0 + 0x18]\n"
- :
- : "r" (p1), "r" (p2), "r" (p3)
- : "g2", "g3", "g4", "g5",
- "o0", "o1", "o2", "o3", "o4", "o5",
- "l0", "l1", "l2", "l3", "l4", "l5");
- p1 += 8;
- p2 += 8;
- p3 += 8;
- } while (--lines > 0);
-}
-
-static void
-sparc_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
- unsigned long *p3, unsigned long *p4)
-{
- int lines = bytes / (sizeof (long)) / 8;
-
- do {
- __asm__ __volatile__(
- "ldd [%0 + 0x00], %%g2\n\t"
- "ldd [%0 + 0x08], %%g4\n\t"
- "ldd [%0 + 0x10], %%o0\n\t"
- "ldd [%0 + 0x18], %%o2\n\t"
- "ldd [%1 + 0x00], %%o4\n\t"
- "ldd [%1 + 0x08], %%l0\n\t"
- "ldd [%1 + 0x10], %%l2\n\t"
- "ldd [%1 + 0x18], %%l4\n\t"
- "xor %%g2, %%o4, %%g2\n\t"
- "xor %%g3, %%o5, %%g3\n\t"
- "ldd [%2 + 0x00], %%o4\n\t"
- "xor %%g4, %%l0, %%g4\n\t"
- "xor %%g5, %%l1, %%g5\n\t"
- "ldd [%2 + 0x08], %%l0\n\t"
- "xor %%o0, %%l2, %%o0\n\t"
- "xor %%o1, %%l3, %%o1\n\t"
- "ldd [%2 + 0x10], %%l2\n\t"
- "xor %%o2, %%l4, %%o2\n\t"
- "xor %%o3, %%l5, %%o3\n\t"
- "ldd [%2 + 0x18], %%l4\n\t"
- "xor %%g2, %%o4, %%g2\n\t"
- "xor %%g3, %%o5, %%g3\n\t"
- "ldd [%3 + 0x00], %%o4\n\t"
- "xor %%g4, %%l0, %%g4\n\t"
- "xor %%g5, %%l1, %%g5\n\t"
- "ldd [%3 + 0x08], %%l0\n\t"
- "xor %%o0, %%l2, %%o0\n\t"
- "xor %%o1, %%l3, %%o1\n\t"
- "ldd [%3 + 0x10], %%l2\n\t"
- "xor %%o2, %%l4, %%o2\n\t"
- "xor %%o3, %%l5, %%o3\n\t"
- "ldd [%3 + 0x18], %%l4\n\t"
- "xor %%g2, %%o4, %%g2\n\t"
- "xor %%g3, %%o5, %%g3\n\t"
- "xor %%g4, %%l0, %%g4\n\t"
- "xor %%g5, %%l1, %%g5\n\t"
- "xor %%o0, %%l2, %%o0\n\t"
- "xor %%o1, %%l3, %%o1\n\t"
- "xor %%o2, %%l4, %%o2\n\t"
- "xor %%o3, %%l5, %%o3\n\t"
- "std %%g2, [%0 + 0x00]\n\t"
- "std %%g4, [%0 + 0x08]\n\t"
- "std %%o0, [%0 + 0x10]\n\t"
- "std %%o2, [%0 + 0x18]\n"
- :
- : "r" (p1), "r" (p2), "r" (p3), "r" (p4)
- : "g2", "g3", "g4", "g5",
- "o0", "o1", "o2", "o3", "o4", "o5",
- "l0", "l1", "l2", "l3", "l4", "l5");
- p1 += 8;
- p2 += 8;
- p3 += 8;
- p4 += 8;
- } while (--lines > 0);
-}
-
-static void
-sparc_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
- unsigned long *p3, unsigned long *p4, unsigned long *p5)
-{
- int lines = bytes / (sizeof (long)) / 8;
-
- do {
- __asm__ __volatile__(
- "ldd [%0 + 0x00], %%g2\n\t"
- "ldd [%0 + 0x08], %%g4\n\t"
- "ldd [%0 + 0x10], %%o0\n\t"
- "ldd [%0 + 0x18], %%o2\n\t"
- "ldd [%1 + 0x00], %%o4\n\t"
- "ldd [%1 + 0x08], %%l0\n\t"
- "ldd [%1 + 0x10], %%l2\n\t"
- "ldd [%1 + 0x18], %%l4\n\t"
- "xor %%g2, %%o4, %%g2\n\t"
- "xor %%g3, %%o5, %%g3\n\t"
- "ldd [%2 + 0x00], %%o4\n\t"
- "xor %%g4, %%l0, %%g4\n\t"
- "xor %%g5, %%l1, %%g5\n\t"
- "ldd [%2 + 0x08], %%l0\n\t"
- "xor %%o0, %%l2, %%o0\n\t"
- "xor %%o1, %%l3, %%o1\n\t"
- "ldd [%2 + 0x10], %%l2\n\t"
- "xor %%o2, %%l4, %%o2\n\t"
- "xor %%o3, %%l5, %%o3\n\t"
- "ldd [%2 + 0x18], %%l4\n\t"
- "xor %%g2, %%o4, %%g2\n\t"
- "xor %%g3, %%o5, %%g3\n\t"
- "ldd [%3 + 0x00], %%o4\n\t"
- "xor %%g4, %%l0, %%g4\n\t"
- "xor %%g5, %%l1, %%g5\n\t"
- "ldd [%3 + 0x08], %%l0\n\t"
- "xor %%o0, %%l2, %%o0\n\t"
- "xor %%o1, %%l3, %%o1\n\t"
- "ldd [%3 + 0x10], %%l2\n\t"
- "xor %%o2, %%l4, %%o2\n\t"
- "xor %%o3, %%l5, %%o3\n\t"
- "ldd [%3 + 0x18], %%l4\n\t"
- "xor %%g2, %%o4, %%g2\n\t"
- "xor %%g3, %%o5, %%g3\n\t"
- "ldd [%4 + 0x00], %%o4\n\t"
- "xor %%g4, %%l0, %%g4\n\t"
- "xor %%g5, %%l1, %%g5\n\t"
- "ldd [%4 + 0x08], %%l0\n\t"
- "xor %%o0, %%l2, %%o0\n\t"
- "xor %%o1, %%l3, %%o1\n\t"
- "ldd [%4 + 0x10], %%l2\n\t"
- "xor %%o2, %%l4, %%o2\n\t"
- "xor %%o3, %%l5, %%o3\n\t"
- "ldd [%4 + 0x18], %%l4\n\t"
- "xor %%g2, %%o4, %%g2\n\t"
- "xor %%g3, %%o5, %%g3\n\t"
- "xor %%g4, %%l0, %%g4\n\t"
- "xor %%g5, %%l1, %%g5\n\t"
- "xor %%o0, %%l2, %%o0\n\t"
- "xor %%o1, %%l3, %%o1\n\t"
- "xor %%o2, %%l4, %%o2\n\t"
- "xor %%o3, %%l5, %%o3\n\t"
- "std %%g2, [%0 + 0x00]\n\t"
- "std %%g4, [%0 + 0x08]\n\t"
- "std %%o0, [%0 + 0x10]\n\t"
- "std %%o2, [%0 + 0x18]\n"
- :
- : "r" (p1), "r" (p2), "r" (p3), "r" (p4), "r" (p5)
- : "g2", "g3", "g4", "g5",
- "o0", "o1", "o2", "o3", "o4", "o5",
- "l0", "l1", "l2", "l3", "l4", "l5");
- p1 += 8;
- p2 += 8;
- p3 += 8;
- p4 += 8;
- p5 += 8;
- } while (--lines > 0);
-}
-
-static struct xor_block_template xor_block_SPARC = {
- .name = "SPARC",
- .do_2 = sparc_2,
- .do_3 = sparc_3,
- .do_4 = sparc_4,
- .do_5 = sparc_5,
-};
-
-/* For grins, also test the generic routines. */
-#include <asm-generic/xor.h>
-
-#undef XOR_TRY_TEMPLATES
-#define XOR_TRY_TEMPLATES \
- do { \
- xor_speed(&xor_block_8regs); \
- xor_speed(&xor_block_32regs); \
- xor_speed(&xor_block_SPARC); \
- } while (0)
+++ /dev/null
-/*
- * include/asm-sparc64/xor.h
- *
- * High speed xor_block operation for RAID4/5 utilizing the
- * UltraSparc Visual Instruction Set and Niagara block-init
- * twin-load instructions.
- *
- * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
- * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * You should have received a copy of the GNU General Public License
- * (for example /usr/src/linux/COPYING); if not, write to the Free
- * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <asm/spitfire.h>
-
-extern void xor_vis_2(unsigned long, unsigned long *, unsigned long *);
-extern void xor_vis_3(unsigned long, unsigned long *, unsigned long *,
- unsigned long *);
-extern void xor_vis_4(unsigned long, unsigned long *, unsigned long *,
- unsigned long *, unsigned long *);
-extern void xor_vis_5(unsigned long, unsigned long *, unsigned long *,
- unsigned long *, unsigned long *, unsigned long *);
-
-/* XXX Ugh, write cheetah versions... -DaveM */
-
-static struct xor_block_template xor_block_VIS = {
- .name = "VIS",
- .do_2 = xor_vis_2,
- .do_3 = xor_vis_3,
- .do_4 = xor_vis_4,
- .do_5 = xor_vis_5,
-};
-
-extern void xor_niagara_2(unsigned long, unsigned long *, unsigned long *);
-extern void xor_niagara_3(unsigned long, unsigned long *, unsigned long *,
- unsigned long *);
-extern void xor_niagara_4(unsigned long, unsigned long *, unsigned long *,
- unsigned long *, unsigned long *);
-extern void xor_niagara_5(unsigned long, unsigned long *, unsigned long *,
- unsigned long *, unsigned long *, unsigned long *);
-
-static struct xor_block_template xor_block_niagara = {
- .name = "Niagara",
- .do_2 = xor_niagara_2,
- .do_3 = xor_niagara_3,
- .do_4 = xor_niagara_4,
- .do_5 = xor_niagara_5,
-};
-
-#undef XOR_TRY_TEMPLATES
-#define XOR_TRY_TEMPLATES \
- do { \
- xor_speed(&xor_block_VIS); \
- xor_speed(&xor_block_niagara); \
- } while (0)
-
-/* For VIS for everything except Niagara. */
-#define XOR_SELECT_TEMPLATE(FASTEST) \
- ((tlb_type == hypervisor && \
- (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
- sun4v_chip_type == SUN4V_CHIP_NIAGARA2)) ? \
- &xor_block_niagara : \
- &xor_block_VIS)
+++ /dev/null
-# dummy file to avoid breaking make headers_install
+++ /dev/null
-#include <asm-sparc/agp.h>
+++ /dev/null
-#include <asm-sparc/apb.h>
+++ /dev/null
-#include <asm-sparc/asi.h>
+++ /dev/null
-#include <asm-sparc/atomic.h>
+++ /dev/null
-#include <asm-sparc/auxio.h>
+++ /dev/null
-#include <asm-sparc/auxvec.h>
+++ /dev/null
-#include <asm-sparc/backoff.h>
+++ /dev/null
-#include <asm-sparc/bbc.h>
+++ /dev/null
-#include <asm-sparc/bitops.h>
+++ /dev/null
-#include <asm-sparc/bpp.h>
+++ /dev/null
-#include <asm-sparc/bug.h>
+++ /dev/null
-#include <asm-sparc/bugs.h>
+++ /dev/null
-#include <asm-sparc/byteorder.h>
+++ /dev/null
-#include <asm-sparc/cache.h>
+++ /dev/null
-#include <asm-sparc/cacheflush.h>
+++ /dev/null
-#include <asm-sparc/chafsr.h>
+++ /dev/null
-#include <asm-sparc/checksum.h>
+++ /dev/null
-#include <asm-sparc/chmctrl.h>
+++ /dev/null
-#include <asm-sparc/cmt.h>
+++ /dev/null
-#include <asm-sparc/compat.h>
+++ /dev/null
-#include <asm-sparc/compat_signal.h>
+++ /dev/null
-#include <asm-sparc/cpudata.h>
+++ /dev/null
-#include <asm-sparc/cputime.h>
+++ /dev/null
-#include <asm-sparc/current.h>
+++ /dev/null
-#include <asm-sparc/dcr.h>
+++ /dev/null
-#include <asm-sparc/dcu.h>
+++ /dev/null
-#include <asm-sparc/delay.h>
+++ /dev/null
-#include <asm-sparc/device.h>
+++ /dev/null
-#include <asm-sparc/display7seg.h>
+++ /dev/null
-#include <asm-sparc/div64.h>
+++ /dev/null
-#include <asm-sparc/dma-mapping.h>
+++ /dev/null
-#include <asm-sparc/dma.h>
+++ /dev/null
-#include <asm-sparc/ebus.h>
+++ /dev/null
-#include <asm-sparc/elf.h>
+++ /dev/null
-#include <asm-sparc/emergency-restart.h>
+++ /dev/null
-#include <asm-sparc/envctrl.h>
+++ /dev/null
-#include <asm-sparc/errno.h>
+++ /dev/null
-#include <asm-sparc/estate.h>
+++ /dev/null
-#include <asm-sparc/fb.h>
+++ /dev/null
-#include <asm-sparc/fbio.h>
+++ /dev/null
-#include <asm-sparc/fcntl.h>
+++ /dev/null
-#include <asm-sparc/fhc.h>
+++ /dev/null
-#include <asm-sparc/floppy.h>
+++ /dev/null
-#include <asm-sparc/fpumacro.h>
+++ /dev/null
-#ifndef _ASM_SPARC64_FTRACE
-#define _ASM_SPARC64_FTRACE
-
-#ifdef CONFIG_MCOUNT
-#define MCOUNT_ADDR ((long)(_mcount))
-#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
-
-#ifndef __ASSEMBLY__
-extern void _mcount(void);
-#endif
-
-#endif
-
-#endif /* _ASM_SPARC64_FTRACE */
+++ /dev/null
-#include <asm-sparc/futex.h>
+++ /dev/null
-#include <asm-sparc/hardirq.h>
+++ /dev/null
-#include <asm-sparc/head.h>
+++ /dev/null
-#include <asm-sparc/hugetlb.h>
+++ /dev/null
-#include <asm-sparc/hvtramp.h>
+++ /dev/null
-#include <asm-sparc/hw_irq.h>
+++ /dev/null
-#include <asm-sparc/hypervisor.h>
+++ /dev/null
-#include <asm-sparc/ide.h>
+++ /dev/null
-#include <asm-sparc/idprom.h>
+++ /dev/null
-#include <asm-sparc/intr_queue.h>
+++ /dev/null
-#include <asm-sparc/io.h>
+++ /dev/null
-#include <asm-sparc/ioctl.h>
+++ /dev/null
-#include <asm-sparc/ioctls.h>
+++ /dev/null
-#include <asm-sparc/iommu.h>
+++ /dev/null
-#include <asm-sparc/ipcbuf.h>
+++ /dev/null
-#include <asm-sparc/irq.h>
+++ /dev/null
-#include <asm-sparc/irq_regs.h>
+++ /dev/null
-#include <asm-sparc/irqflags.h>
+++ /dev/null
-#include <asm-sparc/kdebug.h>
+++ /dev/null
-#include <asm-sparc/kgdb.h>
+++ /dev/null
-#include <asm-sparc/kmap_types.h>
+++ /dev/null
-#include <asm-sparc/kprobes.h>
+++ /dev/null
-#include <asm-sparc/ldc.h>
+++ /dev/null
-#include <asm-sparc/linkage.h>
+++ /dev/null
-#include <asm-sparc/lmb.h>
+++ /dev/null
-#include <asm-generic/local.h>
+++ /dev/null
-#include <asm-sparc/lsu.h>
+++ /dev/null
-#include <asm-sparc/mc146818rtc.h>
+++ /dev/null
-#include <asm-sparc/mdesc.h>
+++ /dev/null
-#include <asm-sparc/mman.h>
+++ /dev/null
-#include <asm-sparc/mmu.h>
+++ /dev/null
-#include <asm-sparc/mmu_context.h>
+++ /dev/null
-#include <asm-sparc/mmzone.h>
+++ /dev/null
-#include <asm-sparc/module.h>
+++ /dev/null
-#include <asm-sparc/mostek.h>
+++ /dev/null
-#include <asm-sparc/msgbuf.h>
+++ /dev/null
-#include <asm-sparc/mutex.h>
+++ /dev/null
-#include <asm-sparc/ns87303.h>
+++ /dev/null
-#include <asm-sparc/of_device.h>
+++ /dev/null
-#include <asm-sparc/of_platform.h>
+++ /dev/null
-#include <asm-sparc/openprom.h>
+++ /dev/null
-#include <asm-sparc/openpromio.h>
+++ /dev/null
-#include <asm-sparc/oplib.h>
+++ /dev/null
-#include <asm-sparc/page.h>
+++ /dev/null
-#include <asm-sparc/param.h>
+++ /dev/null
-#include <asm-sparc/parport.h>
+++ /dev/null
-#include <asm-sparc/pci.h>
+++ /dev/null
-#include <asm-sparc/percpu.h>
+++ /dev/null
-#include <asm-sparc/perfctr.h>
+++ /dev/null
-#include <asm-sparc/pgalloc.h>
+++ /dev/null
-#include <asm-sparc/pgtable.h>
+++ /dev/null
-#include <asm-sparc/pil.h>
+++ /dev/null
-#include <asm-sparc/poll.h>
+++ /dev/null
-#include <asm-sparc/posix_types.h>
+++ /dev/null
-#include <asm-sparc/processor.h>
+++ /dev/null
-#include <asm-sparc/prom.h>
+++ /dev/null
-#include <asm-sparc/psrcompat.h>
+++ /dev/null
-#include <asm-sparc/pstate.h>
+++ /dev/null
-#include <asm-sparc/ptrace.h>
+++ /dev/null
-#include <asm-sparc/reboot.h>
+++ /dev/null
-#include <asm-sparc/reg.h>
+++ /dev/null
-#include <asm-sparc/resource.h>
+++ /dev/null
-#include <asm-sparc/rtc.h>
+++ /dev/null
-#include <asm-sparc/rwsem-const.h>
+++ /dev/null
-#include <asm-sparc/rwsem.h>
+++ /dev/null
-#include <asm-sparc/sbus.h>
+++ /dev/null
-#include <asm-sparc/scatterlist.h>
+++ /dev/null
-#include <asm-sparc/scratchpad.h>
+++ /dev/null
-#include <asm-sparc/seccomp.h>
+++ /dev/null
-#include <asm-sparc/sections.h>
+++ /dev/null
-#include <asm-sparc/sembuf.h>
+++ /dev/null
-#include <asm-sparc/setup.h>
+++ /dev/null
-#include <asm-sparc/sfafsr.h>
+++ /dev/null
-#include <asm-sparc/sfp-machine.h>
+++ /dev/null
-#include <asm-sparc/shmbuf.h>
+++ /dev/null
-#include <asm-sparc/shmparam.h>
+++ /dev/null
-#include <asm-sparc/sigcontext.h>
+++ /dev/null
-#include <asm-sparc/siginfo.h>
+++ /dev/null
-#include <asm-sparc/signal.h>
+++ /dev/null
-#include <asm-sparc/smp.h>
+++ /dev/null
-#include <asm-sparc/socket.h>
+++ /dev/null
-#include <asm-sparc/sockios.h>
+++ /dev/null
-#include <asm-sparc/sparsemem.h>
+++ /dev/null
-#include <asm-sparc/spinlock.h>
+++ /dev/null
-#include <asm-sparc/spinlock_types.h>
+++ /dev/null
-#include <asm-sparc/spitfire.h>
+++ /dev/null
-#include <asm-sparc/sstate.h>
+++ /dev/null
-#include <asm-sparc/stacktrace.h>
+++ /dev/null
-#include <asm-sparc/starfire.h>
+++ /dev/null
-#include <asm-sparc/stat.h>
+++ /dev/null
-#include <asm-sparc/statfs.h>
+++ /dev/null
-#include <asm-sparc/string.h>
+++ /dev/null
-#include <asm-sparc/sunbpp.h>
+++ /dev/null
-#include <asm-sparc/syscalls.h>
+++ /dev/null
-#include <asm-sparc/system.h>
+++ /dev/null
-#include <asm-sparc/termbits.h>
+++ /dev/null
-#include <asm-sparc/termios.h>
+++ /dev/null
-#include <asm-sparc/thread_info.h>
+++ /dev/null
-#include <asm-sparc/timer.h>
+++ /dev/null
-#include <asm-sparc/timex.h>
+++ /dev/null
-#include <asm-sparc/tlb.h>
+++ /dev/null
-#include <asm-sparc/tlbflush.h>
+++ /dev/null
-#include <asm-sparc/topology.h>
+++ /dev/null
-#include <asm-sparc/tsb.h>
+++ /dev/null
-#include <asm-sparc/ttable.h>
+++ /dev/null
-#include <asm-sparc/types.h>
+++ /dev/null
-#include <asm-sparc/uaccess.h>
+++ /dev/null
-#include <asm-sparc/uctx.h>
+++ /dev/null
-#include <asm-sparc/unaligned.h>
+++ /dev/null
-#include <asm-sparc/unistd.h>
+++ /dev/null
-#include <asm-sparc/upa.h>
+++ /dev/null
-#include <asm-sparc/user.h>
+++ /dev/null
-#include <asm-sparc/utrap.h>
+++ /dev/null
-#include <asm-sparc/vga.h>
+++ /dev/null
-#include <asm-sparc/vio.h>
+++ /dev/null
-#include <asm-sparc/visasm.h>
+++ /dev/null
-#include <asm-sparc/watchdog.h>
+++ /dev/null
-#include <asm-sparc/xor.h>
unsigned long nvcsw, nivcsw, cnvcsw, cnivcsw;
unsigned long min_flt, maj_flt, cmin_flt, cmaj_flt;
unsigned long inblock, oublock, cinblock, coublock;
- struct proc_io_accounting ioac;
+ struct task_io_accounting ioac;
/*
* Cumulative ns of scheduled CPU time for dead threads in the
unsigned long ptrace_message;
siginfo_t *last_siginfo; /* For ptrace use. */
- struct proc_io_accounting ioac;
+ struct task_io_accounting ioac;
#if defined(CONFIG_TASK_XACCT)
u64 acct_rss_mem1; /* accumulated rss usage */
u64 acct_vm_mem1; /* accumulated virtual memory usage */
#ifdef CONFIG_TASK_XACCT
static inline void add_rchar(struct task_struct *tsk, ssize_t amt)
{
- tsk->ioac.chr.rchar += amt;
+ tsk->ioac.rchar += amt;
}
static inline void add_wchar(struct task_struct *tsk, ssize_t amt)
{
- tsk->ioac.chr.wchar += amt;
+ tsk->ioac.wchar += amt;
}
static inline void inc_syscr(struct task_struct *tsk)
{
- tsk->ioac.chr.syscr++;
+ tsk->ioac.syscr++;
}
static inline void inc_syscw(struct task_struct *tsk)
{
- tsk->ioac.chr.syscw++;
+ tsk->ioac.syscw++;
}
#else
static inline void add_rchar(struct task_struct *tsk, ssize_t amt)
/*
- * proc_io_accounting: a structure which is used for recording a single task's
+ * task_io_accounting: a structure which is used for recording a single task's
* IO statistics.
*
* Don't include this header file directly - it is designed to be dragged in via
* Blame akpm@osdl.org for all this.
*/
+struct task_io_accounting {
#ifdef CONFIG_TASK_XACCT
-struct task_chr_io_accounting {
/* bytes read */
u64 rchar;
/* bytes written */
u64 syscr;
/* # of write syscalls */
u64 syscw;
-};
-#else /* CONFIG_TASK_XACCT */
-struct task_chr_io_accounting {
-};
#endif /* CONFIG_TASK_XACCT */
#ifdef CONFIG_TASK_IO_ACCOUNTING
-struct task_io_accounting {
/*
* The number of bytes which this task has caused to be read from
* storage.
* information loss in doing that.
*/
u64 cancelled_write_bytes;
-};
-#else /* CONFIG_TASK_IO_ACCOUNTING */
-struct task_io_accounting {
-};
#endif /* CONFIG_TASK_IO_ACCOUNTING */
-
-struct proc_io_accounting {
- struct task_chr_io_accounting chr;
- struct task_io_accounting blk;
};
#ifdef CONFIG_TASK_IO_ACCOUNTING
static inline void task_io_account_read(size_t bytes)
{
- current->ioac.blk.read_bytes += bytes;
+ current->ioac.read_bytes += bytes;
}
/*
*/
static inline unsigned long task_io_get_inblock(const struct task_struct *p)
{
- return p->ioac.blk.read_bytes >> 9;
+ return p->ioac.read_bytes >> 9;
}
static inline void task_io_account_write(size_t bytes)
{
- current->ioac.blk.write_bytes += bytes;
+ current->ioac.write_bytes += bytes;
}
/*
*/
static inline unsigned long task_io_get_oublock(const struct task_struct *p)
{
- return p->ioac.blk.write_bytes >> 9;
+ return p->ioac.write_bytes >> 9;
}
static inline void task_io_account_cancelled_write(size_t bytes)
{
- current->ioac.blk.cancelled_write_bytes += bytes;
+ current->ioac.cancelled_write_bytes += bytes;
}
-static inline void task_io_accounting_init(struct proc_io_accounting *ioac)
+static inline void task_io_accounting_init(struct task_io_accounting *ioac)
{
memset(ioac, 0, sizeof(*ioac));
}
-static inline void task_blk_io_accounting_add(struct proc_io_accounting *dst,
- struct proc_io_accounting *src)
+static inline void task_blk_io_accounting_add(struct task_io_accounting *dst,
+ struct task_io_accounting *src)
{
- dst->blk.read_bytes += src->blk.read_bytes;
- dst->blk.write_bytes += src->blk.write_bytes;
- dst->blk.cancelled_write_bytes += src->blk.cancelled_write_bytes;
+ dst->read_bytes += src->read_bytes;
+ dst->write_bytes += src->write_bytes;
+ dst->cancelled_write_bytes += src->cancelled_write_bytes;
}
#else
{
}
-static inline void task_io_accounting_init(struct proc_io_accounting *ioac)
+static inline void task_io_accounting_init(struct task_io_accounting *ioac)
{
}
-static inline void task_blk_io_accounting_add(struct proc_io_accounting *dst,
- struct proc_io_accounting *src)
+static inline void task_blk_io_accounting_add(struct task_io_accounting *dst,
+ struct task_io_accounting *src)
{
}
#endif /* CONFIG_TASK_IO_ACCOUNTING */
#ifdef CONFIG_TASK_XACCT
-static inline void task_chr_io_accounting_add(struct proc_io_accounting *dst,
- struct proc_io_accounting *src)
+static inline void task_chr_io_accounting_add(struct task_io_accounting *dst,
+ struct task_io_accounting *src)
{
- dst->chr.rchar += src->chr.rchar;
- dst->chr.wchar += src->chr.wchar;
- dst->chr.syscr += src->chr.syscr;
- dst->chr.syscw += src->chr.syscw;
+ dst->rchar += src->rchar;
+ dst->wchar += src->wchar;
+ dst->syscr += src->syscr;
+ dst->syscw += src->syscw;
}
#else
-static inline void task_chr_io_accounting_add(struct proc_io_accounting *dst,
- struct proc_io_accounting *src)
+static inline void task_chr_io_accounting_add(struct task_io_accounting *dst,
+ struct task_io_accounting *src)
{
}
#endif /* CONFIG_TASK_XACCT */
-static inline void task_io_accounting_add(struct proc_io_accounting *dst,
- struct proc_io_accounting *src)
+static inline void task_io_accounting_add(struct task_io_accounting *dst,
+ struct task_io_accounting *src)
{
task_chr_io_accounting_add(dst, src);
task_blk_io_accounting_add(dst, src);
#if defined(CONFIG_VIDEO_V4L1_COMPAT) || !defined (__KERNEL__)
+#define VID_TYPE_CAPTURE 1 /* Can capture */
+#define VID_TYPE_TUNER 2 /* Can tune */
+#define VID_TYPE_TELETEXT 4 /* Does teletext */
+#define VID_TYPE_OVERLAY 8 /* Overlay onto frame buffer */
+#define VID_TYPE_CHROMAKEY 16 /* Overlay by chromakey */
+#define VID_TYPE_CLIPPING 32 /* Can clip */
+#define VID_TYPE_FRAMERAM 64 /* Uses the frame buffer memory */
+#define VID_TYPE_SCALES 128 /* Scalable */
+#define VID_TYPE_MONOCHROME 256 /* Monochrome only */
+#define VID_TYPE_SUBCAPTURE 512 /* Can capture subareas of the image */
+#define VID_TYPE_MPEG_DECODER 1024 /* Can decode MPEG streams */
+#define VID_TYPE_MPEG_ENCODER 2048 /* Can encode MPEG streams */
+#define VID_TYPE_MJPEG_DECODER 4096 /* Can decode MJPEG streams */
+#define VID_TYPE_MJPEG_ENCODER 8192 /* Can encode MJPEG streams */
+
struct video_capability
{
char name[32];
*/
#define VIDEO_MAX_FRAME 32
+#ifndef __KERNEL__
+
+/* These defines are V4L1 specific and should not be used with the V4L2 API!
+ They will be removed from this header in the future. */
+
#define VID_TYPE_CAPTURE 1 /* Can capture */
#define VID_TYPE_TUNER 2 /* Can tune */
#define VID_TYPE_TELETEXT 4 /* Does teletext */
#define VID_TYPE_MPEG_ENCODER 2048 /* Can encode MPEG streams */
#define VID_TYPE_MJPEG_DECODER 4096 /* Can decode MJPEG streams */
#define VID_TYPE_MJPEG_ENCODER 8192 /* Can encode MJPEG streams */
+#endif
/*
* M I S C E L L A N E O U S
*/
/* Four-character-code (FOURCC) */
-#define v4l2_fourcc(a,b,c,d)\
- (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
+#define v4l2_fourcc(a, b, c, d)\
+ ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24))
/*
* E N U M S
/*
* D R I V E R C A P A B I L I T I E S
*/
-struct v4l2_capability
-{
+struct v4l2_capability {
__u8 driver[16]; /* i.e. "bttv" */
__u8 card[32]; /* i.e. "Hauppauge WinTV" */
__u8 bus_info[32]; /* "PCI:" + pci_name(pci_dev) */
/*
* V I D E O I M A G E F O R M A T
*/
-struct v4l2_pix_format
-{
+struct v4l2_pix_format {
__u32 width;
__u32 height;
__u32 pixelformat;
};
/* Pixel format FOURCC depth Description */
-#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R','G','B','1') /* 8 RGB-3-3-2 */
-#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R','4','4','4') /* 16 xxxxrrrr ggggbbbb */
-#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R','G','B','O') /* 16 RGB-5-5-5 */
-#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R','G','B','P') /* 16 RGB-5-6-5 */
-#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R','G','B','Q') /* 16 RGB-5-5-5 BE */
-#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R','G','B','R') /* 16 RGB-5-6-5 BE */
-#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B','G','R','3') /* 24 BGR-8-8-8 */
-#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R','G','B','3') /* 24 RGB-8-8-8 */
-#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B','G','R','4') /* 32 BGR-8-8-8-8 */
-#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R','G','B','4') /* 32 RGB-8-8-8-8 */
-#define V4L2_PIX_FMT_GREY v4l2_fourcc('G','R','E','Y') /* 8 Greyscale */
-#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y','1','6',' ') /* 16 Greyscale */
-#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P','A','L','8') /* 8 8-bit palette */
-#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y','V','U','9') /* 9 YVU 4:1:0 */
-#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y','V','1','2') /* 12 YVU 4:2:0 */
-#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y','U','Y','V') /* 16 YUV 4:2:2 */
-#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U','Y','V','Y') /* 16 YUV 4:2:2 */
-#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4','2','2','P') /* 16 YVU422 planar */
-#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4','1','1','P') /* 16 YVU411 planar */
-#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y','4','1','P') /* 12 YUV 4:1:1 */
-#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y','4','4','4') /* 16 xxxxyyyy uuuuvvvv */
-#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y','U','V','O') /* 16 YUV-5-5-5 */
-#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y','U','V','P') /* 16 YUV-5-6-5 */
-#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y','U','V','4') /* 32 YUV-8-8-8-8 */
+#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1') /* 8 RGB-3-3-2 */
+#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4') /* 16 xxxxrrrr ggggbbbb */
+#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O') /* 16 RGB-5-5-5 */
+#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R', 'G', 'B', 'P') /* 16 RGB-5-6-5 */
+#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') /* 16 RGB-5-5-5 BE */
+#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16 RGB-5-6-5 BE */
+#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') /* 24 BGR-8-8-8 */
+#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') /* 24 RGB-8-8-8 */
+#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') /* 32 BGR-8-8-8-8 */
+#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') /* 32 RGB-8-8-8-8 */
+#define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */
+#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */
+#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') /* 8 8-bit palette */
+#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y', 'V', 'U', '9') /* 9 YVU 4:1:0 */
+#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y', 'V', '1', '2') /* 12 YVU 4:2:0 */
+#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y', 'U', 'Y', 'V') /* 16 YUV 4:2:2 */
+#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U', 'Y', 'V', 'Y') /* 16 YUV 4:2:2 */
+#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P') /* 16 YVU422 planar */
+#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P') /* 16 YVU411 planar */
+#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P') /* 12 YUV 4:1:1 */
+#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') /* 16 xxxxyyyy uuuuvvvv */
+#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') /* 16 YUV-5-5-5 */
+#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') /* 16 YUV-5-6-5 */
+#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') /* 32 YUV-8-8-8-8 */
/* two planes -- one Y, one Cr + Cb interleaved */
-#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N','V','1','2') /* 12 Y/CbCr 4:2:0 */
-#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N','V','2','1') /* 12 Y/CrCb 4:2:0 */
+#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
+#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */
/* The following formats are not defined in the V4L2 specification */
-#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y','U','V','9') /* 9 YUV 4:1:0 */
-#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y','U','1','2') /* 12 YUV 4:2:0 */
-#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y','Y','U','V') /* 16 YUV 4:2:2 */
-#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H','I','2','4') /* 8 8-bit color */
-#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H','M','1','2') /* 8 YUV 4:2:0 16x16 macroblocks */
+#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y', 'U', 'V', '9') /* 9 YUV 4:1:0 */
+#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y', 'U', '1', '2') /* 12 YUV 4:2:0 */
+#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y', 'Y', 'U', 'V') /* 16 YUV 4:2:2 */
+#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */
+#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */
/* see http://www.siliconimaging.com/RGB%20Bayer.htm */
-#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B','A','8','1') /* 8 BGBG.. GRGR.. */
-#define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G','B','R','G') /* 8 GBGB.. RGRG.. */
-#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B','Y','R','2') /* 16 BGBG.. GRGR.. */
+#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') /* 8 BGBG.. GRGR.. */
+#define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G', 'B', 'R', 'G') /* 8 GBGB.. RGRG.. */
+#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') /* 16 BGBG.. GRGR.. */
/* compressed formats */
-#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M','J','P','G') /* Motion-JPEG */
-#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J','P','E','G') /* JFIF JPEG */
-#define V4L2_PIX_FMT_DV v4l2_fourcc('d','v','s','d') /* 1394 */
-#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M','P','E','G') /* MPEG-1/2/4 */
+#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG */
+#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G') /* JFIF JPEG */
+#define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd') /* 1394 */
+#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G') /* MPEG-1/2/4 */
/* Vendor-specific formats */
-#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W','N','V','A') /* Winnov hw compress */
-#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S','9','1','0') /* SN9C10x compression */
-#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P','W','C','1') /* pwc older webcam */
-#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P','W','C','2') /* pwc newer webcam */
-#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E','6','2','5') /* ET61X251 compression */
-#define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S','5','0','1') /* YUYV per line */
-#define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S','5','6','1') /* compressed GBRG bayer */
-#define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P','2','0','7') /* compressed BGGR bayer */
+#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W', 'N', 'V', 'A') /* Winnov hw compress */
+#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S', '9', '1', '0') /* SN9C10x compression */
+#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P', 'W', 'C', '1') /* pwc older webcam */
+#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P', 'W', 'C', '2') /* pwc newer webcam */
+#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E', '6', '2', '5') /* ET61X251 compression */
+#define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S', '5', '0', '1') /* YUYV per line */
+#define V4L2_PIX_FMT_SPCA505 v4l2_fourcc('S', '5', '0', '5') /* YYUV per line */
+#define V4L2_PIX_FMT_SPCA508 v4l2_fourcc('S', '5', '0', '8') /* YUVY per line */
+#define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S', '5', '6', '1') /* compressed GBRG bayer */
+#define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P', '2', '0', '7') /* compressed BGGR bayer */
/*
* F O R M A T E N U M E R A T I O N
*/
-struct v4l2_fmtdesc
-{
+struct v4l2_fmtdesc {
__u32 index; /* Format number */
enum v4l2_buf_type type; /* buffer type */
__u32 flags;
/*
* F R A M E S I Z E E N U M E R A T I O N
*/
-enum v4l2_frmsizetypes
-{
+enum v4l2_frmsizetypes {
V4L2_FRMSIZE_TYPE_DISCRETE = 1,
V4L2_FRMSIZE_TYPE_CONTINUOUS = 2,
V4L2_FRMSIZE_TYPE_STEPWISE = 3,
};
-struct v4l2_frmsize_discrete
-{
+struct v4l2_frmsize_discrete {
__u32 width; /* Frame width [pixel] */
__u32 height; /* Frame height [pixel] */
};
-struct v4l2_frmsize_stepwise
-{
+struct v4l2_frmsize_stepwise {
__u32 min_width; /* Minimum frame width [pixel] */
__u32 max_width; /* Maximum frame width [pixel] */
__u32 step_width; /* Frame width step size [pixel] */
__u32 step_height; /* Frame height step size [pixel] */
};
-struct v4l2_frmsizeenum
-{
+struct v4l2_frmsizeenum {
__u32 index; /* Frame size number */
__u32 pixel_format; /* Pixel format */
__u32 type; /* Frame size type the device supports. */
/*
* F R A M E R A T E E N U M E R A T I O N
*/
-enum v4l2_frmivaltypes
-{
+enum v4l2_frmivaltypes {
V4L2_FRMIVAL_TYPE_DISCRETE = 1,
V4L2_FRMIVAL_TYPE_CONTINUOUS = 2,
V4L2_FRMIVAL_TYPE_STEPWISE = 3,
};
-struct v4l2_frmival_stepwise
-{
+struct v4l2_frmival_stepwise {
struct v4l2_fract min; /* Minimum frame interval [s] */
struct v4l2_fract max; /* Maximum frame interval [s] */
struct v4l2_fract step; /* Frame interval step size [s] */
};
-struct v4l2_frmivalenum
-{
+struct v4l2_frmivalenum {
__u32 index; /* Frame format index */
__u32 pixel_format; /* Pixel format */
__u32 width; /* Frame width */
/*
* T I M E C O D E
*/
-struct v4l2_timecode
-{
+struct v4l2_timecode {
__u32 type;
__u32 flags;
__u8 frames;
#define V4L2_TC_USERBITS_8BITCHARS 0x0008
/* The above is based on SMPTE timecodes */
-struct v4l2_jpegcompression
-{
+struct v4l2_jpegcompression {
int quality;
int APPn; /* Number of APP segment to be written,
/*
* M E M O R Y - M A P P I N G B U F F E R S
*/
-struct v4l2_requestbuffers
-{
+struct v4l2_requestbuffers {
__u32 count;
enum v4l2_buf_type type;
enum v4l2_memory memory;
__u32 reserved[2];
};
-struct v4l2_buffer
-{
+struct v4l2_buffer {
__u32 index;
enum v4l2_buf_type type;
__u32 bytesused;
/*
* O V E R L A Y P R E V I E W
*/
-struct v4l2_framebuffer
-{
+struct v4l2_framebuffer {
__u32 capability;
__u32 flags;
/* FIXME: in theory we should pass something like PCI device + memory
* region + offset instead of some physical address */
- void* base;
+ void *base;
struct v4l2_pix_format fmt;
};
/* Flags for the 'capability' field. Read only */
#define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010
#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020
-struct v4l2_clip
-{
+struct v4l2_clip {
struct v4l2_rect c;
struct v4l2_clip __user *next;
};
-struct v4l2_window
-{
+struct v4l2_window {
struct v4l2_rect w;
enum v4l2_field field;
__u32 chromakey;
/*
* C A P T U R E P A R A M E T E R S
*/
-struct v4l2_captureparm
-{
+struct v4l2_captureparm {
__u32 capability; /* Supported modes */
__u32 capturemode; /* Current mode */
struct v4l2_fract timeperframe; /* Time per frame in .1us units */
#define V4L2_MODE_HIGHQUALITY 0x0001 /* High quality imaging mode */
#define V4L2_CAP_TIMEPERFRAME 0x1000 /* timeperframe field is supported */
-struct v4l2_outputparm
-{
+struct v4l2_outputparm {
__u32 capability; /* Supported modes */
__u32 outputmode; /* Current mode */
struct v4l2_fract timeperframe; /* Time per frame in seconds */
#define V4L2_STD_ALL (V4L2_STD_525_60 |\
V4L2_STD_625_50)
-struct v4l2_standard
-{
+struct v4l2_standard {
__u32 index;
v4l2_std_id id;
__u8 name[24];
/*
* V I D E O I N P U T S
*/
-struct v4l2_input
-{
+struct v4l2_input {
__u32 index; /* Which input */
__u8 name[32]; /* Label */
__u32 type; /* Type of input */
/*
* V I D E O O U T P U T S
*/
-struct v4l2_output
-{
+struct v4l2_output {
__u32 index; /* Which output */
__u8 name[32]; /* Label */
__u32 type; /* Type of output */
/*
* C O N T R O L S
*/
-struct v4l2_control
-{
+struct v4l2_control {
__u32 id;
__s32 value;
};
-struct v4l2_ext_control
-{
+struct v4l2_ext_control {
__u32 id;
__u32 reserved2[2];
union {
};
} __attribute__ ((packed));
-struct v4l2_ext_controls
-{
+struct v4l2_ext_controls {
__u32 ctrl_class;
__u32 count;
__u32 error_idx;
#define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000)
/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */
-struct v4l2_queryctrl
-{
+struct v4l2_queryctrl {
__u32 id;
enum v4l2_ctrl_type type;
__u8 name[32]; /* Whatever */
};
/* Used in the VIDIOC_QUERYMENU ioctl for querying menu items */
-struct v4l2_querymenu
-{
+struct v4l2_querymenu {
__u32 id;
__u32 index;
__u8 name[32]; /* Whatever */
/*
* T U N I N G
*/
-struct v4l2_tuner
-{
+struct v4l2_tuner {
__u32 index;
__u8 name[32];
enum v4l2_tuner_type type;
__u32 reserved[4];
};
-struct v4l2_modulator
-{
+struct v4l2_modulator {
__u32 index;
__u8 name[32];
__u32 capability;
#define V4L2_TUNER_MODE_LANG1 0x0003
#define V4L2_TUNER_MODE_LANG1_LANG2 0x0004
-struct v4l2_frequency
-{
+struct v4l2_frequency {
__u32 tuner;
enum v4l2_tuner_type type;
__u32 frequency;
/*
* A U D I O
*/
-struct v4l2_audio
-{
+struct v4l2_audio {
__u32 index;
__u8 name[32];
__u32 capability;
/* Flags for the 'mode' field */
#define V4L2_AUDMODE_AVL 0x00001
-struct v4l2_audioout
-{
+struct v4l2_audioout {
__u32 index;
__u8 name[32];
__u32 capability;
*/
/* Raw VBI */
-struct v4l2_vbi_format
-{
+struct v4l2_vbi_format {
__u32 sampling_rate; /* in 1 Hz */
__u32 offset;
__u32 samples_per_line;
};
/* VBI flags */
-#define V4L2_VBI_UNSYNC (1<< 0)
-#define V4L2_VBI_INTERLACED (1<< 1)
+#define V4L2_VBI_UNSYNC (1 << 0)
+#define V4L2_VBI_INTERLACED (1 << 1)
/* Sliced VBI
*
* notice in the definitive implementation.
*/
-struct v4l2_sliced_vbi_format
-{
+struct v4l2_sliced_vbi_format {
__u16 service_set;
/* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field
service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field
#define V4L2_SLICED_VBI_525 (V4L2_SLICED_CAPTION_525)
#define V4L2_SLICED_VBI_625 (V4L2_SLICED_TELETEXT_B | V4L2_SLICED_VPS | V4L2_SLICED_WSS_625)
-struct v4l2_sliced_vbi_cap
-{
+struct v4l2_sliced_vbi_cap {
__u16 service_set;
/* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field
service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field
__u32 reserved[3]; /* must be 0 */
};
-struct v4l2_sliced_vbi_data
-{
+struct v4l2_sliced_vbi_data {
__u32 id;
__u32 field; /* 0: first field, 1: second field */
__u32 line; /* 1-23 */
/* Stream data format
*/
-struct v4l2_format
-{
+struct v4l2_format {
enum v4l2_buf_type type;
- union
- {
- struct v4l2_pix_format pix; // V4L2_BUF_TYPE_VIDEO_CAPTURE
- struct v4l2_window win; // V4L2_BUF_TYPE_VIDEO_OVERLAY
- struct v4l2_vbi_format vbi; // V4L2_BUF_TYPE_VBI_CAPTURE
- struct v4l2_sliced_vbi_format sliced; // V4L2_BUF_TYPE_SLICED_VBI_CAPTURE
- __u8 raw_data[200]; // user-defined
+ union {
+ struct v4l2_pix_format pix; /* V4L2_BUF_TYPE_VIDEO_CAPTURE */
+ struct v4l2_window win; /* V4L2_BUF_TYPE_VIDEO_OVERLAY */
+ struct v4l2_vbi_format vbi; /* V4L2_BUF_TYPE_VBI_CAPTURE */
+ struct v4l2_sliced_vbi_format sliced; /* V4L2_BUF_TYPE_SLICED_VBI_CAPTURE */
+ __u8 raw_data[200]; /* user-defined */
} fmt;
};
/* Stream type-dependent parameters
*/
-struct v4l2_streamparm
-{
+struct v4l2_streamparm {
enum v4l2_buf_type type;
- union
- {
+ union {
struct v4l2_captureparm capture;
struct v4l2_outputparm output;
__u8 raw_data[200]; /* user-defined */
* I O C T L C O D E S F O R V I D E O D E V I C E S
*
*/
-#define VIDIOC_QUERYCAP _IOR ('V', 0, struct v4l2_capability)
-#define VIDIOC_RESERVED _IO ('V', 1)
-#define VIDIOC_ENUM_FMT _IOWR ('V', 2, struct v4l2_fmtdesc)
-#define VIDIOC_G_FMT _IOWR ('V', 4, struct v4l2_format)
-#define VIDIOC_S_FMT _IOWR ('V', 5, struct v4l2_format)
-#define VIDIOC_REQBUFS _IOWR ('V', 8, struct v4l2_requestbuffers)
-#define VIDIOC_QUERYBUF _IOWR ('V', 9, struct v4l2_buffer)
-#define VIDIOC_G_FBUF _IOR ('V', 10, struct v4l2_framebuffer)
-#define VIDIOC_S_FBUF _IOW ('V', 11, struct v4l2_framebuffer)
-#define VIDIOC_OVERLAY _IOW ('V', 14, int)
-#define VIDIOC_QBUF _IOWR ('V', 15, struct v4l2_buffer)
-#define VIDIOC_DQBUF _IOWR ('V', 17, struct v4l2_buffer)
-#define VIDIOC_STREAMON _IOW ('V', 18, int)
-#define VIDIOC_STREAMOFF _IOW ('V', 19, int)
-#define VIDIOC_G_PARM _IOWR ('V', 21, struct v4l2_streamparm)
-#define VIDIOC_S_PARM _IOWR ('V', 22, struct v4l2_streamparm)
-#define VIDIOC_G_STD _IOR ('V', 23, v4l2_std_id)
-#define VIDIOC_S_STD _IOW ('V', 24, v4l2_std_id)
-#define VIDIOC_ENUMSTD _IOWR ('V', 25, struct v4l2_standard)
-#define VIDIOC_ENUMINPUT _IOWR ('V', 26, struct v4l2_input)
-#define VIDIOC_G_CTRL _IOWR ('V', 27, struct v4l2_control)
-#define VIDIOC_S_CTRL _IOWR ('V', 28, struct v4l2_control)
-#define VIDIOC_G_TUNER _IOWR ('V', 29, struct v4l2_tuner)
-#define VIDIOC_S_TUNER _IOW ('V', 30, struct v4l2_tuner)
-#define VIDIOC_G_AUDIO _IOR ('V', 33, struct v4l2_audio)
-#define VIDIOC_S_AUDIO _IOW ('V', 34, struct v4l2_audio)
-#define VIDIOC_QUERYCTRL _IOWR ('V', 36, struct v4l2_queryctrl)
-#define VIDIOC_QUERYMENU _IOWR ('V', 37, struct v4l2_querymenu)
-#define VIDIOC_G_INPUT _IOR ('V', 38, int)
-#define VIDIOC_S_INPUT _IOWR ('V', 39, int)
-#define VIDIOC_G_OUTPUT _IOR ('V', 46, int)
-#define VIDIOC_S_OUTPUT _IOWR ('V', 47, int)
-#define VIDIOC_ENUMOUTPUT _IOWR ('V', 48, struct v4l2_output)
-#define VIDIOC_G_AUDOUT _IOR ('V', 49, struct v4l2_audioout)
-#define VIDIOC_S_AUDOUT _IOW ('V', 50, struct v4l2_audioout)
-#define VIDIOC_G_MODULATOR _IOWR ('V', 54, struct v4l2_modulator)
-#define VIDIOC_S_MODULATOR _IOW ('V', 55, struct v4l2_modulator)
-#define VIDIOC_G_FREQUENCY _IOWR ('V', 56, struct v4l2_frequency)
-#define VIDIOC_S_FREQUENCY _IOW ('V', 57, struct v4l2_frequency)
-#define VIDIOC_CROPCAP _IOWR ('V', 58, struct v4l2_cropcap)
-#define VIDIOC_G_CROP _IOWR ('V', 59, struct v4l2_crop)
-#define VIDIOC_S_CROP _IOW ('V', 60, struct v4l2_crop)
-#define VIDIOC_G_JPEGCOMP _IOR ('V', 61, struct v4l2_jpegcompression)
-#define VIDIOC_S_JPEGCOMP _IOW ('V', 62, struct v4l2_jpegcompression)
-#define VIDIOC_QUERYSTD _IOR ('V', 63, v4l2_std_id)
-#define VIDIOC_TRY_FMT _IOWR ('V', 64, struct v4l2_format)
-#define VIDIOC_ENUMAUDIO _IOWR ('V', 65, struct v4l2_audio)
-#define VIDIOC_ENUMAUDOUT _IOWR ('V', 66, struct v4l2_audioout)
-#define VIDIOC_G_PRIORITY _IOR ('V', 67, enum v4l2_priority)
-#define VIDIOC_S_PRIORITY _IOW ('V', 68, enum v4l2_priority)
-#define VIDIOC_G_SLICED_VBI_CAP _IOWR ('V', 69, struct v4l2_sliced_vbi_cap)
-#define VIDIOC_LOG_STATUS _IO ('V', 70)
-#define VIDIOC_G_EXT_CTRLS _IOWR ('V', 71, struct v4l2_ext_controls)
-#define VIDIOC_S_EXT_CTRLS _IOWR ('V', 72, struct v4l2_ext_controls)
-#define VIDIOC_TRY_EXT_CTRLS _IOWR ('V', 73, struct v4l2_ext_controls)
+#define VIDIOC_QUERYCAP _IOR('V', 0, struct v4l2_capability)
+#define VIDIOC_RESERVED _IO('V', 1)
+#define VIDIOC_ENUM_FMT _IOWR('V', 2, struct v4l2_fmtdesc)
+#define VIDIOC_G_FMT _IOWR('V', 4, struct v4l2_format)
+#define VIDIOC_S_FMT _IOWR('V', 5, struct v4l2_format)
+#define VIDIOC_REQBUFS _IOWR('V', 8, struct v4l2_requestbuffers)
+#define VIDIOC_QUERYBUF _IOWR('V', 9, struct v4l2_buffer)
+#define VIDIOC_G_FBUF _IOR('V', 10, struct v4l2_framebuffer)
+#define VIDIOC_S_FBUF _IOW('V', 11, struct v4l2_framebuffer)
+#define VIDIOC_OVERLAY _IOW('V', 14, int)
+#define VIDIOC_QBUF _IOWR('V', 15, struct v4l2_buffer)
+#define VIDIOC_DQBUF _IOWR('V', 17, struct v4l2_buffer)
+#define VIDIOC_STREAMON _IOW('V', 18, int)
+#define VIDIOC_STREAMOFF _IOW('V', 19, int)
+#define VIDIOC_G_PARM _IOWR('V', 21, struct v4l2_streamparm)
+#define VIDIOC_S_PARM _IOWR('V', 22, struct v4l2_streamparm)
+#define VIDIOC_G_STD _IOR('V', 23, v4l2_std_id)
+#define VIDIOC_S_STD _IOW('V', 24, v4l2_std_id)
+#define VIDIOC_ENUMSTD _IOWR('V', 25, struct v4l2_standard)
+#define VIDIOC_ENUMINPUT _IOWR('V', 26, struct v4l2_input)
+#define VIDIOC_G_CTRL _IOWR('V', 27, struct v4l2_control)
+#define VIDIOC_S_CTRL _IOWR('V', 28, struct v4l2_control)
+#define VIDIOC_G_TUNER _IOWR('V', 29, struct v4l2_tuner)
+#define VIDIOC_S_TUNER _IOW('V', 30, struct v4l2_tuner)
+#define VIDIOC_G_AUDIO _IOR('V', 33, struct v4l2_audio)
+#define VIDIOC_S_AUDIO _IOW('V', 34, struct v4l2_audio)
+#define VIDIOC_QUERYCTRL _IOWR('V', 36, struct v4l2_queryctrl)
+#define VIDIOC_QUERYMENU _IOWR('V', 37, struct v4l2_querymenu)
+#define VIDIOC_G_INPUT _IOR('V', 38, int)
+#define VIDIOC_S_INPUT _IOWR('V', 39, int)
+#define VIDIOC_G_OUTPUT _IOR('V', 46, int)
+#define VIDIOC_S_OUTPUT _IOWR('V', 47, int)
+#define VIDIOC_ENUMOUTPUT _IOWR('V', 48, struct v4l2_output)
+#define VIDIOC_G_AUDOUT _IOR('V', 49, struct v4l2_audioout)
+#define VIDIOC_S_AUDOUT _IOW('V', 50, struct v4l2_audioout)
+#define VIDIOC_G_MODULATOR _IOWR('V', 54, struct v4l2_modulator)
+#define VIDIOC_S_MODULATOR _IOW('V', 55, struct v4l2_modulator)
+#define VIDIOC_G_FREQUENCY _IOWR('V', 56, struct v4l2_frequency)
+#define VIDIOC_S_FREQUENCY _IOW('V', 57, struct v4l2_frequency)
+#define VIDIOC_CROPCAP _IOWR('V', 58, struct v4l2_cropcap)
+#define VIDIOC_G_CROP _IOWR('V', 59, struct v4l2_crop)
+#define VIDIOC_S_CROP _IOW('V', 60, struct v4l2_crop)
+#define VIDIOC_G_JPEGCOMP _IOR('V', 61, struct v4l2_jpegcompression)
+#define VIDIOC_S_JPEGCOMP _IOW('V', 62, struct v4l2_jpegcompression)
+#define VIDIOC_QUERYSTD _IOR('V', 63, v4l2_std_id)
+#define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format)
+#define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio)
+#define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout)
+#define VIDIOC_G_PRIORITY _IOR('V', 67, enum v4l2_priority)
+#define VIDIOC_S_PRIORITY _IOW('V', 68, enum v4l2_priority)
+#define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap)
+#define VIDIOC_LOG_STATUS _IO('V', 70)
+#define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls)
+#define VIDIOC_S_EXT_CTRLS _IOWR('V', 72, struct v4l2_ext_controls)
+#define VIDIOC_TRY_EXT_CTRLS _IOWR('V', 73, struct v4l2_ext_controls)
#if 1
-#define VIDIOC_ENUM_FRAMESIZES _IOWR ('V', 74, struct v4l2_frmsizeenum)
-#define VIDIOC_ENUM_FRAMEINTERVALS _IOWR ('V', 75, struct v4l2_frmivalenum)
-#define VIDIOC_G_ENC_INDEX _IOR ('V', 76, struct v4l2_enc_idx)
-#define VIDIOC_ENCODER_CMD _IOWR ('V', 77, struct v4l2_encoder_cmd)
-#define VIDIOC_TRY_ENCODER_CMD _IOWR ('V', 78, struct v4l2_encoder_cmd)
+#define VIDIOC_ENUM_FRAMESIZES _IOWR('V', 74, struct v4l2_frmsizeenum)
+#define VIDIOC_ENUM_FRAMEINTERVALS _IOWR('V', 75, struct v4l2_frmivalenum)
+#define VIDIOC_G_ENC_INDEX _IOR('V', 76, struct v4l2_enc_idx)
+#define VIDIOC_ENCODER_CMD _IOWR('V', 77, struct v4l2_encoder_cmd)
+#define VIDIOC_TRY_ENCODER_CMD _IOWR('V', 78, struct v4l2_encoder_cmd)
/* Experimental, only implemented if CONFIG_VIDEO_ADV_DEBUG is defined */
-#define VIDIOC_DBG_S_REGISTER _IOW ('V', 79, struct v4l2_register)
-#define VIDIOC_DBG_G_REGISTER _IOWR ('V', 80, struct v4l2_register)
+#define VIDIOC_DBG_S_REGISTER _IOW('V', 79, struct v4l2_register)
+#define VIDIOC_DBG_G_REGISTER _IOWR('V', 80, struct v4l2_register)
-#define VIDIOC_G_CHIP_IDENT _IOWR ('V', 81, struct v4l2_chip_ident)
+#define VIDIOC_G_CHIP_IDENT _IOWR('V', 81, struct v4l2_chip_ident)
#endif
-#define VIDIOC_S_HW_FREQ_SEEK _IOW ('V', 82, struct v4l2_hw_freq_seek)
+#define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek)
#ifdef __OLD_VIDIOC_
/* for compatibility, will go away some day */
-#define VIDIOC_OVERLAY_OLD _IOWR ('V', 14, int)
-#define VIDIOC_S_PARM_OLD _IOW ('V', 22, struct v4l2_streamparm)
-#define VIDIOC_S_CTRL_OLD _IOW ('V', 28, struct v4l2_control)
-#define VIDIOC_G_AUDIO_OLD _IOWR ('V', 33, struct v4l2_audio)
-#define VIDIOC_G_AUDOUT_OLD _IOWR ('V', 49, struct v4l2_audioout)
-#define VIDIOC_CROPCAP_OLD _IOR ('V', 58, struct v4l2_cropcap)
+#define VIDIOC_OVERLAY_OLD _IOWR('V', 14, int)
+#define VIDIOC_S_PARM_OLD _IOW('V', 22, struct v4l2_streamparm)
+#define VIDIOC_S_CTRL_OLD _IOW('V', 28, struct v4l2_control)
+#define VIDIOC_G_AUDIO_OLD _IOWR('V', 33, struct v4l2_audio)
+#define VIDIOC_G_AUDOUT_OLD _IOWR('V', 49, struct v4l2_audioout)
+#define VIDIOC_CROPCAP_OLD _IOR('V', 58, struct v4l2_cropcap)
#endif
#define BASE_VIDIOC_PRIVATE 192 /* 192-255 are private */
#endif /* __LINUX_VIDEODEV2_H */
-
-/*
- * Local variables:
- * c-basic-offset: 8
- * End:
- */
#define VTXIOCCLRCACHE_OLD 0x710b /* clear cache on VTX-interface (if avail.) */
#define VTXIOCSETVIRT_OLD 0x710c /* turn on virtual mode (this disables TV-display) */
-/*
+/*
* Definitions for VTXIOCGETINFO
*/
-
+
#define SAA5243 0
#define SAA5246 1
#define SAA5249 2
typedef struct {
int version_major, version_minor; /* version of driver; if version_major changes, driver */
- /* is not backward compatible!!! CHECK THIS!!! */
+ /* is not backward compatible!!! CHECK THIS!!! */
int numpages; /* number of page-buffers of vtx-chipset */
int cct_type; /* type of vtx-chipset (SAA5243, SAA5246, SAA5248 or
- * SAA5249) */
+ * SAA5249) */
}
vtx_info_t;
#define PGMASK_HOUR (HR_TEN | HR_UNIT)
#define PGMASK_MINUTE (MIN_TEN | MIN_UNIT)
-typedef struct
+typedef struct
{
int page; /* number of requested page (hexadecimal) */
int hour; /* requested hour (hexadecimal) */
/*
* Definitions for VTXIOC{GETSTAT,PUTSTAT}
*/
-
+
#define VTX_PAGESIZE (40 * 24)
#define VTX_VIRTUALSIZE (40 * 49)
-typedef struct
+typedef struct
{
int pagenum; /* number of page (hexadecimal) */
int hour; /* hour (hexadecimal) */
unsigned hamming : 1; /* hamming-error occurred */
}
vtx_pageinfo_t;
-
+
#endif /* _VTX_H */
-/*
- */
-
-#ifndef AUDIOCHIP_H
-#define AUDIOCHIP_H
-
-enum audiochip {
- AUDIO_CHIP_NONE,
- AUDIO_CHIP_UNKNOWN,
- /* Provided by video chip */
- AUDIO_CHIP_INTERNAL,
- /* Provided by tvaudio.c */
- AUDIO_CHIP_TDA8425,
- AUDIO_CHIP_TEA6300,
- AUDIO_CHIP_TEA6420,
- AUDIO_CHIP_TDA9840,
- AUDIO_CHIP_TDA985X,
- AUDIO_CHIP_TDA9874,
- AUDIO_CHIP_PIC16C54,
- /* Provided by msp3400.c */
- AUDIO_CHIP_MSP34XX,
- /* Provided by wm8775.c */
- AUDIO_CHIP_WM8775
-};
-
-#endif /* AUDIOCHIP_H */
#define __SAA7146_VV__
#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
#include <media/saa7146.h>
#include <media/videobuf-dma-sg.h>
struct tveeprom {
u32 has_radio;
- u32 has_ir; /* bit 0: IR receiver present, bit 1: IR transmitter (blaster) present. -1 == unknown */
+ /* If has_ir == 0, then it is unknown what the IR capabilities are,
+ otherwise:
+ bit 0: 1 (= IR capabilities are known)
+ bit 1: IR receiver present
+ bit 2: IR transmitter (blaster) present */
+ u32 has_ir;
u32 has_MAC_address; /* 0: no MAC, 1: MAC present, 2: unknown */
u32 tuner_type;
/* module m52790: just ident 52790 */
V4L2_IDENT_M52790 = 52790,
- /* module msp34xx: reserved range 34000-34999 */
+ /* module msp3400: reserved range 34000-34999 and 44000-44999 */
+ V4L2_IDENT_MSPX4XX = 34000, /* generic MSPX4XX identifier, only
+ use internally (tveeprom.c). */
+
V4L2_IDENT_MSP3400B = 34002,
V4L2_IDENT_MSP3410B = 34102,
V4L2_IDENT_MSP3457G = 34577,
V4L2_IDENT_MSP3467G = 34677,
- /* module msp44xx: reserved range 44000-44999 */
+ /* module msp3400: reserved range 34000-34999 and 44000-44999 */
V4L2_IDENT_MSP4400G = 44007,
V4L2_IDENT_MSP4410G = 44107,
V4L2_IDENT_MSP4420G = 44207,
#include <media/v4l2-dev.h>
-/* v4l debugging and diagnostics */
-
-/* Debug bitmask flags to be used on V4L2 */
-#define V4L2_DEBUG_IOCTL 0x01
-#define V4L2_DEBUG_IOCTL_ARG 0x02
-
/* Common printk constucts for v4l-i2c drivers. These macros create a unique
prefix consisting of the driver name, the adapter number and the i2c
address. */
v4l_client_printk(KERN_DEBUG, client, fmt , ## arg); \
} while (0)
+/* ------------------------------------------------------------------------- */
-/* Use this macro for non-I2C drivers. Pass the driver name as the first arg. */
-#define v4l_print_ioctl(name, cmd) \
- do { \
- printk(KERN_DEBUG "%s: ", name); \
- v4l_printk_ioctl(cmd); \
- } while (0)
+/* Priority helper functions */
-/* Use this macro in I2C drivers where 'client' is the struct i2c_client
- pointer */
-#define v4l_i2c_print_ioctl(client, cmd) \
- do { \
- v4l_client_printk(KERN_DEBUG, client, ""); \
- v4l_printk_ioctl(cmd); \
- } while (0)
+struct v4l2_prio_state {
+ atomic_t prios[4];
+};
+int v4l2_prio_init(struct v4l2_prio_state *global);
+int v4l2_prio_change(struct v4l2_prio_state *global, enum v4l2_priority *local,
+ enum v4l2_priority new);
+int v4l2_prio_open(struct v4l2_prio_state *global, enum v4l2_priority *local);
+int v4l2_prio_close(struct v4l2_prio_state *global, enum v4l2_priority *local);
+enum v4l2_priority v4l2_prio_max(struct v4l2_prio_state *global);
+int v4l2_prio_check(struct v4l2_prio_state *global, enum v4l2_priority *local);
/* ------------------------------------------------------------------------- */
#ifndef _V4L2_DEV_H
#define _V4L2_DEV_H
-#define OBSOLETE_OWNER 1 /* to be removed soon */
#define OBSOLETE_DEVDATA 1 /* to be removed soon */
#include <linux/poll.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/compiler.h> /* need __user */
-#ifdef CONFIG_VIDEO_V4L1_COMPAT
-#include <linux/videodev.h>
-#else
#include <linux/videodev2.h>
-#endif
#define VIDEO_MAJOR 81
/* Minor device allocation */
#define VFL_TYPE_RADIO 2
#define VFL_TYPE_VTX 3
-/* Video standard functions */
-extern const char *v4l2_norm_to_name(v4l2_std_id id);
-extern int v4l2_video_std_construct(struct v4l2_standard *vs,
- int id, const char *name);
-/* Prints the ioctl in a human-readable format */
-extern void v4l_printk_ioctl(unsigned int cmd);
-
-/* prority handling */
-struct v4l2_prio_state {
- atomic_t prios[4];
-};
-int v4l2_prio_init(struct v4l2_prio_state *global);
-int v4l2_prio_change(struct v4l2_prio_state *global, enum v4l2_priority *local,
- enum v4l2_priority new);
-int v4l2_prio_open(struct v4l2_prio_state *global, enum v4l2_priority *local);
-int v4l2_prio_close(struct v4l2_prio_state *global, enum v4l2_priority *local);
-enum v4l2_priority v4l2_prio_max(struct v4l2_prio_state *global);
-int v4l2_prio_check(struct v4l2_prio_state *global, enum v4l2_priority *local);
-
-/* names for fancy debug output */
-extern const char *v4l2_field_names[];
-extern const char *v4l2_type_names[];
-
-/* Compatibility layer interface -- v4l1-compat module */
-typedef int (*v4l2_kioctl)(struct inode *inode, struct file *file,
- unsigned int cmd, void *arg);
-#ifdef CONFIG_VIDEO_V4L1_COMPAT
-int v4l_compat_translate_ioctl(struct inode *inode, struct file *file,
- int cmd, void *arg, v4l2_kioctl driver_ioctl);
-#else
-#define v4l_compat_translate_ioctl(inode,file,cmd,arg,ioctl) -EINVAL
-#endif
-
-/* 32 Bits compatibility layer for 64 bits processors */
-extern long v4l_compat_ioctl32(struct file *file, unsigned int cmd,
- unsigned long arg);
+struct v4l2_ioctl_callbacks;
/*
* Newer version of video_device, handled by videodev2.c
const struct file_operations *fops;
/* sysfs */
- struct device class_dev; /* v4l device */
- struct device *dev; /* device parent */
+ struct device dev; /* v4l device */
+ struct device *parent; /* device parent */
/* device info */
char name[32];
- int type; /* v4l1 */
- int type2; /* v4l2 */
+ int vfl_type;
int minor;
- /* attribute to diferentiate multiple indexs on one physical device */
+ /* attribute to differentiate multiple indices on one physical device */
int index;
- int debug; /* Activates debug level*/
+ int debug; /* Activates debug level*/
/* Video standard vars */
v4l2_std_id tvnorms; /* Supported tv norms */
void (*release)(struct video_device *vfd);
/* ioctl callbacks */
+ const struct v4l2_ioctl_ops *ioctl_ops;
- /* VIDIOC_QUERYCAP handler */
- int (*vidioc_querycap)(struct file *file, void *fh, struct v4l2_capability *cap);
-
- /* Priority handling */
- int (*vidioc_g_priority) (struct file *file, void *fh,
- enum v4l2_priority *p);
- int (*vidioc_s_priority) (struct file *file, void *fh,
- enum v4l2_priority p);
-
- /* VIDIOC_ENUM_FMT handlers */
- int (*vidioc_enum_fmt_vid_cap) (struct file *file, void *fh,
- struct v4l2_fmtdesc *f);
- int (*vidioc_enum_fmt_vid_overlay) (struct file *file, void *fh,
- struct v4l2_fmtdesc *f);
- int (*vidioc_enum_fmt_vid_out) (struct file *file, void *fh,
- struct v4l2_fmtdesc *f);
-#if 1
- /* deprecated, will be removed in 2.6.28 */
- int (*vidioc_enum_fmt_vbi_cap) (struct file *file, void *fh,
- struct v4l2_fmtdesc *f);
-#endif
- int (*vidioc_enum_fmt_type_private)(struct file *file, void *fh,
- struct v4l2_fmtdesc *f);
-
- /* VIDIOC_G_FMT handlers */
- int (*vidioc_g_fmt_vid_cap) (struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_g_fmt_vid_overlay)(struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_g_fmt_vid_out) (struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_g_fmt_vid_out_overlay)(struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_g_fmt_vbi_cap) (struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_g_fmt_vbi_out) (struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_g_fmt_sliced_vbi_cap)(struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_g_fmt_sliced_vbi_out)(struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_g_fmt_type_private)(struct file *file, void *fh,
- struct v4l2_format *f);
-
- /* VIDIOC_S_FMT handlers */
- int (*vidioc_s_fmt_vid_cap) (struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_s_fmt_vid_overlay)(struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_s_fmt_vid_out) (struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_s_fmt_vid_out_overlay)(struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_s_fmt_vbi_cap) (struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_s_fmt_vbi_out) (struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_s_fmt_sliced_vbi_cap)(struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_s_fmt_sliced_vbi_out)(struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_s_fmt_type_private)(struct file *file, void *fh,
- struct v4l2_format *f);
-
- /* VIDIOC_TRY_FMT handlers */
- int (*vidioc_try_fmt_vid_cap) (struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_try_fmt_vid_overlay)(struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_try_fmt_vid_out) (struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_try_fmt_vid_out_overlay)(struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_try_fmt_vbi_cap) (struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_try_fmt_vbi_out) (struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_try_fmt_sliced_vbi_cap)(struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_try_fmt_sliced_vbi_out)(struct file *file, void *fh,
- struct v4l2_format *f);
- int (*vidioc_try_fmt_type_private)(struct file *file, void *fh,
- struct v4l2_format *f);
-
- /* Buffer handlers */
- int (*vidioc_reqbufs) (struct file *file, void *fh, struct v4l2_requestbuffers *b);
- int (*vidioc_querybuf)(struct file *file, void *fh, struct v4l2_buffer *b);
- int (*vidioc_qbuf) (struct file *file, void *fh, struct v4l2_buffer *b);
- int (*vidioc_dqbuf) (struct file *file, void *fh, struct v4l2_buffer *b);
-
-
- int (*vidioc_overlay) (struct file *file, void *fh, unsigned int i);
-#ifdef CONFIG_VIDEO_V4L1_COMPAT
- /* buffer type is struct vidio_mbuf * */
- int (*vidiocgmbuf) (struct file *file, void *fh, struct video_mbuf *p);
-#endif
- int (*vidioc_g_fbuf) (struct file *file, void *fh,
- struct v4l2_framebuffer *a);
- int (*vidioc_s_fbuf) (struct file *file, void *fh,
- struct v4l2_framebuffer *a);
-
- /* Stream on/off */
- int (*vidioc_streamon) (struct file *file, void *fh, enum v4l2_buf_type i);
- int (*vidioc_streamoff)(struct file *file, void *fh, enum v4l2_buf_type i);
-
- /* Standard handling
- ENUMSTD is handled by videodev.c
- */
- int (*vidioc_g_std) (struct file *file, void *fh, v4l2_std_id *norm);
- int (*vidioc_s_std) (struct file *file, void *fh, v4l2_std_id *norm);
- int (*vidioc_querystd) (struct file *file, void *fh, v4l2_std_id *a);
-
- /* Input handling */
- int (*vidioc_enum_input)(struct file *file, void *fh,
- struct v4l2_input *inp);
- int (*vidioc_g_input) (struct file *file, void *fh, unsigned int *i);
- int (*vidioc_s_input) (struct file *file, void *fh, unsigned int i);
-
- /* Output handling */
- int (*vidioc_enum_output) (struct file *file, void *fh,
- struct v4l2_output *a);
- int (*vidioc_g_output) (struct file *file, void *fh, unsigned int *i);
- int (*vidioc_s_output) (struct file *file, void *fh, unsigned int i);
-
- /* Control handling */
- int (*vidioc_queryctrl) (struct file *file, void *fh,
- struct v4l2_queryctrl *a);
- int (*vidioc_g_ctrl) (struct file *file, void *fh,
- struct v4l2_control *a);
- int (*vidioc_s_ctrl) (struct file *file, void *fh,
- struct v4l2_control *a);
- int (*vidioc_g_ext_ctrls) (struct file *file, void *fh,
- struct v4l2_ext_controls *a);
- int (*vidioc_s_ext_ctrls) (struct file *file, void *fh,
- struct v4l2_ext_controls *a);
- int (*vidioc_try_ext_ctrls) (struct file *file, void *fh,
- struct v4l2_ext_controls *a);
- int (*vidioc_querymenu) (struct file *file, void *fh,
- struct v4l2_querymenu *a);
-
- /* Audio ioctls */
- int (*vidioc_enumaudio) (struct file *file, void *fh,
- struct v4l2_audio *a);
- int (*vidioc_g_audio) (struct file *file, void *fh,
- struct v4l2_audio *a);
- int (*vidioc_s_audio) (struct file *file, void *fh,
- struct v4l2_audio *a);
-
- /* Audio out ioctls */
- int (*vidioc_enumaudout) (struct file *file, void *fh,
- struct v4l2_audioout *a);
- int (*vidioc_g_audout) (struct file *file, void *fh,
- struct v4l2_audioout *a);
- int (*vidioc_s_audout) (struct file *file, void *fh,
- struct v4l2_audioout *a);
- int (*vidioc_g_modulator) (struct file *file, void *fh,
- struct v4l2_modulator *a);
- int (*vidioc_s_modulator) (struct file *file, void *fh,
- struct v4l2_modulator *a);
- /* Crop ioctls */
- int (*vidioc_cropcap) (struct file *file, void *fh,
- struct v4l2_cropcap *a);
- int (*vidioc_g_crop) (struct file *file, void *fh,
- struct v4l2_crop *a);
- int (*vidioc_s_crop) (struct file *file, void *fh,
- struct v4l2_crop *a);
- /* Compression ioctls */
- int (*vidioc_g_jpegcomp) (struct file *file, void *fh,
- struct v4l2_jpegcompression *a);
- int (*vidioc_s_jpegcomp) (struct file *file, void *fh,
- struct v4l2_jpegcompression *a);
- int (*vidioc_g_enc_index) (struct file *file, void *fh,
- struct v4l2_enc_idx *a);
- int (*vidioc_encoder_cmd) (struct file *file, void *fh,
- struct v4l2_encoder_cmd *a);
- int (*vidioc_try_encoder_cmd) (struct file *file, void *fh,
- struct v4l2_encoder_cmd *a);
-
- /* Stream type-dependent parameter ioctls */
- int (*vidioc_g_parm) (struct file *file, void *fh,
- struct v4l2_streamparm *a);
- int (*vidioc_s_parm) (struct file *file, void *fh,
- struct v4l2_streamparm *a);
-
- /* Tuner ioctls */
- int (*vidioc_g_tuner) (struct file *file, void *fh,
- struct v4l2_tuner *a);
- int (*vidioc_s_tuner) (struct file *file, void *fh,
- struct v4l2_tuner *a);
- int (*vidioc_g_frequency) (struct file *file, void *fh,
- struct v4l2_frequency *a);
- int (*vidioc_s_frequency) (struct file *file, void *fh,
- struct v4l2_frequency *a);
-
- /* Sliced VBI cap */
- int (*vidioc_g_sliced_vbi_cap) (struct file *file, void *fh,
- struct v4l2_sliced_vbi_cap *a);
-
- /* Log status ioctl */
- int (*vidioc_log_status) (struct file *file, void *fh);
-
- int (*vidioc_s_hw_freq_seek) (struct file *file, void *fh,
- struct v4l2_hw_freq_seek *a);
-
- /* Debugging ioctls */
-#ifdef CONFIG_VIDEO_ADV_DEBUG
- int (*vidioc_g_register) (struct file *file, void *fh,
- struct v4l2_register *reg);
- int (*vidioc_s_register) (struct file *file, void *fh,
- struct v4l2_register *reg);
-#endif
- int (*vidioc_g_chip_ident) (struct file *file, void *fh,
- struct v4l2_chip_ident *chip);
-
- /* For other private ioctls */
- int (*vidioc_default) (struct file *file, void *fh,
- int cmd, void *arg);
-
-
-#ifdef OBSOLETE_OWNER /* to be removed soon */
-/* obsolete -- fops->owner is used instead */
-struct module *owner;
-/* dev->driver_data will be used instead some day.
- * Use the video_{get|set}_drvdata() helper functions,
- * so the switch over will be transparent for you.
- * Or use {pci|usb}_{get|set}_drvdata() directly. */
-void *priv;
+#ifdef OBSOLETE_DEVDATA /* to be removed soon */
+ /* dev->driver_data will be used instead some day.
+ * Use the video_{get|set}_drvdata() helper functions,
+ * so the switch over will be transparent for you.
+ * Or use {pci|usb}_{get|set}_drvdata() directly. */
+ void *priv;
#endif
- /* for videodev.c intenal usage -- please don't touch */
+ /* for videodev.c internal usage -- please don't touch */
int users; /* video_exclusive_{open|close} ... */
struct mutex lock; /* ... helper function uses these */
};
/* Class-dev to video-device */
-#define to_video_device(cd) container_of(cd, struct video_device, class_dev)
+#define to_video_device(cd) container_of(cd, struct video_device, dev)
/* Version 2 functions */
extern int video_register_device(struct video_device *vfd, int type, int nr);
int video_register_device_index(struct video_device *vfd, int type, int nr,
int index);
void video_unregister_device(struct video_device *);
-extern int video_ioctl2(struct inode *inode, struct file *file,
- unsigned int cmd, unsigned long arg);
/* helper functions to alloc / release struct video_device, the
later can be used for video_device->release() */
struct video_device *video_device_alloc(void);
void video_device_release(struct video_device *vfd);
-/* Include support for obsoleted stuff */
-extern int video_usercopy(struct inode *inode, struct file *file,
- unsigned int cmd, unsigned long arg,
- int (*func)(struct inode *inode, struct file *file,
- unsigned int cmd, void *arg));
-
-#ifdef CONFIG_VIDEO_V4L1_COMPAT
-#include <linux/mm.h>
-
-static inline int __must_check
-video_device_create_file(struct video_device *vfd,
- struct device_attribute *attr)
-{
- int ret = device_create_file(&vfd->class_dev, attr);
- if (ret < 0)
- printk(KERN_WARNING "%s error: %d\n", __func__, ret);
- return ret;
-}
-static inline void
-video_device_remove_file(struct video_device *vfd,
- struct device_attribute *attr)
-{
- device_remove_file(&vfd->class_dev, attr);
-}
-
-#endif /* CONFIG_VIDEO_V4L1_COMPAT */
-
-#ifdef OBSOLETE_OWNER /* to be removed soon */
+#ifdef OBSOLETE_DEVDATA /* to be removed soon */
/* helper functions to access driver private data. */
static inline void *video_get_drvdata(struct video_device *dev)
{
dev->priv = data;
}
-#endif
-
-#ifdef OBSOLETE_DEVDATA /* to be removed soon */
/* Obsolete stuff - Still needed for radio devices and obsolete drivers */
extern struct video_device* video_devdata(struct file*);
extern int video_exclusive_open(struct inode *inode, struct file *file);
--- /dev/null
+/*
+ *
+ * V 4 L 2 D R I V E R H E L P E R A P I
+ *
+ * Moved from videodev2.h
+ *
+ * Some commonly needed functions for drivers (v4l2-common.o module)
+ */
+#ifndef _V4L2_IOCTL_H
+#define _V4L2_IOCTL_H
+
+#include <linux/poll.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/mutex.h>
+#include <linux/compiler.h> /* need __user */
+#ifdef CONFIG_VIDEO_V4L1_COMPAT
+#include <linux/videodev.h>
+#else
+#include <linux/videodev2.h>
+#endif
+
+struct v4l2_ioctl_ops {
+ /* ioctl callbacks */
+
+ /* VIDIOC_QUERYCAP handler */
+ int (*vidioc_querycap)(struct file *file, void *fh, struct v4l2_capability *cap);
+
+ /* Priority handling */
+ int (*vidioc_g_priority) (struct file *file, void *fh,
+ enum v4l2_priority *p);
+ int (*vidioc_s_priority) (struct file *file, void *fh,
+ enum v4l2_priority p);
+
+ /* VIDIOC_ENUM_FMT handlers */
+ int (*vidioc_enum_fmt_vid_cap) (struct file *file, void *fh,
+ struct v4l2_fmtdesc *f);
+ int (*vidioc_enum_fmt_vid_overlay) (struct file *file, void *fh,
+ struct v4l2_fmtdesc *f);
+ int (*vidioc_enum_fmt_vid_out) (struct file *file, void *fh,
+ struct v4l2_fmtdesc *f);
+#if 1
+ /* deprecated, will be removed in 2.6.28 */
+ int (*vidioc_enum_fmt_vbi_cap) (struct file *file, void *fh,
+ struct v4l2_fmtdesc *f);
+#endif
+ int (*vidioc_enum_fmt_type_private)(struct file *file, void *fh,
+ struct v4l2_fmtdesc *f);
+
+ /* VIDIOC_G_FMT handlers */
+ int (*vidioc_g_fmt_vid_cap) (struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_g_fmt_vid_overlay)(struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_g_fmt_vid_out) (struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_g_fmt_vid_out_overlay)(struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_g_fmt_vbi_cap) (struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_g_fmt_vbi_out) (struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_g_fmt_sliced_vbi_cap)(struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_g_fmt_sliced_vbi_out)(struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_g_fmt_type_private)(struct file *file, void *fh,
+ struct v4l2_format *f);
+
+ /* VIDIOC_S_FMT handlers */
+ int (*vidioc_s_fmt_vid_cap) (struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_s_fmt_vid_overlay)(struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_s_fmt_vid_out) (struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_s_fmt_vid_out_overlay)(struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_s_fmt_vbi_cap) (struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_s_fmt_vbi_out) (struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_s_fmt_sliced_vbi_cap)(struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_s_fmt_sliced_vbi_out)(struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_s_fmt_type_private)(struct file *file, void *fh,
+ struct v4l2_format *f);
+
+ /* VIDIOC_TRY_FMT handlers */
+ int (*vidioc_try_fmt_vid_cap) (struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_try_fmt_vid_overlay)(struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_try_fmt_vid_out) (struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_try_fmt_vid_out_overlay)(struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_try_fmt_vbi_cap) (struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_try_fmt_vbi_out) (struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_try_fmt_sliced_vbi_cap)(struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_try_fmt_sliced_vbi_out)(struct file *file, void *fh,
+ struct v4l2_format *f);
+ int (*vidioc_try_fmt_type_private)(struct file *file, void *fh,
+ struct v4l2_format *f);
+
+ /* Buffer handlers */
+ int (*vidioc_reqbufs) (struct file *file, void *fh, struct v4l2_requestbuffers *b);
+ int (*vidioc_querybuf)(struct file *file, void *fh, struct v4l2_buffer *b);
+ int (*vidioc_qbuf) (struct file *file, void *fh, struct v4l2_buffer *b);
+ int (*vidioc_dqbuf) (struct file *file, void *fh, struct v4l2_buffer *b);
+
+
+ int (*vidioc_overlay) (struct file *file, void *fh, unsigned int i);
+#ifdef CONFIG_VIDEO_V4L1_COMPAT
+ /* buffer type is struct vidio_mbuf * */
+ int (*vidiocgmbuf) (struct file *file, void *fh, struct video_mbuf *p);
+#endif
+ int (*vidioc_g_fbuf) (struct file *file, void *fh,
+ struct v4l2_framebuffer *a);
+ int (*vidioc_s_fbuf) (struct file *file, void *fh,
+ struct v4l2_framebuffer *a);
+
+ /* Stream on/off */
+ int (*vidioc_streamon) (struct file *file, void *fh, enum v4l2_buf_type i);
+ int (*vidioc_streamoff)(struct file *file, void *fh, enum v4l2_buf_type i);
+
+ /* Standard handling
+ ENUMSTD is handled by videodev.c
+ */
+ int (*vidioc_g_std) (struct file *file, void *fh, v4l2_std_id *norm);
+ int (*vidioc_s_std) (struct file *file, void *fh, v4l2_std_id *norm);
+ int (*vidioc_querystd) (struct file *file, void *fh, v4l2_std_id *a);
+
+ /* Input handling */
+ int (*vidioc_enum_input)(struct file *file, void *fh,
+ struct v4l2_input *inp);
+ int (*vidioc_g_input) (struct file *file, void *fh, unsigned int *i);
+ int (*vidioc_s_input) (struct file *file, void *fh, unsigned int i);
+
+ /* Output handling */
+ int (*vidioc_enum_output) (struct file *file, void *fh,
+ struct v4l2_output *a);
+ int (*vidioc_g_output) (struct file *file, void *fh, unsigned int *i);
+ int (*vidioc_s_output) (struct file *file, void *fh, unsigned int i);
+
+ /* Control handling */
+ int (*vidioc_queryctrl) (struct file *file, void *fh,
+ struct v4l2_queryctrl *a);
+ int (*vidioc_g_ctrl) (struct file *file, void *fh,
+ struct v4l2_control *a);
+ int (*vidioc_s_ctrl) (struct file *file, void *fh,
+ struct v4l2_control *a);
+ int (*vidioc_g_ext_ctrls) (struct file *file, void *fh,
+ struct v4l2_ext_controls *a);
+ int (*vidioc_s_ext_ctrls) (struct file *file, void *fh,
+ struct v4l2_ext_controls *a);
+ int (*vidioc_try_ext_ctrls) (struct file *file, void *fh,
+ struct v4l2_ext_controls *a);
+ int (*vidioc_querymenu) (struct file *file, void *fh,
+ struct v4l2_querymenu *a);
+
+ /* Audio ioctls */
+ int (*vidioc_enumaudio) (struct file *file, void *fh,
+ struct v4l2_audio *a);
+ int (*vidioc_g_audio) (struct file *file, void *fh,
+ struct v4l2_audio *a);
+ int (*vidioc_s_audio) (struct file *file, void *fh,
+ struct v4l2_audio *a);
+
+ /* Audio out ioctls */
+ int (*vidioc_enumaudout) (struct file *file, void *fh,
+ struct v4l2_audioout *a);
+ int (*vidioc_g_audout) (struct file *file, void *fh,
+ struct v4l2_audioout *a);
+ int (*vidioc_s_audout) (struct file *file, void *fh,
+ struct v4l2_audioout *a);
+ int (*vidioc_g_modulator) (struct file *file, void *fh,
+ struct v4l2_modulator *a);
+ int (*vidioc_s_modulator) (struct file *file, void *fh,
+ struct v4l2_modulator *a);
+ /* Crop ioctls */
+ int (*vidioc_cropcap) (struct file *file, void *fh,
+ struct v4l2_cropcap *a);
+ int (*vidioc_g_crop) (struct file *file, void *fh,
+ struct v4l2_crop *a);
+ int (*vidioc_s_crop) (struct file *file, void *fh,
+ struct v4l2_crop *a);
+ /* Compression ioctls */
+ int (*vidioc_g_jpegcomp) (struct file *file, void *fh,
+ struct v4l2_jpegcompression *a);
+ int (*vidioc_s_jpegcomp) (struct file *file, void *fh,
+ struct v4l2_jpegcompression *a);
+ int (*vidioc_g_enc_index) (struct file *file, void *fh,
+ struct v4l2_enc_idx *a);
+ int (*vidioc_encoder_cmd) (struct file *file, void *fh,
+ struct v4l2_encoder_cmd *a);
+ int (*vidioc_try_encoder_cmd) (struct file *file, void *fh,
+ struct v4l2_encoder_cmd *a);
+
+ /* Stream type-dependent parameter ioctls */
+ int (*vidioc_g_parm) (struct file *file, void *fh,
+ struct v4l2_streamparm *a);
+ int (*vidioc_s_parm) (struct file *file, void *fh,
+ struct v4l2_streamparm *a);
+
+ /* Tuner ioctls */
+ int (*vidioc_g_tuner) (struct file *file, void *fh,
+ struct v4l2_tuner *a);
+ int (*vidioc_s_tuner) (struct file *file, void *fh,
+ struct v4l2_tuner *a);
+ int (*vidioc_g_frequency) (struct file *file, void *fh,
+ struct v4l2_frequency *a);
+ int (*vidioc_s_frequency) (struct file *file, void *fh,
+ struct v4l2_frequency *a);
+
+ /* Sliced VBI cap */
+ int (*vidioc_g_sliced_vbi_cap) (struct file *file, void *fh,
+ struct v4l2_sliced_vbi_cap *a);
+
+ /* Log status ioctl */
+ int (*vidioc_log_status) (struct file *file, void *fh);
+
+ int (*vidioc_s_hw_freq_seek) (struct file *file, void *fh,
+ struct v4l2_hw_freq_seek *a);
+
+ /* Debugging ioctls */
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+ int (*vidioc_g_register) (struct file *file, void *fh,
+ struct v4l2_register *reg);
+ int (*vidioc_s_register) (struct file *file, void *fh,
+ struct v4l2_register *reg);
+#endif
+ int (*vidioc_g_chip_ident) (struct file *file, void *fh,
+ struct v4l2_chip_ident *chip);
+
+ /* For other private ioctls */
+ int (*vidioc_default) (struct file *file, void *fh,
+ int cmd, void *arg);
+};
+
+
+/* v4l debugging and diagnostics */
+
+/* Debug bitmask flags to be used on V4L2 */
+#define V4L2_DEBUG_IOCTL 0x01
+#define V4L2_DEBUG_IOCTL_ARG 0x02
+
+/* Use this macro for non-I2C drivers. Pass the driver name as the first arg. */
+#define v4l_print_ioctl(name, cmd) \
+ do { \
+ printk(KERN_DEBUG "%s: ", name); \
+ v4l_printk_ioctl(cmd); \
+ } while (0)
+
+/* Use this macro in I2C drivers where 'client' is the struct i2c_client
+ pointer */
+#define v4l_i2c_print_ioctl(client, cmd) \
+ do { \
+ v4l_client_printk(KERN_DEBUG, client, ""); \
+ v4l_printk_ioctl(cmd); \
+ } while (0)
+
+/* Video standard functions */
+extern const char *v4l2_norm_to_name(v4l2_std_id id);
+extern int v4l2_video_std_construct(struct v4l2_standard *vs,
+ int id, const char *name);
+/* Prints the ioctl in a human-readable format */
+extern void v4l_printk_ioctl(unsigned int cmd);
+
+/* names for fancy debug output */
+extern const char *v4l2_field_names[];
+extern const char *v4l2_type_names[];
+
+/* Compatibility layer interface -- v4l1-compat module */
+typedef int (*v4l2_kioctl)(struct inode *inode, struct file *file,
+ unsigned int cmd, void *arg);
+#ifdef CONFIG_VIDEO_V4L1_COMPAT
+int v4l_compat_translate_ioctl(struct inode *inode, struct file *file,
+ int cmd, void *arg, v4l2_kioctl driver_ioctl);
+#else
+#define v4l_compat_translate_ioctl(inode, file, cmd, arg, ioctl) (-EINVAL)
+#endif
+
+/* 32 Bits compatibility layer for 64 bits processors */
+extern long v4l_compat_ioctl32(struct file *file, unsigned int cmd,
+ unsigned long arg);
+
+extern int video_ioctl2(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg);
+
+/* Include support for obsoleted stuff */
+extern int video_usercopy(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg,
+ int (*func)(struct inode *inode, struct file *file,
+ unsigned int cmd, void *arg));
+
+#endif /* _V4L2_IOCTL_H */
stats->hiwater_vm = mm->hiwater_vm * PAGE_SIZE / KB;
mmput(mm);
}
- stats->read_char = p->ioac.chr.rchar;
- stats->write_char = p->ioac.chr.wchar;
- stats->read_syscalls = p->ioac.chr.syscr;
- stats->write_syscalls = p->ioac.chr.syscw;
+ stats->read_char = p->ioac.rchar;
+ stats->write_char = p->ioac.wchar;
+ stats->read_syscalls = p->ioac.syscr;
+ stats->write_syscalls = p->ioac.syscw;
#ifdef CONFIG_TASK_IO_ACCOUNTING
- stats->read_bytes = p->ioac.blk.read_bytes;
- stats->write_bytes = p->ioac.blk.write_bytes;
- stats->cancelled_write_bytes = p->ioac.blk.cancelled_write_bytes;
+ stats->read_bytes = p->ioac.read_bytes;
+ stats->write_bytes = p->ioac.write_bytes;
+ stats->cancelled_write_bytes = p->ioac.cancelled_write_bytes;
#else
stats->read_bytes = 0;
stats->write_bytes = 0;
extern void dccp_v4_send_check(struct sock *sk, int len, struct sk_buff *skb);
-extern int dccp_retransmit_skb(struct sock *sk, struct sk_buff *skb);
+extern int dccp_retransmit_skb(struct sock *sk);
extern void dccp_send_ack(struct sock *sk);
extern void dccp_reqsk_send_ack(struct sk_buff *sk, struct request_sock *rsk);
static void dccp_v4_err(struct sk_buff *skb, u32 info)
{
const struct iphdr *iph = (struct iphdr *)skb->data;
- const struct dccp_hdr *dh = (struct dccp_hdr *)(skb->data +
- (iph->ihl << 2));
+ const u8 offset = iph->ihl << 2;
+ const struct dccp_hdr *dh = (struct dccp_hdr *)(skb->data + offset);
struct dccp_sock *dp;
struct inet_sock *inet;
const int type = icmp_hdr(skb)->type;
int err;
struct net *net = dev_net(skb->dev);
- if (skb->len < (iph->ihl << 2) + 8) {
+ if (skb->len < offset + sizeof(*dh) ||
+ skb->len < offset + __dccp_basic_hdr_len(dh)) {
ICMP_INC_STATS_BH(net, ICMP_MIB_INERRORS);
return;
}
dp = dccp_sk(sk);
seq = dccp_hdr_seq(dh);
if ((1 << sk->sk_state) & ~(DCCPF_REQUESTING | DCCPF_LISTEN) &&
- !between48(seq, dp->dccps_swl, dp->dccps_swh)) {
+ !between48(seq, dp->dccps_awl, dp->dccps_awh)) {
NET_INC_STATS_BH(net, LINUX_MIB_OUTOFWINDOWICMPS);
goto out;
}
{
struct ipv6hdr *hdr = (struct ipv6hdr *)skb->data;
const struct dccp_hdr *dh = (struct dccp_hdr *)(skb->data + offset);
+ struct dccp_sock *dp;
struct ipv6_pinfo *np;
struct sock *sk;
int err;
__u64 seq;
struct net *net = dev_net(skb->dev);
+ if (skb->len < offset + sizeof(*dh) ||
+ skb->len < offset + __dccp_basic_hdr_len(dh)) {
+ ICMP6_INC_STATS_BH(__in6_dev_get(skb->dev), ICMP6_MIB_INERRORS);
+ return;
+ }
+
sk = inet6_lookup(net, &dccp_hashinfo,
&hdr->daddr, dh->dccph_dport,
&hdr->saddr, dh->dccph_sport, inet6_iif(skb));
if (sk->sk_state == DCCP_CLOSED)
goto out;
+ dp = dccp_sk(sk);
+ seq = dccp_hdr_seq(dh);
+ if ((1 << sk->sk_state) & ~(DCCPF_REQUESTING | DCCPF_LISTEN) &&
+ !between48(seq, dp->dccps_awl, dp->dccps_awh)) {
+ NET_INC_STATS_BH(net, LINUX_MIB_OUTOFWINDOWICMPS);
+ goto out;
+ }
+
np = inet6_sk(sk);
if (type == ICMPV6_PKT_TOOBIG) {
icmpv6_err_convert(type, code, &err);
- seq = dccp_hdr_seq(dh);
/* Might be for an request_sock */
switch (sk->sk_state) {
struct request_sock *req, **prev;
dccp_packet_hdr_len(dcb->dccpd_type);
int err, set_ack = 1;
u64 ackno = dp->dccps_gsr;
-
- dccp_inc_seqno(&dp->dccps_gss);
+ /*
+ * Increment GSS here already in case the option code needs it.
+ * Update GSS for real only if option processing below succeeds.
+ */
+ dcb->dccpd_seq = ADD48(dp->dccps_gss, 1);
switch (dcb->dccpd_type) {
case DCCP_PKT_DATA:
case DCCP_PKT_REQUEST:
set_ack = 0;
+ /* Use ISS on the first (non-retransmitted) Request. */
+ if (icsk->icsk_retransmits == 0)
+ dcb->dccpd_seq = dp->dccps_iss;
/* fall through */
case DCCP_PKT_SYNC:
break;
}
- dcb->dccpd_seq = dp->dccps_gss;
-
if (dccp_insert_options(sk, skb)) {
kfree_skb(skb);
return -EPROTO;
/* XXX For now we're using only 48 bits sequence numbers */
dh->dccph_x = 1;
- dp->dccps_awh = dp->dccps_gss;
+ dccp_update_gss(sk, dcb->dccpd_seq);
dccp_hdr_set_seq(dh, dp->dccps_gss);
if (set_ack)
dccp_hdr_set_ack(dccp_hdr_ack_bits(skb), ackno);
case DCCP_PKT_REQUEST:
dccp_hdr_request(skb)->dccph_req_service =
dp->dccps_service;
+ /*
+ * Limit Ack window to ISS <= P.ackno <= GSS, so that
+ * only Responses to Requests we sent are considered.
+ */
+ dp->dccps_awl = dp->dccps_iss;
break;
case DCCP_PKT_RESET:
dccp_hdr_reset(skb)->dccph_reset_code =
}
}
-int dccp_retransmit_skb(struct sock *sk, struct sk_buff *skb)
+/**
+ * dccp_retransmit_skb - Retransmit Request, Close, or CloseReq packets
+ * There are only four retransmittable packet types in DCCP:
+ * - Request in client-REQUEST state (sec. 8.1.1),
+ * - CloseReq in server-CLOSEREQ state (sec. 8.3),
+ * - Close in node-CLOSING state (sec. 8.3),
+ * - Acks in client-PARTOPEN state (sec. 8.1.5, handled by dccp_delack_timer()).
+ * This function expects sk->sk_send_head to contain the original skb.
+ */
+int dccp_retransmit_skb(struct sock *sk)
{
+ WARN_ON(sk->sk_send_head == NULL);
+
if (inet_csk(sk)->icsk_af_ops->rebuild_header(sk) != 0)
return -EHOSTUNREACH; /* Routing failure or similar. */
- return dccp_transmit_skb(sk, (skb_cloned(skb) ?
- pskb_copy(skb, GFP_ATOMIC):
- skb_clone(skb, GFP_ATOMIC)));
+ /* this count is used to distinguish original and retransmitted skb */
+ inet_csk(sk)->icsk_retransmits++;
+
+ return dccp_transmit_skb(sk, skb_clone(sk->sk_send_head, GFP_ATOMIC));
}
struct sk_buff *dccp_make_response(struct sock *sk, struct dst_entry *dst,
dccp_sync_mss(sk, dst_mtu(dst));
- /*
- * SWL and AWL are initially adjusted so that they are not less than
- * the initial Sequence Numbers received and sent, respectively:
- * SWL := max(GSR + 1 - floor(W/4), ISR),
- * AWL := max(GSS - W' + 1, ISS).
- * These adjustments MUST be applied only at the beginning of the
- * connection.
- */
- dccp_update_gss(sk, dp->dccps_iss);
- dccp_set_seqno(&dp->dccps_awl, max48(dp->dccps_awl, dp->dccps_iss));
-
- /* S.GAR - greatest valid acknowledgement number received on a non-Sync;
- * initialized to S.ISS (sec. 8.5) */
+ /* Initialise GAR as per 8.5; AWL/AWH are set in dccp_transmit_skb() */
dp->dccps_gar = dp->dccps_iss;
icsk->icsk_retransmits = 0;
goto backoff;
}
- /*
- * sk->sk_send_head has to have one skb with
- * DCCP_SKB_CB(skb)->dccpd_type set to one of the retransmittable DCCP
- * packet types. The only packets eligible for retransmission are:
- * -- Requests in client-REQUEST state (sec. 8.1.1)
- * -- Acks in client-PARTOPEN state (sec. 8.1.5)
- * -- CloseReq in server-CLOSEREQ state (sec. 8.3)
- * -- Close in node-CLOSING state (sec. 8.3) */
- WARN_ON(sk->sk_send_head == NULL);
-
/*
* More than than 4MSL (8 minutes) has passed, a RESET(aborted) was
* sent, no need to retransmit, this sock is dead.
*/
if (dccp_write_timeout(sk))
- goto out;
+ return;
/*
* We want to know the number of packets retransmitted, not the
if (icsk->icsk_retransmits == 0)
DCCP_INC_STATS_BH(DCCP_MIB_TIMEOUTS);
- if (dccp_retransmit_skb(sk, sk->sk_send_head) < 0) {
+ if (dccp_retransmit_skb(sk) != 0) {
/*
* Retransmission failed because of local congestion,
* do not backoff.
*/
- if (icsk->icsk_retransmits == 0)
+ if (--icsk->icsk_retransmits == 0)
icsk->icsk_retransmits = 1;
inet_csk_reset_xmit_timer(sk, ICSK_TIME_RETRANS,
min(icsk->icsk_rto,
TCP_RESOURCE_PROBE_INTERVAL),
DCCP_RTO_MAX);
- goto out;
+ return;
}
backoff:
icsk->icsk_backoff++;
- icsk->icsk_retransmits++;
icsk->icsk_rto = min(icsk->icsk_rto << 1, DCCP_RTO_MAX);
inet_csk_reset_xmit_timer(sk, ICSK_TIME_RETRANS, icsk->icsk_rto,
DCCP_RTO_MAX);
if (icsk->icsk_retransmits > sysctl_dccp_retries1)
__sk_dst_reset(sk);
-out:;
}
static void dccp_write_timer(unsigned long data)
static int ipcomp4_init_state(struct xfrm_state *x)
{
- int err;
- struct ipcomp_data *ipcd;
- struct xfrm_algo_desc *calg_desc;
+ int err = -EINVAL;
x->props.header_len = 0;
switch (x->props.mode) {
static int ipcomp6_init_state(struct xfrm_state *x)
{
- int err;
- struct ipcomp_data *ipcd;
- struct xfrm_algo_desc *calg_desc;
+ int err = -EINVAL;
x->props.header_len = 0;
switch (x->props.mode) {
}
memset(&tea->vd, 0, sizeof(tea->vd));
- tea->vd.owner = tea->card->module;
strcpy(tea->vd.name, tea->tea5759 ? "TEA5759 radio" : "TEA5757 radio");
- tea->vd.type = VID_TYPE_TUNER;
tea->vd.release = snd_tea575x_release;
video_set_drvdata(&tea->vd, tea);
tea->vd.fops = &tea->fops;
projects / cascardo / linux.git / commitdiff