This is necessary for determining the reference clock value on
platforms lacking an RTC.
+config SH_CLK_CPG
+ def_bool y
+
+config SH_CLK_CPG_LEGACY
+ depends on SH_CLK_CPG
+ def_bool y if !CPU_SUBTYPE_SH7785
+
config SH_CLK_MD
int "CPU Mode Pin Setting"
depends on CPU_SH2
* Renesas Technology Corp. R0P7785LC0011RL Support.
*
* Copyright (C) 2008 Yoshihiro Shimoda
+ * Copyright (C) 2009 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
-
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/sm501.h>
#include <linux/i2c-pca-platform.h>
#include <linux/i2c-algo-pca.h>
#include <linux/irq.h>
-#include <asm/heartbeat.h>
+#include <linux/clk.h>
+#include <linux/errno.h>
#include <mach/sh7785lcr.h>
+#include <asm/heartbeat.h>
+#include <asm/clock.h>
/*
* NOTE: This board has 2 physical memory maps.
plat_irq_setup_pins(IRQ_MODE_IRQ3210);
}
+static int sh7785lcr_clk_init(void)
+{
+ struct clk *clk;
+ int ret;
+
+ clk = clk_get(NULL, "extal");
+ if (!clk || IS_ERR(clk))
+ return PTR_ERR(clk);
+ ret = clk_set_rate(clk, 33333333);
+ clk_put(clk);
+
+ return ret;
+}
+
static void sh7785lcr_power_off(void)
{
unsigned char *p;
static struct sh_machine_vector mv_sh7785lcr __initmv = {
.mv_name = "SH7785LCR",
.mv_setup = sh7785lcr_setup,
+ .mv_clk_init = sh7785lcr_clk_init,
.mv_init_irq = init_sh7785lcr_IRQ,
};
struct clk_ops {
void (*init)(struct clk *clk);
- void (*enable)(struct clk *clk);
+ int (*enable)(struct clk *clk);
void (*disable)(struct clk *clk);
- void (*recalc)(struct clk *clk);
+ unsigned long (*recalc)(struct clk *clk);
int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
int (*set_parent)(struct clk *clk, struct clk *parent);
long (*round_rate)(struct clk *clk, unsigned long rate);
struct clk *parent;
struct clk_ops *ops;
+ struct list_head children;
+ struct list_head sibling; /* node for children */
+
int usecount;
unsigned long rate;
unsigned long flags;
+
+ void __iomem *enable_reg;
+ unsigned int enable_bit;
+
unsigned long arch_flags;
+ void *priv;
+ struct dentry *dentry;
+};
+
+struct clk_lookup {
+ struct list_head node;
+ const char *dev_id;
+ const char *con_id;
+ struct clk *clk;
};
-#define CLK_ALWAYS_ENABLED (1 << 0)
-#define CLK_RATE_PROPAGATES (1 << 1)
-#define CLK_NEEDS_INIT (1 << 2)
+#define CLK_ENABLE_ON_INIT (1 << 0)
/* Should be defined by processor-specific code */
-void arch_init_clk_ops(struct clk_ops **, int type);
+void __deprecated arch_init_clk_ops(struct clk_ops **, int type);
int __init arch_clk_init(void);
/* arch/sh/kernel/cpu/clock.c */
int clk_init(void);
-
-void clk_recalc_rate(struct clk *);
-
+unsigned long followparent_recalc(struct clk *);
+void recalculate_root_clocks(void);
+void propagate_rate(struct clk *);
+int clk_reparent(struct clk *child, struct clk *parent);
int clk_register(struct clk *);
void clk_unregister(struct clk *);
-static inline int clk_always_enable(const char *id)
-{
- struct clk *clk;
- int ret;
-
- clk = clk_get(NULL, id);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
- ret = clk_enable(clk);
- if (ret)
- clk_put(clk);
-
- return ret;
-}
+/* arch/sh/kernel/cpu/clock-cpg.c */
+int __init __deprecated cpg_clk_init(void);
/* the exported API, in addition to clk_set_rate */
/**
IP_N1,
};
+
+struct clk_div_mult_table {
+ unsigned int *divisors;
+ unsigned int nr_divisors;
+ unsigned int *multipliers;
+ unsigned int nr_multipliers;
+};
+
+struct cpufreq_frequency_table;
+void clk_rate_table_build(struct clk *clk,
+ struct cpufreq_frequency_table *freq_table,
+ int nr_freqs,
+ struct clk_div_mult_table *src_table,
+ unsigned long *bitmap);
+
+long clk_rate_table_round(struct clk *clk,
+ struct cpufreq_frequency_table *freq_table,
+ unsigned long rate);
+
#endif /* __ASM_SH_CLOCK_H */
void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
void (*mv_ioport_unmap)(void __iomem *);
+
+ int (*mv_clk_init)(void);
};
extern struct sh_machine_vector sh_mv;
obj-$(CONFIG_UBC_WAKEUP) += ubc.o
obj-$(CONFIG_SH_ADC) += adc.o
+obj-$(CONFIG_SH_CLK_CPG) += clock-cpg.o
obj-y += irq/ init.o clock.o
--- /dev/null
+#include <linux/clk.h>
+#include <linux/compiler.h>
+#include <asm/clock.h>
+
+#ifdef CONFIG_SH_CLK_CPG_LEGACY
+static struct clk master_clk = {
+ .name = "master_clk",
+ .flags = CLK_ENABLE_ON_INIT,
+ .rate = CONFIG_SH_PCLK_FREQ,
+};
+
+static struct clk peripheral_clk = {
+ .name = "peripheral_clk",
+ .parent = &master_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+};
+
+static struct clk bus_clk = {
+ .name = "bus_clk",
+ .parent = &master_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+};
+
+static struct clk cpu_clk = {
+ .name = "cpu_clk",
+ .parent = &master_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+};
+
+/*
+ * The ordering of these clocks matters, do not change it.
+ */
+static struct clk *onchip_clocks[] = {
+ &master_clk,
+ &peripheral_clk,
+ &bus_clk,
+ &cpu_clk,
+};
+
+int __init __deprecated cpg_clk_init(void)
+{
+ int i, ret = 0;
+
+ for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
+ struct clk *clk = onchip_clocks[i];
+ arch_init_clk_ops(&clk->ops, i);
+ if (clk->ops)
+ ret |= clk_register(clk);
+ }
+
+ return ret;
+}
+
+/*
+ * Placeholder for compatability, until the lazy CPUs do this
+ * on their own.
+ */
+int __init __weak arch_clk_init(void)
+{
+ return cpg_clk_init();
+}
+#endif /* CONFIG_SH_CPG_CLK_LEGACY */
/*
* arch/sh/kernel/cpu/clock.c - SuperH clock framework
*
- * Copyright (C) 2005, 2006, 2007 Paul Mundt
+ * Copyright (C) 2005 - 2009 Paul Mundt
*
* This clock framework is derived from the OMAP version by:
*
- * Copyright (C) 2004 - 2005 Nokia Corporation
+ * Copyright (C) 2004 - 2008 Nokia Corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
*
* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
*
+ * With clkdev bits:
+ *
+ * Copyright (C) 2008 Russell King.
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
#include <linux/seq_file.h>
#include <linux/err.h>
#include <linux/platform_device.h>
-#include <linux/proc_fs.h>
+#include <linux/debugfs.h>
+#include <linux/cpufreq.h>
#include <asm/clock.h>
+#include <asm/machvec.h>
static LIST_HEAD(clock_list);
static DEFINE_SPINLOCK(clock_lock);
static DEFINE_MUTEX(clock_list_sem);
-/*
- * Each subtype is expected to define the init routines for these clocks,
- * as each subtype (or processor family) will have these clocks at the
- * very least. These are all provided through the CPG, which even some of
- * the more quirky parts (such as ST40, SH4-202, etc.) still have.
- *
- * The processor-specific code is expected to register any additional
- * clock sources that are of interest.
- */
-static struct clk master_clk = {
- .name = "master_clk",
- .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
- .rate = CONFIG_SH_PCLK_FREQ,
-};
+void clk_rate_table_build(struct clk *clk,
+ struct cpufreq_frequency_table *freq_table,
+ int nr_freqs,
+ struct clk_div_mult_table *src_table,
+ unsigned long *bitmap)
+{
+ unsigned long mult, div;
+ unsigned long freq;
+ int i;
-static struct clk module_clk = {
- .name = "module_clk",
- .parent = &master_clk,
- .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
-};
+ for (i = 0; i < nr_freqs; i++) {
+ div = 1;
+ mult = 1;
-static struct clk bus_clk = {
- .name = "bus_clk",
- .parent = &master_clk,
- .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
-};
+ if (src_table->divisors && i < src_table->nr_divisors)
+ div = src_table->divisors[i];
-static struct clk cpu_clk = {
- .name = "cpu_clk",
- .parent = &master_clk,
- .flags = CLK_ALWAYS_ENABLED,
-};
+ if (src_table->multipliers && i < src_table->nr_multipliers)
+ mult = src_table->multipliers[i];
-/*
- * The ordering of these clocks matters, do not change it.
- */
-static struct clk *onchip_clocks[] = {
- &master_clk,
- &module_clk,
- &bus_clk,
- &cpu_clk,
-};
+ if (!div || !mult || (bitmap && !test_bit(i, bitmap)))
+ freq = CPUFREQ_ENTRY_INVALID;
+ else
+ freq = clk->parent->rate * mult / div;
-static void propagate_rate(struct clk *clk)
-{
- struct clk *clkp;
-
- list_for_each_entry(clkp, &clock_list, node) {
- if (likely(clkp->parent != clk))
- continue;
- if (likely(clkp->ops && clkp->ops->recalc))
- clkp->ops->recalc(clkp);
- if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
- propagate_rate(clkp);
+ freq_table[i].index = i;
+ freq_table[i].frequency = freq;
}
+
+ /* Termination entry */
+ freq_table[i].index = i;
+ freq_table[i].frequency = CPUFREQ_TABLE_END;
}
-static void __clk_init(struct clk *clk)
+long clk_rate_table_round(struct clk *clk,
+ struct cpufreq_frequency_table *freq_table,
+ unsigned long rate)
{
- /*
- * See if this is the first time we're enabling the clock, some
- * clocks that are always enabled still require "special"
- * initialization. This is especially true if the clock mode
- * changes and the clock needs to hunt for the proper set of
- * divisors to use before it can effectively recalc.
- */
+ unsigned long rate_error, rate_error_prev = ~0UL;
+ unsigned long rate_best_fit = rate;
+ unsigned long highest, lowest;
+ int i;
- if (clk->flags & CLK_NEEDS_INIT) {
- if (clk->ops && clk->ops->init)
- clk->ops->init(clk);
+ highest = lowest = 0;
- clk->flags &= ~CLK_NEEDS_INIT;
- }
-}
+ for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
+ unsigned long freq = freq_table[i].frequency;
-static int __clk_enable(struct clk *clk)
-{
- if (!clk)
- return -EINVAL;
+ if (freq == CPUFREQ_ENTRY_INVALID)
+ continue;
- clk->usecount++;
+ if (freq > highest)
+ highest = freq;
+ if (freq < lowest)
+ lowest = freq;
- /* nothing to do if always enabled */
- if (clk->flags & CLK_ALWAYS_ENABLED)
- return 0;
+ rate_error = abs(freq - rate);
+ if (rate_error < rate_error_prev) {
+ rate_best_fit = freq;
+ rate_error_prev = rate_error;
+ }
- if (clk->usecount == 1) {
- __clk_init(clk);
+ if (rate_error == 0)
+ break;
+ }
- __clk_enable(clk->parent);
+ if (rate >= highest)
+ rate_best_fit = highest;
+ if (rate <= lowest)
+ rate_best_fit = lowest;
- if (clk->ops && clk->ops->enable)
- clk->ops->enable(clk);
- }
+ return rate_best_fit;
+}
- return 0;
+/* Used for clocks that always have same value as the parent clock */
+unsigned long followparent_recalc(struct clk *clk)
+{
+ return clk->parent ? clk->parent->rate : 0;
}
-int clk_enable(struct clk *clk)
+int clk_reparent(struct clk *child, struct clk *parent)
{
- unsigned long flags;
- int ret;
+ list_del_init(&child->sibling);
+ if (parent)
+ list_add(&child->sibling, &parent->children);
+ child->parent = parent;
- spin_lock_irqsave(&clock_lock, flags);
- ret = __clk_enable(clk);
- spin_unlock_irqrestore(&clock_lock, flags);
+ /* now do the debugfs renaming to reattach the child
+ to the proper parent */
- return ret;
+ return 0;
}
-EXPORT_SYMBOL_GPL(clk_enable);
-static void __clk_disable(struct clk *clk)
+/* Propagate rate to children */
+void propagate_rate(struct clk *tclk)
{
- if (!clk)
- return;
+ struct clk *clkp;
- clk->usecount--;
+ list_for_each_entry(clkp, &tclk->children, sibling) {
+ if (clkp->ops && clkp->ops->recalc)
+ clkp->rate = clkp->ops->recalc(clkp);
- WARN_ON(clk->usecount < 0);
+ propagate_rate(clkp);
+ }
+}
- if (clk->flags & CLK_ALWAYS_ENABLED)
+static void __clk_disable(struct clk *clk)
+{
+ if (clk->usecount == 0) {
+ printk(KERN_ERR "Trying disable clock %s with 0 usecount\n",
+ clk->name);
+ WARN_ON(1);
return;
+ }
- if (clk->usecount == 0) {
+ if (!(--clk->usecount)) {
if (likely(clk->ops && clk->ops->disable))
clk->ops->disable(clk);
-
- __clk_disable(clk->parent);
+ if (likely(clk->parent))
+ __clk_disable(clk->parent);
}
}
{
unsigned long flags;
+ if (!clk)
+ return;
+
spin_lock_irqsave(&clock_lock, flags);
__clk_disable(clk);
spin_unlock_irqrestore(&clock_lock, flags);
}
EXPORT_SYMBOL_GPL(clk_disable);
+static int __clk_enable(struct clk *clk)
+{
+ int ret = 0;
+
+ if (clk->usecount++ == 0) {
+ if (clk->parent) {
+ ret = __clk_enable(clk->parent);
+ if (unlikely(ret))
+ goto err;
+ }
+
+ if (clk->ops && clk->ops->enable) {
+ ret = clk->ops->enable(clk);
+ if (ret) {
+ if (clk->parent)
+ __clk_disable(clk->parent);
+ goto err;
+ }
+ }
+ }
+
+ return ret;
+err:
+ clk->usecount--;
+ return ret;
+}
+
+int clk_enable(struct clk *clk)
+{
+ unsigned long flags;
+ int ret;
+
+ if (!clk)
+ return -EINVAL;
+
+ spin_lock_irqsave(&clock_lock, flags);
+ ret = __clk_enable(clk);
+ spin_unlock_irqrestore(&clock_lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+static LIST_HEAD(root_clks);
+
+/**
+ * recalculate_root_clocks - recalculate and propagate all root clocks
+ *
+ * Recalculates all root clocks (clocks with no parent), which if the
+ * clock's .recalc is set correctly, should also propagate their rates.
+ * Called at init.
+ */
+void recalculate_root_clocks(void)
+{
+ struct clk *clkp;
+
+ list_for_each_entry(clkp, &root_clks, sibling) {
+ if (clkp->ops && clkp->ops->recalc)
+ clkp->rate = clkp->ops->recalc(clkp);
+ propagate_rate(clkp);
+ }
+}
+
int clk_register(struct clk *clk)
{
+ if (clk == NULL || IS_ERR(clk))
+ return -EINVAL;
+
+ /*
+ * trap out already registered clocks
+ */
+ if (clk->node.next || clk->node.prev)
+ return 0;
+
mutex_lock(&clock_list_sem);
- list_add(&clk->node, &clock_list);
+ INIT_LIST_HEAD(&clk->children);
clk->usecount = 0;
- clk->flags |= CLK_NEEDS_INIT;
- mutex_unlock(&clock_list_sem);
+ if (clk->parent)
+ list_add(&clk->sibling, &clk->parent->children);
+ else
+ list_add(&clk->sibling, &root_clks);
- if (clk->flags & CLK_ALWAYS_ENABLED) {
- __clk_init(clk);
- pr_debug( "Clock '%s' is ALWAYS_ENABLED\n", clk->name);
- if (clk->ops && clk->ops->enable)
- clk->ops->enable(clk);
- pr_debug( "Enabled.");
- }
+ list_add(&clk->node, &clock_list);
+ if (clk->ops && clk->ops->init)
+ clk->ops->init(clk);
+ mutex_unlock(&clock_list_sem);
return 0;
}
void clk_unregister(struct clk *clk)
{
mutex_lock(&clock_list_sem);
+ list_del(&clk->sibling);
list_del(&clk->node);
mutex_unlock(&clock_list_sem);
}
EXPORT_SYMBOL_GPL(clk_unregister);
+static void clk_enable_init_clocks(void)
+{
+ struct clk *clkp;
+
+ list_for_each_entry(clkp, &clock_list, node)
+ if (clkp->flags & CLK_ENABLE_ON_INIT)
+ clk_enable(clkp);
+}
+
unsigned long clk_get_rate(struct clk *clk)
{
return clk->rate;
int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
{
int ret = -EOPNOTSUPP;
+ unsigned long flags;
- if (likely(clk->ops && clk->ops->set_rate)) {
- unsigned long flags;
+ spin_lock_irqsave(&clock_lock, flags);
- spin_lock_irqsave(&clock_lock, flags);
+ if (likely(clk->ops && clk->ops->set_rate)) {
ret = clk->ops->set_rate(clk, rate, algo_id);
- spin_unlock_irqrestore(&clock_lock, flags);
+ if (ret != 0)
+ goto out_unlock;
+ } else {
+ clk->rate = rate;
+ ret = 0;
}
- if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
- propagate_rate(clk);
+ if (clk->ops && clk->ops->recalc)
+ clk->rate = clk->ops->recalc(clk);
- return ret;
-}
-EXPORT_SYMBOL_GPL(clk_set_rate_ex);
+ propagate_rate(clk);
-void clk_recalc_rate(struct clk *clk)
-{
- if (likely(clk->ops && clk->ops->recalc)) {
- unsigned long flags;
-
- spin_lock_irqsave(&clock_lock, flags);
- clk->ops->recalc(clk);
- spin_unlock_irqrestore(&clock_lock, flags);
- }
+out_unlock:
+ spin_unlock_irqrestore(&clock_lock, flags);
- if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
- propagate_rate(clk);
+ return ret;
}
-EXPORT_SYMBOL_GPL(clk_recalc_rate);
+EXPORT_SYMBOL_GPL(clk_set_rate_ex);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
+ unsigned long flags;
int ret = -EINVAL;
- struct clk *old;
if (!parent || !clk)
return ret;
+ if (clk->parent == parent)
+ return 0;
- old = clk->parent;
- if (likely(clk->ops && clk->ops->set_parent)) {
- unsigned long flags;
- spin_lock_irqsave(&clock_lock, flags);
- ret = clk->ops->set_parent(clk, parent);
- spin_unlock_irqrestore(&clock_lock, flags);
- clk->parent = (ret ? old : parent);
- }
+ spin_lock_irqsave(&clock_lock, flags);
+ if (clk->usecount == 0) {
+ if (clk->ops->set_parent)
+ ret = clk->ops->set_parent(clk, parent);
+ else
+ ret = clk_reparent(clk, parent);
+
+ if (ret == 0) {
+ pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
+ clk->name, clk->parent->name, clk->rate);
+ if (clk->ops->recalc)
+ clk->rate = clk->ops->recalc(clk);
+ propagate_rate(clk);
+ }
+ } else
+ ret = -EBUSY;
+ spin_unlock_irqrestore(&clock_lock, flags);
- if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
- propagate_rate(clk);
return ret;
}
EXPORT_SYMBOL_GPL(clk_set_parent);
}
EXPORT_SYMBOL_GPL(clk_round_rate);
+/*
+ * Find the correct struct clk for the device and connection ID.
+ * We do slightly fuzzy matching here:
+ * An entry with a NULL ID is assumed to be a wildcard.
+ * If an entry has a device ID, it must match
+ * If an entry has a connection ID, it must match
+ * Then we take the most specific entry - with the following
+ * order of precidence: dev+con > dev only > con only.
+ */
+static struct clk *clk_find(const char *dev_id, const char *con_id)
+{
+ struct clk_lookup *p;
+ struct clk *clk = NULL;
+ int match, best = 0;
+
+ list_for_each_entry(p, &clock_list, node) {
+ match = 0;
+ if (p->dev_id) {
+ if (!dev_id || strcmp(p->dev_id, dev_id))
+ continue;
+ match += 2;
+ }
+ if (p->con_id) {
+ if (!con_id || strcmp(p->con_id, con_id))
+ continue;
+ match += 1;
+ }
+ if (match == 0)
+ continue;
+
+ if (match > best) {
+ clk = p->clk;
+ best = match;
+ }
+ }
+ return clk;
+}
+
+struct clk *clk_get_sys(const char *dev_id, const char *con_id)
+{
+ struct clk *clk;
+
+ mutex_lock(&clock_list_sem);
+ clk = clk_find(dev_id, con_id);
+ mutex_unlock(&clock_list_sem);
+
+ return clk ? clk : ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL_GPL(clk_get_sys);
+
/*
* Returns a clock. Note that we first try to use device id on the bus
* and clock name. If this fails, we try to use clock name only.
*/
struct clk *clk_get(struct device *dev, const char *id)
{
+ const char *dev_id = dev ? dev_name(dev) : NULL;
struct clk *p, *clk = ERR_PTR(-ENOENT);
int idno;
+ clk = clk_get_sys(dev_id, id);
+ if (clk && !IS_ERR(clk))
+ return clk;
+
if (dev == NULL || dev->bus != &platform_bus_type)
idno = -1;
else
}
EXPORT_SYMBOL_GPL(clk_put);
-void __init __attribute__ ((weak))
-arch_init_clk_ops(struct clk_ops **ops, int type)
-{
-}
-
-int __init __attribute__ ((weak))
-arch_clk_init(void)
-{
- return 0;
-}
-
-static int show_clocks(char *buf, char **start, off_t off,
- int len, int *eof, void *data)
-{
- struct clk *clk;
- char *p = buf;
-
- list_for_each_entry_reverse(clk, &clock_list, node) {
- unsigned long rate = clk_get_rate(clk);
-
- p += sprintf(p, "%-12s\t: %ld.%02ldMHz\t%s\n", clk->name,
- rate / 1000000, (rate % 1000000) / 10000,
- ((clk->flags & CLK_ALWAYS_ENABLED) ||
- clk->usecount > 0) ?
- "enabled" : "disabled");
- }
-
- return p - buf;
-}
-
#ifdef CONFIG_PM
static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
{
switch (state.event) {
case PM_EVENT_ON:
/* Resumeing from hibernation */
- if (prev_state.event == PM_EVENT_FREEZE) {
- list_for_each_entry(clkp, &clock_list, node)
- if (likely(clkp->ops)) {
- unsigned long rate = clkp->rate;
-
- if (likely(clkp->ops->set_parent))
- clkp->ops->set_parent(clkp,
- clkp->parent);
- if (likely(clkp->ops->set_rate))
- clkp->ops->set_rate(clkp,
- rate, NO_CHANGE);
- else if (likely(clkp->ops->recalc))
- clkp->ops->recalc(clkp);
- }
+ if (prev_state.event != PM_EVENT_FREEZE)
+ break;
+
+ list_for_each_entry(clkp, &clock_list, node) {
+ if (likely(clkp->ops)) {
+ unsigned long rate = clkp->rate;
+
+ if (likely(clkp->ops->set_parent))
+ clkp->ops->set_parent(clkp,
+ clkp->parent);
+ if (likely(clkp->ops->set_rate))
+ clkp->ops->set_rate(clkp,
+ rate, NO_CHANGE);
+ else if (likely(clkp->ops->recalc))
+ clkp->rate = clkp->ops->recalc(clkp);
+ }
}
break;
case PM_EVENT_FREEZE:
int __init clk_init(void)
{
- int i, ret = 0;
-
- BUG_ON(!master_clk.rate);
-
- for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
- struct clk *clk = onchip_clocks[i];
+ int ret;
- arch_init_clk_ops(&clk->ops, i);
- ret |= clk_register(clk);
+ ret = arch_clk_init();
+ if (unlikely(ret)) {
+ pr_err("%s: CPU clock registration failed.\n", __func__);
+ return ret;
}
- ret |= arch_clk_init();
+ if (sh_mv.mv_clk_init) {
+ ret = sh_mv.mv_clk_init();
+ if (unlikely(ret)) {
+ pr_err("%s: machvec clock initialization failed.\n",
+ __func__);
+ return ret;
+ }
+ }
/* Kick the child clocks.. */
- propagate_rate(&master_clk);
- propagate_rate(&bus_clk);
+ recalculate_root_clocks();
+
+ /* Enable the necessary init clocks */
+ clk_enable_init_clocks();
return ret;
}
-static int __init clk_proc_init(void)
+/*
+ * debugfs support to trace clock tree hierarchy and attributes
+ */
+static struct dentry *clk_debugfs_root;
+
+static int clk_debugfs_register_one(struct clk *c)
{
- struct proc_dir_entry *p;
- p = create_proc_read_entry("clocks", S_IRUSR, NULL,
- show_clocks, NULL);
- if (unlikely(!p))
- return -EINVAL;
+ int err;
+ struct dentry *d, *child;
+ struct clk *pa = c->parent;
+ char s[255];
+ char *p = s;
+
+ p += sprintf(p, "%s", c->name);
+ if (c->id >= 0)
+ sprintf(p, ":%d", c->id);
+ d = debugfs_create_dir(s, pa ? pa->dentry : clk_debugfs_root);
+ if (!d)
+ return -ENOMEM;
+ c->dentry = d;
+
+ d = debugfs_create_u8("usecount", S_IRUGO, c->dentry, (u8 *)&c->usecount);
+ if (!d) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+ d = debugfs_create_u32("rate", S_IRUGO, c->dentry, (u32 *)&c->rate);
+ if (!d) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+ d = debugfs_create_x32("flags", S_IRUGO, c->dentry, (u32 *)&c->flags);
+ if (!d) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+ return 0;
+
+err_out:
+ d = c->dentry;
+ list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
+ debugfs_remove(child);
+ debugfs_remove(c->dentry);
+ return err;
+}
+
+static int clk_debugfs_register(struct clk *c)
+{
+ int err;
+ struct clk *pa = c->parent;
+
+ if (pa && !pa->dentry) {
+ err = clk_debugfs_register(pa);
+ if (err)
+ return err;
+ }
+ if (!c->dentry) {
+ err = clk_debugfs_register_one(c);
+ if (err)
+ return err;
+ }
+ return 0;
+}
+
+static int __init clk_debugfs_init(void)
+{
+ struct clk *c;
+ struct dentry *d;
+ int err;
+
+ d = debugfs_create_dir("clock", NULL);
+ if (!d)
+ return -ENOMEM;
+ clk_debugfs_root = d;
+
+ list_for_each_entry(c, &clock_list, node) {
+ err = clk_debugfs_register(c);
+ if (err)
+ goto err_out;
+ }
return 0;
+err_out:
+ debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */
+ return err;
}
-subsys_initcall(clk_proc_init);
+late_initcall(clk_debugfs_init);
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FREQCR) & 0x0007);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7619_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
- clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
+ return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
}
static struct clk_ops sh7619_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
-{
- clk->rate = clk->parent->rate;
-}
-
static struct clk_ops sh7619_cpu_clk_ops = {
- .recalc = cpu_clk_recalc,
+ .recalc = followparent_recalc,
};
static struct clk_ops *sh7619_clk_ops[] = {
if (idx < ARRAY_SIZE(sh7619_clk_ops))
*ops = sh7619_clk_ops[idx];
}
-
.name = "CMT0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
.name = "CMT1",
.channel_offset = 0x08,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
static void master_clk_init(struct clk *clk)
{
- clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
+ return 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
}
static struct clk_ops sh7201_master_clk_ops = {
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FREQCR) & 0x0007);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7201_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FREQCR) & 0x0007);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7201_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007);
- clk->rate = clk->parent->rate / ifc_divisors[idx];
+ return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7201_cpu_clk_ops = {
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FREQCR) & 0x0007);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7203_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FREQCR) & 0x0007);
- clk->rate = clk->parent->rate / pfc_divisors[idx-2];
+ return clk->parent->rate / pfc_divisors[idx-2];
}
static struct clk_ops sh7203_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
-{
- clk->rate = clk->parent->rate;
-}
-
static struct clk_ops sh7203_cpu_clk_ops = {
- .recalc = cpu_clk_recalc,
+ .recalc = followparent_recalc,
};
static struct clk_ops *sh7203_clk_ops[] = {
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FREQCR) & 0x0007);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7206_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
- clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
+ return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
}
static struct clk_ops sh7206_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FREQCR) & 0x0007);
- clk->rate = clk->parent->rate / ifc_divisors[idx];
+ return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7206_cpu_clk_ops = {
.name = "MTU2_0",
.channel_offset = -0x80,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_1",
.channel_offset = -0x100,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_2",
.channel_offset = 0x80,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_0",
.channel_offset = -0x80,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_1",
.channel_offset = -0x100,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_2",
.channel_offset = 0x80,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "CMT0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
.name = "CMT1",
.channel_offset = 0x08,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
.name = "MTU2_0",
.channel_offset = -0x80,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_1",
.channel_offset = -0x100,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "CMT0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
.name = "CMT1",
.channel_offset = 0x08,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
.name = "MTU2_0",
.channel_offset = -0x80,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_1",
.channel_offset = -0x100,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_2",
.channel_offset = 0x80,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh3_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
- clk->rate = clk->parent->rate / stc_multipliers[idx];
+ return clk->parent->rate / stc_multipliers[idx];
}
static struct clk_ops sh3_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
- clk->rate = clk->parent->rate / ifc_divisors[idx];
+ return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh3_cpu_clk_ops = {
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = ctrl_inw(FRQCR) & 0x0003;
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7705_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8;
- clk->rate = clk->parent->rate / stc_multipliers[idx];
+ return clk->parent->rate / stc_multipliers[idx];
}
static struct clk_ops sh7705_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4;
- clk->rate = clk->parent->rate / ifc_divisors[idx];
+ return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7705_cpu_clk_ops = {
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7706_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
- clk->rate = clk->parent->rate / stc_multipliers[idx];
+ return clk->parent->rate / stc_multipliers[idx];
}
static struct clk_ops sh7706_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
- clk->rate = clk->parent->rate / ifc_divisors[idx];
+ return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7706_cpu_clk_ops = {
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7709_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int idx = (frqcr & 0x0080) ?
((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1;
- clk->rate = clk->parent->rate * stc_multipliers[idx];
+ return clk->parent->rate * stc_multipliers[idx];
}
static struct clk_ops sh7709_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
- clk->rate = clk->parent->rate / ifc_divisors[idx];
+ return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7709_cpu_clk_ops = {
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FRQCR) & 0x0007);
- clk->rate = clk->parent->rate / md_table[idx];
+ return clk->parent->rate / md_table[idx];
}
static struct clk_ops sh7710_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FRQCR) & 0x0700) >> 8;
- clk->rate = clk->parent->rate / md_table[idx];
+ return clk->parent->rate / md_table[idx];
}
static struct clk_ops sh7710_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FRQCR) & 0x0070) >> 4;
- clk->rate = clk->parent->rate / md_table[idx];
+ return clk->parent->rate / md_table[idx];
}
static struct clk_ops sh7710_cpu_clk_ops = {
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int idx = frqcr & 0x0007;
- clk->rate = clk->parent->rate / divisors[idx];
+ return clk->parent->rate / divisors[idx];
}
static struct clk_ops sh7712_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int idx = (frqcr & 0x0030) >> 4;
- clk->rate = clk->parent->rate / divisors[idx];
+ return clk->parent->rate / divisors[idx];
}
static struct clk_ops sh7712_cpu_clk_ops = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "CMT0",
.channel_offset = 0x10,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 125,
};
.name = "CMT1",
.channel_offset = 0x20,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource cmt1_resources[] = {
.name = "CMT2",
.channel_offset = 0x30,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource cmt2_resources[] = {
.name = "CMT3",
.channel_offset = 0x40,
.timer_bit = 3,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource cmt3_resources[] = {
.name = "CMT4",
.channel_offset = 0x50,
.timer_bit = 4,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource cmt4_resources[] = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 };
static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 };
-static void emi_clk_recalc(struct clk *clk)
+static unsigned long emi_clk_recalc(struct clk *clk)
{
int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007;
- clk->rate = clk->parent->rate / frqcr3_divisors[idx];
+ return clk->parent->rate / frqcr3_divisors[idx];
}
static inline int frqcr3_lookup(struct clk *clk, unsigned long rate)
static struct clk sh4202_emi_clk = {
.name = "emi_clk",
- .flags = CLK_ALWAYS_ENABLED,
+ .flags = CLK_ENABLE_ON_INIT,
.ops = &sh4202_emi_clk_ops,
};
-static void femi_clk_recalc(struct clk *clk)
+static unsigned long femi_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007;
- clk->rate = clk->parent->rate / frqcr3_divisors[idx];
+ return clk->parent->rate / frqcr3_divisors[idx];
}
static struct clk_ops sh4202_femi_clk_ops = {
static struct clk sh4202_femi_clk = {
.name = "femi_clk",
- .flags = CLK_ALWAYS_ENABLED,
+ .flags = CLK_ENABLE_ON_INIT,
.ops = &sh4202_femi_clk_ops,
};
WARN_ON(i == ARRAY_SIZE(frqcr3_divisors)); /* Undefined clock */
}
-static void shoc_clk_recalc(struct clk *clk)
+static unsigned long shoc_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007;
- clk->rate = clk->parent->rate / frqcr3_divisors[idx];
+ return clk->parent->rate / frqcr3_divisors[idx];
}
static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
static struct clk sh4202_shoc_clk = {
.name = "shoc_clk",
- .flags = CLK_ALWAYS_ENABLED,
+ .flags = CLK_ENABLE_ON_INIT,
.ops = &sh4202_shoc_clk_ops,
};
&sh4202_shoc_clk,
};
-static int __init sh4202_clk_init(void)
+int __init arch_clk_init(void)
{
- struct clk *clk = clk_get(NULL, "master_clk");
- int i;
+ struct clk *clk;
+ int i, ret = 0;
+
+ cpg_clk_init();
+ clk = clk_get(NULL, "master_clk");
for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) {
struct clk *clkp = sh4202_onchip_clocks[i];
clkp->parent = clk;
- clk_register(clkp);
- clk_enable(clkp);
+ ret |= clk_register(clkp);
}
- /*
- * Now that we have the rest of the clocks registered, we need to
- * force the parent clock to propagate so that these clocks will
- * automatically figure out their rate. We cheat by handing the
- * parent clock its current rate and forcing child propagation.
- */
- clk_set_rate(clk, clk_get_rate(clk));
-
clk_put(clk);
- return 0;
+ return ret;
}
-
-arch_initcall(sh4202_clk_init);
-
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FRQCR) & 0x0007);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh4_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FRQCR) >> 3) & 0x0007;
- clk->rate = clk->parent->rate / bfc_divisors[idx];
+ return clk->parent->rate / bfc_divisors[idx];
}
static struct clk_ops sh4_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FRQCR) >> 6) & 0x0007;
- clk->rate = clk->parent->rate / ifc_divisors[idx];
+ return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh4_cpu_clk_ops = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
#endif
-static void master_clk_recalc(struct clk *clk)
+static unsigned long master_clk_recalc(struct clk *clk)
{
unsigned frqcr = ctrl_inl(FRQCR);
- clk->rate = CONFIG_SH_PCLK_FREQ * STCPLL(frqcr);
+ return CONFIG_SH_PCLK_FREQ * STCPLL(frqcr);
}
static void master_clk_init(struct clk *clk)
{
clk->parent = NULL;
- clk->flags |= CLK_RATE_PROPAGATES;
- clk->rate = CONFIG_SH_PCLK_FREQ;
- master_clk_recalc(clk);
+ clk->rate = master_clk_recalc(clk);
}
-
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
unsigned long frqcr = ctrl_inl(FRQCR);
- clk->rate = clk->parent->rate / STCPLL(frqcr);
+ return clk->parent->rate / STCPLL(frqcr);
}
#if defined(CONFIG_CPU_SUBTYPE_SH7724)
return index;
}
-static void sh7722_frqcr_recalc(struct clk *clk)
+static unsigned long sh7722_frqcr_recalc(struct clk *clk)
{
struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
unsigned long frqcr = ctrl_inl(FRQCR);
int index;
index = (frqcr >> ctx.shift) & ctx.mask;
- clk->rate = clk->parent->rate * 2 / divisors2[index];
+ return clk->parent->rate * 2 / divisors2[index];
}
static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
/*
* clock ops methods for SIU A/B and IrDA clock
- *
*/
-
#ifndef CONFIG_CPU_SUBTYPE_SH7343
-
static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
{
unsigned long r;
return 0;
}
-static void sh7722_siu_recalc(struct clk *clk)
+static unsigned long sh7722_siu_recalc(struct clk *clk)
{
unsigned long r;
r = ctrl_inl(clk->arch_flags);
- clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF];
+ return clk->parent->rate * 2 / divisors2[r & 0xF];
}
static int sh7722_siu_start_stop(struct clk *clk, int enable)
return 0;
}
-static void sh7722_siu_enable(struct clk *clk)
+static int sh7722_siu_enable(struct clk *clk)
{
- sh7722_siu_start_stop(clk, 1);
+ return sh7722_siu_start_stop(clk, 1);
}
static void sh7722_siu_disable(struct clk *clk)
#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
-static void sh7722_video_enable(struct clk *clk)
+static int sh7722_video_enable(struct clk *clk)
{
unsigned long r;
r = ctrl_inl(VCLKCR);
ctrl_outl( r & ~(1<<8), VCLKCR);
+ return 0;
}
static void sh7722_video_disable(struct clk *clk)
return 0;
}
-static void sh7722_video_recalc(struct clk *clk)
+static unsigned long sh7722_video_recalc(struct clk *clk)
{
unsigned long r;
r = ctrl_inl(VCLKCR);
- clk->rate = clk->parent->rate / ((r & 0x3F) + 1);
+ return clk->parent->rate / ((r & 0x3F) + 1);
}
static struct clk_ops sh7722_video_clk_ops = {
static struct clk sh7722_umem_clock = {
.name = "umem_clk",
.ops = &sh7722_frqcr_clk_ops,
- .flags = CLK_RATE_PROPAGATES,
};
static struct clk sh7722_sh_clock = {
.name = "sh_clk",
.ops = &sh7722_frqcr_clk_ops,
- .flags = CLK_RATE_PROPAGATES,
};
static struct clk sh7722_peripheral_clock = {
.name = "peripheral_clk",
.ops = &sh7722_frqcr_clk_ops,
- .flags = CLK_RATE_PROPAGATES,
};
static struct clk sh7722_sdram_clock = {
static struct clk sh7722_r_clock = {
.name = "r_clk",
.rate = 32768,
- .flags = CLK_RATE_PROPAGATES,
};
#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
break;
default:
return -EINVAL;
- }
+ }
r = ctrl_inl(reg);
return 0;
}
-static void sh7722_mstpcr_enable(struct clk *clk)
+static int sh7722_mstpcr_enable(struct clk *clk)
{
- sh7722_mstpcr_start_stop(clk, 1);
+ return sh7722_mstpcr_start_stop(clk, 1);
}
static void sh7722_mstpcr_disable(struct clk *clk)
sh7722_mstpcr_start_stop(clk, 0);
}
-static void sh7722_mstpcr_recalc(struct clk *clk)
-{
- if (clk->parent)
- clk->rate = clk->parent->rate;
-}
-
static struct clk_ops sh7722_mstpcr_clk_ops = {
.enable = sh7722_mstpcr_enable,
.disable = sh7722_mstpcr_disable,
- .recalc = sh7722_mstpcr_recalc,
+ .recalc = followparent_recalc,
};
-#define MSTPCR(_name, _parent, regnr, bitnr) \
+#define MSTPCR(_name, _parent, regnr, bitnr, _flags) \
{ \
.name = _name, \
+ .flags = _flags, \
.arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \
.ops = (void *)_parent, \
}
static struct clk sh7722_mstpcr_clocks[] = {
#if defined(CONFIG_CPU_SUBTYPE_SH7722)
- MSTPCR("uram0", "umem_clk", 0, 28),
- MSTPCR("xymem0", "bus_clk", 0, 26),
- MSTPCR("tmu0", "peripheral_clk", 0, 15),
- MSTPCR("cmt0", "r_clk", 0, 14),
- MSTPCR("rwdt0", "r_clk", 0, 13),
- MSTPCR("flctl0", "peripheral_clk", 0, 10),
- MSTPCR("scif0", "peripheral_clk", 0, 7),
- MSTPCR("scif1", "peripheral_clk", 0, 6),
- MSTPCR("scif2", "peripheral_clk", 0, 5),
- MSTPCR("i2c0", "peripheral_clk", 1, 9),
- MSTPCR("rtc0", "r_clk", 1, 8),
- MSTPCR("sdhi0", "peripheral_clk", 2, 18),
- MSTPCR("keysc0", "r_clk", 2, 14),
- MSTPCR("usbf0", "peripheral_clk", 2, 11),
- MSTPCR("2dg0", "bus_clk", 2, 9),
- MSTPCR("siu0", "bus_clk", 2, 8),
- MSTPCR("vou0", "bus_clk", 2, 5),
- MSTPCR("jpu0", "bus_clk", 2, 6),
- MSTPCR("beu0", "bus_clk", 2, 4),
- MSTPCR("ceu0", "bus_clk", 2, 3),
- MSTPCR("veu0", "bus_clk", 2, 2),
- MSTPCR("vpu0", "bus_clk", 2, 1),
- MSTPCR("lcdc0", "bus_clk", 2, 0),
+ MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT),
+ MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT),
+ MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
+ MSTPCR("cmt0", "r_clk", 0, 14, 0),
+ MSTPCR("rwdt0", "r_clk", 0, 13, 0),
+ MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
+ MSTPCR("scif0", "peripheral_clk", 0, 7, 0),
+ MSTPCR("scif1", "peripheral_clk", 0, 6, 0),
+ MSTPCR("scif2", "peripheral_clk", 0, 5, 0),
+ MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
+ MSTPCR("rtc0", "r_clk", 1, 8, 0),
+ MSTPCR("sdhi0", "peripheral_clk", 2, 18, 0),
+ MSTPCR("keysc0", "r_clk", 2, 14, 0),
+ MSTPCR("usbf0", "peripheral_clk", 2, 11, 0),
+ MSTPCR("2dg0", "bus_clk", 2, 9, 0),
+ MSTPCR("siu0", "bus_clk", 2, 8, 0),
+ MSTPCR("vou0", "bus_clk", 2, 5, 0),
+ MSTPCR("jpu0", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT),
+ MSTPCR("beu0", "bus_clk", 2, 4, 0),
+ MSTPCR("ceu0", "bus_clk", 2, 3, 0),
+ MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
+ MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
+ MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7723)
/* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
- MSTPCR("tlb0", "cpu_clk", 0, 31),
- MSTPCR("ic0", "cpu_clk", 0, 30),
- MSTPCR("oc0", "cpu_clk", 0, 29),
- MSTPCR("l2c0", "sh_clk", 0, 28),
- MSTPCR("ilmem0", "cpu_clk", 0, 27),
- MSTPCR("fpu0", "cpu_clk", 0, 24),
- MSTPCR("intc0", "cpu_clk", 0, 22),
- MSTPCR("dmac0", "bus_clk", 0, 21),
- MSTPCR("sh0", "sh_clk", 0, 20),
- MSTPCR("hudi0", "peripheral_clk", 0, 19),
- MSTPCR("ubc0", "cpu_clk", 0, 17),
- MSTPCR("tmu0", "peripheral_clk", 0, 15),
- MSTPCR("cmt0", "r_clk", 0, 14),
- MSTPCR("rwdt0", "r_clk", 0, 13),
- MSTPCR("dmac1", "bus_clk", 0, 12),
- MSTPCR("tmu1", "peripheral_clk", 0, 11),
- MSTPCR("flctl0", "peripheral_clk", 0, 10),
- MSTPCR("scif0", "peripheral_clk", 0, 9),
- MSTPCR("scif1", "peripheral_clk", 0, 8),
- MSTPCR("scif2", "peripheral_clk", 0, 7),
- MSTPCR("scif3", "bus_clk", 0, 6),
- MSTPCR("scif4", "bus_clk", 0, 5),
- MSTPCR("scif5", "bus_clk", 0, 4),
- MSTPCR("msiof0", "bus_clk", 0, 2),
- MSTPCR("msiof1", "bus_clk", 0, 1),
- MSTPCR("meram0", "sh_clk", 0, 0),
- MSTPCR("i2c0", "peripheral_clk", 1, 9),
- MSTPCR("rtc0", "r_clk", 1, 8),
- MSTPCR("atapi0", "sh_clk", 2, 28),
- MSTPCR("adc0", "peripheral_clk", 2, 28),
- MSTPCR("tpu0", "bus_clk", 2, 25),
- MSTPCR("irda0", "peripheral_clk", 2, 24),
- MSTPCR("tsif0", "bus_clk", 2, 22),
- MSTPCR("icb0", "bus_clk", 2, 21),
- MSTPCR("sdhi0", "bus_clk", 2, 18),
- MSTPCR("sdhi1", "bus_clk", 2, 17),
- MSTPCR("keysc0", "r_clk", 2, 14),
- MSTPCR("usb0", "bus_clk", 2, 11),
- MSTPCR("2dg0", "bus_clk", 2, 10),
- MSTPCR("siu0", "bus_clk", 2, 8),
- MSTPCR("veu1", "bus_clk", 2, 6),
- MSTPCR("vou0", "bus_clk", 2, 5),
- MSTPCR("beu0", "bus_clk", 2, 4),
- MSTPCR("ceu0", "bus_clk", 2, 3),
- MSTPCR("veu0", "bus_clk", 2, 2),
- MSTPCR("vpu0", "bus_clk", 2, 1),
- MSTPCR("lcdc0", "bus_clk", 2, 0),
+ MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
+ MSTPCR("ic0", "cpu_clk", 0, 30, 0),
+ MSTPCR("oc0", "cpu_clk", 0, 29, 0),
+ MSTPCR("l2c0", "sh_clk", 0, 28, 0),
+ MSTPCR("ilmem0", "cpu_clk", 0, 27, 0),
+ MSTPCR("fpu0", "cpu_clk", 0, 24, 0),
+ MSTPCR("intc0", "cpu_clk", 0, 22, 0),
+ MSTPCR("dmac0", "bus_clk", 0, 21, 0),
+ MSTPCR("sh0", "sh_clk", 0, 20, 0),
+ MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
+ MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
+ MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
+ MSTPCR("cmt0", "r_clk", 0, 14, 0),
+ MSTPCR("rwdt0", "r_clk", 0, 13, 0),
+ MSTPCR("dmac1", "bus_clk", 0, 12, 0),
+ MSTPCR("tmu1", "peripheral_clk", 0, 11, 0),
+ MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
+ MSTPCR("scif0", "peripheral_clk", 0, 9, 0),
+ MSTPCR("scif1", "peripheral_clk", 0, 8, 0),
+ MSTPCR("scif2", "peripheral_clk", 0, 7, 0),
+ MSTPCR("scif3", "bus_clk", 0, 6, 0),
+ MSTPCR("scif4", "bus_clk", 0, 5, 0),
+ MSTPCR("scif5", "bus_clk", 0, 4, 0),
+ MSTPCR("msiof0", "bus_clk", 0, 2, 0),
+ MSTPCR("msiof1", "bus_clk", 0, 1, 0),
+ MSTPCR("meram0", "sh_clk", 0, 0, CLK_ENABLE_ON_INIT),
+ MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
+ MSTPCR("rtc0", "r_clk", 1, 8, 0),
+ MSTPCR("atapi0", "sh_clk", 2, 28, 0),
+ MSTPCR("adc0", "peripheral_clk", 2, 28, 0),
+ MSTPCR("tpu0", "bus_clk", 2, 25, 0),
+ MSTPCR("irda0", "peripheral_clk", 2, 24, 0),
+ MSTPCR("tsif0", "bus_clk", 2, 22, 0),
+ MSTPCR("icb0", "bus_clk", 2, 21, 0),
+ MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
+ MSTPCR("sdhi1", "bus_clk", 2, 17, 0),
+ MSTPCR("keysc0", "r_clk", 2, 14, 0),
+ MSTPCR("usb0", "bus_clk", 2, 11, 0),
+ MSTPCR("2dg0", "bus_clk", 2, 10, 0),
+ MSTPCR("siu0", "bus_clk", 2, 8, 0),
+ MSTPCR("veu1", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT),
+ MSTPCR("vou0", "bus_clk", 2, 5, 0),
+ MSTPCR("beu0", "bus_clk", 2, 4, 0),
+ MSTPCR("ceu0", "bus_clk", 2, 3, 0),
+ MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
+ MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
+ MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7724)
/* See Datasheet : Overview -> Block Diagram */
- MSTPCR("tlb0", "cpu_clk", 0, 31),
- MSTPCR("ic0", "cpu_clk", 0, 30),
- MSTPCR("oc0", "cpu_clk", 0, 29),
- MSTPCR("rs0", "bus_clk", 0, 28),
- MSTPCR("ilmem0", "cpu_clk", 0, 27),
- MSTPCR("l2c0", "sh_clk", 0, 26),
- MSTPCR("fpu0", "cpu_clk", 0, 24),
- MSTPCR("intc0", "peripheral_clk", 0, 22),
- MSTPCR("dmac0", "bus_clk", 0, 21),
- MSTPCR("sh0", "sh_clk", 0, 20),
- MSTPCR("hudi0", "peripheral_clk", 0, 19),
- MSTPCR("ubc0", "cpu_clk", 0, 17),
- MSTPCR("tmu0", "peripheral_clk", 0, 15),
- MSTPCR("cmt0", "r_clk", 0, 14),
- MSTPCR("rwdt0", "r_clk", 0, 13),
- MSTPCR("dmac1", "bus_clk", 0, 12),
- MSTPCR("tmu1", "peripheral_clk", 0, 10),
- MSTPCR("scif0", "peripheral_clk", 0, 9),
- MSTPCR("scif1", "peripheral_clk", 0, 8),
- MSTPCR("scif2", "peripheral_clk", 0, 7),
- MSTPCR("scif3", "bus_clk", 0, 6),
- MSTPCR("scif4", "bus_clk", 0, 5),
- MSTPCR("scif5", "bus_clk", 0, 4),
- MSTPCR("msiof0", "bus_clk", 0, 2),
- MSTPCR("msiof1", "bus_clk", 0, 1),
- MSTPCR("keysc0", "r_clk", 1, 12),
- MSTPCR("rtc0", "r_clk", 1, 11),
- MSTPCR("i2c0", "peripheral_clk", 1, 9),
- MSTPCR("i2c1", "peripheral_clk", 1, 8),
- MSTPCR("mmc0", "bus_clk", 2, 29),
- MSTPCR("eth0", "bus_clk", 2, 28),
- MSTPCR("atapi0", "bus_clk", 2, 26),
- MSTPCR("tpu0", "bus_clk", 2, 25),
- MSTPCR("irda0", "peripheral_clk", 2, 24),
- MSTPCR("tsif0", "bus_clk", 2, 22),
- MSTPCR("usb1", "bus_clk", 2, 21),
- MSTPCR("usb0", "bus_clk", 2, 20),
- MSTPCR("2dg0", "bus_clk", 2, 19),
- MSTPCR("sdhi0", "bus_clk", 2, 18),
- MSTPCR("sdhi1", "bus_clk", 2, 17),
- MSTPCR("veu1", "bus_clk", 2, 15),
- MSTPCR("ceu1", "bus_clk", 2, 13),
- MSTPCR("beu1", "bus_clk", 2, 12),
- MSTPCR("2ddmac0", "sh_clk", 2, 10),
- MSTPCR("spu0", "bus_clk", 2, 9),
- MSTPCR("jpu0", "bus_clk", 2, 6),
- MSTPCR("vou0", "bus_clk", 2, 5),
- MSTPCR("beu0", "bus_clk", 2, 4),
- MSTPCR("ceu0", "bus_clk", 2, 3),
- MSTPCR("veu0", "bus_clk", 2, 2),
- MSTPCR("vpu0", "bus_clk", 2, 1),
- MSTPCR("lcdc0", "bus_clk", 2, 0),
+ MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
+ MSTPCR("ic0", "cpu_clk", 0, 30, 0),
+ MSTPCR("oc0", "cpu_clk", 0, 29, 0),
+ MSTPCR("rs0", "bus_clk", 0, 28, 0),
+ MSTPCR("ilmem0", "cpu_clk", 0, 27, 0),
+ MSTPCR("l2c0", "sh_clk", 0, 26, 0),
+ MSTPCR("fpu0", "cpu_clk", 0, 24, 0),
+ MSTPCR("intc0", "peripheral_clk", 0, 22, 0),
+ MSTPCR("dmac0", "bus_clk", 0, 21, 0),
+ MSTPCR("sh0", "sh_clk", 0, 20, 0),
+ MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
+ MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
+ MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
+ MSTPCR("cmt0", "r_clk", 0, 14, 0),
+ MSTPCR("rwdt0", "r_clk", 0, 13, 0),
+ MSTPCR("dmac1", "bus_clk", 0, 12, 0),
+ MSTPCR("tmu1", "peripheral_clk", 0, 10, 0),
+ MSTPCR("scif0", "peripheral_clk", 0, 9, 0),
+ MSTPCR("scif1", "peripheral_clk", 0, 8, 0),
+ MSTPCR("scif2", "peripheral_clk", 0, 7, 0),
+ MSTPCR("scif3", "bus_clk", 0, 6, 0),
+ MSTPCR("scif4", "bus_clk", 0, 5, 0),
+ MSTPCR("scif5", "bus_clk", 0, 4, 0),
+ MSTPCR("msiof0", "bus_clk", 0, 2, 0),
+ MSTPCR("msiof1", "bus_clk", 0, 1, 0),
+ MSTPCR("keysc0", "r_clk", 1, 12, 0),
+ MSTPCR("rtc0", "r_clk", 1, 11, 0),
+ MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
+ MSTPCR("i2c1", "peripheral_clk", 1, 8, 0),
+ MSTPCR("mmc0", "bus_clk", 2, 29, 0),
+ MSTPCR("eth0", "bus_clk", 2, 28, 0),
+ MSTPCR("atapi0", "bus_clk", 2, 26, 0),
+ MSTPCR("tpu0", "bus_clk", 2, 25, 0),
+ MSTPCR("irda0", "peripheral_clk", 2, 24, 0),
+ MSTPCR("tsif0", "bus_clk", 2, 22, 0),
+ MSTPCR("usb1", "bus_clk", 2, 21, 0),
+ MSTPCR("usb0", "bus_clk", 2, 20, 0),
+ MSTPCR("2dg0", "bus_clk", 2, 19, 0),
+ MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
+ MSTPCR("sdhi1", "bus_clk", 2, 17, 0),
+ MSTPCR("veu1", "bus_clk", 2, 15, CLK_ENABLE_ON_INIT),
+ MSTPCR("ceu1", "bus_clk", 2, 13, 0),
+ MSTPCR("beu1", "bus_clk", 2, 12, 0),
+ MSTPCR("2ddmac0", "sh_clk", 2, 10, 0),
+ MSTPCR("spu0", "bus_clk", 2, 9, 0),
+ MSTPCR("jpu0", "bus_clk", 2, 6, 0),
+ MSTPCR("vou0", "bus_clk", 2, 5, 0),
+ MSTPCR("beu0", "bus_clk", 2, 4, 0),
+ MSTPCR("ceu0", "bus_clk", 2, 3, 0),
+ MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
+ MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
+ MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7343)
- MSTPCR("uram0", "umem_clk", 0, 28),
- MSTPCR("xymem0", "bus_clk", 0, 26),
- MSTPCR("tmu0", "peripheral_clk", 0, 15),
- MSTPCR("cmt0", "r_clk", 0, 14),
- MSTPCR("rwdt0", "r_clk", 0, 13),
- MSTPCR("scif0", "peripheral_clk", 0, 7),
- MSTPCR("scif1", "peripheral_clk", 0, 6),
- MSTPCR("scif2", "peripheral_clk", 0, 5),
- MSTPCR("scif3", "peripheral_clk", 0, 4),
- MSTPCR("i2c0", "peripheral_clk", 1, 9),
- MSTPCR("i2c1", "peripheral_clk", 1, 8),
- MSTPCR("sdhi0", "peripheral_clk", 2, 18),
- MSTPCR("keysc0", "r_clk", 2, 14),
- MSTPCR("usbf0", "peripheral_clk", 2, 11),
- MSTPCR("siu0", "bus_clk", 2, 8),
- MSTPCR("jpu0", "bus_clk", 2, 6),
- MSTPCR("vou0", "bus_clk", 2, 5),
- MSTPCR("beu0", "bus_clk", 2, 4),
- MSTPCR("ceu0", "bus_clk", 2, 3),
- MSTPCR("veu0", "bus_clk", 2, 2),
- MSTPCR("vpu0", "bus_clk", 2, 1),
- MSTPCR("lcdc0", "bus_clk", 2, 0),
+ MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT),
+ MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT),
+ MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
+ MSTPCR("cmt0", "r_clk", 0, 14, 0),
+ MSTPCR("rwdt0", "r_clk", 0, 13, 0),
+ MSTPCR("scif0", "peripheral_clk", 0, 7, 0),
+ MSTPCR("scif1", "peripheral_clk", 0, 6, 0),
+ MSTPCR("scif2", "peripheral_clk", 0, 5, 0),
+ MSTPCR("scif3", "peripheral_clk", 0, 4, 0),
+ MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
+ MSTPCR("i2c1", "peripheral_clk", 1, 8, 0),
+ MSTPCR("sdhi0", "peripheral_clk", 2, 18, 0),
+ MSTPCR("keysc0", "r_clk", 2, 14, 0),
+ MSTPCR("usbf0", "peripheral_clk", 2, 11, 0),
+ MSTPCR("siu0", "bus_clk", 2, 8, 0),
+ MSTPCR("jpu0", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT),
+ MSTPCR("vou0", "bus_clk", 2, 5, 0),
+ MSTPCR("beu0", "bus_clk", 2, 4, 0),
+ MSTPCR("ceu0", "bus_clk", 2, 3, 0),
+ MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
+ MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
+ MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7366)
/* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
- MSTPCR("tlb0", "cpu_clk", 0, 31),
- MSTPCR("ic0", "cpu_clk", 0, 30),
- MSTPCR("oc0", "cpu_clk", 0, 29),
- MSTPCR("rsmem0", "sh_clk", 0, 28),
- MSTPCR("xymem0", "cpu_clk", 0, 26),
- MSTPCR("intc30", "peripheral_clk", 0, 23),
- MSTPCR("intc0", "peripheral_clk", 0, 22),
- MSTPCR("dmac0", "bus_clk", 0, 21),
- MSTPCR("sh0", "sh_clk", 0, 20),
- MSTPCR("hudi0", "peripheral_clk", 0, 19),
- MSTPCR("ubc0", "cpu_clk", 0, 17),
- MSTPCR("tmu0", "peripheral_clk", 0, 15),
- MSTPCR("cmt0", "r_clk", 0, 14),
- MSTPCR("rwdt0", "r_clk", 0, 13),
- MSTPCR("flctl0", "peripheral_clk", 0, 10),
- MSTPCR("scif0", "peripheral_clk", 0, 7),
- MSTPCR("scif1", "bus_clk", 0, 6),
- MSTPCR("scif2", "bus_clk", 0, 5),
- MSTPCR("msiof0", "peripheral_clk", 0, 2),
- MSTPCR("sbr0", "peripheral_clk", 0, 1),
- MSTPCR("i2c0", "peripheral_clk", 1, 9),
- MSTPCR("icb0", "bus_clk", 2, 27),
- MSTPCR("meram0", "sh_clk", 2, 26),
- MSTPCR("dacc0", "peripheral_clk", 2, 24),
- MSTPCR("dacy0", "peripheral_clk", 2, 23),
- MSTPCR("tsif0", "bus_clk", 2, 22),
- MSTPCR("sdhi0", "bus_clk", 2, 18),
- MSTPCR("mmcif0", "bus_clk", 2, 17),
- MSTPCR("usb0", "bus_clk", 2, 11),
- MSTPCR("siu0", "bus_clk", 2, 8),
- MSTPCR("veu1", "bus_clk", 2, 7),
- MSTPCR("vou0", "bus_clk", 2, 5),
- MSTPCR("beu0", "bus_clk", 2, 4),
- MSTPCR("ceu0", "bus_clk", 2, 3),
- MSTPCR("veu0", "bus_clk", 2, 2),
- MSTPCR("vpu0", "bus_clk", 2, 1),
- MSTPCR("lcdc0", "bus_clk", 2, 0),
+ MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
+ MSTPCR("ic0", "cpu_clk", 0, 30, 0),
+ MSTPCR("oc0", "cpu_clk", 0, 29, 0),
+ MSTPCR("rsmem0", "sh_clk", 0, 28, CLK_ENABLE_ON_INIT),
+ MSTPCR("xymem0", "cpu_clk", 0, 26, CLK_ENABLE_ON_INIT),
+ MSTPCR("intc30", "peripheral_clk", 0, 23, 0),
+ MSTPCR("intc0", "peripheral_clk", 0, 22, 0),
+ MSTPCR("dmac0", "bus_clk", 0, 21, 0),
+ MSTPCR("sh0", "sh_clk", 0, 20, 0),
+ MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
+ MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
+ MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
+ MSTPCR("cmt0", "r_clk", 0, 14, 0),
+ MSTPCR("rwdt0", "r_clk", 0, 13, 0),
+ MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
+ MSTPCR("scif0", "peripheral_clk", 0, 7, 0),
+ MSTPCR("scif1", "bus_clk", 0, 6, 0),
+ MSTPCR("scif2", "bus_clk", 0, 5, 0),
+ MSTPCR("msiof0", "peripheral_clk", 0, 2, 0),
+ MSTPCR("sbr0", "peripheral_clk", 0, 1, 0),
+ MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
+ MSTPCR("icb0", "bus_clk", 2, 27, 0),
+ MSTPCR("meram0", "sh_clk", 2, 26, 0),
+ MSTPCR("dacc0", "peripheral_clk", 2, 24, 0),
+ MSTPCR("dacy0", "peripheral_clk", 2, 23, 0),
+ MSTPCR("tsif0", "bus_clk", 2, 22, 0),
+ MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
+ MSTPCR("mmcif0", "bus_clk", 2, 17, 0),
+ MSTPCR("usb0", "bus_clk", 2, 11, 0),
+ MSTPCR("siu0", "bus_clk", 2, 8, 0),
+ MSTPCR("veu1", "bus_clk", 2, 7, CLK_ENABLE_ON_INIT),
+ MSTPCR("vou0", "bus_clk", 2, 5, 0),
+ MSTPCR("beu0", "bus_clk", 2, 4, 0),
+ MSTPCR("ceu0", "bus_clk", 2, 3, 0),
+ MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
+ MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
+ MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
};
void __init
arch_init_clk_ops(struct clk_ops **ops, int type)
{
- BUG_ON(type < 0 || type > ARRAY_SIZE(onchip_ops));
+ BUG_ON(type < 0 || type >= ARRAY_SIZE(onchip_ops));
*ops = onchip_ops[type];
}
struct clk *clk;
int i;
+ cpg_clk_init();
+
clk = clk_get(NULL, "master_clk");
for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) {
pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name);
clk_put(clk);
}
- clk_recalc_rate(&sh7722_r_clock); /* make sure rate gets propagated */
+ propagate_rate(&sh7722_r_clock); /* make sure rate gets propagated */
return 0;
}
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07);
- clk->rate = clk->parent->rate / p0fc_divisors[idx];
+ return clk->parent->rate / p0fc_divisors[idx];
}
static struct clk_ops sh7763_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07);
- clk->rate = clk->parent->rate / bfc_divisors[idx];
+ return clk->parent->rate / bfc_divisors[idx];
}
static struct clk_ops sh7763_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
-{
- clk->rate = clk->parent->rate;
-}
-
static struct clk_ops sh7763_cpu_clk_ops = {
- .recalc = cpu_clk_recalc,
+ .recalc = followparent_recalc,
};
static struct clk_ops *sh7763_clk_ops[] = {
*ops = sh7763_clk_ops[idx];
}
-static void shyway_clk_recalc(struct clk *clk)
+static unsigned long shyway_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07);
- clk->rate = clk->parent->rate / cfc_divisors[idx];
+ return clk->parent->rate / cfc_divisors[idx];
}
static struct clk_ops sh7763_shyway_clk_ops = {
static struct clk sh7763_shyway_clk = {
.name = "shyway_clk",
- .flags = CLK_ALWAYS_ENABLED,
+ .flags = CLK_ENABLE_ON_INIT,
.ops = &sh7763_shyway_clk_ops,
};
&sh7763_shyway_clk,
};
-static int __init sh7763_clk_init(void)
+int __init arch_clk_init(void)
{
- struct clk *clk = clk_get(NULL, "master_clk");
- int i;
+ struct clk *clk;
+ int i, ret = 0;
+
+ cpg_clk_init();
+ clk = clk_get(NULL, "master_clk");
for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) {
struct clk *clkp = sh7763_onchip_clocks[i];
clkp->parent = clk;
- clk_register(clkp);
- clk_enable(clkp);
+ ret |= clk_register(clkp);
}
- /*
- * Now that we have the rest of the clocks registered, we need to
- * force the parent clock to propagate so that these clocks will
- * automatically figure out their rate. We cheat by handing the
- * parent clock its current rate and forcing child propagation.
- */
- clk_set_rate(clk, clk_get_rate(clk));
-
clk_put(clk);
- return 0;
+ return ret;
}
-
-arch_initcall(sh7763_clk_init);
-
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7770_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inl(FRQCR) & 0x000f);
- clk->rate = clk->parent->rate / bfc_divisors[idx];
+ return clk->parent->rate / bfc_divisors[idx];
}
static struct clk_ops sh7770_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f);
- clk->rate = clk->parent->rate / ifc_divisors[idx];
+ return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7770_cpu_clk_ops = {
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inl(FRQCR) & 0x0003);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7780_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007);
- clk->rate = clk->parent->rate / bfc_divisors[idx];
+ return clk->parent->rate / bfc_divisors[idx];
}
static struct clk_ops sh7780_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001);
- clk->rate = clk->parent->rate / ifc_divisors[idx];
+ return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7780_cpu_clk_ops = {
*ops = sh7780_clk_ops[idx];
}
-static void shyway_clk_recalc(struct clk *clk)
+static unsigned long shyway_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007);
- clk->rate = clk->parent->rate / cfc_divisors[idx];
+ return clk->parent->rate / cfc_divisors[idx];
}
static struct clk_ops sh7780_shyway_clk_ops = {
static struct clk sh7780_shyway_clk = {
.name = "shyway_clk",
- .flags = CLK_ALWAYS_ENABLED,
+ .flags = CLK_ENABLE_ON_INIT,
.ops = &sh7780_shyway_clk_ops,
};
&sh7780_shyway_clk,
};
-static int __init sh7780_clk_init(void)
+int __init arch_clk_init(void)
{
- struct clk *clk = clk_get(NULL, "master_clk");
- int i;
+ struct clk *clk;
+ int i, ret = 0;
+ cpg_clk_init();
+
+ clk = clk_get(NULL, "master_clk");
for (i = 0; i < ARRAY_SIZE(sh7780_onchip_clocks); i++) {
struct clk *clkp = sh7780_onchip_clocks[i];
clkp->parent = clk;
- clk_register(clkp);
- clk_enable(clkp);
+ ret |= clk_register(clkp);
}
- /*
- * Now that we have the rest of the clocks registered, we need to
- * force the parent clock to propagate so that these clocks will
- * automatically figure out their rate. We cheat by handing the
- * parent clock its current rate and forcing child propagation.
- */
- clk_set_rate(clk, clk_get_rate(clk));
-
clk_put(clk);
- return 0;
+ return ret;
}
-
-arch_initcall(sh7780_clk_init);
-
*
* SH7785 support for the clock framework
*
- * Copyright (C) 2007 Paul Mundt
+ * Copyright (C) 2007 - 2009 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
*/
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/cpufreq.h>
#include <asm/clock.h>
#include <asm/freq.h>
-#include <asm/io.h>
-
-static int ifc_divisors[] = { 1, 2, 4, 6 };
-static int ufc_divisors[] = { 1, 1, 4, 6 };
-static int sfc_divisors[] = { 1, 1, 4, 6 };
-static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18,
- 24, 32, 36, 48, 1, 1, 1, 1 };
-static int mfc_divisors[] = { 1, 1, 4, 6 };
-static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18,
- 24, 32, 36, 48, 1, 1, 1, 1 };
-
-static void master_clk_init(struct clk *clk)
-{
- clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
-}
-static struct clk_ops sh7785_master_clk_ops = {
- .init = master_clk_init,
+static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
+ 24, 32, 36, 48 };
+
+static struct clk_div_mult_table cpg_div = {
+ .divisors = div2,
+ .nr_divisors = ARRAY_SIZE(div2),
};
-static void module_clk_recalc(struct clk *clk)
-{
- int idx = (ctrl_inl(FRQMR1) & 0x000f);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
-}
+struct clk_priv {
+ unsigned int shift;
+
+ /* allowable divisor bitmap */
+ unsigned long div_bitmap;
-static struct clk_ops sh7785_module_clk_ops = {
- .recalc = module_clk_recalc,
+ /* Supportable frequencies + termination entry */
+ struct cpufreq_frequency_table freq_table[ARRAY_SIZE(div2)+1];
};
-static void bus_clk_recalc(struct clk *clk)
-{
- int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
- clk->rate = clk->parent->rate / bfc_divisors[idx];
+#define FRQMR_CLK_DATA(_name, _shift, _div_bitmap) \
+static struct clk_priv _name##_data = { \
+ .shift = _shift, \
+ .div_bitmap = _div_bitmap, \
+ \
+ .freq_table[0] = { \
+ .index = 0, \
+ .frequency = CPUFREQ_TABLE_END, \
+ }, \
}
-static struct clk_ops sh7785_bus_clk_ops = {
- .recalc = bus_clk_recalc,
-};
+FRQMR_CLK_DATA(pfc, 0, 0x0f80);
+FRQMR_CLK_DATA(s3fc, 4, 0x0ff0);
+FRQMR_CLK_DATA(s2fc, 8, 0x0030);
+FRQMR_CLK_DATA(mfc, 12, 0x000c);
+FRQMR_CLK_DATA(bfc, 16, 0x0fe0);
+FRQMR_CLK_DATA(sfc, 20, 0x000c);
+FRQMR_CLK_DATA(ufc, 24, 0x000c);
+FRQMR_CLK_DATA(ifc, 28, 0x000e);
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long frqmr_recalc(struct clk *clk)
{
- int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
- clk->rate = clk->parent->rate / ifc_divisors[idx];
+ struct clk_priv *data = clk->priv;
+ unsigned int idx = (__raw_readl(FRQMR1) >> data->shift) & 0x000f;
+
+ clk_rate_table_build(clk, data->freq_table, ARRAY_SIZE(div2),
+ &cpg_div, &data->div_bitmap);
+
+ return data->freq_table[idx].frequency;
}
-static struct clk_ops sh7785_cpu_clk_ops = {
- .recalc = cpu_clk_recalc,
-};
+static long frqmr_round_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk_priv *data = clk->priv;
+
+ return clk_rate_table_round(clk, data->freq_table, rate);
+}
-static struct clk_ops *sh7785_clk_ops[] = {
- &sh7785_master_clk_ops,
- &sh7785_module_clk_ops,
- &sh7785_bus_clk_ops,
- &sh7785_cpu_clk_ops,
+static struct clk_ops frqmr_clk_ops = {
+ .recalc = frqmr_recalc,
+ .round_rate = frqmr_round_rate,
};
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+static unsigned long pll_recalc(struct clk *clk)
{
- if (idx < ARRAY_SIZE(sh7785_clk_ops))
- *ops = sh7785_clk_ops[idx];
+ /*
+ * XXX: PLL1 multiplier is locked for the default clock mode,
+ * when mode pin detection and configuration support is added,
+ * select the multiplier dynamically.
+ */
+ return clk->parent->rate * 36;
}
-static void shyway_clk_recalc(struct clk *clk)
-{
- int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
- clk->rate = clk->parent->rate / sfc_divisors[idx];
-}
+static struct clk_ops pll_clk_ops = {
+ .recalc = pll_recalc,
+};
-static struct clk_ops sh7785_shyway_clk_ops = {
- .recalc = shyway_clk_recalc,
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk extal_clk = {
+ .name = "extal",
+ .id = -1,
+ .rate = 33333333,
};
-static struct clk sh7785_shyway_clk = {
- .name = "shyway_clk",
- .flags = CLK_ALWAYS_ENABLED,
- .ops = &sh7785_shyway_clk_ops,
+static struct clk pll_clk = {
+ .name = "pll_clk",
+ .id = -1,
+ .ops = &pll_clk_ops,
+ .parent = &extal_clk,
+ .flags = CLK_ENABLE_ON_INIT,
};
-static void ddr_clk_recalc(struct clk *clk)
-{
- int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
- clk->rate = clk->parent->rate / mfc_divisors[idx];
-}
+static struct clk cpu_clk = {
+ .name = "cpu_clk", /* Ick */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &pll_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+ .priv = &ifc_data,
+};
-static struct clk_ops sh7785_ddr_clk_ops = {
- .recalc = ddr_clk_recalc,
+static struct clk shyway_clk = {
+ .name = "shyway_clk", /* SHck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &pll_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+ .priv = &sfc_data,
};
-static struct clk sh7785_ddr_clk = {
- .name = "ddr_clk",
- .flags = CLK_ALWAYS_ENABLED,
- .ops = &sh7785_ddr_clk_ops,
+static struct clk peripheral_clk = {
+ .name = "peripheral_clk", /* Pck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &pll_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+ .priv = &pfc_data,
};
-static void ram_clk_recalc(struct clk *clk)
-{
- int idx = ((ctrl_inl(FRQMR1) >> 24) & 0x0003);
- clk->rate = clk->parent->rate / ufc_divisors[idx];
-}
+static struct clk ddr_clk = {
+ .name = "ddr_clk", /* DDRck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &pll_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+ .priv = &mfc_data,
+};
-static struct clk_ops sh7785_ram_clk_ops = {
- .recalc = ram_clk_recalc,
+static struct clk bus_clk = {
+ .name = "bus_clk", /* Bck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &pll_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+ .priv = &bfc_data,
};
-static struct clk sh7785_ram_clk = {
- .name = "ram_clk",
- .flags = CLK_ALWAYS_ENABLED,
- .ops = &sh7785_ram_clk_ops,
+static struct clk ga_clk = {
+ .name = "ga_clk", /* GAck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &pll_clk,
+ .priv = &s2fc_data,
};
-/*
- * Additional SH7785-specific on-chip clocks that aren't already part of the
- * clock framework
- */
-static struct clk *sh7785_onchip_clocks[] = {
- &sh7785_shyway_clk,
- &sh7785_ddr_clk,
- &sh7785_ram_clk,
+static struct clk du_clk = {
+ .name = "du_clk", /* DUck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &pll_clk,
+ .priv = &s3fc_data,
+};
+
+static struct clk umem_clk = {
+ .name = "umem_clk", /* uck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &pll_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+ .priv = &ufc_data,
};
-static int __init sh7785_clk_init(void)
+static struct clk *clks[] = {
+ &extal_clk,
+ &pll_clk,
+ &cpu_clk,
+ ­way_clk,
+ &peripheral_clk,
+ &ddr_clk,
+ &bus_clk,
+ &ga_clk,
+ &du_clk,
+ &umem_clk,
+};
+
+static int mstpcr_clk_enable(struct clk *clk)
{
- struct clk *clk = clk_get(NULL, "master_clk");
- int i;
+ __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
+ clk->enable_reg);
+ return 0;
+}
- for (i = 0; i < ARRAY_SIZE(sh7785_onchip_clocks); i++) {
- struct clk *clkp = sh7785_onchip_clocks[i];
+static void mstpcr_clk_disable(struct clk *clk)
+{
+ __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
+ clk->enable_reg);
+}
- clkp->parent = clk;
- clk_register(clkp);
- clk_enable(clkp);
- }
+static struct clk_ops mstpcr_clk_ops = {
+ .enable = mstpcr_clk_enable,
+ .disable = mstpcr_clk_disable,
+ .recalc = followparent_recalc,
+};
- /*
- * Now that we have the rest of the clocks registered, we need to
- * force the parent clock to propagate so that these clocks will
- * automatically figure out their rate. We cheat by handing the
- * parent clock its current rate and forcing child propagation.
- */
- clk_set_rate(clk, clk_get_rate(clk));
+#define MSTPCR0 0xffc80030
+#define MSTPCR1 0xffc80034
- clk_put(clk);
+#define CLK(_name, _id, _parent, _enable_reg, \
+ _enable_bit, _flags) \
+{ \
+ .name = _name, \
+ .id = _id, \
+ .parent = _parent, \
+ .enable_reg = (void __iomem *)_enable_reg, \
+ .enable_bit = _enable_bit, \
+ .flags = _flags, \
+ .ops = &mstpcr_clk_ops, \
+}
- return 0;
+static struct clk mstpcr_clks[] = {
+ /* MSTPCR0 */
+ CLK("scif_fck", 5, &peripheral_clk, MSTPCR0, 29, 0),
+ CLK("scif_fck", 4, &peripheral_clk, MSTPCR0, 28, 0),
+ CLK("scif_fck", 3, &peripheral_clk, MSTPCR0, 27, 0),
+ CLK("scif_fck", 2, &peripheral_clk, MSTPCR0, 26, 0),
+ CLK("scif_fck", 1, &peripheral_clk, MSTPCR0, 25, 0),
+ CLK("scif_fck", 0, &peripheral_clk, MSTPCR0, 24, 0),
+ CLK("ssi_fck", 1, &peripheral_clk, MSTPCR0, 21, 0),
+ CLK("ssi_fck", 0, &peripheral_clk, MSTPCR0, 20, 0),
+ CLK("hac_fck", 1, &peripheral_clk, MSTPCR0, 17, 0),
+ CLK("hac_fck", 0, &peripheral_clk, MSTPCR0, 16, 0),
+ CLK("mmcif_fck", -1, &peripheral_clk, MSTPCR0, 13, 0),
+ CLK("flctl_fck", -1, &peripheral_clk, MSTPCR0, 12, 0),
+ CLK("tmu345_fck", -1, &peripheral_clk, MSTPCR0, 9, 0),
+ CLK("tmu012_fck", -1, &peripheral_clk, MSTPCR0, 8, 0),
+ CLK("siof_fck", -1, &peripheral_clk, MSTPCR0, 3, 0),
+ CLK("hspi_fck", -1, &peripheral_clk, MSTPCR0, 2, 0),
+
+ /* MSTPCR1 */
+ CLK("hudi_fck", -1, NULL, MSTPCR1, 19, 0),
+ CLK("ubc_fck", -1, NULL, MSTPCR1, 17, 0),
+ CLK("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
+ CLK("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
+ CLK("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
+};
+
+int __init arch_clk_init(void)
+{
+ int i, ret = 0;
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++)
+ ret |= clk_register(clks[i]);
+ for (i = 0; i < ARRAY_SIZE(mstpcr_clks); i++)
+ ret |= clk_register(&mstpcr_clks[i]);
+
+ return ret;
}
-arch_initcall(sh7785_clk_init);
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inl(FRQMR1) & 0x000f);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7786_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
- clk->rate = clk->parent->rate / bfc_divisors[idx];
+ return clk->parent->rate / bfc_divisors[idx];
}
static struct clk_ops sh7786_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
- clk->rate = clk->parent->rate / ifc_divisors[idx];
+ return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7786_cpu_clk_ops = {
*ops = sh7786_clk_ops[idx];
}
-static void shyway_clk_recalc(struct clk *clk)
+static unsigned long shyway_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
- clk->rate = clk->parent->rate / sfc_divisors[idx];
+ return clk->parent->rate / sfc_divisors[idx];
}
static struct clk_ops sh7786_shyway_clk_ops = {
static struct clk sh7786_shyway_clk = {
.name = "shyway_clk",
- .flags = CLK_ALWAYS_ENABLED,
+ .flags = CLK_ENABLE_ON_INIT,
.ops = &sh7786_shyway_clk_ops,
};
-static void ddr_clk_recalc(struct clk *clk)
+static unsigned long ddr_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
- clk->rate = clk->parent->rate / mfc_divisors[idx];
+ return clk->parent->rate / mfc_divisors[idx];
}
static struct clk_ops sh7786_ddr_clk_ops = {
static struct clk sh7786_ddr_clk = {
.name = "ddr_clk",
- .flags = CLK_ALWAYS_ENABLED,
+ .flags = CLK_ENABLE_ON_INIT,
.ops = &sh7786_ddr_clk_ops,
};
&sh7786_ddr_clk,
};
-static int __init sh7786_clk_init(void)
+int __init arch_clk_init(void)
{
- struct clk *clk = clk_get(NULL, "master_clk");
- int i;
+ struct clk *clk;
+ int i, ret = 0;
+ cpg_clk_init();
+
+ clk = clk_get(NULL, "master_clk");
for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
struct clk *clkp = sh7786_onchip_clocks[i];
clkp->parent = clk;
- clk_register(clkp);
- clk_enable(clkp);
+ ret |= clk_register(clkp);
}
- /*
- * Now that we have the rest of the clocks registered, we need to
- * force the parent clock to propagate so that these clocks will
- * automatically figure out their rate. We cheat by handing the
- * parent clock its current rate and forcing child propagation.
- */
- clk_set_rate(clk, clk_get_rate(clk));
-
clk_put(clk);
- return 0;
+ return ret;
}
-arch_initcall(sh7786_clk_init);
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
+ return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops shx3_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK);
- clk->rate = clk->parent->rate / bfc_divisors[idx];
+ return clk->parent->rate / bfc_divisors[idx];
}
static struct clk_ops shx3_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK);
- clk->rate = clk->parent->rate / ifc_divisors[idx];
+ return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops shx3_cpu_clk_ops = {
*ops = shx3_clk_ops[idx];
}
-static void shyway_clk_recalc(struct clk *clk)
+static unsigned long shyway_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK);
- clk->rate = clk->parent->rate / cfc_divisors[idx];
+ return clk->parent->rate / cfc_divisors[idx];
}
static struct clk_ops shx3_shyway_clk_ops = {
static struct clk shx3_shyway_clk = {
.name = "shyway_clk",
- .flags = CLK_ALWAYS_ENABLED,
+ .flags = CLK_ENABLE_ON_INIT,
.ops = &shx3_shyway_clk_ops,
};
&shx3_shyway_clk,
};
-static int __init shx3_clk_init(void)
+int __init arch_clk_init(void)
{
- struct clk *clk = clk_get(NULL, "master_clk");
- int i;
+ struct clk *clk;
+ int i, ret = 0;
+ cpg_clk_init();
+
+ clk = clk_get(NULL, "master_clk");
for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {
struct clk *clkp = shx3_onchip_clocks[i];
clkp->parent = clk;
- clk_register(clkp);
- clk_enable(clkp);
+ ret |= clk_register(clkp);
}
- /*
- * Now that we have the rest of the clocks registered, we need to
- * force the parent clock to propagate so that these clocks will
- * automatically figure out their rate. We cheat by handing the
- * parent clock its current rate and forcing child propagation.
- */
- clk_set_rate(clk, clk_get_rate(clk));
-
clk_put(clk);
- return 0;
+ return ret;
}
-arch_initcall(shx3_clk_init);
static int __init sh7343_devices_setup(void)
{
- clk_always_enable("uram0"); /* URAM */
- clk_always_enable("xymem0"); /* XYMEM */
- clk_always_enable("veu0"); /* VEU */
- clk_always_enable("vpu0"); /* VPU */
- clk_always_enable("jpu0"); /* JPU */
-
platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
static int __init sh7366_devices_setup(void)
{
- clk_always_enable("rsmem0"); /* RSMEM */
- clk_always_enable("xymem0"); /* XYMEM */
- clk_always_enable("veu1"); /* VEU-2 */
- clk_always_enable("veu0"); /* VEU-1 */
- clk_always_enable("vpu0"); /* VPU */
-
platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
static int __init sh7722_devices_setup(void)
{
- clk_always_enable("uram0"); /* URAM */
- clk_always_enable("xymem0"); /* XYMEM */
- clk_always_enable("veu0"); /* VEU */
- clk_always_enable("vpu0"); /* VPU */
- clk_always_enable("jpu0"); /* JPU */
-
platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
static int __init sh7723_devices_setup(void)
{
- clk_always_enable("meram0"); /* MERAM */
- clk_always_enable("veu1"); /* VEU2H1 */
- clk_always_enable("veu0"); /* VEU2H0 */
- clk_always_enable("vpu0"); /* VPU */
-
platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
static int __init sh7724_devices_setup(void)
{
- clk_always_enable("vpu0"); /* VPU */
- clk_always_enable("veu1"); /* VEU3F1 */
- clk_always_enable("veu0"); /* VEU3F0 */
-
platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
.name = "TMU6",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu6_resources[] = {
.name = "TMU7",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu7_resources[] = {
.name = "TMU8",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu8_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "tmu012_fck",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "tmu012_fck",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "tmu012_fck",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "tmu345_fck",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "tmu345_fck",
};
static struct resource tmu4_resources[] = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "tmu345_fck",
};
static struct resource tmu5_resources[] = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 40, 40, 40, 40 },
+ .clk = "scif_fck",
}, {
.mapbase = 0xffeb0000,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 44, 44, 44, 44 },
+ .clk = "scif_fck",
}, {
.mapbase = 0xffec0000,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 60, 60, 60, 60 },
+ .clk = "scif_fck",
}, {
.mapbase = 0xffed0000,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 61, 61, 61, 61 },
+ .clk = "scif_fck",
}, {
.mapbase = 0xffee0000,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 62, 62, 62, 62 },
+ .clk = "scif_fck",
}, {
.mapbase = 0xffef0000,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 63, 63, 63, 63 },
+ .clk = "scif_fck",
}, {
.flags = 0,
}
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
.name = "TMU6",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu6_resources[] = {
.name = "TMU7",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu7_resources[] = {
.name = "TMU8",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu8_resources[] = {
.name = "TMU9",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu9_resources[] = {
.name = "TMU10",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu10_resources[] = {
.name = "TMU11",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu11_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
.init = master_clk_init,
};
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007;
- clk->rate = clk->parent->rate / ifc_table[idx];
+ return clk->parent->rate / ifc_table[idx];
}
static struct clk_ops sh5_module_clk_ops = {
.recalc = module_clk_recalc,
};
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007;
- clk->rate = clk->parent->rate / ifc_table[idx];
+ return clk->parent->rate / ifc_table[idx];
}
static struct clk_ops sh5_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(cprc_base) & 0x0007);
- clk->rate = clk->parent->rate / ifc_table[idx];
+ return clk->parent->rate / ifc_table[idx];
}
static struct clk_ops sh5_cpu_clk_ops = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
signed char cdf, cdfm;
int scgd, scgdm, scgds;
- mclk = clk_get(NULL, "module_clk");
+ mclk = clk_get(NULL, "peripheral_clk");
if (IS_ERR(mclk)) {
return PTR_ERR(mclk);
} else {
sci_port->port.uartclk = CONFIG_CPU_CLOCK;
#elif defined(CONFIG_HAVE_CLK)
sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL;
- sci_port->dclk = clk_get(&dev->dev, "module_clk");
+ sci_port->dclk = clk_get(&dev->dev, "peripheral_clk");
sci_port->enable = sci_clk_enable;
sci_port->disable = sci_clk_disable;
#else
projects / cascardo / linux.git / commitdiff