ARM: shmobile: r8a7740: add MSTP clock assignments to DT
authorUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Fri, 8 Aug 2014 14:23:11 +0000 (16:23 +0200)
committerSimon Horman <horms+renesas@verge.net.au>
Sat, 23 Aug 2014 10:56:26 +0000 (19:56 +0900)
Assigns clocks to ether, i2c*, scif*, tpu, mmcif0, sdhi*, and fsi2.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7740.dtsi

index 3c61c5d..6cd6a46 100644 (file)
                reg = <0xe9a00000 0x800>,
                      <0xe9a01800 0x800>;
                interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
-               /* clocks = <&mstp3_clks R8A7740_CLK_GETHER>; */
+               clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
                phy-mode = "mii";
                #address-cells = <1>;
                #size-cells = <0>;
                              0 202 IRQ_TYPE_LEVEL_HIGH
                              0 203 IRQ_TYPE_LEVEL_HIGH
                              0 204 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
                status = "disabled";
        };
 
                              0 71 IRQ_TYPE_LEVEL_HIGH
                              0 72 IRQ_TYPE_LEVEL_HIGH
                              0 73 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
                status = "disabled";
        };
 
                compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                reg = <0xe6c40000 0x100>;
                interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
+               clock-names = "sci_ick";
                status = "disabled";
        };
 
                compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                reg = <0xe6c50000 0x100>;
                interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
+               clock-names = "sci_ick";
                status = "disabled";
        };
 
                compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                reg = <0xe6c60000 0x100>;
                interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
+               clock-names = "sci_ick";
                status = "disabled";
        };
 
                compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                reg = <0xe6c70000 0x100>;
                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
+               clock-names = "sci_ick";
                status = "disabled";
        };
 
                compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                reg = <0xe6c80000 0x100>;
                interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
+               clock-names = "sci_ick";
                status = "disabled";
        };
 
                compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                reg = <0xe6cb0000 0x100>;
                interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
+               clock-names = "sci_ick";
                status = "disabled";
        };
 
                compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                reg = <0xe6cc0000 0x100>;
                interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
+               clock-names = "sci_ick";
                status = "disabled";
        };
 
                compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                reg = <0xe6cd0000 0x100>;
                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
+               clock-names = "sci_ick";
                status = "disabled";
        };
 
                compatible = "renesas,scifb-r8a7740", "renesas,scifb";
                reg = <0xe6c30000 0x100>;
                interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
+               clock-names = "sci_ick";
                status = "disabled";
        };
 
        tpu: pwm@e6600000 {
                compatible = "renesas,tpu-r8a7740", "renesas,tpu";
                reg = <0xe6600000 0x100>;
+               clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
                status = "disabled";
                #pwm-cells = <3>;
        };
                reg = <0xe6bd0000 0x100>;
                interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
                              0 57 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp3_clks R8A7740_CLK_MMC>;
                status = "disabled";
        };
 
                interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
                              0 118 IRQ_TYPE_LEVEL_HIGH
                              0 119 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
                cap-sd-highspeed;
                cap-sdio-irq;
                status = "disabled";
                interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
                              0 122 IRQ_TYPE_LEVEL_HIGH
                              0 123 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
                cap-sd-highspeed;
                cap-sdio-irq;
                status = "disabled";
                interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
                              0 126 IRQ_TYPE_LEVEL_HIGH
                              0 127 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
                cap-sd-highspeed;
                cap-sdio-irq;
                status = "disabled";
                compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
                reg = <0xfe1f0000 0x400>;
                interrupts = <0 9 0x4>;
+               clocks = <&mstp3_clks R8A7740_CLK_FSI>;
                status = "disabled";
        };