ARM: tegra: Use lower-case hexadecimal digits

For consistency with other device tree content, use lower-case
hexadecimal digits in register region specifications.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
index 23e1d31..41372d4 100644 (file)
--- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
+++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
@@ -29,7 +29,7 @@ Example:
 
        fuse@7000f800 {
                compatible = "nvidia,tegra20-efuse";
-               reg = <0x7000F800 0x400>,
+               reg = <0x7000f800 0x400>,
                      <0x70000000 0x400>;
                clocks = <&tegra_car TEGRA20_CLK_FUSE>;
                clock-names = "fuse";

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index cf01c81..0d9f9ae 100644 (file)
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -300,7 +300,7 @@
        apbmisc@0,70000800 {
                compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
                reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
-                     <0x0 0x7000E864 0x0 0x04>;   /* Strapping options */
+                     <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
        };
 
        pinmux: pinmux@0,70000868 {

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index adf6b04..f444b67 100644 (file)
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -563,7 +563,7 @@
 
        fuse@7000f800 {
                compatible = "nvidia,tegra20-efuse";
-               reg = <0x7000F800 0x400>;
+               reg = <0x7000f800 0x400>;
                clocks = <&tegra_car TEGRA20_CLK_FUSE>;
                clock-names = "fuse";
                resets = <&tegra_car 39>;