/ {
model = "MPC8540ADS";
- compatible = "MPC85xxADS";
+ compatible = "MPC8540ADS", "MPC85xxADS";
#address-cells = <1>;
#size-cells = <1>;
- linux,phandle = <100>;
cpus {
#cpus = <1>;
#address-cells = <1>;
#size-cells = <0>;
- linux,phandle = <200>;
PowerPC,8540@0 {
device_type = "cpu";
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
32-bit;
- linux,phandle = <201>;
};
};
memory {
device_type = "memory";
- linux,phandle = <300>;
reg = <00000000 08000000>; // 128M at 0x0
};
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <1b 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
dfsrr;
};
device_type = "mdio";
compatible = "gianfar";
reg = <24520 20>;
- linux,phandle = <24520>;
- ethernet-phy@0 {
- linux,phandle = <2452000>;
- interrupt-parent = <40000>;
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
interrupts = <35 1>;
reg = <0>;
device_type = "ethernet-phy";
};
- ethernet-phy@1 {
- linux,phandle = <2452001>;
- interrupt-parent = <40000>;
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
interrupts = <35 1>;
reg = <1>;
device_type = "ethernet-phy";
};
- ethernet-phy@3 {
- linux,phandle = <2452003>;
- interrupt-parent = <40000>;
+ phy3: ethernet-phy@3 {
+ interrupt-parent = <&mpic>;
interrupts = <37 1>;
reg = <3>;
device_type = "ethernet-phy";
address = [ 00 E0 0C 00 73 00 ];
local-mac-address = [ 00 E0 0C 00 73 00 ];
interrupts = <d 2 e 2 12 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452000>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy0>;
};
ethernet@25000 {
address = [ 00 E0 0C 00 73 01 ];
local-mac-address = [ 00 E0 0C 00 73 01 ];
interrupts = <13 2 14 2 18 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452001>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy1>;
};
ethernet@26000 {
address = [ 00 E0 0C 00 73 02 ];
local-mac-address = [ 00 E0 0C 00 73 02 ];
interrupts = <19 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452003>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy3>;
};
serial@4500 {
reg = <4500 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <1a 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
};
serial@4600 {
reg = <4600 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <1a 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
};
pci@8000 {
- linux,phandle = <8000>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x02 */
- 1000 0 0 1 40000 31 1
- 1000 0 0 2 40000 32 1
- 1000 0 0 3 40000 33 1
- 1000 0 0 4 40000 34 1
+ 1000 0 0 1 &mpic 31 1
+ 1000 0 0 2 &mpic 32 1
+ 1000 0 0 3 &mpic 33 1
+ 1000 0 0 4 &mpic 34 1
/* IDSEL 0x03 */
- 1800 0 0 1 40000 34 1
- 1800 0 0 2 40000 31 1
- 1800 0 0 3 40000 32 1
- 1800 0 0 4 40000 33 1
+ 1800 0 0 1 &mpic 34 1
+ 1800 0 0 2 &mpic 31 1
+ 1800 0 0 3 &mpic 32 1
+ 1800 0 0 4 &mpic 33 1
/* IDSEL 0x04 */
- 2000 0 0 1 40000 33 1
- 2000 0 0 2 40000 34 1
- 2000 0 0 3 40000 31 1
- 2000 0 0 4 40000 32 1
+ 2000 0 0 1 &mpic 33 1
+ 2000 0 0 2 &mpic 34 1
+ 2000 0 0 3 &mpic 31 1
+ 2000 0 0 4 &mpic 32 1
/* IDSEL 0x05 */
- 2800 0 0 1 40000 32 1
- 2800 0 0 2 40000 33 1
- 2800 0 0 3 40000 34 1
- 2800 0 0 4 40000 31 1
+ 2800 0 0 1 &mpic 32 1
+ 2800 0 0 2 &mpic 33 1
+ 2800 0 0 3 &mpic 34 1
+ 2800 0 0 4 &mpic 31 1
/* IDSEL 0x0c */
- 6000 0 0 1 40000 31 1
- 6000 0 0 2 40000 32 1
- 6000 0 0 3 40000 33 1
- 6000 0 0 4 40000 34 1
+ 6000 0 0 1 &mpic 31 1
+ 6000 0 0 2 &mpic 32 1
+ 6000 0 0 3 &mpic 33 1
+ 6000 0 0 4 &mpic 34 1
/* IDSEL 0x0d */
- 6800 0 0 1 40000 34 1
- 6800 0 0 2 40000 31 1
- 6800 0 0 3 40000 32 1
- 6800 0 0 4 40000 33 1
+ 6800 0 0 1 &mpic 34 1
+ 6800 0 0 2 &mpic 31 1
+ 6800 0 0 3 &mpic 32 1
+ 6800 0 0 4 &mpic 33 1
/* IDSEL 0x0e */
- 7000 0 0 1 40000 33 1
- 7000 0 0 2 40000 34 1
- 7000 0 0 3 40000 31 1
- 7000 0 0 4 40000 32 1
+ 7000 0 0 1 &mpic 33 1
+ 7000 0 0 2 &mpic 34 1
+ 7000 0 0 3 &mpic 31 1
+ 7000 0 0 4 &mpic 32 1
/* IDSEL 0x0f */
- 7800 0 0 1 40000 32 1
- 7800 0 0 2 40000 33 1
- 7800 0 0 3 40000 34 1
- 7800 0 0 4 40000 31 1
+ 7800 0 0 1 &mpic 32 1
+ 7800 0 0 2 &mpic 33 1
+ 7800 0 0 3 &mpic 34 1
+ 7800 0 0 4 &mpic 31 1
/* IDSEL 0x12 */
- 9000 0 0 1 40000 31 1
- 9000 0 0 2 40000 32 1
- 9000 0 0 3 40000 33 1
- 9000 0 0 4 40000 34 1
+ 9000 0 0 1 &mpic 31 1
+ 9000 0 0 2 &mpic 32 1
+ 9000 0 0 3 &mpic 33 1
+ 9000 0 0 4 &mpic 34 1
/* IDSEL 0x13 */
- 9800 0 0 1 40000 34 1
- 9800 0 0 2 40000 31 1
- 9800 0 0 3 40000 32 1
- 9800 0 0 4 40000 33 1
+ 9800 0 0 1 &mpic 34 1
+ 9800 0 0 2 &mpic 31 1
+ 9800 0 0 3 &mpic 32 1
+ 9800 0 0 4 &mpic 33 1
/* IDSEL 0x14 */
- a000 0 0 1 40000 33 1
- a000 0 0 2 40000 34 1
- a000 0 0 3 40000 31 1
- a000 0 0 4 40000 32 1
+ a000 0 0 1 &mpic 33 1
+ a000 0 0 2 &mpic 34 1
+ a000 0 0 3 &mpic 31 1
+ a000 0 0 4 &mpic 32 1
/* IDSEL 0x15 */
- a800 0 0 1 40000 32 1
- a800 0 0 2 40000 33 1
- a800 0 0 3 40000 34 1
- a800 0 0 4 40000 31 1>;
- interrupt-parent = <40000>;
+ a800 0 0 1 &mpic 32 1
+ a800 0 0 2 &mpic 33 1
+ a800 0 0 3 &mpic 34 1
+ a800 0 0 4 &mpic 31 1>;
+ interrupt-parent = <&mpic>;
interrupts = <08 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
device_type = "pci";
};
- pic@40000 {
- linux,phandle = <40000>;
+ mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
/ {
model = "MPC8541CDS";
- compatible = "MPC85xxCDS";
+ compatible = "MPC8541CDS", "MPC85xxCDS";
#address-cells = <1>;
#size-cells = <1>;
- linux,phandle = <100>;
cpus {
#cpus = <1>;
#address-cells = <1>;
#size-cells = <0>;
- linux,phandle = <200>;
PowerPC,8541@0 {
device_type = "cpu";
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
32-bit;
- linux,phandle = <201>;
};
};
memory {
device_type = "memory";
- linux,phandle = <300>;
reg = <00000000 08000000>; // 128M at 0x0
};
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <1b 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
dfsrr;
};
device_type = "mdio";
compatible = "gianfar";
reg = <24520 20>;
- linux,phandle = <24520>;
- ethernet-phy@0 {
- linux,phandle = <2452000>;
- interrupt-parent = <40000>;
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
interrupts = <35 0>;
reg = <0>;
device_type = "ethernet-phy";
};
- ethernet-phy@1 {
- linux,phandle = <2452001>;
- interrupt-parent = <40000>;
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
interrupts = <35 0>;
reg = <1>;
device_type = "ethernet-phy";
reg = <24000 1000>;
local-mac-address = [ 00 E0 0C 00 73 00 ];
interrupts = <d 2 e 2 12 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452000>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy0>;
};
ethernet@25000 {
reg = <25000 1000>;
local-mac-address = [ 00 E0 0C 00 73 01 ];
interrupts = <13 2 14 2 18 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452001>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy1>;
};
serial@4500 {
reg = <4500 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <1a 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
};
serial@4600 {
reg = <4600 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <1a 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
};
- pci@8000 {
- linux,phandle = <8000>;
+ pci1: pci@8000 {
interrupt-map-mask = <1f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 */
- 08000 0 0 1 40000 30 1
- 08000 0 0 2 40000 31 1
- 08000 0 0 3 40000 32 1
- 08000 0 0 4 40000 33 1
+ 08000 0 0 1 &mpic 30 1
+ 08000 0 0 2 &mpic 31 1
+ 08000 0 0 3 &mpic 32 1
+ 08000 0 0 4 &mpic 33 1
/* IDSEL 0x11 */
- 08800 0 0 1 40000 30 1
- 08800 0 0 2 40000 31 1
- 08800 0 0 3 40000 32 1
- 08800 0 0 4 40000 33 1
+ 08800 0 0 1 &mpic 30 1
+ 08800 0 0 2 &mpic 31 1
+ 08800 0 0 3 &mpic 32 1
+ 08800 0 0 4 &mpic 33 1
/* IDSEL 0x12 (Slot 1) */
- 09000 0 0 1 40000 30 1
- 09000 0 0 2 40000 31 1
- 09000 0 0 3 40000 32 1
- 09000 0 0 4 40000 33 1
+ 09000 0 0 1 &mpic 30 1
+ 09000 0 0 2 &mpic 31 1
+ 09000 0 0 3 &mpic 32 1
+ 09000 0 0 4 &mpic 33 1
/* IDSEL 0x13 (Slot 2) */
- 09800 0 0 1 40000 31 1
- 09800 0 0 2 40000 32 1
- 09800 0 0 3 40000 33 1
- 09800 0 0 4 40000 30 1
+ 09800 0 0 1 &mpic 31 1
+ 09800 0 0 2 &mpic 32 1
+ 09800 0 0 3 &mpic 33 1
+ 09800 0 0 4 &mpic 30 1
/* IDSEL 0x14 (Slot 3) */
- 0a000 0 0 1 40000 32 1
- 0a000 0 0 2 40000 33 1
- 0a000 0 0 3 40000 30 1
- 0a000 0 0 4 40000 31 1
+ 0a000 0 0 1 &mpic 32 1
+ 0a000 0 0 2 &mpic 33 1
+ 0a000 0 0 3 &mpic 30 1
+ 0a000 0 0 4 &mpic 31 1
/* IDSEL 0x15 (Slot 4) */
- 0a800 0 0 1 40000 33 1
- 0a800 0 0 2 40000 30 1
- 0a800 0 0 3 40000 31 1
- 0a800 0 0 4 40000 32 1
+ 0a800 0 0 1 &mpic 33 1
+ 0a800 0 0 2 &mpic 30 1
+ 0a800 0 0 3 &mpic 31 1
+ 0a800 0 0 4 &mpic 32 1
/* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */
- 19000 0 0 1 40000 30 1
- 19000 0 0 2 40000 31 1
- 19000 0 0 3 40000 32 1
- 19000 0 0 4 40000 33 1>;
- interrupt-parent = <40000>;
+ 19000 0 0 1 &mpic 30 1
+ 19000 0 0 2 &mpic 31 1
+ 19000 0 0 3 &mpic 32 1
+ 19000 0 0 4 &mpic 33 1>;
+ interrupt-parent = <&mpic>;
interrupts = <08 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
compatible = "chrp,iic";
big-endian;
interrupts = <1>;
- interrupt-parent = <8000>;
+ interrupt-parent = <&pci1>;
};
};
pci@9000 {
- linux,phandle = <9000>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x15 */
- a800 0 0 1 40000 3b 1
- a800 0 0 2 40000 3b 1
- a800 0 0 3 40000 3b 1
- a800 0 0 4 40000 3b 1>;
- interrupt-parent = <40000>;
+ a800 0 0 1 &mpic 3b 1
+ a800 0 0 2 &mpic 3b 1
+ a800 0 0 3 &mpic 3b 1
+ a800 0 0 4 &mpic 3b 1>;
+ interrupt-parent = <&mpic>;
interrupts = <09 2>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
device_type = "pci";
};
- pic@40000 {
- linux,phandle = <40000>;
+ mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
/ {
model = "MPC8548CDS";
- compatible = "MPC85xxCDS";
+ compatible = "MPC8548CDS", "MPC85xxCDS";
#address-cells = <1>;
#size-cells = <1>;
- linux,phandle = <100>;
cpus {
#cpus = <1>;
#address-cells = <1>;
#size-cells = <0>;
- linux,phandle = <200>;
PowerPC,8548@0 {
device_type = "cpu";
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
32-bit;
- linux,phandle = <201>;
};
};
memory {
device_type = "memory";
- linux,phandle = <300>;
reg = <00000000 08000000>; // 128M at 0x0
};
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <1b 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
dfsrr;
};
device_type = "mdio";
compatible = "gianfar";
reg = <24520 20>;
- linux,phandle = <24520>;
- ethernet-phy@0 {
- linux,phandle = <2452000>;
- interrupt-parent = <40000>;
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
interrupts = <35 0>;
reg = <0>;
device_type = "ethernet-phy";
};
- ethernet-phy@1 {
- linux,phandle = <2452001>;
- interrupt-parent = <40000>;
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
interrupts = <35 0>;
reg = <1>;
device_type = "ethernet-phy";
};
-
- ethernet-phy@2 {
- linux,phandle = <2452002>;
- interrupt-parent = <40000>;
+ phy2: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
interrupts = <35 0>;
reg = <2>;
device_type = "ethernet-phy";
};
- ethernet-phy@3 {
- linux,phandle = <2452003>;
- interrupt-parent = <40000>;
+ phy3: ethernet-phy@3 {
+ interrupt-parent = <&mpic>;
interrupts = <35 0>;
reg = <3>;
device_type = "ethernet-phy";
reg = <24000 1000>;
local-mac-address = [ 00 E0 0C 00 73 00 ];
interrupts = <d 2 e 2 12 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452000>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy0>;
};
ethernet@25000 {
reg = <25000 1000>;
local-mac-address = [ 00 E0 0C 00 73 01 ];
interrupts = <13 2 14 2 18 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452001>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy1>;
};
+/* eTSEC 3/4 are currently broken
ethernet@26000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <26000 1000>;
local-mac-address = [ 00 E0 0C 00 73 02 ];
interrupts = <f 2 10 2 11 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452001>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy2>;
};
-/* eTSEC 4 is currently broken
ethernet@27000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <27000 1000>;
local-mac-address = [ 00 E0 0C 00 73 03 ];
interrupts = <15 2 16 2 17 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452001>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy3>;
};
*/
reg = <4500 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <1a 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
};
serial@4600 {
reg = <4600 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <1a 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
};
- pci@8000 {
- linux,phandle = <8000>;
+ pci1: pci@8000 {
interrupt-map-mask = <1f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 */
- 08000 0 0 1 40000 30 1
- 08000 0 0 2 40000 31 1
- 08000 0 0 3 40000 32 1
- 08000 0 0 4 40000 33 1
+ 08000 0 0 1 &mpic 30 1
+ 08000 0 0 2 &mpic 31 1
+ 08000 0 0 3 &mpic 32 1
+ 08000 0 0 4 &mpic 33 1
/* IDSEL 0x11 */
- 08800 0 0 1 40000 30 1
- 08800 0 0 2 40000 31 1
- 08800 0 0 3 40000 32 1
- 08800 0 0 4 40000 33 1
+ 08800 0 0 1 &mpic 30 1
+ 08800 0 0 2 &mpic 31 1
+ 08800 0 0 3 &mpic 32 1
+ 08800 0 0 4 &mpic 33 1
/* IDSEL 0x12 (Slot 1) */
- 09000 0 0 1 40000 30 1
- 09000 0 0 2 40000 31 1
- 09000 0 0 3 40000 32 1
- 09000 0 0 4 40000 33 1
+ 09000 0 0 1 &mpic 30 1
+ 09000 0 0 2 &mpic 31 1
+ 09000 0 0 3 &mpic 32 1
+ 09000 0 0 4 &mpic 33 1
/* IDSEL 0x13 (Slot 2) */
- 09800 0 0 1 40000 31 1
- 09800 0 0 2 40000 32 1
- 09800 0 0 3 40000 33 1
- 09800 0 0 4 40000 30 1
+ 09800 0 0 1 &mpic 31 1
+ 09800 0 0 2 &mpic 32 1
+ 09800 0 0 3 &mpic 33 1
+ 09800 0 0 4 &mpic 30 1
/* IDSEL 0x14 (Slot 3) */
- 0a000 0 0 1 40000 32 1
- 0a000 0 0 2 40000 33 1
- 0a000 0 0 3 40000 30 1
- 0a000 0 0 4 40000 31 1
+ 0a000 0 0 1 &mpic 32 1
+ 0a000 0 0 2 &mpic 33 1
+ 0a000 0 0 3 &mpic 30 1
+ 0a000 0 0 4 &mpic 31 1
/* IDSEL 0x15 (Slot 4) */
- 0a800 0 0 1 40000 33 1
- 0a800 0 0 2 40000 30 1
- 0a800 0 0 3 40000 31 1
- 0a800 0 0 4 40000 32 1
+ 0a800 0 0 1 &mpic 33 1
+ 0a800 0 0 2 &mpic 30 1
+ 0a800 0 0 3 &mpic 31 1
+ 0a800 0 0 4 &mpic 32 1
/* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */
- 19000 0 0 1 40000 30 1
- 19000 0 0 2 40000 31 1
- 19000 0 0 3 40000 32 1
- 19000 0 0 4 40000 33 1>;
- interrupt-parent = <40000>;
+ 19000 0 0 1 &mpic 30 1
+ 19000 0 0 2 &mpic 31 1
+ 19000 0 0 3 &mpic 32 1
+ 19000 0 0 4 &mpic 33 1>;
+ interrupt-parent = <&mpic>;
interrupts = <08 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
compatible = "chrp,iic";
big-endian;
interrupts = <1>;
- interrupt-parent = <8000>;
+ interrupt-parent = <&pci1>;
};
};
pci@9000 {
- linux,phandle = <9000>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x15 */
- a800 0 0 1 40000 3b 1
- a800 0 0 2 40000 3b 1
- a800 0 0 3 40000 3b 1
- a800 0 0 4 40000 3b 1>;
- interrupt-parent = <40000>;
+ a800 0 0 1 &mpic 3b 1
+ a800 0 0 2 &mpic 3b 1
+ a800 0 0 3 &mpic 3b 1
+ a800 0 0 4 &mpic 3b 1>;
+ interrupt-parent = <&mpic>;
interrupts = <09 2>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
device_type = "pci";
};
- pic@40000 {
- linux,phandle = <40000>;
+ mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
/ {
model = "MPC8555CDS";
- compatible = "MPC85xxCDS";
+ compatible = "MPC8555CDS", "MPC85xxCDS";
#address-cells = <1>;
#size-cells = <1>;
- linux,phandle = <100>;
cpus {
#cpus = <1>;
#address-cells = <1>;
#size-cells = <0>;
- linux,phandle = <200>;
PowerPC,8555@0 {
device_type = "cpu";
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
32-bit;
- linux,phandle = <201>;
};
};
memory {
device_type = "memory";
- linux,phandle = <300>;
reg = <00000000 08000000>; // 128M at 0x0
};
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <1b 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
dfsrr;
};
device_type = "mdio";
compatible = "gianfar";
reg = <24520 20>;
- linux,phandle = <24520>;
- ethernet-phy@0 {
- linux,phandle = <2452000>;
- interrupt-parent = <40000>;
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
interrupts = <35 0>;
reg = <0>;
device_type = "ethernet-phy";
};
- ethernet-phy@1 {
- linux,phandle = <2452001>;
- interrupt-parent = <40000>;
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
interrupts = <35 0>;
reg = <1>;
device_type = "ethernet-phy";
reg = <24000 1000>;
local-mac-address = [ 00 E0 0C 00 73 00 ];
interrupts = <0d 2 0e 2 12 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452000>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy0>;
};
ethernet@25000 {
reg = <25000 1000>;
local-mac-address = [ 00 E0 0C 00 73 01 ];
interrupts = <13 2 14 2 18 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452001>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy1>;
};
serial@4500 {
reg = <4500 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <1a 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
};
serial@4600 {
reg = <4600 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <1a 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
};
- pci@8000 {
- linux,phandle = <8000>;
+ pci1: pci@8000 {
interrupt-map-mask = <1f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 */
- 08000 0 0 1 40000 30 1
- 08000 0 0 2 40000 31 1
- 08000 0 0 3 40000 32 1
- 08000 0 0 4 40000 33 1
+ 08000 0 0 1 &mpic 30 1
+ 08000 0 0 2 &mpic 31 1
+ 08000 0 0 3 &mpic 32 1
+ 08000 0 0 4 &mpic 33 1
/* IDSEL 0x11 */
- 08800 0 0 1 40000 30 1
- 08800 0 0 2 40000 31 1
- 08800 0 0 3 40000 32 1
- 08800 0 0 4 40000 33 1
+ 08800 0 0 1 &mpic 30 1
+ 08800 0 0 2 &mpic 31 1
+ 08800 0 0 3 &mpic 32 1
+ 08800 0 0 4 &mpic 33 1
/* IDSEL 0x12 (Slot 1) */
- 09000 0 0 1 40000 30 1
- 09000 0 0 2 40000 31 1
- 09000 0 0 3 40000 32 1
- 09000 0 0 4 40000 33 1
+ 09000 0 0 1 &mpic 30 1
+ 09000 0 0 2 &mpic 31 1
+ 09000 0 0 3 &mpic 32 1
+ 09000 0 0 4 &mpic 33 1
/* IDSEL 0x13 (Slot 2) */
- 09800 0 0 1 40000 31 1
- 09800 0 0 2 40000 32 1
- 09800 0 0 3 40000 33 1
- 09800 0 0 4 40000 30 1
+ 09800 0 0 1 &mpic 31 1
+ 09800 0 0 2 &mpic 32 1
+ 09800 0 0 3 &mpic 33 1
+ 09800 0 0 4 &mpic 30 1
/* IDSEL 0x14 (Slot 3) */
- 0a000 0 0 1 40000 32 1
- 0a000 0 0 2 40000 33 1
- 0a000 0 0 3 40000 30 1
- 0a000 0 0 4 40000 31 1
+ 0a000 0 0 1 &mpic 32 1
+ 0a000 0 0 2 &mpic 33 1
+ 0a000 0 0 3 &mpic 30 1
+ 0a000 0 0 4 &mpic 31 1
/* IDSEL 0x15 (Slot 4) */
- 0a800 0 0 1 40000 33 1
- 0a800 0 0 2 40000 30 1
- 0a800 0 0 3 40000 31 1
- 0a800 0 0 4 40000 32 1
+ 0a800 0 0 1 &mpic 33 1
+ 0a800 0 0 2 &mpic 30 1
+ 0a800 0 0 3 &mpic 31 1
+ 0a800 0 0 4 &mpic 32 1
/* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */
- 19000 0 0 1 40000 30 1
- 19000 0 0 2 40000 31 1
- 19000 0 0 3 40000 32 1
- 19000 0 0 4 40000 33 1>;
- interrupt-parent = <40000>;
+ 19000 0 0 1 &mpic 30 1
+ 19000 0 0 2 &mpic 31 1
+ 19000 0 0 3 &mpic 32 1
+ 19000 0 0 4 &mpic 33 1>;
+ interrupt-parent = <&mpic>;
interrupts = <08 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
compatible = "chrp,iic";
big-endian;
interrupts = <1>;
- interrupt-parent = <8000>;
+ interrupt-parent = <&pci1>;
};
};
pci@9000 {
- linux,phandle = <9000>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x15 */
- a800 0 0 1 40000 3b 1
- a800 0 0 2 40000 3b 1
- a800 0 0 3 40000 3b 1
- a800 0 0 4 40000 3b 1>;
- interrupt-parent = <40000>;
+ a800 0 0 1 &mpic 3b 1
+ a800 0 0 2 &mpic 3b 1
+ a800 0 0 3 &mpic 3b 1
+ a800 0 0 4 &mpic 3b 1>;
+ interrupt-parent = <&mpic>;
interrupts = <09 2>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
device_type = "pci";
};
- pic@40000 {
- linux,phandle = <40000>;
+ mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
/ {
model = "MPC8560ADS";
- compatible = "MPC85xxADS";
+ compatible = "MPC8560ADS", "MPC85xxADS";
#address-cells = <1>;
#size-cells = <1>;
- linux,phandle = <100>;
cpus {
#cpus = <1>;
#address-cells = <1>;
#size-cells = <0>;
- linux,phandle = <200>;
PowerPC,8560@0 {
device_type = "cpu";
bus-frequency = <13ab6680>;
clock-frequency = <312c8040>;
32-bit;
- linux,phandle = <201>;
};
};
memory {
device_type = "memory";
- linux,phandle = <300>;
reg = <00000000 10000000>;
};
device_type = "mdio";
compatible = "gianfar";
reg = <24520 20>;
- linux,phandle = <24520>;
#address-cells = <1>;
#size-cells = <0>;
- ethernet-phy@0 {
- linux,phandle = <2452000>;
- interrupt-parent = <40000>;
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
interrupts = <35 1>;
reg = <0>;
device_type = "ethernet-phy";
};
- ethernet-phy@1 {
- linux,phandle = <2452001>;
- interrupt-parent = <40000>;
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
interrupts = <35 1>;
reg = <1>;
device_type = "ethernet-phy";
};
- ethernet-phy@2 {
- linux,phandle = <2452002>;
- interrupt-parent = <40000>;
+ phy2: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
interrupts = <37 1>;
reg = <2>;
device_type = "ethernet-phy";
};
- ethernet-phy@3 {
- linux,phandle = <2452003>;
- interrupt-parent = <40000>;
+ phy3: ethernet-phy@3 {
+ interrupt-parent = <&mpic>;
interrupts = <37 1>;
reg = <3>;
device_type = "ethernet-phy";
reg = <24000 1000>;
address = [ 00 00 0C 00 00 FD ];
interrupts = <d 2 e 2 12 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452000>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy0>;
};
ethernet@25000 {
reg = <25000 1000>;
address = [ 00 00 0C 00 01 FD ];
interrupts = <13 2 14 2 18 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452001>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy1>;
};
pci@8000 {
- linux,phandle = <8000>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
interrupt-map = <
/* IDSEL 0x2 */
- 1000 0 0 1 40000 31 1
- 1000 0 0 2 40000 32 1
- 1000 0 0 3 40000 33 1
- 1000 0 0 4 40000 34 1
+ 1000 0 0 1 &mpic 31 1
+ 1000 0 0 2 &mpic 32 1
+ 1000 0 0 3 &mpic 33 1
+ 1000 0 0 4 &mpic 34 1
/* IDSEL 0x3 */
- 1800 0 0 1 40000 34 1
- 1800 0 0 2 40000 31 1
- 1800 0 0 3 40000 32 1
- 1800 0 0 4 40000 33 1
+ 1800 0 0 1 &mpic 34 1
+ 1800 0 0 2 &mpic 31 1
+ 1800 0 0 3 &mpic 32 1
+ 1800 0 0 4 &mpic 33 1
/* IDSEL 0x4 */
- 2000 0 0 1 40000 33 1
- 2000 0 0 2 40000 34 1
- 2000 0 0 3 40000 31 1
- 2000 0 0 4 40000 32 1
+ 2000 0 0 1 &mpic 33 1
+ 2000 0 0 2 &mpic 34 1
+ 2000 0 0 3 &mpic 31 1
+ 2000 0 0 4 &mpic 32 1
/* IDSEL 0x5 */
- 2800 0 0 1 40000 32 1
- 2800 0 0 2 40000 33 1
- 2800 0 0 3 40000 34 1
- 2800 0 0 4 40000 31 1
+ 2800 0 0 1 &mpic 32 1
+ 2800 0 0 2 &mpic 33 1
+ 2800 0 0 3 &mpic 34 1
+ 2800 0 0 4 &mpic 31 1
/* IDSEL 12 */
- 6000 0 0 1 40000 31 1
- 6000 0 0 2 40000 32 1
- 6000 0 0 3 40000 33 1
- 6000 0 0 4 40000 34 1
+ 6000 0 0 1 &mpic 31 1
+ 6000 0 0 2 &mpic 32 1
+ 6000 0 0 3 &mpic 33 1
+ 6000 0 0 4 &mpic 34 1
/* IDSEL 13 */
- 6800 0 0 1 40000 34 1
- 6800 0 0 2 40000 31 1
- 6800 0 0 3 40000 32 1
- 6800 0 0 4 40000 33 1
+ 6800 0 0 1 &mpic 34 1
+ 6800 0 0 2 &mpic 31 1
+ 6800 0 0 3 &mpic 32 1
+ 6800 0 0 4 &mpic 33 1
/* IDSEL 14*/
- 7000 0 0 1 40000 33 1
- 7000 0 0 2 40000 34 1
- 7000 0 0 3 40000 31 1
- 7000 0 0 4 40000 32 1
+ 7000 0 0 1 &mpic 33 1
+ 7000 0 0 2 &mpic 34 1
+ 7000 0 0 3 &mpic 31 1
+ 7000 0 0 4 &mpic 32 1
/* IDSEL 15 */
- 7800 0 0 1 40000 32 1
- 7800 0 0 2 40000 33 1
- 7800 0 0 3 40000 34 1
- 7800 0 0 4 40000 31 1
+ 7800 0 0 1 &mpic 32 1
+ 7800 0 0 2 &mpic 33 1
+ 7800 0 0 3 &mpic 34 1
+ 7800 0 0 4 &mpic 31 1
/* IDSEL 18 */
- 9000 0 0 1 40000 31 1
- 9000 0 0 2 40000 32 1
- 9000 0 0 3 40000 33 1
- 9000 0 0 4 40000 34 1
+ 9000 0 0 1 &mpic 31 1
+ 9000 0 0 2 &mpic 32 1
+ 9000 0 0 3 &mpic 33 1
+ 9000 0 0 4 &mpic 34 1
/* IDSEL 19 */
- 9800 0 0 1 40000 34 1
- 9800 0 0 2 40000 31 1
- 9800 0 0 3 40000 32 1
- 9800 0 0 4 40000 33 1
+ 9800 0 0 1 &mpic 34 1
+ 9800 0 0 2 &mpic 31 1
+ 9800 0 0 3 &mpic 32 1
+ 9800 0 0 4 &mpic 33 1
/* IDSEL 20 */
- a000 0 0 1 40000 33 1
- a000 0 0 2 40000 34 1
- a000 0 0 3 40000 31 1
- a000 0 0 4 40000 32 1
+ a000 0 0 1 &mpic 33 1
+ a000 0 0 2 &mpic 34 1
+ a000 0 0 3 &mpic 31 1
+ a000 0 0 4 &mpic 32 1
/* IDSEL 21 */
- a800 0 0 1 40000 32 1
- a800 0 0 2 40000 33 1
- a800 0 0 3 40000 34 1
- a800 0 0 4 40000 31 1>;
+ a800 0 0 1 &mpic 32 1
+ a800 0 0 2 &mpic 33 1
+ a800 0 0 3 &mpic 34 1
+ a800 0 0 4 &mpic 31 1>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
interrupts = <8 0>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 01000000>;
};
- pic@40000 {
- linux,phandle = <40000>;
+ mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 20100>;
+ reg = <40000 40000>;
built-in;
device_type = "open-pic";
};
cpm@e0000000 {
- linux,phandle = <e0000000>;
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
command-proc = <919c0>;
brg-frequency = <9d5b340>;
- pic@90c00 {
- linux,phandle = <90c00>;
+ cpmpic: pic@90c00 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <1e 0>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
reg = <90c00 80>;
built-in;
device_type = "cpm-pic";
tx-clock = <1>;
current-speed = <1c200>;
interrupts = <28 8>;
- interrupt-parent = <90c00>;
+ interrupt-parent = <&cpmpic>;
};
scc@91a20 {
tx-clock = <2>;
current-speed = <1c200>;
interrupts = <29 8>;
- interrupt-parent = <90c00>;
+ interrupt-parent = <&cpmpic>;
};
fcc@91320 {
rx-clock = <15>;
tx-clock = <16>;
interrupts = <21 8>;
- interrupt-parent = <90c00>;
- phy-handle = <2452002>;
+ interrupt-parent = <&cpmpic>;
+ phy-handle = <&phy2>;
};
fcc@91340 {
rx-clock = <17>;
tx-clock = <18>;
interrupts = <22 8>;
- interrupt-parent = <90c00>;
- phy-handle = <2452003>;
+ interrupt-parent = <&cpmpic>;
+ phy-handle = <&phy3>;
};
};
};
/ {
model = "MPC8568EMDS";
- compatible = "MPC85xxMDS";
+ compatible = "MPC8568EMDS", "MPC85xxMDS";
#address-cells = <1>;
#size-cells = <1>;
- linux,phandle = <100>;
cpus {
#cpus = <1>;
#address-cells = <1>;
#size-cells = <0>;
- linux,phandle = <200>;
PowerPC,8568@0 {
device_type = "cpu";
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
- linux,phandle = <201>;
};
};
memory {
device_type = "memory";
- linux,phandle = <300>;
reg = <00000000 10000000>;
};
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <1b 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
dfsrr;
};
compatible = "fsl-i2c";
reg = <3100 100>;
interrupts = <1b 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
dfsrr;
};
device_type = "mdio";
compatible = "gianfar";
reg = <24520 20>;
- linux,phandle = <24520>;
- ethernet-phy@0 {
- linux,phandle = <2452000>;
- interrupt-parent = <40000>;
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
interrupts = <31 1>;
reg = <0>;
device_type = "ethernet-phy";
};
- ethernet-phy@1 {
- linux,phandle = <2452001>;
- interrupt-parent = <40000>;
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
interrupts = <32 1>;
reg = <1>;
device_type = "ethernet-phy";
};
-
- ethernet-phy@2 {
- linux,phandle = <2452002>;
- interrupt-parent = <40000>;
+ phy2: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
interrupts = <31 1>;
reg = <2>;
device_type = "ethernet-phy";
};
- ethernet-phy@3 {
- linux,phandle = <2452003>;
- interrupt-parent = <40000>;
+ phy3: ethernet-phy@3 {
+ interrupt-parent = <&mpic>;
interrupts = <32 1>;
reg = <3>;
device_type = "ethernet-phy";
reg = <24000 1000>;
mac-address = [ 00 00 00 00 00 00 ];
interrupts = <d 2 e 2 12 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452002>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy2>;
};
ethernet@25000 {
reg = <25000 1000>;
mac-address = [ 00 00 00 00 00 00];
interrupts = <13 2 14 2 18 2>;
- interrupt-parent = <40000>;
- phy-handle = <2452003>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy3>;
};
serial@4500 {
reg = <4500 100>;
clock-frequency = <0>;
interrupts = <1a 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
};
serial@4600 {
reg = <4600 100>;
clock-frequency = <0>;
interrupts = <1a 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
};
crypto@30000 {
compatible = "talitos";
reg = <30000 f000>;
interrupts = <1d 2>;
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
num-channels = <4>;
channel-fifo-len = <18>;
exec-units-mask = <000000fe>;
descriptor-types-mask = <012b0ebf>;
};
- pic@40000 {
- linux,phandle = <40000>;
+ mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
device_type = "par_io";
num-ports = <7>;
- ucc_pin@01 {
- linux,phandle = <e010001>;
+ pio1: ucc_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
4 0a 1 0 2 0 /* TxD0 */
4 13 1 0 2 0 /* GTX_CLK */
1 1f 2 0 3 0>; /* GTX125 */
};
- ucc_pin@02 {
- linux,phandle = <e010002>;
+ pio2: ucc_pin@02 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
5 0a 1 0 2 0 /* TxD0 */
compatible = "fsl_spi";
reg = <4c0 40>;
interrupts = <2>;
- interrupt-parent = <80>;
+ interrupt-parent = <&qeic>;
mode = "cpu";
};
compatible = "fsl_spi";
reg = <500 40>;
interrupts = <1>;
- interrupt-parent = <80>;
+ interrupt-parent = <&qeic>;
mode = "cpu";
};
device-id = <1>;
reg = <2000 200>;
interrupts = <20>;
- interrupt-parent = <80>;
+ interrupt-parent = <&qeic>;
mac-address = [ 00 04 9f 00 23 23 ];
rx-clock = <0>;
tx-clock = <19>;
- phy-handle = <212000>;
- pio-handle = <e010001>;
+ phy-handle = <&qe_phy0>;
+ pio-handle = <&pio1>;
};
ucc@3000 {
device-id = <2>;
reg = <3000 200>;
interrupts = <21>;
- interrupt-parent = <80>;
+ interrupt-parent = <&qeic>;
mac-address = [ 00 11 22 33 44 55 ];
rx-clock = <0>;
tx-clock = <14>;
- phy-handle = <212001>;
- pio-handle = <e010002>;
+ phy-handle = <&qe_phy1>;
+ pio-handle = <&pio2>;
};
mdio@2120 {
/* These are the same PHYs as on
* gianfar's MDIO bus */
- ethernet-phy@00 {
- linux,phandle = <212000>;
- interrupt-parent = <40000>;
+ qe_phy0: ethernet-phy@00 {
+ interrupt-parent = <&mpic>;
interrupts = <31 1>;
reg = <0>;
device_type = "ethernet-phy";
interface = <6>; //ENET_1000_GMII
};
- ethernet-phy@01 {
- linux,phandle = <212001>;
- interrupt-parent = <40000>;
+ qe_phy1: ethernet-phy@01 {
+ interrupt-parent = <&mpic>;
interrupts = <32 1>;
reg = <1>;
device_type = "ethernet-phy";
interface = <6>;
};
- ethernet-phy@02 {
- linux,phandle = <212002>;
- interrupt-parent = <40000>;
+ qe_phy2: ethernet-phy@02 {
+ interrupt-parent = <&mpic>;
interrupts = <31 1>;
reg = <2>;
device_type = "ethernet-phy";
interface = <6>; //ENET_1000_GMII
};
- ethernet-phy@03 {
- linux,phandle = <212003>;
- interrupt-parent = <40000>;
+ qe_phy3: ethernet-phy@03 {
+ interrupt-parent = <&mpic>;
interrupts = <32 1>;
reg = <3>;
device_type = "ethernet-phy";
};
};
- qeic@80 {
- linux,phandle = <80>;
+ qeic: qeic@80 {
interrupt-controller;
device_type = "qeic";
#address-cells = <0>;
built-in;
big-endian;
interrupts = <1e 2 1e 2>; //high:30 low:30
- interrupt-parent = <40000>;
+ interrupt-parent = <&mpic>;
};
};
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20-rc5
-# Wed Feb 7 23:54:25 2007
+# Linux kernel version: 2.6.20
+# Sat Feb 17 16:26:53 2007
#
# CONFIG_PPC64 is not set
CONFIG_PPC32=y
# CONFIG_PPC_83xx is not set
CONFIG_PPC_85xx=y
# CONFIG_PPC_86xx is not set
+# CONFIG_PPC_8xx is not set
# CONFIG_40x is not set
# CONFIG_44x is not set
-# CONFIG_8xx is not set
# CONFIG_E200 is not set
CONFIG_85xx=y
CONFIG_E500=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_MPC8540_ADS is not set
# CONFIG_MPC8560_ADS is not set
# CONFIG_MPC85xx_CDS is not set
-CONFIG_MPC8568_MDS=y
+CONFIG_MPC85xx_MDS=y
CONFIG_MPC85xx=y
CONFIG_PPC_INDIRECT_PCI_BE=y
CONFIG_MPIC=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
CONFIG_PROC_DEVICETREE=y
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_PM is not set
#
# Bus options
#
+CONFIG_ZONE_DMA=y
# CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set
CONFIG_PPC_INDIRECT_PCI=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
#
#
# Misc devices
#
-# CONFIG_TIFM_CORE is not set
#
# ATA/ATAPI/MFM/RLL support
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_OF_PLATFORM is not set
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# HID Devices
#
CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
#
# USB support
# DMA Devices
#
+#
+# Auxiliary Display support
+#
+
#
# Virtualization
#
CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_PLIST=y
-CONFIG_IOMAP_COPY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
#
# Instrumentation Support
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_LIST is not set
CONFIG_FORCED_INLINING=y
# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUGGER=y
# CONFIG_XMON is not set
# CONFIG_BDI_SWITCH is not set
# CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set
# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set
# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set
+# CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE is not set
+# CONFIG_PPC_EARLY_DEBUG_BEAT is not set
#
# Security options
# CONFIG_CRYPTO_GF128MUL is not set
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
# CONFIG_CRYPTO_LRW is not set
CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
#
help
This option enables support for the MPC85xx CDS board
-config MPC8568_MDS
- bool "Freescale MPC8568 MDS"
+config MPC85xx_MDS
+ bool "Freescale MPC85xx MDS"
select DEFAULT_UIMAGE
# select QUICC_ENGINE
help
- This option enables support for the MPC8568 MDS board
+ This option enables support for the MPC85xx MDS board
endchoice
bool
select PPC_UDBG_16550
select PPC_INDIRECT_PCI
- default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS || MPC8568_MDS
+ default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS || MPC85xx_MDS
config PPC_INDIRECT_PCI_BE
bool
obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
-obj-$(CONFIG_MPC8568_MDS) += mpc8568_mds.o
+obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
+++ /dev/null
-/*
- * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
- *
- * Author: Andy Fleming <afleming@freescale.com>
- *
- * Based on 83xx/mpc8360e_pb.c by:
- * Li Yang <LeoLi@freescale.com>
- * Yin Olivia <Hong-hua.Yin@freescale.com>
- *
- * Description:
- * MPC8568E MDS PB board specific routines.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/major.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/initrd.h>
-#include <linux/module.h>
-#include <linux/fsl_devices.h>
-
-#include <asm/of_device.h>
-#include <asm/of_platform.h>
-#include <asm/system.h>
-#include <asm/atomic.h>
-#include <asm/time.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/bootinfo.h>
-#include <asm/pci-bridge.h>
-#include <asm/mpc85xx.h>
-#include <asm/irq.h>
-#include <mm/mmu_decl.h>
-#include <asm/prom.h>
-#include <asm/udbg.h>
-#include <sysdev/fsl_soc.h>
-#include <asm/qe.h>
-#include <asm/qe_ic.h>
-#include <asm/mpic.h>
-
-#include "mpc85xx.h"
-
-#undef DEBUG
-#ifdef DEBUG
-#define DBG(fmt...) udbg_printf(fmt)
-#else
-#define DBG(fmt...)
-#endif
-
-#ifndef CONFIG_PCI
-unsigned long isa_io_base = 0;
-unsigned long isa_mem_base = 0;
-#endif
-
-/* ************************************************************************
- *
- * Setup the architecture
- *
- */
-static void __init mpc8568_mds_setup_arch(void)
-{
- struct device_node *np;
- static u8 *bcsr_regs = NULL;
-
-
- if (ppc_md.progress)
- ppc_md.progress("mpc8568_mds_setup_arch()", 0);
-
- np = of_find_node_by_type(NULL, "cpu");
- if (np != NULL) {
- const unsigned int *fp =
- get_property(np, "clock-frequency", NULL);
- if (fp != NULL)
- loops_per_jiffy = *fp / HZ;
- else
- loops_per_jiffy = 50000000 / HZ;
- of_node_put(np);
- }
-
- /* Map BCSR area */
- np = of_find_node_by_name(NULL, "bcsr");
- if (np != NULL) {
- struct resource res;
-
- of_address_to_resource(np, 0, &res);
- bcsr_regs = ioremap(res.start, res.end - res.start +1);
- of_node_put(np);
- }
-
-#ifdef CONFIG_PCI
- for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
- add_bridge(np);
- }
- of_node_put(np);
-#endif
-
-#ifdef CONFIG_QUICC_ENGINE
- if ((np = of_find_node_by_name(NULL, "qe")) != NULL) {
- qe_reset();
- of_node_put(np);
- }
-
- if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
- struct device_node *ucc = NULL;
-
- par_io_init(np);
- of_node_put(np);
-
- for ( ;(ucc = of_find_node_by_name(ucc, "ucc")) != NULL;)
- par_io_of_config(ucc);
-
- of_node_put(ucc);
- }
-
- if (bcsr_regs) {
- u8 bcsr_phy;
-
- /* Reset the Ethernet PHY */
- bcsr_phy = in_be8(&bcsr_regs[9]);
- bcsr_phy &= ~0x20;
- out_be8(&bcsr_regs[9], bcsr_phy);
-
- udelay(1000);
-
- bcsr_phy = in_be8(&bcsr_regs[9]);
- bcsr_phy |= 0x20;
- out_be8(&bcsr_regs[9], bcsr_phy);
-
- iounmap(bcsr_regs);
- }
-
-#endif /* CONFIG_QUICC_ENGINE */
-}
-
-static struct of_device_id mpc8568_ids[] = {
- { .type = "soc", },
- { .compatible = "soc", },
- { .type = "qe", },
- {},
-};
-
-static int __init mpc8568_publish_devices(void)
-{
- if (!machine_is(mpc8568_mds))
- return 0;
-
- /* Publish the QE devices */
- of_platform_bus_probe(NULL,mpc8568_ids,NULL);
-
- return 0;
-}
-device_initcall(mpc8568_publish_devices);
-
-static void __init mpc8568_mds_pic_init(void)
-{
- struct mpic *mpic;
- struct resource r;
- struct device_node *np = NULL;
-
- np = of_find_node_by_type(NULL, "open-pic");
- if (!np)
- return;
-
- if (of_address_to_resource(np, 0, &r)) {
- printk(KERN_ERR "Failed to map mpic register space\n");
- of_node_put(np);
- return;
- }
-
- mpic = mpic_alloc(np, r.start,
- MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
- 4, 0, " OpenPIC ");
- BUG_ON(mpic == NULL);
- of_node_put(np);
-
- /* Internal Interrupts */
- mpic_assign_isu(mpic, 0, r.start + 0x10200);
- mpic_assign_isu(mpic, 1, r.start + 0x10280);
- mpic_assign_isu(mpic, 2, r.start + 0x10300);
- mpic_assign_isu(mpic, 3, r.start + 0x10380);
- mpic_assign_isu(mpic, 4, r.start + 0x10400);
- mpic_assign_isu(mpic, 5, r.start + 0x10480);
- mpic_assign_isu(mpic, 6, r.start + 0x10500);
- mpic_assign_isu(mpic, 7, r.start + 0x10580);
- mpic_assign_isu(mpic, 8, r.start + 0x10600);
- mpic_assign_isu(mpic, 9, r.start + 0x10680);
- mpic_assign_isu(mpic, 10, r.start + 0x10700);
- mpic_assign_isu(mpic, 11, r.start + 0x10780);
-
- /* External Interrupts */
- mpic_assign_isu(mpic, 12, r.start + 0x10000);
- mpic_assign_isu(mpic, 13, r.start + 0x10080);
- mpic_assign_isu(mpic, 14, r.start + 0x10100);
-
- mpic_init(mpic);
-
-
-#ifdef CONFIG_QUICC_ENGINE
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
-
- qe_ic_init(np, 0);
- of_node_put(np);
-#endif /* CONFIG_QUICC_ENGINE */
-}
-
-
-static int __init mpc8568_mds_probe(void)
-{
- char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
- "model", NULL);
- if (model == NULL)
- return 0;
- if (strcmp(model, "MPC8568EMDS"))
- return 0;
-
- DBG("MPC8568EMDS found\n");
-
- return 1;
-}
-
-
-define_machine(mpc8568_mds) {
- .name = "MPC8568E MDS",
- .probe = mpc8568_mds_probe,
- .setup_arch = mpc8568_mds_setup_arch,
- .init_IRQ = mpc8568_mds_pic_init,
- .get_irq = mpic_get_irq,
- .restart = mpc85xx_restart,
- .calibrate_decr = generic_calibrate_decr,
- .progress = udbg_progress,
-};
*/
static int __init mpc85xx_ads_probe(void)
{
- /* We always match for now, eventually we should look at the flat
- dev tree to ensure this is the board we are suppose to run on
- */
- return 1;
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "MPC85xxADS");
}
define_machine(mpc85xx_ads) {
*/
static int __init mpc85xx_cds_probe(void)
{
- /* We always match for now, eventually we should look at
- * the flat dev tree to ensure this is the board we are
- * supposed to run on
- */
- return 1;
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "MPC85xxCDS");
}
define_machine(mpc85xx_cds) {
--- /dev/null
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
+ *
+ * Author: Andy Fleming <afleming@freescale.com>
+ *
+ * Based on 83xx/mpc8360e_pb.c by:
+ * Li Yang <LeoLi@freescale.com>
+ * Yin Olivia <Hong-hua.Yin@freescale.com>
+ *
+ * Description:
+ * MPC85xx MDS board specific routines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/initrd.h>
+#include <linux/module.h>
+#include <linux/fsl_devices.h>
+
+#include <asm/of_device.h>
+#include <asm/of_platform.h>
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/bootinfo.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpc85xx.h>
+#include <asm/irq.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <sysdev/fsl_soc.h>
+#include <asm/qe.h>
+#include <asm/qe_ic.h>
+#include <asm/mpic.h>
+
+#include "mpc85xx.h"
+
+#undef DEBUG
+#ifdef DEBUG
+#define DBG(fmt...) udbg_printf(fmt)
+#else
+#define DBG(fmt...)
+#endif
+
+#ifndef CONFIG_PCI
+unsigned long isa_io_base = 0;
+unsigned long isa_mem_base = 0;
+#endif
+
+/* ************************************************************************
+ *
+ * Setup the architecture
+ *
+ */
+static void __init mpc85xx_mds_setup_arch(void)
+{
+ struct device_node *np;
+ static u8 *bcsr_regs = NULL;
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
+
+ np = of_find_node_by_type(NULL, "cpu");
+ if (np != NULL) {
+ const unsigned int *fp =
+ get_property(np, "clock-frequency", NULL);
+ if (fp != NULL)
+ loops_per_jiffy = *fp / HZ;
+ else
+ loops_per_jiffy = 50000000 / HZ;
+ of_node_put(np);
+ }
+
+ /* Map BCSR area */
+ np = of_find_node_by_name(NULL, "bcsr");
+ if (np != NULL) {
+ struct resource res;
+
+ of_address_to_resource(np, 0, &res);
+ bcsr_regs = ioremap(res.start, res.end - res.start +1);
+ of_node_put(np);
+ }
+
+#ifdef CONFIG_PCI
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
+ add_bridge(np);
+ }
+ of_node_put(np);
+#endif
+
+#ifdef CONFIG_QUICC_ENGINE
+ if ((np = of_find_node_by_name(NULL, "qe")) != NULL) {
+ qe_reset();
+ of_node_put(np);
+ }
+
+ if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
+ struct device_node *ucc = NULL;
+
+ par_io_init(np);
+ of_node_put(np);
+
+ for ( ;(ucc = of_find_node_by_name(ucc, "ucc")) != NULL;)
+ par_io_of_config(ucc);
+
+ of_node_put(ucc);
+ }
+
+ if (bcsr_regs) {
+ u8 bcsr_phy;
+
+ /* Reset the Ethernet PHY */
+ bcsr_phy = in_be8(&bcsr_regs[9]);
+ bcsr_phy &= ~0x20;
+ out_be8(&bcsr_regs[9], bcsr_phy);
+
+ udelay(1000);
+
+ bcsr_phy = in_be8(&bcsr_regs[9]);
+ bcsr_phy |= 0x20;
+ out_be8(&bcsr_regs[9], bcsr_phy);
+
+ iounmap(bcsr_regs);
+ }
+
+#endif /* CONFIG_QUICC_ENGINE */
+}
+
+static struct of_device_id mpc85xx_ids[] = {
+ { .type = "soc", },
+ { .compatible = "soc", },
+ { .type = "qe", },
+ {},
+};
+
+static int __init mpc85xx_publish_devices(void)
+{
+ if (!machine_is(mpc85xx_mds))
+ return 0;
+
+ /* Publish the QE devices */
+ of_platform_bus_probe(NULL,mpc85xx_ids,NULL);
+
+ return 0;
+}
+device_initcall(mpc85xx_publish_devices);
+
+static void __init mpc85xx_mds_pic_init(void)
+{
+ struct mpic *mpic;
+ struct resource r;
+ struct device_node *np = NULL;
+
+ np = of_find_node_by_type(NULL, "open-pic");
+ if (!np)
+ return;
+
+ if (of_address_to_resource(np, 0, &r)) {
+ printk(KERN_ERR "Failed to map mpic register space\n");
+ of_node_put(np);
+ return;
+ }
+
+ mpic = mpic_alloc(np, r.start,
+ MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+ 4, 0, " OpenPIC ");
+ BUG_ON(mpic == NULL);
+ of_node_put(np);
+
+ /* Internal Interrupts */
+ mpic_assign_isu(mpic, 0, r.start + 0x10200);
+ mpic_assign_isu(mpic, 1, r.start + 0x10280);
+ mpic_assign_isu(mpic, 2, r.start + 0x10300);
+ mpic_assign_isu(mpic, 3, r.start + 0x10380);
+ mpic_assign_isu(mpic, 4, r.start + 0x10400);
+ mpic_assign_isu(mpic, 5, r.start + 0x10480);
+ mpic_assign_isu(mpic, 6, r.start + 0x10500);
+ mpic_assign_isu(mpic, 7, r.start + 0x10580);
+ mpic_assign_isu(mpic, 8, r.start + 0x10600);
+ mpic_assign_isu(mpic, 9, r.start + 0x10680);
+ mpic_assign_isu(mpic, 10, r.start + 0x10700);
+ mpic_assign_isu(mpic, 11, r.start + 0x10780);
+
+ /* External Interrupts */
+ mpic_assign_isu(mpic, 12, r.start + 0x10000);
+ mpic_assign_isu(mpic, 13, r.start + 0x10080);
+ mpic_assign_isu(mpic, 14, r.start + 0x10100);
+
+ mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_node_by_type(NULL, "qeic");
+ if (!np)
+ return;
+
+ qe_ic_init(np, 0);
+ of_node_put(np);
+#endif /* CONFIG_QUICC_ENGINE */
+}
+
+static int __init mpc85xx_mds_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "MPC85xxMDS");
+}
+
+define_machine(mpc85xx_mds) {
+ .name = "MPC85xx MDS",
+ .probe = mpc85xx_mds_probe,
+ .setup_arch = mpc85xx_mds_setup_arch,
+ .init_IRQ = mpc85xx_mds_pic_init,
+ .get_irq = mpic_get_irq,
+ .restart = mpc85xx_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
projects / cascardo / linux.git / commitdiff