Merge branch 'next/dt2' into HEAD

Conflicts:
	arch/arm/mach-exynos/clock-exynos5.c

diff --combined arch/arm/boot/dts/exynos5250.dtsi
index b55794b,f69e389..dddfd6e
--- 1/arch/arm/boot/dts/exynos5250.dtsi
--- 2/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@@ -27,10 -27,6 +27,10 @@@
                spi0 = &spi_0;
                spi1 = &spi_1;
                spi2 = &spi_2;
 +              gsc0 = &gsc_0;
 +              gsc1 = &gsc_1;
 +              gsc2 = &gsc_2;
 +              gsc3 = &gsc_3;
        };
  
        gic:interrupt-controller@10481000 {
@@@ -186,6 -182,38 +186,38 @@@
                #size-cells = <0>;
        };
  
+       dwmmc0@12200000 {
+               compatible = "samsung,exynos5250-dw-mshc";
+               reg = <0x12200000 0x1000>;
+               interrupts = <0 75 0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+ 
+       dwmmc1@12210000 {
+               compatible = "samsung,exynos5250-dw-mshc";
+               reg = <0x12210000 0x1000>;
+               interrupts = <0 76 0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+ 
+       dwmmc2@12220000 {
+               compatible = "samsung,exynos5250-dw-mshc";
+               reg = <0x12220000 0x1000>;
+               interrupts = <0 77 0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+ 
+       dwmmc3@12230000 {
+               compatible = "samsung,exynos5250-dw-mshc";
+               reg = <0x12230000 0x1000>;
+               interrupts = <0 78 0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+ 
        amba {
                #address-cells = <1>;
                #size-cells = <1>;
@@@ -464,28 -492,4 +496,28 @@@
                        #gpio-cells = <4>;
                };
        };
 +
 +      gsc_0:  gsc@0x13e00000 {
 +              compatible = "samsung,exynos5-gsc";
 +              reg = <0x13e00000 0x1000>;
 +              interrupts = <0 85 0>;
 +      };
 +
 +      gsc_1:  gsc@0x13e10000 {
 +              compatible = "samsung,exynos5-gsc";
 +              reg = <0x13e10000 0x1000>;
 +              interrupts = <0 86 0>;
 +      };
 +
 +      gsc_2:  gsc@0x13e20000 {
 +              compatible = "samsung,exynos5-gsc";
 +              reg = <0x13e20000 0x1000>;
 +              interrupts = <0 87 0>;
 +      };
 +
 +      gsc_3:  gsc@0x13e30000 {
 +              compatible = "samsung,exynos5-gsc";
 +              reg = <0x13e30000 0x1000>;
 +              interrupts = <0 88 0>;
 +      };
  };

diff --combined arch/arm/mach-exynos/clock-exynos5.c
index f3171c3,17e6c77..c44ca1e
--- 1/arch/arm/mach-exynos/clock-exynos5.c
--- 2/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@@ -166,6 -166,11 +166,6 @@@ static int exynos5_clk_ip_gen_ctrl(stru
        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
  }
  
 -static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
 -{
 -      return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
 -}
 -
  static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
  {
        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
@@@ -547,68 -552,6 +547,68 @@@ static struct clksrc_clk exynos5_clk_ac
        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
  };
  
 +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
 +      .clk    = {
 +              .name           = "mout_aclk_300_gscl_mid",
 +      },
 +      .sources = &exynos5_clkset_aclk,
 +      .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
 +};
 +
 +static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
 +      [0] = &exynos5_clk_sclk_vpll.clk,
 +      [1] = &exynos5_clk_mout_cpll.clk,
 +};
 +
 +static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
 +      .sources        = exynos5_clkset_aclk_300_mid1_list,
 +      .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
 +};
 +
 +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
 +      .clk    = {
 +              .name           = "mout_aclk_300_gscl_mid1",
 +      },
 +      .sources = &exynos5_clkset_aclk_300_gscl_mid1,
 +      .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
 +};
 +
 +static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
 +      [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
 +      [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
 +};
 +
 +static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
 +      .sources        = exynos5_clkset_aclk_300_gscl_list,
 +      .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
 +};
 +
 +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
 +      .clk    = {
 +              .name           = "mout_aclk_300_gscl",
 +      },
 +      .sources = &exynos5_clkset_aclk_300_gscl,
 +      .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
 +};
 +
 +static struct clk *exynos5_clk_src_gscl_300_list[] = {
 +      [0] = &clk_ext_xtal_mux,
 +      [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
 +};
 +
 +static struct clksrc_sources exynos5_clk_src_gscl_300 = {
 +      .sources        = exynos5_clk_src_gscl_300_list,
 +      .nr_sources     = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
 +};
 +
 +static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
 +      .clk    = {
 +              .name           = "aclk_300_gscl",
 +      },
 +      .sources = &exynos5_clk_src_gscl_300,
 +      .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
 +};
 +
  static struct clk exynos5_init_clocks_off[] = {
        {
                .name           = "timers",
@@@ -626,34 -569,29 +626,29 @@@
                .enable         = exynos5_clk_ip_peris_ctrl,
                .ctrlbit        = (1 << 19),
        }, {
-               .name           = "hsmmc",
-               .devname        = "exynos4-sdhci.0",
+               .name           = "biu",        /* bus interface unit clock */
+               .devname        = "dw_mmc.0",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 12),
        }, {
-               .name           = "hsmmc",
-               .devname        = "exynos4-sdhci.1",
+               .name           = "biu",
+               .devname        = "dw_mmc.1",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 13),
        }, {
-               .name           = "hsmmc",
-               .devname        = "exynos4-sdhci.2",
+               .name           = "biu",
+               .devname        = "dw_mmc.2",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 14),
        }, {
-               .name           = "hsmmc",
-               .devname        = "exynos4-sdhci.3",
+               .name           = "biu",
+               .devname        = "dw_mmc.3",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 15),
-       }, {
-               .name           = "dwmci",
-               .parent         = &exynos5_clk_aclk_200.clk,
-               .enable         = exynos5_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 16),
        }, {
                .name           = "sata",
                .devname        = "ahci",
@@@ -728,6 -666,10 +723,6 @@@
                .name           = "usbotg",
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 7),
 -      }, {
 -              .name           = "gps",
 -              .enable         = exynos5_clk_ip_gps_ctrl,
 -              .ctrlbit        = ((1 << 3) | (1 << 2) | (1 << 0)),
        }, {
                .name           = "nfcon",
                .enable         = exynos5_clk_ip_fsys_ctrl,
@@@ -816,26 -758,6 +811,26 @@@
                .parent         = &exynos5_clk_aclk_66.clk,
                .enable         = exynos5_clk_ip_peric_ctrl,
                .ctrlbit        = (1 << 18),
 +      }, {
 +              .name           = "gscl",
 +              .devname        = "exynos-gsc.0",
 +              .enable         = exynos5_clk_ip_gscl_ctrl,
 +              .ctrlbit        = (1 << 0),
 +      }, {
 +              .name           = "gscl",
 +              .devname        = "exynos-gsc.1",
 +              .enable         = exynos5_clk_ip_gscl_ctrl,
 +              .ctrlbit        = (1 << 1),
 +      }, {
 +              .name           = "gscl",
 +              .devname        = "exynos-gsc.2",
 +              .enable         = exynos5_clk_ip_gscl_ctrl,
 +              .ctrlbit        = (1 << 2),
 +      }, {
 +              .name           = "gscl",
 +              .devname        = "exynos-gsc.3",
 +              .enable         = exynos5_clk_ip_gscl_ctrl,
 +              .ctrlbit        = (1 << 3),
        }, {
                .name           = SYSMMU_CLOCK_NAME,
                .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
@@@ -964,13 -886,6 +959,13 @@@ static struct clk exynos5_clk_mdma1 = 
        .ctrlbit        = (1 << 4),
  };
  
 +static struct clk exynos5_clk_fimd1 = {
 +      .name           = "fimd",
 +      .devname        = "exynos5-fb.1",
 +      .enable         = exynos5_clk_ip_disp1_ctrl,
 +      .ctrlbit        = (1 << 0),
 +};
 +
  struct clk *exynos5_clkset_group_list[] = {
        [0] = &clk_ext_xtal_mux,
        [1] = NULL,
@@@ -1095,8 -1010,8 +1090,8 @@@ static struct clksrc_clk exynos5_clk_sc
  
  static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
        .clk    = {
-               .name           = "sclk_mmc",
-               .devname        = "exynos4-sdhci.0",
+               .name           = "ciu",        /* card interface unit clock */
+               .devname        = "dw_mmc.0",
                .parent         = &exynos5_clk_dout_mmc0.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 0),
@@@ -1106,8 -1021,8 +1101,8 @@@
  
  static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
        .clk    = {
-               .name           = "sclk_mmc",
-               .devname        = "exynos4-sdhci.1",
+               .name           = "ciu",
+               .devname        = "dw_mmc.1",
                .parent         = &exynos5_clk_dout_mmc1.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 4),
@@@ -1117,8 -1032,8 +1112,8 @@@
  
  static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
        .clk    = {
-               .name           = "sclk_mmc",
-               .devname        = "exynos4-sdhci.2",
+               .name           = "ciu",
+               .devname        = "dw_mmc.2",
                .parent         = &exynos5_clk_dout_mmc2.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 8),
@@@ -1128,8 -1043,8 +1123,8 @@@
  
  static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
        .clk    = {
-               .name           = "sclk_mmc",
-               .devname        = "exynos4-sdhci.3",
+               .name           = "ciu",
+               .devname        = "dw_mmc.3",
                .parent         = &exynos5_clk_dout_mmc3.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 12),
@@@ -1200,28 -1115,18 +1195,20 @@@ static struct clksrc_clk exynos5_clk_sc
        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
  };
  
 +struct clksrc_clk exynos5_clk_sclk_fimd1 = {
 +      .clk    = {
 +              .name           = "sclk_fimd",
 +              .devname        = "exynos5-fb.1",
 +              .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
 +              .ctrlbit        = (1 << 0),
 +      },
 +      .sources = &exynos5_clkset_group,
 +      .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
 +      .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
 +};
 +
  static struct clksrc_clk exynos5_clksrcs[] = {
        {
--              .clk    = {
-                       .name           = "sclk_dwmci",
-                       .parent         = &exynos5_clk_dout_mmc4.clk,
-                       .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                       .ctrlbit        = (1 << 16),
 -                      .name           = "sclk_fimd",
 -                      .devname        = "s3cfb.1",
 -                      .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
 -                      .ctrlbit        = (1 << 0),
--              },
-               .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
 -              .sources = &exynos5_clkset_group,
 -              .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
 -              .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
--      }, {
                .clk    = {
                        .name           = "aclk_266_gscl",
                },
@@@ -1307,10 -1212,6 +1294,10 @@@ static struct clksrc_clk *exynos5_syscl
        &exynos5_clk_aclk_266,
        &exynos5_clk_aclk_200,
        &exynos5_clk_aclk_166,
 +      &exynos5_clk_aclk_300_gscl,
 +      &exynos5_clk_mout_aclk_300_gscl,
 +      &exynos5_clk_mout_aclk_300_gscl_mid,
 +      &exynos5_clk_mout_aclk_300_gscl_mid1,
        &exynos5_clk_aclk_66_pre,
        &exynos5_clk_aclk_66,
        &exynos5_clk_dout_mmc0,
@@@ -1326,14 -1227,12 +1313,14 @@@
        &exynos5_clk_mdout_spi0,
        &exynos5_clk_mdout_spi1,
        &exynos5_clk_mdout_spi2,
 +      &exynos5_clk_sclk_fimd1,
  };
  
  static struct clk *exynos5_clk_cdev[] = {
        &exynos5_clk_pdma0,
        &exynos5_clk_pdma1,
        &exynos5_clk_mdma1,
 +      &exynos5_clk_fimd1,
  };
  
  static struct clksrc_clk *exynos5_clksrc_cdev[] = {
@@@ -1362,7 -1261,6 +1349,7 @@@ static struct clk_lookup exynos5_clk_lo
        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
 +      CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
  };
  
  static unsigned long exynos5_epll_get_rate(struct clk *clk)

diff --combined arch/arm/mach-exynos/include/mach/map.h
index 5aa77f9,5edbbe9..8480849
--- 1/arch/arm/mach-exynos/include/mach/map.h
--- 2/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@@ -89,7 -89,7 +89,7 @@@
  #define EXYNOS4_PA_L2CC                       0x10502000
  
  #define EXYNOS4_PA_MDMA0              0x10810000
 -#define EXYNOS4_PA_MDMA1              0x12840000
 +#define EXYNOS4_PA_MDMA1              0x12850000
  #define EXYNOS4_PA_PDMA0              0x12680000
  #define EXYNOS4_PA_PDMA1              0x12690000
  #define EXYNOS5_PA_MDMA0              0x10800000
@@@ -121,11 -121,6 +121,11 @@@
  #define EXYNOS4_PA_SYSMMU_MFC_L               0x13620000
  #define EXYNOS4_PA_SYSMMU_MFC_R               0x13630000
  
 +#define EXYNOS5_PA_GSC0                       0x13E00000
 +#define EXYNOS5_PA_GSC1                       0x13E10000
 +#define EXYNOS5_PA_GSC2                       0x13E20000
 +#define EXYNOS5_PA_GSC3                       0x13E30000
 +
  #define EXYNOS5_PA_SYSMMU_MDMA1               0x10A40000
  #define EXYNOS5_PA_SYSMMU_SSS         0x10A50000
  #define EXYNOS5_PA_SYSMMU_2D          0x10A60000
@@@ -136,6 -131,7 +136,6 @@@
  #define EXYNOS5_PA_SYSMMU_JPEG                0x11F20000
  #define EXYNOS5_PA_SYSMMU_IOP         0x12360000
  #define EXYNOS5_PA_SYSMMU_RTIC                0x12370000
 -#define EXYNOS5_PA_SYSMMU_GPS         0x12630000
  #define EXYNOS5_PA_SYSMMU_ISP         0x13260000
  #define EXYNOS5_PA_SYSMMU_DRC         0x12370000
  #define EXYNOS5_PA_SYSMMU_SCALERC     0x13280000
@@@ -177,6 -173,10 +177,10 @@@
  
  #define EXYNOS4_PA_HSMMC(x)           (0x12510000 + ((x) * 0x10000))
  #define EXYNOS4_PA_DWMCI              0x12550000
+ #define EXYNOS5_PA_DWMCI0             0x12200000
+ #define EXYNOS5_PA_DWMCI1             0x12210000
+ #define EXYNOS5_PA_DWMCI2             0x12220000
+ #define EXYNOS5_PA_DWMCI3             0x12230000
  
  #define EXYNOS4_PA_HSOTG              0x12480000
  #define EXYNOS4_PA_USB_HSPHY          0x125B0000

diff --combined arch/arm/mach-exynos/mach-exynos5-dt.c
index e707eb1,ce82f30..fee9dcd
--- 1/arch/arm/mach-exynos/mach-exynos5-dt.c
--- 2/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@@ -47,6 -47,14 +47,14 @@@ static const struct of_dev_auxdata exyn
                                "s3c2440-i2c.0", NULL),
        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
                                "s3c2440-i2c.1", NULL),
+       OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
+                               "dw_mmc.0", NULL),
+       OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
+                               "dw_mmc.1", NULL),
+       OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
+                               "dw_mmc.2", NULL),
+       OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
+                               "dw_mmc.3", NULL),
        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
                                "exynos4210-spi.0", NULL),
        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
@@@ -56,14 -64,6 +64,14 @@@
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
 +      OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
 +                              "exynos-gsc.0", NULL),
 +      OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
 +                              "exynos-gsc.1", NULL),
 +      OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
 +                              "exynos-gsc.2", NULL),
 +      OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
 +                              "exynos-gsc.3", NULL),
        {},
  };