drm/i915: SWF screatch registers need an offset on VLV

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5944b4b..215443c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3051,19 +3051,19 @@
                (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
 
 /* VBIOS flags */
-#define SWF00                  0x71410
-#define SWF01                  0x71414
-#define SWF02                  0x71418
-#define SWF03                  0x7141c
-#define SWF04                  0x71420
-#define SWF05                  0x71424
-#define SWF06                  0x71428
-#define SWF10                  0x70410
-#define SWF11                  0x70414
-#define SWF14                  0x71420
-#define SWF30                  0x72414
-#define SWF31                  0x72418
-#define SWF32                  0x7241c
+#define SWF00                  (dev_priv->info->display_mmio_offset + 0x71410)
+#define SWF01                  (dev_priv->info->display_mmio_offset + 0x71414)
+#define SWF02                  (dev_priv->info->display_mmio_offset + 0x71418)
+#define SWF03                  (dev_priv->info->display_mmio_offset + 0x7141c)
+#define SWF04                  (dev_priv->info->display_mmio_offset + 0x71420)
+#define SWF05                  (dev_priv->info->display_mmio_offset + 0x71424)
+#define SWF06                  (dev_priv->info->display_mmio_offset + 0x71428)
+#define SWF10                  (dev_priv->info->display_mmio_offset + 0x70410)
+#define SWF11                  (dev_priv->info->display_mmio_offset + 0x70414)
+#define SWF14                  (dev_priv->info->display_mmio_offset + 0x71420)
+#define SWF30                  (dev_priv->info->display_mmio_offset + 0x72414)
+#define SWF31                  (dev_priv->info->display_mmio_offset + 0x72418)
+#define SWF32                  (dev_priv->info->display_mmio_offset + 0x7241c)
 
 /* Pipe B */
 #define _PIPEBDSL              (dev_priv->info->display_mmio_offset + 0x71000)