CHROMIUM: exynos: dts: Update PS8622 bridge address

The bridge is now at 0x8 instead of 0x48.

Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=none
TEST=See display on Spring.

Change-Id: I4903824d401c5ac46cc101ec39b5c6f01809d1db
Reviewed-on: https://gerrit.chromium.org/gerrit/41689
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vic Yang <victoryang@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>

diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index 35baae4..22528ff 100644 (file)
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -86,9 +86,9 @@
        };
 
        i2c@12CD0000 {
-               ps8622-bridge@20 {
+               ps8622-bridge@8 {
                        compatible = "parade,ps8622";
-                       reg = <0x48>;
+                       reg = <0x08>;
                        sleep-gpio = <&gpc3 6 1 0 0>;
                        reset-gpio = <&gpc3 1 1 0 0>;
                        hpd-gpio = <&gpc3 0 0 0 0>;