drm/amdgpu: disable legacy path of firmware check if powerplay is enabled

Powerplay will use a different interface once it's integrated.  These
legacy pathes will be removed once powerplay is enabled by default.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index b20369e..d90aae0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -2902,16 +2902,18 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
 
        gfx_v8_0_rlc_reset(adev);
 
-       if (!adev->firmware.smu_load) {
-               /* legacy rlc firmware loading */
-               r = gfx_v8_0_rlc_load_microcode(adev);
-               if (r)
-                       return r;
-       } else {
-               r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-                                               AMDGPU_UCODE_ID_RLC_G);
-               if (r)
-                       return -EINVAL;
+       if (!amdgpu_powerplay) {
+               if (!adev->firmware.smu_load) {
+                       /* legacy rlc firmware loading */
+                       r = gfx_v8_0_rlc_load_microcode(adev);
+                       if (r)
+                               return r;
+               } else {
+                       r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
+                                                       AMDGPU_UCODE_ID_RLC_G);
+                       if (r)
+                               return -EINVAL;
+               }
        }
 
        gfx_v8_0_rlc_start(adev);
@@ -3802,35 +3804,37 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
        if (!(adev->flags & AMD_IS_APU))
                gfx_v8_0_enable_gui_idle_interrupt(adev, false);
 
-       if (!adev->firmware.smu_load) {
-               /* legacy firmware loading */
-               r = gfx_v8_0_cp_gfx_load_microcode(adev);
-               if (r)
-                       return r;
-
-               r = gfx_v8_0_cp_compute_load_microcode(adev);
-               if (r)
-                       return r;
-       } else {
-               r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-                                               AMDGPU_UCODE_ID_CP_CE);
-               if (r)
-                       return -EINVAL;
-
-               r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-                                               AMDGPU_UCODE_ID_CP_PFP);
-               if (r)
-                       return -EINVAL;
-
-               r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-                                               AMDGPU_UCODE_ID_CP_ME);
-               if (r)
-                       return -EINVAL;
+       if (!amdgpu_powerplay) {
+               if (!adev->firmware.smu_load) {
+                       /* legacy firmware loading */
+                       r = gfx_v8_0_cp_gfx_load_microcode(adev);
+                       if (r)
+                               return r;
 
-               r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-                                               AMDGPU_UCODE_ID_CP_MEC1);
-               if (r)
-                       return -EINVAL;
+                       r = gfx_v8_0_cp_compute_load_microcode(adev);
+                       if (r)
+                               return r;
+               } else {
+                       r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
+                                                       AMDGPU_UCODE_ID_CP_CE);
+                       if (r)
+                               return -EINVAL;
+
+                       r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
+                                                       AMDGPU_UCODE_ID_CP_PFP);
+                       if (r)
+                               return -EINVAL;
+
+                       r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
+                                                       AMDGPU_UCODE_ID_CP_ME);
+                       if (r)
+                               return -EINVAL;
+
+                       r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
+                                                       AMDGPU_UCODE_ID_CP_MEC1);
+                       if (r)
+                               return -EINVAL;
+               }
        }
 
        r = gfx_v8_0_cp_gfx_resume(adev);

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 7253132..8091c1c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -727,18 +727,20 @@ static int sdma_v3_0_start(struct amdgpu_device *adev)
 {
        int r, i;
 
-       if (!adev->firmware.smu_load) {
-               r = sdma_v3_0_load_microcode(adev);
-               if (r)
-                       return r;
-       } else {
-               for (i = 0; i < adev->sdma.num_instances; i++) {
-                       r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-                                                                        (i == 0) ?
-                                                                        AMDGPU_UCODE_ID_SDMA0 :
-                                                                        AMDGPU_UCODE_ID_SDMA1);
+       if (!amdgpu_powerplay) {
+               if (!adev->firmware.smu_load) {
+                       r = sdma_v3_0_load_microcode(adev);
                        if (r)
-                               return -EINVAL;
+                               return r;
+               } else {
+                       for (i = 0; i < adev->sdma.num_instances; i++) {
+                               r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
+                                                                                (i == 0) ?
+                                                                                AMDGPU_UCODE_ID_SDMA0 :
+                                                                                AMDGPU_UCODE_ID_SDMA1);
+                               if (r)
+                                       return -EINVAL;
+                       }
                }
        }