#define __NVKM_BUS_H__
#include <core/subdev.h>
-struct nvkm_bus_intr {
- u32 stat;
- u32 unit;
-};
-
struct nvkm_bus {
+ const struct nvkm_bus_func *func;
struct nvkm_subdev subdev;
- int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32);
- u32 hwsq_size;
};
-static inline struct nvkm_bus *
-nvkm_bus(void *obj)
-{
- return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BUS);
-}
-
-#define nvkm_bus_create(p, e, o, d) \
- nvkm_subdev_create_((p), (e), (o), 0, "PBUS", "master", \
- sizeof(**d), (void **)d)
-#define nvkm_bus_destroy(p) \
- nvkm_subdev_destroy(&(p)->subdev)
-#define nvkm_bus_init(p) \
- nvkm_subdev_init_old(&(p)->subdev)
-#define nvkm_bus_fini(p, s) \
- nvkm_subdev_fini_old(&(p)->subdev, (s))
-
-#define _nvkm_bus_dtor _nvkm_subdev_dtor
-#define _nvkm_bus_init _nvkm_subdev_init
-#define _nvkm_bus_fini _nvkm_subdev_fini
-
-extern struct nvkm_oclass *nv04_bus_oclass;
-extern struct nvkm_oclass *nv31_bus_oclass;
-extern struct nvkm_oclass *nv50_bus_oclass;
-extern struct nvkm_oclass *g94_bus_oclass;
-extern struct nvkm_oclass *gf100_bus_oclass;
-
/* interface to sequencer */
struct nvkm_hwsq;
-int nvkm_hwsq_init(struct nvkm_bus *, struct nvkm_hwsq **);
+int nvkm_hwsq_init(struct nvkm_subdev *, struct nvkm_hwsq **);
int nvkm_hwsq_fini(struct nvkm_hwsq **, bool exec);
void nvkm_hwsq_wr32(struct nvkm_hwsq *, u32 addr, u32 data);
void nvkm_hwsq_setf(struct nvkm_hwsq *, u8 flag, int data);
void nvkm_hwsq_wait(struct nvkm_hwsq *, u8 flag, u8 data);
void nvkm_hwsq_nsec(struct nvkm_hwsq *, u32 nsec);
+
+int nv04_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
+int nv31_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
+int nv50_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
+int g94_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
+int gf100_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
#endif
nv4_chipset = {
.name = "NV04",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv04_devinit_new,
// .fb = nv04_fb_new,
nv5_chipset = {
.name = "NV05",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv05_devinit_new,
// .fb = nv04_fb_new,
nv10_chipset = {
.name = "NV10",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
nv11_chipset = {
.name = "NV11",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
nv15_chipset = {
.name = "NV15",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
nv17_chipset = {
.name = "NV17",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
nv18_chipset = {
.name = "NV18",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
nv1a_chipset = {
.name = "nForce",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv1a_fb_new,
nv1f_chipset = {
.name = "nForce2",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv1a_fb_new,
nv20_chipset = {
.name = "NV20",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv20_fb_new,
nv25_chipset = {
.name = "NV25",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
nv28_chipset = {
.name = "NV28",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
nv2a_chipset = {
.name = "NV2A",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
nv30_chipset = {
.name = "NV30",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv30_fb_new,
nv31_chipset = {
.name = "NV31",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv30_fb_new,
nv34_chipset = {
.name = "NV34",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
nv35_chipset = {
.name = "NV35",
.bios = nvkm_bios_new,
-// .bus = nv04_bus_new,
+ .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv35_fb_new,
nv36_chipset = {
.name = "NV36",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv36_fb_new,
nv40_chipset = {
.name = "NV40",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv40_fb_new,
nv41_chipset = {
.name = "NV41",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
nv42_chipset = {
.name = "NV42",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
nv43_chipset = {
.name = "NV43",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
nv44_chipset = {
.name = "NV44",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv44_fb_new,
nv45_chipset = {
.name = "NV45",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv40_fb_new,
nv46_chipset = {
.name = "G72",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
nv47_chipset = {
.name = "G70",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv47_fb_new,
nv49_chipset = {
.name = "G71",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv49_fb_new,
nv4a_chipset = {
.name = "NV44A",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv44_fb_new,
nv4b_chipset = {
.name = "G73",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv49_fb_new,
nv4c_chipset = {
.name = "C61",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
nv4e_chipset = {
.name = "C51",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv4e_fb_new,
.name = "G80",
.bar = nv50_bar_new,
.bios = nvkm_bios_new,
-// .bus = nv50_bus_new,
+ .bus = nv50_bus_new,
// .clk = nv50_clk_new,
// .devinit = nv50_devinit_new,
// .fb = nv50_fb_new,
nv63_chipset = {
.name = "C73",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
nv67_chipset = {
.name = "C67",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
nv68_chipset = {
.name = "C68",
.bios = nvkm_bios_new,
-// .bus = nv31_bus_new,
+ .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
.name = "G84",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
-// .bus = nv50_bus_new,
+ .bus = nv50_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
.name = "G86",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
-// .bus = nv50_bus_new,
+ .bus = nv50_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
.name = "G92",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
-// .bus = nv50_bus_new,
+ .bus = nv50_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
.name = "G94",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
-// .bus = g94_bus_new,
+ .bus = g94_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .mxm = nv50_mxm_new,
// .devinit = g84_devinit_new,
// .mc = g94_mc_new,
-// .bus = g94_bus_new,
+ .bus = g94_bus_new,
// .timer = nv04_timer_new,
// .fb = g84_fb_new,
// .imem = nv50_instmem_new,
// .mxm = nv50_mxm_new,
// .devinit = g98_devinit_new,
// .mc = g98_mc_new,
-// .bus = g94_bus_new,
+ .bus = g94_bus_new,
// .timer = nv04_timer_new,
// .fb = g84_fb_new,
// .imem = nv50_instmem_new,
.name = "GT200",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
-// .bus = g94_bus_new,
+ .bus = g94_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
.name = "GT215",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
-// .bus = g94_bus_new,
+ .bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
.name = "GT216",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
-// .bus = g94_bus_new,
+ .bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
.name = "GT218",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
-// .bus = g94_bus_new,
+ .bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
.name = "MCP77/MCP78",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
-// .bus = g94_bus_new,
+ .bus = g94_bus_new,
// .clk = mcp77_clk_new,
// .devinit = g98_devinit_new,
// .fb = mcp77_fb_new,
.name = "MCP79/MCP7A",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
-// .bus = g94_bus_new,
+ .bus = g94_bus_new,
// .clk = mcp77_clk_new,
// .devinit = g98_devinit_new,
// .fb = mcp77_fb_new,
.name = "MCP89",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
-// .bus = g94_bus_new,
+ .bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = mcp89_devinit_new,
// .fb = mcp89_fb_new,
.name = "GF100",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.name = "GF108",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.name = "GF106",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.name = "GF104",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.name = "GF110",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.name = "GF114",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.name = "GF116",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.name = "GF117",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.name = "GF119",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.name = "GK104",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
.name = "GK106",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
.name = "GK107",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
nvea_chipset = {
.name = "GK20A",
.bar = gk20a_bar_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gk20a_clk_new,
// .fb = gk20a_fb_new,
// .fuse = gf100_fuse_new,
.name = "GK110",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
.name = "GK110B",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
.name = "GK208B",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
.name = "GK208",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
.name = "GM107",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gm107_devinit_new,
// .fb = gm107_fb_new,
.name = "GM204",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .devinit = gm204_devinit_new,
// .fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
.name = "GM206",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .devinit = gm204_devinit_new,
// .fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
nv12b_chipset = {
.name = "GM20B",
.bar = gk20a_bar_new,
-// .bus = gf100_bus_new,
+ .bus = gf100_bus_new,
// .fb = gk20a_fb_new,
// .fuse = gm107_fuse_new,
// .ibus = gk20a_ibus_new,
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
case 0xea:
device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
- device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
+nvkm-y += nvkm/subdev/bus/base.o
nvkm-y += nvkm/subdev/bus/hwsq.o
nvkm-y += nvkm/subdev/bus/nv04.o
nvkm-y += nvkm/subdev/bus/nv31.o
--- /dev/null
+/*
+ * Copyright 2015 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+#include "priv.h"
+
+static void
+nvkm_bus_intr(struct nvkm_subdev *subdev)
+{
+ struct nvkm_bus *bus = nvkm_bus(subdev);
+ bus->func->intr(bus);
+}
+
+static int
+nvkm_bus_init(struct nvkm_subdev *subdev)
+{
+ struct nvkm_bus *bus = nvkm_bus(subdev);
+ bus->func->init(bus);
+ return 0;
+}
+
+static void *
+nvkm_bus_dtor(struct nvkm_subdev *subdev)
+{
+ return nvkm_bus(subdev);
+}
+
+static const struct nvkm_subdev_func
+nvkm_bus = {
+ .dtor = nvkm_bus_dtor,
+ .init = nvkm_bus_init,
+ .intr = nvkm_bus_intr,
+};
+
+int
+nvkm_bus_new_(const struct nvkm_bus_func *func, struct nvkm_device *device,
+ int index, struct nvkm_bus **pbus)
+{
+ struct nvkm_bus *bus;
+ if (!(bus = *pbus = kzalloc(sizeof(*bus), GFP_KERNEL)))
+ return -ENOMEM;
+ nvkm_subdev_ctor(&nvkm_bus, device, index, 0, &bus->subdev);
+ bus->func = func;
+ return 0;
+}
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
-#include "nv04.h"
+#include "priv.h"
#include <subdev/timer.h>
return 0;
}
-struct nvkm_oclass *
-g94_bus_oclass = &(struct nv04_bus_impl) {
- .base.handle = NV_SUBDEV(BUS, 0x94),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = nv04_bus_ctor,
- .dtor = _nvkm_bus_dtor,
- .init = nv50_bus_init,
- .fini = _nvkm_bus_fini,
- },
+static const struct nvkm_bus_func
+g94_bus = {
+ .init = nv50_bus_init,
.intr = nv50_bus_intr,
.hwsq_exec = g94_bus_hwsq_exec,
.hwsq_size = 128,
-}.base;
+};
+
+int
+g94_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus)
+{
+ return nvkm_bus_new_(&g94_bus, device, index, pbus);
+}
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
-#include "nv04.h"
+#include "priv.h"
static void
-gf100_bus_intr(struct nvkm_subdev *subdev)
+gf100_bus_intr(struct nvkm_bus *bus)
{
+ struct nvkm_subdev *subdev = &bus->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
}
}
-static int
-gf100_bus_init(struct nvkm_object *object)
+static void
+gf100_bus_init(struct nvkm_bus *bus)
{
- struct nvkm_bus *bus = (void *)object;
struct nvkm_device *device = bus->subdev.device;
- int ret;
-
- ret = nvkm_bus_init(bus);
- if (ret)
- return ret;
-
nvkm_wr32(device, 0x001100, 0xffffffff);
nvkm_wr32(device, 0x001140, 0x0000000e);
- return 0;
}
-struct nvkm_oclass *
-gf100_bus_oclass = &(struct nv04_bus_impl) {
- .base.handle = NV_SUBDEV(BUS, 0xc0),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = nv04_bus_ctor,
- .dtor = _nvkm_bus_dtor,
- .init = gf100_bus_init,
- .fini = _nvkm_bus_fini,
- },
+static const struct nvkm_bus_func
+gf100_bus = {
+ .init = gf100_bus_init,
.intr = gf100_bus_intr,
-}.base;
+};
+
+int
+gf100_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus)
+{
+ return nvkm_bus_new_(&gf100_bus, device, index, pbus);
+}
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-#include <subdev/bus.h>
+#include "priv.h"
struct nvkm_hwsq {
- struct nvkm_bus *bus;
+ struct nvkm_subdev *subdev;
u32 addr;
u32 data;
struct {
}
int
-nvkm_hwsq_init(struct nvkm_bus *bus, struct nvkm_hwsq **phwsq)
+nvkm_hwsq_init(struct nvkm_subdev *subdev, struct nvkm_hwsq **phwsq)
{
struct nvkm_hwsq *hwsq;
hwsq = *phwsq = kmalloc(sizeof(*hwsq), GFP_KERNEL);
if (hwsq) {
- hwsq->bus = bus;
+ hwsq->subdev = subdev;
hwsq->addr = ~0;
hwsq->data = ~0;
memset(hwsq->c.data, 0x7f, sizeof(hwsq->c.data));
struct nvkm_hwsq *hwsq = *phwsq;
int ret = 0, i;
if (hwsq) {
- struct nvkm_bus *bus = hwsq->bus;
- struct nvkm_subdev *subdev = &bus->subdev;
+ struct nvkm_subdev *subdev = hwsq->subdev;
+ struct nvkm_bus *bus = subdev->device->bus;
hwsq->c.size = (hwsq->c.size + 4) / 4;
- if (hwsq->c.size <= bus->hwsq_size) {
+ if (hwsq->c.size <= bus->func->hwsq_size) {
if (exec)
- ret = bus->hwsq_exec(bus, (u32 *)hwsq->c.data,
- hwsq->c.size);
+ ret = bus->func->hwsq_exec(bus,
+ (u32 *)hwsq->c.data,
+ hwsq->c.size);
if (ret)
nvkm_error(subdev, "hwsq exec failed: %d\n", ret);
} else {
void
nvkm_hwsq_wr32(struct nvkm_hwsq *hwsq, u32 addr, u32 data)
{
- nvkm_debug(&hwsq->bus->subdev, "R[%06x] = %08x\n", addr, data);
+ nvkm_debug(hwsq->subdev, "R[%06x] = %08x\n", addr, data);
if (hwsq->data != data) {
if ((data & 0xffff0000) != (hwsq->data & 0xffff0000)) {
void
nvkm_hwsq_setf(struct nvkm_hwsq *hwsq, u8 flag, int data)
{
- nvkm_debug(&hwsq->bus->subdev, " FLAG[%02x] = %d\n", flag, data);
+ nvkm_debug(hwsq->subdev, " FLAG[%02x] = %d\n", flag, data);
flag += 0x80;
if (data >= 0)
flag += 0x20;
void
nvkm_hwsq_wait(struct nvkm_hwsq *hwsq, u8 flag, u8 data)
{
- nvkm_debug(&hwsq->bus->subdev, " WAIT[%02x] = %d\n", flag, data);
+ nvkm_debug(hwsq->subdev, " WAIT[%02x] = %d\n", flag, data);
hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data });
}
shift++;
}
- nvkm_debug(&hwsq->bus->subdev, " DELAY = %d ns\n", nsec);
+ nvkm_debug(hwsq->subdev, " DELAY = %d ns\n", nsec);
hwsq_cmd(hwsq, 1, (u8[]){ 0x00 | (shift << 2) | usec });
}
static inline int
hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev)
{
- struct nvkm_bus *bus = nvkm_bus(subdev);
int ret;
- ret = nvkm_hwsq_init(bus, &ram->hwsq);
+ ret = nvkm_hwsq_init(subdev, &ram->hwsq);
if (ret)
return ret;
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
-#include "nv04.h"
+#include "priv.h"
+
+#include <subdev/gpio.h>
#include <subdev/gpio.h>
static void
-nv04_bus_intr(struct nvkm_subdev *subdev)
+nv04_bus_intr(struct nvkm_bus *bus)
{
+ struct nvkm_subdev *subdev = &bus->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
}
}
-static int
-nv04_bus_init(struct nvkm_object *object)
+static void
+nv04_bus_init(struct nvkm_bus *bus)
{
- struct nvkm_bus *bus = (void *)object;
struct nvkm_device *device = bus->subdev.device;
-
nvkm_wr32(device, 0x001100, 0xffffffff);
nvkm_wr32(device, 0x001140, 0x00000111);
-
- return nvkm_bus_init(bus);
}
+static const struct nvkm_bus_func
+nv04_bus = {
+ .init = nv04_bus_init,
+ .intr = nv04_bus_intr,
+};
+
int
-nv04_bus_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+nv04_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus)
{
- struct nv04_bus_impl *impl = (void *)oclass;
- struct nvkm_bus *bus;
- int ret;
-
- ret = nvkm_bus_create(parent, engine, oclass, &bus);
- *pobject = nv_object(bus);
- if (ret)
- return ret;
-
- nv_subdev(bus)->intr = impl->intr;
- bus->hwsq_exec = impl->hwsq_exec;
- bus->hwsq_size = impl->hwsq_size;
- return 0;
+ return nvkm_bus_new_(&nv04_bus, device, index, pbus);
}
-
-struct nvkm_oclass *
-nv04_bus_oclass = &(struct nv04_bus_impl) {
- .base.handle = NV_SUBDEV(BUS, 0x04),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = nv04_bus_ctor,
- .dtor = _nvkm_bus_dtor,
- .init = nv04_bus_init,
- .fini = _nvkm_bus_fini,
- },
- .intr = nv04_bus_intr,
-}.base;
+++ /dev/null
-#ifndef __NVKM_BUS_NV04_H__
-#define __NVKM_BUS_NV04_H__
-#include <subdev/bus.h>
-
-int nv04_bus_ctor(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, void *, u32,
- struct nvkm_object **);
-int nv50_bus_init(struct nvkm_object *);
-void nv50_bus_intr(struct nvkm_subdev *);
-
-struct nv04_bus_impl {
- struct nvkm_oclass base;
- void (*intr)(struct nvkm_subdev *);
- int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32);
- u32 hwsq_size;
-};
-#endif
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
-#include "nv04.h"
+#include "priv.h"
#include <subdev/gpio.h>
#include <subdev/therm.h>
static void
-nv31_bus_intr(struct nvkm_subdev *subdev)
+nv31_bus_intr(struct nvkm_bus *bus)
{
+ struct nvkm_subdev *subdev = &bus->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
u32 gpio = nvkm_rd32(device, 0x001104) & nvkm_rd32(device, 0x001144);
}
}
-static int
-nv31_bus_init(struct nvkm_object *object)
+static void
+nv31_bus_init(struct nvkm_bus *bus)
{
- struct nvkm_bus *bus = (void *)object;
struct nvkm_device *device = bus->subdev.device;
- int ret;
-
- ret = nvkm_bus_init(bus);
- if (ret)
- return ret;
-
nvkm_wr32(device, 0x001100, 0xffffffff);
nvkm_wr32(device, 0x001140, 0x00070008);
- return 0;
}
-struct nvkm_oclass *
-nv31_bus_oclass = &(struct nv04_bus_impl) {
- .base.handle = NV_SUBDEV(BUS, 0x31),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = nv04_bus_ctor,
- .dtor = _nvkm_bus_dtor,
- .init = nv31_bus_init,
- .fini = _nvkm_bus_fini,
- },
+static const struct nvkm_bus_func
+nv31_bus = {
+ .init = nv31_bus_init,
.intr = nv31_bus_intr,
-}.base;
+};
+
+int
+nv31_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus)
+{
+ return nvkm_bus_new_(&nv31_bus, device, index, pbus);
+}
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
-#include "nv04.h"
+#include "priv.h"
#include <subdev/therm.h>
#include <subdev/timer.h>
}
void
-nv50_bus_intr(struct nvkm_subdev *subdev)
+nv50_bus_intr(struct nvkm_bus *bus)
{
+ struct nvkm_subdev *subdev = &bus->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
}
}
-int
-nv50_bus_init(struct nvkm_object *object)
+void
+nv50_bus_init(struct nvkm_bus *bus)
{
- struct nvkm_bus *bus = (void *)object;
struct nvkm_device *device = bus->subdev.device;
- int ret;
-
- ret = nvkm_bus_init(bus);
- if (ret)
- return ret;
-
nvkm_wr32(device, 0x001100, 0xffffffff);
nvkm_wr32(device, 0x001140, 0x00010008);
- return 0;
}
-struct nvkm_oclass *
-nv50_bus_oclass = &(struct nv04_bus_impl) {
- .base.handle = NV_SUBDEV(BUS, 0x50),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = nv04_bus_ctor,
- .dtor = _nvkm_bus_dtor,
- .init = nv50_bus_init,
- .fini = _nvkm_bus_fini,
- },
+static const struct nvkm_bus_func
+nv50_bus = {
+ .init = nv50_bus_init,
.intr = nv50_bus_intr,
.hwsq_exec = nv50_bus_hwsq_exec,
.hwsq_size = 64,
-}.base;
+};
+
+int
+nv50_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus)
+{
+ return nvkm_bus_new_(&nv50_bus, device, index, pbus);
+}
--- /dev/null
+#ifndef __NVKM_BUS_PRIV_H__
+#define __NVKM_BUS_PRIV_H__
+#define nvkm_bus(p) container_of((p), struct nvkm_bus, subdev)
+#include <subdev/bus.h>
+
+struct nvkm_bus_func {
+ void (*init)(struct nvkm_bus *);
+ void (*intr)(struct nvkm_bus *);
+ int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32);
+ u32 hwsq_size;
+};
+
+int nvkm_bus_new_(const struct nvkm_bus_func *, struct nvkm_device *, int,
+ struct nvkm_bus **);
+
+void nv50_bus_init(struct nvkm_bus *);
+void nv50_bus_intr(struct nvkm_bus *);
+#endif
projects / cascardo / linux.git / commitdiff