--- /dev/null
+What: tcp_dma_copybreak sysctl
+Date: Removed in kernel v3.13
+Contact: Dan Williams <dan.j.williams@intel.com>
+Description:
+ Formerly the lower limit, in bytes, of the size of socket reads
+ that will be offloaded to a DMA copy engine. Removed due to
+ coherency issues of the cpu potentially touching the buffers
+ while dma is in flight.
Required properties for iomux controller:
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
+ or "atmel,sama5d3-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
Bits used for CONFIG:
-PULL_UP (1 << 0): indicate this pin need a pull up.
-MULTIDRIVE (1 << 1): indicate this pin need to be configured as multidrive.
-DEGLITCH (1 << 2): indicate this pin need deglitch.
-PULL_DOWN (1 << 3): indicate this pin need a pull down.
-DIS_SCHMIT (1 << 4): indicate this pin need to disable schmit trigger.
-DEBOUNCE (1 << 16): indicate this pin need debounce.
-DEBOUNCE_VAL (0x3fff << 17): debounce val.
+PULL_UP (1 << 0): indicate this pin needs a pull up.
+MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive.
+ Multi-drive is equivalent to open-drain type output.
+DEGLITCH (1 << 2): indicate this pin needs deglitch.
+PULL_DOWN (1 << 3): indicate this pin needs a pull down.
+DIS_SCHMIT (1 << 4): indicate this pin needs to the disable schmitt trigger.
+DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
+ following values:
+ 00 - No change (reset state value kept)
+ 01 - Low
+ 10 - Medium
+ 11 - High
+DEBOUNCE (1 << 16): indicate this pin needs debounce.
+DEBOUNCE_VAL (0x3fff << 17): debounce value.
NOTE:
Some requirements for using atmel,at91rm9200-pinctrl binding:
- reg: Should contain a list of base address and size pairs for:
-- first entry - the drive strength and pad control registers.
-- second entry - the pinmux registers
+ -- third entry - the MIPI_PAD_CTRL register
Tegra124 adds the following optional properties for pin configuration subnodes.
The macros for options are defined in the
dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4.
+ MIPI pad control groups:
+
+ These support only the nvidia,function property.
+
+ dsi_b
+
Valid values for nvidia,functions are:
blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1,
- dp, rtck, sys, clk tmds.
+ dp, rtck, sys, clk tmds, csi, dsi_b
Example:
pinmux: pinmux {
compatible = "nvidia,tegra124-pinmux";
- reg = <0x70000868 0x164 /* Pad control registers */
- 0x70003000 0x434>; /* PinMux registers */
+ reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
+ <0x0 0x70003000 0x0 0x434>, /* Mux registers */
+ <0x0 0x70000820 0x0 0x8>; /* MIPI pad control */
};
Example pinmux entries:
nodes, is again defined entirely by the binding for the individual pin
controller device.
+== Generic pin multiplexing node content ==
+
+pin multiplexing nodes:
+
+function - the mux function to select
+groups - the list of groups to select with this function
+
+Example:
+
+state_0_node_a {
+ function = "uart0";
+ groups = "u0rxtx", "u0rtscts";
+};
+state_1_node_a {
+ function = "spi0";
+ groups = "spi0pins";
+};
+
== Generic pin configuration node content ==
Many data items that are represented in a pin configuration node are common
Supported generic properties are:
pins - the list of pins that properties in the node
- apply to
-function - the mux function to select
+ apply to (either this or "group" has to be
+ specified)
+group - the group to apply the properties to, if the driver
+ supports configuration of whole groups rather than
+ individual pins (either this or "pins" has to be
+ specified)
bias-disable - disable any pin bias
bias-high-impedance - high impedance mode ("third-state", "floating")
bias-bus-hold - latch weakly
output-high - set the pin to output mode with high level
slew-rate - set the slew rate
+For example:
+
+state_0_node_a {
+ pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
+ bias-pull-up;
+};
+state_1_node_a {
+ pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
+ output-high;
+};
+state_2_node_a {
+ group = "foo-group";
+ bias-pull-up;
+};
+
Some of the generic properties take arguments. For those that do, the
arguments are described below.
binding for the hardware defines:
- Whether the entries are integers or strings, and their meaning.
-- function takes a list of function names/IDs as a required argument. The
- specific binding for the hardware defines:
- - Whether the entries are integers or strings, and their meaning.
- - Whether only a single entry is allowed (which is applied to all entries
- in the pins property), or whether there may alternatively be one entry per
- entry in the pins property, in which case the list lengths must match, and
- for each list index i, the function at list index i is applied to the pin
- at list index i.
-
- bias-pull-up, -down and -pin-default take as optional argument on hardware
supporting it the pull strength in Ohm. bias-disable will disable the pull.
gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
- riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic,
+ riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold
Example:
--- /dev/null
+Qualcomm APQ8084 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+MSM8960 platform.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,apq8084-pinctrl"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+ Usage: required
+ Value type: <string-array>
+ Definition: List of gpio pins affected by the properties specified in
+ this subnode. Valid pins are:
+ gpio0-gpio146,
+ sdc1_clk,
+ sdc1_cmd,
+ sdc1_data
+ sdc2_clk,
+ sdc2_cmd,
+ sdc2_data
+
+- function:
+ Usage: required
+ Value type: <string>
+ Definition: Specify the alternative function to be configured for the
+ specified pins. Functions are only valid for gpio pins.
+ Valid values are:
+ adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
+ blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
+ blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
+ blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
+ blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
+ blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3,
+ blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8,
+ blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
+ blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
+ blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
+ blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2,
+ cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
+ cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
+ edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i
+ gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio,
+ hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic,
+ ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst,
+ pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
+ qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
+ sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
+ spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1,
+ tsif2, uim, uim_batt_alarm
+
+- bias-disable:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull up.
+
+- output-high:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ high.
+ Not valid for sdc pins.
+
+- output-low:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ low.
+ Not valid for sdc pins.
+
+- drive-strength:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects the drive strength for the specified pins, in mA.
+ Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+ tlmm: pinctrl@fd510000 {
+ compatible = "qcom,apq8084-pinctrl";
+ reg = <0xfd510000 0x4000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 208 0>;
+
+ uart2: uart2-default {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
+ };
+
+ tx {
+ pins = "gpio4";
+ drive-strength = <4>;
+ bias-disable;
+ };
+
+ rx {
+ pins = "gpio5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
The Rockchip Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
-multiplexing the PAD input/output signals. For each PAD there are up to
-4 muxing options with option 0 being the use as a GPIO.
+multiplexing the PAD input/output signals. For each PAD there are several
+muxing options with option 0 being the use as a GPIO.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
Required properties for pin configuration node:
- rockchip,pins: 3 integers array, represents a group of pins mux and config
setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
- The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
+ The MUX 0 means gpio and MUX 1 to N mean the specific device function.
The phandle of a node containing the generic pinconfig options
to use, as described in pinctrl-bindings.txt in this directory.
--- /dev/null
+OMAP Pinctrl definitions
+
+Required properties:
+- compatible : Should be one of:
+ "ti,omap2420-padconf" - OMAP2420 compatible pinctrl
+ "ti,omap2430-padconf" - OMAP2430 compatible pinctrl
+ "ti,omap3-padconf" - OMAP3 compatible pinctrl
+ "ti,omap4-padconf" - OMAP4 compatible pinctrl
+ "ti,omap5-padconf" - OMAP5 compatible pinctrl
+ "ti,dra7-padconf" - DRA7 compatible pinctrl
+ "ti,am437-padconf" - AM437x compatible pinctrl
+
+See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details.
not receive a window scaling option from them.
Default: 0
-tcp_dma_copybreak - INTEGER
- Lower limit, in bytes, of the size of socket reads that will be
- offloaded to a DMA copy engine, if one is present in the system
- and CONFIG_NET_DMA is enabled.
- Default: 4096
-
tcp_thin_linear_timeouts - BOOLEAN
Enable dynamic triggering of linear timeouts for thin streams.
If set, a check is performed upon retransmission by timeout to
return 0;
}
-int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
+int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
u8 regbit = (1 << selector + group);
return 0;
}
-void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
- unsigned group)
-{
- u8 regbit = (1 << selector + group);
-
- writeb((readb(MUX) & ~(regbit)), MUX)
- return 0;
-}
-
struct pinmux_ops foo_pmxops = {
.get_functions_count = foo_get_functions_count,
.get_function_name = foo_get_fname,
.get_function_groups = foo_get_groups,
- .enable = foo_enable,
- .disable = foo_disable,
+ .set_mux = foo_set_mux,
};
/* Pinmux operations are handled by some pin controller */
ARM/INTEL IOP32X ARM ARCHITECTURE
M: Lennert Buytenhek <kernel@wantstofly.org>
-M: Dan Williams <dan.j.williams@intel.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/INTEL IOP33X ARM ARCHITECTURE
-M: Dan Williams <dan.j.williams@intel.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Maintained
+S: Orphan
ARM/INTEL IOP13XX ARM ARCHITECTURE
M: Lennert Buytenhek <kernel@wantstofly.org>
-M: Dan Williams <dan.j.williams@intel.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/INTEL IQ81342EX MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
-M: Dan Williams <dan.j.williams@intel.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/INTEL XSC3 (MANZANO) ARM CORE
M: Lennert Buytenhek <kernel@wantstofly.org>
-M: Dan Williams <dan.j.williams@intel.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: drivers/platform/x86/eeepc*.c
ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API
-M: Dan Williams <dan.j.williams@intel.com>
+R: Dan Williams <dan.j.williams@intel.com>
W: http://sourceforge.net/projects/xscaleiop
-S: Maintained
+S: Odd fixes
F: Documentation/crypto/async-tx-api.txt
F: crypto/async_tx/
F: drivers/dma/
S: Supported
F: drivers/tty/serial/atmel_serial.c
+ATMEL Audio ALSA driver
+M: Bo Shen <voice.shen@atmel.com>
+L: alsa-devel@alsa-project.org (moderated for non-subscribers)
+S: Supported
+F: sound/soc/atmel
+
ATMEL DMA DRIVER
M: Nicolas Ferre <nicolas.ferre@atmel.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
F: drivers/scsi/bfa/
BROCADE BNA 10 GIGABIT ETHERNET DRIVER
-M: Rasesh Mody <rmody@brocade.com>
+M: Rasesh Mody <rasesh.mody@qlogic.com>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/ethernet/brocade/bna/
DMA GENERIC OFFLOAD ENGINE SUBSYSTEM
M: Vinod Koul <vinod.koul@intel.com>
-M: Dan Williams <dan.j.williams@intel.com>
L: dmaengine@vger.kernel.org
Q: https://patchwork.kernel.org/project/linux-dmaengine/list/
-S: Supported
+S: Maintained
F: drivers/dma/
F: include/linux/dma*
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx.git
T: git git://git.infradead.org/users/vkoul/slave-dma.git (slave-dma)
DME1737 HARDWARE MONITOR DRIVER
F: arch/x86/kernel/cpu/microcode/intel*
INTEL I/OAT DMA DRIVER
-M: Dan Williams <dan.j.williams@intel.com>
M: Dave Jiang <dave.jiang@intel.com>
+R: Dan Williams <dan.j.williams@intel.com>
L: dmaengine@vger.kernel.org
Q: https://patchwork.kernel.org/project/linux-dmaengine/list/
S: Supported
F: include/linux/intel-iommu.h
INTEL IOP-ADMA DMA DRIVER
-M: Dan Williams <dan.j.williams@intel.com>
+R: Dan Williams <dan.j.williams@intel.com>
S: Odd fixes
F: drivers/dma/iop-adma.c
LINUX FOR POWERPC EMBEDDED MPC5XXX
M: Anatolij Gustschin <agust@denx.de>
L: linuxppc-dev@lists.ozlabs.org
-T: git git://git.denx.de/linux-2.6-agust.git
+T: git git://git.denx.de/linux-denx-agust.git
S: Maintained
F: arch/powerpc/platforms/512x/
F: arch/powerpc/platforms/52xx/
VERSION = 3
PATCHLEVEL = 17
SUBLEVEL = 0
-EXTRAVERSION = -rc7
+EXTRAVERSION =
NAME = Shuffling Zombie Juror
# *DOCUMENTATION*
endif # INSTALL_MOD_STRIP
export mod_strip_cmd
+# CONFIG_MODULE_COMPRESS, if defined, will cause module to be compressed
+# after they are installed in agreement with CONFIG_MODULE_COMPRESS_GZIP
+# or CONFIG_MODULE_COMPRESS_XZ.
+
+mod_compress_cmd = true
+ifdef CONFIG_MODULE_COMPRESS
+ ifdef CONFIG_MODULE_COMPRESS_GZIP
+ mod_compress_cmd = gzip -n
+ endif # CONFIG_MODULE_COMPRESS_GZIP
+ ifdef CONFIG_MODULE_COMPRESS_XZ
+ mod_compress_cmd = xz
+ endif # CONFIG_MODULE_COMPRESS_XZ
+endif # CONFIG_MODULE_COMPRESS
+export mod_compress_cmd
+
# Select initial ramdisk compression format, default is gzip(1).
# This shall be used by the dracut(8) tool while creating an initramfs image.
#
*/
#define v7_exit_coherency_flush(level) \
asm volatile( \
+ ".arch armv7-a \n\t" \
"stmfd sp!, {fp, ip} \n\t" \
"mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \
"bic r0, r0, #"__stringify(CR_C)" \n\t" \
asm("mcr p15, 0, %0, c13, c0, 3"
: : "r" (val));
} else {
+#ifdef CONFIG_KUSER_HELPERS
/*
* User space must never try to access this
* directly. Expect your app to break
* entry-armv.S for details)
*/
*((unsigned int *)0xffff0ff0) = val;
+#endif
}
}
*
* @ TESTCASE_START
* bl __kprobes_test_case_start
- * @ start of inline data...
+ * .pushsection .rodata
+ * "10:
* .ascii "mov r0, r7" @ text title for test case
* .byte 0
- * .align 2, 0
+ * .popsection
+ * @ start of inline data...
+ * .word 10b @ pointer to title in .rodata section
*
* @ TEST_ARG_REG
* .byte ARG_TYPE_REG
__asm__ __volatile__ (
"stmdb sp!, {r4-r11} \n\t"
"sub sp, sp, #"__stringify(TEST_MEMORY_SIZE)"\n\t"
- "bic r0, lr, #1 @ r0 = inline title string \n\t"
+ "bic r0, lr, #1 @ r0 = inline data \n\t"
"mov r1, sp \n\t"
"bl kprobes_test_case_start \n\t"
"bx r0 \n\t"
return pc + 4;
}
-static uintptr_t __used kprobes_test_case_start(const char *title, void *stack)
+static uintptr_t __used kprobes_test_case_start(const char **title, void *stack)
{
struct test_arg *args;
struct test_arg_end *end_arg;
unsigned long test_code;
- args = (struct test_arg *)PTR_ALIGN(title + strlen(title) + 1, 4);
-
- current_title = title;
+ current_title = *title++;
+ args = (struct test_arg *)title;
current_args = args;
current_stack = stack;
#define TESTCASE_START(title) \
__asm__ __volatile__ ( \
"bl __kprobes_test_case_start \n\t" \
+ ".pushsection .rodata \n\t" \
+ "10: \n\t" \
/* don't use .asciz here as 'title' may be */ \
/* multiple strings to be concatenated. */ \
".ascii "#title" \n\t" \
".byte 0 \n\t" \
- ".align 2, 0 \n\t"
+ ".popsection \n\t" \
+ ".word 10b \n\t"
#define TEST_ARG_REG(reg, val) \
".byte "__stringify(ARG_TYPE_REG)" \n\t" \
#define ABCDSR_PERIPH_C 0x2
#define ABCDSR_PERIPH_D 0x3
+#define SAMA5D3_PIO_DRIVER1 0x118 /*PIO Driver 1 register offset*/
+#define SAMA5D3_PIO_DRIVER2 0x11C /*PIO Driver 2 register offset*/
+
+#define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
+#define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
+
#endif
* This code is not portable to processors with late data abort handling.
*/
#define CODING_BITS(i) (i & 0x0e000000)
+#define COND_BITS(i) (i & 0xf0000000)
#define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
#define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
break;
case 0x04000000: /* ldr or str immediate */
+ if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */
+ goto bad;
offset.un = OFFSET_BITS(instr);
handler = do_alignment_ldrstr;
break;
* TFR EV X F IHD LR S
* .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM
* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
- * 11 0 110 1 0011 1100 .111 1101 < we want
+ * 11 0 110 0 0011 1100 .111 1101 < we want
*/
.align 2
.type v7_crval, #object
v7_crval:
- crval clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c
+ crval clear=0x0122c302, mmuset=0x30c03c7d, ucset=0x00c01c7c
select HAVE_ACPI_APEI if ACPI
select HAVE_ACPI_APEI_NMI if ACPI
select ACPI_LEGACY_TABLES_LOOKUP if ACPI
+ select X86_FEATURE_NAMES if PROC_FS
config INSTRUCTION_DECODER
def_bool y
If you don't know what to do here, say N.
+config X86_FEATURE_NAMES
+ bool "Processor feature human-readable names" if EMBEDDED
+ default y
+ ---help---
+ This option compiles in a table of x86 feature bits and corresponding
+ names. This is required to support /proc/cpuinfo and a few kernel
+ messages. You can disable this to save space, at the expense of
+ making those few kernel messages show numeric feature bits instead.
+
+ If in doubt, say Y.
+
config X86_X2APIC
bool "Support x2apic"
depends on X86_LOCAL_APIC && X86_64 && IRQ_REMAP
$(Q)$(MAKE) $(clean)=arch/x86/tools
$(Q)$(MAKE) $(clean)=arch/x86/purgatory
-PHONY += kvmconfig
-kvmconfig:
- $(if $(wildcard $(objtree)/.config),, $(error You need an existing .config for this target))
- $(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh -m -O $(objtree) $(objtree)/.config $(srctree)/arch/x86/configs/kvm_guest.config
- $(Q)yes "" | $(MAKE) -f $(srctree)/Makefile oldconfig
-
define archhelp
echo '* bzImage - Compressed kernel image (arch/x86/boot/bzImage)'
echo ' install - Install kernel using'
echo ' bzdisk/fdimage*/isoimage also accept:'
echo ' FDARGS="..." arguments for the booted kernel'
echo ' FDINITRD=file initrd for the booted kernel'
- echo ' kvmconfig - Enable additional options for guest kernel support'
endef
setup-y += video-bios.o
targets += $(setup-y)
-hostprogs-y := mkcpustr tools/build
+hostprogs-y := tools/build
+hostprogs-$(CONFIG_X86_FEATURE_NAMES) += mkcpustr
HOST_EXTRACFLAGS += -I$(srctree)/tools/include \
-include include/generated/autoconf.h \
-D__EXPORTED_HEADERS__
+ifdef CONFIG_X86_FEATURE_NAMES
$(obj)/cpu.o: $(obj)/cpustr.h
quiet_cmd_cpustr = CPUSTR $@
cmd_cpustr = $(obj)/mkcpustr > $@
-targets += cpustr.h
+targets += cpustr.h
$(obj)/cpustr.h: $(obj)/mkcpustr FORCE
$(call if_changed,cpustr)
+endif
# ---------------------------------------------------------------------------
hostprogs-y := mkpiggy
HOST_EXTRACFLAGS += -I$(srctree)/tools/include
-VMLINUX_OBJS = $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \
- $(obj)/string.o $(obj)/cmdline.o $(obj)/early_serial_console.o \
- $(obj)/piggy.o $(obj)/cpuflags.o $(obj)/aslr.o
+vmlinux-objs-y := $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \
+ $(obj)/string.o $(obj)/cmdline.o \
+ $(obj)/piggy.o $(obj)/cpuflags.o
+
+vmlinux-objs-$(CONFIG_EARLY_PRINTK) += $(obj)/early_serial_console.o
+vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/aslr.o
$(obj)/eboot.o: KBUILD_CFLAGS += -fshort-wchar -mno-red-zone
-ifeq ($(CONFIG_EFI_STUB), y)
- VMLINUX_OBJS += $(obj)/eboot.o $(obj)/efi_stub_$(BITS).o
-endif
+vmlinux-objs-$(CONFIG_EFI_STUB) += $(obj)/eboot.o $(obj)/efi_stub_$(BITS).o
-$(obj)/vmlinux: $(VMLINUX_OBJS) FORCE
+$(obj)/vmlinux: $(vmlinux-objs-y) FORCE
$(call if_changed,ld)
@:
$(obj)/vmlinux.bin: vmlinux FORCE
$(call if_changed,objcopy)
-targets += $(patsubst $(obj)/%,%,$(VMLINUX_OBJS)) vmlinux.bin.all vmlinux.relocs
+targets += $(patsubst $(obj)/%,%,$(vmlinux-objs-y)) vmlinux.bin.all vmlinux.relocs
CMD_RELOCS = arch/x86/tools/relocs
quiet_cmd_relocs = RELOCS $@
#include "misc.h"
-#ifdef CONFIG_RANDOMIZE_BASE
#include <asm/msr.h>
#include <asm/archrandom.h>
#include <asm/e820.h>
out:
return (unsigned char *)choice;
}
-
-#endif /* CONFIG_RANDOMIZE_BASE */
#include "misc.h"
-#ifdef CONFIG_EARLY_PRINTK
-
int early_serial_base;
#include "../early_serial_console.c"
-
-#endif
*/
#include "boot.h"
+#ifdef CONFIG_X86_FEATURE_NAMES
#include "cpustr.h"
+#endif
static char *cpu_name(int level)
{
}
}
+static void show_cap_strs(u32 *err_flags)
+{
+ int i, j;
+#ifdef CONFIG_X86_FEATURE_NAMES
+ const unsigned char *msg_strs = (const unsigned char *)x86_cap_strs;
+ for (i = 0; i < NCAPINTS; i++) {
+ u32 e = err_flags[i];
+ for (j = 0; j < 32; j++) {
+ if (msg_strs[0] < i ||
+ (msg_strs[0] == i && msg_strs[1] < j)) {
+ /* Skip to the next string */
+ msg_strs += 2;
+ while (*msg_strs++)
+ ;
+ }
+ if (e & 1) {
+ if (msg_strs[0] == i &&
+ msg_strs[1] == j &&
+ msg_strs[2])
+ printf("%s ", msg_strs+2);
+ else
+ printf("%d:%d ", i, j);
+ }
+ e >>= 1;
+ }
+ }
+#else
+ for (i = 0; i < NCAPINTS; i++) {
+ u32 e = err_flags[i];
+ for (j = 0; j < 32; j++) {
+ if (e & 1)
+ printf("%d:%d ", i, j);
+ e >>= 1;
+ }
+ }
+#endif
+}
+
int validate_cpu(void)
{
u32 *err_flags;
int cpu_level, req_level;
- const unsigned char *msg_strs;
check_cpu(&cpu_level, &req_level, &err_flags);
}
if (err_flags) {
- int i, j;
puts("This kernel requires the following features "
"not present on the CPU:\n");
-
- msg_strs = (const unsigned char *)x86_cap_strs;
-
- for (i = 0; i < NCAPINTS; i++) {
- u32 e = err_flags[i];
-
- for (j = 0; j < 32; j++) {
- if (msg_strs[0] < i ||
- (msg_strs[0] == i && msg_strs[1] < j)) {
- /* Skip to the next string */
- msg_strs += 2;
- while (*msg_strs++)
- ;
- }
- if (e & 1) {
- if (msg_strs[0] == i &&
- msg_strs[1] == j &&
- msg_strs[2])
- printf("%s ", msg_strs+2);
- else
- printf("%d:%d ", i, j);
- }
- e >>= 1;
- }
- }
+ show_cap_strs(err_flags);
putchar('\n');
return -1;
} else {
--- /dev/null
+CONFIG_NOHIGHMEM=y
#include <asm/asm.h>
#include <linux/bitops.h>
+#ifdef CONFIG_X86_FEATURE_NAMES
extern const char * const x86_cap_flags[NCAPINTS*32];
extern const char * const x86_power_flags[32];
+#define X86_CAP_FMT "%s"
+#define x86_cap_flag(flag) x86_cap_flags[flag]
+#else
+#define X86_CAP_FMT "%d:%d"
+#define x86_cap_flag(flag) ((flag) >> 5), ((flag) & 31)
+#endif
/*
* In order to save room, we index into this array by doing
CFLAGS_common.o := $(nostackp)
obj-y := intel_cacheinfo.o scattered.o topology.o
-obj-y += proc.o capflags.o powerflags.o common.o
+obj-y += common.o
obj-y += rdrand.o
obj-y += match.o
+obj-$(CONFIG_PROC_FS) += proc.o
+obj-$(CONFIG_X86_FEATURE_NAMES) += capflags.o powerflags.o
+
obj-$(CONFIG_X86_32) += bugs.o
obj-$(CONFIG_X86_64) += bugs_64.o
obj-$(CONFIG_HYPERVISOR_GUEST) += vmware.o hypervisor.o mshyperv.o
+ifdef CONFIG_X86_FEATURE_NAMES
quiet_cmd_mkcapflags = MKCAP $@
cmd_mkcapflags = $(CONFIG_SHELL) $(srctree)/$(src)/mkcapflags.sh $< $@
targets += capflags.c
$(obj)/capflags.c: $(cpufeature) $(src)/mkcapflags.sh FORCE
$(call if_changed,mkcapflags)
+endif
continue;
printk(KERN_WARNING
- "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
- x86_cap_flags[df->feature], df->level);
+ "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
+ x86_cap_flag(df->feature), df->level);
}
}
tx = dma->device_prep_dma_xor(chan, dma_dest, src_list,
xor_src_cnt, unmap->len,
dma_flags);
- src_list[0] = tmp;
-
if (unlikely(!tx))
async_tx_quiesce(&submit->depend_tx);
xor_src_cnt, unmap->len,
dma_flags);
}
+ src_list[0] = tmp;
dma_set_unmap(tx, unmap);
async_tx_submit(chan, tx, submit);
= IPMI_CHANNEL_MEDIUM_IPMB;
intf->channels[0].protocol
= IPMI_CHANNEL_PROTOCOL_IPMB;
- rv = -ENOSYS;
intf->curr_channel = IPMI_MAX_CHANNELS;
wake_up(&intf->waitq);
if (rv) {
/* Got an error somehow, just give up. */
+ printk(KERN_WARNING PFX
+ "Error sending channel information for channel"
+ " %d: %d\n", intf->curr_channel, rv);
+
intf->curr_channel = IPMI_MAX_CHANNELS;
wake_up(&intf->waitq);
-
- printk(KERN_WARNING PFX
- "Error sending channel information: %d\n",
- rv);
}
}
out:
intf->null_user_handler = channel_handler;
intf->curr_channel = 0;
rv = send_channel_info_cmd(intf, 0);
- if (rv)
+ if (rv) {
+ printk(KERN_WARNING PFX
+ "Error sending channel information for channel"
+ " 0, %d\n", rv);
goto out;
+ }
/* Wait for the channel info to be read. */
wait_event(intf->waitq,
return ts->tv_nsec != -1;
}
-static int ipmi_thread_busy_wait(enum si_sm_result smi_result,
- const struct smi_info *smi_info,
- struct timespec *busy_until)
+static inline int ipmi_thread_busy_wait(enum si_sm_result smi_result,
+ const struct smi_info *smi_info,
+ struct timespec *busy_until)
{
unsigned int max_busy_us = 0;
if (!match)
return -EINVAL;
+ if (!of_device_is_available(np))
+ return -EINVAL;
+
ret = of_address_to_resource(np, 0, &resource);
if (ret) {
dev_warn(&dev->dev, PFX "invalid address from OF\n");
if (!to_clean)
return;
+ if (to_clean->dev)
+ dev_set_drvdata(to_clean->dev, NULL);
+
list_del(&to_clean->link);
/* Tell the driver that we are shutting down. */
if (!cpufreq_driver)
return;
- cpufreq_suspended = true;
-
if (!has_target())
- return;
+ goto suspend;
pr_debug("%s: Suspending Governors\n", __func__);
pr_err("%s: Failed to suspend driver: %p\n", __func__,
policy);
}
+
+suspend:
+ cpufreq_suspended = true;
}
/**
return cpufreq_register_driver(&integrator_driver);
}
-static void __exit integrator_cpufreq_remove(struct platform_device *pdev)
+static int __exit integrator_cpufreq_remove(struct platform_device *pdev)
{
- cpufreq_unregister_driver(&integrator_driver);
+ return cpufreq_unregister_driver(&integrator_driver);
}
static const struct of_device_id integrator_cpufreq_match[] = {
u32 input_buffer;
int cpu;
- spin_lock(&pcc_lock);
cpu = policy->cpu;
pcc_cpu_data = per_cpu_ptr(pcc_cpu_info, cpu);
freqs.old = policy->cur;
freqs.new = target_freq;
cpufreq_freq_transition_begin(policy, &freqs);
+ spin_lock(&pcc_lock);
input_buffer = 0x1 | (((target_freq * 100)
/ (ioread32(&pcch_hdr->nominal) * 1000)) << 8);
comment "DMA Clients"
depends on DMA_ENGINE
-config NET_DMA
- bool "Network: TCP receive copy offload"
- depends on DMA_ENGINE && NET
- default (INTEL_IOATDMA || FSL_DMA)
- depends on BROKEN
- help
- This enables the use of DMA engines in the network stack to
- offload receive copy-to-user operations, freeing CPU cycles.
-
- Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
- say N.
-
config ASYNC_TX_DMA
bool "Async_tx: Offload support for the async_tx api"
depends on DMA_ENGINE
obj-$(CONFIG_DMA_ACPI) += acpi-dma.o
obj-$(CONFIG_DMA_OF) += of-dma.o
-obj-$(CONFIG_NET_DMA) += iovlock.o
obj-$(CONFIG_INTEL_MID_DMAC) += intel_mid_dma.o
obj-$(CONFIG_DMATEST) += dmatest.o
obj-$(CONFIG_INTEL_IOATDMA) += ioat/
}
EXPORT_SYMBOL(dmaengine_get_unmap_data);
-/**
- * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
- * @chan: DMA channel to offload copy to
- * @dest_pg: destination page
- * @dest_off: offset in page to copy to
- * @src_pg: source page
- * @src_off: offset in page to copy from
- * @len: length
- *
- * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
- * address according to the DMA mapping API rules for streaming mappings.
- * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
- * (kernel memory or locked user space pages).
- */
-dma_cookie_t
-dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
- unsigned int dest_off, struct page *src_pg, unsigned int src_off,
- size_t len)
-{
- struct dma_device *dev = chan->device;
- struct dma_async_tx_descriptor *tx;
- struct dmaengine_unmap_data *unmap;
- dma_cookie_t cookie;
- unsigned long flags;
-
- unmap = dmaengine_get_unmap_data(dev->dev, 2, GFP_NOWAIT);
- if (!unmap)
- return -ENOMEM;
-
- unmap->to_cnt = 1;
- unmap->from_cnt = 1;
- unmap->addr[0] = dma_map_page(dev->dev, src_pg, src_off, len,
- DMA_TO_DEVICE);
- unmap->addr[1] = dma_map_page(dev->dev, dest_pg, dest_off, len,
- DMA_FROM_DEVICE);
- unmap->len = len;
- flags = DMA_CTRL_ACK;
- tx = dev->device_prep_dma_memcpy(chan, unmap->addr[1], unmap->addr[0],
- len, flags);
-
- if (!tx) {
- dmaengine_unmap_put(unmap);
- return -ENOMEM;
- }
-
- dma_set_unmap(tx, unmap);
- cookie = tx->tx_submit(tx);
- dmaengine_unmap_put(unmap);
-
- preempt_disable();
- __this_cpu_add(chan->local->bytes_transferred, len);
- __this_cpu_inc(chan->local->memcpy_count);
- preempt_enable();
-
- return cookie;
-}
-EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
-
-/**
- * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
- * @chan: DMA channel to offload copy to
- * @dest: destination address (virtual)
- * @src: source address (virtual)
- * @len: length
- *
- * Both @dest and @src must be mappable to a bus address according to the
- * DMA mapping API rules for streaming mappings.
- * Both @dest and @src must stay memory resident (kernel memory or locked
- * user space pages).
- */
-dma_cookie_t
-dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
- void *src, size_t len)
-{
- return dma_async_memcpy_pg_to_pg(chan, virt_to_page(dest),
- (unsigned long) dest & ~PAGE_MASK,
- virt_to_page(src),
- (unsigned long) src & ~PAGE_MASK, len);
-}
-EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
-
-/**
- * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
- * @chan: DMA channel to offload copy to
- * @page: destination page
- * @offset: offset in page to copy to
- * @kdata: source address (virtual)
- * @len: length
- *
- * Both @page/@offset and @kdata must be mappable to a bus address according
- * to the DMA mapping API rules for streaming mappings.
- * Both @page/@offset and @kdata must stay memory resident (kernel memory or
- * locked user space pages)
- */
-dma_cookie_t
-dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
- unsigned int offset, void *kdata, size_t len)
-{
- return dma_async_memcpy_pg_to_pg(chan, page, offset,
- virt_to_page(kdata),
- (unsigned long) kdata & ~PAGE_MASK, len);
-}
-EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
-
void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
struct dma_chan *chan)
{
runtime = ktime_us_delta(ktime_get(), ktime);
ret = 0;
+err_dstbuf:
for (i = 0; thread->dsts[i]; i++)
kfree(thread->dsts[i]);
-err_dstbuf:
kfree(thread->dsts);
err_dsts:
+err_srcbuf:
for (i = 0; thread->srcs[i]; i++)
kfree(thread->srcs[i]);
-err_srcbuf:
kfree(thread->srcs);
err_srcs:
kfree(pq_coefs);
#include "dma.h"
#include "registers.h"
+#include "dma_v2.h"
/*
* Bit 7 of a tag map entry is the "valid" bit, if it is set then bits 0:6
u16 id;
/* This implementation only supports PCI-Express */
- if (dev->bus != &pci_bus_type)
+ if (!dev_is_pci(dev))
return -ENODEV;
pdev = to_pci_dev(dev);
id = dcaid_from_pcidev(pdev);
int i;
/* This implementation only supports PCI-Express */
- if (dev->bus != &pci_bus_type)
+ if (!dev_is_pci(dev))
return -ENODEV;
pdev = to_pci_dev(dev);
u16 global_req_table;
/* This implementation only supports PCI-Express */
- if (dev->bus != &pci_bus_type)
+ if (!dev_is_pci(dev))
return -ENODEV;
pdev = to_pci_dev(dev);
id = dcaid_from_pcidev(pdev);
u16 global_req_table;
/* This implementation only supports PCI-Express */
- if (dev->bus != &pci_bus_type)
+ if (!dev_is_pci(dev))
return -ENODEV;
pdev = to_pci_dev(dev);
u16 global_req_table;
/* This implementation only supports PCI-Express */
- if (dev->bus != &pci_bus_type)
+ if (!dev_is_pci(dev))
return -ENODEV;
pdev = to_pci_dev(dev);
id = dcaid_from_pcidev(pdev);
u16 global_req_table;
/* This implementation only supports PCI-Express */
- if (dev->bus != &pci_bus_type)
+ if (!dev_is_pci(dev))
return -ENODEV;
pdev = to_pci_dev(dev);
for (i = 0; i < msixcnt; i++)
device->msix_entries[i].entry = i;
- err = pci_enable_msix(pdev, device->msix_entries, msixcnt);
+ err = pci_enable_msix_exact(pdev, device->msix_entries, msixcnt);
if (err)
goto msi;
err = ioat_probe(device);
if (err)
return err;
- ioat_set_tcp_copy_break(4096);
err = ioat_register(device);
if (err)
return err;
#define dump_desc_dbg(c, d) \
({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })
-static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
-{
- #ifdef CONFIG_NET_DMA
- sysctl_tcp_dma_copybreak = copybreak;
- #endif
-}
-
static inline struct ioat_chan_common *
ioat_chan_by_index(struct ioatdma_device *device, int index)
{
* called under bh_disabled so we need to trigger the timer
* event directly
*/
- if (jiffies > chan->timer.expires && timer_pending(&chan->timer)) {
+ if (time_is_before_jiffies(chan->timer.expires)
+ && timer_pending(&chan->timer)) {
struct ioatdma_device *device = chan->device;
mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
err = ioat_probe(device);
if (err)
return err;
- ioat_set_tcp_copy_break(2048);
list_for_each_entry(c, &dma->channels, device_node) {
chan = to_chan_common(c);
return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags);
}
-struct dma_async_tx_descriptor *
+static struct dma_async_tx_descriptor *
ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
unsigned int src_cnt, size_t len,
enum sum_check_flags *result, unsigned long flags)
}
}
-struct dma_async_tx_descriptor *
+static struct dma_async_tx_descriptor *
ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
unsigned int src_cnt, const unsigned char *scf, size_t len,
enum sum_check_flags *pqres, unsigned long flags)
flags);
}
-struct dma_async_tx_descriptor *
+static struct dma_async_tx_descriptor *
ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src,
unsigned int src_cnt, size_t len,
enum sum_check_flags *result, unsigned long flags)
err = ioat_probe(device);
if (err)
return err;
- ioat_set_tcp_copy_break(262144);
list_for_each_entry(c, &dma->channels, device_node) {
chan = to_chan_common(c);
+++ /dev/null
-/*
- * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
- * Portions based on net/core/datagram.c and copyrighted by their authors.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59
- * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * The full GNU General Public License is included in this distribution in the
- * file called COPYING.
- */
-
-/*
- * This code allows the net stack to make use of a DMA engine for
- * skb to iovec copies.
- */
-
-#include <linux/dmaengine.h>
-#include <linux/pagemap.h>
-#include <linux/slab.h>
-#include <net/tcp.h> /* for memcpy_toiovec */
-#include <asm/io.h>
-#include <asm/uaccess.h>
-
-static int num_pages_spanned(struct iovec *iov)
-{
- return
- ((PAGE_ALIGN((unsigned long)iov->iov_base + iov->iov_len) -
- ((unsigned long)iov->iov_base & PAGE_MASK)) >> PAGE_SHIFT);
-}
-
-/*
- * Pin down all the iovec pages needed for len bytes.
- * Return a struct dma_pinned_list to keep track of pages pinned down.
- *
- * We are allocating a single chunk of memory, and then carving it up into
- * 3 sections, the latter 2 whose size depends on the number of iovecs and the
- * total number of pages, respectively.
- */
-struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len)
-{
- struct dma_pinned_list *local_list;
- struct page **pages;
- int i;
- int ret;
- int nr_iovecs = 0;
- int iovec_len_used = 0;
- int iovec_pages_used = 0;
-
- /* don't pin down non-user-based iovecs */
- if (segment_eq(get_fs(), KERNEL_DS))
- return NULL;
-
- /* determine how many iovecs/pages there are, up front */
- do {
- iovec_len_used += iov[nr_iovecs].iov_len;
- iovec_pages_used += num_pages_spanned(&iov[nr_iovecs]);
- nr_iovecs++;
- } while (iovec_len_used < len);
-
- /* single kmalloc for pinned list, page_list[], and the page arrays */
- local_list = kmalloc(sizeof(*local_list)
- + (nr_iovecs * sizeof (struct dma_page_list))
- + (iovec_pages_used * sizeof (struct page*)), GFP_KERNEL);
- if (!local_list)
- goto out;
-
- /* list of pages starts right after the page list array */
- pages = (struct page **) &local_list->page_list[nr_iovecs];
-
- local_list->nr_iovecs = 0;
-
- for (i = 0; i < nr_iovecs; i++) {
- struct dma_page_list *page_list = &local_list->page_list[i];
-
- len -= iov[i].iov_len;
-
- if (!access_ok(VERIFY_WRITE, iov[i].iov_base, iov[i].iov_len))
- goto unpin;
-
- page_list->nr_pages = num_pages_spanned(&iov[i]);
- page_list->base_address = iov[i].iov_base;
-
- page_list->pages = pages;
- pages += page_list->nr_pages;
-
- /* pin pages down */
- down_read(¤t->mm->mmap_sem);
- ret = get_user_pages(
- current,
- current->mm,
- (unsigned long) iov[i].iov_base,
- page_list->nr_pages,
- 1, /* write */
- 0, /* force */
- page_list->pages,
- NULL);
- up_read(¤t->mm->mmap_sem);
-
- if (ret != page_list->nr_pages)
- goto unpin;
-
- local_list->nr_iovecs = i + 1;
- }
-
- return local_list;
-
-unpin:
- dma_unpin_iovec_pages(local_list);
-out:
- return NULL;
-}
-
-void dma_unpin_iovec_pages(struct dma_pinned_list *pinned_list)
-{
- int i, j;
-
- if (!pinned_list)
- return;
-
- for (i = 0; i < pinned_list->nr_iovecs; i++) {
- struct dma_page_list *page_list = &pinned_list->page_list[i];
- for (j = 0; j < page_list->nr_pages; j++) {
- set_page_dirty_lock(page_list->pages[j]);
- page_cache_release(page_list->pages[j]);
- }
- }
-
- kfree(pinned_list);
-}
-
-
-/*
- * We have already pinned down the pages we will be using in the iovecs.
- * Each entry in iov array has corresponding entry in pinned_list->page_list.
- * Using array indexing to keep iov[] and page_list[] in sync.
- * Initial elements in iov array's iov->iov_len will be 0 if already copied into
- * by another call.
- * iov array length remaining guaranteed to be bigger than len.
- */
-dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
- struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len)
-{
- int iov_byte_offset;
- int copy;
- dma_cookie_t dma_cookie = 0;
- int iovec_idx;
- int page_idx;
-
- if (!chan)
- return memcpy_toiovec(iov, kdata, len);
-
- iovec_idx = 0;
- while (iovec_idx < pinned_list->nr_iovecs) {
- struct dma_page_list *page_list;
-
- /* skip already used-up iovecs */
- while (!iov[iovec_idx].iov_len)
- iovec_idx++;
-
- page_list = &pinned_list->page_list[iovec_idx];
-
- iov_byte_offset = ((unsigned long)iov[iovec_idx].iov_base & ~PAGE_MASK);
- page_idx = (((unsigned long)iov[iovec_idx].iov_base & PAGE_MASK)
- - ((unsigned long)page_list->base_address & PAGE_MASK)) >> PAGE_SHIFT;
-
- /* break up copies to not cross page boundary */
- while (iov[iovec_idx].iov_len) {
- copy = min_t(int, PAGE_SIZE - iov_byte_offset, len);
- copy = min_t(int, copy, iov[iovec_idx].iov_len);
-
- dma_cookie = dma_async_memcpy_buf_to_pg(chan,
- page_list->pages[page_idx],
- iov_byte_offset,
- kdata,
- copy);
- /* poll for a descriptor slot */
- if (unlikely(dma_cookie < 0)) {
- dma_async_issue_pending(chan);
- continue;
- }
-
- len -= copy;
- iov[iovec_idx].iov_len -= copy;
- iov[iovec_idx].iov_base += copy;
-
- if (!len)
- return dma_cookie;
-
- kdata += copy;
- iov_byte_offset = 0;
- page_idx++;
- }
- iovec_idx++;
- }
-
- /* really bad if we ever run out of iovecs */
- BUG();
- return -EFAULT;
-}
-
-dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
- struct dma_pinned_list *pinned_list, struct page *page,
- unsigned int offset, size_t len)
-{
- int iov_byte_offset;
- int copy;
- dma_cookie_t dma_cookie = 0;
- int iovec_idx;
- int page_idx;
- int err;
-
- /* this needs as-yet-unimplemented buf-to-buff, so punt. */
- /* TODO: use dma for this */
- if (!chan || !pinned_list) {
- u8 *vaddr = kmap(page);
- err = memcpy_toiovec(iov, vaddr + offset, len);
- kunmap(page);
- return err;
- }
-
- iovec_idx = 0;
- while (iovec_idx < pinned_list->nr_iovecs) {
- struct dma_page_list *page_list;
-
- /* skip already used-up iovecs */
- while (!iov[iovec_idx].iov_len)
- iovec_idx++;
-
- page_list = &pinned_list->page_list[iovec_idx];
-
- iov_byte_offset = ((unsigned long)iov[iovec_idx].iov_base & ~PAGE_MASK);
- page_idx = (((unsigned long)iov[iovec_idx].iov_base & PAGE_MASK)
- - ((unsigned long)page_list->base_address & PAGE_MASK)) >> PAGE_SHIFT;
-
- /* break up copies to not cross page boundary */
- while (iov[iovec_idx].iov_len) {
- copy = min_t(int, PAGE_SIZE - iov_byte_offset, len);
- copy = min_t(int, copy, iov[iovec_idx].iov_len);
-
- dma_cookie = dma_async_memcpy_pg_to_pg(chan,
- page_list->pages[page_idx],
- iov_byte_offset,
- page,
- offset,
- copy);
- /* poll for a descriptor slot */
- if (unlikely(dma_cookie < 0)) {
- dma_async_issue_pending(chan);
- continue;
- }
-
- len -= copy;
- iov[iovec_idx].iov_len -= copy;
- iov[iovec_idx].iov_base += copy;
-
- if (!len)
- return dma_cookie;
-
- offset += copy;
- iov_byte_offset = 0;
- page_idx++;
- }
- iovec_idx++;
- }
-
- /* really bad if we ever run out of iovecs */
- BUG();
- return -EFAULT;
-}
return 0;
}
-static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
+/* This function must be called with the mv_xor_chan spinlock held */
+static void mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
{
struct mv_xor_desc_slot *iter, *_iter;
dma_cookie_t cookie = 0;
mv_chan->dmachan.completed_cookie = cookie;
}
-static void
-mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
-{
- spin_lock_bh(&mv_chan->lock);
- __mv_xor_slot_cleanup(mv_chan);
- spin_unlock_bh(&mv_chan->lock);
-}
-
static void mv_xor_tasklet(unsigned long data)
{
struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
+
+ spin_lock_bh(&chan->lock);
mv_xor_slot_cleanup(chan);
+ spin_unlock_bh(&chan->lock);
}
static struct mv_xor_desc_slot *
struct mv_xor_desc_slot *iter, *_iter;
int in_use_descs = 0;
+ spin_lock_bh(&mv_chan->lock);
+
mv_xor_slot_cleanup(mv_chan);
- spin_lock_bh(&mv_chan->lock);
list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
chain_node) {
in_use_descs++;
enum dma_status ret;
ret = dma_cookie_status(chan, cookie, txstate);
- if (ret == DMA_COMPLETE) {
- mv_xor_clean_completed_slots(mv_chan);
+ if (ret == DMA_COMPLETE)
return ret;
- }
+
+ spin_lock_bh(&mv_chan->lock);
mv_xor_slot_cleanup(mv_chan);
+ spin_unlock_bh(&mv_chan->lock);
return dma_cookie_status(chan, cookie, txstate);
}
static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan)
{
- int i;
+ int i, ret;
void *src, *dest;
dma_addr_t src_dma, dest_dma;
struct dma_chan *dma_chan;
src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0,
PAGE_SIZE, DMA_TO_DEVICE);
- unmap->to_cnt = 1;
unmap->addr[0] = src_dma;
+ ret = dma_mapping_error(dma_chan->device->dev, src_dma);
+ if (ret) {
+ err = -ENOMEM;
+ goto free_resources;
+ }
+ unmap->to_cnt = 1;
+
dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0,
PAGE_SIZE, DMA_FROM_DEVICE);
- unmap->from_cnt = 1;
unmap->addr[1] = dest_dma;
+ ret = dma_mapping_error(dma_chan->device->dev, dest_dma);
+ if (ret) {
+ err = -ENOMEM;
+ goto free_resources;
+ }
+ unmap->from_cnt = 1;
unmap->len = PAGE_SIZE;
tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
PAGE_SIZE, 0);
+ if (!tx) {
+ dev_err(dma_chan->device->dev,
+ "Self-test cannot prepare operation, disabling\n");
+ err = -ENODEV;
+ goto free_resources;
+ }
+
cookie = mv_xor_tx_submit(tx);
+ if (dma_submit_error(cookie)) {
+ dev_err(dma_chan->device->dev,
+ "Self-test submit error, disabling\n");
+ err = -ENODEV;
+ goto free_resources;
+ }
+
mv_xor_issue_pending(dma_chan);
async_tx_ack(tx);
msleep(1);
static int
mv_xor_xor_self_test(struct mv_xor_chan *mv_chan)
{
- int i, src_idx;
+ int i, src_idx, ret;
struct page *dest;
struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
0, PAGE_SIZE, DMA_TO_DEVICE);
dma_srcs[i] = unmap->addr[i];
+ ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]);
+ if (ret) {
+ err = -ENOMEM;
+ goto free_resources;
+ }
unmap->to_cnt++;
}
unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
DMA_FROM_DEVICE);
dest_dma = unmap->addr[src_count];
+ ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]);
+ if (ret) {
+ err = -ENOMEM;
+ goto free_resources;
+ }
unmap->from_cnt = 1;
unmap->len = PAGE_SIZE;
tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
src_count, PAGE_SIZE, 0);
+ if (!tx) {
+ dev_err(dma_chan->device->dev,
+ "Self-test cannot prepare operation, disabling\n");
+ err = -ENODEV;
+ goto free_resources;
+ }
cookie = mv_xor_tx_submit(tx);
+ if (dma_submit_error(cookie)) {
+ dev_err(dma_chan->device->dev,
+ "Self-test submit error, disabling\n");
+ err = -ENODEV;
+ goto free_resources;
+ }
+
mv_xor_issue_pending(dma_chan);
async_tx_ack(tx);
msleep(8);
return err;
}
+/*
+ * Select DCT to which PCI cfg accesses are routed
+ */
+static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
+{
+ u32 reg = 0;
+
+ amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®);
+ reg &= (pvt->model == 0x30) ? ~3 : ~1;
+ reg |= dct;
+ amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
+}
+
/*
*
* Depending on the family, F2 DCT reads need special handling:
*
- * K8: has a single DCT only
+ * K8: has a single DCT only and no address offsets >= 0x100
*
* F10h: each DCT has its own set of regs
* DCT0 -> F2x040..
* DCT1 -> F2x140..
*
- * F15h: we select which DCT we access using F1x10C[DctCfgSel]
- *
* F16h: has only 1 DCT
+ *
+ * F15h: we select which DCT we access using F1x10C[DctCfgSel]
*/
-static int k8_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
- const char *func)
+static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
+ int offset, u32 *val)
{
- if (addr >= 0x100)
- return -EINVAL;
-
- return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
-}
+ switch (pvt->fam) {
+ case 0xf:
+ if (dct || offset >= 0x100)
+ return -EINVAL;
+ break;
-static int f10_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
- const char *func)
-{
- return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
-}
+ case 0x10:
+ if (dct) {
+ /*
+ * Note: If ganging is enabled, barring the regs
+ * F2x[1,0]98 and F2x[1,0]9C; reads reads to F2x1xx
+ * return 0. (cf. Section 2.8.1 F10h BKDG)
+ */
+ if (dct_ganging_enabled(pvt))
+ return 0;
-/*
- * Select DCT to which PCI cfg accesses are routed
- */
-static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
-{
- u32 reg = 0;
+ offset += 0x100;
+ }
+ break;
- amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®);
- reg &= (pvt->model >= 0x30) ? ~3 : ~1;
- reg |= dct;
- amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
-}
+ case 0x15:
+ /*
+ * F15h: F2x1xx addresses do not map explicitly to DCT1.
+ * We should select which DCT we access using F1x10C[DctCfgSel]
+ */
+ dct = (dct && pvt->model == 0x30) ? 3 : dct;
+ f15h_select_dct(pvt, dct);
+ break;
-static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
- const char *func)
-{
- u8 dct = 0;
+ case 0x16:
+ if (dct)
+ return -EINVAL;
+ break;
- /* For F15 M30h, the second dct is DCT 3, refer to BKDG Section 2.10 */
- if (addr >= 0x140 && addr <= 0x1a0) {
- dct = (pvt->model >= 0x30) ? 3 : 1;
- addr -= 0x100;
+ default:
+ break;
}
-
- f15h_select_dct(pvt, dct);
-
- return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
+ return amd64_read_pci_cfg(pvt->F2, offset, val);
}
/*
u32 *base0 = &pvt->csels[0].csbases[cs];
u32 *base1 = &pvt->csels[1].csbases[cs];
- if (!amd64_read_dct_pci_cfg(pvt, reg0, base0))
+ if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0))
edac_dbg(0, " DCSB0[%d]=0x%08x reg: F2x%x\n",
cs, *base0, reg0);
- if (pvt->fam == 0xf || dct_ganging_enabled(pvt))
+ if (pvt->fam == 0xf)
continue;
- if (!amd64_read_dct_pci_cfg(pvt, reg1, base1))
+ if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1))
edac_dbg(0, " DCSB1[%d]=0x%08x reg: F2x%x\n",
- cs, *base1, reg1);
+ cs, *base1, (pvt->fam == 0x10) ? reg1
+ : reg0);
}
for_each_chip_select_mask(cs, 0, pvt) {
u32 *mask0 = &pvt->csels[0].csmasks[cs];
u32 *mask1 = &pvt->csels[1].csmasks[cs];
- if (!amd64_read_dct_pci_cfg(pvt, reg0, mask0))
+ if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0))
edac_dbg(0, " DCSM0[%d]=0x%08x reg: F2x%x\n",
cs, *mask0, reg0);
- if (pvt->fam == 0xf || dct_ganging_enabled(pvt))
+ if (pvt->fam == 0xf)
continue;
- if (!amd64_read_dct_pci_cfg(pvt, reg1, mask1))
+ if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1))
edac_dbg(0, " DCSM1[%d]=0x%08x reg: F2x%x\n",
- cs, *mask1, reg1);
+ cs, *mask1, (pvt->fam == 0x10) ? reg1
+ : reg0);
}
}
if (pvt->fam == 0xf)
return;
- if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) {
+ if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) {
edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
dct_sel_interleave_addr(pvt));
}
- amd64_read_dct_pci_cfg(pvt, DCT_SEL_HI, &pvt->dct_sel_hi);
+ amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi);
}
/*
return sys_addr;
}
- amd64_read_dct_pci_cfg(pvt, SWAP_INTLV_REG, &swap_reg);
+ amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg);
if (!(swap_reg & 0x1))
return sys_addr;
WARN_ON(ctrl != 0);
}
- dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 : pvt->dbam0;
- dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->csels[1].csbases
- : pvt->csels[0].csbases;
-
+ if (pvt->fam == 0x10) {
+ dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1
+ : pvt->dbam0;
+ dcsb = (ctrl && !dct_ganging_enabled(pvt)) ?
+ pvt->csels[1].csbases :
+ pvt->csels[0].csbases;
+ } else if (ctrl) {
+ dbam = pvt->dbam0;
+ dcsb = pvt->csels[1].csbases;
+ }
edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
ctrl, dbam);
.early_channel_count = k8_early_channel_count,
.map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow,
.dbam_to_cs = k8_dbam_to_chip_select,
- .read_dct_pci_cfg = k8_read_dct_pci_cfg,
}
},
[F10_CPUS] = {
.early_channel_count = f1x_early_channel_count,
.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
.dbam_to_cs = f10_dbam_to_chip_select,
- .read_dct_pci_cfg = f10_read_dct_pci_cfg,
}
},
[F15_CPUS] = {
.early_channel_count = f1x_early_channel_count,
.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
.dbam_to_cs = f15_dbam_to_chip_select,
- .read_dct_pci_cfg = f15_read_dct_pci_cfg,
}
},
[F15_M30H_CPUS] = {
.early_channel_count = f1x_early_channel_count,
.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
.dbam_to_cs = f16_dbam_to_chip_select,
- .read_dct_pci_cfg = f15_read_dct_pci_cfg,
}
},
[F16_CPUS] = {
.early_channel_count = f1x_early_channel_count,
.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
.dbam_to_cs = f16_dbam_to_chip_select,
- .read_dct_pci_cfg = f10_read_dct_pci_cfg,
}
},
[F16_M30H_CPUS] = {
.early_channel_count = f1x_early_channel_count,
.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
.dbam_to_cs = f16_dbam_to_chip_select,
- .read_dct_pci_cfg = f10_read_dct_pci_cfg,
}
},
};
read_dct_base_mask(pvt);
amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);
- amd64_read_dct_pci_cfg(pvt, DBAM0, &pvt->dbam0);
+ amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0);
amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);
- amd64_read_dct_pci_cfg(pvt, DCLR0, &pvt->dclr0);
- amd64_read_dct_pci_cfg(pvt, DCHR0, &pvt->dchr0);
+ amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0);
+ amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0);
if (!dct_ganging_enabled(pvt)) {
- amd64_read_dct_pci_cfg(pvt, DCLR1, &pvt->dclr1);
- amd64_read_dct_pci_cfg(pvt, DCHR1, &pvt->dchr1);
+ amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1);
+ amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1);
}
pvt->ecc_sym_sz = 4;
if (pvt->fam >= 0x10) {
amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
+ /* F16h has only DCT0, so no need to read dbam1 */
if (pvt->fam != 0x16)
- /* F16h has only DCT0 */
- amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1);
+ amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1);
/* F10h, revD and later can do x8 ECC too */
if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25))
void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
struct err_info *);
int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode);
- int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset,
- u32 *val, const char *func);
};
struct amd64_family_type {
#define amd64_write_pci_cfg(pdev, offset, val) \
__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
-#define amd64_read_dct_pci_cfg(pvt, offset, val) \
- pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)
-
int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
u64 *hole_offset, u64 *hole_size);
#define EDAC_PCI "PCI"
#define EDAC_DEBUG "DEBUG"
-extern const char *edac_mem_types[];
+extern const char * const edac_mem_types[];
#ifdef CONFIG_EDAC_DEBUG
extern int edac_debug_level;
/*
* keep those in sync with the enum mem_type
*/
-const char *edac_mem_types[] = {
+const char * const edac_mem_types[] = {
"Empty csrow",
"Reserved csrow type",
"Unknown csrow type",
if (edac_op_state == EDAC_OPSTATE_INT) {
pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
res = devm_request_irq(&op->dev, pdata->irq,
- mpc85xx_l2_isr, 0,
+ mpc85xx_l2_isr, IRQF_SHARED,
"[EDAC] L2 err", edac_dev);
if (res < 0) {
printk(KERN_ERR
* page size (PAGE_SIZE) or the memory width (2 or 4).
*/
for (j = 0; j < csi->nr_channels; j++) {
- struct dimm_info *dimm = csi->channels[j].dimm;
+ struct dimm_info *dimm = csi->channels[j]->dimm;
dimm->nr_pages = nr_pages / csi->nr_channels;
dimm->grain = 1;
POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
}
+static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
+{
+ if (INTEL_INFO(dev_priv->dev)->gen < 6) {
+ intel_gtt_chipset_flush();
+ } else {
+ I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
+ POSTING_READ(GFX_FLSH_CNTL_GEN6);
+ }
+}
+
void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
dev_priv->gtt.base.start,
dev_priv->gtt.base.total,
true);
+
+ i915_ggtt_flush(dev_priv);
}
void i915_gem_restore_gtt_mappings(struct drm_device *dev)
gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
}
- i915_gem_chipset_flush(dev);
+ i915_ggtt_flush(dev_priv);
}
int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
MODULE_PARM_DESC(powersave,
"Enable powersavings, fbc, downclocking, etc. (default: true)");
-module_param_named(semaphores, i915.semaphores, int, 0400);
+module_param_named_unsafe(semaphores, i915.semaphores, int, 0400);
MODULE_PARM_DESC(semaphores,
"Use semaphores for inter-ring sync "
"(default: -1 (use per-chip defaults))");
-module_param_named(enable_rc6, i915.enable_rc6, int, 0400);
+module_param_named_unsafe(enable_rc6, i915.enable_rc6, int, 0400);
MODULE_PARM_DESC(enable_rc6,
"Enable power-saving render C-state 6. "
"Different stages can be selected via bitmask values "
"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
"default: -1 (use per-chip default)");
-module_param_named(enable_fbc, i915.enable_fbc, int, 0600);
+module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, 0600);
MODULE_PARM_DESC(enable_fbc,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
"WARNING: Disabling this can cause system wide hangs. "
"(default: true)");
-module_param_named(enable_ppgtt, i915.enable_ppgtt, int, 0400);
+module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, 0400);
MODULE_PARM_DESC(enable_ppgtt,
"Override PPGTT usage. "
"(-1=auto [default], 0=disabled, 1=aliasing, 2=full)");
return -EINVAL;
}
+/*
+ * If the vendor backlight interface is not in use and ACPI backlight interface
+ * is broken, do not bother processing backlight change requests from firmware.
+ */
+static bool should_ignore_backlight_request(void)
+{
+ return acpi_video_backlight_support() &&
+ !acpi_video_verify_backlight_support();
+}
+
static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
{
struct drm_i915_private *dev_priv = dev->dev_private;
DRM_DEBUG_DRIVER("bclp = 0x%08x\n", bclp);
- /*
- * If the acpi_video interface is not supposed to be used, don't
- * bother processing backlight level change requests from firmware.
- */
- if (!acpi_video_verify_backlight_support()) {
+ if (should_ignore_backlight_request()) {
DRM_DEBUG_KMS("opregion backlight request ignored\n");
return 0;
}
const int or = ffs(outp->or) - 1;
const u32 loff = (or * 0x800) + (link * 0x80);
const u16 mask = (outp->sorconf.link << 6) | outp->or;
+ struct dcb_output match;
u8 ver, hdr;
- if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, outp))
+ if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, &match))
nv_mask(priv, 0x61c10c + loff, 0x00000001, 0x00000000);
}
struct nouveau_software_chan *swch;
struct nv_dma_v0 args = {};
int ret, i;
+ bool save;
nvif_object_map(chan->object);
}
/* initialise synchronisation */
- return nouveau_fence(chan->drm)->context_new(chan);
+ save = cli->base.super;
+ cli->base.super = true; /* hack until fencenv50 fixed */
+ ret = nouveau_fence(chan->drm)->context_new(chan);
+ cli->base.super = save;
+ return ret;
}
int
}
int
-nouveau_display_suspend(struct drm_device *dev)
+nouveau_display_suspend(struct drm_device *dev, bool runtime)
{
- struct nouveau_drm *drm = nouveau_drm(dev);
struct drm_crtc *crtc;
nouveau_display_fini(dev);
- NV_INFO(drm, "unpinning framebuffer(s)...\n");
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
struct nouveau_framebuffer *nouveau_fb;
}
void
-nouveau_display_repin(struct drm_device *dev)
+nouveau_display_resume(struct drm_device *dev, bool runtime)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct drm_crtc *crtc;
- int ret;
+ int ret, head;
+ /* re-pin fb/cursors */
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
struct nouveau_framebuffer *nouveau_fb;
if (ret)
NV_ERROR(drm, "Could not pin/map cursor.\n");
}
-}
-
-void
-nouveau_display_resume(struct drm_device *dev)
-{
- struct drm_crtc *crtc;
- int head;
nouveau_display_init(dev);
for (head = 0; head < dev->mode_config.num_crtc; head++)
drm_vblank_on(dev, head);
+ /* This should ensure we don't hit a locking problem when someone
+ * wakes us up via a connector. We should never go into suspend
+ * while the display is on anyways.
+ */
+ if (runtime)
+ return;
+
drm_helper_resume_force_mode(dev);
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
void nouveau_display_destroy(struct drm_device *dev);
int nouveau_display_init(struct drm_device *dev);
void nouveau_display_fini(struct drm_device *dev);
-int nouveau_display_suspend(struct drm_device *dev);
-void nouveau_display_repin(struct drm_device *dev);
-void nouveau_display_resume(struct drm_device *dev);
+int nouveau_display_suspend(struct drm_device *dev, bool runtime);
+void nouveau_display_resume(struct drm_device *dev, bool runtime);
int nouveau_display_vblank_enable(struct drm_device *, int);
void nouveau_display_vblank_disable(struct drm_device *, int);
int nouveau_display_scanoutpos(struct drm_device *, int, unsigned int,
struct nouveau_cli *cli;
int ret;
- if (dev->mode_config.num_crtc && !runtime) {
+ if (dev->mode_config.num_crtc) {
+ NV_INFO(drm, "suspending console...\n");
+ nouveau_fbcon_set_suspend(dev, 1);
NV_INFO(drm, "suspending display...\n");
- ret = nouveau_display_suspend(dev);
+ ret = nouveau_display_suspend(dev, runtime);
if (ret)
return ret;
}
fail_display:
if (dev->mode_config.num_crtc) {
NV_INFO(drm, "resuming display...\n");
- nouveau_display_resume(dev);
+ nouveau_display_resume(dev, runtime);
}
return ret;
}
drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
return 0;
- if (drm_dev->mode_config.num_crtc)
- nouveau_fbcon_set_suspend(drm_dev, 1);
-
ret = nouveau_do_suspend(drm_dev, false);
if (ret)
return ret;
}
static int
-nouveau_do_resume(struct drm_device *dev)
+nouveau_do_resume(struct drm_device *dev, bool runtime)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_cli *cli;
if (dev->mode_config.num_crtc) {
NV_INFO(drm, "resuming display...\n");
- nouveau_display_repin(dev);
+ nouveau_display_resume(dev, runtime);
+ NV_INFO(drm, "resuming console...\n");
+ nouveau_fbcon_set_suspend(dev, 0);
}
return 0;
return ret;
pci_set_master(pdev);
- ret = nouveau_do_resume(drm_dev);
- if (ret)
- return ret;
-
- if (drm_dev->mode_config.num_crtc) {
- nouveau_display_resume(drm_dev);
- nouveau_fbcon_set_suspend(drm_dev, 0);
- }
-
- return 0;
+ return nouveau_do_resume(drm_dev, false);
}
static int nouveau_pmops_freeze(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct drm_device *drm_dev = pci_get_drvdata(pdev);
- int ret;
-
- if (drm_dev->mode_config.num_crtc)
- nouveau_fbcon_set_suspend(drm_dev, 1);
-
- ret = nouveau_do_suspend(drm_dev, false);
- return ret;
+ return nouveau_do_suspend(drm_dev, false);
}
static int nouveau_pmops_thaw(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct drm_device *drm_dev = pci_get_drvdata(pdev);
- int ret;
-
- ret = nouveau_do_resume(drm_dev);
- if (ret)
- return ret;
-
- if (drm_dev->mode_config.num_crtc) {
- nouveau_display_resume(drm_dev);
- nouveau_fbcon_set_suspend(drm_dev, 0);
- }
-
- return 0;
+ return nouveau_do_resume(drm_dev, false);
}
return ret;
pci_set_master(pdev);
- ret = nouveau_do_resume(drm_dev);
+ ret = nouveau_do_resume(drm_dev, true);
drm_kms_helper_poll_enable(drm_dev);
/* do magic */
nvif_mask(device, 0x88488, (1 << 25), (1 << 25));
.fb_probe = nouveau_fbcon_create,
};
+static void
+nouveau_fbcon_set_suspend_work(struct work_struct *work)
+{
+ struct nouveau_fbdev *fbcon = container_of(work, typeof(*fbcon), work);
+ console_lock();
+ nouveau_fbcon_accel_restore(fbcon->dev);
+ nouveau_fbcon_zfill(fbcon->dev, fbcon);
+ fb_set_suspend(fbcon->helper.fbdev, FBINFO_STATE_RUNNING);
+ console_unlock();
+}
int
nouveau_fbcon_init(struct drm_device *dev)
if (!fbcon)
return -ENOMEM;
+ INIT_WORK(&fbcon->work, nouveau_fbcon_set_suspend_work);
fbcon->dev = dev;
drm->fbcon = fbcon;
{
struct nouveau_drm *drm = nouveau_drm(dev);
if (drm->fbcon) {
- console_lock();
- if (state == 0) {
- nouveau_fbcon_accel_restore(dev);
- nouveau_fbcon_zfill(dev, drm->fbcon);
+ if (state == FBINFO_STATE_RUNNING) {
+ schedule_work(&drm->fbcon->work);
+ return;
}
+ flush_work(&drm->fbcon->work);
+ console_lock();
fb_set_suspend(drm->fbcon->helper.fbdev, state);
- if (state == 1)
- nouveau_fbcon_accel_save_disable(dev);
+ nouveau_fbcon_accel_save_disable(dev);
console_unlock();
}
}
struct nouveau_framebuffer nouveau_fb;
struct list_head fbdev_list;
struct drm_device *dev;
+ struct work_struct work;
unsigned int saved_flags;
struct nvif_object surf2d;
struct nvif_object clip;
qup->adap.dev.of_node = pdev->dev.of_node;
strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
- ret = i2c_add_adapter(&qup->adap);
- if (ret)
- goto fail;
-
pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
pm_runtime_use_autosuspend(qup->dev);
pm_runtime_set_active(qup->dev);
pm_runtime_enable(qup->dev);
+
+ ret = i2c_add_adapter(&qup->adap);
+ if (ret)
+ goto fail_runtime;
+
return 0;
+fail_runtime:
+ pm_runtime_disable(qup->dev);
+ pm_runtime_set_suspended(qup->dev);
fail:
qup_i2c_disable_clocks(qup);
return ret;
for (i = 0; i < 8; ++i) {
val = 0;
for (j = 0; j < 4; ++j) {
- if (i2c->processed == i2c->msg->len)
+ if ((i2c->processed == i2c->msg->len) && (cnt != 0))
break;
if (i2c->processed == 0 && cnt == 0)
#define cpu_to_group(cpu) cpu_to_node(cpu)
#define ANY_GROUP NUMA_NO_NODE
+static bool devices_handle_discard_safely = false;
+module_param(devices_handle_discard_safely, bool, 0644);
+MODULE_PARM_DESC(devices_handle_discard_safely,
+ "Set to Y if all devices in each array reliably return zeroes on reads from discarded regions");
static struct workqueue_struct *raid5_wq;
/*
* Stripe cache
mddev->queue->limits.discard_granularity = stripe;
/*
* unaligned part of discard request will be ignored, so can't
- * guarantee discard_zerors_data
+ * guarantee discard_zeroes_data
*/
mddev->queue->limits.discard_zeroes_data = 0;
!bdev_get_queue(rdev->bdev)->
limits.discard_zeroes_data)
discard_supported = false;
+ /* Unfortunately, discard_zeroes_data is not currently
+ * a guarantee - just a hint. So we only allow DISCARD
+ * if the sysadmin has confirmed that only safe devices
+ * are in use by setting a module parameter.
+ */
+ if (!devices_handle_discard_safely) {
+ if (discard_supported) {
+ pr_info("md/raid456: discard support disabled due to uncertainty.\n");
+ pr_info("Set raid456.devices_handle_discard_safely=Y to override.\n");
+ }
+ discard_supported = false;
+ }
}
if (discard_supported &&
.disconnect = em28xx_usb_disconnect,
.suspend = em28xx_usb_suspend,
.resume = em28xx_usb_resume,
+ .reset_resume = em28xx_usb_resume,
.id_table = em28xx_id_table,
};
skb->protocol = eth_type_trans(skb, bp->dev);
- if ((len > (bp->dev->mtu + ETH_HLEN)) &&
- (ntohs(skb->protocol) != 0x8100)) {
+ if (len > (bp->dev->mtu + ETH_HLEN) &&
+ skb->protocol != htons(0x8100) &&
+ skb->protocol != htons(ETH_P_8021AD)) {
dev_kfree_skb(skb);
goto next_rx;
skb->protocol = eth_type_trans(skb, tp->dev);
if (len > (tp->dev->mtu + ETH_HLEN) &&
- skb->protocol != htons(ETH_P_8021Q)) {
+ skb->protocol != htons(ETH_P_8021Q) &&
+ skb->protocol != htons(ETH_P_8021AD)) {
dev_kfree_skb_any(skb);
goto drop_it_no_recycle;
}
#include <linux/of_device.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
-#include <linux/pinctrl/consumer.h>
#include "macb.h"
struct phy_device *phydev;
u32 config;
int err = -ENXIO;
- struct pinctrl *pinctrl;
const char *mac;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
goto err_out;
}
- pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
- if (IS_ERR(pinctrl)) {
- err = PTR_ERR(pinctrl);
- if (err == -EPROBE_DEFER)
- goto err_out;
-
- dev_warn(&pdev->dev, "No pinctrl provided\n");
- }
-
err = -ENOMEM;
dev = alloc_etherdev(sizeof(*bp));
if (!dev)
#endif /* CONFIG_PCI_MSI */
static uint8_t num_vfs[3] = {0, 0, 0};
-static int num_vfs_argc = 3;
+static int num_vfs_argc;
module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
"num_vfs=port1,port2,port1+2");
static uint8_t probe_vf[3] = {0, 0, 0};
-static int probe_vfs_argc = 3;
+static int probe_vfs_argc;
module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
"probe_vf=port1,port2,port1+2");
int i, j;
struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
+ spin_lock(&adapter->tx_clean_lock);
cmd_buf = tx_ring->cmd_buf_arr;
for (i = 0; i < tx_ring->num_desc; i++) {
buffrag = cmd_buf->frag_array;
}
cmd_buf++;
}
+ spin_unlock(&adapter->tx_clean_lock);
}
void netxen_free_sw_resources(struct netxen_adapter *adapter)
break;
}
- if (count && netif_running(netdev)) {
- tx_ring->sw_consumer = sw_consumer;
+ tx_ring->sw_consumer = sw_consumer;
+ if (count && netif_running(netdev)) {
smp_mb();
if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev))
return;
smp_mb();
- spin_lock(&adapter->tx_clean_lock);
netif_carrier_off(netdev);
netif_tx_disable(netdev);
netxen_napi_disable(adapter);
netxen_release_tx_buffers(adapter);
- spin_unlock(&adapter->tx_clean_lock);
}
/* Usage: During suspend and firmware recovery module */
{
u32 idc_params, val;
- if (qlcnic_83xx_lockless_flash_read32(adapter,
- QLC_83XX_IDC_FLASH_PARAM_ADDR,
- (u8 *)&idc_params, 1)) {
+ if (qlcnic_83xx_flash_read32(adapter, QLC_83XX_IDC_FLASH_PARAM_ADDR,
+ (u8 *)&idc_params, 1)) {
dev_info(&adapter->pdev->dev,
"%s:failed to get IDC params from flash\n", __func__);
adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
struct qlcnic_host_tx_ring *tx_ring;
struct qlcnic_esw_statistics port_stats;
struct qlcnic_mac_statistics mac_stats;
- int index, ret, length, size, tx_size, ring;
+ int index, ret, length, size, ring;
char *p;
- tx_size = adapter->drv_tx_rings * QLCNIC_TX_STATS_LEN;
+ memset(data, 0, stats->n_stats * sizeof(u64));
- memset(data, 0, tx_size * sizeof(u64));
for (ring = 0, index = 0; ring < adapter->drv_tx_rings; ring++) {
- if (test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
+ if (adapter->is_up == QLCNIC_ADAPTER_UP_MAGIC) {
tx_ring = &adapter->tx_ring[ring];
data = qlcnic_fill_tx_queue_stats(data, tx_ring);
qlcnic_update_stats(adapter);
+ } else {
+ data += QLCNIC_TX_STATS_LEN;
}
}
- memset(data, 0, stats->n_stats * sizeof(u64));
length = QLCNIC_STATS_LEN;
for (index = 0; index < length; index++) {
p = (char *)adapter + qlcnic_gstrings_stats[index].stat_offset;
if (IS_ERR(priv->stmmac_clk)) {
dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
__func__);
- ret = PTR_ERR(priv->stmmac_clk);
- goto error_clk_get;
+ /* If failed to obtain stmmac_clk and specific clk_csr value
+ * is NOT passed from the platform, probe fail.
+ */
+ if (!priv->plat->clk_csr) {
+ ret = PTR_ERR(priv->stmmac_clk);
+ goto error_clk_get;
+ } else {
+ priv->stmmac_clk = NULL;
+ }
}
clk_prepare_enable(priv->stmmac_clk);
int hdr_offset;
u32 net_trans_info;
u32 hash;
+ u32 skb_length = skb->len;
/* We will atmost need two pages to describe the rndis
drop:
if (ret == 0) {
- net->stats.tx_bytes += skb->len;
+ net->stats.tx_bytes += skb_length;
net->stats.tx_packets++;
} else {
kfree(packet);
return err;
}
+/* Requires RTNL */
static int macvtap_set_queue(struct net_device *dev, struct file *file,
struct macvtap_queue *q)
{
struct macvlan_dev *vlan = netdev_priv(dev);
- int err = -EBUSY;
- rtnl_lock();
if (vlan->numqueues == MAX_MACVTAP_QUEUES)
- goto out;
+ return -EBUSY;
- err = 0;
rcu_assign_pointer(q->vlan, vlan);
rcu_assign_pointer(vlan->taps[vlan->numvtaps], q);
sock_hold(&q->sk);
vlan->numvtaps++;
vlan->numqueues++;
-out:
- rtnl_unlock();
- return err;
+ return 0;
}
static int macvtap_disable_queue(struct macvtap_queue *q)
static int macvtap_open(struct inode *inode, struct file *file)
{
struct net *net = current->nsproxy->net_ns;
- struct net_device *dev = dev_get_by_macvtap_minor(iminor(inode));
+ struct net_device *dev;
struct macvtap_queue *q;
- int err;
+ int err = -ENODEV;
- err = -ENODEV;
+ rtnl_lock();
+ dev = dev_get_by_macvtap_minor(iminor(inode));
if (!dev)
goto out;
if (dev)
dev_put(dev);
+ rtnl_unlock();
return err;
}
#include <net/ip6_checksum.h>
/* Version Information */
-#define DRIVER_VERSION "v1.06.0 (2014/03/03)"
+#define DRIVER_VERSION "v1.06.1 (2014/10/01)"
#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
#define MODULENAME "r8152"
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
}
+static int rtl_start_rx(struct r8152 *tp)
+{
+ int i, ret = 0;
+
+ INIT_LIST_HEAD(&tp->rx_done);
+ for (i = 0; i < RTL8152_MAX_RX; i++) {
+ INIT_LIST_HEAD(&tp->rx_info[i].list);
+ ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
+ if (ret)
+ break;
+ }
+
+ return ret;
+}
+
+static int rtl_stop_rx(struct r8152 *tp)
+{
+ int i;
+
+ for (i = 0; i < RTL8152_MAX_RX; i++)
+ usb_kill_urb(tp->rx_info[i].urb);
+
+ return 0;
+}
+
static int rtl_enable(struct r8152 *tp)
{
u32 ocp_data;
- int i, ret;
r8152b_reset_packet_filter(tp);
rxdy_gated_en(tp, false);
- INIT_LIST_HEAD(&tp->rx_done);
- ret = 0;
- for (i = 0; i < RTL8152_MAX_RX; i++) {
- INIT_LIST_HEAD(&tp->rx_info[i].list);
- ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
- }
-
- return ret;
+ return rtl_start_rx(tp);
}
static int rtl8152_enable(struct r8152 *tp)
mdelay(1);
}
- for (i = 0; i < RTL8152_MAX_RX; i++)
- usb_kill_urb(tp->rx_info[i].urb);
+ rtl_stop_rx(tp);
rtl8152_nic_reset(tp);
}
}
}
-static void rtl_clear_bp(struct r8152 *tp)
-{
- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
- ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
- ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
- ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
- ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
- mdelay(3);
- ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
- ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
-}
-
-static void r8153_clear_bp(struct r8152 *tp)
-{
- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
- ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0);
- rtl_clear_bp(tp);
-}
-
static void r8153_teredo_off(struct r8152 *tp)
{
u32 ocp_data;
r8152_mdio_write(tp, MII_BMCR, data);
}
- rtl_clear_bp(tp);
-
set_bit(PHY_RESET, &tp->flags);
}
r8152_mdio_write(tp, MII_BMCR, data);
}
- r8153_clear_bp(tp);
-
if (tp->version == RTL_VER_03) {
data = ocp_reg_read(tp, OCP_EEE_CFG);
data &= ~CTAP_SHORT_EN;
clear_bit(WORK_ENABLE, &tp->flags);
usb_kill_urb(tp->intr_urb);
cancel_delayed_work_sync(&tp->schedule);
+ tasklet_disable(&tp->tl);
if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
+ rtl_stop_rx(tp);
rtl_runtime_suspend_enable(tp, true);
} else {
- tasklet_disable(&tp->tl);
tp->rtl_ops.down(tp);
- tasklet_enable(&tp->tl);
}
+ tasklet_enable(&tp->tl);
}
return 0;
if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
rtl_runtime_suspend_enable(tp, false);
clear_bit(SELECTIVE_SUSPEND, &tp->flags);
+ set_bit(WORK_ENABLE, &tp->flags);
if (tp->speed & LINK_STATUS)
- tp->rtl_ops.disable(tp);
+ rtl_start_rx(tp);
} else {
tp->rtl_ops.up(tp);
rtl8152_set_speed(tp, AUTONEG_ENABLE,
tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
DUPLEX_FULL);
+ tp->speed = 0;
+ netif_carrier_off(tp->netdev);
+ set_bit(WORK_ENABLE, &tp->flags);
}
- tp->speed = 0;
- netif_carrier_off(tp->netdev);
- set_bit(WORK_ENABLE, &tp->flags);
usb_submit_urb(tp->intr_urb, GFP_KERNEL);
}
if (test_bit(RTL8152_UNPLUG, &tp->flags))
return;
- r8153_power_cut_en(tp, true);
+ r8153_power_cut_en(tp, false);
}
static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
usb_set_intfdata(intf, NULL);
if (tp) {
- set_bit(RTL8152_UNPLUG, &tp->flags);
+ struct usb_device *udev = tp->udev;
+
+ if (udev->state == USB_STATE_NOTATTACHED)
+ set_bit(RTL8152_UNPLUG, &tp->flags);
+
tasklet_kill(&tp->tl);
unregister_netdev(tp->netdev);
tp->rtl_ops.unload(tp);
serial_port.iotype = UPIO_PORT;
serial_port.type = PORT_16550A;
serial_port.uartclk = 115200*16;
- serial_port.fifosize = 16;
+ serial_port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE |
+ UPF_BOOT_AUTOCONF;
/* serial port #1 */
serial_port.iobase = sio_dev.sp1_base;
BCM28145, and BCM28155 SoCs. This driver requires the pinctrl
framework. GPIO is provided by a separate GPIO driver.
-config PINCTRL_IMX
- bool
- select PINMUX
- select PINCONF
-
-config PINCTRL_IMX1_CORE
- bool
- select PINMUX
- select PINCONF
-
-config PINCTRL_IMX1
- bool "IMX1 pinctrl driver"
- depends on SOC_IMX1
- select PINCTRL_IMX1_CORE
- help
- Say Y here to enable the imx1 pinctrl driver
-
-config PINCTRL_IMX27
- bool "IMX27 pinctrl driver"
- depends on SOC_IMX27
- select PINCTRL_IMX1_CORE
- help
- Say Y here to enable the imx27 pinctrl driver
-
-
-config PINCTRL_IMX25
- bool "IMX25 pinctrl driver"
- depends on OF
- depends on SOC_IMX25
- select PINCTRL_IMX
- help
- Say Y here to enable the imx25 pinctrl driver
-
-config PINCTRL_IMX35
- bool "IMX35 pinctrl driver"
- depends on SOC_IMX35
- select PINCTRL_IMX
- help
- Say Y here to enable the imx35 pinctrl driver
-
-config PINCTRL_IMX50
- bool "IMX50 pinctrl driver"
- depends on SOC_IMX50
- select PINCTRL_IMX
- help
- Say Y here to enable the imx50 pinctrl driver
-
-config PINCTRL_IMX51
- bool "IMX51 pinctrl driver"
- depends on SOC_IMX51
- select PINCTRL_IMX
- help
- Say Y here to enable the imx51 pinctrl driver
-
-config PINCTRL_IMX53
- bool "IMX53 pinctrl driver"
- depends on SOC_IMX53
- select PINCTRL_IMX
- help
- Say Y here to enable the imx53 pinctrl driver
-
-config PINCTRL_IMX6Q
- bool "IMX6Q/DL pinctrl driver"
- depends on SOC_IMX6Q
- select PINCTRL_IMX
- help
- Say Y here to enable the imx6q/dl pinctrl driver
-
-config PINCTRL_IMX6SL
- bool "IMX6SL pinctrl driver"
- depends on SOC_IMX6SL
- select PINCTRL_IMX
- help
- Say Y here to enable the imx6sl pinctrl driver
-
-config PINCTRL_IMX6SX
- bool "IMX6SX pinctrl driver"
- depends on SOC_IMX6SX
- select PINCTRL_IMX
- help
- Say Y here to enable the imx6sx pinctrl driver
-
-config PINCTRL_VF610
- bool "Freescale Vybrid VF610 pinctrl driver"
- depends on SOC_VF610
- select PINCTRL_IMX
- help
- Say Y here to enable the Freescale Vybrid VF610 pinctrl driver
-
config PINCTRL_LANTIQ
bool
depends on LANTIQ
depends on SOC_FALCON
depends on PINCTRL_LANTIQ
-config PINCTRL_MXS
- bool
- select PINMUX
- select PINCONF
-
-config PINCTRL_IMX23
- bool
- select PINCTRL_MXS
-
-config PINCTRL_IMX28
- bool
- select PINCTRL_MXS
-
config PINCTRL_ROCKCHIP
bool
select PINMUX
TPS65913, TPS80036 etc.
source "drivers/pinctrl/berlin/Kconfig"
+source "drivers/pinctrl/freescale/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/nomadik/Kconfig"
source "drivers/pinctrl/qcom/Kconfig"
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
-obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
-obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
-obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
-obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
-obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
-obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
-obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
-obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
-obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
-obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
-obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
-obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
-obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
-obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
-obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
-obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
-obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_ARCH_BERLIN) += berlin/
+obj-y += freescale/
obj-$(CONFIG_PLAT_ORION) += mvebu/
obj-y += nomadik/
obj-$(CONFIG_ARCH_QCOM) += qcom/
-obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
-obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
-obj-$(CONFIG_SUPERH) += sh-pfc/
+obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
+obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_ARCH_VT8500) += vt8500/
return 0;
}
-static void berlin_pinctrl_dt_free_map(struct pinctrl_dev *pctrl_dev,
- struct pinctrl_map *map,
- unsigned nmaps)
-{
- int i;
-
- for (i = 0; i < nmaps; i++) {
- if (map[i].type == PIN_MAP_TYPE_MUX_GROUP) {
- kfree(map[i].data.mux.group);
-
- /* a function can be applied to multiple groups */
- if (i == 0)
- kfree(map[i].data.mux.function);
- }
- }
-
- kfree(map);
-}
-
static const struct pinctrl_ops berlin_pinctrl_ops = {
.get_groups_count = &berlin_pinctrl_get_group_count,
.get_group_name = &berlin_pinctrl_get_group_name,
.dt_node_to_map = &berlin_pinctrl_dt_node_to_map,
- .dt_free_map = &berlin_pinctrl_dt_free_map,
+ .dt_free_map = &pinctrl_utils_dt_free_map,
};
static int berlin_pinmux_get_functions_count(struct pinctrl_dev *pctrl_dev)
return NULL;
}
-static int berlin_pinmux_enable(struct pinctrl_dev *pctrl_dev,
- unsigned function,
- unsigned group)
+static int berlin_pinmux_set(struct pinctrl_dev *pctrl_dev,
+ unsigned function,
+ unsigned group)
{
struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
const struct berlin_desc_group *group_desc = pctrl->desc->groups + group;
.get_functions_count = &berlin_pinmux_get_functions_count,
.get_function_name = &berlin_pinmux_get_function_name,
.get_function_groups = &berlin_pinmux_get_function_groups,
- .enable = &berlin_pinmux_enable,
+ .set_mux = &berlin_pinmux_set,
};
static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl,
--- /dev/null
+config PINCTRL_IMX
+ bool
+ select PINMUX
+ select PINCONF
+
+config PINCTRL_IMX1_CORE
+ bool
+ select PINMUX
+ select PINCONF
+
+config PINCTRL_IMX1
+ bool "IMX1 pinctrl driver"
+ depends on SOC_IMX1
+ select PINCTRL_IMX1_CORE
+ help
+ Say Y here to enable the imx1 pinctrl driver
+
+config PINCTRL_IMX21
+ bool "i.MX21 pinctrl driver"
+ depends on SOC_IMX21
+ select PINCTRL_IMX1_CORE
+ help
+ Say Y here to enable the i.MX21 pinctrl driver
+
+config PINCTRL_IMX27
+ bool "IMX27 pinctrl driver"
+ depends on SOC_IMX27
+ select PINCTRL_IMX1_CORE
+ help
+ Say Y here to enable the imx27 pinctrl driver
+
+
+config PINCTRL_IMX25
+ bool "IMX25 pinctrl driver"
+ depends on OF
+ depends on SOC_IMX25
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx25 pinctrl driver
+
+config PINCTRL_IMX35
+ bool "IMX35 pinctrl driver"
+ depends on SOC_IMX35
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx35 pinctrl driver
+
+config PINCTRL_IMX50
+ bool "IMX50 pinctrl driver"
+ depends on SOC_IMX50
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx50 pinctrl driver
+
+config PINCTRL_IMX51
+ bool "IMX51 pinctrl driver"
+ depends on SOC_IMX51
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx51 pinctrl driver
+
+config PINCTRL_IMX53
+ bool "IMX53 pinctrl driver"
+ depends on SOC_IMX53
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx53 pinctrl driver
+
+config PINCTRL_IMX6Q
+ bool "IMX6Q/DL pinctrl driver"
+ depends on SOC_IMX6Q
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx6q/dl pinctrl driver
+
+config PINCTRL_IMX6SL
+ bool "IMX6SL pinctrl driver"
+ depends on SOC_IMX6SL
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx6sl pinctrl driver
+
+config PINCTRL_IMX6SX
+ bool "IMX6SX pinctrl driver"
+ depends on SOC_IMX6SX
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx6sx pinctrl driver
+
+config PINCTRL_VF610
+ bool "Freescale Vybrid VF610 pinctrl driver"
+ depends on SOC_VF610
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the Freescale Vybrid VF610 pinctrl driver
+
+config PINCTRL_MXS
+ bool
+ select PINMUX
+ select PINCONF
+
+config PINCTRL_IMX23
+ bool
+ select PINCTRL_MXS
+
+config PINCTRL_IMX28
+ bool
+ select PINCTRL_MXS
--- /dev/null
+# Freescale pin control drivers
+obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
+obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
+obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o
+obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
+obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
+obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
+obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
+obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
+obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
+obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
+obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
+obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
+obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
+obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
+obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
+obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
+obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
--- /dev/null
+/*
+ * Core driver for the imx pin controller
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "pinctrl-imx.h"
+
+/* The bits in CONFIG cell defined in binding doc*/
+#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
+#define IMX_PAD_SION 0x40000000 /* set SION */
+
+/**
+ * @dev: a pointer back to containing device
+ * @base: the offset to the controller in virtual memory
+ */
+struct imx_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ void __iomem *base;
+ const struct imx_pinctrl_soc_info *info;
+};
+
+static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
+ const struct imx_pinctrl_soc_info *info,
+ const char *name)
+{
+ const struct imx_pin_group *grp = NULL;
+ int i;
+
+ for (i = 0; i < info->ngroups; i++) {
+ if (!strcmp(info->groups[i].name, name)) {
+ grp = &info->groups[i];
+ break;
+ }
+ }
+
+ return grp;
+}
+
+static int imx_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ return info->ngroups;
+}
+
+static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ return info->groups[selector].name;
+}
+
+static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
+ const unsigned **pins,
+ unsigned *npins)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ if (selector >= info->ngroups)
+ return -EINVAL;
+
+ *pins = info->groups[selector].pin_ids;
+ *npins = info->groups[selector].npins;
+
+ return 0;
+}
+
+static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+ unsigned offset)
+{
+ seq_printf(s, "%s", dev_name(pctldev->dev));
+}
+
+static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map, unsigned *num_maps)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_group *grp;
+ struct pinctrl_map *new_map;
+ struct device_node *parent;
+ int map_num = 1;
+ int i, j;
+
+ /*
+ * first find the group of this node and check if we need create
+ * config maps for pins
+ */
+ grp = imx_pinctrl_find_group_by_name(info, np->name);
+ if (!grp) {
+ dev_err(info->dev, "unable to find group for node %s\n",
+ np->name);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < grp->npins; i++) {
+ if (!(grp->pins[i].config & IMX_NO_PAD_CTL))
+ map_num++;
+ }
+
+ new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
+ if (!new_map)
+ return -ENOMEM;
+
+ *map = new_map;
+ *num_maps = map_num;
+
+ /* create mux map */
+ parent = of_get_parent(np);
+ if (!parent) {
+ kfree(new_map);
+ return -EINVAL;
+ }
+ new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+ new_map[0].data.mux.function = parent->name;
+ new_map[0].data.mux.group = np->name;
+ of_node_put(parent);
+
+ /* create config map */
+ new_map++;
+ for (i = j = 0; i < grp->npins; i++) {
+ if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) {
+ new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ new_map[j].data.configs.group_or_pin =
+ pin_get_name(pctldev, grp->pins[i].pin);
+ new_map[j].data.configs.configs = &grp->pins[i].config;
+ new_map[j].data.configs.num_configs = 1;
+ j++;
+ }
+ }
+
+ dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
+ (*map)->data.mux.function, (*map)->data.mux.group, map_num);
+
+ return 0;
+}
+
+static void imx_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned num_maps)
+{
+ kfree(map);
+}
+
+static const struct pinctrl_ops imx_pctrl_ops = {
+ .get_groups_count = imx_get_groups_count,
+ .get_group_name = imx_get_group_name,
+ .get_group_pins = imx_get_group_pins,
+ .pin_dbg_show = imx_pin_dbg_show,
+ .dt_node_to_map = imx_dt_node_to_map,
+ .dt_free_map = imx_dt_free_map,
+
+};
+
+static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg;
+ unsigned int npins, pin_id;
+ int i;
+ struct imx_pin_group *grp;
+
+ /*
+ * Configure the mux mode for each pin in the group for a specific
+ * function.
+ */
+ grp = &info->groups[group];
+ npins = grp->npins;
+
+ dev_dbg(ipctl->dev, "enable function %s group %s\n",
+ info->functions[selector].name, grp->name);
+
+ for (i = 0; i < npins; i++) {
+ struct imx_pin *pin = &grp->pins[i];
+ pin_id = pin->pin;
+ pin_reg = &info->pin_regs[pin_id];
+
+ if (pin_reg->mux_reg == -1) {
+ dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
+ info->pins[pin_id].name);
+ return -EINVAL;
+ }
+
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ u32 reg;
+ reg = readl(ipctl->base + pin_reg->mux_reg);
+ reg &= ~(0x7 << 20);
+ reg |= (pin->mux_mode << 20);
+ writel(reg, ipctl->base + pin_reg->mux_reg);
+ } else {
+ writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
+ }
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, pin->mux_mode);
+
+ /*
+ * If the select input value begins with 0xff, it's a quirky
+ * select input and the value should be interpreted as below.
+ * 31 23 15 7 0
+ * | 0xff | shift | width | select |
+ * It's used to work around the problem that the select
+ * input for some pin is not implemented in the select
+ * input register but in some general purpose register.
+ * We encode the select input value, width and shift of
+ * the bit field into input_val cell of pin function ID
+ * in device tree, and then decode them here for setting
+ * up the select input bits in general purpose register.
+ */
+ if (pin->input_val >> 24 == 0xff) {
+ u32 val = pin->input_val;
+ u8 select = val & 0xff;
+ u8 width = (val >> 8) & 0xff;
+ u8 shift = (val >> 16) & 0xff;
+ u32 mask = ((1 << width) - 1) << shift;
+ /*
+ * The input_reg[i] here is actually some IOMUXC general
+ * purpose register, not regular select input register.
+ */
+ val = readl(ipctl->base + pin->input_reg);
+ val &= ~mask;
+ val |= select << shift;
+ writel(val, ipctl->base + pin->input_reg);
+ } else if (pin->input_reg) {
+ /*
+ * Regular select input register can never be at offset
+ * 0, and we only print register value for regular case.
+ */
+ writel(pin->input_val, ipctl->base + pin->input_reg);
+ dev_dbg(ipctl->dev,
+ "==>select_input: offset 0x%x val 0x%x\n",
+ pin->input_reg, pin->input_val);
+ }
+ }
+
+ return 0;
+}
+
+static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ return info->nfunctions;
+}
+
+static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ return info->functions[selector].name;
+}
+
+static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ *groups = info->functions[selector].groups;
+ *num_groups = info->functions[selector].num_groups;
+
+ return 0;
+}
+
+static const struct pinmux_ops imx_pmx_ops = {
+ .get_functions_count = imx_pmx_get_funcs_count,
+ .get_function_name = imx_pmx_get_func_name,
+ .get_function_groups = imx_pmx_get_groups,
+ .set_mux = imx_pmx_set,
+};
+
+static int imx_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
+
+ if (pin_reg->conf_reg == -1) {
+ dev_err(info->dev, "Pin(%s) does not support config function\n",
+ info->pins[pin_id].name);
+ return -EINVAL;
+ }
+
+ *config = readl(ipctl->base + pin_reg->conf_reg);
+
+ if (info->flags & SHARE_MUX_CONF_REG)
+ *config &= 0xffff;
+
+ return 0;
+}
+
+static int imx_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
+ int i;
+
+ if (pin_reg->conf_reg == -1) {
+ dev_err(info->dev, "Pin(%s) does not support config function\n",
+ info->pins[pin_id].name);
+ return -EINVAL;
+ }
+
+ dev_dbg(ipctl->dev, "pinconf set pin %s\n",
+ info->pins[pin_id].name);
+
+ for (i = 0; i < num_configs; i++) {
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ u32 reg;
+ reg = readl(ipctl->base + pin_reg->conf_reg);
+ reg &= ~0xffff;
+ reg |= configs[i];
+ writel(reg, ipctl->base + pin_reg->conf_reg);
+ } else {
+ writel(configs[i], ipctl->base + pin_reg->conf_reg);
+ }
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
+ pin_reg->conf_reg, configs[i]);
+ } /* for each config */
+
+ return 0;
+}
+
+static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned pin_id)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
+ unsigned long config;
+
+ if (!pin_reg || !pin_reg->conf_reg) {
+ seq_printf(s, "N/A");
+ return;
+ }
+
+ config = readl(ipctl->base + pin_reg->conf_reg);
+ seq_printf(s, "0x%lx", config);
+}
+
+static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned group)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin_group *grp;
+ unsigned long config;
+ const char *name;
+ int i, ret;
+
+ if (group > info->ngroups)
+ return;
+
+ seq_printf(s, "\n");
+ grp = &info->groups[group];
+ for (i = 0; i < grp->npins; i++) {
+ struct imx_pin *pin = &grp->pins[i];
+ name = pin_get_name(pctldev, pin->pin);
+ ret = imx_pinconf_get(pctldev, pin->pin, &config);
+ if (ret)
+ return;
+ seq_printf(s, "%s: 0x%lx", name, config);
+ }
+}
+
+static const struct pinconf_ops imx_pinconf_ops = {
+ .pin_config_get = imx_pinconf_get,
+ .pin_config_set = imx_pinconf_set,
+ .pin_config_dbg_show = imx_pinconf_dbg_show,
+ .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc imx_pinctrl_desc = {
+ .pctlops = &imx_pctrl_ops,
+ .pmxops = &imx_pmx_ops,
+ .confops = &imx_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+/*
+ * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
+ * 1 u32 CONFIG, so 24 types in total for each pin.
+ */
+#define FSL_PIN_SIZE 24
+#define SHARE_FSL_PIN_SIZE 20
+
+static int imx_pinctrl_parse_groups(struct device_node *np,
+ struct imx_pin_group *grp,
+ struct imx_pinctrl_soc_info *info,
+ u32 index)
+{
+ int size, pin_size;
+ const __be32 *list;
+ int i;
+ u32 config;
+
+ dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+
+ if (info->flags & SHARE_MUX_CONF_REG)
+ pin_size = SHARE_FSL_PIN_SIZE;
+ else
+ pin_size = FSL_PIN_SIZE;
+ /* Initialise group */
+ grp->name = np->name;
+
+ /*
+ * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
+ * do sanity check and calculate pins number
+ */
+ list = of_get_property(np, "fsl,pins", &size);
+ if (!list) {
+ dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
+ return -EINVAL;
+ }
+
+ /* we do not check return since it's safe node passed down */
+ if (!size || size % pin_size) {
+ dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
+ return -EINVAL;
+ }
+
+ grp->npins = size / pin_size;
+ grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin),
+ GFP_KERNEL);
+ grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
+ GFP_KERNEL);
+ if (!grp->pins || ! grp->pin_ids)
+ return -ENOMEM;
+
+ for (i = 0; i < grp->npins; i++) {
+ u32 mux_reg = be32_to_cpu(*list++);
+ u32 conf_reg;
+ unsigned int pin_id;
+ struct imx_pin_reg *pin_reg;
+ struct imx_pin *pin = &grp->pins[i];
+
+ if (info->flags & SHARE_MUX_CONF_REG)
+ conf_reg = mux_reg;
+ else
+ conf_reg = be32_to_cpu(*list++);
+
+ pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+ pin_reg = &info->pin_regs[pin_id];
+ pin->pin = pin_id;
+ grp->pin_ids[i] = pin_id;
+ pin_reg->mux_reg = mux_reg;
+ pin_reg->conf_reg = conf_reg;
+ pin->input_reg = be32_to_cpu(*list++);
+ pin->mux_mode = be32_to_cpu(*list++);
+ pin->input_val = be32_to_cpu(*list++);
+
+ /* SION bit is in mux register */
+ config = be32_to_cpu(*list++);
+ if (config & IMX_PAD_SION)
+ pin->mux_mode |= IOMUXC_CONFIG_SION;
+ pin->config = config & ~IMX_PAD_SION;
+
+ dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
+ pin->mux_mode, pin->config);
+ }
+
+ return 0;
+}
+
+static int imx_pinctrl_parse_functions(struct device_node *np,
+ struct imx_pinctrl_soc_info *info,
+ u32 index)
+{
+ struct device_node *child;
+ struct imx_pmx_func *func;
+ struct imx_pin_group *grp;
+ static u32 grp_index;
+ u32 i = 0;
+
+ dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
+
+ func = &info->functions[index];
+
+ /* Initialise function */
+ func->name = np->name;
+ func->num_groups = of_get_child_count(np);
+ if (func->num_groups == 0) {
+ dev_err(info->dev, "no groups defined in %s\n", np->full_name);
+ return -EINVAL;
+ }
+ func->groups = devm_kzalloc(info->dev,
+ func->num_groups * sizeof(char *), GFP_KERNEL);
+
+ for_each_child_of_node(np, child) {
+ func->groups[i] = child->name;
+ grp = &info->groups[grp_index++];
+ imx_pinctrl_parse_groups(child, grp, info, i++);
+ }
+
+ return 0;
+}
+
+static int imx_pinctrl_probe_dt(struct platform_device *pdev,
+ struct imx_pinctrl_soc_info *info)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *child;
+ u32 nfuncs = 0;
+ u32 i = 0;
+
+ if (!np)
+ return -ENODEV;
+
+ nfuncs = of_get_child_count(np);
+ if (nfuncs <= 0) {
+ dev_err(&pdev->dev, "no functions defined\n");
+ return -EINVAL;
+ }
+
+ info->nfunctions = nfuncs;
+ info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
+ GFP_KERNEL);
+ if (!info->functions)
+ return -ENOMEM;
+
+ info->ngroups = 0;
+ for_each_child_of_node(np, child)
+ info->ngroups += of_get_child_count(child);
+ info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
+ GFP_KERNEL);
+ if (!info->groups)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child)
+ imx_pinctrl_parse_functions(child, info, i++);
+
+ return 0;
+}
+
+int imx_pinctrl_probe(struct platform_device *pdev,
+ struct imx_pinctrl_soc_info *info)
+{
+ struct imx_pinctrl *ipctl;
+ struct resource *res;
+ int ret;
+
+ if (!info || !info->pins || !info->npins) {
+ dev_err(&pdev->dev, "wrong pinctrl info\n");
+ return -EINVAL;
+ }
+ info->dev = &pdev->dev;
+
+ /* Create state holders etc for this driver */
+ ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
+ if (!ipctl)
+ return -ENOMEM;
+
+ info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) *
+ info->npins, GFP_KERNEL);
+ if (!info->pin_regs)
+ return -ENOMEM;
+ memset(info->pin_regs, 0xff, sizeof(*info->pin_regs) * info->npins);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ipctl->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ipctl->base))
+ return PTR_ERR(ipctl->base);
+
+ imx_pinctrl_desc.name = dev_name(&pdev->dev);
+ imx_pinctrl_desc.pins = info->pins;
+ imx_pinctrl_desc.npins = info->npins;
+
+ ret = imx_pinctrl_probe_dt(pdev, info);
+ if (ret) {
+ dev_err(&pdev->dev, "fail to probe dt properties\n");
+ return ret;
+ }
+
+ ipctl->info = info;
+ ipctl->dev = info->dev;
+ platform_set_drvdata(pdev, ipctl);
+ ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
+ if (!ipctl->pctl) {
+ dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
+ return -EINVAL;
+ }
+
+ dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
+
+ return 0;
+}
+
+int imx_pinctrl_remove(struct platform_device *pdev)
+{
+ struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(ipctl->pctl);
+
+ return 0;
+}
--- /dev/null
+/*
+ * IMX pinmux core definitions
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DRIVERS_PINCTRL_IMX_H
+#define __DRIVERS_PINCTRL_IMX_H
+
+struct platform_device;
+
+/**
+ * struct imx_pin_group - describes a single i.MX pin
+ * @pin: the pin_id of this pin
+ * @mux_mode: the mux mode for this pin.
+ * @input_reg: the select input register offset for this pin if any
+ * 0 if no select input setting needed.
+ * @input_val: the select input value for this pin.
+ * @configs: the config for this pin.
+ */
+struct imx_pin {
+ unsigned int pin;
+ unsigned int mux_mode;
+ u16 input_reg;
+ unsigned int input_val;
+ unsigned long config;
+};
+
+/**
+ * struct imx_pin_group - describes an IMX pin group
+ * @name: the name of this specific pin group
+ * @npins: the number of pins in this group array, i.e. the number of
+ * elements in .pins so we can iterate over that array
+ * @pin_ids: array of pin_ids. pinctrl forces us to maintain such an array
+ * @pins: array of pins
+ */
+struct imx_pin_group {
+ const char *name;
+ unsigned npins;
+ unsigned int *pin_ids;
+ struct imx_pin *pins;
+};
+
+/**
+ * struct imx_pmx_func - describes IMX pinmux functions
+ * @name: the name of this specific function
+ * @groups: corresponding pin groups
+ * @num_groups: the number of groups
+ */
+struct imx_pmx_func {
+ const char *name;
+ const char **groups;
+ unsigned num_groups;
+};
+
+/**
+ * struct imx_pin_reg - describe a pin reg map
+ * @mux_reg: mux register offset
+ * @conf_reg: config register offset
+ */
+struct imx_pin_reg {
+ s16 mux_reg;
+ s16 conf_reg;
+};
+
+struct imx_pinctrl_soc_info {
+ struct device *dev;
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ struct imx_pin_reg *pin_regs;
+ struct imx_pin_group *groups;
+ unsigned int ngroups;
+ struct imx_pmx_func *functions;
+ unsigned int nfunctions;
+ unsigned int flags;
+};
+
+#define SHARE_MUX_CONF_REG 0x1
+
+#define NO_MUX 0x0
+#define NO_PAD 0x0
+
+#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+
+#define PAD_CTL_MASK(len) ((1 << len) - 1)
+#define IMX_MUX_MASK 0x7
+#define IOMUXC_CONFIG_SION (0x1 << 4)
+
+int imx_pinctrl_probe(struct platform_device *pdev,
+ struct imx_pinctrl_soc_info *info);
+int imx_pinctrl_remove(struct platform_device *pdev);
+#endif /* __DRIVERS_PINCTRL_IMX_H */
--- /dev/null
+/*
+ * Core driver for the imx pin controller in imx1/21/27
+ *
+ * Copyright (C) 2013 Pengutronix
+ * Author: Markus Pargmann <mpa@pengutronix.de>
+ *
+ * Based on pinctrl-imx.c:
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "pinctrl-imx1.h"
+
+struct imx1_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ void __iomem *base;
+ const struct imx1_pinctrl_soc_info *info;
+};
+
+/*
+ * MX1 register offsets
+ */
+
+#define MX1_DDIR 0x00
+#define MX1_OCR 0x04
+#define MX1_ICONFA 0x0c
+#define MX1_ICONFB 0x14
+#define MX1_GIUS 0x20
+#define MX1_GPR 0x38
+#define MX1_PUEN 0x40
+
+#define MX1_PORT_STRIDE 0x100
+
+
+/*
+ * MUX_ID format defines
+ */
+#define MX1_MUX_FUNCTION(val) (BIT(0) & val)
+#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
+#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
+#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
+#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
+#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
+
+
+/*
+ * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
+ * control register are seperated into function, output configuration, input
+ * configuration A, input configuration B, GPIO in use and data direction.
+ *
+ * Those controls that are represented by 1 bit have a direct mapping between
+ * bit position and pin id. If they are represented by 2 bit, the lower 16 pins
+ * are in the first register and the upper 16 pins in the second (next)
+ * register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
+ */
+
+/*
+ * Calculates the register offset from a pin_id
+ */
+static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
+{
+ unsigned int port = pin_id / 32;
+ return ipctl->base + port * MX1_PORT_STRIDE;
+}
+
+/*
+ * Write to a register with 2 bits per pin. The function will automatically
+ * use the next register if the pin is managed in the second register.
+ */
+static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 value, u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
+ int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
+ u32 old_val;
+ u32 new_val;
+
+ /* Use the next register if the pin's port pin number is >=16 */
+ if (pin_id % 32 >= 16)
+ reg += 0x04;
+
+ dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
+ reg, offset, value);
+
+ /* Get current state of pins */
+ old_val = readl(reg);
+ old_val &= mask;
+
+ new_val = value & 0x3; /* Make sure value is really 2 bit */
+ new_val <<= offset;
+ new_val |= old_val;/* Set new state for pin_id */
+
+ writel(new_val, reg);
+}
+
+static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 value, u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = pin_id % 32;
+ int mask = ~BIT_MASK(offset);
+ u32 old_val;
+ u32 new_val;
+
+ /* Get current state of pins */
+ old_val = readl(reg);
+ old_val &= mask;
+
+ new_val = value & 0x1; /* Make sure value is really 1 bit */
+ new_val <<= offset;
+ new_val |= old_val;/* Set new state for pin_id */
+
+ writel(new_val, reg);
+}
+
+static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = (pin_id % 16) * 2;
+
+ /* Use the next register if the pin's port pin number is >=16 */
+ if (pin_id % 32 >= 16)
+ reg += 0x04;
+
+ return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
+}
+
+static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = pin_id % 32;
+
+ return !!(readl(reg) & BIT(offset));
+}
+
+static const inline struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
+ const struct imx1_pinctrl_soc_info *info,
+ const char *name)
+{
+ const struct imx1_pin_group *grp = NULL;
+ int i;
+
+ for (i = 0; i < info->ngroups; i++) {
+ if (!strcmp(info->groups[i].name, name)) {
+ grp = &info->groups[i];
+ break;
+ }
+ }
+
+ return grp;
+}
+
+static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->ngroups;
+}
+
+static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->groups[selector].name;
+}
+
+static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
+ const unsigned int **pins,
+ unsigned *npins)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ if (selector >= info->ngroups)
+ return -EINVAL;
+
+ *pins = info->groups[selector].pin_ids;
+ *npins = info->groups[selector].npins;
+
+ return 0;
+}
+
+static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+ unsigned offset)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
+ imx1_read_bit(ipctl, offset, MX1_GIUS),
+ imx1_read_bit(ipctl, offset, MX1_GPR),
+ imx1_read_bit(ipctl, offset, MX1_DDIR),
+ imx1_read_2bit(ipctl, offset, MX1_OCR),
+ imx1_read_2bit(ipctl, offset, MX1_ICONFA),
+ imx1_read_2bit(ipctl, offset, MX1_ICONFB));
+}
+
+static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map, unsigned *num_maps)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ const struct imx1_pin_group *grp;
+ struct pinctrl_map *new_map;
+ struct device_node *parent;
+ int map_num = 1;
+ int i, j;
+
+ /*
+ * first find the group of this node and check if we need create
+ * config maps for pins
+ */
+ grp = imx1_pinctrl_find_group_by_name(info, np->name);
+ if (!grp) {
+ dev_err(info->dev, "unable to find group for node %s\n",
+ np->name);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < grp->npins; i++)
+ map_num++;
+
+ new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
+ if (!new_map)
+ return -ENOMEM;
+
+ *map = new_map;
+ *num_maps = map_num;
+
+ /* create mux map */
+ parent = of_get_parent(np);
+ if (!parent) {
+ kfree(new_map);
+ return -EINVAL;
+ }
+ new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+ new_map[0].data.mux.function = parent->name;
+ new_map[0].data.mux.group = np->name;
+ of_node_put(parent);
+
+ /* create config map */
+ new_map++;
+ for (i = j = 0; i < grp->npins; i++) {
+ new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ new_map[j].data.configs.group_or_pin =
+ pin_get_name(pctldev, grp->pins[i].pin_id);
+ new_map[j].data.configs.configs = &grp->pins[i].config;
+ new_map[j].data.configs.num_configs = 1;
+ j++;
+ }
+
+ dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
+ (*map)->data.mux.function, (*map)->data.mux.group, map_num);
+
+ return 0;
+}
+
+static void imx1_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned num_maps)
+{
+ kfree(map);
+}
+
+static const struct pinctrl_ops imx1_pctrl_ops = {
+ .get_groups_count = imx1_get_groups_count,
+ .get_group_name = imx1_get_group_name,
+ .get_group_pins = imx1_get_group_pins,
+ .pin_dbg_show = imx1_pin_dbg_show,
+ .dt_node_to_map = imx1_dt_node_to_map,
+ .dt_free_map = imx1_dt_free_map,
+
+};
+
+static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ const struct imx1_pin *pins;
+ unsigned int npins;
+ int i;
+
+ /*
+ * Configure the mux mode for each pin in the group for a specific
+ * function.
+ */
+ pins = info->groups[group].pins;
+ npins = info->groups[group].npins;
+
+ WARN_ON(!pins || !npins);
+
+ dev_dbg(ipctl->dev, "enable function %s group %s\n",
+ info->functions[selector].name, info->groups[group].name);
+
+ for (i = 0; i < npins; i++) {
+ unsigned int mux = pins[i].mux_id;
+ unsigned int pin_id = pins[i].pin_id;
+ unsigned int afunction = MX1_MUX_FUNCTION(mux);
+ unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
+ unsigned int direction = MX1_MUX_DIR(mux);
+ unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
+ unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
+ unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
+
+ dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
+ __func__, pin_id, afunction, gpio_in_use,
+ direction, gpio_oconf, gpio_iconfa,
+ gpio_iconfb);
+
+ imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
+ imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
+
+ if (gpio_in_use) {
+ imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
+ imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
+ MX1_ICONFA);
+ imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
+ MX1_ICONFB);
+ } else {
+ imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
+ }
+ }
+
+ return 0;
+}
+
+static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->nfunctions;
+}
+
+static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->functions[selector].name;
+}
+
+static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ *groups = info->functions[selector].groups;
+ *num_groups = info->functions[selector].num_groups;
+
+ return 0;
+}
+
+static const struct pinmux_ops imx1_pmx_ops = {
+ .get_functions_count = imx1_pmx_get_funcs_count,
+ .get_function_name = imx1_pmx_get_func_name,
+ .get_function_groups = imx1_pmx_get_groups,
+ .set_mux = imx1_pmx_set,
+};
+
+static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
+
+ return 0;
+}
+
+static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ int i;
+
+ for (i = 0; i != num_configs; ++i) {
+ imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
+
+ dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
+ info->pins[pin_id].name);
+ }
+
+ return 0;
+}
+
+static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned pin_id)
+{
+ unsigned long config;
+
+ imx1_pinconf_get(pctldev, pin_id, &config);
+ seq_printf(s, "0x%lx", config);
+}
+
+static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned group)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ struct imx1_pin_group *grp;
+ unsigned long config;
+ const char *name;
+ int i, ret;
+
+ if (group > info->ngroups)
+ return;
+
+ seq_puts(s, "\n");
+ grp = &info->groups[group];
+ for (i = 0; i < grp->npins; i++) {
+ name = pin_get_name(pctldev, grp->pins[i].pin_id);
+ ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config);
+ if (ret)
+ return;
+ seq_printf(s, "%s: 0x%lx", name, config);
+ }
+}
+
+static const struct pinconf_ops imx1_pinconf_ops = {
+ .pin_config_get = imx1_pinconf_get,
+ .pin_config_set = imx1_pinconf_set,
+ .pin_config_dbg_show = imx1_pinconf_dbg_show,
+ .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc imx1_pinctrl_desc = {
+ .pctlops = &imx1_pctrl_ops,
+ .pmxops = &imx1_pmx_ops,
+ .confops = &imx1_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static int imx1_pinctrl_parse_groups(struct device_node *np,
+ struct imx1_pin_group *grp,
+ struct imx1_pinctrl_soc_info *info,
+ u32 index)
+{
+ int size;
+ const __be32 *list;
+ int i;
+
+ dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+
+ /* Initialise group */
+ grp->name = np->name;
+
+ /*
+ * the binding format is fsl,pins = <PIN MUX_ID CONFIG>
+ */
+ list = of_get_property(np, "fsl,pins", &size);
+ /* we do not check return since it's safe node passed down */
+ if (!size || size % 12) {
+ dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n",
+ np->name);
+ return -EINVAL;
+ }
+
+ grp->npins = size / 12;
+ grp->pins = devm_kzalloc(info->dev,
+ grp->npins * sizeof(struct imx1_pin), GFP_KERNEL);
+ grp->pin_ids = devm_kzalloc(info->dev,
+ grp->npins * sizeof(unsigned int), GFP_KERNEL);
+
+ if (!grp->pins || !grp->pin_ids)
+ return -ENOMEM;
+
+ for (i = 0; i < grp->npins; i++) {
+ grp->pins[i].pin_id = be32_to_cpu(*list++);
+ grp->pins[i].mux_id = be32_to_cpu(*list++);
+ grp->pins[i].config = be32_to_cpu(*list++);
+
+ grp->pin_ids[i] = grp->pins[i].pin_id;
+ }
+
+ return 0;
+}
+
+static int imx1_pinctrl_parse_functions(struct device_node *np,
+ struct imx1_pinctrl_soc_info *info,
+ u32 index)
+{
+ struct device_node *child;
+ struct imx1_pmx_func *func;
+ struct imx1_pin_group *grp;
+ int ret;
+ static u32 grp_index;
+ u32 i = 0;
+
+ dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
+
+ func = &info->functions[index];
+
+ /* Initialise function */
+ func->name = np->name;
+ func->num_groups = of_get_child_count(np);
+ if (func->num_groups == 0)
+ return -EINVAL;
+
+ func->groups = devm_kzalloc(info->dev,
+ func->num_groups * sizeof(char *), GFP_KERNEL);
+
+ if (!func->groups)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ func->groups[i] = child->name;
+ grp = &info->groups[grp_index++];
+ ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
+ if (ret == -ENOMEM)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
+ struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *child;
+ int ret;
+ u32 nfuncs = 0;
+ u32 ngroups = 0;
+ u32 ifunc = 0;
+
+ if (!np)
+ return -ENODEV;
+
+ for_each_child_of_node(np, child) {
+ ++nfuncs;
+ ngroups += of_get_child_count(child);
+ }
+
+ if (!nfuncs) {
+ dev_err(&pdev->dev, "No pin functions defined\n");
+ return -EINVAL;
+ }
+
+ info->nfunctions = nfuncs;
+ info->functions = devm_kzalloc(&pdev->dev,
+ nfuncs * sizeof(struct imx1_pmx_func), GFP_KERNEL);
+
+ info->ngroups = ngroups;
+ info->groups = devm_kzalloc(&pdev->dev,
+ ngroups * sizeof(struct imx1_pin_group), GFP_KERNEL);
+
+
+ if (!info->functions || !info->groups)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
+ if (ret == -ENOMEM)
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+int imx1_pinctrl_core_probe(struct platform_device *pdev,
+ struct imx1_pinctrl_soc_info *info)
+{
+ struct imx1_pinctrl *ipctl;
+ struct resource *res;
+ struct pinctrl_desc *pctl_desc;
+ int ret;
+
+ if (!info || !info->pins || !info->npins) {
+ dev_err(&pdev->dev, "wrong pinctrl info\n");
+ return -EINVAL;
+ }
+ info->dev = &pdev->dev;
+
+ /* Create state holders etc for this driver */
+ ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
+ if (!ipctl)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENOENT;
+
+ ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start,
+ resource_size(res));
+ if (!ipctl->base)
+ return -ENOMEM;
+
+ pctl_desc = &imx1_pinctrl_desc;
+ pctl_desc->name = dev_name(&pdev->dev);
+ pctl_desc->pins = info->pins;
+ pctl_desc->npins = info->npins;
+
+ ret = imx1_pinctrl_parse_dt(pdev, ipctl, info);
+ if (ret) {
+ dev_err(&pdev->dev, "fail to probe dt properties\n");
+ return ret;
+ }
+
+ ipctl->info = info;
+ ipctl->dev = info->dev;
+ platform_set_drvdata(pdev, ipctl);
+ ipctl->pctl = pinctrl_register(pctl_desc, &pdev->dev, ipctl);
+ if (!ipctl->pctl) {
+ dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
+ return -EINVAL;
+ }
+
+ ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
+ if (ret) {
+ pinctrl_unregister(ipctl->pctl);
+ dev_err(&pdev->dev, "Failed to populate subdevices\n");
+ return ret;
+ }
+
+ dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
+
+ return 0;
+}
+
+int imx1_pinctrl_core_remove(struct platform_device *pdev)
+{
+ struct imx1_pinctrl *ipctl = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(ipctl->pctl);
+
+ return 0;
+}
--- /dev/null
+/*
+ * i.MX1 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx1.h"
+
+#define PAD_ID(port, pin) ((port) * 32 + (pin))
+#define PA 0
+#define PB 1
+#define PC 2
+#define PD 3
+
+enum imx1_pads {
+ MX1_PAD_A24 = PAD_ID(PA, 0),
+ MX1_PAD_TIN = PAD_ID(PA, 1),
+ MX1_PAD_PWMO = PAD_ID(PA, 2),
+ MX1_PAD_CSI_MCLK = PAD_ID(PA, 3),
+ MX1_PAD_CSI_D0 = PAD_ID(PA, 4),
+ MX1_PAD_CSI_D1 = PAD_ID(PA, 5),
+ MX1_PAD_CSI_D2 = PAD_ID(PA, 6),
+ MX1_PAD_CSI_D3 = PAD_ID(PA, 7),
+ MX1_PAD_CSI_D4 = PAD_ID(PA, 8),
+ MX1_PAD_CSI_D5 = PAD_ID(PA, 9),
+ MX1_PAD_CSI_D6 = PAD_ID(PA, 10),
+ MX1_PAD_CSI_D7 = PAD_ID(PA, 11),
+ MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12),
+ MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13),
+ MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14),
+ MX1_PAD_I2C_SDA = PAD_ID(PA, 15),
+ MX1_PAD_I2C_SCL = PAD_ID(PA, 16),
+ MX1_PAD_DTACK = PAD_ID(PA, 17),
+ MX1_PAD_BCLK = PAD_ID(PA, 18),
+ MX1_PAD_LBA = PAD_ID(PA, 19),
+ MX1_PAD_ECB = PAD_ID(PA, 20),
+ MX1_PAD_A0 = PAD_ID(PA, 21),
+ MX1_PAD_CS4 = PAD_ID(PA, 22),
+ MX1_PAD_CS5 = PAD_ID(PA, 23),
+ MX1_PAD_A16 = PAD_ID(PA, 24),
+ MX1_PAD_A17 = PAD_ID(PA, 25),
+ MX1_PAD_A18 = PAD_ID(PA, 26),
+ MX1_PAD_A19 = PAD_ID(PA, 27),
+ MX1_PAD_A20 = PAD_ID(PA, 28),
+ MX1_PAD_A21 = PAD_ID(PA, 29),
+ MX1_PAD_A22 = PAD_ID(PA, 30),
+ MX1_PAD_A23 = PAD_ID(PA, 31),
+ MX1_PAD_SD_DAT0 = PAD_ID(PB, 8),
+ MX1_PAD_SD_DAT1 = PAD_ID(PB, 9),
+ MX1_PAD_SD_DAT2 = PAD_ID(PB, 10),
+ MX1_PAD_SD_DAT3 = PAD_ID(PB, 11),
+ MX1_PAD_SD_SCLK = PAD_ID(PB, 12),
+ MX1_PAD_SD_CMD = PAD_ID(PB, 13),
+ MX1_PAD_SIM_SVEN = PAD_ID(PB, 14),
+ MX1_PAD_SIM_PD = PAD_ID(PB, 15),
+ MX1_PAD_SIM_TX = PAD_ID(PB, 16),
+ MX1_PAD_SIM_RX = PAD_ID(PB, 17),
+ MX1_PAD_SIM_RST = PAD_ID(PB, 18),
+ MX1_PAD_SIM_CLK = PAD_ID(PB, 19),
+ MX1_PAD_USBD_AFE = PAD_ID(PB, 20),
+ MX1_PAD_USBD_OE = PAD_ID(PB, 21),
+ MX1_PAD_USBD_RCV = PAD_ID(PB, 22),
+ MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23),
+ MX1_PAD_USBD_VP = PAD_ID(PB, 24),
+ MX1_PAD_USBD_VM = PAD_ID(PB, 25),
+ MX1_PAD_USBD_VPO = PAD_ID(PB, 26),
+ MX1_PAD_USBD_VMO = PAD_ID(PB, 27),
+ MX1_PAD_UART2_CTS = PAD_ID(PB, 28),
+ MX1_PAD_UART2_RTS = PAD_ID(PB, 29),
+ MX1_PAD_UART2_TXD = PAD_ID(PB, 30),
+ MX1_PAD_UART2_RXD = PAD_ID(PB, 31),
+ MX1_PAD_SSI_RXFS = PAD_ID(PC, 3),
+ MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4),
+ MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5),
+ MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6),
+ MX1_PAD_SSI_TXFS = PAD_ID(PC, 7),
+ MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8),
+ MX1_PAD_UART1_CTS = PAD_ID(PC, 9),
+ MX1_PAD_UART1_RTS = PAD_ID(PC, 10),
+ MX1_PAD_UART1_TXD = PAD_ID(PC, 11),
+ MX1_PAD_UART1_RXD = PAD_ID(PC, 12),
+ MX1_PAD_SPI1_RDY = PAD_ID(PC, 13),
+ MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14),
+ MX1_PAD_SPI1_SS = PAD_ID(PC, 15),
+ MX1_PAD_SPI1_MISO = PAD_ID(PC, 16),
+ MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17),
+ MX1_PAD_BT13 = PAD_ID(PC, 19),
+ MX1_PAD_BT12 = PAD_ID(PC, 20),
+ MX1_PAD_BT11 = PAD_ID(PC, 21),
+ MX1_PAD_BT10 = PAD_ID(PC, 22),
+ MX1_PAD_BT9 = PAD_ID(PC, 23),
+ MX1_PAD_BT8 = PAD_ID(PC, 24),
+ MX1_PAD_BT7 = PAD_ID(PC, 25),
+ MX1_PAD_BT6 = PAD_ID(PC, 26),
+ MX1_PAD_BT5 = PAD_ID(PC, 27),
+ MX1_PAD_BT4 = PAD_ID(PC, 28),
+ MX1_PAD_BT3 = PAD_ID(PC, 29),
+ MX1_PAD_BT2 = PAD_ID(PC, 30),
+ MX1_PAD_BT1 = PAD_ID(PC, 31),
+ MX1_PAD_LSCLK = PAD_ID(PD, 6),
+ MX1_PAD_REV = PAD_ID(PD, 7),
+ MX1_PAD_CLS = PAD_ID(PD, 8),
+ MX1_PAD_PS = PAD_ID(PD, 9),
+ MX1_PAD_SPL_SPR = PAD_ID(PD, 10),
+ MX1_PAD_CONTRAST = PAD_ID(PD, 11),
+ MX1_PAD_ACD_OE = PAD_ID(PD, 12),
+ MX1_PAD_LP_HSYNC = PAD_ID(PD, 13),
+ MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14),
+ MX1_PAD_LD0 = PAD_ID(PD, 15),
+ MX1_PAD_LD1 = PAD_ID(PD, 16),
+ MX1_PAD_LD2 = PAD_ID(PD, 17),
+ MX1_PAD_LD3 = PAD_ID(PD, 18),
+ MX1_PAD_LD4 = PAD_ID(PD, 19),
+ MX1_PAD_LD5 = PAD_ID(PD, 20),
+ MX1_PAD_LD6 = PAD_ID(PD, 21),
+ MX1_PAD_LD7 = PAD_ID(PD, 22),
+ MX1_PAD_LD8 = PAD_ID(PD, 23),
+ MX1_PAD_LD9 = PAD_ID(PD, 24),
+ MX1_PAD_LD10 = PAD_ID(PD, 25),
+ MX1_PAD_LD11 = PAD_ID(PD, 26),
+ MX1_PAD_LD12 = PAD_ID(PD, 27),
+ MX1_PAD_LD13 = PAD_ID(PD, 28),
+ MX1_PAD_LD14 = PAD_ID(PD, 29),
+ MX1_PAD_LD15 = PAD_ID(PD, 30),
+ MX1_PAD_TMR2OUT = PAD_ID(PD, 31),
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX1_PAD_A24),
+ IMX_PINCTRL_PIN(MX1_PAD_TIN),
+ IMX_PINCTRL_PIN(MX1_PAD_PWMO),
+ IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK),
+ IMX_PINCTRL_PIN(MX1_PAD_CSI_D0),
+ IMX_PINCTRL_PIN(MX1_PAD_CSI_D1),
+ IMX_PINCTRL_PIN(MX1_PAD_CSI_D2),
+ IMX_PINCTRL_PIN(MX1_PAD_CSI_D3),
+ IMX_PINCTRL_PIN(MX1_PAD_CSI_D4),
+ IMX_PINCTRL_PIN(MX1_PAD_CSI_D5),
+ IMX_PINCTRL_PIN(MX1_PAD_CSI_D6),
+ IMX_PINCTRL_PIN(MX1_PAD_CSI_D7),
+ IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC),
+ IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC),
+ IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK),
+ IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA),
+ IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL),
+ IMX_PINCTRL_PIN(MX1_PAD_DTACK),
+ IMX_PINCTRL_PIN(MX1_PAD_BCLK),
+ IMX_PINCTRL_PIN(MX1_PAD_LBA),
+ IMX_PINCTRL_PIN(MX1_PAD_ECB),
+ IMX_PINCTRL_PIN(MX1_PAD_A0),
+ IMX_PINCTRL_PIN(MX1_PAD_CS4),
+ IMX_PINCTRL_PIN(MX1_PAD_CS5),
+ IMX_PINCTRL_PIN(MX1_PAD_A16),
+ IMX_PINCTRL_PIN(MX1_PAD_A17),
+ IMX_PINCTRL_PIN(MX1_PAD_A18),
+ IMX_PINCTRL_PIN(MX1_PAD_A19),
+ IMX_PINCTRL_PIN(MX1_PAD_A20),
+ IMX_PINCTRL_PIN(MX1_PAD_A21),
+ IMX_PINCTRL_PIN(MX1_PAD_A22),
+ IMX_PINCTRL_PIN(MX1_PAD_A23),
+ IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0),
+ IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1),
+ IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2),
+ IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3),
+ IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK),
+ IMX_PINCTRL_PIN(MX1_PAD_SD_CMD),
+ IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN),
+ IMX_PINCTRL_PIN(MX1_PAD_SIM_PD),
+ IMX_PINCTRL_PIN(MX1_PAD_SIM_TX),
+ IMX_PINCTRL_PIN(MX1_PAD_SIM_RX),
+ IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK),
+ IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE),
+ IMX_PINCTRL_PIN(MX1_PAD_USBD_OE),
+ IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV),
+ IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND),
+ IMX_PINCTRL_PIN(MX1_PAD_USBD_VP),
+ IMX_PINCTRL_PIN(MX1_PAD_USBD_VM),
+ IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO),
+ IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO),
+ IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS),
+ IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS),
+ IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD),
+ IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD),
+ IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS),
+ IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK),
+ IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT),
+ IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT),
+ IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS),
+ IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK),
+ IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS),
+ IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS),
+ IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY),
+ IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK),
+ IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS),
+ IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO),
+ IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI),
+ IMX_PINCTRL_PIN(MX1_PAD_BT13),
+ IMX_PINCTRL_PIN(MX1_PAD_BT12),
+ IMX_PINCTRL_PIN(MX1_PAD_BT11),
+ IMX_PINCTRL_PIN(MX1_PAD_BT10),
+ IMX_PINCTRL_PIN(MX1_PAD_BT9),
+ IMX_PINCTRL_PIN(MX1_PAD_BT8),
+ IMX_PINCTRL_PIN(MX1_PAD_BT7),
+ IMX_PINCTRL_PIN(MX1_PAD_BT6),
+ IMX_PINCTRL_PIN(MX1_PAD_BT5),
+ IMX_PINCTRL_PIN(MX1_PAD_BT4),
+ IMX_PINCTRL_PIN(MX1_PAD_BT3),
+ IMX_PINCTRL_PIN(MX1_PAD_BT2),
+ IMX_PINCTRL_PIN(MX1_PAD_BT1),
+ IMX_PINCTRL_PIN(MX1_PAD_LSCLK),
+ IMX_PINCTRL_PIN(MX1_PAD_REV),
+ IMX_PINCTRL_PIN(MX1_PAD_CLS),
+ IMX_PINCTRL_PIN(MX1_PAD_PS),
+ IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR),
+ IMX_PINCTRL_PIN(MX1_PAD_CONTRAST),
+ IMX_PINCTRL_PIN(MX1_PAD_ACD_OE),
+ IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC),
+ IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC),
+ IMX_PINCTRL_PIN(MX1_PAD_LD0),
+ IMX_PINCTRL_PIN(MX1_PAD_LD1),
+ IMX_PINCTRL_PIN(MX1_PAD_LD2),
+ IMX_PINCTRL_PIN(MX1_PAD_LD3),
+ IMX_PINCTRL_PIN(MX1_PAD_LD4),
+ IMX_PINCTRL_PIN(MX1_PAD_LD5),
+ IMX_PINCTRL_PIN(MX1_PAD_LD6),
+ IMX_PINCTRL_PIN(MX1_PAD_LD7),
+ IMX_PINCTRL_PIN(MX1_PAD_LD8),
+ IMX_PINCTRL_PIN(MX1_PAD_LD9),
+ IMX_PINCTRL_PIN(MX1_PAD_LD10),
+ IMX_PINCTRL_PIN(MX1_PAD_LD11),
+ IMX_PINCTRL_PIN(MX1_PAD_LD12),
+ IMX_PINCTRL_PIN(MX1_PAD_LD13),
+ IMX_PINCTRL_PIN(MX1_PAD_LD14),
+ IMX_PINCTRL_PIN(MX1_PAD_LD15),
+ IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT),
+};
+
+static struct imx1_pinctrl_soc_info imx1_pinctrl_info = {
+ .pins = imx1_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx1_pinctrl_pads),
+};
+
+static int __init imx1_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info);
+}
+
+static const struct of_device_id imx1_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx1-iomuxc", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, imx1_pinctrl_of_match);
+
+static struct platform_driver imx1_pinctrl_driver = {
+ .driver = {
+ .name = "imx1-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = imx1_pinctrl_of_match,
+ },
+ .remove = imx1_pinctrl_core_remove,
+};
+module_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);
+
+MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
+MODULE_DESCRIPTION("Freescale i.MX1 pinctrl driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * IMX pinmux core definitions
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DRIVERS_PINCTRL_IMX1_H
+#define __DRIVERS_PINCTRL_IMX1_H
+
+struct platform_device;
+
+/**
+ * struct imx1_pin - describes an IMX1/21/27 pin.
+ * @pin_id: ID of the described pin.
+ * @mux_id: ID of the mux setup.
+ * @config: Configuration of the pin (currently only pullup-enable).
+ */
+struct imx1_pin {
+ unsigned int pin_id;
+ unsigned int mux_id;
+ unsigned long config;
+};
+
+/**
+ * struct imx1_pin_group - describes an IMX pin group
+ * @name: the name of this specific pin group
+ * @pins: an array of imx1_pin structs used in this group
+ * @npins: the number of pins in this group array, i.e. the number of
+ * elements in .pins so we can iterate over that array
+ */
+struct imx1_pin_group {
+ const char *name;
+ unsigned int *pin_ids;
+ struct imx1_pin *pins;
+ unsigned npins;
+};
+
+/**
+ * struct imx1_pmx_func - describes IMX pinmux functions
+ * @name: the name of this specific function
+ * @groups: corresponding pin groups
+ * @num_groups: the number of groups
+ */
+struct imx1_pmx_func {
+ const char *name;
+ const char **groups;
+ unsigned num_groups;
+};
+
+struct imx1_pinctrl_soc_info {
+ struct device *dev;
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ struct imx1_pin_group *groups;
+ unsigned int ngroups;
+ struct imx1_pmx_func *functions;
+ unsigned int nfunctions;
+};
+
+#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+
+int imx1_pinctrl_core_probe(struct platform_device *pdev,
+ struct imx1_pinctrl_soc_info *info);
+int imx1_pinctrl_core_remove(struct platform_device *pdev);
+#endif /* __DRIVERS_PINCTRL_IMX1_H */
--- /dev/null
+/*
+ * i.MX21 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx1.h"
+
+#define PAD_ID(port, pin) ((port) * 32 + (pin))
+#define PA 0
+#define PB 1
+#define PC 2
+#define PD 3
+#define PE 4
+#define PF 5
+
+enum imx21_pads {
+ MX21_PAD_LSCLK = PAD_ID(PA, 5),
+ MX21_PAD_LD0 = PAD_ID(PA, 6),
+ MX21_PAD_LD1 = PAD_ID(PA, 7),
+ MX21_PAD_LD2 = PAD_ID(PA, 8),
+ MX21_PAD_LD3 = PAD_ID(PA, 9),
+ MX21_PAD_LD4 = PAD_ID(PA, 10),
+ MX21_PAD_LD5 = PAD_ID(PA, 11),
+ MX21_PAD_LD6 = PAD_ID(PA, 12),
+ MX21_PAD_LD7 = PAD_ID(PA, 13),
+ MX21_PAD_LD8 = PAD_ID(PA, 14),
+ MX21_PAD_LD9 = PAD_ID(PA, 15),
+ MX21_PAD_LD10 = PAD_ID(PA, 16),
+ MX21_PAD_LD11 = PAD_ID(PA, 17),
+ MX21_PAD_LD12 = PAD_ID(PA, 18),
+ MX21_PAD_LD13 = PAD_ID(PA, 19),
+ MX21_PAD_LD14 = PAD_ID(PA, 20),
+ MX21_PAD_LD15 = PAD_ID(PA, 21),
+ MX21_PAD_LD16 = PAD_ID(PA, 22),
+ MX21_PAD_LD17 = PAD_ID(PA, 23),
+ MX21_PAD_REV = PAD_ID(PA, 24),
+ MX21_PAD_CLS = PAD_ID(PA, 25),
+ MX21_PAD_PS = PAD_ID(PA, 26),
+ MX21_PAD_SPL_SPR = PAD_ID(PA, 27),
+ MX21_PAD_HSYNC = PAD_ID(PA, 28),
+ MX21_PAD_VSYNC = PAD_ID(PA, 29),
+ MX21_PAD_CONTRAST = PAD_ID(PA, 30),
+ MX21_PAD_OE_ACD = PAD_ID(PA, 31),
+ MX21_PAD_SD2_D0 = PAD_ID(PB, 4),
+ MX21_PAD_SD2_D1 = PAD_ID(PB, 5),
+ MX21_PAD_SD2_D2 = PAD_ID(PB, 6),
+ MX21_PAD_SD2_D3 = PAD_ID(PB, 7),
+ MX21_PAD_SD2_CMD = PAD_ID(PB, 8),
+ MX21_PAD_SD2_CLK = PAD_ID(PB, 9),
+ MX21_PAD_CSI_D0 = PAD_ID(PB, 10),
+ MX21_PAD_CSI_D1 = PAD_ID(PB, 11),
+ MX21_PAD_CSI_D2 = PAD_ID(PB, 12),
+ MX21_PAD_CSI_D3 = PAD_ID(PB, 13),
+ MX21_PAD_CSI_D4 = PAD_ID(PB, 14),
+ MX21_PAD_CSI_MCLK = PAD_ID(PB, 15),
+ MX21_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
+ MX21_PAD_CSI_D5 = PAD_ID(PB, 17),
+ MX21_PAD_CSI_D6 = PAD_ID(PB, 18),
+ MX21_PAD_CSI_D7 = PAD_ID(PB, 19),
+ MX21_PAD_CSI_VSYNC = PAD_ID(PB, 20),
+ MX21_PAD_CSI_HSYNC = PAD_ID(PB, 21),
+ MX21_PAD_USB_BYP = PAD_ID(PB, 22),
+ MX21_PAD_USB_PWR = PAD_ID(PB, 23),
+ MX21_PAD_USB_OC = PAD_ID(PB, 24),
+ MX21_PAD_USBH_ON = PAD_ID(PB, 25),
+ MX21_PAD_USBH1_FS = PAD_ID(PB, 26),
+ MX21_PAD_USBH1_OE = PAD_ID(PB, 27),
+ MX21_PAD_USBH1_TXDM = PAD_ID(PB, 28),
+ MX21_PAD_USBH1_TXDP = PAD_ID(PB, 29),
+ MX21_PAD_USBH1_RXDM = PAD_ID(PB, 30),
+ MX21_PAD_USBH1_RXDP = PAD_ID(PB, 31),
+ MX21_PAD_USBG_SDA = PAD_ID(PC, 5),
+ MX21_PAD_USBG_SCL = PAD_ID(PC, 6),
+ MX21_PAD_USBG_ON = PAD_ID(PC, 7),
+ MX21_PAD_USBG_FS = PAD_ID(PC, 8),
+ MX21_PAD_USBG_OE = PAD_ID(PC, 9),
+ MX21_PAD_USBG_TXDM = PAD_ID(PC, 10),
+ MX21_PAD_USBG_TXDP = PAD_ID(PC, 11),
+ MX21_PAD_USBG_RXDM = PAD_ID(PC, 12),
+ MX21_PAD_USBG_RXDP = PAD_ID(PC, 13),
+ MX21_PAD_TOUT = PAD_ID(PC, 14),
+ MX21_PAD_TIN = PAD_ID(PC, 15),
+ MX21_PAD_SAP_FS = PAD_ID(PC, 16),
+ MX21_PAD_SAP_RXD = PAD_ID(PC, 17),
+ MX21_PAD_SAP_TXD = PAD_ID(PC, 18),
+ MX21_PAD_SAP_CLK = PAD_ID(PC, 19),
+ MX21_PAD_SSI1_FS = PAD_ID(PC, 20),
+ MX21_PAD_SSI1_RXD = PAD_ID(PC, 21),
+ MX21_PAD_SSI1_TXD = PAD_ID(PC, 22),
+ MX21_PAD_SSI1_CLK = PAD_ID(PC, 23),
+ MX21_PAD_SSI2_FS = PAD_ID(PC, 24),
+ MX21_PAD_SSI2_RXD = PAD_ID(PC, 25),
+ MX21_PAD_SSI2_TXD = PAD_ID(PC, 26),
+ MX21_PAD_SSI2_CLK = PAD_ID(PC, 27),
+ MX21_PAD_SSI3_FS = PAD_ID(PC, 28),
+ MX21_PAD_SSI3_RXD = PAD_ID(PC, 29),
+ MX21_PAD_SSI3_TXD = PAD_ID(PC, 30),
+ MX21_PAD_SSI3_CLK = PAD_ID(PC, 31),
+ MX21_PAD_I2C_DATA = PAD_ID(PD, 17),
+ MX21_PAD_I2C_CLK = PAD_ID(PD, 18),
+ MX21_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
+ MX21_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
+ MX21_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
+ MX21_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
+ MX21_PAD_CSPI2_MISO = PAD_ID(PD, 23),
+ MX21_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
+ MX21_PAD_CSPI1_RDY = PAD_ID(PD, 25),
+ MX21_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
+ MX21_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
+ MX21_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
+ MX21_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
+ MX21_PAD_CSPI1_MISO = PAD_ID(PD, 30),
+ MX21_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
+ MX21_PAD_TEST_WB2 = PAD_ID(PE, 0),
+ MX21_PAD_TEST_WB1 = PAD_ID(PE, 1),
+ MX21_PAD_TEST_WB0 = PAD_ID(PE, 2),
+ MX21_PAD_UART2_CTS = PAD_ID(PE, 3),
+ MX21_PAD_UART2_RTS = PAD_ID(PE, 4),
+ MX21_PAD_PWMO = PAD_ID(PE, 5),
+ MX21_PAD_UART2_TXD = PAD_ID(PE, 6),
+ MX21_PAD_UART2_RXD = PAD_ID(PE, 7),
+ MX21_PAD_UART3_TXD = PAD_ID(PE, 8),
+ MX21_PAD_UART3_RXD = PAD_ID(PE, 9),
+ MX21_PAD_UART3_CTS = PAD_ID(PE, 10),
+ MX21_PAD_UART3_RTS = PAD_ID(PE, 11),
+ MX21_PAD_UART1_TXD = PAD_ID(PE, 12),
+ MX21_PAD_UART1_RXD = PAD_ID(PE, 13),
+ MX21_PAD_UART1_CTS = PAD_ID(PE, 14),
+ MX21_PAD_UART1_RTS = PAD_ID(PE, 15),
+ MX21_PAD_RTCK = PAD_ID(PE, 16),
+ MX21_PAD_RESET_OUT = PAD_ID(PE, 17),
+ MX21_PAD_SD1_D0 = PAD_ID(PE, 18),
+ MX21_PAD_SD1_D1 = PAD_ID(PE, 19),
+ MX21_PAD_SD1_D2 = PAD_ID(PE, 20),
+ MX21_PAD_SD1_D3 = PAD_ID(PE, 21),
+ MX21_PAD_SD1_CMD = PAD_ID(PE, 22),
+ MX21_PAD_SD1_CLK = PAD_ID(PE, 23),
+ MX21_PAD_NFRB = PAD_ID(PF, 0),
+ MX21_PAD_NFCE = PAD_ID(PF, 1),
+ MX21_PAD_NFWP = PAD_ID(PF, 2),
+ MX21_PAD_NFCLE = PAD_ID(PF, 3),
+ MX21_PAD_NFALE = PAD_ID(PF, 4),
+ MX21_PAD_NFRE = PAD_ID(PF, 5),
+ MX21_PAD_NFWE = PAD_ID(PF, 6),
+ MX21_PAD_NFIO0 = PAD_ID(PF, 7),
+ MX21_PAD_NFIO1 = PAD_ID(PF, 8),
+ MX21_PAD_NFIO2 = PAD_ID(PF, 9),
+ MX21_PAD_NFIO3 = PAD_ID(PF, 10),
+ MX21_PAD_NFIO4 = PAD_ID(PF, 11),
+ MX21_PAD_NFIO5 = PAD_ID(PF, 12),
+ MX21_PAD_NFIO6 = PAD_ID(PF, 13),
+ MX21_PAD_NFIO7 = PAD_ID(PF, 14),
+ MX21_PAD_CLKO = PAD_ID(PF, 15),
+ MX21_PAD_RESERVED = PAD_ID(PF, 16),
+ MX21_PAD_CS4 = PAD_ID(PF, 21),
+ MX21_PAD_CS5 = PAD_ID(PF, 22),
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX21_PAD_LSCLK),
+ IMX_PINCTRL_PIN(MX21_PAD_LD0),
+ IMX_PINCTRL_PIN(MX21_PAD_LD1),
+ IMX_PINCTRL_PIN(MX21_PAD_LD2),
+ IMX_PINCTRL_PIN(MX21_PAD_LD3),
+ IMX_PINCTRL_PIN(MX21_PAD_LD4),
+ IMX_PINCTRL_PIN(MX21_PAD_LD5),
+ IMX_PINCTRL_PIN(MX21_PAD_LD6),
+ IMX_PINCTRL_PIN(MX21_PAD_LD7),
+ IMX_PINCTRL_PIN(MX21_PAD_LD8),
+ IMX_PINCTRL_PIN(MX21_PAD_LD9),
+ IMX_PINCTRL_PIN(MX21_PAD_LD10),
+ IMX_PINCTRL_PIN(MX21_PAD_LD11),
+ IMX_PINCTRL_PIN(MX21_PAD_LD12),
+ IMX_PINCTRL_PIN(MX21_PAD_LD13),
+ IMX_PINCTRL_PIN(MX21_PAD_LD14),
+ IMX_PINCTRL_PIN(MX21_PAD_LD15),
+ IMX_PINCTRL_PIN(MX21_PAD_LD16),
+ IMX_PINCTRL_PIN(MX21_PAD_LD17),
+ IMX_PINCTRL_PIN(MX21_PAD_REV),
+ IMX_PINCTRL_PIN(MX21_PAD_CLS),
+ IMX_PINCTRL_PIN(MX21_PAD_PS),
+ IMX_PINCTRL_PIN(MX21_PAD_SPL_SPR),
+ IMX_PINCTRL_PIN(MX21_PAD_HSYNC),
+ IMX_PINCTRL_PIN(MX21_PAD_VSYNC),
+ IMX_PINCTRL_PIN(MX21_PAD_CONTRAST),
+ IMX_PINCTRL_PIN(MX21_PAD_OE_ACD),
+ IMX_PINCTRL_PIN(MX21_PAD_SD2_D0),
+ IMX_PINCTRL_PIN(MX21_PAD_SD2_D1),
+ IMX_PINCTRL_PIN(MX21_PAD_SD2_D2),
+ IMX_PINCTRL_PIN(MX21_PAD_SD2_D3),
+ IMX_PINCTRL_PIN(MX21_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX21_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX21_PAD_CSI_D0),
+ IMX_PINCTRL_PIN(MX21_PAD_CSI_D1),
+ IMX_PINCTRL_PIN(MX21_PAD_CSI_D2),
+ IMX_PINCTRL_PIN(MX21_PAD_CSI_D3),
+ IMX_PINCTRL_PIN(MX21_PAD_CSI_D4),
+ IMX_PINCTRL_PIN(MX21_PAD_CSI_MCLK),
+ IMX_PINCTRL_PIN(MX21_PAD_CSI_PIXCLK),
+ IMX_PINCTRL_PIN(MX21_PAD_CSI_D5),
+ IMX_PINCTRL_PIN(MX21_PAD_CSI_D6),
+ IMX_PINCTRL_PIN(MX21_PAD_CSI_D7),
+ IMX_PINCTRL_PIN(MX21_PAD_CSI_VSYNC),
+ IMX_PINCTRL_PIN(MX21_PAD_CSI_HSYNC),
+ IMX_PINCTRL_PIN(MX21_PAD_USB_BYP),
+ IMX_PINCTRL_PIN(MX21_PAD_USB_PWR),
+ IMX_PINCTRL_PIN(MX21_PAD_USB_OC),
+ IMX_PINCTRL_PIN(MX21_PAD_USBH_ON),
+ IMX_PINCTRL_PIN(MX21_PAD_USBH1_FS),
+ IMX_PINCTRL_PIN(MX21_PAD_USBH1_OE),
+ IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDM),
+ IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDP),
+ IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDM),
+ IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDP),
+ IMX_PINCTRL_PIN(MX21_PAD_USBG_SDA),
+ IMX_PINCTRL_PIN(MX21_PAD_USBG_SCL),
+ IMX_PINCTRL_PIN(MX21_PAD_USBG_ON),
+ IMX_PINCTRL_PIN(MX21_PAD_USBG_FS),
+ IMX_PINCTRL_PIN(MX21_PAD_USBG_OE),
+ IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDM),
+ IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDP),
+ IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDM),
+ IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDP),
+ IMX_PINCTRL_PIN(MX21_PAD_TOUT),
+ IMX_PINCTRL_PIN(MX21_PAD_TIN),
+ IMX_PINCTRL_PIN(MX21_PAD_SAP_FS),
+ IMX_PINCTRL_PIN(MX21_PAD_SAP_RXD),
+ IMX_PINCTRL_PIN(MX21_PAD_SAP_TXD),
+ IMX_PINCTRL_PIN(MX21_PAD_SAP_CLK),
+ IMX_PINCTRL_PIN(MX21_PAD_SSI1_FS),
+ IMX_PINCTRL_PIN(MX21_PAD_SSI1_RXD),
+ IMX_PINCTRL_PIN(MX21_PAD_SSI1_TXD),
+ IMX_PINCTRL_PIN(MX21_PAD_SSI1_CLK),
+ IMX_PINCTRL_PIN(MX21_PAD_SSI2_FS),
+ IMX_PINCTRL_PIN(MX21_PAD_SSI2_RXD),
+ IMX_PINCTRL_PIN(MX21_PAD_SSI2_TXD),
+ IMX_PINCTRL_PIN(MX21_PAD_SSI2_CLK),
+ IMX_PINCTRL_PIN(MX21_PAD_SSI3_FS),
+ IMX_PINCTRL_PIN(MX21_PAD_SSI3_RXD),
+ IMX_PINCTRL_PIN(MX21_PAD_SSI3_TXD),
+ IMX_PINCTRL_PIN(MX21_PAD_SSI3_CLK),
+ IMX_PINCTRL_PIN(MX21_PAD_I2C_DATA),
+ IMX_PINCTRL_PIN(MX21_PAD_I2C_CLK),
+ IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS2),
+ IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS1),
+ IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS0),
+ IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SCLK),
+ IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MISO),
+ IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MOSI),
+ IMX_PINCTRL_PIN(MX21_PAD_CSPI1_RDY),
+ IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS2),
+ IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS1),
+ IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS0),
+ IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SCLK),
+ IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MISO),
+ IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MOSI),
+ IMX_PINCTRL_PIN(MX21_PAD_TEST_WB2),
+ IMX_PINCTRL_PIN(MX21_PAD_TEST_WB1),
+ IMX_PINCTRL_PIN(MX21_PAD_TEST_WB0),
+ IMX_PINCTRL_PIN(MX21_PAD_UART2_CTS),
+ IMX_PINCTRL_PIN(MX21_PAD_UART2_RTS),
+ IMX_PINCTRL_PIN(MX21_PAD_PWMO),
+ IMX_PINCTRL_PIN(MX21_PAD_UART2_TXD),
+ IMX_PINCTRL_PIN(MX21_PAD_UART2_RXD),
+ IMX_PINCTRL_PIN(MX21_PAD_UART3_TXD),
+ IMX_PINCTRL_PIN(MX21_PAD_UART3_RXD),
+ IMX_PINCTRL_PIN(MX21_PAD_UART3_CTS),
+ IMX_PINCTRL_PIN(MX21_PAD_UART3_RTS),
+ IMX_PINCTRL_PIN(MX21_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX21_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX21_PAD_UART1_CTS),
+ IMX_PINCTRL_PIN(MX21_PAD_UART1_RTS),
+ IMX_PINCTRL_PIN(MX21_PAD_RTCK),
+ IMX_PINCTRL_PIN(MX21_PAD_RESET_OUT),
+ IMX_PINCTRL_PIN(MX21_PAD_SD1_D0),
+ IMX_PINCTRL_PIN(MX21_PAD_SD1_D1),
+ IMX_PINCTRL_PIN(MX21_PAD_SD1_D2),
+ IMX_PINCTRL_PIN(MX21_PAD_SD1_D3),
+ IMX_PINCTRL_PIN(MX21_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX21_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX21_PAD_NFRB),
+ IMX_PINCTRL_PIN(MX21_PAD_NFCE),
+ IMX_PINCTRL_PIN(MX21_PAD_NFWP),
+ IMX_PINCTRL_PIN(MX21_PAD_NFCLE),
+ IMX_PINCTRL_PIN(MX21_PAD_NFALE),
+ IMX_PINCTRL_PIN(MX21_PAD_NFRE),
+ IMX_PINCTRL_PIN(MX21_PAD_NFWE),
+ IMX_PINCTRL_PIN(MX21_PAD_NFIO0),
+ IMX_PINCTRL_PIN(MX21_PAD_NFIO1),
+ IMX_PINCTRL_PIN(MX21_PAD_NFIO2),
+ IMX_PINCTRL_PIN(MX21_PAD_NFIO3),
+ IMX_PINCTRL_PIN(MX21_PAD_NFIO4),
+ IMX_PINCTRL_PIN(MX21_PAD_NFIO5),
+ IMX_PINCTRL_PIN(MX21_PAD_NFIO6),
+ IMX_PINCTRL_PIN(MX21_PAD_NFIO7),
+ IMX_PINCTRL_PIN(MX21_PAD_CLKO),
+ IMX_PINCTRL_PIN(MX21_PAD_RESERVED),
+ IMX_PINCTRL_PIN(MX21_PAD_CS4),
+ IMX_PINCTRL_PIN(MX21_PAD_CS5),
+};
+
+static struct imx1_pinctrl_soc_info imx21_pinctrl_info = {
+ .pins = imx21_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx21_pinctrl_pads),
+};
+
+static int __init imx21_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx1_pinctrl_core_probe(pdev, &imx21_pinctrl_info);
+}
+
+static const struct of_device_id imx21_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx21-iomuxc", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, imx21_pinctrl_of_match);
+
+static struct platform_driver imx21_pinctrl_driver = {
+ .driver = {
+ .name = "imx21-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = imx21_pinctrl_of_match,
+ },
+ .remove = imx1_pinctrl_core_remove,
+};
+module_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe);
+
+MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
+MODULE_DESCRIPTION("Freescale i.MX21 pinctrl driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mxs.h"
+
+enum imx23_pin_enum {
+ GPMI_D00 = PINID(0, 0),
+ GPMI_D01 = PINID(0, 1),
+ GPMI_D02 = PINID(0, 2),
+ GPMI_D03 = PINID(0, 3),
+ GPMI_D04 = PINID(0, 4),
+ GPMI_D05 = PINID(0, 5),
+ GPMI_D06 = PINID(0, 6),
+ GPMI_D07 = PINID(0, 7),
+ GPMI_D08 = PINID(0, 8),
+ GPMI_D09 = PINID(0, 9),
+ GPMI_D10 = PINID(0, 10),
+ GPMI_D11 = PINID(0, 11),
+ GPMI_D12 = PINID(0, 12),
+ GPMI_D13 = PINID(0, 13),
+ GPMI_D14 = PINID(0, 14),
+ GPMI_D15 = PINID(0, 15),
+ GPMI_CLE = PINID(0, 16),
+ GPMI_ALE = PINID(0, 17),
+ GPMI_CE2N = PINID(0, 18),
+ GPMI_RDY0 = PINID(0, 19),
+ GPMI_RDY1 = PINID(0, 20),
+ GPMI_RDY2 = PINID(0, 21),
+ GPMI_RDY3 = PINID(0, 22),
+ GPMI_WPN = PINID(0, 23),
+ GPMI_WRN = PINID(0, 24),
+ GPMI_RDN = PINID(0, 25),
+ AUART1_CTS = PINID(0, 26),
+ AUART1_RTS = PINID(0, 27),
+ AUART1_RX = PINID(0, 28),
+ AUART1_TX = PINID(0, 29),
+ I2C_SCL = PINID(0, 30),
+ I2C_SDA = PINID(0, 31),
+ LCD_D00 = PINID(1, 0),
+ LCD_D01 = PINID(1, 1),
+ LCD_D02 = PINID(1, 2),
+ LCD_D03 = PINID(1, 3),
+ LCD_D04 = PINID(1, 4),
+ LCD_D05 = PINID(1, 5),
+ LCD_D06 = PINID(1, 6),
+ LCD_D07 = PINID(1, 7),
+ LCD_D08 = PINID(1, 8),
+ LCD_D09 = PINID(1, 9),
+ LCD_D10 = PINID(1, 10),
+ LCD_D11 = PINID(1, 11),
+ LCD_D12 = PINID(1, 12),
+ LCD_D13 = PINID(1, 13),
+ LCD_D14 = PINID(1, 14),
+ LCD_D15 = PINID(1, 15),
+ LCD_D16 = PINID(1, 16),
+ LCD_D17 = PINID(1, 17),
+ LCD_RESET = PINID(1, 18),
+ LCD_RS = PINID(1, 19),
+ LCD_WR = PINID(1, 20),
+ LCD_CS = PINID(1, 21),
+ LCD_DOTCK = PINID(1, 22),
+ LCD_ENABLE = PINID(1, 23),
+ LCD_HSYNC = PINID(1, 24),
+ LCD_VSYNC = PINID(1, 25),
+ PWM0 = PINID(1, 26),
+ PWM1 = PINID(1, 27),
+ PWM2 = PINID(1, 28),
+ PWM3 = PINID(1, 29),
+ PWM4 = PINID(1, 30),
+ SSP1_CMD = PINID(2, 0),
+ SSP1_DETECT = PINID(2, 1),
+ SSP1_DATA0 = PINID(2, 2),
+ SSP1_DATA1 = PINID(2, 3),
+ SSP1_DATA2 = PINID(2, 4),
+ SSP1_DATA3 = PINID(2, 5),
+ SSP1_SCK = PINID(2, 6),
+ ROTARYA = PINID(2, 7),
+ ROTARYB = PINID(2, 8),
+ EMI_A00 = PINID(2, 9),
+ EMI_A01 = PINID(2, 10),
+ EMI_A02 = PINID(2, 11),
+ EMI_A03 = PINID(2, 12),
+ EMI_A04 = PINID(2, 13),
+ EMI_A05 = PINID(2, 14),
+ EMI_A06 = PINID(2, 15),
+ EMI_A07 = PINID(2, 16),
+ EMI_A08 = PINID(2, 17),
+ EMI_A09 = PINID(2, 18),
+ EMI_A10 = PINID(2, 19),
+ EMI_A11 = PINID(2, 20),
+ EMI_A12 = PINID(2, 21),
+ EMI_BA0 = PINID(2, 22),
+ EMI_BA1 = PINID(2, 23),
+ EMI_CASN = PINID(2, 24),
+ EMI_CE0N = PINID(2, 25),
+ EMI_CE1N = PINID(2, 26),
+ GPMI_CE1N = PINID(2, 27),
+ GPMI_CE0N = PINID(2, 28),
+ EMI_CKE = PINID(2, 29),
+ EMI_RASN = PINID(2, 30),
+ EMI_WEN = PINID(2, 31),
+ EMI_D00 = PINID(3, 0),
+ EMI_D01 = PINID(3, 1),
+ EMI_D02 = PINID(3, 2),
+ EMI_D03 = PINID(3, 3),
+ EMI_D04 = PINID(3, 4),
+ EMI_D05 = PINID(3, 5),
+ EMI_D06 = PINID(3, 6),
+ EMI_D07 = PINID(3, 7),
+ EMI_D08 = PINID(3, 8),
+ EMI_D09 = PINID(3, 9),
+ EMI_D10 = PINID(3, 10),
+ EMI_D11 = PINID(3, 11),
+ EMI_D12 = PINID(3, 12),
+ EMI_D13 = PINID(3, 13),
+ EMI_D14 = PINID(3, 14),
+ EMI_D15 = PINID(3, 15),
+ EMI_DQM0 = PINID(3, 16),
+ EMI_DQM1 = PINID(3, 17),
+ EMI_DQS0 = PINID(3, 18),
+ EMI_DQS1 = PINID(3, 19),
+ EMI_CLK = PINID(3, 20),
+ EMI_CLKN = PINID(3, 21),
+};
+
+static const struct pinctrl_pin_desc imx23_pins[] = {
+ MXS_PINCTRL_PIN(GPMI_D00),
+ MXS_PINCTRL_PIN(GPMI_D01),
+ MXS_PINCTRL_PIN(GPMI_D02),
+ MXS_PINCTRL_PIN(GPMI_D03),
+ MXS_PINCTRL_PIN(GPMI_D04),
+ MXS_PINCTRL_PIN(GPMI_D05),
+ MXS_PINCTRL_PIN(GPMI_D06),
+ MXS_PINCTRL_PIN(GPMI_D07),
+ MXS_PINCTRL_PIN(GPMI_D08),
+ MXS_PINCTRL_PIN(GPMI_D09),
+ MXS_PINCTRL_PIN(GPMI_D10),
+ MXS_PINCTRL_PIN(GPMI_D11),
+ MXS_PINCTRL_PIN(GPMI_D12),
+ MXS_PINCTRL_PIN(GPMI_D13),
+ MXS_PINCTRL_PIN(GPMI_D14),
+ MXS_PINCTRL_PIN(GPMI_D15),
+ MXS_PINCTRL_PIN(GPMI_CLE),
+ MXS_PINCTRL_PIN(GPMI_ALE),
+ MXS_PINCTRL_PIN(GPMI_CE2N),
+ MXS_PINCTRL_PIN(GPMI_RDY0),
+ MXS_PINCTRL_PIN(GPMI_RDY1),
+ MXS_PINCTRL_PIN(GPMI_RDY2),
+ MXS_PINCTRL_PIN(GPMI_RDY3),
+ MXS_PINCTRL_PIN(GPMI_WPN),
+ MXS_PINCTRL_PIN(GPMI_WRN),
+ MXS_PINCTRL_PIN(GPMI_RDN),
+ MXS_PINCTRL_PIN(AUART1_CTS),
+ MXS_PINCTRL_PIN(AUART1_RTS),
+ MXS_PINCTRL_PIN(AUART1_RX),
+ MXS_PINCTRL_PIN(AUART1_TX),
+ MXS_PINCTRL_PIN(I2C_SCL),
+ MXS_PINCTRL_PIN(I2C_SDA),
+ MXS_PINCTRL_PIN(LCD_D00),
+ MXS_PINCTRL_PIN(LCD_D01),
+ MXS_PINCTRL_PIN(LCD_D02),
+ MXS_PINCTRL_PIN(LCD_D03),
+ MXS_PINCTRL_PIN(LCD_D04),
+ MXS_PINCTRL_PIN(LCD_D05),
+ MXS_PINCTRL_PIN(LCD_D06),
+ MXS_PINCTRL_PIN(LCD_D07),
+ MXS_PINCTRL_PIN(LCD_D08),
+ MXS_PINCTRL_PIN(LCD_D09),
+ MXS_PINCTRL_PIN(LCD_D10),
+ MXS_PINCTRL_PIN(LCD_D11),
+ MXS_PINCTRL_PIN(LCD_D12),
+ MXS_PINCTRL_PIN(LCD_D13),
+ MXS_PINCTRL_PIN(LCD_D14),
+ MXS_PINCTRL_PIN(LCD_D15),
+ MXS_PINCTRL_PIN(LCD_D16),
+ MXS_PINCTRL_PIN(LCD_D17),
+ MXS_PINCTRL_PIN(LCD_RESET),
+ MXS_PINCTRL_PIN(LCD_RS),
+ MXS_PINCTRL_PIN(LCD_WR),
+ MXS_PINCTRL_PIN(LCD_CS),
+ MXS_PINCTRL_PIN(LCD_DOTCK),
+ MXS_PINCTRL_PIN(LCD_ENABLE),
+ MXS_PINCTRL_PIN(LCD_HSYNC),
+ MXS_PINCTRL_PIN(LCD_VSYNC),
+ MXS_PINCTRL_PIN(PWM0),
+ MXS_PINCTRL_PIN(PWM1),
+ MXS_PINCTRL_PIN(PWM2),
+ MXS_PINCTRL_PIN(PWM3),
+ MXS_PINCTRL_PIN(PWM4),
+ MXS_PINCTRL_PIN(SSP1_CMD),
+ MXS_PINCTRL_PIN(SSP1_DETECT),
+ MXS_PINCTRL_PIN(SSP1_DATA0),
+ MXS_PINCTRL_PIN(SSP1_DATA1),
+ MXS_PINCTRL_PIN(SSP1_DATA2),
+ MXS_PINCTRL_PIN(SSP1_DATA3),
+ MXS_PINCTRL_PIN(SSP1_SCK),
+ MXS_PINCTRL_PIN(ROTARYA),
+ MXS_PINCTRL_PIN(ROTARYB),
+ MXS_PINCTRL_PIN(EMI_A00),
+ MXS_PINCTRL_PIN(EMI_A01),
+ MXS_PINCTRL_PIN(EMI_A02),
+ MXS_PINCTRL_PIN(EMI_A03),
+ MXS_PINCTRL_PIN(EMI_A04),
+ MXS_PINCTRL_PIN(EMI_A05),
+ MXS_PINCTRL_PIN(EMI_A06),
+ MXS_PINCTRL_PIN(EMI_A07),
+ MXS_PINCTRL_PIN(EMI_A08),
+ MXS_PINCTRL_PIN(EMI_A09),
+ MXS_PINCTRL_PIN(EMI_A10),
+ MXS_PINCTRL_PIN(EMI_A11),
+ MXS_PINCTRL_PIN(EMI_A12),
+ MXS_PINCTRL_PIN(EMI_BA0),
+ MXS_PINCTRL_PIN(EMI_BA1),
+ MXS_PINCTRL_PIN(EMI_CASN),
+ MXS_PINCTRL_PIN(EMI_CE0N),
+ MXS_PINCTRL_PIN(EMI_CE1N),
+ MXS_PINCTRL_PIN(GPMI_CE1N),
+ MXS_PINCTRL_PIN(GPMI_CE0N),
+ MXS_PINCTRL_PIN(EMI_CKE),
+ MXS_PINCTRL_PIN(EMI_RASN),
+ MXS_PINCTRL_PIN(EMI_WEN),
+ MXS_PINCTRL_PIN(EMI_D00),
+ MXS_PINCTRL_PIN(EMI_D01),
+ MXS_PINCTRL_PIN(EMI_D02),
+ MXS_PINCTRL_PIN(EMI_D03),
+ MXS_PINCTRL_PIN(EMI_D04),
+ MXS_PINCTRL_PIN(EMI_D05),
+ MXS_PINCTRL_PIN(EMI_D06),
+ MXS_PINCTRL_PIN(EMI_D07),
+ MXS_PINCTRL_PIN(EMI_D08),
+ MXS_PINCTRL_PIN(EMI_D09),
+ MXS_PINCTRL_PIN(EMI_D10),
+ MXS_PINCTRL_PIN(EMI_D11),
+ MXS_PINCTRL_PIN(EMI_D12),
+ MXS_PINCTRL_PIN(EMI_D13),
+ MXS_PINCTRL_PIN(EMI_D14),
+ MXS_PINCTRL_PIN(EMI_D15),
+ MXS_PINCTRL_PIN(EMI_DQM0),
+ MXS_PINCTRL_PIN(EMI_DQM1),
+ MXS_PINCTRL_PIN(EMI_DQS0),
+ MXS_PINCTRL_PIN(EMI_DQS1),
+ MXS_PINCTRL_PIN(EMI_CLK),
+ MXS_PINCTRL_PIN(EMI_CLKN),
+};
+
+static struct mxs_regs imx23_regs = {
+ .muxsel = 0x100,
+ .drive = 0x200,
+ .pull = 0x400,
+};
+
+static struct mxs_pinctrl_soc_data imx23_pinctrl_data = {
+ .regs = &imx23_regs,
+ .pins = imx23_pins,
+ .npins = ARRAY_SIZE(imx23_pins),
+};
+
+static int imx23_pinctrl_probe(struct platform_device *pdev)
+{
+ return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
+}
+
+static const struct of_device_id imx23_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx23-pinctrl", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match);
+
+static struct platform_driver imx23_pinctrl_driver = {
+ .driver = {
+ .name = "imx23-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = imx23_pinctrl_of_match,
+ },
+ .probe = imx23_pinctrl_probe,
+ .remove = mxs_pinctrl_remove,
+};
+
+static int __init imx23_pinctrl_init(void)
+{
+ return platform_driver_register(&imx23_pinctrl_driver);
+}
+postcore_initcall(imx23_pinctrl_init);
+
+static void __exit imx23_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx23_pinctrl_driver);
+}
+module_exit(imx23_pinctrl_exit);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
+MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * imx25 pinctrl driver.
+ *
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ *
+ * This driver was mostly copied from the imx51 pinctrl driver which has:
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * Author: Denis Carikli <denis@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx25_pads {
+ MX25_PAD_RESERVE0 = 1,
+ MX25_PAD_RESERVE1 = 2,
+ MX25_PAD_A10 = 3,
+ MX25_PAD_A13 = 4,
+ MX25_PAD_A14 = 5,
+ MX25_PAD_A15 = 6,
+ MX25_PAD_A16 = 7,
+ MX25_PAD_A17 = 8,
+ MX25_PAD_A18 = 9,
+ MX25_PAD_A19 = 10,
+ MX25_PAD_A20 = 11,
+ MX25_PAD_A21 = 12,
+ MX25_PAD_A22 = 13,
+ MX25_PAD_A23 = 14,
+ MX25_PAD_A24 = 15,
+ MX25_PAD_A25 = 16,
+ MX25_PAD_EB0 = 17,
+ MX25_PAD_EB1 = 18,
+ MX25_PAD_OE = 19,
+ MX25_PAD_CS0 = 20,
+ MX25_PAD_CS1 = 21,
+ MX25_PAD_CS4 = 22,
+ MX25_PAD_CS5 = 23,
+ MX25_PAD_NF_CE0 = 24,
+ MX25_PAD_ECB = 25,
+ MX25_PAD_LBA = 26,
+ MX25_PAD_BCLK = 27,
+ MX25_PAD_RW = 28,
+ MX25_PAD_NFWE_B = 29,
+ MX25_PAD_NFRE_B = 30,
+ MX25_PAD_NFALE = 31,
+ MX25_PAD_NFCLE = 32,
+ MX25_PAD_NFWP_B = 33,
+ MX25_PAD_NFRB = 34,
+ MX25_PAD_D15 = 35,
+ MX25_PAD_D14 = 36,
+ MX25_PAD_D13 = 37,
+ MX25_PAD_D12 = 38,
+ MX25_PAD_D11 = 39,
+ MX25_PAD_D10 = 40,
+ MX25_PAD_D9 = 41,
+ MX25_PAD_D8 = 42,
+ MX25_PAD_D7 = 43,
+ MX25_PAD_D6 = 44,
+ MX25_PAD_D5 = 45,
+ MX25_PAD_D4 = 46,
+ MX25_PAD_D3 = 47,
+ MX25_PAD_D2 = 48,
+ MX25_PAD_D1 = 49,
+ MX25_PAD_D0 = 50,
+ MX25_PAD_LD0 = 51,
+ MX25_PAD_LD1 = 52,
+ MX25_PAD_LD2 = 53,
+ MX25_PAD_LD3 = 54,
+ MX25_PAD_LD4 = 55,
+ MX25_PAD_LD5 = 56,
+ MX25_PAD_LD6 = 57,
+ MX25_PAD_LD7 = 58,
+ MX25_PAD_LD8 = 59,
+ MX25_PAD_LD9 = 60,
+ MX25_PAD_LD10 = 61,
+ MX25_PAD_LD11 = 62,
+ MX25_PAD_LD12 = 63,
+ MX25_PAD_LD13 = 64,
+ MX25_PAD_LD14 = 65,
+ MX25_PAD_LD15 = 66,
+ MX25_PAD_HSYNC = 67,
+ MX25_PAD_VSYNC = 68,
+ MX25_PAD_LSCLK = 69,
+ MX25_PAD_OE_ACD = 70,
+ MX25_PAD_CONTRAST = 71,
+ MX25_PAD_PWM = 72,
+ MX25_PAD_CSI_D2 = 73,
+ MX25_PAD_CSI_D3 = 74,
+ MX25_PAD_CSI_D4 = 75,
+ MX25_PAD_CSI_D5 = 76,
+ MX25_PAD_CSI_D6 = 77,
+ MX25_PAD_CSI_D7 = 78,
+ MX25_PAD_CSI_D8 = 79,
+ MX25_PAD_CSI_D9 = 80,
+ MX25_PAD_CSI_MCLK = 81,
+ MX25_PAD_CSI_VSYNC = 82,
+ MX25_PAD_CSI_HSYNC = 83,
+ MX25_PAD_CSI_PIXCLK = 84,
+ MX25_PAD_I2C1_CLK = 85,
+ MX25_PAD_I2C1_DAT = 86,
+ MX25_PAD_CSPI1_MOSI = 87,
+ MX25_PAD_CSPI1_MISO = 88,
+ MX25_PAD_CSPI1_SS0 = 89,
+ MX25_PAD_CSPI1_SS1 = 90,
+ MX25_PAD_CSPI1_SCLK = 91,
+ MX25_PAD_CSPI1_RDY = 92,
+ MX25_PAD_UART1_RXD = 93,
+ MX25_PAD_UART1_TXD = 94,
+ MX25_PAD_UART1_RTS = 95,
+ MX25_PAD_UART1_CTS = 96,
+ MX25_PAD_UART2_RXD = 97,
+ MX25_PAD_UART2_TXD = 98,
+ MX25_PAD_UART2_RTS = 99,
+ MX25_PAD_UART2_CTS = 100,
+ MX25_PAD_SD1_CMD = 101,
+ MX25_PAD_SD1_CLK = 102,
+ MX25_PAD_SD1_DATA0 = 103,
+ MX25_PAD_SD1_DATA1 = 104,
+ MX25_PAD_SD1_DATA2 = 105,
+ MX25_PAD_SD1_DATA3 = 106,
+ MX25_PAD_KPP_ROW0 = 107,
+ MX25_PAD_KPP_ROW1 = 108,
+ MX25_PAD_KPP_ROW2 = 109,
+ MX25_PAD_KPP_ROW3 = 110,
+ MX25_PAD_KPP_COL0 = 111,
+ MX25_PAD_KPP_COL1 = 112,
+ MX25_PAD_KPP_COL2 = 113,
+ MX25_PAD_KPP_COL3 = 114,
+ MX25_PAD_FEC_MDC = 115,
+ MX25_PAD_FEC_MDIO = 116,
+ MX25_PAD_FEC_TDATA0 = 117,
+ MX25_PAD_FEC_TDATA1 = 118,
+ MX25_PAD_FEC_TX_EN = 119,
+ MX25_PAD_FEC_RDATA0 = 120,
+ MX25_PAD_FEC_RDATA1 = 121,
+ MX25_PAD_FEC_RX_DV = 122,
+ MX25_PAD_FEC_TX_CLK = 123,
+ MX25_PAD_RTCK = 124,
+ MX25_PAD_DE_B = 125,
+ MX25_PAD_GPIO_A = 126,
+ MX25_PAD_GPIO_B = 127,
+ MX25_PAD_GPIO_C = 128,
+ MX25_PAD_GPIO_D = 129,
+ MX25_PAD_GPIO_E = 130,
+ MX25_PAD_GPIO_F = 131,
+ MX25_PAD_EXT_ARMCLK = 132,
+ MX25_PAD_UPLL_BYPCLK = 133,
+ MX25_PAD_VSTBY_REQ = 134,
+ MX25_PAD_VSTBY_ACK = 135,
+ MX25_PAD_POWER_FAIL = 136,
+ MX25_PAD_CLKO = 137,
+ MX25_PAD_BOOT_MODE0 = 138,
+ MX25_PAD_BOOT_MODE1 = 139,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX25_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(MX25_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(MX25_PAD_A10),
+ IMX_PINCTRL_PIN(MX25_PAD_A13),
+ IMX_PINCTRL_PIN(MX25_PAD_A14),
+ IMX_PINCTRL_PIN(MX25_PAD_A15),
+ IMX_PINCTRL_PIN(MX25_PAD_A16),
+ IMX_PINCTRL_PIN(MX25_PAD_A17),
+ IMX_PINCTRL_PIN(MX25_PAD_A18),
+ IMX_PINCTRL_PIN(MX25_PAD_A19),
+ IMX_PINCTRL_PIN(MX25_PAD_A20),
+ IMX_PINCTRL_PIN(MX25_PAD_A21),
+ IMX_PINCTRL_PIN(MX25_PAD_A22),
+ IMX_PINCTRL_PIN(MX25_PAD_A23),
+ IMX_PINCTRL_PIN(MX25_PAD_A24),
+ IMX_PINCTRL_PIN(MX25_PAD_A25),
+ IMX_PINCTRL_PIN(MX25_PAD_EB0),
+ IMX_PINCTRL_PIN(MX25_PAD_EB1),
+ IMX_PINCTRL_PIN(MX25_PAD_OE),
+ IMX_PINCTRL_PIN(MX25_PAD_CS0),
+ IMX_PINCTRL_PIN(MX25_PAD_CS1),
+ IMX_PINCTRL_PIN(MX25_PAD_CS4),
+ IMX_PINCTRL_PIN(MX25_PAD_CS5),
+ IMX_PINCTRL_PIN(MX25_PAD_NF_CE0),
+ IMX_PINCTRL_PIN(MX25_PAD_ECB),
+ IMX_PINCTRL_PIN(MX25_PAD_LBA),
+ IMX_PINCTRL_PIN(MX25_PAD_BCLK),
+ IMX_PINCTRL_PIN(MX25_PAD_RW),
+ IMX_PINCTRL_PIN(MX25_PAD_NFWE_B),
+ IMX_PINCTRL_PIN(MX25_PAD_NFRE_B),
+ IMX_PINCTRL_PIN(MX25_PAD_NFALE),
+ IMX_PINCTRL_PIN(MX25_PAD_NFCLE),
+ IMX_PINCTRL_PIN(MX25_PAD_NFWP_B),
+ IMX_PINCTRL_PIN(MX25_PAD_NFRB),
+ IMX_PINCTRL_PIN(MX25_PAD_D15),
+ IMX_PINCTRL_PIN(MX25_PAD_D14),
+ IMX_PINCTRL_PIN(MX25_PAD_D13),
+ IMX_PINCTRL_PIN(MX25_PAD_D12),
+ IMX_PINCTRL_PIN(MX25_PAD_D11),
+ IMX_PINCTRL_PIN(MX25_PAD_D10),
+ IMX_PINCTRL_PIN(MX25_PAD_D9),
+ IMX_PINCTRL_PIN(MX25_PAD_D8),
+ IMX_PINCTRL_PIN(MX25_PAD_D7),
+ IMX_PINCTRL_PIN(MX25_PAD_D6),
+ IMX_PINCTRL_PIN(MX25_PAD_D5),
+ IMX_PINCTRL_PIN(MX25_PAD_D4),
+ IMX_PINCTRL_PIN(MX25_PAD_D3),
+ IMX_PINCTRL_PIN(MX25_PAD_D2),
+ IMX_PINCTRL_PIN(MX25_PAD_D1),
+ IMX_PINCTRL_PIN(MX25_PAD_D0),
+ IMX_PINCTRL_PIN(MX25_PAD_LD0),
+ IMX_PINCTRL_PIN(MX25_PAD_LD1),
+ IMX_PINCTRL_PIN(MX25_PAD_LD2),
+ IMX_PINCTRL_PIN(MX25_PAD_LD3),
+ IMX_PINCTRL_PIN(MX25_PAD_LD4),
+ IMX_PINCTRL_PIN(MX25_PAD_LD5),
+ IMX_PINCTRL_PIN(MX25_PAD_LD6),
+ IMX_PINCTRL_PIN(MX25_PAD_LD7),
+ IMX_PINCTRL_PIN(MX25_PAD_LD8),
+ IMX_PINCTRL_PIN(MX25_PAD_LD9),
+ IMX_PINCTRL_PIN(MX25_PAD_LD10),
+ IMX_PINCTRL_PIN(MX25_PAD_LD11),
+ IMX_PINCTRL_PIN(MX25_PAD_LD12),
+ IMX_PINCTRL_PIN(MX25_PAD_LD13),
+ IMX_PINCTRL_PIN(MX25_PAD_LD14),
+ IMX_PINCTRL_PIN(MX25_PAD_LD15),
+ IMX_PINCTRL_PIN(MX25_PAD_HSYNC),
+ IMX_PINCTRL_PIN(MX25_PAD_VSYNC),
+ IMX_PINCTRL_PIN(MX25_PAD_LSCLK),
+ IMX_PINCTRL_PIN(MX25_PAD_OE_ACD),
+ IMX_PINCTRL_PIN(MX25_PAD_CONTRAST),
+ IMX_PINCTRL_PIN(MX25_PAD_PWM),
+ IMX_PINCTRL_PIN(MX25_PAD_CSI_D2),
+ IMX_PINCTRL_PIN(MX25_PAD_CSI_D3),
+ IMX_PINCTRL_PIN(MX25_PAD_CSI_D4),
+ IMX_PINCTRL_PIN(MX25_PAD_CSI_D5),
+ IMX_PINCTRL_PIN(MX25_PAD_CSI_D6),
+ IMX_PINCTRL_PIN(MX25_PAD_CSI_D7),
+ IMX_PINCTRL_PIN(MX25_PAD_CSI_D8),
+ IMX_PINCTRL_PIN(MX25_PAD_CSI_D9),
+ IMX_PINCTRL_PIN(MX25_PAD_CSI_MCLK),
+ IMX_PINCTRL_PIN(MX25_PAD_CSI_VSYNC),
+ IMX_PINCTRL_PIN(MX25_PAD_CSI_HSYNC),
+ IMX_PINCTRL_PIN(MX25_PAD_CSI_PIXCLK),
+ IMX_PINCTRL_PIN(MX25_PAD_I2C1_CLK),
+ IMX_PINCTRL_PIN(MX25_PAD_I2C1_DAT),
+ IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MOSI),
+ IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MISO),
+ IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS0),
+ IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS1),
+ IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SCLK),
+ IMX_PINCTRL_PIN(MX25_PAD_CSPI1_RDY),
+ IMX_PINCTRL_PIN(MX25_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX25_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX25_PAD_UART1_RTS),
+ IMX_PINCTRL_PIN(MX25_PAD_UART1_CTS),
+ IMX_PINCTRL_PIN(MX25_PAD_UART2_RXD),
+ IMX_PINCTRL_PIN(MX25_PAD_UART2_TXD),
+ IMX_PINCTRL_PIN(MX25_PAD_UART2_RTS),
+ IMX_PINCTRL_PIN(MX25_PAD_UART2_CTS),
+ IMX_PINCTRL_PIN(MX25_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX25_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA0),
+ IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA1),
+ IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA2),
+ IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA3),
+ IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW0),
+ IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW1),
+ IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW2),
+ IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW3),
+ IMX_PINCTRL_PIN(MX25_PAD_KPP_COL0),
+ IMX_PINCTRL_PIN(MX25_PAD_KPP_COL1),
+ IMX_PINCTRL_PIN(MX25_PAD_KPP_COL2),
+ IMX_PINCTRL_PIN(MX25_PAD_KPP_COL3),
+ IMX_PINCTRL_PIN(MX25_PAD_FEC_MDC),
+ IMX_PINCTRL_PIN(MX25_PAD_FEC_MDIO),
+ IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA0),
+ IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA1),
+ IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_EN),
+ IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA0),
+ IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA1),
+ IMX_PINCTRL_PIN(MX25_PAD_FEC_RX_DV),
+ IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_CLK),
+ IMX_PINCTRL_PIN(MX25_PAD_RTCK),
+ IMX_PINCTRL_PIN(MX25_PAD_DE_B),
+ IMX_PINCTRL_PIN(MX25_PAD_GPIO_A),
+ IMX_PINCTRL_PIN(MX25_PAD_GPIO_B),
+ IMX_PINCTRL_PIN(MX25_PAD_GPIO_C),
+ IMX_PINCTRL_PIN(MX25_PAD_GPIO_D),
+ IMX_PINCTRL_PIN(MX25_PAD_GPIO_E),
+ IMX_PINCTRL_PIN(MX25_PAD_GPIO_F),
+ IMX_PINCTRL_PIN(MX25_PAD_EXT_ARMCLK),
+ IMX_PINCTRL_PIN(MX25_PAD_UPLL_BYPCLK),
+ IMX_PINCTRL_PIN(MX25_PAD_VSTBY_REQ),
+ IMX_PINCTRL_PIN(MX25_PAD_VSTBY_ACK),
+ IMX_PINCTRL_PIN(MX25_PAD_POWER_FAIL),
+ IMX_PINCTRL_PIN(MX25_PAD_CLKO),
+ IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE0),
+ IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1),
+};
+
+static struct imx_pinctrl_soc_info imx25_pinctrl_info = {
+ .pins = imx25_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx25_pinctrl_pads),
+};
+
+static const struct of_device_id imx25_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx25-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx25_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx25_pinctrl_info);
+}
+
+static struct platform_driver imx25_pinctrl_driver = {
+ .driver = {
+ .name = "imx25-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(imx25_pinctrl_of_match),
+ },
+ .probe = imx25_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+};
+
+static int __init imx25_pinctrl_init(void)
+{
+ return platform_driver_register(&imx25_pinctrl_driver);
+}
+arch_initcall(imx25_pinctrl_init);
+
+static void __exit imx25_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx25_pinctrl_driver);
+}
+module_exit(imx25_pinctrl_exit);
+MODULE_AUTHOR("Denis Carikli <denis@eukrea.com>");
+MODULE_DESCRIPTION("Freescale IMX25 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * imx27 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2013 Pengutronix
+ *
+ * Author: Markus Pargmann <mpa@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx1.h"
+
+#define PAD_ID(port, pin) (port*32 + pin)
+#define PA 0
+#define PB 1
+#define PC 2
+#define PD 3
+#define PE 4
+#define PF 5
+
+enum imx27_pads {
+ MX27_PAD_USBH2_CLK = PAD_ID(PA, 0),
+ MX27_PAD_USBH2_DIR = PAD_ID(PA, 1),
+ MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2),
+ MX27_PAD_USBH2_NXT = PAD_ID(PA, 3),
+ MX27_PAD_USBH2_STP = PAD_ID(PA, 4),
+ MX27_PAD_LSCLK = PAD_ID(PA, 5),
+ MX27_PAD_LD0 = PAD_ID(PA, 6),
+ MX27_PAD_LD1 = PAD_ID(PA, 7),
+ MX27_PAD_LD2 = PAD_ID(PA, 8),
+ MX27_PAD_LD3 = PAD_ID(PA, 9),
+ MX27_PAD_LD4 = PAD_ID(PA, 10),
+ MX27_PAD_LD5 = PAD_ID(PA, 11),
+ MX27_PAD_LD6 = PAD_ID(PA, 12),
+ MX27_PAD_LD7 = PAD_ID(PA, 13),
+ MX27_PAD_LD8 = PAD_ID(PA, 14),
+ MX27_PAD_LD9 = PAD_ID(PA, 15),
+ MX27_PAD_LD10 = PAD_ID(PA, 16),
+ MX27_PAD_LD11 = PAD_ID(PA, 17),
+ MX27_PAD_LD12 = PAD_ID(PA, 18),
+ MX27_PAD_LD13 = PAD_ID(PA, 19),
+ MX27_PAD_LD14 = PAD_ID(PA, 20),
+ MX27_PAD_LD15 = PAD_ID(PA, 21),
+ MX27_PAD_LD16 = PAD_ID(PA, 22),
+ MX27_PAD_LD17 = PAD_ID(PA, 23),
+ MX27_PAD_REV = PAD_ID(PA, 24),
+ MX27_PAD_CLS = PAD_ID(PA, 25),
+ MX27_PAD_PS = PAD_ID(PA, 26),
+ MX27_PAD_SPL_SPR = PAD_ID(PA, 27),
+ MX27_PAD_HSYNC = PAD_ID(PA, 28),
+ MX27_PAD_VSYNC = PAD_ID(PA, 29),
+ MX27_PAD_CONTRAST = PAD_ID(PA, 30),
+ MX27_PAD_OE_ACD = PAD_ID(PA, 31),
+
+ MX27_PAD_SD2_D0 = PAD_ID(PB, 4),
+ MX27_PAD_SD2_D1 = PAD_ID(PB, 5),
+ MX27_PAD_SD2_D2 = PAD_ID(PB, 6),
+ MX27_PAD_SD2_D3 = PAD_ID(PB, 7),
+ MX27_PAD_SD2_CMD = PAD_ID(PB, 8),
+ MX27_PAD_SD2_CLK = PAD_ID(PB, 9),
+ MX27_PAD_CSI_D0 = PAD_ID(PB, 10),
+ MX27_PAD_CSI_D1 = PAD_ID(PB, 11),
+ MX27_PAD_CSI_D2 = PAD_ID(PB, 12),
+ MX27_PAD_CSI_D3 = PAD_ID(PB, 13),
+ MX27_PAD_CSI_D4 = PAD_ID(PB, 14),
+ MX27_PAD_CSI_MCLK = PAD_ID(PB, 15),
+ MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
+ MX27_PAD_CSI_D5 = PAD_ID(PB, 17),
+ MX27_PAD_CSI_D6 = PAD_ID(PB, 18),
+ MX27_PAD_CSI_D7 = PAD_ID(PB, 19),
+ MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20),
+ MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21),
+ MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22),
+ MX27_PAD_USB_PWR = PAD_ID(PB, 23),
+ MX27_PAD_USB_OC_B = PAD_ID(PB, 24),
+ MX27_PAD_USBH1_RCV = PAD_ID(PB, 25),
+ MX27_PAD_USBH1_FS = PAD_ID(PB, 26),
+ MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27),
+ MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28),
+ MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29),
+ MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30),
+ MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31),
+
+ MX27_PAD_I2C2_SDA = PAD_ID(PC, 5),
+ MX27_PAD_I2C2_SCL = PAD_ID(PC, 6),
+ MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7),
+ MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8),
+ MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9),
+ MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10),
+ MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11),
+ MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12),
+ MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13),
+ MX27_PAD_TOUT = PAD_ID(PC, 14),
+ MX27_PAD_TIN = PAD_ID(PC, 15),
+ MX27_PAD_SSI4_FS = PAD_ID(PC, 16),
+ MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17),
+ MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18),
+ MX27_PAD_SSI4_CLK = PAD_ID(PC, 19),
+ MX27_PAD_SSI1_FS = PAD_ID(PC, 20),
+ MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21),
+ MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22),
+ MX27_PAD_SSI1_CLK = PAD_ID(PC, 23),
+ MX27_PAD_SSI2_FS = PAD_ID(PC, 24),
+ MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25),
+ MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26),
+ MX27_PAD_SSI2_CLK = PAD_ID(PC, 27),
+ MX27_PAD_SSI3_FS = PAD_ID(PC, 28),
+ MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29),
+ MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30),
+ MX27_PAD_SSI3_CLK = PAD_ID(PC, 31),
+
+ MX27_PAD_SD3_CMD = PAD_ID(PD, 0),
+ MX27_PAD_SD3_CLK = PAD_ID(PD, 1),
+ MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2),
+ MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3),
+ MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4),
+ MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5),
+ MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6),
+ MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7),
+ MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8),
+ MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9),
+ MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10),
+ MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11),
+ MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12),
+ MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13),
+ MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14),
+ MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15),
+ MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16),
+ MX27_PAD_I2C_DATA = PAD_ID(PD, 17),
+ MX27_PAD_I2C_CLK = PAD_ID(PD, 18),
+ MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
+ MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
+ MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
+ MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
+ MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23),
+ MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
+ MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25),
+ MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
+ MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
+ MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
+ MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
+ MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30),
+ MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
+
+ MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0),
+ MX27_PAD_USBOTG_STP = PAD_ID(PE, 1),
+ MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2),
+ MX27_PAD_UART2_CTS = PAD_ID(PE, 3),
+ MX27_PAD_UART2_RTS = PAD_ID(PE, 4),
+ MX27_PAD_PWMO = PAD_ID(PE, 5),
+ MX27_PAD_UART2_TXD = PAD_ID(PE, 6),
+ MX27_PAD_UART2_RXD = PAD_ID(PE, 7),
+ MX27_PAD_UART3_TXD = PAD_ID(PE, 8),
+ MX27_PAD_UART3_RXD = PAD_ID(PE, 9),
+ MX27_PAD_UART3_CTS = PAD_ID(PE, 10),
+ MX27_PAD_UART3_RTS = PAD_ID(PE, 11),
+ MX27_PAD_UART1_TXD = PAD_ID(PE, 12),
+ MX27_PAD_UART1_RXD = PAD_ID(PE, 13),
+ MX27_PAD_UART1_CTS = PAD_ID(PE, 14),
+ MX27_PAD_UART1_RTS = PAD_ID(PE, 15),
+ MX27_PAD_RTCK = PAD_ID(PE, 16),
+ MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17),
+ MX27_PAD_SD1_D0 = PAD_ID(PE, 18),
+ MX27_PAD_SD1_D1 = PAD_ID(PE, 19),
+ MX27_PAD_SD1_D2 = PAD_ID(PE, 20),
+ MX27_PAD_SD1_D3 = PAD_ID(PE, 21),
+ MX27_PAD_SD1_CMD = PAD_ID(PE, 22),
+ MX27_PAD_SD1_CLK = PAD_ID(PE, 23),
+ MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24),
+ MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25),
+
+ MX27_PAD_NFRB = PAD_ID(PF, 0),
+ MX27_PAD_NFCLE = PAD_ID(PF, 1),
+ MX27_PAD_NFWP_B = PAD_ID(PF, 2),
+ MX27_PAD_NFCE_B = PAD_ID(PF, 3),
+ MX27_PAD_NFALE = PAD_ID(PF, 4),
+ MX27_PAD_NFRE_B = PAD_ID(PF, 5),
+ MX27_PAD_NFWE_B = PAD_ID(PF, 6),
+ MX27_PAD_PC_POE = PAD_ID(PF, 7),
+ MX27_PAD_PC_RW_B = PAD_ID(PF, 8),
+ MX27_PAD_IOIS16 = PAD_ID(PF, 9),
+ MX27_PAD_PC_RST = PAD_ID(PF, 10),
+ MX27_PAD_PC_BVD2 = PAD_ID(PF, 11),
+ MX27_PAD_PC_BVD1 = PAD_ID(PF, 12),
+ MX27_PAD_PC_VS2 = PAD_ID(PF, 13),
+ MX27_PAD_PC_VS1 = PAD_ID(PF, 14),
+ MX27_PAD_CLKO = PAD_ID(PF, 15),
+ MX27_PAD_PC_PWRON = PAD_ID(PF, 16),
+ MX27_PAD_PC_READY = PAD_ID(PF, 17),
+ MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18),
+ MX27_PAD_PC_CD2_B = PAD_ID(PF, 19),
+ MX27_PAD_PC_CD1_B = PAD_ID(PF, 20),
+ MX27_PAD_CS4_B = PAD_ID(PF, 21),
+ MX27_PAD_CS5_B = PAD_ID(PF, 22),
+ MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP),
+ IMX_PINCTRL_PIN(MX27_PAD_LSCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_LD0),
+ IMX_PINCTRL_PIN(MX27_PAD_LD1),
+ IMX_PINCTRL_PIN(MX27_PAD_LD2),
+ IMX_PINCTRL_PIN(MX27_PAD_LD3),
+ IMX_PINCTRL_PIN(MX27_PAD_LD4),
+ IMX_PINCTRL_PIN(MX27_PAD_LD5),
+ IMX_PINCTRL_PIN(MX27_PAD_LD6),
+ IMX_PINCTRL_PIN(MX27_PAD_LD7),
+ IMX_PINCTRL_PIN(MX27_PAD_LD8),
+ IMX_PINCTRL_PIN(MX27_PAD_LD9),
+ IMX_PINCTRL_PIN(MX27_PAD_LD10),
+ IMX_PINCTRL_PIN(MX27_PAD_LD11),
+ IMX_PINCTRL_PIN(MX27_PAD_LD12),
+ IMX_PINCTRL_PIN(MX27_PAD_LD13),
+ IMX_PINCTRL_PIN(MX27_PAD_LD14),
+ IMX_PINCTRL_PIN(MX27_PAD_LD15),
+ IMX_PINCTRL_PIN(MX27_PAD_LD16),
+ IMX_PINCTRL_PIN(MX27_PAD_LD17),
+ IMX_PINCTRL_PIN(MX27_PAD_REV),
+ IMX_PINCTRL_PIN(MX27_PAD_CLS),
+ IMX_PINCTRL_PIN(MX27_PAD_PS),
+ IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR),
+ IMX_PINCTRL_PIN(MX27_PAD_HSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_VSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_CONTRAST),
+ IMX_PINCTRL_PIN(MX27_PAD_OE_ACD),
+
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D4),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D5),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D6),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D7),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP),
+ IMX_PINCTRL_PIN(MX27_PAD_USB_PWR),
+ IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP),
+
+ IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3),
+ IMX_PINCTRL_PIN(MX27_PAD_TOUT),
+ IMX_PINCTRL_PIN(MX27_PAD_TIN),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK),
+
+ IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI),
+
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_PWMO),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_RTCK),
+ IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7),
+
+ IMX_PINCTRL_PIN(MX27_PAD_NFRB),
+ IMX_PINCTRL_PIN(MX27_PAD_NFCLE),
+ IMX_PINCTRL_PIN(MX27_PAD_NFWP_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFCE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFALE),
+ IMX_PINCTRL_PIN(MX27_PAD_NFRE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFWE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_POE),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B),
+ IMX_PINCTRL_PIN(MX27_PAD_IOIS16),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_RST),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_VS2),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_VS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CLKO),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_READY),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B),
+ IMX_PINCTRL_PIN(MX27_PAD_CS4_B),
+ IMX_PINCTRL_PIN(MX27_PAD_CS5_B),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15),
+};
+
+static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
+ .pins = imx27_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx27_pinctrl_pads),
+};
+
+static const struct of_device_id imx27_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx27-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx27_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info);
+}
+
+static struct platform_driver imx27_pinctrl_driver = {
+ .driver = {
+ .name = "imx27-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(imx27_pinctrl_of_match),
+ },
+ .probe = imx27_pinctrl_probe,
+ .remove = imx1_pinctrl_core_remove,
+};
+
+static int __init imx27_pinctrl_init(void)
+{
+ return platform_driver_register(&imx27_pinctrl_driver);
+}
+arch_initcall(imx27_pinctrl_init);
+
+static void __exit imx27_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx27_pinctrl_driver);
+}
+module_exit(imx27_pinctrl_exit);
+MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>");
+MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mxs.h"
+
+enum imx28_pin_enum {
+ GPMI_D00 = PINID(0, 0),
+ GPMI_D01 = PINID(0, 1),
+ GPMI_D02 = PINID(0, 2),
+ GPMI_D03 = PINID(0, 3),
+ GPMI_D04 = PINID(0, 4),
+ GPMI_D05 = PINID(0, 5),
+ GPMI_D06 = PINID(0, 6),
+ GPMI_D07 = PINID(0, 7),
+ GPMI_CE0N = PINID(0, 16),
+ GPMI_CE1N = PINID(0, 17),
+ GPMI_CE2N = PINID(0, 18),
+ GPMI_CE3N = PINID(0, 19),
+ GPMI_RDY0 = PINID(0, 20),
+ GPMI_RDY1 = PINID(0, 21),
+ GPMI_RDY2 = PINID(0, 22),
+ GPMI_RDY3 = PINID(0, 23),
+ GPMI_RDN = PINID(0, 24),
+ GPMI_WRN = PINID(0, 25),
+ GPMI_ALE = PINID(0, 26),
+ GPMI_CLE = PINID(0, 27),
+ GPMI_RESETN = PINID(0, 28),
+ LCD_D00 = PINID(1, 0),
+ LCD_D01 = PINID(1, 1),
+ LCD_D02 = PINID(1, 2),
+ LCD_D03 = PINID(1, 3),
+ LCD_D04 = PINID(1, 4),
+ LCD_D05 = PINID(1, 5),
+ LCD_D06 = PINID(1, 6),
+ LCD_D07 = PINID(1, 7),
+ LCD_D08 = PINID(1, 8),
+ LCD_D09 = PINID(1, 9),
+ LCD_D10 = PINID(1, 10),
+ LCD_D11 = PINID(1, 11),
+ LCD_D12 = PINID(1, 12),
+ LCD_D13 = PINID(1, 13),
+ LCD_D14 = PINID(1, 14),
+ LCD_D15 = PINID(1, 15),
+ LCD_D16 = PINID(1, 16),
+ LCD_D17 = PINID(1, 17),
+ LCD_D18 = PINID(1, 18),
+ LCD_D19 = PINID(1, 19),
+ LCD_D20 = PINID(1, 20),
+ LCD_D21 = PINID(1, 21),
+ LCD_D22 = PINID(1, 22),
+ LCD_D23 = PINID(1, 23),
+ LCD_RD_E = PINID(1, 24),
+ LCD_WR_RWN = PINID(1, 25),
+ LCD_RS = PINID(1, 26),
+ LCD_CS = PINID(1, 27),
+ LCD_VSYNC = PINID(1, 28),
+ LCD_HSYNC = PINID(1, 29),
+ LCD_DOTCLK = PINID(1, 30),
+ LCD_ENABLE = PINID(1, 31),
+ SSP0_DATA0 = PINID(2, 0),
+ SSP0_DATA1 = PINID(2, 1),
+ SSP0_DATA2 = PINID(2, 2),
+ SSP0_DATA3 = PINID(2, 3),
+ SSP0_DATA4 = PINID(2, 4),
+ SSP0_DATA5 = PINID(2, 5),
+ SSP0_DATA6 = PINID(2, 6),
+ SSP0_DATA7 = PINID(2, 7),
+ SSP0_CMD = PINID(2, 8),
+ SSP0_DETECT = PINID(2, 9),
+ SSP0_SCK = PINID(2, 10),
+ SSP1_SCK = PINID(2, 12),
+ SSP1_CMD = PINID(2, 13),
+ SSP1_DATA0 = PINID(2, 14),
+ SSP1_DATA3 = PINID(2, 15),
+ SSP2_SCK = PINID(2, 16),
+ SSP2_MOSI = PINID(2, 17),
+ SSP2_MISO = PINID(2, 18),
+ SSP2_SS0 = PINID(2, 19),
+ SSP2_SS1 = PINID(2, 20),
+ SSP2_SS2 = PINID(2, 21),
+ SSP3_SCK = PINID(2, 24),
+ SSP3_MOSI = PINID(2, 25),
+ SSP3_MISO = PINID(2, 26),
+ SSP3_SS0 = PINID(2, 27),
+ AUART0_RX = PINID(3, 0),
+ AUART0_TX = PINID(3, 1),
+ AUART0_CTS = PINID(3, 2),
+ AUART0_RTS = PINID(3, 3),
+ AUART1_RX = PINID(3, 4),
+ AUART1_TX = PINID(3, 5),
+ AUART1_CTS = PINID(3, 6),
+ AUART1_RTS = PINID(3, 7),
+ AUART2_RX = PINID(3, 8),
+ AUART2_TX = PINID(3, 9),
+ AUART2_CTS = PINID(3, 10),
+ AUART2_RTS = PINID(3, 11),
+ AUART3_RX = PINID(3, 12),
+ AUART3_TX = PINID(3, 13),
+ AUART3_CTS = PINID(3, 14),
+ AUART3_RTS = PINID(3, 15),
+ PWM0 = PINID(3, 16),
+ PWM1 = PINID(3, 17),
+ PWM2 = PINID(3, 18),
+ SAIF0_MCLK = PINID(3, 20),
+ SAIF0_LRCLK = PINID(3, 21),
+ SAIF0_BITCLK = PINID(3, 22),
+ SAIF0_SDATA0 = PINID(3, 23),
+ I2C0_SCL = PINID(3, 24),
+ I2C0_SDA = PINID(3, 25),
+ SAIF1_SDATA0 = PINID(3, 26),
+ SPDIF = PINID(3, 27),
+ PWM3 = PINID(3, 28),
+ PWM4 = PINID(3, 29),
+ LCD_RESET = PINID(3, 30),
+ ENET0_MDC = PINID(4, 0),
+ ENET0_MDIO = PINID(4, 1),
+ ENET0_RX_EN = PINID(4, 2),
+ ENET0_RXD0 = PINID(4, 3),
+ ENET0_RXD1 = PINID(4, 4),
+ ENET0_TX_CLK = PINID(4, 5),
+ ENET0_TX_EN = PINID(4, 6),
+ ENET0_TXD0 = PINID(4, 7),
+ ENET0_TXD1 = PINID(4, 8),
+ ENET0_RXD2 = PINID(4, 9),
+ ENET0_RXD3 = PINID(4, 10),
+ ENET0_TXD2 = PINID(4, 11),
+ ENET0_TXD3 = PINID(4, 12),
+ ENET0_RX_CLK = PINID(4, 13),
+ ENET0_COL = PINID(4, 14),
+ ENET0_CRS = PINID(4, 15),
+ ENET_CLK = PINID(4, 16),
+ JTAG_RTCK = PINID(4, 20),
+ EMI_D00 = PINID(5, 0),
+ EMI_D01 = PINID(5, 1),
+ EMI_D02 = PINID(5, 2),
+ EMI_D03 = PINID(5, 3),
+ EMI_D04 = PINID(5, 4),
+ EMI_D05 = PINID(5, 5),
+ EMI_D06 = PINID(5, 6),
+ EMI_D07 = PINID(5, 7),
+ EMI_D08 = PINID(5, 8),
+ EMI_D09 = PINID(5, 9),
+ EMI_D10 = PINID(5, 10),
+ EMI_D11 = PINID(5, 11),
+ EMI_D12 = PINID(5, 12),
+ EMI_D13 = PINID(5, 13),
+ EMI_D14 = PINID(5, 14),
+ EMI_D15 = PINID(5, 15),
+ EMI_ODT0 = PINID(5, 16),
+ EMI_DQM0 = PINID(5, 17),
+ EMI_ODT1 = PINID(5, 18),
+ EMI_DQM1 = PINID(5, 19),
+ EMI_DDR_OPEN_FB = PINID(5, 20),
+ EMI_CLK = PINID(5, 21),
+ EMI_DQS0 = PINID(5, 22),
+ EMI_DQS1 = PINID(5, 23),
+ EMI_DDR_OPEN = PINID(5, 26),
+ EMI_A00 = PINID(6, 0),
+ EMI_A01 = PINID(6, 1),
+ EMI_A02 = PINID(6, 2),
+ EMI_A03 = PINID(6, 3),
+ EMI_A04 = PINID(6, 4),
+ EMI_A05 = PINID(6, 5),
+ EMI_A06 = PINID(6, 6),
+ EMI_A07 = PINID(6, 7),
+ EMI_A08 = PINID(6, 8),
+ EMI_A09 = PINID(6, 9),
+ EMI_A10 = PINID(6, 10),
+ EMI_A11 = PINID(6, 11),
+ EMI_A12 = PINID(6, 12),
+ EMI_A13 = PINID(6, 13),
+ EMI_A14 = PINID(6, 14),
+ EMI_BA0 = PINID(6, 16),
+ EMI_BA1 = PINID(6, 17),
+ EMI_BA2 = PINID(6, 18),
+ EMI_CASN = PINID(6, 19),
+ EMI_RASN = PINID(6, 20),
+ EMI_WEN = PINID(6, 21),
+ EMI_CE0N = PINID(6, 22),
+ EMI_CE1N = PINID(6, 23),
+ EMI_CKE = PINID(6, 24),
+};
+
+static const struct pinctrl_pin_desc imx28_pins[] = {
+ MXS_PINCTRL_PIN(GPMI_D00),
+ MXS_PINCTRL_PIN(GPMI_D01),
+ MXS_PINCTRL_PIN(GPMI_D02),
+ MXS_PINCTRL_PIN(GPMI_D03),
+ MXS_PINCTRL_PIN(GPMI_D04),
+ MXS_PINCTRL_PIN(GPMI_D05),
+ MXS_PINCTRL_PIN(GPMI_D06),
+ MXS_PINCTRL_PIN(GPMI_D07),
+ MXS_PINCTRL_PIN(GPMI_CE0N),
+ MXS_PINCTRL_PIN(GPMI_CE1N),
+ MXS_PINCTRL_PIN(GPMI_CE2N),
+ MXS_PINCTRL_PIN(GPMI_CE3N),
+ MXS_PINCTRL_PIN(GPMI_RDY0),
+ MXS_PINCTRL_PIN(GPMI_RDY1),
+ MXS_PINCTRL_PIN(GPMI_RDY2),
+ MXS_PINCTRL_PIN(GPMI_RDY3),
+ MXS_PINCTRL_PIN(GPMI_RDN),
+ MXS_PINCTRL_PIN(GPMI_WRN),
+ MXS_PINCTRL_PIN(GPMI_ALE),
+ MXS_PINCTRL_PIN(GPMI_CLE),
+ MXS_PINCTRL_PIN(GPMI_RESETN),
+ MXS_PINCTRL_PIN(LCD_D00),
+ MXS_PINCTRL_PIN(LCD_D01),
+ MXS_PINCTRL_PIN(LCD_D02),
+ MXS_PINCTRL_PIN(LCD_D03),
+ MXS_PINCTRL_PIN(LCD_D04),
+ MXS_PINCTRL_PIN(LCD_D05),
+ MXS_PINCTRL_PIN(LCD_D06),
+ MXS_PINCTRL_PIN(LCD_D07),
+ MXS_PINCTRL_PIN(LCD_D08),
+ MXS_PINCTRL_PIN(LCD_D09),
+ MXS_PINCTRL_PIN(LCD_D10),
+ MXS_PINCTRL_PIN(LCD_D11),
+ MXS_PINCTRL_PIN(LCD_D12),
+ MXS_PINCTRL_PIN(LCD_D13),
+ MXS_PINCTRL_PIN(LCD_D14),
+ MXS_PINCTRL_PIN(LCD_D15),
+ MXS_PINCTRL_PIN(LCD_D16),
+ MXS_PINCTRL_PIN(LCD_D17),
+ MXS_PINCTRL_PIN(LCD_D18),
+ MXS_PINCTRL_PIN(LCD_D19),
+ MXS_PINCTRL_PIN(LCD_D20),
+ MXS_PINCTRL_PIN(LCD_D21),
+ MXS_PINCTRL_PIN(LCD_D22),
+ MXS_PINCTRL_PIN(LCD_D23),
+ MXS_PINCTRL_PIN(LCD_RD_E),
+ MXS_PINCTRL_PIN(LCD_WR_RWN),
+ MXS_PINCTRL_PIN(LCD_RS),
+ MXS_PINCTRL_PIN(LCD_CS),
+ MXS_PINCTRL_PIN(LCD_VSYNC),
+ MXS_PINCTRL_PIN(LCD_HSYNC),
+ MXS_PINCTRL_PIN(LCD_DOTCLK),
+ MXS_PINCTRL_PIN(LCD_ENABLE),
+ MXS_PINCTRL_PIN(SSP0_DATA0),
+ MXS_PINCTRL_PIN(SSP0_DATA1),
+ MXS_PINCTRL_PIN(SSP0_DATA2),
+ MXS_PINCTRL_PIN(SSP0_DATA3),
+ MXS_PINCTRL_PIN(SSP0_DATA4),
+ MXS_PINCTRL_PIN(SSP0_DATA5),
+ MXS_PINCTRL_PIN(SSP0_DATA6),
+ MXS_PINCTRL_PIN(SSP0_DATA7),
+ MXS_PINCTRL_PIN(SSP0_CMD),
+ MXS_PINCTRL_PIN(SSP0_DETECT),
+ MXS_PINCTRL_PIN(SSP0_SCK),
+ MXS_PINCTRL_PIN(SSP1_SCK),
+ MXS_PINCTRL_PIN(SSP1_CMD),
+ MXS_PINCTRL_PIN(SSP1_DATA0),
+ MXS_PINCTRL_PIN(SSP1_DATA3),
+ MXS_PINCTRL_PIN(SSP2_SCK),
+ MXS_PINCTRL_PIN(SSP2_MOSI),
+ MXS_PINCTRL_PIN(SSP2_MISO),
+ MXS_PINCTRL_PIN(SSP2_SS0),
+ MXS_PINCTRL_PIN(SSP2_SS1),
+ MXS_PINCTRL_PIN(SSP2_SS2),
+ MXS_PINCTRL_PIN(SSP3_SCK),
+ MXS_PINCTRL_PIN(SSP3_MOSI),
+ MXS_PINCTRL_PIN(SSP3_MISO),
+ MXS_PINCTRL_PIN(SSP3_SS0),
+ MXS_PINCTRL_PIN(AUART0_RX),
+ MXS_PINCTRL_PIN(AUART0_TX),
+ MXS_PINCTRL_PIN(AUART0_CTS),
+ MXS_PINCTRL_PIN(AUART0_RTS),
+ MXS_PINCTRL_PIN(AUART1_RX),
+ MXS_PINCTRL_PIN(AUART1_TX),
+ MXS_PINCTRL_PIN(AUART1_CTS),
+ MXS_PINCTRL_PIN(AUART1_RTS),
+ MXS_PINCTRL_PIN(AUART2_RX),
+ MXS_PINCTRL_PIN(AUART2_TX),
+ MXS_PINCTRL_PIN(AUART2_CTS),
+ MXS_PINCTRL_PIN(AUART2_RTS),
+ MXS_PINCTRL_PIN(AUART3_RX),
+ MXS_PINCTRL_PIN(AUART3_TX),
+ MXS_PINCTRL_PIN(AUART3_CTS),
+ MXS_PINCTRL_PIN(AUART3_RTS),
+ MXS_PINCTRL_PIN(PWM0),
+ MXS_PINCTRL_PIN(PWM1),
+ MXS_PINCTRL_PIN(PWM2),
+ MXS_PINCTRL_PIN(SAIF0_MCLK),
+ MXS_PINCTRL_PIN(SAIF0_LRCLK),
+ MXS_PINCTRL_PIN(SAIF0_BITCLK),
+ MXS_PINCTRL_PIN(SAIF0_SDATA0),
+ MXS_PINCTRL_PIN(I2C0_SCL),
+ MXS_PINCTRL_PIN(I2C0_SDA),
+ MXS_PINCTRL_PIN(SAIF1_SDATA0),
+ MXS_PINCTRL_PIN(SPDIF),
+ MXS_PINCTRL_PIN(PWM3),
+ MXS_PINCTRL_PIN(PWM4),
+ MXS_PINCTRL_PIN(LCD_RESET),
+ MXS_PINCTRL_PIN(ENET0_MDC),
+ MXS_PINCTRL_PIN(ENET0_MDIO),
+ MXS_PINCTRL_PIN(ENET0_RX_EN),
+ MXS_PINCTRL_PIN(ENET0_RXD0),
+ MXS_PINCTRL_PIN(ENET0_RXD1),
+ MXS_PINCTRL_PIN(ENET0_TX_CLK),
+ MXS_PINCTRL_PIN(ENET0_TX_EN),
+ MXS_PINCTRL_PIN(ENET0_TXD0),
+ MXS_PINCTRL_PIN(ENET0_TXD1),
+ MXS_PINCTRL_PIN(ENET0_RXD2),
+ MXS_PINCTRL_PIN(ENET0_RXD3),
+ MXS_PINCTRL_PIN(ENET0_TXD2),
+ MXS_PINCTRL_PIN(ENET0_TXD3),
+ MXS_PINCTRL_PIN(ENET0_RX_CLK),
+ MXS_PINCTRL_PIN(ENET0_COL),
+ MXS_PINCTRL_PIN(ENET0_CRS),
+ MXS_PINCTRL_PIN(ENET_CLK),
+ MXS_PINCTRL_PIN(JTAG_RTCK),
+ MXS_PINCTRL_PIN(EMI_D00),
+ MXS_PINCTRL_PIN(EMI_D01),
+ MXS_PINCTRL_PIN(EMI_D02),
+ MXS_PINCTRL_PIN(EMI_D03),
+ MXS_PINCTRL_PIN(EMI_D04),
+ MXS_PINCTRL_PIN(EMI_D05),
+ MXS_PINCTRL_PIN(EMI_D06),
+ MXS_PINCTRL_PIN(EMI_D07),
+ MXS_PINCTRL_PIN(EMI_D08),
+ MXS_PINCTRL_PIN(EMI_D09),
+ MXS_PINCTRL_PIN(EMI_D10),
+ MXS_PINCTRL_PIN(EMI_D11),
+ MXS_PINCTRL_PIN(EMI_D12),
+ MXS_PINCTRL_PIN(EMI_D13),
+ MXS_PINCTRL_PIN(EMI_D14),
+ MXS_PINCTRL_PIN(EMI_D15),
+ MXS_PINCTRL_PIN(EMI_ODT0),
+ MXS_PINCTRL_PIN(EMI_DQM0),
+ MXS_PINCTRL_PIN(EMI_ODT1),
+ MXS_PINCTRL_PIN(EMI_DQM1),
+ MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
+ MXS_PINCTRL_PIN(EMI_CLK),
+ MXS_PINCTRL_PIN(EMI_DQS0),
+ MXS_PINCTRL_PIN(EMI_DQS1),
+ MXS_PINCTRL_PIN(EMI_DDR_OPEN),
+ MXS_PINCTRL_PIN(EMI_A00),
+ MXS_PINCTRL_PIN(EMI_A01),
+ MXS_PINCTRL_PIN(EMI_A02),
+ MXS_PINCTRL_PIN(EMI_A03),
+ MXS_PINCTRL_PIN(EMI_A04),
+ MXS_PINCTRL_PIN(EMI_A05),
+ MXS_PINCTRL_PIN(EMI_A06),
+ MXS_PINCTRL_PIN(EMI_A07),
+ MXS_PINCTRL_PIN(EMI_A08),
+ MXS_PINCTRL_PIN(EMI_A09),
+ MXS_PINCTRL_PIN(EMI_A10),
+ MXS_PINCTRL_PIN(EMI_A11),
+ MXS_PINCTRL_PIN(EMI_A12),
+ MXS_PINCTRL_PIN(EMI_A13),
+ MXS_PINCTRL_PIN(EMI_A14),
+ MXS_PINCTRL_PIN(EMI_BA0),
+ MXS_PINCTRL_PIN(EMI_BA1),
+ MXS_PINCTRL_PIN(EMI_BA2),
+ MXS_PINCTRL_PIN(EMI_CASN),
+ MXS_PINCTRL_PIN(EMI_RASN),
+ MXS_PINCTRL_PIN(EMI_WEN),
+ MXS_PINCTRL_PIN(EMI_CE0N),
+ MXS_PINCTRL_PIN(EMI_CE1N),
+ MXS_PINCTRL_PIN(EMI_CKE),
+};
+
+static struct mxs_regs imx28_regs = {
+ .muxsel = 0x100,
+ .drive = 0x300,
+ .pull = 0x600,
+};
+
+static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
+ .regs = &imx28_regs,
+ .pins = imx28_pins,
+ .npins = ARRAY_SIZE(imx28_pins),
+};
+
+static int imx28_pinctrl_probe(struct platform_device *pdev)
+{
+ return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
+}
+
+static const struct of_device_id imx28_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx28-pinctrl", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match);
+
+static struct platform_driver imx28_pinctrl_driver = {
+ .driver = {
+ .name = "imx28-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = imx28_pinctrl_of_match,
+ },
+ .probe = imx28_pinctrl_probe,
+ .remove = mxs_pinctrl_remove,
+};
+
+static int __init imx28_pinctrl_init(void)
+{
+ return platform_driver_register(&imx28_pinctrl_driver);
+}
+postcore_initcall(imx28_pinctrl_init);
+
+static void __exit imx28_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx28_pinctrl_driver);
+}
+module_exit(imx28_pinctrl_exit);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
+MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * imx35 pinctrl driver.
+ *
+ * This driver was mostly copied from the imx51 pinctrl driver which has:
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx35_pads {
+ MX35_PAD_RESERVE0 = 0,
+ MX35_PAD_CAPTURE = 1,
+ MX35_PAD_COMPARE = 2,
+ MX35_PAD_WDOG_RST = 3,
+ MX35_PAD_GPIO1_0 = 4,
+ MX35_PAD_GPIO1_1 = 5,
+ MX35_PAD_GPIO2_0 = 6,
+ MX35_PAD_GPIO3_0 = 7,
+ MX35_PAD_CLKO = 8,
+ MX35_PAD_VSTBY = 9,
+ MX35_PAD_A0 = 10,
+ MX35_PAD_A1 = 11,
+ MX35_PAD_A2 = 12,
+ MX35_PAD_A3 = 13,
+ MX35_PAD_A4 = 14,
+ MX35_PAD_A5 = 15,
+ MX35_PAD_A6 = 16,
+ MX35_PAD_A7 = 17,
+ MX35_PAD_A8 = 18,
+ MX35_PAD_A9 = 19,
+ MX35_PAD_A10 = 20,
+ MX35_PAD_MA10 = 21,
+ MX35_PAD_A11 = 22,
+ MX35_PAD_A12 = 23,
+ MX35_PAD_A13 = 24,
+ MX35_PAD_A14 = 25,
+ MX35_PAD_A15 = 26,
+ MX35_PAD_A16 = 27,
+ MX35_PAD_A17 = 28,
+ MX35_PAD_A18 = 29,
+ MX35_PAD_A19 = 30,
+ MX35_PAD_A20 = 31,
+ MX35_PAD_A21 = 32,
+ MX35_PAD_A22 = 33,
+ MX35_PAD_A23 = 34,
+ MX35_PAD_A24 = 35,
+ MX35_PAD_A25 = 36,
+ MX35_PAD_EB0 = 37,
+ MX35_PAD_EB1 = 38,
+ MX35_PAD_OE = 39,
+ MX35_PAD_CS0 = 40,
+ MX35_PAD_CS1 = 41,
+ MX35_PAD_CS2 = 42,
+ MX35_PAD_CS3 = 43,
+ MX35_PAD_CS4 = 44,
+ MX35_PAD_CS5 = 45,
+ MX35_PAD_NF_CE0 = 46,
+ MX35_PAD_LBA = 47,
+ MX35_PAD_BCLK = 48,
+ MX35_PAD_RW = 49,
+ MX35_PAD_NFWE_B = 50,
+ MX35_PAD_NFRE_B = 51,
+ MX35_PAD_NFALE = 52,
+ MX35_PAD_NFCLE = 53,
+ MX35_PAD_NFWP_B = 54,
+ MX35_PAD_NFRB = 55,
+ MX35_PAD_CSI_D8 = 56,
+ MX35_PAD_CSI_D9 = 57,
+ MX35_PAD_CSI_D10 = 58,
+ MX35_PAD_CSI_D11 = 59,
+ MX35_PAD_CSI_D12 = 60,
+ MX35_PAD_CSI_D13 = 61,
+ MX35_PAD_CSI_D14 = 62,
+ MX35_PAD_CSI_D15 = 63,
+ MX35_PAD_CSI_MCLK = 64,
+ MX35_PAD_CSI_VSYNC = 65,
+ MX35_PAD_CSI_HSYNC = 66,
+ MX35_PAD_CSI_PIXCLK = 67,
+ MX35_PAD_I2C1_CLK = 68,
+ MX35_PAD_I2C1_DAT = 69,
+ MX35_PAD_I2C2_CLK = 70,
+ MX35_PAD_I2C2_DAT = 71,
+ MX35_PAD_STXD4 = 72,
+ MX35_PAD_SRXD4 = 73,
+ MX35_PAD_SCK4 = 74,
+ MX35_PAD_STXFS4 = 75,
+ MX35_PAD_STXD5 = 76,
+ MX35_PAD_SRXD5 = 77,
+ MX35_PAD_SCK5 = 78,
+ MX35_PAD_STXFS5 = 79,
+ MX35_PAD_SCKR = 80,
+ MX35_PAD_FSR = 81,
+ MX35_PAD_HCKR = 82,
+ MX35_PAD_SCKT = 83,
+ MX35_PAD_FST = 84,
+ MX35_PAD_HCKT = 85,
+ MX35_PAD_TX5_RX0 = 86,
+ MX35_PAD_TX4_RX1 = 87,
+ MX35_PAD_TX3_RX2 = 88,
+ MX35_PAD_TX2_RX3 = 89,
+ MX35_PAD_TX1 = 90,
+ MX35_PAD_TX0 = 91,
+ MX35_PAD_CSPI1_MOSI = 92,
+ MX35_PAD_CSPI1_MISO = 93,
+ MX35_PAD_CSPI1_SS0 = 94,
+ MX35_PAD_CSPI1_SS1 = 95,
+ MX35_PAD_CSPI1_SCLK = 96,
+ MX35_PAD_CSPI1_SPI_RDY = 97,
+ MX35_PAD_RXD1 = 98,
+ MX35_PAD_TXD1 = 99,
+ MX35_PAD_RTS1 = 100,
+ MX35_PAD_CTS1 = 101,
+ MX35_PAD_RXD2 = 102,
+ MX35_PAD_TXD2 = 103,
+ MX35_PAD_RTS2 = 104,
+ MX35_PAD_CTS2 = 105,
+ MX35_PAD_USBOTG_PWR = 106,
+ MX35_PAD_USBOTG_OC = 107,
+ MX35_PAD_LD0 = 108,
+ MX35_PAD_LD1 = 109,
+ MX35_PAD_LD2 = 110,
+ MX35_PAD_LD3 = 111,
+ MX35_PAD_LD4 = 112,
+ MX35_PAD_LD5 = 113,
+ MX35_PAD_LD6 = 114,
+ MX35_PAD_LD7 = 115,
+ MX35_PAD_LD8 = 116,
+ MX35_PAD_LD9 = 117,
+ MX35_PAD_LD10 = 118,
+ MX35_PAD_LD11 = 119,
+ MX35_PAD_LD12 = 120,
+ MX35_PAD_LD13 = 121,
+ MX35_PAD_LD14 = 122,
+ MX35_PAD_LD15 = 123,
+ MX35_PAD_LD16 = 124,
+ MX35_PAD_LD17 = 125,
+ MX35_PAD_LD18 = 126,
+ MX35_PAD_LD19 = 127,
+ MX35_PAD_LD20 = 128,
+ MX35_PAD_LD21 = 129,
+ MX35_PAD_LD22 = 130,
+ MX35_PAD_LD23 = 131,
+ MX35_PAD_D3_HSYNC = 132,
+ MX35_PAD_D3_FPSHIFT = 133,
+ MX35_PAD_D3_DRDY = 134,
+ MX35_PAD_CONTRAST = 135,
+ MX35_PAD_D3_VSYNC = 136,
+ MX35_PAD_D3_REV = 137,
+ MX35_PAD_D3_CLS = 138,
+ MX35_PAD_D3_SPL = 139,
+ MX35_PAD_SD1_CMD = 140,
+ MX35_PAD_SD1_CLK = 141,
+ MX35_PAD_SD1_DATA0 = 142,
+ MX35_PAD_SD1_DATA1 = 143,
+ MX35_PAD_SD1_DATA2 = 144,
+ MX35_PAD_SD1_DATA3 = 145,
+ MX35_PAD_SD2_CMD = 146,
+ MX35_PAD_SD2_CLK = 147,
+ MX35_PAD_SD2_DATA0 = 148,
+ MX35_PAD_SD2_DATA1 = 149,
+ MX35_PAD_SD2_DATA2 = 150,
+ MX35_PAD_SD2_DATA3 = 151,
+ MX35_PAD_ATA_CS0 = 152,
+ MX35_PAD_ATA_CS1 = 153,
+ MX35_PAD_ATA_DIOR = 154,
+ MX35_PAD_ATA_DIOW = 155,
+ MX35_PAD_ATA_DMACK = 156,
+ MX35_PAD_ATA_RESET_B = 157,
+ MX35_PAD_ATA_IORDY = 158,
+ MX35_PAD_ATA_DATA0 = 159,
+ MX35_PAD_ATA_DATA1 = 160,
+ MX35_PAD_ATA_DATA2 = 161,
+ MX35_PAD_ATA_DATA3 = 162,
+ MX35_PAD_ATA_DATA4 = 163,
+ MX35_PAD_ATA_DATA5 = 164,
+ MX35_PAD_ATA_DATA6 = 165,
+ MX35_PAD_ATA_DATA7 = 166,
+ MX35_PAD_ATA_DATA8 = 167,
+ MX35_PAD_ATA_DATA9 = 168,
+ MX35_PAD_ATA_DATA10 = 169,
+ MX35_PAD_ATA_DATA11 = 170,
+ MX35_PAD_ATA_DATA12 = 171,
+ MX35_PAD_ATA_DATA13 = 172,
+ MX35_PAD_ATA_DATA14 = 173,
+ MX35_PAD_ATA_DATA15 = 174,
+ MX35_PAD_ATA_INTRQ = 175,
+ MX35_PAD_ATA_BUFF_EN = 176,
+ MX35_PAD_ATA_DMARQ = 177,
+ MX35_PAD_ATA_DA0 = 178,
+ MX35_PAD_ATA_DA1 = 179,
+ MX35_PAD_ATA_DA2 = 180,
+ MX35_PAD_MLB_CLK = 181,
+ MX35_PAD_MLB_DAT = 182,
+ MX35_PAD_MLB_SIG = 183,
+ MX35_PAD_FEC_TX_CLK = 184,
+ MX35_PAD_FEC_RX_CLK = 185,
+ MX35_PAD_FEC_RX_DV = 186,
+ MX35_PAD_FEC_COL = 187,
+ MX35_PAD_FEC_RDATA0 = 188,
+ MX35_PAD_FEC_TDATA0 = 189,
+ MX35_PAD_FEC_TX_EN = 190,
+ MX35_PAD_FEC_MDC = 191,
+ MX35_PAD_FEC_MDIO = 192,
+ MX35_PAD_FEC_TX_ERR = 193,
+ MX35_PAD_FEC_RX_ERR = 194,
+ MX35_PAD_FEC_CRS = 195,
+ MX35_PAD_FEC_RDATA1 = 196,
+ MX35_PAD_FEC_TDATA1 = 197,
+ MX35_PAD_FEC_RDATA2 = 198,
+ MX35_PAD_FEC_TDATA2 = 199,
+ MX35_PAD_FEC_RDATA3 = 200,
+ MX35_PAD_FEC_TDATA3 = 201,
+ MX35_PAD_RESERVE1 = 202,
+ MX35_PAD_RESERVE2 = 203,
+ MX35_PAD_RESERVE3 = 204,
+ MX35_PAD_RESERVE4 = 205,
+ MX35_PAD_RESERVE5 = 206,
+ MX35_PAD_RESERVE6 = 207,
+ MX35_PAD_RESERVE7 = 208,
+ MX35_PAD_RESET_IN_B = 209,
+ MX35_PAD_POR_B = 210,
+ MX35_PAD_RESERVE8 = 211,
+ MX35_PAD_BOOT_MODE0 = 212,
+ MX35_PAD_BOOT_MODE1 = 213,
+ MX35_PAD_CLK_MODE0 = 214,
+ MX35_PAD_CLK_MODE1 = 215,
+ MX35_PAD_POWER_FAIL = 216,
+ MX35_PAD_RESERVE9 = 217,
+ MX35_PAD_RESERVE10 = 218,
+ MX35_PAD_RESERVE11 = 219,
+ MX35_PAD_RESERVE12 = 220,
+ MX35_PAD_RESERVE13 = 221,
+ MX35_PAD_RESERVE14 = 222,
+ MX35_PAD_RESERVE15 = 223,
+ MX35_PAD_RESERVE16 = 224,
+ MX35_PAD_RESERVE17 = 225,
+ MX35_PAD_RESERVE18 = 226,
+ MX35_PAD_RESERVE19 = 227,
+ MX35_PAD_RESERVE20 = 228,
+ MX35_PAD_RESERVE21 = 229,
+ MX35_PAD_RESERVE22 = 230,
+ MX35_PAD_RESERVE23 = 231,
+ MX35_PAD_RESERVE24 = 232,
+ MX35_PAD_RESERVE25 = 233,
+ MX35_PAD_RESERVE26 = 234,
+ MX35_PAD_RESERVE27 = 235,
+ MX35_PAD_RESERVE28 = 236,
+ MX35_PAD_RESERVE29 = 237,
+ MX35_PAD_RESERVE30 = 238,
+ MX35_PAD_RESERVE31 = 239,
+ MX35_PAD_RESERVE32 = 240,
+ MX35_PAD_RESERVE33 = 241,
+ MX35_PAD_RESERVE34 = 242,
+ MX35_PAD_RESERVE35 = 243,
+ MX35_PAD_RESERVE36 = 244,
+ MX35_PAD_SDBA1 = 245,
+ MX35_PAD_SDBA0 = 246,
+ MX35_PAD_SD0 = 247,
+ MX35_PAD_SD1 = 248,
+ MX35_PAD_SD2 = 249,
+ MX35_PAD_SD3 = 250,
+ MX35_PAD_SD4 = 251,
+ MX35_PAD_SD5 = 252,
+ MX35_PAD_SD6 = 253,
+ MX35_PAD_SD7 = 254,
+ MX35_PAD_SD8 = 255,
+ MX35_PAD_SD9 = 256,
+ MX35_PAD_SD10 = 257,
+ MX35_PAD_SD11 = 258,
+ MX35_PAD_SD12 = 259,
+ MX35_PAD_SD13 = 260,
+ MX35_PAD_SD14 = 261,
+ MX35_PAD_SD15 = 262,
+ MX35_PAD_SD16 = 263,
+ MX35_PAD_SD17 = 264,
+ MX35_PAD_SD18 = 265,
+ MX35_PAD_SD19 = 266,
+ MX35_PAD_SD20 = 267,
+ MX35_PAD_SD21 = 268,
+ MX35_PAD_SD22 = 269,
+ MX35_PAD_SD23 = 270,
+ MX35_PAD_SD24 = 271,
+ MX35_PAD_SD25 = 272,
+ MX35_PAD_SD26 = 273,
+ MX35_PAD_SD27 = 274,
+ MX35_PAD_SD28 = 275,
+ MX35_PAD_SD29 = 276,
+ MX35_PAD_SD30 = 277,
+ MX35_PAD_SD31 = 278,
+ MX35_PAD_DQM0 = 279,
+ MX35_PAD_DQM1 = 280,
+ MX35_PAD_DQM2 = 281,
+ MX35_PAD_DQM3 = 282,
+ MX35_PAD_RESERVE37 = 283,
+ MX35_PAD_RESERVE38 = 284,
+ MX35_PAD_RESERVE39 = 285,
+ MX35_PAD_RESERVE40 = 286,
+ MX35_PAD_RESERVE41 = 287,
+ MX35_PAD_RESERVE42 = 288,
+ MX35_PAD_RESERVE43 = 289,
+ MX35_PAD_RESERVE44 = 290,
+ MX35_PAD_RESERVE45 = 291,
+ MX35_PAD_RESERVE46 = 292,
+ MX35_PAD_ECB = 293,
+ MX35_PAD_RESERVE47 = 294,
+ MX35_PAD_RESERVE48 = 295,
+ MX35_PAD_RESERVE49 = 296,
+ MX35_PAD_RAS = 297,
+ MX35_PAD_CAS = 298,
+ MX35_PAD_SDWE = 299,
+ MX35_PAD_SDCKE0 = 300,
+ MX35_PAD_SDCKE1 = 301,
+ MX35_PAD_SDCLK = 302,
+ MX35_PAD_SDQS0 = 303,
+ MX35_PAD_SDQS1 = 304,
+ MX35_PAD_SDQS2 = 305,
+ MX35_PAD_SDQS3 = 306,
+ MX35_PAD_RESERVE50 = 307,
+ MX35_PAD_RESERVE51 = 308,
+ MX35_PAD_RESERVE52 = 309,
+ MX35_PAD_RESERVE53 = 310,
+ MX35_PAD_RESERVE54 = 311,
+ MX35_PAD_RESERVE55 = 312,
+ MX35_PAD_D15 = 313,
+ MX35_PAD_D14 = 314,
+ MX35_PAD_D13 = 315,
+ MX35_PAD_D12 = 316,
+ MX35_PAD_D11 = 317,
+ MX35_PAD_D10 = 318,
+ MX35_PAD_D9 = 319,
+ MX35_PAD_D8 = 320,
+ MX35_PAD_D7 = 321,
+ MX35_PAD_D6 = 322,
+ MX35_PAD_D5 = 323,
+ MX35_PAD_D4 = 324,
+ MX35_PAD_D3 = 325,
+ MX35_PAD_D2 = 326,
+ MX35_PAD_D1 = 327,
+ MX35_PAD_D0 = 328,
+ MX35_PAD_RESERVE56 = 329,
+ MX35_PAD_RESERVE57 = 330,
+ MX35_PAD_RESERVE58 = 331,
+ MX35_PAD_RESERVE59 = 332,
+ MX35_PAD_RESERVE60 = 333,
+ MX35_PAD_RESERVE61 = 334,
+ MX35_PAD_RESERVE62 = 335,
+ MX35_PAD_RESERVE63 = 336,
+ MX35_PAD_RESERVE64 = 337,
+ MX35_PAD_RESERVE65 = 338,
+ MX35_PAD_RESERVE66 = 339,
+ MX35_PAD_RESERVE67 = 340,
+ MX35_PAD_RESERVE68 = 341,
+ MX35_PAD_RESERVE69 = 342,
+ MX35_PAD_RESERVE70 = 343,
+ MX35_PAD_RESERVE71 = 344,
+ MX35_PAD_RESERVE72 = 345,
+ MX35_PAD_RESERVE73 = 346,
+ MX35_PAD_RESERVE74 = 347,
+ MX35_PAD_RESERVE75 = 348,
+ MX35_PAD_RESERVE76 = 349,
+ MX35_PAD_RESERVE77 = 350,
+ MX35_PAD_RESERVE78 = 351,
+ MX35_PAD_RESERVE79 = 352,
+ MX35_PAD_RESERVE80 = 353,
+ MX35_PAD_RESERVE81 = 354,
+ MX35_PAD_RESERVE82 = 355,
+ MX35_PAD_RESERVE83 = 356,
+ MX35_PAD_RESERVE84 = 357,
+ MX35_PAD_RESERVE85 = 358,
+ MX35_PAD_RESERVE86 = 359,
+ MX35_PAD_RESERVE87 = 360,
+ MX35_PAD_RESERVE88 = 361,
+ MX35_PAD_RESERVE89 = 362,
+ MX35_PAD_RESERVE90 = 363,
+ MX35_PAD_RESERVE91 = 364,
+ MX35_PAD_RESERVE92 = 365,
+ MX35_PAD_RESERVE93 = 366,
+ MX35_PAD_RESERVE94 = 367,
+ MX35_PAD_RESERVE95 = 368,
+ MX35_PAD_RESERVE96 = 369,
+ MX35_PAD_RESERVE97 = 370,
+ MX35_PAD_RESERVE98 = 371,
+ MX35_PAD_RESERVE99 = 372,
+ MX35_PAD_RESERVE100 = 373,
+ MX35_PAD_RESERVE101 = 374,
+ MX35_PAD_RESERVE102 = 375,
+ MX35_PAD_RESERVE103 = 376,
+ MX35_PAD_RESERVE104 = 377,
+ MX35_PAD_RESERVE105 = 378,
+ MX35_PAD_RTCK = 379,
+ MX35_PAD_TCK = 380,
+ MX35_PAD_TMS = 381,
+ MX35_PAD_TDI = 382,
+ MX35_PAD_TDO = 383,
+ MX35_PAD_TRSTB = 384,
+ MX35_PAD_DE_B = 385,
+ MX35_PAD_SJC_MOD = 386,
+ MX35_PAD_RESERVE106 = 387,
+ MX35_PAD_RESERVE107 = 388,
+ MX35_PAD_RESERVE108 = 389,
+ MX35_PAD_RESERVE109 = 390,
+ MX35_PAD_RESERVE110 = 391,
+ MX35_PAD_RESERVE111 = 392,
+ MX35_PAD_RESERVE112 = 393,
+ MX35_PAD_RESERVE113 = 394,
+ MX35_PAD_RESERVE114 = 395,
+ MX35_PAD_RESERVE115 = 396,
+ MX35_PAD_RESERVE116 = 397,
+ MX35_PAD_RESERVE117 = 398,
+ MX35_PAD_RESERVE118 = 399,
+ MX35_PAD_RESERVE119 = 400,
+ MX35_PAD_RESERVE120 = 401,
+ MX35_PAD_RESERVE121 = 402,
+ MX35_PAD_RESERVE122 = 403,
+ MX35_PAD_RESERVE123 = 404,
+ MX35_PAD_RESERVE124 = 405,
+ MX35_PAD_RESERVE125 = 406,
+ MX35_PAD_RESERVE126 = 407,
+ MX35_PAD_RESERVE127 = 408,
+ MX35_PAD_RESERVE128 = 409,
+ MX35_PAD_RESERVE129 = 410,
+ MX35_PAD_RESERVE130 = 411,
+ MX35_PAD_RESERVE131 = 412,
+ MX35_PAD_RESERVE132 = 413,
+ MX35_PAD_RESERVE133 = 414,
+ MX35_PAD_RESERVE134 = 415,
+ MX35_PAD_RESERVE135 = 416,
+ MX35_PAD_RESERVE136 = 417,
+ MX35_PAD_RESERVE137 = 418,
+ MX35_PAD_RESERVE138 = 419,
+ MX35_PAD_RESERVE139 = 420,
+ MX35_PAD_RESERVE140 = 421,
+ MX35_PAD_RESERVE141 = 422,
+ MX35_PAD_RESERVE142 = 423,
+ MX35_PAD_RESERVE143 = 424,
+ MX35_PAD_RESERVE144 = 425,
+ MX35_PAD_RESERVE145 = 426,
+ MX35_PAD_RESERVE146 = 427,
+ MX35_PAD_RESERVE147 = 428,
+ MX35_PAD_RESERVE148 = 429,
+ MX35_PAD_RESERVE149 = 430,
+ MX35_PAD_RESERVE150 = 431,
+ MX35_PAD_RESERVE151 = 432,
+ MX35_PAD_RESERVE152 = 433,
+ MX35_PAD_RESERVE153 = 434,
+ MX35_PAD_RESERVE154 = 435,
+ MX35_PAD_RESERVE155 = 436,
+ MX35_PAD_RESERVE156 = 437,
+ MX35_PAD_RESERVE157 = 438,
+ MX35_PAD_RESERVE158 = 439,
+ MX35_PAD_RESERVE159 = 440,
+ MX35_PAD_RESERVE160 = 441,
+ MX35_PAD_RESERVE161 = 442,
+ MX35_PAD_RESERVE162 = 443,
+ MX35_PAD_RESERVE163 = 444,
+ MX35_PAD_RESERVE164 = 445,
+ MX35_PAD_RESERVE165 = 446,
+ MX35_PAD_RESERVE166 = 447,
+ MX35_PAD_RESERVE167 = 448,
+ MX35_PAD_RESERVE168 = 449,
+ MX35_PAD_RESERVE169 = 450,
+ MX35_PAD_RESERVE170 = 451,
+ MX35_PAD_RESERVE171 = 452,
+ MX35_PAD_RESERVE172 = 453,
+ MX35_PAD_RESERVE173 = 454,
+ MX35_PAD_RESERVE174 = 455,
+ MX35_PAD_RESERVE175 = 456,
+ MX35_PAD_RESERVE176 = 457,
+ MX35_PAD_RESERVE177 = 458,
+ MX35_PAD_RESERVE178 = 459,
+ MX35_PAD_RESERVE179 = 460,
+ MX35_PAD_RESERVE180 = 461,
+ MX35_PAD_RESERVE181 = 462,
+ MX35_PAD_RESERVE182 = 463,
+ MX35_PAD_RESERVE183 = 464,
+ MX35_PAD_RESERVE184 = 465,
+ MX35_PAD_RESERVE185 = 466,
+ MX35_PAD_RESERVE186 = 467,
+ MX35_PAD_RESERVE187 = 468,
+ MX35_PAD_RESERVE188 = 469,
+ MX35_PAD_RESERVE189 = 470,
+ MX35_PAD_RESERVE190 = 471,
+ MX35_PAD_RESERVE191 = 472,
+ MX35_PAD_RESERVE192 = 473,
+ MX35_PAD_RESERVE193 = 474,
+ MX35_PAD_RESERVE194 = 475,
+ MX35_PAD_RESERVE195 = 476,
+ MX35_PAD_RESERVE196 = 477,
+ MX35_PAD_RESERVE197 = 478,
+ MX35_PAD_RESERVE198 = 479,
+ MX35_PAD_RESERVE199 = 480,
+ MX35_PAD_RESERVE200 = 481,
+ MX35_PAD_RESERVE201 = 482,
+ MX35_PAD_EXT_ARMCLK = 483,
+ MX35_PAD_TEST_MODE = 484,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(MX35_PAD_CAPTURE),
+ IMX_PINCTRL_PIN(MX35_PAD_COMPARE),
+ IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST),
+ IMX_PINCTRL_PIN(MX35_PAD_GPIO1_0),
+ IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1),
+ IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0),
+ IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0),
+ IMX_PINCTRL_PIN(MX35_PAD_CLKO),
+ IMX_PINCTRL_PIN(MX35_PAD_VSTBY),
+ IMX_PINCTRL_PIN(MX35_PAD_A0),
+ IMX_PINCTRL_PIN(MX35_PAD_A1),
+ IMX_PINCTRL_PIN(MX35_PAD_A2),
+ IMX_PINCTRL_PIN(MX35_PAD_A3),
+ IMX_PINCTRL_PIN(MX35_PAD_A4),
+ IMX_PINCTRL_PIN(MX35_PAD_A5),
+ IMX_PINCTRL_PIN(MX35_PAD_A6),
+ IMX_PINCTRL_PIN(MX35_PAD_A7),
+ IMX_PINCTRL_PIN(MX35_PAD_A8),
+ IMX_PINCTRL_PIN(MX35_PAD_A9),
+ IMX_PINCTRL_PIN(MX35_PAD_A10),
+ IMX_PINCTRL_PIN(MX35_PAD_MA10),
+ IMX_PINCTRL_PIN(MX35_PAD_A11),
+ IMX_PINCTRL_PIN(MX35_PAD_A12),
+ IMX_PINCTRL_PIN(MX35_PAD_A13),
+ IMX_PINCTRL_PIN(MX35_PAD_A14),
+ IMX_PINCTRL_PIN(MX35_PAD_A15),
+ IMX_PINCTRL_PIN(MX35_PAD_A16),
+ IMX_PINCTRL_PIN(MX35_PAD_A17),
+ IMX_PINCTRL_PIN(MX35_PAD_A18),
+ IMX_PINCTRL_PIN(MX35_PAD_A19),
+ IMX_PINCTRL_PIN(MX35_PAD_A20),
+ IMX_PINCTRL_PIN(MX35_PAD_A21),
+ IMX_PINCTRL_PIN(MX35_PAD_A22),
+ IMX_PINCTRL_PIN(MX35_PAD_A23),
+ IMX_PINCTRL_PIN(MX35_PAD_A24),
+ IMX_PINCTRL_PIN(MX35_PAD_A25),
+ IMX_PINCTRL_PIN(MX35_PAD_EB0),
+ IMX_PINCTRL_PIN(MX35_PAD_EB1),
+ IMX_PINCTRL_PIN(MX35_PAD_OE),
+ IMX_PINCTRL_PIN(MX35_PAD_CS0),
+ IMX_PINCTRL_PIN(MX35_PAD_CS1),
+ IMX_PINCTRL_PIN(MX35_PAD_CS2),
+ IMX_PINCTRL_PIN(MX35_PAD_CS3),
+ IMX_PINCTRL_PIN(MX35_PAD_CS4),
+ IMX_PINCTRL_PIN(MX35_PAD_CS5),
+ IMX_PINCTRL_PIN(MX35_PAD_NF_CE0),
+ IMX_PINCTRL_PIN(MX35_PAD_LBA),
+ IMX_PINCTRL_PIN(MX35_PAD_BCLK),
+ IMX_PINCTRL_PIN(MX35_PAD_RW),
+ IMX_PINCTRL_PIN(MX35_PAD_NFWE_B),
+ IMX_PINCTRL_PIN(MX35_PAD_NFRE_B),
+ IMX_PINCTRL_PIN(MX35_PAD_NFALE),
+ IMX_PINCTRL_PIN(MX35_PAD_NFCLE),
+ IMX_PINCTRL_PIN(MX35_PAD_NFWP_B),
+ IMX_PINCTRL_PIN(MX35_PAD_NFRB),
+ IMX_PINCTRL_PIN(MX35_PAD_CSI_D8),
+ IMX_PINCTRL_PIN(MX35_PAD_CSI_D9),
+ IMX_PINCTRL_PIN(MX35_PAD_CSI_D10),
+ IMX_PINCTRL_PIN(MX35_PAD_CSI_D11),
+ IMX_PINCTRL_PIN(MX35_PAD_CSI_D12),
+ IMX_PINCTRL_PIN(MX35_PAD_CSI_D13),
+ IMX_PINCTRL_PIN(MX35_PAD_CSI_D14),
+ IMX_PINCTRL_PIN(MX35_PAD_CSI_D15),
+ IMX_PINCTRL_PIN(MX35_PAD_CSI_MCLK),
+ IMX_PINCTRL_PIN(MX35_PAD_CSI_VSYNC),
+ IMX_PINCTRL_PIN(MX35_PAD_CSI_HSYNC),
+ IMX_PINCTRL_PIN(MX35_PAD_CSI_PIXCLK),
+ IMX_PINCTRL_PIN(MX35_PAD_I2C1_CLK),
+ IMX_PINCTRL_PIN(MX35_PAD_I2C1_DAT),
+ IMX_PINCTRL_PIN(MX35_PAD_I2C2_CLK),
+ IMX_PINCTRL_PIN(MX35_PAD_I2C2_DAT),
+ IMX_PINCTRL_PIN(MX35_PAD_STXD4),
+ IMX_PINCTRL_PIN(MX35_PAD_SRXD4),
+ IMX_PINCTRL_PIN(MX35_PAD_SCK4),
+ IMX_PINCTRL_PIN(MX35_PAD_STXFS4),
+ IMX_PINCTRL_PIN(MX35_PAD_STXD5),
+ IMX_PINCTRL_PIN(MX35_PAD_SRXD5),
+ IMX_PINCTRL_PIN(MX35_PAD_SCK5),
+ IMX_PINCTRL_PIN(MX35_PAD_STXFS5),
+ IMX_PINCTRL_PIN(MX35_PAD_SCKR),
+ IMX_PINCTRL_PIN(MX35_PAD_FSR),
+ IMX_PINCTRL_PIN(MX35_PAD_HCKR),
+ IMX_PINCTRL_PIN(MX35_PAD_SCKT),
+ IMX_PINCTRL_PIN(MX35_PAD_FST),
+ IMX_PINCTRL_PIN(MX35_PAD_HCKT),
+ IMX_PINCTRL_PIN(MX35_PAD_TX5_RX0),
+ IMX_PINCTRL_PIN(MX35_PAD_TX4_RX1),
+ IMX_PINCTRL_PIN(MX35_PAD_TX3_RX2),
+ IMX_PINCTRL_PIN(MX35_PAD_TX2_RX3),
+ IMX_PINCTRL_PIN(MX35_PAD_TX1),
+ IMX_PINCTRL_PIN(MX35_PAD_TX0),
+ IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MOSI),
+ IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MISO),
+ IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS0),
+ IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS1),
+ IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SCLK),
+ IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SPI_RDY),
+ IMX_PINCTRL_PIN(MX35_PAD_RXD1),
+ IMX_PINCTRL_PIN(MX35_PAD_TXD1),
+ IMX_PINCTRL_PIN(MX35_PAD_RTS1),
+ IMX_PINCTRL_PIN(MX35_PAD_CTS1),
+ IMX_PINCTRL_PIN(MX35_PAD_RXD2),
+ IMX_PINCTRL_PIN(MX35_PAD_TXD2),
+ IMX_PINCTRL_PIN(MX35_PAD_RTS2),
+ IMX_PINCTRL_PIN(MX35_PAD_CTS2),
+ IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR),
+ IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC),
+ IMX_PINCTRL_PIN(MX35_PAD_LD0),
+ IMX_PINCTRL_PIN(MX35_PAD_LD1),
+ IMX_PINCTRL_PIN(MX35_PAD_LD2),
+ IMX_PINCTRL_PIN(MX35_PAD_LD3),
+ IMX_PINCTRL_PIN(MX35_PAD_LD4),
+ IMX_PINCTRL_PIN(MX35_PAD_LD5),
+ IMX_PINCTRL_PIN(MX35_PAD_LD6),
+ IMX_PINCTRL_PIN(MX35_PAD_LD7),
+ IMX_PINCTRL_PIN(MX35_PAD_LD8),
+ IMX_PINCTRL_PIN(MX35_PAD_LD9),
+ IMX_PINCTRL_PIN(MX35_PAD_LD10),
+ IMX_PINCTRL_PIN(MX35_PAD_LD11),
+ IMX_PINCTRL_PIN(MX35_PAD_LD12),
+ IMX_PINCTRL_PIN(MX35_PAD_LD13),
+ IMX_PINCTRL_PIN(MX35_PAD_LD14),
+ IMX_PINCTRL_PIN(MX35_PAD_LD15),
+ IMX_PINCTRL_PIN(MX35_PAD_LD16),
+ IMX_PINCTRL_PIN(MX35_PAD_LD17),
+ IMX_PINCTRL_PIN(MX35_PAD_LD18),
+ IMX_PINCTRL_PIN(MX35_PAD_LD19),
+ IMX_PINCTRL_PIN(MX35_PAD_LD20),
+ IMX_PINCTRL_PIN(MX35_PAD_LD21),
+ IMX_PINCTRL_PIN(MX35_PAD_LD22),
+ IMX_PINCTRL_PIN(MX35_PAD_LD23),
+ IMX_PINCTRL_PIN(MX35_PAD_D3_HSYNC),
+ IMX_PINCTRL_PIN(MX35_PAD_D3_FPSHIFT),
+ IMX_PINCTRL_PIN(MX35_PAD_D3_DRDY),
+ IMX_PINCTRL_PIN(MX35_PAD_CONTRAST),
+ IMX_PINCTRL_PIN(MX35_PAD_D3_VSYNC),
+ IMX_PINCTRL_PIN(MX35_PAD_D3_REV),
+ IMX_PINCTRL_PIN(MX35_PAD_D3_CLS),
+ IMX_PINCTRL_PIN(MX35_PAD_D3_SPL),
+ IMX_PINCTRL_PIN(MX35_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX35_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA0),
+ IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA1),
+ IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA2),
+ IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA3),
+ IMX_PINCTRL_PIN(MX35_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX35_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA0),
+ IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA1),
+ IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA2),
+ IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA3),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_CS0),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_CS1),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOR),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOW),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DMACK),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_RESET_B),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_IORDY),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA0),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA1),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA2),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA3),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA4),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA5),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA6),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA7),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA8),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA9),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA10),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA11),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA12),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA13),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA14),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA15),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_INTRQ),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_BUFF_EN),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DMARQ),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DA0),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DA1),
+ IMX_PINCTRL_PIN(MX35_PAD_ATA_DA2),
+ IMX_PINCTRL_PIN(MX35_PAD_MLB_CLK),
+ IMX_PINCTRL_PIN(MX35_PAD_MLB_DAT),
+ IMX_PINCTRL_PIN(MX35_PAD_MLB_SIG),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_CLK),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_CLK),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_DV),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_COL),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA0),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA0),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_EN),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_MDC),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_MDIO),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_ERR),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_ERR),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_CRS),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA1),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA1),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA2),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3),
+ IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE2),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE3),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE4),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE5),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE6),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE7),
+ IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B),
+ IMX_PINCTRL_PIN(MX35_PAD_POR_B),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE8),
+ IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0),
+ IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1),
+ IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0),
+ IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1),
+ IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE9),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE10),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE11),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE12),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE13),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE14),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE15),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE16),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE17),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE18),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE19),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE20),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE21),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE22),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE23),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE24),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE25),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE26),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE27),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE28),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE29),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE30),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE31),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE32),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE33),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE34),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE35),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE36),
+ IMX_PINCTRL_PIN(MX35_PAD_SDBA1),
+ IMX_PINCTRL_PIN(MX35_PAD_SDBA0),
+ IMX_PINCTRL_PIN(MX35_PAD_SD0),
+ IMX_PINCTRL_PIN(MX35_PAD_SD1),
+ IMX_PINCTRL_PIN(MX35_PAD_SD2),
+ IMX_PINCTRL_PIN(MX35_PAD_SD3),
+ IMX_PINCTRL_PIN(MX35_PAD_SD4),
+ IMX_PINCTRL_PIN(MX35_PAD_SD5),
+ IMX_PINCTRL_PIN(MX35_PAD_SD6),
+ IMX_PINCTRL_PIN(MX35_PAD_SD7),
+ IMX_PINCTRL_PIN(MX35_PAD_SD8),
+ IMX_PINCTRL_PIN(MX35_PAD_SD9),
+ IMX_PINCTRL_PIN(MX35_PAD_SD10),
+ IMX_PINCTRL_PIN(MX35_PAD_SD11),
+ IMX_PINCTRL_PIN(MX35_PAD_SD12),
+ IMX_PINCTRL_PIN(MX35_PAD_SD13),
+ IMX_PINCTRL_PIN(MX35_PAD_SD14),
+ IMX_PINCTRL_PIN(MX35_PAD_SD15),
+ IMX_PINCTRL_PIN(MX35_PAD_SD16),
+ IMX_PINCTRL_PIN(MX35_PAD_SD17),
+ IMX_PINCTRL_PIN(MX35_PAD_SD18),
+ IMX_PINCTRL_PIN(MX35_PAD_SD19),
+ IMX_PINCTRL_PIN(MX35_PAD_SD20),
+ IMX_PINCTRL_PIN(MX35_PAD_SD21),
+ IMX_PINCTRL_PIN(MX35_PAD_SD22),
+ IMX_PINCTRL_PIN(MX35_PAD_SD23),
+ IMX_PINCTRL_PIN(MX35_PAD_SD24),
+ IMX_PINCTRL_PIN(MX35_PAD_SD25),
+ IMX_PINCTRL_PIN(MX35_PAD_SD26),
+ IMX_PINCTRL_PIN(MX35_PAD_SD27),
+ IMX_PINCTRL_PIN(MX35_PAD_SD28),
+ IMX_PINCTRL_PIN(MX35_PAD_SD29),
+ IMX_PINCTRL_PIN(MX35_PAD_SD30),
+ IMX_PINCTRL_PIN(MX35_PAD_SD31),
+ IMX_PINCTRL_PIN(MX35_PAD_DQM0),
+ IMX_PINCTRL_PIN(MX35_PAD_DQM1),
+ IMX_PINCTRL_PIN(MX35_PAD_DQM2),
+ IMX_PINCTRL_PIN(MX35_PAD_DQM3),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE37),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE38),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE39),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE40),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE41),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE42),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE43),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE44),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE45),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE46),
+ IMX_PINCTRL_PIN(MX35_PAD_ECB),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE47),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE48),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE49),
+ IMX_PINCTRL_PIN(MX35_PAD_RAS),
+ IMX_PINCTRL_PIN(MX35_PAD_CAS),
+ IMX_PINCTRL_PIN(MX35_PAD_SDWE),
+ IMX_PINCTRL_PIN(MX35_PAD_SDCKE0),
+ IMX_PINCTRL_PIN(MX35_PAD_SDCKE1),
+ IMX_PINCTRL_PIN(MX35_PAD_SDCLK),
+ IMX_PINCTRL_PIN(MX35_PAD_SDQS0),
+ IMX_PINCTRL_PIN(MX35_PAD_SDQS1),
+ IMX_PINCTRL_PIN(MX35_PAD_SDQS2),
+ IMX_PINCTRL_PIN(MX35_PAD_SDQS3),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE50),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE51),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE52),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE53),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE54),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE55),
+ IMX_PINCTRL_PIN(MX35_PAD_D15),
+ IMX_PINCTRL_PIN(MX35_PAD_D14),
+ IMX_PINCTRL_PIN(MX35_PAD_D13),
+ IMX_PINCTRL_PIN(MX35_PAD_D12),
+ IMX_PINCTRL_PIN(MX35_PAD_D11),
+ IMX_PINCTRL_PIN(MX35_PAD_D10),
+ IMX_PINCTRL_PIN(MX35_PAD_D9),
+ IMX_PINCTRL_PIN(MX35_PAD_D8),
+ IMX_PINCTRL_PIN(MX35_PAD_D7),
+ IMX_PINCTRL_PIN(MX35_PAD_D6),
+ IMX_PINCTRL_PIN(MX35_PAD_D5),
+ IMX_PINCTRL_PIN(MX35_PAD_D4),
+ IMX_PINCTRL_PIN(MX35_PAD_D3),
+ IMX_PINCTRL_PIN(MX35_PAD_D2),
+ IMX_PINCTRL_PIN(MX35_PAD_D1),
+ IMX_PINCTRL_PIN(MX35_PAD_D0),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE56),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE57),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE58),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE59),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE60),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE61),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE62),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE63),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE64),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE65),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE66),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE67),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE68),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE69),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE70),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE71),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE72),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE73),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE74),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE75),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE76),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE77),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE78),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE79),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE80),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE81),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE82),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE83),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE84),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE85),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE86),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE87),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE88),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE89),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE90),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE91),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE92),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE93),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE94),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE95),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE96),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE97),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE98),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE99),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE100),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE101),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE102),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE103),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE104),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE105),
+ IMX_PINCTRL_PIN(MX35_PAD_RTCK),
+ IMX_PINCTRL_PIN(MX35_PAD_TCK),
+ IMX_PINCTRL_PIN(MX35_PAD_TMS),
+ IMX_PINCTRL_PIN(MX35_PAD_TDI),
+ IMX_PINCTRL_PIN(MX35_PAD_TDO),
+ IMX_PINCTRL_PIN(MX35_PAD_TRSTB),
+ IMX_PINCTRL_PIN(MX35_PAD_DE_B),
+ IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE106),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE107),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE108),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE109),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE110),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE111),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE112),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE113),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE114),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE115),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE116),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE117),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE118),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE119),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE120),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE121),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE122),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE123),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE124),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE125),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE126),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE127),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE128),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE129),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE130),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE131),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE132),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE133),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE134),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE135),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE136),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE137),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE138),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE139),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE140),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE141),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE142),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE143),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE144),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE145),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE146),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE147),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE148),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE149),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE150),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE151),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE152),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE153),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE154),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE155),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE156),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE157),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE158),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE159),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE160),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE161),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE162),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE163),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE164),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE165),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE166),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE167),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE168),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE169),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE170),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE171),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE172),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE173),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE174),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE175),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE176),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE177),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE178),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE179),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE180),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE181),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE182),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE183),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE184),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE185),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE186),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE187),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE188),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE189),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE190),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE191),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE192),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE193),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE194),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE195),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE196),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE197),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE198),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE199),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE200),
+ IMX_PINCTRL_PIN(MX35_PAD_RESERVE201),
+ IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK),
+ IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE),
+};
+
+static struct imx_pinctrl_soc_info imx35_pinctrl_info = {
+ .pins = imx35_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx35_pinctrl_pads),
+};
+
+static const struct of_device_id imx35_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx35-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx35_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx35_pinctrl_info);
+}
+
+static struct platform_driver imx35_pinctrl_driver = {
+ .driver = {
+ .name = "imx35-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = imx35_pinctrl_of_match,
+ },
+ .probe = imx35_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+};
+
+static int __init imx35_pinctrl_init(void)
+{
+ return platform_driver_register(&imx35_pinctrl_driver);
+}
+arch_initcall(imx35_pinctrl_init);
+
+static void __exit imx35_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx35_pinctrl_driver);
+}
+module_exit(imx35_pinctrl_exit);
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
+MODULE_DESCRIPTION("Freescale IMX35 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * imx50 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx50_pads {
+ MX50_PAD_RESERVE0 = 0,
+ MX50_PAD_RESERVE1 = 1,
+ MX50_PAD_RESERVE2 = 2,
+ MX50_PAD_RESERVE3 = 3,
+ MX50_PAD_RESERVE4 = 4,
+ MX50_PAD_RESERVE5 = 5,
+ MX50_PAD_RESERVE6 = 6,
+ MX50_PAD_RESERVE7 = 7,
+ MX50_PAD_KEY_COL0 = 8,
+ MX50_PAD_KEY_ROW0 = 9,
+ MX50_PAD_KEY_COL1 = 10,
+ MX50_PAD_KEY_ROW1 = 11,
+ MX50_PAD_KEY_COL2 = 12,
+ MX50_PAD_KEY_ROW2 = 13,
+ MX50_PAD_KEY_COL3 = 14,
+ MX50_PAD_KEY_ROW3 = 15,
+ MX50_PAD_I2C1_SCL = 16,
+ MX50_PAD_I2C1_SDA = 17,
+ MX50_PAD_I2C2_SCL = 18,
+ MX50_PAD_I2C2_SDA = 19,
+ MX50_PAD_I2C3_SCL = 20,
+ MX50_PAD_I2C3_SDA = 21,
+ MX50_PAD_PWM1 = 22,
+ MX50_PAD_PWM2 = 23,
+ MX50_PAD_0WIRE = 24,
+ MX50_PAD_EPITO = 25,
+ MX50_PAD_WDOG = 26,
+ MX50_PAD_SSI_TXFS = 27,
+ MX50_PAD_SSI_TXC = 28,
+ MX50_PAD_SSI_TXD = 29,
+ MX50_PAD_SSI_RXD = 30,
+ MX50_PAD_SSI_RXF = 31,
+ MX50_PAD_SSI_RXC = 32,
+ MX50_PAD_UART1_TXD = 33,
+ MX50_PAD_UART1_RXD = 34,
+ MX50_PAD_UART1_CTS = 35,
+ MX50_PAD_UART1_RTS = 36,
+ MX50_PAD_UART2_TXD = 37,
+ MX50_PAD_UART2_RXD = 38,
+ MX50_PAD_UART2_CTS = 39,
+ MX50_PAD_UART2_RTS = 40,
+ MX50_PAD_UART3_TXD = 41,
+ MX50_PAD_UART3_RXD = 42,
+ MX50_PAD_UART4_TXD = 43,
+ MX50_PAD_UART4_RXD = 44,
+ MX50_PAD_CSPI_CLK = 45,
+ MX50_PAD_CSPI_MOSI = 46,
+ MX50_PAD_CSPI_MISO = 47,
+ MX50_PAD_CSPI_SS0 = 48,
+ MX50_PAD_ECSPI1_CLK = 49,
+ MX50_PAD_ECSPI1_MOSI = 50,
+ MX50_PAD_ECSPI1_MISO = 51,
+ MX50_PAD_ECSPI1_SS0 = 52,
+ MX50_PAD_ECSPI2_CLK = 53,
+ MX50_PAD_ECSPI2_MOSI = 54,
+ MX50_PAD_ECSPI2_MISO = 55,
+ MX50_PAD_ECSPI2_SS0 = 56,
+ MX50_PAD_SD1_CLK = 57,
+ MX50_PAD_SD1_CMD = 58,
+ MX50_PAD_SD1_D0 = 59,
+ MX50_PAD_SD1_D1 = 60,
+ MX50_PAD_SD1_D2 = 61,
+ MX50_PAD_SD1_D3 = 62,
+ MX50_PAD_SD2_CLK = 63,
+ MX50_PAD_SD2_CMD = 64,
+ MX50_PAD_SD2_D0 = 65,
+ MX50_PAD_SD2_D1 = 66,
+ MX50_PAD_SD2_D2 = 67,
+ MX50_PAD_SD2_D3 = 68,
+ MX50_PAD_SD2_D4 = 69,
+ MX50_PAD_SD2_D5 = 70,
+ MX50_PAD_SD2_D6 = 71,
+ MX50_PAD_SD2_D7 = 72,
+ MX50_PAD_SD2_WP = 73,
+ MX50_PAD_SD2_CD = 74,
+ MX50_PAD_DISP_D0 = 75,
+ MX50_PAD_DISP_D1 = 76,
+ MX50_PAD_DISP_D2 = 77,
+ MX50_PAD_DISP_D3 = 78,
+ MX50_PAD_DISP_D4 = 79,
+ MX50_PAD_DISP_D5 = 80,
+ MX50_PAD_DISP_D6 = 81,
+ MX50_PAD_DISP_D7 = 82,
+ MX50_PAD_DISP_WR = 83,
+ MX50_PAD_DISP_RD = 84,
+ MX50_PAD_DISP_RS = 85,
+ MX50_PAD_DISP_CS = 86,
+ MX50_PAD_DISP_BUSY = 87,
+ MX50_PAD_DISP_RESET = 88,
+ MX50_PAD_SD3_CLK = 89,
+ MX50_PAD_SD3_CMD = 90,
+ MX50_PAD_SD3_D0 = 91,
+ MX50_PAD_SD3_D1 = 92,
+ MX50_PAD_SD3_D2 = 93,
+ MX50_PAD_SD3_D3 = 94,
+ MX50_PAD_SD3_D4 = 95,
+ MX50_PAD_SD3_D5 = 96,
+ MX50_PAD_SD3_D6 = 97,
+ MX50_PAD_SD3_D7 = 98,
+ MX50_PAD_SD3_WP = 99,
+ MX50_PAD_DISP_D8 = 100,
+ MX50_PAD_DISP_D9 = 101,
+ MX50_PAD_DISP_D10 = 102,
+ MX50_PAD_DISP_D11 = 103,
+ MX50_PAD_DISP_D12 = 104,
+ MX50_PAD_DISP_D13 = 105,
+ MX50_PAD_DISP_D14 = 106,
+ MX50_PAD_DISP_D15 = 107,
+ MX50_PAD_EPDC_D0 = 108,
+ MX50_PAD_EPDC_D1 = 109,
+ MX50_PAD_EPDC_D2 = 110,
+ MX50_PAD_EPDC_D3 = 111,
+ MX50_PAD_EPDC_D4 = 112,
+ MX50_PAD_EPDC_D5 = 113,
+ MX50_PAD_EPDC_D6 = 114,
+ MX50_PAD_EPDC_D7 = 115,
+ MX50_PAD_EPDC_D8 = 116,
+ MX50_PAD_EPDC_D9 = 117,
+ MX50_PAD_EPDC_D10 = 118,
+ MX50_PAD_EPDC_D11 = 119,
+ MX50_PAD_EPDC_D12 = 120,
+ MX50_PAD_EPDC_D13 = 121,
+ MX50_PAD_EPDC_D14 = 122,
+ MX50_PAD_EPDC_D15 = 123,
+ MX50_PAD_EPDC_GDCLK = 124,
+ MX50_PAD_EPDC_GDSP = 125,
+ MX50_PAD_EPDC_GDOE = 126,
+ MX50_PAD_EPDC_GDRL = 127,
+ MX50_PAD_EPDC_SDCLK = 128,
+ MX50_PAD_EPDC_SDOEZ = 129,
+ MX50_PAD_EPDC_SDOED = 130,
+ MX50_PAD_EPDC_SDOE = 131,
+ MX50_PAD_EPDC_SDLE = 132,
+ MX50_PAD_EPDC_SDCLKN = 133,
+ MX50_PAD_EPDC_SDSHR = 134,
+ MX50_PAD_EPDC_PWRCOM = 135,
+ MX50_PAD_EPDC_PWRSTAT = 136,
+ MX50_PAD_EPDC_PWRCTRL0 = 137,
+ MX50_PAD_EPDC_PWRCTRL1 = 138,
+ MX50_PAD_EPDC_PWRCTRL2 = 139,
+ MX50_PAD_EPDC_PWRCTRL3 = 140,
+ MX50_PAD_EPDC_VCOM0 = 141,
+ MX50_PAD_EPDC_VCOM1 = 142,
+ MX50_PAD_EPDC_BDR0 = 143,
+ MX50_PAD_EPDC_BDR1 = 144,
+ MX50_PAD_EPDC_SDCE0 = 145,
+ MX50_PAD_EPDC_SDCE1 = 146,
+ MX50_PAD_EPDC_SDCE2 = 147,
+ MX50_PAD_EPDC_SDCE3 = 148,
+ MX50_PAD_EPDC_SDCE4 = 149,
+ MX50_PAD_EPDC_SDCE5 = 150,
+ MX50_PAD_EIM_DA0 = 151,
+ MX50_PAD_EIM_DA1 = 152,
+ MX50_PAD_EIM_DA2 = 153,
+ MX50_PAD_EIM_DA3 = 154,
+ MX50_PAD_EIM_DA4 = 155,
+ MX50_PAD_EIM_DA5 = 156,
+ MX50_PAD_EIM_DA6 = 157,
+ MX50_PAD_EIM_DA7 = 158,
+ MX50_PAD_EIM_DA8 = 159,
+ MX50_PAD_EIM_DA9 = 160,
+ MX50_PAD_EIM_DA10 = 161,
+ MX50_PAD_EIM_DA11 = 162,
+ MX50_PAD_EIM_DA12 = 163,
+ MX50_PAD_EIM_DA13 = 164,
+ MX50_PAD_EIM_DA14 = 165,
+ MX50_PAD_EIM_DA15 = 166,
+ MX50_PAD_EIM_CS2 = 167,
+ MX50_PAD_EIM_CS1 = 168,
+ MX50_PAD_EIM_CS0 = 169,
+ MX50_PAD_EIM_EB0 = 170,
+ MX50_PAD_EIM_EB1 = 171,
+ MX50_PAD_EIM_WAIT = 172,
+ MX50_PAD_EIM_BCLK = 173,
+ MX50_PAD_EIM_RDY = 174,
+ MX50_PAD_EIM_OE = 175,
+ MX50_PAD_EIM_RW = 176,
+ MX50_PAD_EIM_LBA = 177,
+ MX50_PAD_EIM_CRE = 178,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
+ IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL),
+ IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA),
+ IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL),
+ IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA),
+ IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL),
+ IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA),
+ IMX_PINCTRL_PIN(MX50_PAD_PWM1),
+ IMX_PINCTRL_PIN(MX50_PAD_PWM2),
+ IMX_PINCTRL_PIN(MX50_PAD_0WIRE),
+ IMX_PINCTRL_PIN(MX50_PAD_EPITO),
+ IMX_PINCTRL_PIN(MX50_PAD_WDOG),
+ IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS),
+ IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC),
+ IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD),
+ IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD),
+ IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF),
+ IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC),
+ IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS),
+ IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS),
+ IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS),
+ IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS),
+ IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD),
+ IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK),
+ IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI),
+ IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO),
+ IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0),
+ IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX50_PAD_SD1_D0),
+ IMX_PINCTRL_PIN(MX50_PAD_SD1_D1),
+ IMX_PINCTRL_PIN(MX50_PAD_SD1_D2),
+ IMX_PINCTRL_PIN(MX50_PAD_SD1_D3),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D0),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D1),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D2),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D3),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D4),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D5),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D6),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D7),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_WP),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_CD),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D0),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D1),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D2),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D3),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D4),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D5),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D6),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D7),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_WR),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_RD),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_RS),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_CS),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D0),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D1),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D2),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D3),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D4),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D5),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D6),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D7),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_WP),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D8),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D9),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D10),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D11),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D12),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D13),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D14),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D15),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_OE),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_RW),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
+};
+
+static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
+ .pins = imx50_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx50_pinctrl_pads),
+};
+
+static const struct of_device_id imx50_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx50-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx50_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx50_pinctrl_info);
+}
+
+static struct platform_driver imx50_pinctrl_driver = {
+ .driver = {
+ .name = "imx50-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(imx50_pinctrl_of_match),
+ },
+ .probe = imx50_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+};
+
+static int __init imx50_pinctrl_init(void)
+{
+ return platform_driver_register(&imx50_pinctrl_driver);
+}
+arch_initcall(imx50_pinctrl_init);
+
+static void __exit imx50_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx50_pinctrl_driver);
+}
+module_exit(imx50_pinctrl_exit);
+MODULE_DESCRIPTION("Freescale IMX50 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * imx51 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx51_pads {
+ MX51_PAD_RESERVE0 = 0,
+ MX51_PAD_RESERVE1 = 1,
+ MX51_PAD_RESERVE2 = 2,
+ MX51_PAD_RESERVE3 = 3,
+ MX51_PAD_RESERVE4 = 4,
+ MX51_PAD_RESERVE5 = 5,
+ MX51_PAD_RESERVE6 = 6,
+ MX51_PAD_EIM_DA0 = 7,
+ MX51_PAD_EIM_DA1 = 8,
+ MX51_PAD_EIM_DA2 = 9,
+ MX51_PAD_EIM_DA3 = 10,
+ MX51_PAD_EIM_DA4 = 11,
+ MX51_PAD_EIM_DA5 = 12,
+ MX51_PAD_EIM_DA6 = 13,
+ MX51_PAD_EIM_DA7 = 14,
+ MX51_PAD_EIM_DA8 = 15,
+ MX51_PAD_EIM_DA9 = 16,
+ MX51_PAD_EIM_DA10 = 17,
+ MX51_PAD_EIM_DA11 = 18,
+ MX51_PAD_EIM_DA12 = 19,
+ MX51_PAD_EIM_DA13 = 20,
+ MX51_PAD_EIM_DA14 = 21,
+ MX51_PAD_EIM_DA15 = 22,
+ MX51_PAD_EIM_D16 = 23,
+ MX51_PAD_EIM_D17 = 24,
+ MX51_PAD_EIM_D18 = 25,
+ MX51_PAD_EIM_D19 = 26,
+ MX51_PAD_EIM_D20 = 27,
+ MX51_PAD_EIM_D21 = 28,
+ MX51_PAD_EIM_D22 = 29,
+ MX51_PAD_EIM_D23 = 30,
+ MX51_PAD_EIM_D24 = 31,
+ MX51_PAD_EIM_D25 = 32,
+ MX51_PAD_EIM_D26 = 33,
+ MX51_PAD_EIM_D27 = 34,
+ MX51_PAD_EIM_D28 = 35,
+ MX51_PAD_EIM_D29 = 36,
+ MX51_PAD_EIM_D30 = 37,
+ MX51_PAD_EIM_D31 = 38,
+ MX51_PAD_EIM_A16 = 39,
+ MX51_PAD_EIM_A17 = 40,
+ MX51_PAD_EIM_A18 = 41,
+ MX51_PAD_EIM_A19 = 42,
+ MX51_PAD_EIM_A20 = 43,
+ MX51_PAD_EIM_A21 = 44,
+ MX51_PAD_EIM_A22 = 45,
+ MX51_PAD_EIM_A23 = 46,
+ MX51_PAD_EIM_A24 = 47,
+ MX51_PAD_EIM_A25 = 48,
+ MX51_PAD_EIM_A26 = 49,
+ MX51_PAD_EIM_A27 = 50,
+ MX51_PAD_EIM_EB0 = 51,
+ MX51_PAD_EIM_EB1 = 52,
+ MX51_PAD_EIM_EB2 = 53,
+ MX51_PAD_EIM_EB3 = 54,
+ MX51_PAD_EIM_OE = 55,
+ MX51_PAD_EIM_CS0 = 56,
+ MX51_PAD_EIM_CS1 = 57,
+ MX51_PAD_EIM_CS2 = 58,
+ MX51_PAD_EIM_CS3 = 59,
+ MX51_PAD_EIM_CS4 = 60,
+ MX51_PAD_EIM_CS5 = 61,
+ MX51_PAD_EIM_DTACK = 62,
+ MX51_PAD_EIM_LBA = 63,
+ MX51_PAD_EIM_CRE = 64,
+ MX51_PAD_DRAM_CS1 = 65,
+ MX51_PAD_NANDF_WE_B = 66,
+ MX51_PAD_NANDF_RE_B = 67,
+ MX51_PAD_NANDF_ALE = 68,
+ MX51_PAD_NANDF_CLE = 69,
+ MX51_PAD_NANDF_WP_B = 70,
+ MX51_PAD_NANDF_RB0 = 71,
+ MX51_PAD_NANDF_RB1 = 72,
+ MX51_PAD_NANDF_RB2 = 73,
+ MX51_PAD_NANDF_RB3 = 74,
+ MX51_PAD_GPIO_NAND = 75,
+ MX51_PAD_NANDF_CS0 = 76,
+ MX51_PAD_NANDF_CS1 = 77,
+ MX51_PAD_NANDF_CS2 = 78,
+ MX51_PAD_NANDF_CS3 = 79,
+ MX51_PAD_NANDF_CS4 = 80,
+ MX51_PAD_NANDF_CS5 = 81,
+ MX51_PAD_NANDF_CS6 = 82,
+ MX51_PAD_NANDF_CS7 = 83,
+ MX51_PAD_NANDF_RDY_INT = 84,
+ MX51_PAD_NANDF_D15 = 85,
+ MX51_PAD_NANDF_D14 = 86,
+ MX51_PAD_NANDF_D13 = 87,
+ MX51_PAD_NANDF_D12 = 88,
+ MX51_PAD_NANDF_D11 = 89,
+ MX51_PAD_NANDF_D10 = 90,
+ MX51_PAD_NANDF_D9 = 91,
+ MX51_PAD_NANDF_D8 = 92,
+ MX51_PAD_NANDF_D7 = 93,
+ MX51_PAD_NANDF_D6 = 94,
+ MX51_PAD_NANDF_D5 = 95,
+ MX51_PAD_NANDF_D4 = 96,
+ MX51_PAD_NANDF_D3 = 97,
+ MX51_PAD_NANDF_D2 = 98,
+ MX51_PAD_NANDF_D1 = 99,
+ MX51_PAD_NANDF_D0 = 100,
+ MX51_PAD_CSI1_D8 = 101,
+ MX51_PAD_CSI1_D9 = 102,
+ MX51_PAD_CSI1_D10 = 103,
+ MX51_PAD_CSI1_D11 = 104,
+ MX51_PAD_CSI1_D12 = 105,
+ MX51_PAD_CSI1_D13 = 106,
+ MX51_PAD_CSI1_D14 = 107,
+ MX51_PAD_CSI1_D15 = 108,
+ MX51_PAD_CSI1_D16 = 109,
+ MX51_PAD_CSI1_D17 = 110,
+ MX51_PAD_CSI1_D18 = 111,
+ MX51_PAD_CSI1_D19 = 112,
+ MX51_PAD_CSI1_VSYNC = 113,
+ MX51_PAD_CSI1_HSYNC = 114,
+ MX51_PAD_CSI2_D12 = 115,
+ MX51_PAD_CSI2_D13 = 116,
+ MX51_PAD_CSI2_D14 = 117,
+ MX51_PAD_CSI2_D15 = 118,
+ MX51_PAD_CSI2_D16 = 119,
+ MX51_PAD_CSI2_D17 = 120,
+ MX51_PAD_CSI2_D18 = 121,
+ MX51_PAD_CSI2_D19 = 122,
+ MX51_PAD_CSI2_VSYNC = 123,
+ MX51_PAD_CSI2_HSYNC = 124,
+ MX51_PAD_CSI2_PIXCLK = 125,
+ MX51_PAD_I2C1_CLK = 126,
+ MX51_PAD_I2C1_DAT = 127,
+ MX51_PAD_AUD3_BB_TXD = 128,
+ MX51_PAD_AUD3_BB_RXD = 129,
+ MX51_PAD_AUD3_BB_CK = 130,
+ MX51_PAD_AUD3_BB_FS = 131,
+ MX51_PAD_CSPI1_MOSI = 132,
+ MX51_PAD_CSPI1_MISO = 133,
+ MX51_PAD_CSPI1_SS0 = 134,
+ MX51_PAD_CSPI1_SS1 = 135,
+ MX51_PAD_CSPI1_RDY = 136,
+ MX51_PAD_CSPI1_SCLK = 137,
+ MX51_PAD_UART1_RXD = 138,
+ MX51_PAD_UART1_TXD = 139,
+ MX51_PAD_UART1_RTS = 140,
+ MX51_PAD_UART1_CTS = 141,
+ MX51_PAD_UART2_RXD = 142,
+ MX51_PAD_UART2_TXD = 143,
+ MX51_PAD_UART3_RXD = 144,
+ MX51_PAD_UART3_TXD = 145,
+ MX51_PAD_OWIRE_LINE = 146,
+ MX51_PAD_KEY_ROW0 = 147,
+ MX51_PAD_KEY_ROW1 = 148,
+ MX51_PAD_KEY_ROW2 = 149,
+ MX51_PAD_KEY_ROW3 = 150,
+ MX51_PAD_KEY_COL0 = 151,
+ MX51_PAD_KEY_COL1 = 152,
+ MX51_PAD_KEY_COL2 = 153,
+ MX51_PAD_KEY_COL3 = 154,
+ MX51_PAD_KEY_COL4 = 155,
+ MX51_PAD_KEY_COL5 = 156,
+ MX51_PAD_RESERVE7 = 157,
+ MX51_PAD_USBH1_CLK = 158,
+ MX51_PAD_USBH1_DIR = 159,
+ MX51_PAD_USBH1_STP = 160,
+ MX51_PAD_USBH1_NXT = 161,
+ MX51_PAD_USBH1_DATA0 = 162,
+ MX51_PAD_USBH1_DATA1 = 163,
+ MX51_PAD_USBH1_DATA2 = 164,
+ MX51_PAD_USBH1_DATA3 = 165,
+ MX51_PAD_USBH1_DATA4 = 166,
+ MX51_PAD_USBH1_DATA5 = 167,
+ MX51_PAD_USBH1_DATA6 = 168,
+ MX51_PAD_USBH1_DATA7 = 169,
+ MX51_PAD_DI1_PIN11 = 170,
+ MX51_PAD_DI1_PIN12 = 171,
+ MX51_PAD_DI1_PIN13 = 172,
+ MX51_PAD_DI1_D0_CS = 173,
+ MX51_PAD_DI1_D1_CS = 174,
+ MX51_PAD_DISPB2_SER_DIN = 175,
+ MX51_PAD_DISPB2_SER_DIO = 176,
+ MX51_PAD_DISPB2_SER_CLK = 177,
+ MX51_PAD_DISPB2_SER_RS = 178,
+ MX51_PAD_DISP1_DAT0 = 179,
+ MX51_PAD_DISP1_DAT1 = 180,
+ MX51_PAD_DISP1_DAT2 = 181,
+ MX51_PAD_DISP1_DAT3 = 182,
+ MX51_PAD_DISP1_DAT4 = 183,
+ MX51_PAD_DISP1_DAT5 = 184,
+ MX51_PAD_DISP1_DAT6 = 185,
+ MX51_PAD_DISP1_DAT7 = 186,
+ MX51_PAD_DISP1_DAT8 = 187,
+ MX51_PAD_DISP1_DAT9 = 188,
+ MX51_PAD_DISP1_DAT10 = 189,
+ MX51_PAD_DISP1_DAT11 = 190,
+ MX51_PAD_DISP1_DAT12 = 191,
+ MX51_PAD_DISP1_DAT13 = 192,
+ MX51_PAD_DISP1_DAT14 = 193,
+ MX51_PAD_DISP1_DAT15 = 194,
+ MX51_PAD_DISP1_DAT16 = 195,
+ MX51_PAD_DISP1_DAT17 = 196,
+ MX51_PAD_DISP1_DAT18 = 197,
+ MX51_PAD_DISP1_DAT19 = 198,
+ MX51_PAD_DISP1_DAT20 = 199,
+ MX51_PAD_DISP1_DAT21 = 200,
+ MX51_PAD_DISP1_DAT22 = 201,
+ MX51_PAD_DISP1_DAT23 = 202,
+ MX51_PAD_DI1_PIN3 = 203,
+ MX51_PAD_DI1_PIN2 = 204,
+ MX51_PAD_RESERVE8 = 205,
+ MX51_PAD_DI_GP2 = 206,
+ MX51_PAD_DI_GP3 = 207,
+ MX51_PAD_DI2_PIN4 = 208,
+ MX51_PAD_DI2_PIN2 = 209,
+ MX51_PAD_DI2_PIN3 = 210,
+ MX51_PAD_DI2_DISP_CLK = 211,
+ MX51_PAD_DI_GP4 = 212,
+ MX51_PAD_DISP2_DAT0 = 213,
+ MX51_PAD_DISP2_DAT1 = 214,
+ MX51_PAD_DISP2_DAT2 = 215,
+ MX51_PAD_DISP2_DAT3 = 216,
+ MX51_PAD_DISP2_DAT4 = 217,
+ MX51_PAD_DISP2_DAT5 = 218,
+ MX51_PAD_DISP2_DAT6 = 219,
+ MX51_PAD_DISP2_DAT7 = 220,
+ MX51_PAD_DISP2_DAT8 = 221,
+ MX51_PAD_DISP2_DAT9 = 222,
+ MX51_PAD_DISP2_DAT10 = 223,
+ MX51_PAD_DISP2_DAT11 = 224,
+ MX51_PAD_DISP2_DAT12 = 225,
+ MX51_PAD_DISP2_DAT13 = 226,
+ MX51_PAD_DISP2_DAT14 = 227,
+ MX51_PAD_DISP2_DAT15 = 228,
+ MX51_PAD_SD1_CMD = 229,
+ MX51_PAD_SD1_CLK = 230,
+ MX51_PAD_SD1_DATA0 = 231,
+ MX51_PAD_SD1_DATA1 = 232,
+ MX51_PAD_SD1_DATA2 = 233,
+ MX51_PAD_SD1_DATA3 = 234,
+ MX51_PAD_GPIO1_0 = 235,
+ MX51_PAD_GPIO1_1 = 236,
+ MX51_PAD_SD2_CMD = 237,
+ MX51_PAD_SD2_CLK = 238,
+ MX51_PAD_SD2_DATA0 = 239,
+ MX51_PAD_SD2_DATA1 = 240,
+ MX51_PAD_SD2_DATA2 = 241,
+ MX51_PAD_SD2_DATA3 = 242,
+ MX51_PAD_GPIO1_2 = 243,
+ MX51_PAD_GPIO1_3 = 244,
+ MX51_PAD_PMIC_INT_REQ = 245,
+ MX51_PAD_GPIO1_4 = 246,
+ MX51_PAD_GPIO1_5 = 247,
+ MX51_PAD_GPIO1_6 = 248,
+ MX51_PAD_GPIO1_7 = 249,
+ MX51_PAD_GPIO1_8 = 250,
+ MX51_PAD_GPIO1_9 = 251,
+ MX51_PAD_RESERVE9 = 252,
+ MX51_PAD_RESERVE10 = 253,
+ MX51_PAD_RESERVE11 = 254,
+ MX51_PAD_RESERVE12 = 255,
+ MX51_PAD_RESERVE13 = 256,
+ MX51_PAD_RESERVE14 = 257,
+ MX51_PAD_RESERVE15 = 258,
+ MX51_PAD_RESERVE16 = 259,
+ MX51_PAD_RESERVE17 = 260,
+ MX51_PAD_RESERVE18 = 261,
+ MX51_PAD_RESERVE19 = 262,
+ MX51_PAD_RESERVE20 = 263,
+ MX51_PAD_RESERVE21 = 264,
+ MX51_PAD_RESERVE22 = 265,
+ MX51_PAD_RESERVE23 = 266,
+ MX51_PAD_RESERVE24 = 267,
+ MX51_PAD_RESERVE25 = 268,
+ MX51_PAD_RESERVE26 = 269,
+ MX51_PAD_RESERVE27 = 270,
+ MX51_PAD_RESERVE28 = 271,
+ MX51_PAD_RESERVE29 = 272,
+ MX51_PAD_RESERVE30 = 273,
+ MX51_PAD_RESERVE31 = 274,
+ MX51_PAD_RESERVE32 = 275,
+ MX51_PAD_RESERVE33 = 276,
+ MX51_PAD_RESERVE34 = 277,
+ MX51_PAD_RESERVE35 = 278,
+ MX51_PAD_RESERVE36 = 279,
+ MX51_PAD_RESERVE37 = 280,
+ MX51_PAD_RESERVE38 = 281,
+ MX51_PAD_RESERVE39 = 282,
+ MX51_PAD_RESERVE40 = 283,
+ MX51_PAD_RESERVE41 = 284,
+ MX51_PAD_RESERVE42 = 285,
+ MX51_PAD_RESERVE43 = 286,
+ MX51_PAD_RESERVE44 = 287,
+ MX51_PAD_RESERVE45 = 288,
+ MX51_PAD_RESERVE46 = 289,
+ MX51_PAD_RESERVE47 = 290,
+ MX51_PAD_RESERVE48 = 291,
+ MX51_PAD_RESERVE49 = 292,
+ MX51_PAD_RESERVE50 = 293,
+ MX51_PAD_RESERVE51 = 294,
+ MX51_PAD_RESERVE52 = 295,
+ MX51_PAD_RESERVE53 = 296,
+ MX51_PAD_RESERVE54 = 297,
+ MX51_PAD_RESERVE55 = 298,
+ MX51_PAD_RESERVE56 = 299,
+ MX51_PAD_RESERVE57 = 300,
+ MX51_PAD_RESERVE58 = 301,
+ MX51_PAD_RESERVE59 = 302,
+ MX51_PAD_RESERVE60 = 303,
+ MX51_PAD_RESERVE61 = 304,
+ MX51_PAD_RESERVE62 = 305,
+ MX51_PAD_RESERVE63 = 306,
+ MX51_PAD_RESERVE64 = 307,
+ MX51_PAD_RESERVE65 = 308,
+ MX51_PAD_RESERVE66 = 309,
+ MX51_PAD_RESERVE67 = 310,
+ MX51_PAD_RESERVE68 = 311,
+ MX51_PAD_RESERVE69 = 312,
+ MX51_PAD_RESERVE70 = 313,
+ MX51_PAD_RESERVE71 = 314,
+ MX51_PAD_RESERVE72 = 315,
+ MX51_PAD_RESERVE73 = 316,
+ MX51_PAD_RESERVE74 = 317,
+ MX51_PAD_RESERVE75 = 318,
+ MX51_PAD_RESERVE76 = 319,
+ MX51_PAD_RESERVE77 = 320,
+ MX51_PAD_RESERVE78 = 321,
+ MX51_PAD_RESERVE79 = 322,
+ MX51_PAD_RESERVE80 = 323,
+ MX51_PAD_RESERVE81 = 324,
+ MX51_PAD_RESERVE82 = 325,
+ MX51_PAD_RESERVE83 = 326,
+ MX51_PAD_RESERVE84 = 327,
+ MX51_PAD_RESERVE85 = 328,
+ MX51_PAD_RESERVE86 = 329,
+ MX51_PAD_RESERVE87 = 330,
+ MX51_PAD_RESERVE88 = 331,
+ MX51_PAD_RESERVE89 = 332,
+ MX51_PAD_RESERVE90 = 333,
+ MX51_PAD_RESERVE91 = 334,
+ MX51_PAD_RESERVE92 = 335,
+ MX51_PAD_RESERVE93 = 336,
+ MX51_PAD_RESERVE94 = 337,
+ MX51_PAD_RESERVE95 = 338,
+ MX51_PAD_RESERVE96 = 339,
+ MX51_PAD_RESERVE97 = 340,
+ MX51_PAD_RESERVE98 = 341,
+ MX51_PAD_RESERVE99 = 342,
+ MX51_PAD_RESERVE100 = 343,
+ MX51_PAD_RESERVE101 = 344,
+ MX51_PAD_RESERVE102 = 345,
+ MX51_PAD_RESERVE103 = 346,
+ MX51_PAD_RESERVE104 = 347,
+ MX51_PAD_RESERVE105 = 348,
+ MX51_PAD_RESERVE106 = 349,
+ MX51_PAD_RESERVE107 = 350,
+ MX51_PAD_RESERVE108 = 351,
+ MX51_PAD_RESERVE109 = 352,
+ MX51_PAD_RESERVE110 = 353,
+ MX51_PAD_RESERVE111 = 354,
+ MX51_PAD_RESERVE112 = 355,
+ MX51_PAD_RESERVE113 = 356,
+ MX51_PAD_RESERVE114 = 357,
+ MX51_PAD_RESERVE115 = 358,
+ MX51_PAD_RESERVE116 = 359,
+ MX51_PAD_RESERVE117 = 360,
+ MX51_PAD_RESERVE118 = 361,
+ MX51_PAD_RESERVE119 = 362,
+ MX51_PAD_RESERVE120 = 363,
+ MX51_PAD_RESERVE121 = 364,
+ MX51_PAD_CSI1_PIXCLK = 365,
+ MX51_PAD_CSI1_MCLK = 366,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE2),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE3),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE4),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE5),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE6),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D16),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D17),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D18),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D19),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D20),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D21),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D22),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D23),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D24),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D25),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D26),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D27),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D28),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D29),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D30),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_D31),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_A16),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_A17),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_A18),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_A19),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_A20),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_A21),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_A22),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_A23),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_A24),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_A25),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_A26),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_A27),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_EB0),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_EB1),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_EB2),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_EB3),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_OE),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_CS0),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_CS1),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_CS2),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_CS3),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_CS4),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_CS5),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_DTACK),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_LBA),
+ IMX_PINCTRL_PIN(MX51_PAD_EIM_CRE),
+ IMX_PINCTRL_PIN(MX51_PAD_DRAM_CS1),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_WE_B),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_RE_B),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_ALE),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_CLE),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_WP_B),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB0),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB1),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB2),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB3),
+ IMX_PINCTRL_PIN(MX51_PAD_GPIO_NAND),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS0),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS1),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS2),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS3),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS4),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS5),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS6),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS7),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_RDY_INT),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D15),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D14),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D13),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D12),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D11),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D10),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D9),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D8),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D7),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D6),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D5),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D4),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D3),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D2),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D1),
+ IMX_PINCTRL_PIN(MX51_PAD_NANDF_D0),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_D8),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_D9),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_D10),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_D11),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_D12),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_D13),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_D14),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_D15),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_D16),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_D17),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_D18),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI2_D15),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI2_D16),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI2_D17),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI2_D18),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI2_D19),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI2_VSYNC),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI2_HSYNC),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI2_PIXCLK),
+ IMX_PINCTRL_PIN(MX51_PAD_I2C1_CLK),
+ IMX_PINCTRL_PIN(MX51_PAD_I2C1_DAT),
+ IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_TXD),
+ IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_RXD),
+ IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_CK),
+ IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_FS),
+ IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MOSI),
+ IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MISO),
+ IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS0),
+ IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS1),
+ IMX_PINCTRL_PIN(MX51_PAD_CSPI1_RDY),
+ IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SCLK),
+ IMX_PINCTRL_PIN(MX51_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX51_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX51_PAD_UART1_RTS),
+ IMX_PINCTRL_PIN(MX51_PAD_UART1_CTS),
+ IMX_PINCTRL_PIN(MX51_PAD_UART2_RXD),
+ IMX_PINCTRL_PIN(MX51_PAD_UART2_TXD),
+ IMX_PINCTRL_PIN(MX51_PAD_UART3_RXD),
+ IMX_PINCTRL_PIN(MX51_PAD_UART3_TXD),
+ IMX_PINCTRL_PIN(MX51_PAD_OWIRE_LINE),
+ IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW0),
+ IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW1),
+ IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW2),
+ IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW3),
+ IMX_PINCTRL_PIN(MX51_PAD_KEY_COL0),
+ IMX_PINCTRL_PIN(MX51_PAD_KEY_COL1),
+ IMX_PINCTRL_PIN(MX51_PAD_KEY_COL2),
+ IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3),
+ IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4),
+ IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE7),
+ IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK),
+ IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR),
+ IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP),
+ IMX_PINCTRL_PIN(MX51_PAD_USBH1_NXT),
+ IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA0),
+ IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA1),
+ IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA2),
+ IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA3),
+ IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA4),
+ IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA5),
+ IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA6),
+ IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA7),
+ IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN11),
+ IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN12),
+ IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN13),
+ IMX_PINCTRL_PIN(MX51_PAD_DI1_D0_CS),
+ IMX_PINCTRL_PIN(MX51_PAD_DI1_D1_CS),
+ IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIN),
+ IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIO),
+ IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_CLK),
+ IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_RS),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT0),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT1),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT2),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT3),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT4),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT5),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT6),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT7),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT8),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT9),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT10),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT11),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT12),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT13),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT14),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT15),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT16),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT17),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT18),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT19),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT20),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT21),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT22),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23),
+ IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3),
+ IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE8),
+ IMX_PINCTRL_PIN(MX51_PAD_DI_GP2),
+ IMX_PINCTRL_PIN(MX51_PAD_DI_GP3),
+ IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4),
+ IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN2),
+ IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN3),
+ IMX_PINCTRL_PIN(MX51_PAD_DI2_DISP_CLK),
+ IMX_PINCTRL_PIN(MX51_PAD_DI_GP4),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT0),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT1),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT2),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT3),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT4),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT5),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT6),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT7),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT8),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT9),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT10),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT11),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT12),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT13),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT14),
+ IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT15),
+ IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0),
+ IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1),
+ IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2),
+ IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3),
+ IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0),
+ IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1),
+ IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0),
+ IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA1),
+ IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA2),
+ IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA3),
+ IMX_PINCTRL_PIN(MX51_PAD_GPIO1_2),
+ IMX_PINCTRL_PIN(MX51_PAD_GPIO1_3),
+ IMX_PINCTRL_PIN(MX51_PAD_PMIC_INT_REQ),
+ IMX_PINCTRL_PIN(MX51_PAD_GPIO1_4),
+ IMX_PINCTRL_PIN(MX51_PAD_GPIO1_5),
+ IMX_PINCTRL_PIN(MX51_PAD_GPIO1_6),
+ IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7),
+ IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8),
+ IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE9),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE10),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE11),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE12),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE13),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE14),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE15),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE16),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE17),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE18),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE19),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE20),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE21),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE22),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE23),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE24),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE25),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE26),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE27),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE28),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE29),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE30),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE31),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE32),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE33),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE34),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE35),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE36),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE37),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE38),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE39),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE40),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE41),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE42),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE43),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE44),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE45),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE46),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE47),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE48),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE49),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE50),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE51),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE52),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE53),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE54),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE55),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE56),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE57),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE58),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE59),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE60),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE61),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE62),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE63),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE64),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE65),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE66),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE67),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE68),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE69),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE70),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE71),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE72),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE73),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE74),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE75),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE76),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE77),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE78),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE79),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE80),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE81),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE82),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE83),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE84),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE85),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE86),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE87),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE88),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE89),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE90),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE91),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE92),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE93),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE94),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE95),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE96),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE97),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE98),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE99),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE100),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE101),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE102),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE103),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE104),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE105),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE106),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE107),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE108),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE109),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE110),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE111),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE112),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE113),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE114),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE115),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE116),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE117),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE118),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE119),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE120),
+ IMX_PINCTRL_PIN(MX51_PAD_RESERVE121),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK),
+ IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK),
+};
+
+static struct imx_pinctrl_soc_info imx51_pinctrl_info = {
+ .pins = imx51_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx51_pinctrl_pads),
+};
+
+static const struct of_device_id imx51_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx51-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx51_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx51_pinctrl_info);
+}
+
+static struct platform_driver imx51_pinctrl_driver = {
+ .driver = {
+ .name = "imx51-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = imx51_pinctrl_of_match,
+ },
+ .probe = imx51_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+};
+
+static int __init imx51_pinctrl_init(void)
+{
+ return platform_driver_register(&imx51_pinctrl_driver);
+}
+arch_initcall(imx51_pinctrl_init);
+
+static void __exit imx51_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx51_pinctrl_driver);
+}
+module_exit(imx51_pinctrl_exit);
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
+MODULE_DESCRIPTION("Freescale IMX51 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * imx53 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx53_pads {
+ MX53_PAD_RESERVE0 = 0,
+ MX53_PAD_RESERVE1 = 1,
+ MX53_PAD_RESERVE2 = 2,
+ MX53_PAD_RESERVE3 = 3,
+ MX53_PAD_RESERVE4 = 4,
+ MX53_PAD_RESERVE5 = 5,
+ MX53_PAD_RESERVE6 = 6,
+ MX53_PAD_RESERVE7 = 7,
+ MX53_PAD_GPIO_19 = 8,
+ MX53_PAD_KEY_COL0 = 9,
+ MX53_PAD_KEY_ROW0 = 10,
+ MX53_PAD_KEY_COL1 = 11,
+ MX53_PAD_KEY_ROW1 = 12,
+ MX53_PAD_KEY_COL2 = 13,
+ MX53_PAD_KEY_ROW2 = 14,
+ MX53_PAD_KEY_COL3 = 15,
+ MX53_PAD_KEY_ROW3 = 16,
+ MX53_PAD_KEY_COL4 = 17,
+ MX53_PAD_KEY_ROW4 = 18,
+ MX53_PAD_DI0_DISP_CLK = 19,
+ MX53_PAD_DI0_PIN15 = 20,
+ MX53_PAD_DI0_PIN2 = 21,
+ MX53_PAD_DI0_PIN3 = 22,
+ MX53_PAD_DI0_PIN4 = 23,
+ MX53_PAD_DISP0_DAT0 = 24,
+ MX53_PAD_DISP0_DAT1 = 25,
+ MX53_PAD_DISP0_DAT2 = 26,
+ MX53_PAD_DISP0_DAT3 = 27,
+ MX53_PAD_DISP0_DAT4 = 28,
+ MX53_PAD_DISP0_DAT5 = 29,
+ MX53_PAD_DISP0_DAT6 = 30,
+ MX53_PAD_DISP0_DAT7 = 31,
+ MX53_PAD_DISP0_DAT8 = 32,
+ MX53_PAD_DISP0_DAT9 = 33,
+ MX53_PAD_DISP0_DAT10 = 34,
+ MX53_PAD_DISP0_DAT11 = 35,
+ MX53_PAD_DISP0_DAT12 = 36,
+ MX53_PAD_DISP0_DAT13 = 37,
+ MX53_PAD_DISP0_DAT14 = 38,
+ MX53_PAD_DISP0_DAT15 = 39,
+ MX53_PAD_DISP0_DAT16 = 40,
+ MX53_PAD_DISP0_DAT17 = 41,
+ MX53_PAD_DISP0_DAT18 = 42,
+ MX53_PAD_DISP0_DAT19 = 43,
+ MX53_PAD_DISP0_DAT20 = 44,
+ MX53_PAD_DISP0_DAT21 = 45,
+ MX53_PAD_DISP0_DAT22 = 46,
+ MX53_PAD_DISP0_DAT23 = 47,
+ MX53_PAD_CSI0_PIXCLK = 48,
+ MX53_PAD_CSI0_MCLK = 49,
+ MX53_PAD_CSI0_DATA_EN = 50,
+ MX53_PAD_CSI0_VSYNC = 51,
+ MX53_PAD_CSI0_DAT4 = 52,
+ MX53_PAD_CSI0_DAT5 = 53,
+ MX53_PAD_CSI0_DAT6 = 54,
+ MX53_PAD_CSI0_DAT7 = 55,
+ MX53_PAD_CSI0_DAT8 = 56,
+ MX53_PAD_CSI0_DAT9 = 57,
+ MX53_PAD_CSI0_DAT10 = 58,
+ MX53_PAD_CSI0_DAT11 = 59,
+ MX53_PAD_CSI0_DAT12 = 60,
+ MX53_PAD_CSI0_DAT13 = 61,
+ MX53_PAD_CSI0_DAT14 = 62,
+ MX53_PAD_CSI0_DAT15 = 63,
+ MX53_PAD_CSI0_DAT16 = 64,
+ MX53_PAD_CSI0_DAT17 = 65,
+ MX53_PAD_CSI0_DAT18 = 66,
+ MX53_PAD_CSI0_DAT19 = 67,
+ MX53_PAD_EIM_A25 = 68,
+ MX53_PAD_EIM_EB2 = 69,
+ MX53_PAD_EIM_D16 = 70,
+ MX53_PAD_EIM_D17 = 71,
+ MX53_PAD_EIM_D18 = 72,
+ MX53_PAD_EIM_D19 = 73,
+ MX53_PAD_EIM_D20 = 74,
+ MX53_PAD_EIM_D21 = 75,
+ MX53_PAD_EIM_D22 = 76,
+ MX53_PAD_EIM_D23 = 77,
+ MX53_PAD_EIM_EB3 = 78,
+ MX53_PAD_EIM_D24 = 79,
+ MX53_PAD_EIM_D25 = 80,
+ MX53_PAD_EIM_D26 = 81,
+ MX53_PAD_EIM_D27 = 82,
+ MX53_PAD_EIM_D28 = 83,
+ MX53_PAD_EIM_D29 = 84,
+ MX53_PAD_EIM_D30 = 85,
+ MX53_PAD_EIM_D31 = 86,
+ MX53_PAD_EIM_A24 = 87,
+ MX53_PAD_EIM_A23 = 88,
+ MX53_PAD_EIM_A22 = 89,
+ MX53_PAD_EIM_A21 = 90,
+ MX53_PAD_EIM_A20 = 91,
+ MX53_PAD_EIM_A19 = 92,
+ MX53_PAD_EIM_A18 = 93,
+ MX53_PAD_EIM_A17 = 94,
+ MX53_PAD_EIM_A16 = 95,
+ MX53_PAD_EIM_CS0 = 96,
+ MX53_PAD_EIM_CS1 = 97,
+ MX53_PAD_EIM_OE = 98,
+ MX53_PAD_EIM_RW = 99,
+ MX53_PAD_EIM_LBA = 100,
+ MX53_PAD_EIM_EB0 = 101,
+ MX53_PAD_EIM_EB1 = 102,
+ MX53_PAD_EIM_DA0 = 103,
+ MX53_PAD_EIM_DA1 = 104,
+ MX53_PAD_EIM_DA2 = 105,
+ MX53_PAD_EIM_DA3 = 106,
+ MX53_PAD_EIM_DA4 = 107,
+ MX53_PAD_EIM_DA5 = 108,
+ MX53_PAD_EIM_DA6 = 109,
+ MX53_PAD_EIM_DA7 = 110,
+ MX53_PAD_EIM_DA8 = 111,
+ MX53_PAD_EIM_DA9 = 112,
+ MX53_PAD_EIM_DA10 = 113,
+ MX53_PAD_EIM_DA11 = 114,
+ MX53_PAD_EIM_DA12 = 115,
+ MX53_PAD_EIM_DA13 = 116,
+ MX53_PAD_EIM_DA14 = 117,
+ MX53_PAD_EIM_DA15 = 118,
+ MX53_PAD_NANDF_WE_B = 119,
+ MX53_PAD_NANDF_RE_B = 120,
+ MX53_PAD_EIM_WAIT = 121,
+ MX53_PAD_RESERVE8 = 122,
+ MX53_PAD_LVDS1_TX3_P = 123,
+ MX53_PAD_LVDS1_TX2_P = 124,
+ MX53_PAD_LVDS1_CLK_P = 125,
+ MX53_PAD_LVDS1_TX1_P = 126,
+ MX53_PAD_LVDS1_TX0_P = 127,
+ MX53_PAD_LVDS0_TX3_P = 128,
+ MX53_PAD_LVDS0_CLK_P = 129,
+ MX53_PAD_LVDS0_TX2_P = 130,
+ MX53_PAD_LVDS0_TX1_P = 131,
+ MX53_PAD_LVDS0_TX0_P = 132,
+ MX53_PAD_GPIO_10 = 133,
+ MX53_PAD_GPIO_11 = 134,
+ MX53_PAD_GPIO_12 = 135,
+ MX53_PAD_GPIO_13 = 136,
+ MX53_PAD_GPIO_14 = 137,
+ MX53_PAD_NANDF_CLE = 138,
+ MX53_PAD_NANDF_ALE = 139,
+ MX53_PAD_NANDF_WP_B = 140,
+ MX53_PAD_NANDF_RB0 = 141,
+ MX53_PAD_NANDF_CS0 = 142,
+ MX53_PAD_NANDF_CS1 = 143,
+ MX53_PAD_NANDF_CS2 = 144,
+ MX53_PAD_NANDF_CS3 = 145,
+ MX53_PAD_FEC_MDIO = 146,
+ MX53_PAD_FEC_REF_CLK = 147,
+ MX53_PAD_FEC_RX_ER = 148,
+ MX53_PAD_FEC_CRS_DV = 149,
+ MX53_PAD_FEC_RXD1 = 150,
+ MX53_PAD_FEC_RXD0 = 151,
+ MX53_PAD_FEC_TX_EN = 152,
+ MX53_PAD_FEC_TXD1 = 153,
+ MX53_PAD_FEC_TXD0 = 154,
+ MX53_PAD_FEC_MDC = 155,
+ MX53_PAD_PATA_DIOW = 156,
+ MX53_PAD_PATA_DMACK = 157,
+ MX53_PAD_PATA_DMARQ = 158,
+ MX53_PAD_PATA_BUFFER_EN = 159,
+ MX53_PAD_PATA_INTRQ = 160,
+ MX53_PAD_PATA_DIOR = 161,
+ MX53_PAD_PATA_RESET_B = 162,
+ MX53_PAD_PATA_IORDY = 163,
+ MX53_PAD_PATA_DA_0 = 164,
+ MX53_PAD_PATA_DA_1 = 165,
+ MX53_PAD_PATA_DA_2 = 166,
+ MX53_PAD_PATA_CS_0 = 167,
+ MX53_PAD_PATA_CS_1 = 168,
+ MX53_PAD_PATA_DATA0 = 169,
+ MX53_PAD_PATA_DATA1 = 170,
+ MX53_PAD_PATA_DATA2 = 171,
+ MX53_PAD_PATA_DATA3 = 172,
+ MX53_PAD_PATA_DATA4 = 173,
+ MX53_PAD_PATA_DATA5 = 174,
+ MX53_PAD_PATA_DATA6 = 175,
+ MX53_PAD_PATA_DATA7 = 176,
+ MX53_PAD_PATA_DATA8 = 177,
+ MX53_PAD_PATA_DATA9 = 178,
+ MX53_PAD_PATA_DATA10 = 179,
+ MX53_PAD_PATA_DATA11 = 180,
+ MX53_PAD_PATA_DATA12 = 181,
+ MX53_PAD_PATA_DATA13 = 182,
+ MX53_PAD_PATA_DATA14 = 183,
+ MX53_PAD_PATA_DATA15 = 184,
+ MX53_PAD_SD1_DATA0 = 185,
+ MX53_PAD_SD1_DATA1 = 186,
+ MX53_PAD_SD1_CMD = 187,
+ MX53_PAD_SD1_DATA2 = 188,
+ MX53_PAD_SD1_CLK = 189,
+ MX53_PAD_SD1_DATA3 = 190,
+ MX53_PAD_SD2_CLK = 191,
+ MX53_PAD_SD2_CMD = 192,
+ MX53_PAD_SD2_DATA3 = 193,
+ MX53_PAD_SD2_DATA2 = 194,
+ MX53_PAD_SD2_DATA1 = 195,
+ MX53_PAD_SD2_DATA0 = 196,
+ MX53_PAD_GPIO_0 = 197,
+ MX53_PAD_GPIO_1 = 198,
+ MX53_PAD_GPIO_9 = 199,
+ MX53_PAD_GPIO_3 = 200,
+ MX53_PAD_GPIO_6 = 201,
+ MX53_PAD_GPIO_2 = 202,
+ MX53_PAD_GPIO_4 = 203,
+ MX53_PAD_GPIO_5 = 204,
+ MX53_PAD_GPIO_7 = 205,
+ MX53_PAD_GPIO_8 = 206,
+ MX53_PAD_GPIO_16 = 207,
+ MX53_PAD_GPIO_17 = 208,
+ MX53_PAD_GPIO_18 = 209,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX53_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(MX53_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(MX53_PAD_RESERVE2),
+ IMX_PINCTRL_PIN(MX53_PAD_RESERVE3),
+ IMX_PINCTRL_PIN(MX53_PAD_RESERVE4),
+ IMX_PINCTRL_PIN(MX53_PAD_RESERVE5),
+ IMX_PINCTRL_PIN(MX53_PAD_RESERVE6),
+ IMX_PINCTRL_PIN(MX53_PAD_RESERVE7),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_19),
+ IMX_PINCTRL_PIN(MX53_PAD_KEY_COL0),
+ IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW0),
+ IMX_PINCTRL_PIN(MX53_PAD_KEY_COL1),
+ IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW1),
+ IMX_PINCTRL_PIN(MX53_PAD_KEY_COL2),
+ IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW2),
+ IMX_PINCTRL_PIN(MX53_PAD_KEY_COL3),
+ IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW3),
+ IMX_PINCTRL_PIN(MX53_PAD_KEY_COL4),
+ IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW4),
+ IMX_PINCTRL_PIN(MX53_PAD_DI0_DISP_CLK),
+ IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN15),
+ IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN2),
+ IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN3),
+ IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN4),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT0),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT1),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT2),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT3),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT4),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT5),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT6),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT7),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT8),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT9),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT10),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT11),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT12),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT13),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT14),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT15),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT16),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT17),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT18),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT19),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT20),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT21),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT22),
+ IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT23),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_PIXCLK),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_MCLK),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DATA_EN),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_VSYNC),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT4),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT5),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT6),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT7),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT8),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT9),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT10),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT11),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT12),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT13),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT14),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT15),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT16),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT17),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT18),
+ IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT19),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_A25),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_EB2),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D16),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D17),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D18),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D19),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D20),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D21),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D22),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D23),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_EB3),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D24),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D25),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D26),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D27),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D28),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D29),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D30),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_D31),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_A24),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_A23),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_A22),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_A21),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_A20),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_A19),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_A18),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_A17),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_A16),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_CS0),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_CS1),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_OE),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_RW),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_LBA),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_EB0),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_EB1),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA0),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA1),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA2),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA3),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA4),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA5),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA6),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA7),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA8),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA9),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA10),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA11),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA12),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA13),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA14),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_DA15),
+ IMX_PINCTRL_PIN(MX53_PAD_NANDF_WE_B),
+ IMX_PINCTRL_PIN(MX53_PAD_NANDF_RE_B),
+ IMX_PINCTRL_PIN(MX53_PAD_EIM_WAIT),
+ IMX_PINCTRL_PIN(MX53_PAD_RESERVE8),
+ IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX3_P),
+ IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX2_P),
+ IMX_PINCTRL_PIN(MX53_PAD_LVDS1_CLK_P),
+ IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX1_P),
+ IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX0_P),
+ IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX3_P),
+ IMX_PINCTRL_PIN(MX53_PAD_LVDS0_CLK_P),
+ IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX2_P),
+ IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX1_P),
+ IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX0_P),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_10),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_11),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_12),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_13),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_14),
+ IMX_PINCTRL_PIN(MX53_PAD_NANDF_CLE),
+ IMX_PINCTRL_PIN(MX53_PAD_NANDF_ALE),
+ IMX_PINCTRL_PIN(MX53_PAD_NANDF_WP_B),
+ IMX_PINCTRL_PIN(MX53_PAD_NANDF_RB0),
+ IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS0),
+ IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS1),
+ IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS2),
+ IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS3),
+ IMX_PINCTRL_PIN(MX53_PAD_FEC_MDIO),
+ IMX_PINCTRL_PIN(MX53_PAD_FEC_REF_CLK),
+ IMX_PINCTRL_PIN(MX53_PAD_FEC_RX_ER),
+ IMX_PINCTRL_PIN(MX53_PAD_FEC_CRS_DV),
+ IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD1),
+ IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD0),
+ IMX_PINCTRL_PIN(MX53_PAD_FEC_TX_EN),
+ IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD1),
+ IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD0),
+ IMX_PINCTRL_PIN(MX53_PAD_FEC_MDC),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOW),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DMACK),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DMARQ),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_BUFFER_EN),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_INTRQ),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOR),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_RESET_B),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_IORDY),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_0),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_1),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_2),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_0),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_1),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA0),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA1),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA2),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA3),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA4),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA5),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA6),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA7),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA8),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA9),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA10),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA11),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA12),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA13),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA14),
+ IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA15),
+ IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA0),
+ IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA1),
+ IMX_PINCTRL_PIN(MX53_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA2),
+ IMX_PINCTRL_PIN(MX53_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA3),
+ IMX_PINCTRL_PIN(MX53_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX53_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA3),
+ IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA2),
+ IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA1),
+ IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA0),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_0),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_1),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_9),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_3),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_6),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_2),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_4),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_5),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_7),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_8),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_16),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_17),
+ IMX_PINCTRL_PIN(MX53_PAD_GPIO_18),
+};
+
+static struct imx_pinctrl_soc_info imx53_pinctrl_info = {
+ .pins = imx53_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx53_pinctrl_pads),
+};
+
+static const struct of_device_id imx53_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx53-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx53_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx53_pinctrl_info);
+}
+
+static struct platform_driver imx53_pinctrl_driver = {
+ .driver = {
+ .name = "imx53-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = imx53_pinctrl_of_match,
+ },
+ .probe = imx53_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+};
+
+static int __init imx53_pinctrl_init(void)
+{
+ return platform_driver_register(&imx53_pinctrl_driver);
+}
+arch_initcall(imx53_pinctrl_init);
+
+static void __exit imx53_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx53_pinctrl_driver);
+}
+module_exit(imx53_pinctrl_exit);
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
+MODULE_DESCRIPTION("Freescale IMX53 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx6dl_pads {
+ MX6DL_PAD_RESERVE0 = 0,
+ MX6DL_PAD_RESERVE1 = 1,
+ MX6DL_PAD_RESERVE2 = 2,
+ MX6DL_PAD_RESERVE3 = 3,
+ MX6DL_PAD_RESERVE4 = 4,
+ MX6DL_PAD_RESERVE5 = 5,
+ MX6DL_PAD_RESERVE6 = 6,
+ MX6DL_PAD_RESERVE7 = 7,
+ MX6DL_PAD_RESERVE8 = 8,
+ MX6DL_PAD_RESERVE9 = 9,
+ MX6DL_PAD_RESERVE10 = 10,
+ MX6DL_PAD_RESERVE11 = 11,
+ MX6DL_PAD_RESERVE12 = 12,
+ MX6DL_PAD_RESERVE13 = 13,
+ MX6DL_PAD_RESERVE14 = 14,
+ MX6DL_PAD_RESERVE15 = 15,
+ MX6DL_PAD_RESERVE16 = 16,
+ MX6DL_PAD_RESERVE17 = 17,
+ MX6DL_PAD_RESERVE18 = 18,
+ MX6DL_PAD_CSI0_DAT10 = 19,
+ MX6DL_PAD_CSI0_DAT11 = 20,
+ MX6DL_PAD_CSI0_DAT12 = 21,
+ MX6DL_PAD_CSI0_DAT13 = 22,
+ MX6DL_PAD_CSI0_DAT14 = 23,
+ MX6DL_PAD_CSI0_DAT15 = 24,
+ MX6DL_PAD_CSI0_DAT16 = 25,
+ MX6DL_PAD_CSI0_DAT17 = 26,
+ MX6DL_PAD_CSI0_DAT18 = 27,
+ MX6DL_PAD_CSI0_DAT19 = 28,
+ MX6DL_PAD_CSI0_DAT4 = 29,
+ MX6DL_PAD_CSI0_DAT5 = 30,
+ MX6DL_PAD_CSI0_DAT6 = 31,
+ MX6DL_PAD_CSI0_DAT7 = 32,
+ MX6DL_PAD_CSI0_DAT8 = 33,
+ MX6DL_PAD_CSI0_DAT9 = 34,
+ MX6DL_PAD_CSI0_DATA_EN = 35,
+ MX6DL_PAD_CSI0_MCLK = 36,
+ MX6DL_PAD_CSI0_PIXCLK = 37,
+ MX6DL_PAD_CSI0_VSYNC = 38,
+ MX6DL_PAD_DI0_DISP_CLK = 39,
+ MX6DL_PAD_DI0_PIN15 = 40,
+ MX6DL_PAD_DI0_PIN2 = 41,
+ MX6DL_PAD_DI0_PIN3 = 42,
+ MX6DL_PAD_DI0_PIN4 = 43,
+ MX6DL_PAD_DISP0_DAT0 = 44,
+ MX6DL_PAD_DISP0_DAT1 = 45,
+ MX6DL_PAD_DISP0_DAT10 = 46,
+ MX6DL_PAD_DISP0_DAT11 = 47,
+ MX6DL_PAD_DISP0_DAT12 = 48,
+ MX6DL_PAD_DISP0_DAT13 = 49,
+ MX6DL_PAD_DISP0_DAT14 = 50,
+ MX6DL_PAD_DISP0_DAT15 = 51,
+ MX6DL_PAD_DISP0_DAT16 = 52,
+ MX6DL_PAD_DISP0_DAT17 = 53,
+ MX6DL_PAD_DISP0_DAT18 = 54,
+ MX6DL_PAD_DISP0_DAT19 = 55,
+ MX6DL_PAD_DISP0_DAT2 = 56,
+ MX6DL_PAD_DISP0_DAT20 = 57,
+ MX6DL_PAD_DISP0_DAT21 = 58,
+ MX6DL_PAD_DISP0_DAT22 = 59,
+ MX6DL_PAD_DISP0_DAT23 = 60,
+ MX6DL_PAD_DISP0_DAT3 = 61,
+ MX6DL_PAD_DISP0_DAT4 = 62,
+ MX6DL_PAD_DISP0_DAT5 = 63,
+ MX6DL_PAD_DISP0_DAT6 = 64,
+ MX6DL_PAD_DISP0_DAT7 = 65,
+ MX6DL_PAD_DISP0_DAT8 = 66,
+ MX6DL_PAD_DISP0_DAT9 = 67,
+ MX6DL_PAD_EIM_A16 = 68,
+ MX6DL_PAD_EIM_A17 = 69,
+ MX6DL_PAD_EIM_A18 = 70,
+ MX6DL_PAD_EIM_A19 = 71,
+ MX6DL_PAD_EIM_A20 = 72,
+ MX6DL_PAD_EIM_A21 = 73,
+ MX6DL_PAD_EIM_A22 = 74,
+ MX6DL_PAD_EIM_A23 = 75,
+ MX6DL_PAD_EIM_A24 = 76,
+ MX6DL_PAD_EIM_A25 = 77,
+ MX6DL_PAD_EIM_BCLK = 78,
+ MX6DL_PAD_EIM_CS0 = 79,
+ MX6DL_PAD_EIM_CS1 = 80,
+ MX6DL_PAD_EIM_D16 = 81,
+ MX6DL_PAD_EIM_D17 = 82,
+ MX6DL_PAD_EIM_D18 = 83,
+ MX6DL_PAD_EIM_D19 = 84,
+ MX6DL_PAD_EIM_D20 = 85,
+ MX6DL_PAD_EIM_D21 = 86,
+ MX6DL_PAD_EIM_D22 = 87,
+ MX6DL_PAD_EIM_D23 = 88,
+ MX6DL_PAD_EIM_D24 = 89,
+ MX6DL_PAD_EIM_D25 = 90,
+ MX6DL_PAD_EIM_D26 = 91,
+ MX6DL_PAD_EIM_D27 = 92,
+ MX6DL_PAD_EIM_D28 = 93,
+ MX6DL_PAD_EIM_D29 = 94,
+ MX6DL_PAD_EIM_D30 = 95,
+ MX6DL_PAD_EIM_D31 = 96,
+ MX6DL_PAD_EIM_DA0 = 97,
+ MX6DL_PAD_EIM_DA1 = 98,
+ MX6DL_PAD_EIM_DA10 = 99,
+ MX6DL_PAD_EIM_DA11 = 100,
+ MX6DL_PAD_EIM_DA12 = 101,
+ MX6DL_PAD_EIM_DA13 = 102,
+ MX6DL_PAD_EIM_DA14 = 103,
+ MX6DL_PAD_EIM_DA15 = 104,
+ MX6DL_PAD_EIM_DA2 = 105,
+ MX6DL_PAD_EIM_DA3 = 106,
+ MX6DL_PAD_EIM_DA4 = 107,
+ MX6DL_PAD_EIM_DA5 = 108,
+ MX6DL_PAD_EIM_DA6 = 109,
+ MX6DL_PAD_EIM_DA7 = 110,
+ MX6DL_PAD_EIM_DA8 = 111,
+ MX6DL_PAD_EIM_DA9 = 112,
+ MX6DL_PAD_EIM_EB0 = 113,
+ MX6DL_PAD_EIM_EB1 = 114,
+ MX6DL_PAD_EIM_EB2 = 115,
+ MX6DL_PAD_EIM_EB3 = 116,
+ MX6DL_PAD_EIM_LBA = 117,
+ MX6DL_PAD_EIM_OE = 118,
+ MX6DL_PAD_EIM_RW = 119,
+ MX6DL_PAD_EIM_WAIT = 120,
+ MX6DL_PAD_ENET_CRS_DV = 121,
+ MX6DL_PAD_ENET_MDC = 122,
+ MX6DL_PAD_ENET_MDIO = 123,
+ MX6DL_PAD_ENET_REF_CLK = 124,
+ MX6DL_PAD_ENET_RX_ER = 125,
+ MX6DL_PAD_ENET_RXD0 = 126,
+ MX6DL_PAD_ENET_RXD1 = 127,
+ MX6DL_PAD_ENET_TX_EN = 128,
+ MX6DL_PAD_ENET_TXD0 = 129,
+ MX6DL_PAD_ENET_TXD1 = 130,
+ MX6DL_PAD_GPIO_0 = 131,
+ MX6DL_PAD_GPIO_1 = 132,
+ MX6DL_PAD_GPIO_16 = 133,
+ MX6DL_PAD_GPIO_17 = 134,
+ MX6DL_PAD_GPIO_18 = 135,
+ MX6DL_PAD_GPIO_19 = 136,
+ MX6DL_PAD_GPIO_2 = 137,
+ MX6DL_PAD_GPIO_3 = 138,
+ MX6DL_PAD_GPIO_4 = 139,
+ MX6DL_PAD_GPIO_5 = 140,
+ MX6DL_PAD_GPIO_6 = 141,
+ MX6DL_PAD_GPIO_7 = 142,
+ MX6DL_PAD_GPIO_8 = 143,
+ MX6DL_PAD_GPIO_9 = 144,
+ MX6DL_PAD_KEY_COL0 = 145,
+ MX6DL_PAD_KEY_COL1 = 146,
+ MX6DL_PAD_KEY_COL2 = 147,
+ MX6DL_PAD_KEY_COL3 = 148,
+ MX6DL_PAD_KEY_COL4 = 149,
+ MX6DL_PAD_KEY_ROW0 = 150,
+ MX6DL_PAD_KEY_ROW1 = 151,
+ MX6DL_PAD_KEY_ROW2 = 152,
+ MX6DL_PAD_KEY_ROW3 = 153,
+ MX6DL_PAD_KEY_ROW4 = 154,
+ MX6DL_PAD_NANDF_ALE = 155,
+ MX6DL_PAD_NANDF_CLE = 156,
+ MX6DL_PAD_NANDF_CS0 = 157,
+ MX6DL_PAD_NANDF_CS1 = 158,
+ MX6DL_PAD_NANDF_CS2 = 159,
+ MX6DL_PAD_NANDF_CS3 = 160,
+ MX6DL_PAD_NANDF_D0 = 161,
+ MX6DL_PAD_NANDF_D1 = 162,
+ MX6DL_PAD_NANDF_D2 = 163,
+ MX6DL_PAD_NANDF_D3 = 164,
+ MX6DL_PAD_NANDF_D4 = 165,
+ MX6DL_PAD_NANDF_D5 = 166,
+ MX6DL_PAD_NANDF_D6 = 167,
+ MX6DL_PAD_NANDF_D7 = 168,
+ MX6DL_PAD_NANDF_RB0 = 169,
+ MX6DL_PAD_NANDF_WP_B = 170,
+ MX6DL_PAD_RGMII_RD0 = 171,
+ MX6DL_PAD_RGMII_RD1 = 172,
+ MX6DL_PAD_RGMII_RD2 = 173,
+ MX6DL_PAD_RGMII_RD3 = 174,
+ MX6DL_PAD_RGMII_RX_CTL = 175,
+ MX6DL_PAD_RGMII_RXC = 176,
+ MX6DL_PAD_RGMII_TD0 = 177,
+ MX6DL_PAD_RGMII_TD1 = 178,
+ MX6DL_PAD_RGMII_TD2 = 179,
+ MX6DL_PAD_RGMII_TD3 = 180,
+ MX6DL_PAD_RGMII_TX_CTL = 181,
+ MX6DL_PAD_RGMII_TXC = 182,
+ MX6DL_PAD_SD1_CLK = 183,
+ MX6DL_PAD_SD1_CMD = 184,
+ MX6DL_PAD_SD1_DAT0 = 185,
+ MX6DL_PAD_SD1_DAT1 = 186,
+ MX6DL_PAD_SD1_DAT2 = 187,
+ MX6DL_PAD_SD1_DAT3 = 188,
+ MX6DL_PAD_SD2_CLK = 189,
+ MX6DL_PAD_SD2_CMD = 190,
+ MX6DL_PAD_SD2_DAT0 = 191,
+ MX6DL_PAD_SD2_DAT1 = 192,
+ MX6DL_PAD_SD2_DAT2 = 193,
+ MX6DL_PAD_SD2_DAT3 = 194,
+ MX6DL_PAD_SD3_CLK = 195,
+ MX6DL_PAD_SD3_CMD = 196,
+ MX6DL_PAD_SD3_DAT0 = 197,
+ MX6DL_PAD_SD3_DAT1 = 198,
+ MX6DL_PAD_SD3_DAT2 = 199,
+ MX6DL_PAD_SD3_DAT3 = 200,
+ MX6DL_PAD_SD3_DAT4 = 201,
+ MX6DL_PAD_SD3_DAT5 = 202,
+ MX6DL_PAD_SD3_DAT6 = 203,
+ MX6DL_PAD_SD3_DAT7 = 204,
+ MX6DL_PAD_SD3_RST = 205,
+ MX6DL_PAD_SD4_CLK = 206,
+ MX6DL_PAD_SD4_CMD = 207,
+ MX6DL_PAD_SD4_DAT0 = 208,
+ MX6DL_PAD_SD4_DAT1 = 209,
+ MX6DL_PAD_SD4_DAT2 = 210,
+ MX6DL_PAD_SD4_DAT3 = 211,
+ MX6DL_PAD_SD4_DAT4 = 212,
+ MX6DL_PAD_SD4_DAT5 = 213,
+ MX6DL_PAD_SD4_DAT6 = 214,
+ MX6DL_PAD_SD4_DAT7 = 215,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE4),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE5),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE6),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE7),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE8),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE9),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE10),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE11),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE12),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE13),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE14),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE15),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE16),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE17),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE18),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT10),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT11),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT12),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT13),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT14),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT15),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT16),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT17),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT18),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT19),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT4),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT5),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT6),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT7),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT8),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT9),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DATA_EN),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_MCLK),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_PIXCLK),
+ IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_VSYNC),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DI0_DISP_CLK),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN15),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN4),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT10),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT11),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT12),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT13),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT14),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT15),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT16),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT17),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT18),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT19),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT20),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT21),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT22),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT23),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT4),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT5),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT6),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT7),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT8),
+ IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT9),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A16),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A17),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A18),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A19),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A20),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A21),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A22),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A23),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A24),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A25),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_BCLK),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D16),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D17),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D18),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D19),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D20),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D21),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D22),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D23),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D24),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D25),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D26),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D27),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D28),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D29),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D30),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D31),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA10),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA11),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA12),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA13),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA14),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA15),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA4),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA5),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA6),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA7),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA8),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA9),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_LBA),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_OE),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_RW),
+ IMX_PINCTRL_PIN(MX6DL_PAD_EIM_WAIT),
+ IMX_PINCTRL_PIN(MX6DL_PAD_ENET_CRS_DV),
+ IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDC),
+ IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDIO),
+ IMX_PINCTRL_PIN(MX6DL_PAD_ENET_REF_CLK),
+ IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RX_ER),
+ IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TX_EN),
+ IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_16),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_17),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_18),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_19),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_4),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_5),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_6),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_7),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_8),
+ IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_9),
+ IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL4),
+ IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW4),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_ALE),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CLE),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D4),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D5),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D6),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D7),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_RB0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_WP_B),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RX_CTL),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RXC),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TX_CTL),
+ IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TXC),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT4),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT5),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT6),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT7),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD3_RST),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CLK),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CMD),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT0),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT1),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT2),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT3),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT4),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT5),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT6),
+ IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7),
+};
+
+static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
+ .pins = imx6dl_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
+};
+
+static const struct of_device_id imx6dl_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx6dl-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx6dl_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx6dl_pinctrl_info);
+}
+
+static struct platform_driver imx6dl_pinctrl_driver = {
+ .driver = {
+ .name = "imx6dl-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = imx6dl_pinctrl_of_match,
+ },
+ .probe = imx6dl_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+};
+
+static int __init imx6dl_pinctrl_init(void)
+{
+ return platform_driver_register(&imx6dl_pinctrl_driver);
+}
+arch_initcall(imx6dl_pinctrl_init);
+
+static void __exit imx6dl_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx6dl_pinctrl_driver);
+}
+module_exit(imx6dl_pinctrl_exit);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
+MODULE_DESCRIPTION("Freescale imx6dl pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * imx6q pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx6q_pads {
+ MX6Q_PAD_RESERVE0 = 0,
+ MX6Q_PAD_RESERVE1 = 1,
+ MX6Q_PAD_RESERVE2 = 2,
+ MX6Q_PAD_RESERVE3 = 3,
+ MX6Q_PAD_RESERVE4 = 4,
+ MX6Q_PAD_RESERVE5 = 5,
+ MX6Q_PAD_RESERVE6 = 6,
+ MX6Q_PAD_RESERVE7 = 7,
+ MX6Q_PAD_RESERVE8 = 8,
+ MX6Q_PAD_RESERVE9 = 9,
+ MX6Q_PAD_RESERVE10 = 10,
+ MX6Q_PAD_RESERVE11 = 11,
+ MX6Q_PAD_RESERVE12 = 12,
+ MX6Q_PAD_RESERVE13 = 13,
+ MX6Q_PAD_RESERVE14 = 14,
+ MX6Q_PAD_RESERVE15 = 15,
+ MX6Q_PAD_RESERVE16 = 16,
+ MX6Q_PAD_RESERVE17 = 17,
+ MX6Q_PAD_RESERVE18 = 18,
+ MX6Q_PAD_SD2_DAT1 = 19,
+ MX6Q_PAD_SD2_DAT2 = 20,
+ MX6Q_PAD_SD2_DAT0 = 21,
+ MX6Q_PAD_RGMII_TXC = 22,
+ MX6Q_PAD_RGMII_TD0 = 23,
+ MX6Q_PAD_RGMII_TD1 = 24,
+ MX6Q_PAD_RGMII_TD2 = 25,
+ MX6Q_PAD_RGMII_TD3 = 26,
+ MX6Q_PAD_RGMII_RX_CTL = 27,
+ MX6Q_PAD_RGMII_RD0 = 28,
+ MX6Q_PAD_RGMII_TX_CTL = 29,
+ MX6Q_PAD_RGMII_RD1 = 30,
+ MX6Q_PAD_RGMII_RD2 = 31,
+ MX6Q_PAD_RGMII_RD3 = 32,
+ MX6Q_PAD_RGMII_RXC = 33,
+ MX6Q_PAD_EIM_A25 = 34,
+ MX6Q_PAD_EIM_EB2 = 35,
+ MX6Q_PAD_EIM_D16 = 36,
+ MX6Q_PAD_EIM_D17 = 37,
+ MX6Q_PAD_EIM_D18 = 38,
+ MX6Q_PAD_EIM_D19 = 39,
+ MX6Q_PAD_EIM_D20 = 40,
+ MX6Q_PAD_EIM_D21 = 41,
+ MX6Q_PAD_EIM_D22 = 42,
+ MX6Q_PAD_EIM_D23 = 43,
+ MX6Q_PAD_EIM_EB3 = 44,
+ MX6Q_PAD_EIM_D24 = 45,
+ MX6Q_PAD_EIM_D25 = 46,
+ MX6Q_PAD_EIM_D26 = 47,
+ MX6Q_PAD_EIM_D27 = 48,
+ MX6Q_PAD_EIM_D28 = 49,
+ MX6Q_PAD_EIM_D29 = 50,
+ MX6Q_PAD_EIM_D30 = 51,
+ MX6Q_PAD_EIM_D31 = 52,
+ MX6Q_PAD_EIM_A24 = 53,
+ MX6Q_PAD_EIM_A23 = 54,
+ MX6Q_PAD_EIM_A22 = 55,
+ MX6Q_PAD_EIM_A21 = 56,
+ MX6Q_PAD_EIM_A20 = 57,
+ MX6Q_PAD_EIM_A19 = 58,
+ MX6Q_PAD_EIM_A18 = 59,
+ MX6Q_PAD_EIM_A17 = 60,
+ MX6Q_PAD_EIM_A16 = 61,
+ MX6Q_PAD_EIM_CS0 = 62,
+ MX6Q_PAD_EIM_CS1 = 63,
+ MX6Q_PAD_EIM_OE = 64,
+ MX6Q_PAD_EIM_RW = 65,
+ MX6Q_PAD_EIM_LBA = 66,
+ MX6Q_PAD_EIM_EB0 = 67,
+ MX6Q_PAD_EIM_EB1 = 68,
+ MX6Q_PAD_EIM_DA0 = 69,
+ MX6Q_PAD_EIM_DA1 = 70,
+ MX6Q_PAD_EIM_DA2 = 71,
+ MX6Q_PAD_EIM_DA3 = 72,
+ MX6Q_PAD_EIM_DA4 = 73,
+ MX6Q_PAD_EIM_DA5 = 74,
+ MX6Q_PAD_EIM_DA6 = 75,
+ MX6Q_PAD_EIM_DA7 = 76,
+ MX6Q_PAD_EIM_DA8 = 77,
+ MX6Q_PAD_EIM_DA9 = 78,
+ MX6Q_PAD_EIM_DA10 = 79,
+ MX6Q_PAD_EIM_DA11 = 80,
+ MX6Q_PAD_EIM_DA12 = 81,
+ MX6Q_PAD_EIM_DA13 = 82,
+ MX6Q_PAD_EIM_DA14 = 83,
+ MX6Q_PAD_EIM_DA15 = 84,
+ MX6Q_PAD_EIM_WAIT = 85,
+ MX6Q_PAD_EIM_BCLK = 86,
+ MX6Q_PAD_DI0_DISP_CLK = 87,
+ MX6Q_PAD_DI0_PIN15 = 88,
+ MX6Q_PAD_DI0_PIN2 = 89,
+ MX6Q_PAD_DI0_PIN3 = 90,
+ MX6Q_PAD_DI0_PIN4 = 91,
+ MX6Q_PAD_DISP0_DAT0 = 92,
+ MX6Q_PAD_DISP0_DAT1 = 93,
+ MX6Q_PAD_DISP0_DAT2 = 94,
+ MX6Q_PAD_DISP0_DAT3 = 95,
+ MX6Q_PAD_DISP0_DAT4 = 96,
+ MX6Q_PAD_DISP0_DAT5 = 97,
+ MX6Q_PAD_DISP0_DAT6 = 98,
+ MX6Q_PAD_DISP0_DAT7 = 99,
+ MX6Q_PAD_DISP0_DAT8 = 100,
+ MX6Q_PAD_DISP0_DAT9 = 101,
+ MX6Q_PAD_DISP0_DAT10 = 102,
+ MX6Q_PAD_DISP0_DAT11 = 103,
+ MX6Q_PAD_DISP0_DAT12 = 104,
+ MX6Q_PAD_DISP0_DAT13 = 105,
+ MX6Q_PAD_DISP0_DAT14 = 106,
+ MX6Q_PAD_DISP0_DAT15 = 107,
+ MX6Q_PAD_DISP0_DAT16 = 108,
+ MX6Q_PAD_DISP0_DAT17 = 109,
+ MX6Q_PAD_DISP0_DAT18 = 110,
+ MX6Q_PAD_DISP0_DAT19 = 111,
+ MX6Q_PAD_DISP0_DAT20 = 112,
+ MX6Q_PAD_DISP0_DAT21 = 113,
+ MX6Q_PAD_DISP0_DAT22 = 114,
+ MX6Q_PAD_DISP0_DAT23 = 115,
+ MX6Q_PAD_ENET_MDIO = 116,
+ MX6Q_PAD_ENET_REF_CLK = 117,
+ MX6Q_PAD_ENET_RX_ER = 118,
+ MX6Q_PAD_ENET_CRS_DV = 119,
+ MX6Q_PAD_ENET_RXD1 = 120,
+ MX6Q_PAD_ENET_RXD0 = 121,
+ MX6Q_PAD_ENET_TX_EN = 122,
+ MX6Q_PAD_ENET_TXD1 = 123,
+ MX6Q_PAD_ENET_TXD0 = 124,
+ MX6Q_PAD_ENET_MDC = 125,
+ MX6Q_PAD_KEY_COL0 = 126,
+ MX6Q_PAD_KEY_ROW0 = 127,
+ MX6Q_PAD_KEY_COL1 = 128,
+ MX6Q_PAD_KEY_ROW1 = 129,
+ MX6Q_PAD_KEY_COL2 = 130,
+ MX6Q_PAD_KEY_ROW2 = 131,
+ MX6Q_PAD_KEY_COL3 = 132,
+ MX6Q_PAD_KEY_ROW3 = 133,
+ MX6Q_PAD_KEY_COL4 = 134,
+ MX6Q_PAD_KEY_ROW4 = 135,
+ MX6Q_PAD_GPIO_0 = 136,
+ MX6Q_PAD_GPIO_1 = 137,
+ MX6Q_PAD_GPIO_9 = 138,
+ MX6Q_PAD_GPIO_3 = 139,
+ MX6Q_PAD_GPIO_6 = 140,
+ MX6Q_PAD_GPIO_2 = 141,
+ MX6Q_PAD_GPIO_4 = 142,
+ MX6Q_PAD_GPIO_5 = 143,
+ MX6Q_PAD_GPIO_7 = 144,
+ MX6Q_PAD_GPIO_8 = 145,
+ MX6Q_PAD_GPIO_16 = 146,
+ MX6Q_PAD_GPIO_17 = 147,
+ MX6Q_PAD_GPIO_18 = 148,
+ MX6Q_PAD_GPIO_19 = 149,
+ MX6Q_PAD_CSI0_PIXCLK = 150,
+ MX6Q_PAD_CSI0_MCLK = 151,
+ MX6Q_PAD_CSI0_DATA_EN = 152,
+ MX6Q_PAD_CSI0_VSYNC = 153,
+ MX6Q_PAD_CSI0_DAT4 = 154,
+ MX6Q_PAD_CSI0_DAT5 = 155,
+ MX6Q_PAD_CSI0_DAT6 = 156,
+ MX6Q_PAD_CSI0_DAT7 = 157,
+ MX6Q_PAD_CSI0_DAT8 = 158,
+ MX6Q_PAD_CSI0_DAT9 = 159,
+ MX6Q_PAD_CSI0_DAT10 = 160,
+ MX6Q_PAD_CSI0_DAT11 = 161,
+ MX6Q_PAD_CSI0_DAT12 = 162,
+ MX6Q_PAD_CSI0_DAT13 = 163,
+ MX6Q_PAD_CSI0_DAT14 = 164,
+ MX6Q_PAD_CSI0_DAT15 = 165,
+ MX6Q_PAD_CSI0_DAT16 = 166,
+ MX6Q_PAD_CSI0_DAT17 = 167,
+ MX6Q_PAD_CSI0_DAT18 = 168,
+ MX6Q_PAD_CSI0_DAT19 = 169,
+ MX6Q_PAD_SD3_DAT7 = 170,
+ MX6Q_PAD_SD3_DAT6 = 171,
+ MX6Q_PAD_SD3_DAT5 = 172,
+ MX6Q_PAD_SD3_DAT4 = 173,
+ MX6Q_PAD_SD3_CMD = 174,
+ MX6Q_PAD_SD3_CLK = 175,
+ MX6Q_PAD_SD3_DAT0 = 176,
+ MX6Q_PAD_SD3_DAT1 = 177,
+ MX6Q_PAD_SD3_DAT2 = 178,
+ MX6Q_PAD_SD3_DAT3 = 179,
+ MX6Q_PAD_SD3_RST = 180,
+ MX6Q_PAD_NANDF_CLE = 181,
+ MX6Q_PAD_NANDF_ALE = 182,
+ MX6Q_PAD_NANDF_WP_B = 183,
+ MX6Q_PAD_NANDF_RB0 = 184,
+ MX6Q_PAD_NANDF_CS0 = 185,
+ MX6Q_PAD_NANDF_CS1 = 186,
+ MX6Q_PAD_NANDF_CS2 = 187,
+ MX6Q_PAD_NANDF_CS3 = 188,
+ MX6Q_PAD_SD4_CMD = 189,
+ MX6Q_PAD_SD4_CLK = 190,
+ MX6Q_PAD_NANDF_D0 = 191,
+ MX6Q_PAD_NANDF_D1 = 192,
+ MX6Q_PAD_NANDF_D2 = 193,
+ MX6Q_PAD_NANDF_D3 = 194,
+ MX6Q_PAD_NANDF_D4 = 195,
+ MX6Q_PAD_NANDF_D5 = 196,
+ MX6Q_PAD_NANDF_D6 = 197,
+ MX6Q_PAD_NANDF_D7 = 198,
+ MX6Q_PAD_SD4_DAT0 = 199,
+ MX6Q_PAD_SD4_DAT1 = 200,
+ MX6Q_PAD_SD4_DAT2 = 201,
+ MX6Q_PAD_SD4_DAT3 = 202,
+ MX6Q_PAD_SD4_DAT4 = 203,
+ MX6Q_PAD_SD4_DAT5 = 204,
+ MX6Q_PAD_SD4_DAT6 = 205,
+ MX6Q_PAD_SD4_DAT7 = 206,
+ MX6Q_PAD_SD1_DAT1 = 207,
+ MX6Q_PAD_SD1_DAT0 = 208,
+ MX6Q_PAD_SD1_DAT3 = 209,
+ MX6Q_PAD_SD1_CMD = 210,
+ MX6Q_PAD_SD1_DAT2 = 211,
+ MX6Q_PAD_SD1_CLK = 212,
+ MX6Q_PAD_SD2_CLK = 213,
+ MX6Q_PAD_SD2_CMD = 214,
+ MX6Q_PAD_SD2_DAT3 = 215,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE4),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE5),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE6),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE7),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE8),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE9),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE10),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE11),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE12),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE13),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE14),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE15),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE16),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE17),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE18),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT),
+ IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22),
+ IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23),
+ IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO),
+ IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK),
+ IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER),
+ IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV),
+ IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN),
+ IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
+ IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4),
+ IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18),
+ IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
+ IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6),
+ IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
+};
+
+static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
+ .pins = imx6q_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
+};
+
+static const struct of_device_id imx6q_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx6q-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx6q_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info);
+}
+
+static struct platform_driver imx6q_pinctrl_driver = {
+ .driver = {
+ .name = "imx6q-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = imx6q_pinctrl_of_match,
+ },
+ .probe = imx6q_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+};
+
+static int __init imx6q_pinctrl_init(void)
+{
+ return platform_driver_register(&imx6q_pinctrl_driver);
+}
+arch_initcall(imx6q_pinctrl_init);
+
+static void __exit imx6q_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx6q_pinctrl_driver);
+}
+module_exit(imx6q_pinctrl_exit);
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
+MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx6sl_pads {
+ MX6SL_PAD_RESERVE0 = 0,
+ MX6SL_PAD_RESERVE1 = 1,
+ MX6SL_PAD_RESERVE2 = 2,
+ MX6SL_PAD_RESERVE3 = 3,
+ MX6SL_PAD_RESERVE4 = 4,
+ MX6SL_PAD_RESERVE5 = 5,
+ MX6SL_PAD_RESERVE6 = 6,
+ MX6SL_PAD_RESERVE7 = 7,
+ MX6SL_PAD_RESERVE8 = 8,
+ MX6SL_PAD_RESERVE9 = 9,
+ MX6SL_PAD_RESERVE10 = 10,
+ MX6SL_PAD_RESERVE11 = 11,
+ MX6SL_PAD_RESERVE12 = 12,
+ MX6SL_PAD_RESERVE13 = 13,
+ MX6SL_PAD_RESERVE14 = 14,
+ MX6SL_PAD_RESERVE15 = 15,
+ MX6SL_PAD_RESERVE16 = 16,
+ MX6SL_PAD_RESERVE17 = 17,
+ MX6SL_PAD_RESERVE18 = 18,
+ MX6SL_PAD_AUD_MCLK = 19,
+ MX6SL_PAD_AUD_RXC = 20,
+ MX6SL_PAD_AUD_RXD = 21,
+ MX6SL_PAD_AUD_RXFS = 22,
+ MX6SL_PAD_AUD_TXC = 23,
+ MX6SL_PAD_AUD_TXD = 24,
+ MX6SL_PAD_AUD_TXFS = 25,
+ MX6SL_PAD_ECSPI1_MISO = 26,
+ MX6SL_PAD_ECSPI1_MOSI = 27,
+ MX6SL_PAD_ECSPI1_SCLK = 28,
+ MX6SL_PAD_ECSPI1_SS0 = 29,
+ MX6SL_PAD_ECSPI2_MISO = 30,
+ MX6SL_PAD_ECSPI2_MOSI = 31,
+ MX6SL_PAD_ECSPI2_SCLK = 32,
+ MX6SL_PAD_ECSPI2_SS0 = 33,
+ MX6SL_PAD_EPDC_BDR0 = 34,
+ MX6SL_PAD_EPDC_BDR1 = 35,
+ MX6SL_PAD_EPDC_D0 = 36,
+ MX6SL_PAD_EPDC_D1 = 37,
+ MX6SL_PAD_EPDC_D10 = 38,
+ MX6SL_PAD_EPDC_D11 = 39,
+ MX6SL_PAD_EPDC_D12 = 40,
+ MX6SL_PAD_EPDC_D13 = 41,
+ MX6SL_PAD_EPDC_D14 = 42,
+ MX6SL_PAD_EPDC_D15 = 43,
+ MX6SL_PAD_EPDC_D2 = 44,
+ MX6SL_PAD_EPDC_D3 = 45,
+ MX6SL_PAD_EPDC_D4 = 46,
+ MX6SL_PAD_EPDC_D5 = 47,
+ MX6SL_PAD_EPDC_D6 = 48,
+ MX6SL_PAD_EPDC_D7 = 49,
+ MX6SL_PAD_EPDC_D8 = 50,
+ MX6SL_PAD_EPDC_D9 = 51,
+ MX6SL_PAD_EPDC_GDCLK = 52,
+ MX6SL_PAD_EPDC_GDOE = 53,
+ MX6SL_PAD_EPDC_GDRL = 54,
+ MX6SL_PAD_EPDC_GDSP = 55,
+ MX6SL_PAD_EPDC_PWRCOM = 56,
+ MX6SL_PAD_EPDC_PWRCTRL0 = 57,
+ MX6SL_PAD_EPDC_PWRCTRL1 = 58,
+ MX6SL_PAD_EPDC_PWRCTRL2 = 59,
+ MX6SL_PAD_EPDC_PWRCTRL3 = 60,
+ MX6SL_PAD_EPDC_PWRINT = 61,
+ MX6SL_PAD_EPDC_PWRSTAT = 62,
+ MX6SL_PAD_EPDC_PWRWAKEUP = 63,
+ MX6SL_PAD_EPDC_SDCE0 = 64,
+ MX6SL_PAD_EPDC_SDCE1 = 65,
+ MX6SL_PAD_EPDC_SDCE2 = 66,
+ MX6SL_PAD_EPDC_SDCE3 = 67,
+ MX6SL_PAD_EPDC_SDCLK = 68,
+ MX6SL_PAD_EPDC_SDLE = 69,
+ MX6SL_PAD_EPDC_SDOE = 70,
+ MX6SL_PAD_EPDC_SDSHR = 71,
+ MX6SL_PAD_EPDC_VCOM0 = 72,
+ MX6SL_PAD_EPDC_VCOM1 = 73,
+ MX6SL_PAD_FEC_CRS_DV = 74,
+ MX6SL_PAD_FEC_MDC = 75,
+ MX6SL_PAD_FEC_MDIO = 76,
+ MX6SL_PAD_FEC_REF_CLK = 77,
+ MX6SL_PAD_FEC_RX_ER = 78,
+ MX6SL_PAD_FEC_RXD0 = 79,
+ MX6SL_PAD_FEC_RXD1 = 80,
+ MX6SL_PAD_FEC_TX_CLK = 81,
+ MX6SL_PAD_FEC_TX_EN = 82,
+ MX6SL_PAD_FEC_TXD0 = 83,
+ MX6SL_PAD_FEC_TXD1 = 84,
+ MX6SL_PAD_HSIC_DAT = 85,
+ MX6SL_PAD_HSIC_STROBE = 86,
+ MX6SL_PAD_I2C1_SCL = 87,
+ MX6SL_PAD_I2C1_SDA = 88,
+ MX6SL_PAD_I2C2_SCL = 89,
+ MX6SL_PAD_I2C2_SDA = 90,
+ MX6SL_PAD_KEY_COL0 = 91,
+ MX6SL_PAD_KEY_COL1 = 92,
+ MX6SL_PAD_KEY_COL2 = 93,
+ MX6SL_PAD_KEY_COL3 = 94,
+ MX6SL_PAD_KEY_COL4 = 95,
+ MX6SL_PAD_KEY_COL5 = 96,
+ MX6SL_PAD_KEY_COL6 = 97,
+ MX6SL_PAD_KEY_COL7 = 98,
+ MX6SL_PAD_KEY_ROW0 = 99,
+ MX6SL_PAD_KEY_ROW1 = 100,
+ MX6SL_PAD_KEY_ROW2 = 101,
+ MX6SL_PAD_KEY_ROW3 = 102,
+ MX6SL_PAD_KEY_ROW4 = 103,
+ MX6SL_PAD_KEY_ROW5 = 104,
+ MX6SL_PAD_KEY_ROW6 = 105,
+ MX6SL_PAD_KEY_ROW7 = 106,
+ MX6SL_PAD_LCD_CLK = 107,
+ MX6SL_PAD_LCD_DAT0 = 108,
+ MX6SL_PAD_LCD_DAT1 = 109,
+ MX6SL_PAD_LCD_DAT10 = 110,
+ MX6SL_PAD_LCD_DAT11 = 111,
+ MX6SL_PAD_LCD_DAT12 = 112,
+ MX6SL_PAD_LCD_DAT13 = 113,
+ MX6SL_PAD_LCD_DAT14 = 114,
+ MX6SL_PAD_LCD_DAT15 = 115,
+ MX6SL_PAD_LCD_DAT16 = 116,
+ MX6SL_PAD_LCD_DAT17 = 117,
+ MX6SL_PAD_LCD_DAT18 = 118,
+ MX6SL_PAD_LCD_DAT19 = 119,
+ MX6SL_PAD_LCD_DAT2 = 120,
+ MX6SL_PAD_LCD_DAT20 = 121,
+ MX6SL_PAD_LCD_DAT21 = 122,
+ MX6SL_PAD_LCD_DAT22 = 123,
+ MX6SL_PAD_LCD_DAT23 = 124,
+ MX6SL_PAD_LCD_DAT3 = 125,
+ MX6SL_PAD_LCD_DAT4 = 126,
+ MX6SL_PAD_LCD_DAT5 = 127,
+ MX6SL_PAD_LCD_DAT6 = 128,
+ MX6SL_PAD_LCD_DAT7 = 129,
+ MX6SL_PAD_LCD_DAT8 = 130,
+ MX6SL_PAD_LCD_DAT9 = 131,
+ MX6SL_PAD_LCD_ENABLE = 132,
+ MX6SL_PAD_LCD_HSYNC = 133,
+ MX6SL_PAD_LCD_RESET = 134,
+ MX6SL_PAD_LCD_VSYNC = 135,
+ MX6SL_PAD_PWM1 = 136,
+ MX6SL_PAD_REF_CLK_24M = 137,
+ MX6SL_PAD_REF_CLK_32K = 138,
+ MX6SL_PAD_SD1_CLK = 139,
+ MX6SL_PAD_SD1_CMD = 140,
+ MX6SL_PAD_SD1_DAT0 = 141,
+ MX6SL_PAD_SD1_DAT1 = 142,
+ MX6SL_PAD_SD1_DAT2 = 143,
+ MX6SL_PAD_SD1_DAT3 = 144,
+ MX6SL_PAD_SD1_DAT4 = 145,
+ MX6SL_PAD_SD1_DAT5 = 146,
+ MX6SL_PAD_SD1_DAT6 = 147,
+ MX6SL_PAD_SD1_DAT7 = 148,
+ MX6SL_PAD_SD2_CLK = 149,
+ MX6SL_PAD_SD2_CMD = 150,
+ MX6SL_PAD_SD2_DAT0 = 151,
+ MX6SL_PAD_SD2_DAT1 = 152,
+ MX6SL_PAD_SD2_DAT2 = 153,
+ MX6SL_PAD_SD2_DAT3 = 154,
+ MX6SL_PAD_SD2_DAT4 = 155,
+ MX6SL_PAD_SD2_DAT5 = 156,
+ MX6SL_PAD_SD2_DAT6 = 157,
+ MX6SL_PAD_SD2_DAT7 = 158,
+ MX6SL_PAD_SD2_RST = 159,
+ MX6SL_PAD_SD3_CLK = 160,
+ MX6SL_PAD_SD3_CMD = 161,
+ MX6SL_PAD_SD3_DAT0 = 162,
+ MX6SL_PAD_SD3_DAT1 = 163,
+ MX6SL_PAD_SD3_DAT2 = 164,
+ MX6SL_PAD_SD3_DAT3 = 165,
+ MX6SL_PAD_UART1_RXD = 166,
+ MX6SL_PAD_UART1_TXD = 167,
+ MX6SL_PAD_WDOG_B = 168,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE2),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE3),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE4),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE5),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE6),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE7),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE8),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE9),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE10),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE11),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE12),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE13),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE14),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE15),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE16),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE17),
+ IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE18),
+ IMX_PINCTRL_PIN(MX6SL_PAD_AUD_MCLK),
+ IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXC),
+ IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXD),
+ IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXFS),
+ IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXC),
+ IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXD),
+ IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXFS),
+ IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MISO),
+ IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MOSI),
+ IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SCLK),
+ IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SS0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MISO),
+ IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MOSI),
+ IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SCLK),
+ IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SS0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D10),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D11),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D12),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D13),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D14),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D15),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D2),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D3),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D4),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D5),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D6),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D7),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D8),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D9),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDCLK),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDOE),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDRL),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDSP),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCOM),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL2),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL3),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRINT),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRSTAT),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRWAKEUP),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE2),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE3),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCLK),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDLE),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDOE),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDSHR),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_FEC_CRS_DV),
+ IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDC),
+ IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDIO),
+ IMX_PINCTRL_PIN(MX6SL_PAD_FEC_REF_CLK),
+ IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RX_ER),
+ IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_CLK),
+ IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_EN),
+ IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_DAT),
+ IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_STROBE),
+ IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SCL),
+ IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SDA),
+ IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SCL),
+ IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SDA),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL2),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL3),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL4),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL5),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL6),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL7),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW2),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW3),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW4),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW5),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW6),
+ IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW7),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_CLK),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT10),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT11),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT12),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT13),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT14),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT15),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT16),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT17),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT18),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT19),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT2),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT20),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT21),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT22),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT23),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT3),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT4),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT5),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT6),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT7),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT8),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT9),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_ENABLE),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_HSYNC),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_RESET),
+ IMX_PINCTRL_PIN(MX6SL_PAD_LCD_VSYNC),
+ IMX_PINCTRL_PIN(MX6SL_PAD_PWM1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_24M),
+ IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_32K),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT2),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT3),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT4),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT5),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT6),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT7),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT2),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT3),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT4),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT5),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT6),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT7),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD2_RST),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT0),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT1),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT2),
+ IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT3),
+ IMX_PINCTRL_PIN(MX6SL_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX6SL_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX6SL_PAD_WDOG_B),
+};
+
+static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
+ .pins = imx6sl_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
+};
+
+static const struct of_device_id imx6sl_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx6sl-iomuxc", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx6sl_pinctrl_of_match);
+
+static int imx6sl_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx6sl_pinctrl_info);
+}
+
+static struct platform_driver imx6sl_pinctrl_driver = {
+ .driver = {
+ .name = "imx6sl-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = imx6sl_pinctrl_of_match,
+ },
+ .probe = imx6sl_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+};
+
+static int __init imx6sl_pinctrl_init(void)
+{
+ return platform_driver_register(&imx6sl_pinctrl_driver);
+}
+arch_initcall(imx6sl_pinctrl_init);
+
+static void __exit imx6sl_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx6sl_pinctrl_driver);
+}
+module_exit(imx6sl_pinctrl_exit);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
+MODULE_DESCRIPTION("Freescale imx6sl pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx6sx_pads {
+ MX6Sx_PAD_RESERVE0 = 0,
+ MX6Sx_PAD_RESERVE1 = 1,
+ MX6Sx_PAD_RESERVE2 = 2,
+ MX6Sx_PAD_RESERVE3 = 3,
+ MX6Sx_PAD_RESERVE4 = 4,
+ MX6SX_PAD_GPIO1_IO00 = 5,
+ MX6SX_PAD_GPIO1_IO01 = 6,
+ MX6SX_PAD_GPIO1_IO02 = 7,
+ MX6SX_PAD_GPIO1_IO03 = 8,
+ MX6SX_PAD_GPIO1_IO04 = 9,
+ MX6SX_PAD_GPIO1_IO05 = 10,
+ MX6SX_PAD_GPIO1_IO06 = 11,
+ MX6SX_PAD_GPIO1_IO07 = 12,
+ MX6SX_PAD_GPIO1_IO08 = 13,
+ MX6SX_PAD_GPIO1_IO09 = 14,
+ MX6SX_PAD_GPIO1_IO10 = 15,
+ MX6SX_PAD_GPIO1_IO11 = 16,
+ MX6SX_PAD_GPIO1_IO12 = 17,
+ MX6SX_PAD_GPIO1_IO13 = 18,
+ MX6SX_PAD_CSI_DATA00 = 19,
+ MX6SX_PAD_CSI_DATA01 = 20,
+ MX6SX_PAD_CSI_DATA02 = 21,
+ MX6SX_PAD_CSI_DATA03 = 22,
+ MX6SX_PAD_CSI_DATA04 = 23,
+ MX6SX_PAD_CSI_DATA05 = 24,
+ MX6SX_PAD_CSI_DATA06 = 25,
+ MX6SX_PAD_CSI_DATA07 = 26,
+ MX6SX_PAD_CSI_HSYNC = 27,
+ MX6SX_PAD_CSI_MCLK = 28,
+ MX6SX_PAD_CSI_PIXCLK = 29,
+ MX6SX_PAD_CSI_VSYNC = 30,
+ MX6SX_PAD_ENET1_COL = 31,
+ MX6SX_PAD_ENET1_CRS = 32,
+ MX6SX_PAD_ENET1_MDC = 33,
+ MX6SX_PAD_ENET1_MDIO = 34,
+ MX6SX_PAD_ENET1_RX_CLK = 35,
+ MX6SX_PAD_ENET1_TX_CLK = 36,
+ MX6SX_PAD_ENET2_COL = 37,
+ MX6SX_PAD_ENET2_CRS = 38,
+ MX6SX_PAD_ENET2_RX_CLK = 39,
+ MX6SX_PAD_ENET2_TX_CLK = 40,
+ MX6SX_PAD_KEY_COL0 = 41,
+ MX6SX_PAD_KEY_COL1 = 42,
+ MX6SX_PAD_KEY_COL2 = 43,
+ MX6SX_PAD_KEY_COL3 = 44,
+ MX6SX_PAD_KEY_COL4 = 45,
+ MX6SX_PAD_KEY_ROW0 = 46,
+ MX6SX_PAD_KEY_ROW1 = 47,
+ MX6SX_PAD_KEY_ROW2 = 48,
+ MX6SX_PAD_KEY_ROW3 = 49,
+ MX6SX_PAD_KEY_ROW4 = 50,
+ MX6SX_PAD_LCD1_CLK = 51,
+ MX6SX_PAD_LCD1_DATA00 = 52,
+ MX6SX_PAD_LCD1_DATA01 = 53,
+ MX6SX_PAD_LCD1_DATA02 = 54,
+ MX6SX_PAD_LCD1_DATA03 = 55,
+ MX6SX_PAD_LCD1_DATA04 = 56,
+ MX6SX_PAD_LCD1_DATA05 = 57,
+ MX6SX_PAD_LCD1_DATA06 = 58,
+ MX6SX_PAD_LCD1_DATA07 = 59,
+ MX6SX_PAD_LCD1_DATA08 = 60,
+ MX6SX_PAD_LCD1_DATA09 = 61,
+ MX6SX_PAD_LCD1_DATA10 = 62,
+ MX6SX_PAD_LCD1_DATA11 = 63,
+ MX6SX_PAD_LCD1_DATA12 = 64,
+ MX6SX_PAD_LCD1_DATA13 = 65,
+ MX6SX_PAD_LCD1_DATA14 = 66,
+ MX6SX_PAD_LCD1_DATA15 = 67,
+ MX6SX_PAD_LCD1_DATA16 = 68,
+ MX6SX_PAD_LCD1_DATA17 = 69,
+ MX6SX_PAD_LCD1_DATA18 = 70,
+ MX6SX_PAD_LCD1_DATA19 = 71,
+ MX6SX_PAD_LCD1_DATA20 = 72,
+ MX6SX_PAD_LCD1_DATA21 = 73,
+ MX6SX_PAD_LCD1_DATA22 = 74,
+ MX6SX_PAD_LCD1_DATA23 = 75,
+ MX6SX_PAD_LCD1_ENABLE = 76,
+ MX6SX_PAD_LCD1_HSYNC = 77,
+ MX6SX_PAD_LCD1_RESET = 78,
+ MX6SX_PAD_LCD1_VSYNC = 79,
+ MX6SX_PAD_NAND_ALE = 80,
+ MX6SX_PAD_NAND_CE0_B = 81,
+ MX6SX_PAD_NAND_CE1_B = 82,
+ MX6SX_PAD_NAND_CLE = 83,
+ MX6SX_PAD_NAND_DATA00 = 84 ,
+ MX6SX_PAD_NAND_DATA01 = 85,
+ MX6SX_PAD_NAND_DATA02 = 86,
+ MX6SX_PAD_NAND_DATA03 = 87,
+ MX6SX_PAD_NAND_DATA04 = 88,
+ MX6SX_PAD_NAND_DATA05 = 89,
+ MX6SX_PAD_NAND_DATA06 = 90,
+ MX6SX_PAD_NAND_DATA07 = 91,
+ MX6SX_PAD_NAND_RE_B = 92,
+ MX6SX_PAD_NAND_READY_B = 93,
+ MX6SX_PAD_NAND_WE_B = 94,
+ MX6SX_PAD_NAND_WP_B = 95,
+ MX6SX_PAD_QSPI1A_DATA0 = 96,
+ MX6SX_PAD_QSPI1A_DATA1 = 97,
+ MX6SX_PAD_QSPI1A_DATA2 = 98,
+ MX6SX_PAD_QSPI1A_DATA3 = 99,
+ MX6SX_PAD_QSPI1A_DQS = 100,
+ MX6SX_PAD_QSPI1A_SCLK = 101,
+ MX6SX_PAD_QSPI1A_SS0_B = 102,
+ MX6SX_PAD_QSPI1A_SS1_B = 103,
+ MX6SX_PAD_QSPI1B_DATA0 = 104,
+ MX6SX_PAD_QSPI1B_DATA1 = 105,
+ MX6SX_PAD_QSPI1B_DATA2 = 106,
+ MX6SX_PAD_QSPI1B_DATA3 = 107,
+ MX6SX_PAD_QSPI1B_DQS = 108,
+ MX6SX_PAD_QSPI1B_SCLK = 109,
+ MX6SX_PAD_QSPI1B_SS0_B = 110,
+ MX6SX_PAD_QSPI1B_SS1_B = 111,
+ MX6SX_PAD_RGMII1_RD0 = 112,
+ MX6SX_PAD_RGMII1_RD1 = 113,
+ MX6SX_PAD_RGMII1_RD2 = 114,
+ MX6SX_PAD_RGMII1_RD3 = 115,
+ MX6SX_PAD_RGMII1_RX_CTL = 116,
+ MX6SX_PAD_RGMII1_RXC = 117,
+ MX6SX_PAD_RGMII1_TD0 = 118,
+ MX6SX_PAD_RGMII1_TD1 = 119,
+ MX6SX_PAD_RGMII1_TD2 = 120,
+ MX6SX_PAD_RGMII1_TD3 = 121,
+ MX6SX_PAD_RGMII1_TX_CTL = 122,
+ MX6SX_PAD_RGMII1_TXC = 123,
+ MX6SX_PAD_RGMII2_RD0 = 124,
+ MX6SX_PAD_RGMII2_RD1 = 125,
+ MX6SX_PAD_RGMII2_RD2 = 126,
+ MX6SX_PAD_RGMII2_RD3 = 127,
+ MX6SX_PAD_RGMII2_RX_CTL = 128,
+ MX6SX_PAD_RGMII2_RXC = 129,
+ MX6SX_PAD_RGMII2_TD0 = 130,
+ MX6SX_PAD_RGMII2_TD1 = 131,
+ MX6SX_PAD_RGMII2_TD2 = 132,
+ MX6SX_PAD_RGMII2_TD3 = 133,
+ MX6SX_PAD_RGMII2_TX_CTL = 134,
+ MX6SX_PAD_RGMII2_TXC = 135,
+ MX6SX_PAD_SD1_CLK = 136,
+ MX6SX_PAD_SD1_CMD = 137,
+ MX6SX_PAD_SD1_DATA0 = 138,
+ MX6SX_PAD_SD1_DATA1 = 139,
+ MX6SX_PAD_SD1_DATA2 = 140,
+ MX6SX_PAD_SD1_DATA3 = 141,
+ MX6SX_PAD_SD2_CLK = 142,
+ MX6SX_PAD_SD2_CMD = 143,
+ MX6SX_PAD_SD2_DATA0 = 144,
+ MX6SX_PAD_SD2_DATA1 = 145,
+ MX6SX_PAD_SD2_DATA2 = 146,
+ MX6SX_PAD_SD2_DATA3 = 147,
+ MX6SX_PAD_SD3_CLK = 148,
+ MX6SX_PAD_SD3_CMD = 149,
+ MX6SX_PAD_SD3_DATA0 = 150,
+ MX6SX_PAD_SD3_DATA1 = 151,
+ MX6SX_PAD_SD3_DATA2 = 152,
+ MX6SX_PAD_SD3_DATA3 = 153,
+ MX6SX_PAD_SD3_DATA4 = 154,
+ MX6SX_PAD_SD3_DATA5 = 155,
+ MX6SX_PAD_SD3_DATA6 = 156,
+ MX6SX_PAD_SD3_DATA7 = 157,
+ MX6SX_PAD_SD4_CLK = 158,
+ MX6SX_PAD_SD4_CMD = 159,
+ MX6SX_PAD_SD4_DATA0 = 160,
+ MX6SX_PAD_SD4_DATA1 = 161,
+ MX6SX_PAD_SD4_DATA2 = 162,
+ MX6SX_PAD_SD4_DATA3 = 163,
+ MX6SX_PAD_SD4_DATA4 = 164,
+ MX6SX_PAD_SD4_DATA5 = 165,
+ MX6SX_PAD_SD4_DATA6 = 166,
+ MX6SX_PAD_SD4_DATA7 = 167,
+ MX6SX_PAD_SD4_RESET_B = 168,
+ MX6SX_PAD_USB_H_DATA = 169,
+ MX6SX_PAD_USB_H_STROBE = 170,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE2),
+ IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE3),
+ IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE4),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO00),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO01),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO02),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO03),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO04),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO05),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO06),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO07),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO08),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO09),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO10),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO11),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO12),
+ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO13),
+ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA00),
+ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA01),
+ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA02),
+ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA03),
+ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA04),
+ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA05),
+ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA06),
+ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA07),
+ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_HSYNC),
+ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_MCLK),
+ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_PIXCLK),
+ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_VSYNC),
+ IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_COL),
+ IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_CRS),
+ IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDC),
+ IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDIO),
+ IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_RX_CLK),
+ IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_TX_CLK),
+ IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_COL),
+ IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_CRS),
+ IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_RX_CLK),
+ IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_TX_CLK),
+ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL0),
+ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL1),
+ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL2),
+ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL3),
+ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL4),
+ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW0),
+ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW1),
+ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW2),
+ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW3),
+ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW4),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_CLK),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA00),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA01),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA02),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA03),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA04),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA05),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA06),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA07),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA08),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA09),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA10),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA11),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA12),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA13),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA14),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA15),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA16),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA17),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA18),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA19),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA20),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA21),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA22),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA23),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_ENABLE),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_HSYNC),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_RESET),
+ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_VSYNC),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_ALE),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE0_B),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE1_B),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CLE),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA00),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA01),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA02),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA03),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA04),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA05),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA06),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA07),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_RE_B),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_READY_B),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WE_B),
+ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WP_B),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA0),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA1),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA2),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA3),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DQS),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SCLK),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS0_B),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS1_B),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA0),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA1),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA2),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA3),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DQS),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SCLK),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS0_B),
+ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS1_B),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD0),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD1),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD2),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD3),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RX_CTL),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RXC),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD0),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD1),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD2),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD3),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TX_CTL),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TXC),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD0),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD1),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD2),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD3),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RX_CTL),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RXC),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD0),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD1),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD2),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD3),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TX_CTL),
+ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TXC),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA0),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA1),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA2),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA3),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA0),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA1),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA2),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA3),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA0),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA1),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA2),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA3),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA4),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA5),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA6),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA7),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CLK),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CMD),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA0),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA1),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA2),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA3),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA4),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA5),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA6),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA7),
+ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_RESET_B),
+ IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_DATA),
+ IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE),
+};
+
+static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
+ .pins = imx6sx_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
+};
+
+static const struct of_device_id imx6sx_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx6sx-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx6sx_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx6sx_pinctrl_info);
+}
+
+static struct platform_driver imx6sx_pinctrl_driver = {
+ .driver = {
+ .name = "imx6sx-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(imx6sx_pinctrl_of_match),
+ },
+ .probe = imx6sx_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+};
+
+static int __init imx6sx_pinctrl_init(void)
+{
+ return platform_driver_register(&imx6sx_pinctrl_driver);
+}
+arch_initcall(imx6sx_pinctrl_init);
+
+static void __exit imx6sx_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx6sx_pinctrl_driver);
+}
+module_exit(imx6sx_pinctrl_exit);
+
+MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>");
+MODULE_DESCRIPTION("Freescale imx6sx pinctrl driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include "../core.h"
+#include "pinctrl-mxs.h"
+
+#define SUFFIX_LEN 4
+
+struct mxs_pinctrl_data {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ void __iomem *base;
+ struct mxs_pinctrl_soc_data *soc;
+};
+
+static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+ return d->soc->ngroups;
+}
+
+static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned group)
+{
+ struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+ return d->soc->groups[group].name;
+}
+
+static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
+ const unsigned **pins, unsigned *num_pins)
+{
+ struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = d->soc->groups[group].pins;
+ *num_pins = d->soc->groups[group].npins;
+
+ return 0;
+}
+
+static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+ unsigned offset)
+{
+ seq_printf(s, " %s", dev_name(pctldev->dev));
+}
+
+static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map, unsigned *num_maps)
+{
+ struct pinctrl_map *new_map;
+ char *group = NULL;
+ unsigned new_num = 1;
+ unsigned long config = 0;
+ unsigned long *pconfig;
+ int length = strlen(np->name) + SUFFIX_LEN;
+ bool purecfg = false;
+ u32 val, reg;
+ int ret, i = 0;
+
+ /* Check for pin config node which has no 'reg' property */
+ if (of_property_read_u32(np, "reg", ®))
+ purecfg = true;
+
+ ret = of_property_read_u32(np, "fsl,drive-strength", &val);
+ if (!ret)
+ config = val | MA_PRESENT;
+ ret = of_property_read_u32(np, "fsl,voltage", &val);
+ if (!ret)
+ config |= val << VOL_SHIFT | VOL_PRESENT;
+ ret = of_property_read_u32(np, "fsl,pull-up", &val);
+ if (!ret)
+ config |= val << PULL_SHIFT | PULL_PRESENT;
+
+ /* Check for group node which has both mux and config settings */
+ if (!purecfg && config)
+ new_num = 2;
+
+ new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
+ if (!new_map)
+ return -ENOMEM;
+
+ if (!purecfg) {
+ new_map[i].type = PIN_MAP_TYPE_MUX_GROUP;
+ new_map[i].data.mux.function = np->name;
+
+ /* Compose group name */
+ group = kzalloc(length, GFP_KERNEL);
+ if (!group) {
+ ret = -ENOMEM;
+ goto free;
+ }
+ snprintf(group, length, "%s.%d", np->name, reg);
+ new_map[i].data.mux.group = group;
+ i++;
+ }
+
+ if (config) {
+ pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
+ if (!pconfig) {
+ ret = -ENOMEM;
+ goto free_group;
+ }
+
+ new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+ new_map[i].data.configs.group_or_pin = purecfg ? np->name :
+ group;
+ new_map[i].data.configs.configs = pconfig;
+ new_map[i].data.configs.num_configs = 1;
+ }
+
+ *map = new_map;
+ *num_maps = new_num;
+
+ return 0;
+
+free_group:
+ if (!purecfg)
+ kfree(group);
+free:
+ kfree(new_map);
+ return ret;
+}
+
+static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned num_maps)
+{
+ u32 i;
+
+ for (i = 0; i < num_maps; i++) {
+ if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
+ kfree(map[i].data.mux.group);
+ if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
+ kfree(map[i].data.configs.configs);
+ }
+
+ kfree(map);
+}
+
+static const struct pinctrl_ops mxs_pinctrl_ops = {
+ .get_groups_count = mxs_get_groups_count,
+ .get_group_name = mxs_get_group_name,
+ .get_group_pins = mxs_get_group_pins,
+ .pin_dbg_show = mxs_pin_dbg_show,
+ .dt_node_to_map = mxs_dt_node_to_map,
+ .dt_free_map = mxs_dt_free_map,
+};
+
+static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+ return d->soc->nfunctions;
+}
+
+static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned function)
+{
+ struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+ return d->soc->functions[function].name;
+}
+
+static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
+ unsigned group,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = d->soc->functions[group].groups;
+ *num_groups = d->soc->functions[group].ngroups;
+
+ return 0;
+}
+
+static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
+{
+ struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+ struct mxs_group *g = &d->soc->groups[group];
+ void __iomem *reg;
+ u8 bank, shift;
+ u16 pin;
+ u32 i;
+
+ for (i = 0; i < g->npins; i++) {
+ bank = PINID_TO_BANK(g->pins[i]);
+ pin = PINID_TO_PIN(g->pins[i]);
+ reg = d->base + d->soc->regs->muxsel;
+ reg += bank * 0x20 + pin / 16 * 0x10;
+ shift = pin % 16 * 2;
+
+ writel(0x3 << shift, reg + CLR);
+ writel(g->muxsel[i] << shift, reg + SET);
+ }
+
+ return 0;
+}
+
+static const struct pinmux_ops mxs_pinmux_ops = {
+ .get_functions_count = mxs_pinctrl_get_funcs_count,
+ .get_function_name = mxs_pinctrl_get_func_name,
+ .get_function_groups = mxs_pinctrl_get_func_groups,
+ .set_mux = mxs_pinctrl_set_mux,
+};
+
+static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin, unsigned long *config)
+{
+ return -ENOTSUPP;
+}
+
+static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin, unsigned long *configs,
+ unsigned num_configs)
+{
+ return -ENOTSUPP;
+}
+
+static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned group, unsigned long *config)
+{
+ struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+ *config = d->soc->groups[group].config;
+
+ return 0;
+}
+
+static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
+ unsigned group, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+ struct mxs_group *g = &d->soc->groups[group];
+ void __iomem *reg;
+ u8 ma, vol, pull, bank, shift;
+ u16 pin;
+ u32 i;
+ int n;
+ unsigned long config;
+
+ for (n = 0; n < num_configs; n++) {
+ config = configs[n];
+
+ ma = CONFIG_TO_MA(config);
+ vol = CONFIG_TO_VOL(config);
+ pull = CONFIG_TO_PULL(config);
+
+ for (i = 0; i < g->npins; i++) {
+ bank = PINID_TO_BANK(g->pins[i]);
+ pin = PINID_TO_PIN(g->pins[i]);
+
+ /* drive */
+ reg = d->base + d->soc->regs->drive;
+ reg += bank * 0x40 + pin / 8 * 0x10;
+
+ /* mA */
+ if (config & MA_PRESENT) {
+ shift = pin % 8 * 4;
+ writel(0x3 << shift, reg + CLR);
+ writel(ma << shift, reg + SET);
+ }
+
+ /* vol */
+ if (config & VOL_PRESENT) {
+ shift = pin % 8 * 4 + 2;
+ if (vol)
+ writel(1 << shift, reg + SET);
+ else
+ writel(1 << shift, reg + CLR);
+ }
+
+ /* pull */
+ if (config & PULL_PRESENT) {
+ reg = d->base + d->soc->regs->pull;
+ reg += bank * 0x10;
+ shift = pin;
+ if (pull)
+ writel(1 << shift, reg + SET);
+ else
+ writel(1 << shift, reg + CLR);
+ }
+ }
+
+ /* cache the config value for mxs_pinconf_group_get() */
+ g->config = config;
+
+ } /* for each config */
+
+ return 0;
+}
+
+static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned pin)
+{
+ /* Not support */
+}
+
+static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned group)
+{
+ unsigned long config;
+
+ if (!mxs_pinconf_group_get(pctldev, group, &config))
+ seq_printf(s, "0x%lx", config);
+}
+
+static const struct pinconf_ops mxs_pinconf_ops = {
+ .pin_config_get = mxs_pinconf_get,
+ .pin_config_set = mxs_pinconf_set,
+ .pin_config_group_get = mxs_pinconf_group_get,
+ .pin_config_group_set = mxs_pinconf_group_set,
+ .pin_config_dbg_show = mxs_pinconf_dbg_show,
+ .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc mxs_pinctrl_desc = {
+ .pctlops = &mxs_pinctrl_ops,
+ .pmxops = &mxs_pinmux_ops,
+ .confops = &mxs_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static int mxs_pinctrl_parse_group(struct platform_device *pdev,
+ struct device_node *np, int idx,
+ const char **out_name)
+{
+ struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
+ struct mxs_group *g = &d->soc->groups[idx];
+ struct property *prop;
+ const char *propname = "fsl,pinmux-ids";
+ char *group;
+ int length = strlen(np->name) + SUFFIX_LEN;
+ u32 val, i;
+
+ group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
+ if (!group)
+ return -ENOMEM;
+ if (of_property_read_u32(np, "reg", &val))
+ snprintf(group, length, "%s", np->name);
+ else
+ snprintf(group, length, "%s.%d", np->name, val);
+ g->name = group;
+
+ prop = of_find_property(np, propname, &length);
+ if (!prop)
+ return -EINVAL;
+ g->npins = length / sizeof(u32);
+
+ g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
+ GFP_KERNEL);
+ if (!g->pins)
+ return -ENOMEM;
+
+ g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
+ GFP_KERNEL);
+ if (!g->muxsel)
+ return -ENOMEM;
+
+ of_property_read_u32_array(np, propname, g->pins, g->npins);
+ for (i = 0; i < g->npins; i++) {
+ g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
+ g->pins[i] = MUXID_TO_PINID(g->pins[i]);
+ }
+
+ if (out_name)
+ *out_name = g->name;
+
+ return 0;
+}
+
+static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
+ struct mxs_pinctrl_data *d)
+{
+ struct mxs_pinctrl_soc_data *soc = d->soc;
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *child;
+ struct mxs_function *f;
+ const char *gpio_compat = "fsl,mxs-gpio";
+ const char *fn, *fnull = "";
+ int i = 0, idxf = 0, idxg = 0;
+ int ret;
+ u32 val;
+
+ child = of_get_next_child(np, NULL);
+ if (!child) {
+ dev_err(&pdev->dev, "no group is defined\n");
+ return -ENOENT;
+ }
+
+ /* Count total functions and groups */
+ fn = fnull;
+ for_each_child_of_node(np, child) {
+ if (of_device_is_compatible(child, gpio_compat))
+ continue;
+ soc->ngroups++;
+ /* Skip pure pinconf node */
+ if (of_property_read_u32(child, "reg", &val))
+ continue;
+ if (strcmp(fn, child->name)) {
+ fn = child->name;
+ soc->nfunctions++;
+ }
+ }
+
+ soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
+ sizeof(*soc->functions), GFP_KERNEL);
+ if (!soc->functions)
+ return -ENOMEM;
+
+ soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
+ sizeof(*soc->groups), GFP_KERNEL);
+ if (!soc->groups)
+ return -ENOMEM;
+
+ /* Count groups for each function */
+ fn = fnull;
+ f = &soc->functions[idxf];
+ for_each_child_of_node(np, child) {
+ if (of_device_is_compatible(child, gpio_compat))
+ continue;
+ if (of_property_read_u32(child, "reg", &val))
+ continue;
+ if (strcmp(fn, child->name)) {
+ f = &soc->functions[idxf++];
+ f->name = fn = child->name;
+ }
+ f->ngroups++;
+ };
+
+ /* Get groups for each function */
+ idxf = 0;
+ fn = fnull;
+ for_each_child_of_node(np, child) {
+ if (of_device_is_compatible(child, gpio_compat))
+ continue;
+ if (of_property_read_u32(child, "reg", &val)) {
+ ret = mxs_pinctrl_parse_group(pdev, child,
+ idxg++, NULL);
+ if (ret)
+ return ret;
+ continue;
+ }
+
+ if (strcmp(fn, child->name)) {
+ f = &soc->functions[idxf++];
+ f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
+ sizeof(*f->groups),
+ GFP_KERNEL);
+ if (!f->groups)
+ return -ENOMEM;
+ fn = child->name;
+ i = 0;
+ }
+ ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
+ &f->groups[i++]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int mxs_pinctrl_probe(struct platform_device *pdev,
+ struct mxs_pinctrl_soc_data *soc)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct mxs_pinctrl_data *d;
+ int ret;
+
+ d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
+ if (!d)
+ return -ENOMEM;
+
+ d->dev = &pdev->dev;
+ d->soc = soc;
+
+ d->base = of_iomap(np, 0);
+ if (!d->base)
+ return -EADDRNOTAVAIL;
+
+ mxs_pinctrl_desc.pins = d->soc->pins;
+ mxs_pinctrl_desc.npins = d->soc->npins;
+ mxs_pinctrl_desc.name = dev_name(&pdev->dev);
+
+ platform_set_drvdata(pdev, d);
+
+ ret = mxs_pinctrl_probe_dt(pdev, d);
+ if (ret) {
+ dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
+ goto err;
+ }
+
+ d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
+ if (!d->pctl) {
+ dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ return 0;
+
+err:
+ iounmap(d->base);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
+
+int mxs_pinctrl_remove(struct platform_device *pdev)
+{
+ struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(d->pctl);
+ iounmap(d->base);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __PINCTRL_MXS_H
+#define __PINCTRL_MXS_H
+
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#define SET 0x4
+#define CLR 0x8
+#define TOG 0xc
+
+#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+#define PINID(bank, pin) ((bank) * 32 + (pin))
+
+/*
+ * pinmux-id bit field definitions
+ *
+ * bank: 15..12 (4)
+ * pin: 11..4 (8)
+ * muxsel: 3..0 (4)
+ */
+#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
+#define MUXID_TO_MUXSEL(m) ((m) & 0xf)
+
+#define PINID_TO_BANK(p) ((p) >> 5)
+#define PINID_TO_PIN(p) ((p) % 32)
+
+/*
+ * pin config bit field definitions
+ *
+ * pull-up: 6..5 (2)
+ * voltage: 4..3 (2)
+ * mA: 2..0 (3)
+ *
+ * MSB of each field is presence bit for the config.
+ */
+#define PULL_PRESENT (1 << 6)
+#define PULL_SHIFT 5
+#define VOL_PRESENT (1 << 4)
+#define VOL_SHIFT 3
+#define MA_PRESENT (1 << 2)
+#define MA_SHIFT 0
+#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
+#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
+#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
+
+struct mxs_function {
+ const char *name;
+ const char **groups;
+ unsigned ngroups;
+};
+
+struct mxs_group {
+ const char *name;
+ unsigned int *pins;
+ unsigned npins;
+ u8 *muxsel;
+ u8 config;
+};
+
+struct mxs_regs {
+ u16 muxsel;
+ u16 drive;
+ u16 pull;
+};
+
+struct mxs_pinctrl_soc_data {
+ const struct mxs_regs *regs;
+ const struct pinctrl_pin_desc *pins;
+ unsigned npins;
+ struct mxs_function *functions;
+ unsigned nfunctions;
+ struct mxs_group *groups;
+ unsigned ngroups;
+};
+
+int mxs_pinctrl_probe(struct platform_device *pdev,
+ struct mxs_pinctrl_soc_data *soc);
+int mxs_pinctrl_remove(struct platform_device *pdev);
+
+#endif /* __PINCTRL_MXS_H */
--- /dev/null
+/*
+ * VF610 pinctrl driver based on imx pinmux and pinconf core
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum vf610_pads {
+ VF610_PAD_PTA6 = 0,
+ VF610_PAD_PTA8 = 1,
+ VF610_PAD_PTA9 = 2,
+ VF610_PAD_PTA10 = 3,
+ VF610_PAD_PTA11 = 4,
+ VF610_PAD_PTA12 = 5,
+ VF610_PAD_PTA16 = 6,
+ VF610_PAD_PTA17 = 7,
+ VF610_PAD_PTA18 = 8,
+ VF610_PAD_PTA19 = 9,
+ VF610_PAD_PTA20 = 10,
+ VF610_PAD_PTA21 = 11,
+ VF610_PAD_PTA22 = 12,
+ VF610_PAD_PTA23 = 13,
+ VF610_PAD_PTA24 = 14,
+ VF610_PAD_PTA25 = 15,
+ VF610_PAD_PTA26 = 16,
+ VF610_PAD_PTA27 = 17,
+ VF610_PAD_PTA28 = 18,
+ VF610_PAD_PTA29 = 19,
+ VF610_PAD_PTA30 = 20,
+ VF610_PAD_PTA31 = 21,
+ VF610_PAD_PTB0 = 22,
+ VF610_PAD_PTB1 = 23,
+ VF610_PAD_PTB2 = 24,
+ VF610_PAD_PTB3 = 25,
+ VF610_PAD_PTB4 = 26,
+ VF610_PAD_PTB5 = 27,
+ VF610_PAD_PTB6 = 28,
+ VF610_PAD_PTB7 = 29,
+ VF610_PAD_PTB8 = 30,
+ VF610_PAD_PTB9 = 31,
+ VF610_PAD_PTB10 = 32,
+ VF610_PAD_PTB11 = 33,
+ VF610_PAD_PTB12 = 34,
+ VF610_PAD_PTB13 = 35,
+ VF610_PAD_PTB14 = 36,
+ VF610_PAD_PTB15 = 37,
+ VF610_PAD_PTB16 = 38,
+ VF610_PAD_PTB17 = 39,
+ VF610_PAD_PTB18 = 40,
+ VF610_PAD_PTB19 = 41,
+ VF610_PAD_PTB20 = 42,
+ VF610_PAD_PTB21 = 43,
+ VF610_PAD_PTB22 = 44,
+ VF610_PAD_PTC0 = 45,
+ VF610_PAD_PTC1 = 46,
+ VF610_PAD_PTC2 = 47,
+ VF610_PAD_PTC3 = 48,
+ VF610_PAD_PTC4 = 49,
+ VF610_PAD_PTC5 = 50,
+ VF610_PAD_PTC6 = 51,
+ VF610_PAD_PTC7 = 52,
+ VF610_PAD_PTC8 = 53,
+ VF610_PAD_PTC9 = 54,
+ VF610_PAD_PTC10 = 55,
+ VF610_PAD_PTC11 = 56,
+ VF610_PAD_PTC12 = 57,
+ VF610_PAD_PTC13 = 58,
+ VF610_PAD_PTC14 = 59,
+ VF610_PAD_PTC15 = 60,
+ VF610_PAD_PTC16 = 61,
+ VF610_PAD_PTC17 = 62,
+ VF610_PAD_PTD31 = 63,
+ VF610_PAD_PTD30 = 64,
+ VF610_PAD_PTD29 = 65,
+ VF610_PAD_PTD28 = 66,
+ VF610_PAD_PTD27 = 67,
+ VF610_PAD_PTD26 = 68,
+ VF610_PAD_PTD25 = 69,
+ VF610_PAD_PTD24 = 70,
+ VF610_PAD_PTD23 = 71,
+ VF610_PAD_PTD22 = 72,
+ VF610_PAD_PTD21 = 73,
+ VF610_PAD_PTD20 = 74,
+ VF610_PAD_PTD19 = 75,
+ VF610_PAD_PTD18 = 76,
+ VF610_PAD_PTD17 = 77,
+ VF610_PAD_PTD16 = 78,
+ VF610_PAD_PTD0 = 79,
+ VF610_PAD_PTD1 = 80,
+ VF610_PAD_PTD2 = 81,
+ VF610_PAD_PTD3 = 82,
+ VF610_PAD_PTD4 = 83,
+ VF610_PAD_PTD5 = 84,
+ VF610_PAD_PTD6 = 85,
+ VF610_PAD_PTD7 = 86,
+ VF610_PAD_PTD8 = 87,
+ VF610_PAD_PTD9 = 88,
+ VF610_PAD_PTD10 = 89,
+ VF610_PAD_PTD11 = 90,
+ VF610_PAD_PTD12 = 91,
+ VF610_PAD_PTD13 = 92,
+ VF610_PAD_PTB23 = 93,
+ VF610_PAD_PTB24 = 94,
+ VF610_PAD_PTB25 = 95,
+ VF610_PAD_PTB26 = 96,
+ VF610_PAD_PTB27 = 97,
+ VF610_PAD_PTB28 = 98,
+ VF610_PAD_PTC26 = 99,
+ VF610_PAD_PTC27 = 100,
+ VF610_PAD_PTC28 = 101,
+ VF610_PAD_PTC29 = 102,
+ VF610_PAD_PTC30 = 103,
+ VF610_PAD_PTC31 = 104,
+ VF610_PAD_PTE0 = 105,
+ VF610_PAD_PTE1 = 106,
+ VF610_PAD_PTE2 = 107,
+ VF610_PAD_PTE3 = 108,
+ VF610_PAD_PTE4 = 109,
+ VF610_PAD_PTE5 = 110,
+ VF610_PAD_PTE6 = 111,
+ VF610_PAD_PTE7 = 112,
+ VF610_PAD_PTE8 = 113,
+ VF610_PAD_PTE9 = 114,
+ VF610_PAD_PTE10 = 115,
+ VF610_PAD_PTE11 = 116,
+ VF610_PAD_PTE12 = 117,
+ VF610_PAD_PTE13 = 118,
+ VF610_PAD_PTE14 = 119,
+ VF610_PAD_PTE15 = 120,
+ VF610_PAD_PTE16 = 121,
+ VF610_PAD_PTE17 = 122,
+ VF610_PAD_PTE18 = 123,
+ VF610_PAD_PTE19 = 124,
+ VF610_PAD_PTE20 = 125,
+ VF610_PAD_PTE21 = 126,
+ VF610_PAD_PTE22 = 127,
+ VF610_PAD_PTE23 = 128,
+ VF610_PAD_PTE24 = 129,
+ VF610_PAD_PTE25 = 130,
+ VF610_PAD_PTE26 = 131,
+ VF610_PAD_PTE27 = 132,
+ VF610_PAD_PTE28 = 133,
+ VF610_PAD_PTA7 = 134,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(VF610_PAD_PTA6),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA8),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA9),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA10),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA11),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA12),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA16),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA17),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA18),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA19),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA20),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA21),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA22),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA23),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA24),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA25),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA26),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA27),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA28),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA29),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA30),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA31),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB0),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB1),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB2),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB3),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB4),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB5),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB6),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB7),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB8),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB9),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB10),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB11),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB12),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB13),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB14),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB15),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB16),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB17),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB18),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB19),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB20),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB21),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB22),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC0),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC1),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC2),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC3),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC4),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC5),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC6),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC7),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC8),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC9),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC10),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC11),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC12),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC13),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC14),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC15),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC16),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC17),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD31),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD30),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD29),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD28),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD27),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD26),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD25),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD24),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD23),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD22),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD21),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD20),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD19),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD18),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD17),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD16),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD0),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD1),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD2),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD3),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD4),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD5),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD6),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD7),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD8),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD9),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD10),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD11),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD12),
+ IMX_PINCTRL_PIN(VF610_PAD_PTD13),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB23),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB24),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB25),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB26),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB27),
+ IMX_PINCTRL_PIN(VF610_PAD_PTB28),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC26),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC27),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC28),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC29),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC30),
+ IMX_PINCTRL_PIN(VF610_PAD_PTC31),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE0),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE1),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE2),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE3),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE4),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE5),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE6),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE7),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE8),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE9),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE10),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE11),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE12),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE13),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE14),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE15),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE16),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE17),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE18),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE19),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE20),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE21),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE22),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE23),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE24),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE25),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE26),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE27),
+ IMX_PINCTRL_PIN(VF610_PAD_PTE28),
+ IMX_PINCTRL_PIN(VF610_PAD_PTA7),
+};
+
+static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
+ .pins = vf610_pinctrl_pads,
+ .npins = ARRAY_SIZE(vf610_pinctrl_pads),
+ .flags = SHARE_MUX_CONF_REG,
+};
+
+static struct of_device_id vf610_pinctrl_of_match[] = {
+ { .compatible = "fsl,vf610-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int vf610_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &vf610_pinctrl_info);
+}
+
+static struct platform_driver vf610_pinctrl_driver = {
+ .driver = {
+ .name = "vf610-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = vf610_pinctrl_of_match,
+ },
+ .probe = vf610_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+};
+
+static int __init vf610_pinctrl_init(void)
+{
+ return platform_driver_register(&vf610_pinctrl_driver);
+}
+arch_initcall(vf610_pinctrl_init);
+
+static void __exit vf610_pinctrl_exit(void)
+{
+ platform_driver_unregister(&vf610_pinctrl_driver);
+}
+module_exit(vf610_pinctrl_exit);
+
+MODULE_DESCRIPTION("Freescale VF610 pinctrl driver");
+MODULE_LICENSE("GPL v2");
return 0;
}
-static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid,
- unsigned gid)
+static int mvebu_pinmux_set(struct pinctrl_dev *pctldev, unsigned fid,
+ unsigned gid)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct mvebu_pinctrl_function *func = &pctl->functions[fid];
.get_function_groups = mvebu_pinmux_get_groups,
.gpio_request_enable = mvebu_pinmux_gpio_request_enable,
.gpio_set_direction = mvebu_pinmux_gpio_set_direction,
- .enable = mvebu_pinmux_enable,
+ .set_mux = mvebu_pinmux_set,
};
static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
#include "pinctrl-abx500.h"
#include "../core.h"
#include "../pinconf.h"
+#include "../pinctrl-utils.h"
/*
* The AB9540 and AB8540 GPIO support are extended versions
return 0;
}
-static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
- unsigned group)
+static int abx500_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
+ unsigned group)
{
struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
struct gpio_chip *chip = &pct->chip;
.get_functions_count = abx500_pmx_get_funcs_cnt,
.get_function_name = abx500_pmx_get_func_name,
.get_function_groups = abx500_pmx_get_func_groups,
- .enable = abx500_pmx_enable,
+ .set_mux = abx500_pmx_set,
.gpio_request_enable = abx500_gpio_request_enable,
.gpio_disable_free = abx500_gpio_disable_free,
};
chip->base + offset - 1);
}
-static void abx500_dt_free_map(struct pinctrl_dev *pctldev,
- struct pinctrl_map *map, unsigned num_maps)
-{
- int i;
-
- for (i = 0; i < num_maps; i++)
- if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
- kfree(map[i].data.configs.configs);
- kfree(map);
-}
-
-static int abx500_dt_reserve_map(struct pinctrl_map **map,
- unsigned *reserved_maps,
- unsigned *num_maps,
- unsigned reserve)
-{
- unsigned old_num = *reserved_maps;
- unsigned new_num = *num_maps + reserve;
- struct pinctrl_map *new_map;
-
- if (old_num >= new_num)
- return 0;
-
- new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
- if (!new_map)
- return -ENOMEM;
-
- memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
-
- *map = new_map;
- *reserved_maps = new_num;
-
- return 0;
-}
-
static int abx500_dt_add_map_mux(struct pinctrl_map **map,
unsigned *reserved_maps,
unsigned *num_maps, const char *group,
unsigned long *configs;
unsigned int nconfigs = 0;
bool has_config = 0;
- unsigned reserve = 0;
struct property *prop;
const char *group, *gpio_name;
struct device_node *np_config;
ret = of_property_read_string(np, "ste,function", &function);
- if (ret >= 0)
- reserve = 1;
+ if (ret >= 0) {
+ ret = of_property_count_strings(np, "ste,pins");
+ if (ret < 0)
+ goto exit;
+
+ ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
+ num_maps, ret);
+ if (ret < 0)
+ goto exit;
+
+ of_property_for_each_string(np, "ste,pins", prop, group) {
+ ret = abx500_dt_add_map_mux(map, reserved_maps,
+ num_maps, group, function);
+ if (ret < 0)
+ goto exit;
+ }
+ }
ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs);
if (nconfigs)
has_config = 1;
-
np_config = of_parse_phandle(np, "ste,config", 0);
if (np_config) {
ret = pinconf_generic_parse_dt_config(np_config, &configs,
goto exit;
has_config |= nconfigs;
}
+ if (has_config) {
+ ret = of_property_count_strings(np, "ste,pins");
+ if (ret < 0)
+ goto exit;
- ret = of_property_count_strings(np, "ste,pins");
- if (ret < 0)
- goto exit;
-
- if (has_config)
- reserve++;
-
- reserve *= ret;
-
- ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve);
- if (ret < 0)
- goto exit;
+ ret = pinctrl_utils_reserve_map(pctldev, map,
+ reserved_maps,
+ num_maps, ret);
+ if (ret < 0)
+ goto exit;
- of_property_for_each_string(np, "ste,pins", prop, group) {
- if (function) {
- ret = abx500_dt_add_map_mux(map, reserved_maps,
- num_maps, group, function);
- if (ret < 0)
- goto exit;
- }
- if (has_config) {
+ of_property_for_each_string(np, "ste,pins", prop, group) {
gpio_name = abx500_find_pin_name(pctldev, group);
ret = abx500_dt_add_map_configs(map, reserved_maps,
if (ret < 0)
goto exit;
}
-
}
+
exit:
return ret;
}
ret = abx500_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
- abx500_dt_free_map(pctldev, *map, *num_maps);
+ pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
return ret;
}
}
.get_group_pins = abx500_get_group_pins,
.pin_dbg_show = abx500_pin_dbg_show,
.dt_node_to_map = abx500_dt_node_to_map,
- .dt_free_map = abx500_dt_free_map,
+ .dt_free_map = pinctrl_utils_dt_free_map,
};
static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
#include <linux/pinctrl/consumer.h>
#include "pinctrl-nomadik.h"
#include "../core.h"
+#include "../pinctrl-utils.h"
/*
* The GPIO module in the Nomadik family of Systems-on-Chip is an
container_of(chip, struct nmk_gpio_chip, chip);
int mode;
bool is_out;
+ bool data_out;
bool pull;
u32 bit = 1 << offset;
const char *modes[] = {
[NMK_GPIO_ALT_C+3] = "altC3",
[NMK_GPIO_ALT_C+4] = "altC4",
};
+ const char *pulls[] = {
+ "none ",
+ "pull down",
+ "pull up ",
+ };
clk_enable(nmk_chip->clk);
is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
+ data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & bit);
mode = nmk_gpio_get_mode(gpio);
if ((mode == NMK_GPIO_ALT_C) && pctldev)
mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
- seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
- gpio, label ?: "(none)",
- is_out ? "out" : "in ",
- chip->get
- ? (chip->get(chip, offset) ? "hi" : "lo")
- : "? ",
- (mode < 0) ? "unknown" : modes[mode],
- pull ? "pull" : "none");
-
- if (!is_out) {
+ if (is_out) {
+ seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
+ gpio,
+ label ?: "(none)",
+ data_out ? "hi" : "lo",
+ (mode < 0) ? "unknown" : modes[mode]);
+ } else {
int irq = gpio_to_irq(gpio);
struct irq_desc *desc = irq_to_desc(irq);
+ int pullidx = 0;
- /* This races with request_irq(), set_irq_type(),
+ if (pull)
+ pullidx = data_out ? 1 : 2;
+
+ seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
+ gpio,
+ label ?: "(none)",
+ pulls[pullidx],
+ (mode < 0) ? "unknown" : modes[mode]);
+ /*
+ * This races with request_irq(), set_irq_type(),
* and set_irq_wake() ... but those are "rare".
*/
if (irq > 0 && desc && desc->action) {
nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
}
-static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
- struct pinctrl_map *map, unsigned num_maps)
-{
- int i;
-
- for (i = 0; i < num_maps; i++)
- if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
- kfree(map[i].data.configs.configs);
- kfree(map);
-}
-
-static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
- unsigned *num_maps, unsigned reserve)
-{
- unsigned old_num = *reserved_maps;
- unsigned new_num = *num_maps + reserve;
- struct pinctrl_map *new_map;
-
- if (old_num >= new_num)
- return 0;
-
- new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
- if (!new_map)
- return -ENOMEM;
-
- memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
-
- *map = new_map;
- *reserved_maps = new_num;
-
- return 0;
-}
-
static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps, const char *group,
const char *function)
const char *function = NULL;
unsigned long configs = 0;
bool has_config = 0;
- unsigned reserve = 0;
struct property *prop;
const char *group, *gpio_name;
struct device_node *np_config;
ret = of_property_read_string(np, "ste,function", &function);
- if (ret >= 0)
- reserve = 1;
-
- has_config = nmk_pinctrl_dt_get_config(np, &configs);
-
- np_config = of_parse_phandle(np, "ste,config", 0);
- if (np_config)
- has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
-
- ret = of_property_count_strings(np, "ste,pins");
- if (ret < 0)
- goto exit;
-
- if (has_config)
- reserve++;
-
- reserve *= ret;
-
- ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
- if (ret < 0)
- goto exit;
-
- of_property_for_each_string(np, "ste,pins", prop, group) {
- if (function) {
+ if (ret >= 0) {
+ ret = of_property_count_strings(np, "ste,pins");
+ if (ret < 0)
+ goto exit;
+
+ ret = pinctrl_utils_reserve_map(pctldev, map,
+ reserved_maps,
+ num_maps, ret);
+ if (ret < 0)
+ goto exit;
+
+ of_property_for_each_string(np, "ste,pins", prop, group) {
ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
group, function);
if (ret < 0)
goto exit;
}
- if (has_config) {
+ }
+
+ has_config = nmk_pinctrl_dt_get_config(np, &configs);
+ np_config = of_parse_phandle(np, "ste,config", 0);
+ if (np_config)
+ has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
+ if (has_config) {
+ ret = of_property_count_strings(np, "ste,pins");
+ if (ret < 0)
+ goto exit;
+ ret = pinctrl_utils_reserve_map(pctldev, map,
+ reserved_maps,
+ num_maps, ret);
+ if (ret < 0)
+ goto exit;
+
+ of_property_for_each_string(np, "ste,pins", prop, group) {
gpio_name = nmk_find_pin_name(pctldev, group);
- ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps,
- gpio_name, &configs, 1);
+ ret = nmk_dt_add_map_configs(map, reserved_maps,
+ num_maps,
+ gpio_name, &configs, 1);
if (ret < 0)
goto exit;
}
-
}
+
exit:
return ret;
}
ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
- nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps);
+ pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
return ret;
}
}
.get_group_pins = nmk_get_group_pins,
.pin_dbg_show = nmk_pin_dbg_show,
.dt_node_to_map = nmk_pinctrl_dt_node_to_map,
- .dt_free_map = nmk_pinctrl_dt_free_map,
+ .dt_free_map = pinctrl_utils_dt_free_map,
};
static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
return 0;
}
-static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
- unsigned group)
+static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
+ unsigned group)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
const struct nmk_pingroup *g;
.get_functions_count = nmk_pmx_get_funcs_cnt,
.get_function_name = nmk_pmx_get_func_name,
.get_function_groups = nmk_pmx_get_func_groups,
- .enable = nmk_pmx_enable,
+ .set_mux = nmk_pmx_set,
.gpio_request_enable = nmk_gpio_request_enable,
.gpio_disable_free = nmk_gpio_disable_free,
};
.get_group_pins = adi_get_group_pins,
};
-static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id,
- unsigned group_id)
+static int adi_pinmux_set(struct pinctrl_dev *pctldev, unsigned func_id,
+ unsigned group_id)
{
struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
struct gpio_port *port;
}
static struct pinmux_ops adi_pinmux_ops = {
- .enable = adi_pinmux_enable,
+ .set_mux = adi_pinmux_set,
.get_functions_count = adi_pinmux_get_funcs_count,
.get_function_name = adi_pinmux_get_func_name,
.get_function_groups = adi_pinmux_get_groups,
u8 offset;
list_del(&port->node);
- gpiochip_remove_pin_ranges(&port->chip);
gpiochip_remove(&port->chip);
if (port->pint) {
for (offset = 0; offset < port->width; offset++)
return 0;
}
-static int as3722_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
+static int as3722_pinctrl_set(struct pinctrl_dev *pctldev, unsigned function,
unsigned group)
{
struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
.get_functions_count = as3722_pinctrl_get_funcs_count,
.get_function_name = as3722_pinctrl_get_func_name,
.get_function_groups = as3722_pinctrl_get_func_groups,
- .enable = as3722_pinctrl_enable,
+ .set_mux = as3722_pinctrl_set,
.gpio_request_enable = as3722_pinctrl_gpio_request_enable,
.gpio_set_direction = as3722_pinctrl_gpio_set_direction,
};
#define DEGLITCH (1 << 2)
#define PULL_DOWN (1 << 3)
#define DIS_SCHMIT (1 << 4)
+#define DRIVE_STRENGTH_SHIFT 5
+#define DRIVE_STRENGTH_MASK 0x3
+#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
#define DEBOUNCE (1 << 16)
#define DEBOUNCE_VAL_SHIFT 17
#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
+/**
+ * These defines will translated the dt binding settings to our internal
+ * settings. They are not necessarily the same value as the register setting.
+ * The actual drive strength current of low, medium and high must be looked up
+ * from the corresponding device datasheet. This value is different for pins
+ * that are even in the same banks. It is also dependent on VCC.
+ * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
+ * strength when there is no dt config for it.
+ */
+#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
+#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
+#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
+#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
+
/**
* struct at91_pmx_func - describes AT91 pinmux functions
* @name: the name of this specific function
void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
+ unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
+ void (*set_drivestrength)(void __iomem *pio, unsigned pin,
+ u32 strength);
/* irq */
int (*irq_type)(struct irq_data *d, unsigned type);
};
return 1 << pin;
}
+static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
+{
+ /* return the shift value for a pin for "two bit" per pin registers,
+ * i.e. drive strength */
+ return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
+ ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
+}
+
+static unsigned sama5d3_get_drive_register(unsigned int pin)
+{
+ /* drive strength is split between two registers
+ * with two bits per pin */
+ return (pin >= MAX_NB_GPIO_PER_BANK/2)
+ ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
+}
+
+static unsigned at91sam9x5_get_drive_register(unsigned int pin)
+{
+ /* drive strength is split between two registers
+ * with two bits per pin */
+ return (pin >= MAX_NB_GPIO_PER_BANK/2)
+ ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
+}
+
static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
{
writel_relaxed(mask, pio + PIO_IDR);
static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
{
+ if (on)
+ writel_relaxed(mask, pio + PIO_PPDDR);
+
writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
}
static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
{
+ if (is_on)
+ __raw_writel(mask, pio + PIO_PUDR);
+
__raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
}
return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
}
+static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
+{
+ unsigned tmp = __raw_readl(reg);
+
+ tmp = tmp >> two_bit_pin_value_shift_amount(pin);
+
+ return tmp & DRIVE_STRENGTH_MASK;
+}
+
+static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
+ unsigned pin)
+{
+ unsigned tmp = read_drive_strength(pio +
+ sama5d3_get_drive_register(pin), pin);
+
+ /* SAMA5 strength is 1:1 with our defines,
+ * except 0 is equivalent to low per datasheet */
+ if (!tmp)
+ tmp = DRIVE_STRENGTH_LOW;
+
+ return tmp;
+}
+
+static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
+ unsigned pin)
+{
+ unsigned tmp = read_drive_strength(pio +
+ at91sam9x5_get_drive_register(pin), pin);
+
+ /* strength is inverse in SAM9x5s hardware with the pinctrl defines
+ * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
+ tmp = DRIVE_STRENGTH_HI - tmp;
+
+ return tmp;
+}
+
+static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
+{
+ unsigned tmp = __raw_readl(reg);
+ unsigned shift = two_bit_pin_value_shift_amount(pin);
+
+ tmp &= ~(DRIVE_STRENGTH_MASK << shift);
+ tmp |= strength << shift;
+
+ __raw_writel(tmp, reg);
+}
+
+static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
+ u32 setting)
+{
+ /* do nothing if setting is zero */
+ if (!setting)
+ return;
+
+ /* strength is 1 to 1 with setting for SAMA5 */
+ set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
+}
+
+static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
+ u32 setting)
+{
+ /* do nothing if setting is zero */
+ if (!setting)
+ return;
+
+ /* strength is inverse on SAM9x5s with our defines
+ * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
+ setting = DRIVE_STRENGTH_HI - setting;
+
+ set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
+ setting);
+}
+
static struct at91_pinctrl_mux_ops at91rm9200_ops = {
.get_periph = at91_mux_get_periph,
.mux_A_periph = at91_mux_set_A_periph,
.set_pulldown = at91_mux_pio3_set_pulldown,
.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
+ .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
+ .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
+ .irq_type = alt_gpio_irq_type,
+};
+
+static struct at91_pinctrl_mux_ops sama5d3_ops = {
+ .get_periph = at91_mux_pio3_get_periph,
+ .mux_A_periph = at91_mux_pio3_set_A_periph,
+ .mux_B_periph = at91_mux_pio3_set_B_periph,
+ .mux_C_periph = at91_mux_pio3_set_C_periph,
+ .mux_D_periph = at91_mux_pio3_set_D_periph,
+ .get_deglitch = at91_mux_pio3_get_deglitch,
+ .set_deglitch = at91_mux_pio3_set_deglitch,
+ .get_debounce = at91_mux_pio3_get_debounce,
+ .set_debounce = at91_mux_pio3_set_debounce,
+ .get_pulldown = at91_mux_pio3_get_pulldown,
+ .set_pulldown = at91_mux_pio3_set_pulldown,
+ .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
+ .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
+ .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
+ .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
.irq_type = alt_gpio_irq_type,
};
writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
}
-static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
- unsigned group)
+static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
{
struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
.get_functions_count = at91_pmx_get_funcs_count,
.get_function_name = at91_pmx_get_func_name,
.get_function_groups = at91_pmx_get_groups,
- .enable = at91_pmx_enable,
+ .set_mux = at91_pmx_set,
.gpio_request_enable = at91_gpio_request_enable,
.gpio_disable_free = at91_gpio_disable_free,
};
*config |= PULL_DOWN;
if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
*config |= DIS_SCHMIT;
+ if (info->ops->get_drivestrength)
+ *config |= (info->ops->get_drivestrength(pio, pin)
+ << DRIVE_STRENGTH_SHIFT);
return 0;
}
void __iomem *pio;
int i;
unsigned long config;
+ unsigned pin;
for (i = 0; i < num_configs; i++) {
config = configs[i];
"%s:%d, pin_id=%d, config=0x%lx",
__func__, __LINE__, pin_id, config);
pio = pin_to_controller(info, pin_to_bank(pin_id));
- mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
+ pin = pin_id % MAX_NB_GPIO_PER_BANK;
+ mask = pin_to_mask(pin);
if (config & PULL_UP && config & PULL_DOWN)
return -EINVAL;
info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
info->ops->disable_schmitt_trig(pio, mask);
+ if (info->ops->set_drivestrength)
+ info->ops->set_drivestrength(pio, pin,
+ (config & DRIVE_STRENGTH)
+ >> DRIVE_STRENGTH_SHIFT);
} /* for each config */
} \
} while (0)
+#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
+ if ((config & mask) == flag) { \
+ if (num_conf) \
+ seq_puts(s, "|"); \
+ seq_puts(s, #flag); \
+ num_conf++; \
+ } \
+} while (0)
+
static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
DBG_SHOW_FLAG(PULL_DOWN);
DBG_SHOW_FLAG(DIS_SCHMIT);
DBG_SHOW_FLAG(DEGLITCH);
+ DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
+ DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
+ DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
DBG_SHOW_FLAG(DEBOUNCE);
if (config & DEBOUNCE) {
val = config >> DEBOUNCE_VAL_SHIFT;
}
static struct of_device_id at91_pinctrl_of_match[] = {
+ { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
{ .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
{ .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
{ /* sentinel */ }
/* now it may re-trigger */
}
-static int at91_gpio_of_irq_setup(struct device_node *node,
+static int at91_gpio_of_irq_setup(struct platform_device *pdev,
struct at91_gpio_chip *at91_gpio)
{
struct at91_gpio_chip *prev = NULL;
0,
handle_edge_irq,
IRQ_TYPE_EDGE_BOTH);
- if (ret)
- panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
+ if (ret) {
+ dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
at91_gpio->pioc_idx);
+ return ret;
+ }
/* Setup chained handler */
if (at91_gpio->pioc_idx)
at91_chip->pioc_virq = irq;
at91_chip->pioc_idx = alias_idx;
- at91_chip->clock = clk_get(&pdev->dev, NULL);
+ at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(at91_chip->clock)) {
dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
+ ret = PTR_ERR(at91_chip->clock);
goto err;
}
- if (clk_prepare(at91_chip->clock))
- goto clk_prep_err;
+ ret = clk_prepare(at91_chip->clock);
+ if (ret)
+ goto clk_prepare_err;
/* enable PIO controller's clock */
- if (clk_enable(at91_chip->clock)) {
+ ret = clk_enable(at91_chip->clock);
+ if (ret) {
dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
- goto clk_err;
+ goto clk_enable_err;
}
at91_chip->chip = at91_gpio_template;
if (!names) {
ret = -ENOMEM;
- goto clk_err;
+ goto clk_enable_err;
}
for (i = 0; i < chip->ngpio; i++)
ret = gpiochip_add(chip);
if (ret)
- goto clk_err;
+ goto gpiochip_add_err;
gpio_chips[alias_idx] = at91_chip;
gpio_banks = max(gpio_banks, alias_idx + 1);
at91_gpio_probe_fixup();
- at91_gpio_of_irq_setup(np, at91_chip);
+ ret = at91_gpio_of_irq_setup(pdev, at91_chip);
+ if (ret)
+ goto irq_setup_err;
dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
return 0;
-clk_err:
+irq_setup_err:
+ gpiochip_remove(chip);
+gpiochip_add_err:
+ clk_disable(at91_chip->clock);
+clk_enable_err:
clk_unprepare(at91_chip->clock);
-clk_prep_err:
- clk_put(at91_chip->clock);
+clk_prepare_err:
err:
dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
return 0;
}
-static int bcm281xx_pinmux_enable(struct pinctrl_dev *pctldev,
- unsigned function,
- unsigned group)
+static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev,
+ unsigned function,
+ unsigned group)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
const struct bcm281xx_pin_function *f = &pdata->functions[function];
.get_functions_count = bcm281xx_pinctrl_get_fcns_count,
.get_function_name = bcm281xx_pinctrl_get_fcn_name,
.get_function_groups = bcm281xx_pinctrl_get_fcn_groups,
- .enable = bcm281xx_pinmux_enable,
+ .set_mux = bcm281xx_pinmux_set,
};
static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,
return 0;
}
-static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev,
+static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
unsigned func_selector,
unsigned group_selector)
{
.get_functions_count = bcm2835_pmx_get_functions_count,
.get_function_name = bcm2835_pmx_get_function_name,
.get_function_groups = bcm2835_pmx_get_function_groups,
- .enable = bcm2835_pmx_enable,
+ .set_mux = bcm2835_pmx_set,
.gpio_disable_free = bcm2835_pmx_gpio_disable_free,
.gpio_set_direction = bcm2835_pmx_gpio_set_direction,
};
+++ /dev/null
-/*
- * Core driver for the imx pin controller
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro Ltd.
- *
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/slab.h>
-
-#include "core.h"
-#include "pinctrl-imx.h"
-
-/* The bits in CONFIG cell defined in binding doc*/
-#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
-#define IMX_PAD_SION 0x40000000 /* set SION */
-
-/**
- * @dev: a pointer back to containing device
- * @base: the offset to the controller in virtual memory
- */
-struct imx_pinctrl {
- struct device *dev;
- struct pinctrl_dev *pctl;
- void __iomem *base;
- const struct imx_pinctrl_soc_info *info;
-};
-
-static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
- const struct imx_pinctrl_soc_info *info,
- const char *name)
-{
- const struct imx_pin_group *grp = NULL;
- int i;
-
- for (i = 0; i < info->ngroups; i++) {
- if (!strcmp(info->groups[i].name, name)) {
- grp = &info->groups[i];
- break;
- }
- }
-
- return grp;
-}
-
-static int imx_get_groups_count(struct pinctrl_dev *pctldev)
-{
- struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pinctrl_soc_info *info = ipctl->info;
-
- return info->ngroups;
-}
-
-static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
- unsigned selector)
-{
- struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pinctrl_soc_info *info = ipctl->info;
-
- return info->groups[selector].name;
-}
-
-static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
- const unsigned **pins,
- unsigned *npins)
-{
- struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pinctrl_soc_info *info = ipctl->info;
-
- if (selector >= info->ngroups)
- return -EINVAL;
-
- *pins = info->groups[selector].pin_ids;
- *npins = info->groups[selector].npins;
-
- return 0;
-}
-
-static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
- unsigned offset)
-{
- seq_printf(s, "%s", dev_name(pctldev->dev));
-}
-
-static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np,
- struct pinctrl_map **map, unsigned *num_maps)
-{
- struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pinctrl_soc_info *info = ipctl->info;
- const struct imx_pin_group *grp;
- struct pinctrl_map *new_map;
- struct device_node *parent;
- int map_num = 1;
- int i, j;
-
- /*
- * first find the group of this node and check if we need create
- * config maps for pins
- */
- grp = imx_pinctrl_find_group_by_name(info, np->name);
- if (!grp) {
- dev_err(info->dev, "unable to find group for node %s\n",
- np->name);
- return -EINVAL;
- }
-
- for (i = 0; i < grp->npins; i++) {
- if (!(grp->pins[i].config & IMX_NO_PAD_CTL))
- map_num++;
- }
-
- new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
- if (!new_map)
- return -ENOMEM;
-
- *map = new_map;
- *num_maps = map_num;
-
- /* create mux map */
- parent = of_get_parent(np);
- if (!parent) {
- kfree(new_map);
- return -EINVAL;
- }
- new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
- new_map[0].data.mux.function = parent->name;
- new_map[0].data.mux.group = np->name;
- of_node_put(parent);
-
- /* create config map */
- new_map++;
- for (i = j = 0; i < grp->npins; i++) {
- if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) {
- new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
- new_map[j].data.configs.group_or_pin =
- pin_get_name(pctldev, grp->pins[i].pin);
- new_map[j].data.configs.configs = &grp->pins[i].config;
- new_map[j].data.configs.num_configs = 1;
- j++;
- }
- }
-
- dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
- (*map)->data.mux.function, (*map)->data.mux.group, map_num);
-
- return 0;
-}
-
-static void imx_dt_free_map(struct pinctrl_dev *pctldev,
- struct pinctrl_map *map, unsigned num_maps)
-{
- kfree(map);
-}
-
-static const struct pinctrl_ops imx_pctrl_ops = {
- .get_groups_count = imx_get_groups_count,
- .get_group_name = imx_get_group_name,
- .get_group_pins = imx_get_group_pins,
- .pin_dbg_show = imx_pin_dbg_show,
- .dt_node_to_map = imx_dt_node_to_map,
- .dt_free_map = imx_dt_free_map,
-
-};
-
-static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
- unsigned group)
-{
- struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pinctrl_soc_info *info = ipctl->info;
- const struct imx_pin_reg *pin_reg;
- unsigned int npins, pin_id;
- int i;
- struct imx_pin_group *grp;
-
- /*
- * Configure the mux mode for each pin in the group for a specific
- * function.
- */
- grp = &info->groups[group];
- npins = grp->npins;
-
- dev_dbg(ipctl->dev, "enable function %s group %s\n",
- info->functions[selector].name, grp->name);
-
- for (i = 0; i < npins; i++) {
- struct imx_pin *pin = &grp->pins[i];
- pin_id = pin->pin;
- pin_reg = &info->pin_regs[pin_id];
-
- if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
- dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
- info->pins[pin_id].name);
- return -EINVAL;
- }
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- u32 reg;
- reg = readl(ipctl->base + pin_reg->mux_reg);
- reg &= ~(0x7 << 20);
- reg |= (pin->mux_mode << 20);
- writel(reg, ipctl->base + pin_reg->mux_reg);
- } else {
- writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
- }
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
- pin_reg->mux_reg, pin->mux_mode);
-
- /*
- * If the select input value begins with 0xff, it's a quirky
- * select input and the value should be interpreted as below.
- * 31 23 15 7 0
- * | 0xff | shift | width | select |
- * It's used to work around the problem that the select
- * input for some pin is not implemented in the select
- * input register but in some general purpose register.
- * We encode the select input value, width and shift of
- * the bit field into input_val cell of pin function ID
- * in device tree, and then decode them here for setting
- * up the select input bits in general purpose register.
- */
- if (pin->input_val >> 24 == 0xff) {
- u32 val = pin->input_val;
- u8 select = val & 0xff;
- u8 width = (val >> 8) & 0xff;
- u8 shift = (val >> 16) & 0xff;
- u32 mask = ((1 << width) - 1) << shift;
- /*
- * The input_reg[i] here is actually some IOMUXC general
- * purpose register, not regular select input register.
- */
- val = readl(ipctl->base + pin->input_reg);
- val &= ~mask;
- val |= select << shift;
- writel(val, ipctl->base + pin->input_reg);
- } else if (pin->input_reg) {
- /*
- * Regular select input register can never be at offset
- * 0, and we only print register value for regular case.
- */
- writel(pin->input_val, ipctl->base + pin->input_reg);
- dev_dbg(ipctl->dev,
- "==>select_input: offset 0x%x val 0x%x\n",
- pin->input_reg, pin->input_val);
- }
- }
-
- return 0;
-}
-
-static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
-{
- struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pinctrl_soc_info *info = ipctl->info;
-
- return info->nfunctions;
-}
-
-static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
- unsigned selector)
-{
- struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pinctrl_soc_info *info = ipctl->info;
-
- return info->functions[selector].name;
-}
-
-static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
- const char * const **groups,
- unsigned * const num_groups)
-{
- struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pinctrl_soc_info *info = ipctl->info;
-
- *groups = info->functions[selector].groups;
- *num_groups = info->functions[selector].num_groups;
-
- return 0;
-}
-
-static const struct pinmux_ops imx_pmx_ops = {
- .get_functions_count = imx_pmx_get_funcs_count,
- .get_function_name = imx_pmx_get_func_name,
- .get_function_groups = imx_pmx_get_groups,
- .enable = imx_pmx_enable,
-};
-
-static int imx_pinconf_get(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *config)
-{
- struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pinctrl_soc_info *info = ipctl->info;
- const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
-
- if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
- dev_err(info->dev, "Pin(%s) does not support config function\n",
- info->pins[pin_id].name);
- return -EINVAL;
- }
-
- *config = readl(ipctl->base + pin_reg->conf_reg);
-
- if (info->flags & SHARE_MUX_CONF_REG)
- *config &= 0xffff;
-
- return 0;
-}
-
-static int imx_pinconf_set(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *configs,
- unsigned num_configs)
-{
- struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pinctrl_soc_info *info = ipctl->info;
- const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
- int i;
-
- if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
- dev_err(info->dev, "Pin(%s) does not support config function\n",
- info->pins[pin_id].name);
- return -EINVAL;
- }
-
- dev_dbg(ipctl->dev, "pinconf set pin %s\n",
- info->pins[pin_id].name);
-
- for (i = 0; i < num_configs; i++) {
- if (info->flags & SHARE_MUX_CONF_REG) {
- u32 reg;
- reg = readl(ipctl->base + pin_reg->conf_reg);
- reg &= ~0xffff;
- reg |= configs[i];
- writel(reg, ipctl->base + pin_reg->conf_reg);
- } else {
- writel(configs[i], ipctl->base + pin_reg->conf_reg);
- }
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
- pin_reg->conf_reg, configs[i]);
- } /* for each config */
-
- return 0;
-}
-
-static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned pin_id)
-{
- struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pinctrl_soc_info *info = ipctl->info;
- const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
- unsigned long config;
-
- if (!pin_reg || !pin_reg->conf_reg) {
- seq_printf(s, "N/A");
- return;
- }
-
- config = readl(ipctl->base + pin_reg->conf_reg);
- seq_printf(s, "0x%lx", config);
-}
-
-static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned group)
-{
- struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pinctrl_soc_info *info = ipctl->info;
- struct imx_pin_group *grp;
- unsigned long config;
- const char *name;
- int i, ret;
-
- if (group > info->ngroups)
- return;
-
- seq_printf(s, "\n");
- grp = &info->groups[group];
- for (i = 0; i < grp->npins; i++) {
- struct imx_pin *pin = &grp->pins[i];
- name = pin_get_name(pctldev, pin->pin);
- ret = imx_pinconf_get(pctldev, pin->pin, &config);
- if (ret)
- return;
- seq_printf(s, "%s: 0x%lx", name, config);
- }
-}
-
-static const struct pinconf_ops imx_pinconf_ops = {
- .pin_config_get = imx_pinconf_get,
- .pin_config_set = imx_pinconf_set,
- .pin_config_dbg_show = imx_pinconf_dbg_show,
- .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
-};
-
-static struct pinctrl_desc imx_pinctrl_desc = {
- .pctlops = &imx_pctrl_ops,
- .pmxops = &imx_pmx_ops,
- .confops = &imx_pinconf_ops,
- .owner = THIS_MODULE,
-};
-
-/*
- * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
- * 1 u32 CONFIG, so 24 types in total for each pin.
- */
-#define FSL_PIN_SIZE 24
-#define SHARE_FSL_PIN_SIZE 20
-
-static int imx_pinctrl_parse_groups(struct device_node *np,
- struct imx_pin_group *grp,
- struct imx_pinctrl_soc_info *info,
- u32 index)
-{
- int size, pin_size;
- const __be32 *list;
- int i;
- u32 config;
-
- dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
-
- if (info->flags & SHARE_MUX_CONF_REG)
- pin_size = SHARE_FSL_PIN_SIZE;
- else
- pin_size = FSL_PIN_SIZE;
- /* Initialise group */
- grp->name = np->name;
-
- /*
- * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
- * do sanity check and calculate pins number
- */
- list = of_get_property(np, "fsl,pins", &size);
- if (!list) {
- dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
- return -EINVAL;
- }
-
- /* we do not check return since it's safe node passed down */
- if (!size || size % pin_size) {
- dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
- return -EINVAL;
- }
-
- grp->npins = size / pin_size;
- grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin),
- GFP_KERNEL);
- grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
- GFP_KERNEL);
- if (!grp->pins || ! grp->pin_ids)
- return -ENOMEM;
-
- for (i = 0; i < grp->npins; i++) {
- u32 mux_reg = be32_to_cpu(*list++);
- u32 conf_reg;
- unsigned int pin_id;
- struct imx_pin_reg *pin_reg;
- struct imx_pin *pin = &grp->pins[i];
-
- if (info->flags & SHARE_MUX_CONF_REG)
- conf_reg = mux_reg;
- else
- conf_reg = be32_to_cpu(*list++);
-
- pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
- pin_reg = &info->pin_regs[pin_id];
- pin->pin = pin_id;
- grp->pin_ids[i] = pin_id;
- pin_reg->mux_reg = mux_reg;
- pin_reg->conf_reg = conf_reg;
- pin->input_reg = be32_to_cpu(*list++);
- pin->mux_mode = be32_to_cpu(*list++);
- pin->input_val = be32_to_cpu(*list++);
-
- /* SION bit is in mux register */
- config = be32_to_cpu(*list++);
- if (config & IMX_PAD_SION)
- pin->mux_mode |= IOMUXC_CONFIG_SION;
- pin->config = config & ~IMX_PAD_SION;
-
- dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
- pin->mux_mode, pin->config);
- }
-
- return 0;
-}
-
-static int imx_pinctrl_parse_functions(struct device_node *np,
- struct imx_pinctrl_soc_info *info,
- u32 index)
-{
- struct device_node *child;
- struct imx_pmx_func *func;
- struct imx_pin_group *grp;
- static u32 grp_index;
- u32 i = 0;
-
- dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
-
- func = &info->functions[index];
-
- /* Initialise function */
- func->name = np->name;
- func->num_groups = of_get_child_count(np);
- if (func->num_groups == 0) {
- dev_err(info->dev, "no groups defined in %s\n", np->full_name);
- return -EINVAL;
- }
- func->groups = devm_kzalloc(info->dev,
- func->num_groups * sizeof(char *), GFP_KERNEL);
-
- for_each_child_of_node(np, child) {
- func->groups[i] = child->name;
- grp = &info->groups[grp_index++];
- imx_pinctrl_parse_groups(child, grp, info, i++);
- }
-
- return 0;
-}
-
-static int imx_pinctrl_probe_dt(struct platform_device *pdev,
- struct imx_pinctrl_soc_info *info)
-{
- struct device_node *np = pdev->dev.of_node;
- struct device_node *child;
- u32 nfuncs = 0;
- u32 i = 0;
-
- if (!np)
- return -ENODEV;
-
- nfuncs = of_get_child_count(np);
- if (nfuncs <= 0) {
- dev_err(&pdev->dev, "no functions defined\n");
- return -EINVAL;
- }
-
- info->nfunctions = nfuncs;
- info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
- GFP_KERNEL);
- if (!info->functions)
- return -ENOMEM;
-
- info->ngroups = 0;
- for_each_child_of_node(np, child)
- info->ngroups += of_get_child_count(child);
- info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
- GFP_KERNEL);
- if (!info->groups)
- return -ENOMEM;
-
- for_each_child_of_node(np, child)
- imx_pinctrl_parse_functions(child, info, i++);
-
- return 0;
-}
-
-int imx_pinctrl_probe(struct platform_device *pdev,
- struct imx_pinctrl_soc_info *info)
-{
- struct imx_pinctrl *ipctl;
- struct resource *res;
- int ret;
-
- if (!info || !info->pins || !info->npins) {
- dev_err(&pdev->dev, "wrong pinctrl info\n");
- return -EINVAL;
- }
- info->dev = &pdev->dev;
-
- /* Create state holders etc for this driver */
- ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
- if (!ipctl)
- return -ENOMEM;
-
- info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) *
- info->npins, GFP_KERNEL);
- if (!info->pin_regs)
- return -ENOMEM;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- ipctl->base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(ipctl->base))
- return PTR_ERR(ipctl->base);
-
- imx_pinctrl_desc.name = dev_name(&pdev->dev);
- imx_pinctrl_desc.pins = info->pins;
- imx_pinctrl_desc.npins = info->npins;
-
- ret = imx_pinctrl_probe_dt(pdev, info);
- if (ret) {
- dev_err(&pdev->dev, "fail to probe dt properties\n");
- return ret;
- }
-
- ipctl->info = info;
- ipctl->dev = info->dev;
- platform_set_drvdata(pdev, ipctl);
- ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
- if (!ipctl->pctl) {
- dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
- return -EINVAL;
- }
-
- dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
-
- return 0;
-}
-
-int imx_pinctrl_remove(struct platform_device *pdev)
-{
- struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
-
- pinctrl_unregister(ipctl->pctl);
-
- return 0;
-}
+++ /dev/null
-/*
- * IMX pinmux core definitions
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro Ltd.
- *
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef __DRIVERS_PINCTRL_IMX_H
-#define __DRIVERS_PINCTRL_IMX_H
-
-struct platform_device;
-
-/**
- * struct imx_pin_group - describes a single i.MX pin
- * @pin: the pin_id of this pin
- * @mux_mode: the mux mode for this pin.
- * @input_reg: the select input register offset for this pin if any
- * 0 if no select input setting needed.
- * @input_val: the select input value for this pin.
- * @configs: the config for this pin.
- */
-struct imx_pin {
- unsigned int pin;
- unsigned int mux_mode;
- u16 input_reg;
- unsigned int input_val;
- unsigned long config;
-};
-
-/**
- * struct imx_pin_group - describes an IMX pin group
- * @name: the name of this specific pin group
- * @npins: the number of pins in this group array, i.e. the number of
- * elements in .pins so we can iterate over that array
- * @pin_ids: array of pin_ids. pinctrl forces us to maintain such an array
- * @pins: array of pins
- */
-struct imx_pin_group {
- const char *name;
- unsigned npins;
- unsigned int *pin_ids;
- struct imx_pin *pins;
-};
-
-/**
- * struct imx_pmx_func - describes IMX pinmux functions
- * @name: the name of this specific function
- * @groups: corresponding pin groups
- * @num_groups: the number of groups
- */
-struct imx_pmx_func {
- const char *name;
- const char **groups;
- unsigned num_groups;
-};
-
-/**
- * struct imx_pin_reg - describe a pin reg map
- * @mux_reg: mux register offset
- * @conf_reg: config register offset
- */
-struct imx_pin_reg {
- u16 mux_reg;
- u16 conf_reg;
-};
-
-struct imx_pinctrl_soc_info {
- struct device *dev;
- const struct pinctrl_pin_desc *pins;
- unsigned int npins;
- struct imx_pin_reg *pin_regs;
- struct imx_pin_group *groups;
- unsigned int ngroups;
- struct imx_pmx_func *functions;
- unsigned int nfunctions;
- unsigned int flags;
-};
-
-#define ZERO_OFFSET_VALID 0x1
-#define SHARE_MUX_CONF_REG 0x2
-
-#define NO_MUX 0x0
-#define NO_PAD 0x0
-
-#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
-
-#define PAD_CTL_MASK(len) ((1 << len) - 1)
-#define IMX_MUX_MASK 0x7
-#define IOMUXC_CONFIG_SION (0x1 << 4)
-
-int imx_pinctrl_probe(struct platform_device *pdev,
- struct imx_pinctrl_soc_info *info);
-int imx_pinctrl_remove(struct platform_device *pdev);
-#endif /* __DRIVERS_PINCTRL_IMX_H */
+++ /dev/null
-/*
- * Core driver for the imx pin controller in imx1/21/27
- *
- * Copyright (C) 2013 Pengutronix
- * Author: Markus Pargmann <mpa@pengutronix.de>
- *
- * Based on pinctrl-imx.c:
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/slab.h>
-
-#include "core.h"
-#include "pinctrl-imx1.h"
-
-struct imx1_pinctrl {
- struct device *dev;
- struct pinctrl_dev *pctl;
- void __iomem *base;
- const struct imx1_pinctrl_soc_info *info;
-};
-
-/*
- * MX1 register offsets
- */
-
-#define MX1_DDIR 0x00
-#define MX1_OCR 0x04
-#define MX1_ICONFA 0x0c
-#define MX1_ICONFB 0x14
-#define MX1_GIUS 0x20
-#define MX1_GPR 0x38
-#define MX1_PUEN 0x40
-
-#define MX1_PORT_STRIDE 0x100
-
-
-/*
- * MUX_ID format defines
- */
-#define MX1_MUX_FUNCTION(val) (BIT(0) & val)
-#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
-#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
-#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
-#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
-#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
-
-
-/*
- * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
- * control register are seperated into function, output configuration, input
- * configuration A, input configuration B, GPIO in use and data direction.
- *
- * Those controls that are represented by 1 bit have a direct mapping between
- * bit position and pin id. If they are represented by 2 bit, the lower 16 pins
- * are in the first register and the upper 16 pins in the second (next)
- * register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
- */
-
-/*
- * Calculates the register offset from a pin_id
- */
-static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
-{
- unsigned int port = pin_id / 32;
- return ipctl->base + port * MX1_PORT_STRIDE;
-}
-
-/*
- * Write to a register with 2 bits per pin. The function will automatically
- * use the next register if the pin is managed in the second register.
- */
-static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
- u32 value, u32 reg_offset)
-{
- void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
- int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
- int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
- u32 old_val;
- u32 new_val;
-
- /* Use the next register if the pin's port pin number is >=16 */
- if (pin_id % 32 >= 16)
- reg += 0x04;
-
- dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
- reg, offset, value);
-
- /* Get current state of pins */
- old_val = readl(reg);
- old_val &= mask;
-
- new_val = value & 0x3; /* Make sure value is really 2 bit */
- new_val <<= offset;
- new_val |= old_val;/* Set new state for pin_id */
-
- writel(new_val, reg);
-}
-
-static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
- u32 value, u32 reg_offset)
-{
- void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
- int offset = pin_id % 32;
- int mask = ~BIT_MASK(offset);
- u32 old_val;
- u32 new_val;
-
- /* Get current state of pins */
- old_val = readl(reg);
- old_val &= mask;
-
- new_val = value & 0x1; /* Make sure value is really 1 bit */
- new_val <<= offset;
- new_val |= old_val;/* Set new state for pin_id */
-
- writel(new_val, reg);
-}
-
-static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
- u32 reg_offset)
-{
- void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
- int offset = (pin_id % 16) * 2;
-
- /* Use the next register if the pin's port pin number is >=16 */
- if (pin_id % 32 >= 16)
- reg += 0x04;
-
- return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
-}
-
-static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
- u32 reg_offset)
-{
- void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
- int offset = pin_id % 32;
-
- return !!(readl(reg) & BIT(offset));
-}
-
-static const inline struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
- const struct imx1_pinctrl_soc_info *info,
- const char *name)
-{
- const struct imx1_pin_group *grp = NULL;
- int i;
-
- for (i = 0; i < info->ngroups; i++) {
- if (!strcmp(info->groups[i].name, name)) {
- grp = &info->groups[i];
- break;
- }
- }
-
- return grp;
-}
-
-static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
-{
- struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx1_pinctrl_soc_info *info = ipctl->info;
-
- return info->ngroups;
-}
-
-static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
- unsigned selector)
-{
- struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx1_pinctrl_soc_info *info = ipctl->info;
-
- return info->groups[selector].name;
-}
-
-static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
- const unsigned int **pins,
- unsigned *npins)
-{
- struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx1_pinctrl_soc_info *info = ipctl->info;
-
- if (selector >= info->ngroups)
- return -EINVAL;
-
- *pins = info->groups[selector].pin_ids;
- *npins = info->groups[selector].npins;
-
- return 0;
-}
-
-static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
- unsigned offset)
-{
- struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-
- seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
- imx1_read_bit(ipctl, offset, MX1_GIUS),
- imx1_read_bit(ipctl, offset, MX1_GPR),
- imx1_read_bit(ipctl, offset, MX1_DDIR),
- imx1_read_2bit(ipctl, offset, MX1_OCR),
- imx1_read_2bit(ipctl, offset, MX1_ICONFA),
- imx1_read_2bit(ipctl, offset, MX1_ICONFB));
-}
-
-static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np,
- struct pinctrl_map **map, unsigned *num_maps)
-{
- struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx1_pinctrl_soc_info *info = ipctl->info;
- const struct imx1_pin_group *grp;
- struct pinctrl_map *new_map;
- struct device_node *parent;
- int map_num = 1;
- int i, j;
-
- /*
- * first find the group of this node and check if we need create
- * config maps for pins
- */
- grp = imx1_pinctrl_find_group_by_name(info, np->name);
- if (!grp) {
- dev_err(info->dev, "unable to find group for node %s\n",
- np->name);
- return -EINVAL;
- }
-
- for (i = 0; i < grp->npins; i++)
- map_num++;
-
- new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
- if (!new_map)
- return -ENOMEM;
-
- *map = new_map;
- *num_maps = map_num;
-
- /* create mux map */
- parent = of_get_parent(np);
- if (!parent) {
- kfree(new_map);
- return -EINVAL;
- }
- new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
- new_map[0].data.mux.function = parent->name;
- new_map[0].data.mux.group = np->name;
- of_node_put(parent);
-
- /* create config map */
- new_map++;
- for (i = j = 0; i < grp->npins; i++) {
- new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
- new_map[j].data.configs.group_or_pin =
- pin_get_name(pctldev, grp->pins[i].pin_id);
- new_map[j].data.configs.configs = &grp->pins[i].config;
- new_map[j].data.configs.num_configs = 1;
- j++;
- }
-
- dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
- (*map)->data.mux.function, (*map)->data.mux.group, map_num);
-
- return 0;
-}
-
-static void imx1_dt_free_map(struct pinctrl_dev *pctldev,
- struct pinctrl_map *map, unsigned num_maps)
-{
- kfree(map);
-}
-
-static const struct pinctrl_ops imx1_pctrl_ops = {
- .get_groups_count = imx1_get_groups_count,
- .get_group_name = imx1_get_group_name,
- .get_group_pins = imx1_get_group_pins,
- .pin_dbg_show = imx1_pin_dbg_show,
- .dt_node_to_map = imx1_dt_node_to_map,
- .dt_free_map = imx1_dt_free_map,
-
-};
-
-static int imx1_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
- unsigned group)
-{
- struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx1_pinctrl_soc_info *info = ipctl->info;
- const struct imx1_pin *pins;
- unsigned int npins;
- int i;
-
- /*
- * Configure the mux mode for each pin in the group for a specific
- * function.
- */
- pins = info->groups[group].pins;
- npins = info->groups[group].npins;
-
- WARN_ON(!pins || !npins);
-
- dev_dbg(ipctl->dev, "enable function %s group %s\n",
- info->functions[selector].name, info->groups[group].name);
-
- for (i = 0; i < npins; i++) {
- unsigned int mux = pins[i].mux_id;
- unsigned int pin_id = pins[i].pin_id;
- unsigned int afunction = MX1_MUX_FUNCTION(mux);
- unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
- unsigned int direction = MX1_MUX_DIR(mux);
- unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
- unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
- unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
-
- dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
- __func__, pin_id, afunction, gpio_in_use,
- direction, gpio_oconf, gpio_iconfa,
- gpio_iconfb);
-
- imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
- imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
-
- if (gpio_in_use) {
- imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
- imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
- MX1_ICONFA);
- imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
- MX1_ICONFB);
- } else {
- imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
- }
- }
-
- return 0;
-}
-
-static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
-{
- struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx1_pinctrl_soc_info *info = ipctl->info;
-
- return info->nfunctions;
-}
-
-static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev,
- unsigned selector)
-{
- struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx1_pinctrl_soc_info *info = ipctl->info;
-
- return info->functions[selector].name;
-}
-
-static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
- const char * const **groups,
- unsigned * const num_groups)
-{
- struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx1_pinctrl_soc_info *info = ipctl->info;
-
- *groups = info->functions[selector].groups;
- *num_groups = info->functions[selector].num_groups;
-
- return 0;
-}
-
-static const struct pinmux_ops imx1_pmx_ops = {
- .get_functions_count = imx1_pmx_get_funcs_count,
- .get_function_name = imx1_pmx_get_func_name,
- .get_function_groups = imx1_pmx_get_groups,
- .enable = imx1_pmx_enable,
-};
-
-static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *config)
-{
- struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-
- *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
-
- return 0;
-}
-
-static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *configs,
- unsigned num_configs)
-{
- struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx1_pinctrl_soc_info *info = ipctl->info;
- int i;
-
- for (i = 0; i != num_configs; ++i) {
- imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
-
- dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
- info->pins[pin_id].name);
- }
-
- return 0;
-}
-
-static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned pin_id)
-{
- unsigned long config;
-
- imx1_pinconf_get(pctldev, pin_id, &config);
- seq_printf(s, "0x%lx", config);
-}
-
-static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned group)
-{
- struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx1_pinctrl_soc_info *info = ipctl->info;
- struct imx1_pin_group *grp;
- unsigned long config;
- const char *name;
- int i, ret;
-
- if (group > info->ngroups)
- return;
-
- seq_puts(s, "\n");
- grp = &info->groups[group];
- for (i = 0; i < grp->npins; i++) {
- name = pin_get_name(pctldev, grp->pins[i].pin_id);
- ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config);
- if (ret)
- return;
- seq_printf(s, "%s: 0x%lx", name, config);
- }
-}
-
-static const struct pinconf_ops imx1_pinconf_ops = {
- .pin_config_get = imx1_pinconf_get,
- .pin_config_set = imx1_pinconf_set,
- .pin_config_dbg_show = imx1_pinconf_dbg_show,
- .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show,
-};
-
-static struct pinctrl_desc imx1_pinctrl_desc = {
- .pctlops = &imx1_pctrl_ops,
- .pmxops = &imx1_pmx_ops,
- .confops = &imx1_pinconf_ops,
- .owner = THIS_MODULE,
-};
-
-static int imx1_pinctrl_parse_groups(struct device_node *np,
- struct imx1_pin_group *grp,
- struct imx1_pinctrl_soc_info *info,
- u32 index)
-{
- int size;
- const __be32 *list;
- int i;
-
- dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
-
- /* Initialise group */
- grp->name = np->name;
-
- /*
- * the binding format is fsl,pins = <PIN MUX_ID CONFIG>
- */
- list = of_get_property(np, "fsl,pins", &size);
- /* we do not check return since it's safe node passed down */
- if (!size || size % 12) {
- dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n",
- np->name);
- return -EINVAL;
- }
-
- grp->npins = size / 12;
- grp->pins = devm_kzalloc(info->dev,
- grp->npins * sizeof(struct imx1_pin), GFP_KERNEL);
- grp->pin_ids = devm_kzalloc(info->dev,
- grp->npins * sizeof(unsigned int), GFP_KERNEL);
-
- if (!grp->pins || !grp->pin_ids)
- return -ENOMEM;
-
- for (i = 0; i < grp->npins; i++) {
- grp->pins[i].pin_id = be32_to_cpu(*list++);
- grp->pins[i].mux_id = be32_to_cpu(*list++);
- grp->pins[i].config = be32_to_cpu(*list++);
-
- grp->pin_ids[i] = grp->pins[i].pin_id;
- }
-
- return 0;
-}
-
-static int imx1_pinctrl_parse_functions(struct device_node *np,
- struct imx1_pinctrl_soc_info *info,
- u32 index)
-{
- struct device_node *child;
- struct imx1_pmx_func *func;
- struct imx1_pin_group *grp;
- int ret;
- static u32 grp_index;
- u32 i = 0;
-
- dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
-
- func = &info->functions[index];
-
- /* Initialise function */
- func->name = np->name;
- func->num_groups = of_get_child_count(np);
- if (func->num_groups == 0)
- return -EINVAL;
-
- func->groups = devm_kzalloc(info->dev,
- func->num_groups * sizeof(char *), GFP_KERNEL);
-
- if (!func->groups)
- return -ENOMEM;
-
- for_each_child_of_node(np, child) {
- func->groups[i] = child->name;
- grp = &info->groups[grp_index++];
- ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
- if (ret == -ENOMEM)
- return ret;
- }
-
- return 0;
-}
-
-static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
- struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
-{
- struct device_node *np = pdev->dev.of_node;
- struct device_node *child;
- int ret;
- u32 nfuncs = 0;
- u32 ngroups = 0;
- u32 ifunc = 0;
-
- if (!np)
- return -ENODEV;
-
- for_each_child_of_node(np, child) {
- ++nfuncs;
- ngroups += of_get_child_count(child);
- }
-
- if (!nfuncs) {
- dev_err(&pdev->dev, "No pin functions defined\n");
- return -EINVAL;
- }
-
- info->nfunctions = nfuncs;
- info->functions = devm_kzalloc(&pdev->dev,
- nfuncs * sizeof(struct imx1_pmx_func), GFP_KERNEL);
-
- info->ngroups = ngroups;
- info->groups = devm_kzalloc(&pdev->dev,
- ngroups * sizeof(struct imx1_pin_group), GFP_KERNEL);
-
-
- if (!info->functions || !info->groups)
- return -ENOMEM;
-
- for_each_child_of_node(np, child) {
- ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
- if (ret == -ENOMEM)
- return -ENOMEM;
- }
-
- return 0;
-}
-
-int imx1_pinctrl_core_probe(struct platform_device *pdev,
- struct imx1_pinctrl_soc_info *info)
-{
- struct imx1_pinctrl *ipctl;
- struct resource *res;
- struct pinctrl_desc *pctl_desc;
- int ret;
-
- if (!info || !info->pins || !info->npins) {
- dev_err(&pdev->dev, "wrong pinctrl info\n");
- return -EINVAL;
- }
- info->dev = &pdev->dev;
-
- /* Create state holders etc for this driver */
- ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
- if (!ipctl)
- return -ENOMEM;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -ENOENT;
-
- ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start,
- resource_size(res));
- if (!ipctl->base)
- return -ENOMEM;
-
- pctl_desc = &imx1_pinctrl_desc;
- pctl_desc->name = dev_name(&pdev->dev);
- pctl_desc->pins = info->pins;
- pctl_desc->npins = info->npins;
-
- ret = imx1_pinctrl_parse_dt(pdev, ipctl, info);
- if (ret) {
- dev_err(&pdev->dev, "fail to probe dt properties\n");
- return ret;
- }
-
- ipctl->info = info;
- ipctl->dev = info->dev;
- platform_set_drvdata(pdev, ipctl);
- ipctl->pctl = pinctrl_register(pctl_desc, &pdev->dev, ipctl);
- if (!ipctl->pctl) {
- dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
- return -EINVAL;
- }
-
- ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
- if (ret) {
- pinctrl_unregister(ipctl->pctl);
- dev_err(&pdev->dev, "Failed to populate subdevices\n");
- return ret;
- }
-
- dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
-
- return 0;
-}
-
-int imx1_pinctrl_core_remove(struct platform_device *pdev)
-{
- struct imx1_pinctrl *ipctl = platform_get_drvdata(pdev);
-
- pinctrl_unregister(ipctl->pctl);
-
- return 0;
-}
+++ /dev/null
-/*
- * i.MX1 pinctrl driver based on imx pinmux core
- *
- * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#include "pinctrl-imx1.h"
-
-#define PAD_ID(port, pin) ((port) * 32 + (pin))
-#define PA 0
-#define PB 1
-#define PC 2
-#define PD 3
-
-enum imx1_pads {
- MX1_PAD_A24 = PAD_ID(PA, 0),
- MX1_PAD_TIN = PAD_ID(PA, 1),
- MX1_PAD_PWMO = PAD_ID(PA, 2),
- MX1_PAD_CSI_MCLK = PAD_ID(PA, 3),
- MX1_PAD_CSI_D0 = PAD_ID(PA, 4),
- MX1_PAD_CSI_D1 = PAD_ID(PA, 5),
- MX1_PAD_CSI_D2 = PAD_ID(PA, 6),
- MX1_PAD_CSI_D3 = PAD_ID(PA, 7),
- MX1_PAD_CSI_D4 = PAD_ID(PA, 8),
- MX1_PAD_CSI_D5 = PAD_ID(PA, 9),
- MX1_PAD_CSI_D6 = PAD_ID(PA, 10),
- MX1_PAD_CSI_D7 = PAD_ID(PA, 11),
- MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12),
- MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13),
- MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14),
- MX1_PAD_I2C_SDA = PAD_ID(PA, 15),
- MX1_PAD_I2C_SCL = PAD_ID(PA, 16),
- MX1_PAD_DTACK = PAD_ID(PA, 17),
- MX1_PAD_BCLK = PAD_ID(PA, 18),
- MX1_PAD_LBA = PAD_ID(PA, 19),
- MX1_PAD_ECB = PAD_ID(PA, 20),
- MX1_PAD_A0 = PAD_ID(PA, 21),
- MX1_PAD_CS4 = PAD_ID(PA, 22),
- MX1_PAD_CS5 = PAD_ID(PA, 23),
- MX1_PAD_A16 = PAD_ID(PA, 24),
- MX1_PAD_A17 = PAD_ID(PA, 25),
- MX1_PAD_A18 = PAD_ID(PA, 26),
- MX1_PAD_A19 = PAD_ID(PA, 27),
- MX1_PAD_A20 = PAD_ID(PA, 28),
- MX1_PAD_A21 = PAD_ID(PA, 29),
- MX1_PAD_A22 = PAD_ID(PA, 30),
- MX1_PAD_A23 = PAD_ID(PA, 31),
- MX1_PAD_SD_DAT0 = PAD_ID(PB, 8),
- MX1_PAD_SD_DAT1 = PAD_ID(PB, 9),
- MX1_PAD_SD_DAT2 = PAD_ID(PB, 10),
- MX1_PAD_SD_DAT3 = PAD_ID(PB, 11),
- MX1_PAD_SD_SCLK = PAD_ID(PB, 12),
- MX1_PAD_SD_CMD = PAD_ID(PB, 13),
- MX1_PAD_SIM_SVEN = PAD_ID(PB, 14),
- MX1_PAD_SIM_PD = PAD_ID(PB, 15),
- MX1_PAD_SIM_TX = PAD_ID(PB, 16),
- MX1_PAD_SIM_RX = PAD_ID(PB, 17),
- MX1_PAD_SIM_RST = PAD_ID(PB, 18),
- MX1_PAD_SIM_CLK = PAD_ID(PB, 19),
- MX1_PAD_USBD_AFE = PAD_ID(PB, 20),
- MX1_PAD_USBD_OE = PAD_ID(PB, 21),
- MX1_PAD_USBD_RCV = PAD_ID(PB, 22),
- MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23),
- MX1_PAD_USBD_VP = PAD_ID(PB, 24),
- MX1_PAD_USBD_VM = PAD_ID(PB, 25),
- MX1_PAD_USBD_VPO = PAD_ID(PB, 26),
- MX1_PAD_USBD_VMO = PAD_ID(PB, 27),
- MX1_PAD_UART2_CTS = PAD_ID(PB, 28),
- MX1_PAD_UART2_RTS = PAD_ID(PB, 29),
- MX1_PAD_UART2_TXD = PAD_ID(PB, 30),
- MX1_PAD_UART2_RXD = PAD_ID(PB, 31),
- MX1_PAD_SSI_RXFS = PAD_ID(PC, 3),
- MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4),
- MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5),
- MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6),
- MX1_PAD_SSI_TXFS = PAD_ID(PC, 7),
- MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8),
- MX1_PAD_UART1_CTS = PAD_ID(PC, 9),
- MX1_PAD_UART1_RTS = PAD_ID(PC, 10),
- MX1_PAD_UART1_TXD = PAD_ID(PC, 11),
- MX1_PAD_UART1_RXD = PAD_ID(PC, 12),
- MX1_PAD_SPI1_RDY = PAD_ID(PC, 13),
- MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14),
- MX1_PAD_SPI1_SS = PAD_ID(PC, 15),
- MX1_PAD_SPI1_MISO = PAD_ID(PC, 16),
- MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17),
- MX1_PAD_BT13 = PAD_ID(PC, 19),
- MX1_PAD_BT12 = PAD_ID(PC, 20),
- MX1_PAD_BT11 = PAD_ID(PC, 21),
- MX1_PAD_BT10 = PAD_ID(PC, 22),
- MX1_PAD_BT9 = PAD_ID(PC, 23),
- MX1_PAD_BT8 = PAD_ID(PC, 24),
- MX1_PAD_BT7 = PAD_ID(PC, 25),
- MX1_PAD_BT6 = PAD_ID(PC, 26),
- MX1_PAD_BT5 = PAD_ID(PC, 27),
- MX1_PAD_BT4 = PAD_ID(PC, 28),
- MX1_PAD_BT3 = PAD_ID(PC, 29),
- MX1_PAD_BT2 = PAD_ID(PC, 30),
- MX1_PAD_BT1 = PAD_ID(PC, 31),
- MX1_PAD_LSCLK = PAD_ID(PD, 6),
- MX1_PAD_REV = PAD_ID(PD, 7),
- MX1_PAD_CLS = PAD_ID(PD, 8),
- MX1_PAD_PS = PAD_ID(PD, 9),
- MX1_PAD_SPL_SPR = PAD_ID(PD, 10),
- MX1_PAD_CONTRAST = PAD_ID(PD, 11),
- MX1_PAD_ACD_OE = PAD_ID(PD, 12),
- MX1_PAD_LP_HSYNC = PAD_ID(PD, 13),
- MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14),
- MX1_PAD_LD0 = PAD_ID(PD, 15),
- MX1_PAD_LD1 = PAD_ID(PD, 16),
- MX1_PAD_LD2 = PAD_ID(PD, 17),
- MX1_PAD_LD3 = PAD_ID(PD, 18),
- MX1_PAD_LD4 = PAD_ID(PD, 19),
- MX1_PAD_LD5 = PAD_ID(PD, 20),
- MX1_PAD_LD6 = PAD_ID(PD, 21),
- MX1_PAD_LD7 = PAD_ID(PD, 22),
- MX1_PAD_LD8 = PAD_ID(PD, 23),
- MX1_PAD_LD9 = PAD_ID(PD, 24),
- MX1_PAD_LD10 = PAD_ID(PD, 25),
- MX1_PAD_LD11 = PAD_ID(PD, 26),
- MX1_PAD_LD12 = PAD_ID(PD, 27),
- MX1_PAD_LD13 = PAD_ID(PD, 28),
- MX1_PAD_LD14 = PAD_ID(PD, 29),
- MX1_PAD_LD15 = PAD_ID(PD, 30),
- MX1_PAD_TMR2OUT = PAD_ID(PD, 31),
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(MX1_PAD_A24),
- IMX_PINCTRL_PIN(MX1_PAD_TIN),
- IMX_PINCTRL_PIN(MX1_PAD_PWMO),
- IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK),
- IMX_PINCTRL_PIN(MX1_PAD_CSI_D0),
- IMX_PINCTRL_PIN(MX1_PAD_CSI_D1),
- IMX_PINCTRL_PIN(MX1_PAD_CSI_D2),
- IMX_PINCTRL_PIN(MX1_PAD_CSI_D3),
- IMX_PINCTRL_PIN(MX1_PAD_CSI_D4),
- IMX_PINCTRL_PIN(MX1_PAD_CSI_D5),
- IMX_PINCTRL_PIN(MX1_PAD_CSI_D6),
- IMX_PINCTRL_PIN(MX1_PAD_CSI_D7),
- IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC),
- IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC),
- IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK),
- IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA),
- IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL),
- IMX_PINCTRL_PIN(MX1_PAD_DTACK),
- IMX_PINCTRL_PIN(MX1_PAD_BCLK),
- IMX_PINCTRL_PIN(MX1_PAD_LBA),
- IMX_PINCTRL_PIN(MX1_PAD_ECB),
- IMX_PINCTRL_PIN(MX1_PAD_A0),
- IMX_PINCTRL_PIN(MX1_PAD_CS4),
- IMX_PINCTRL_PIN(MX1_PAD_CS5),
- IMX_PINCTRL_PIN(MX1_PAD_A16),
- IMX_PINCTRL_PIN(MX1_PAD_A17),
- IMX_PINCTRL_PIN(MX1_PAD_A18),
- IMX_PINCTRL_PIN(MX1_PAD_A19),
- IMX_PINCTRL_PIN(MX1_PAD_A20),
- IMX_PINCTRL_PIN(MX1_PAD_A21),
- IMX_PINCTRL_PIN(MX1_PAD_A22),
- IMX_PINCTRL_PIN(MX1_PAD_A23),
- IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0),
- IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1),
- IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2),
- IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3),
- IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK),
- IMX_PINCTRL_PIN(MX1_PAD_SD_CMD),
- IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN),
- IMX_PINCTRL_PIN(MX1_PAD_SIM_PD),
- IMX_PINCTRL_PIN(MX1_PAD_SIM_TX),
- IMX_PINCTRL_PIN(MX1_PAD_SIM_RX),
- IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK),
- IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE),
- IMX_PINCTRL_PIN(MX1_PAD_USBD_OE),
- IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV),
- IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND),
- IMX_PINCTRL_PIN(MX1_PAD_USBD_VP),
- IMX_PINCTRL_PIN(MX1_PAD_USBD_VM),
- IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO),
- IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO),
- IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS),
- IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS),
- IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD),
- IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD),
- IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS),
- IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK),
- IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT),
- IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT),
- IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS),
- IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK),
- IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS),
- IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS),
- IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD),
- IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD),
- IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY),
- IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK),
- IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS),
- IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO),
- IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI),
- IMX_PINCTRL_PIN(MX1_PAD_BT13),
- IMX_PINCTRL_PIN(MX1_PAD_BT12),
- IMX_PINCTRL_PIN(MX1_PAD_BT11),
- IMX_PINCTRL_PIN(MX1_PAD_BT10),
- IMX_PINCTRL_PIN(MX1_PAD_BT9),
- IMX_PINCTRL_PIN(MX1_PAD_BT8),
- IMX_PINCTRL_PIN(MX1_PAD_BT7),
- IMX_PINCTRL_PIN(MX1_PAD_BT6),
- IMX_PINCTRL_PIN(MX1_PAD_BT5),
- IMX_PINCTRL_PIN(MX1_PAD_BT4),
- IMX_PINCTRL_PIN(MX1_PAD_BT3),
- IMX_PINCTRL_PIN(MX1_PAD_BT2),
- IMX_PINCTRL_PIN(MX1_PAD_BT1),
- IMX_PINCTRL_PIN(MX1_PAD_LSCLK),
- IMX_PINCTRL_PIN(MX1_PAD_REV),
- IMX_PINCTRL_PIN(MX1_PAD_CLS),
- IMX_PINCTRL_PIN(MX1_PAD_PS),
- IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR),
- IMX_PINCTRL_PIN(MX1_PAD_CONTRAST),
- IMX_PINCTRL_PIN(MX1_PAD_ACD_OE),
- IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC),
- IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC),
- IMX_PINCTRL_PIN(MX1_PAD_LD0),
- IMX_PINCTRL_PIN(MX1_PAD_LD1),
- IMX_PINCTRL_PIN(MX1_PAD_LD2),
- IMX_PINCTRL_PIN(MX1_PAD_LD3),
- IMX_PINCTRL_PIN(MX1_PAD_LD4),
- IMX_PINCTRL_PIN(MX1_PAD_LD5),
- IMX_PINCTRL_PIN(MX1_PAD_LD6),
- IMX_PINCTRL_PIN(MX1_PAD_LD7),
- IMX_PINCTRL_PIN(MX1_PAD_LD8),
- IMX_PINCTRL_PIN(MX1_PAD_LD9),
- IMX_PINCTRL_PIN(MX1_PAD_LD10),
- IMX_PINCTRL_PIN(MX1_PAD_LD11),
- IMX_PINCTRL_PIN(MX1_PAD_LD12),
- IMX_PINCTRL_PIN(MX1_PAD_LD13),
- IMX_PINCTRL_PIN(MX1_PAD_LD14),
- IMX_PINCTRL_PIN(MX1_PAD_LD15),
- IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT),
-};
-
-static struct imx1_pinctrl_soc_info imx1_pinctrl_info = {
- .pins = imx1_pinctrl_pads,
- .npins = ARRAY_SIZE(imx1_pinctrl_pads),
-};
-
-static int __init imx1_pinctrl_probe(struct platform_device *pdev)
-{
- return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info);
-}
-
-static const struct of_device_id imx1_pinctrl_of_match[] = {
- { .compatible = "fsl,imx1-iomuxc", },
- { }
-};
-MODULE_DEVICE_TABLE(of, imx1_pinctrl_of_match);
-
-static struct platform_driver imx1_pinctrl_driver = {
- .driver = {
- .name = "imx1-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = imx1_pinctrl_of_match,
- },
- .remove = imx1_pinctrl_core_remove,
-};
-module_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);
-
-MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
-MODULE_DESCRIPTION("Freescale i.MX1 pinctrl driver");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * IMX pinmux core definitions
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro Ltd.
- *
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef __DRIVERS_PINCTRL_IMX1_H
-#define __DRIVERS_PINCTRL_IMX1_H
-
-struct platform_device;
-
-/**
- * struct imx1_pin - describes an IMX1/21/27 pin.
- * @pin_id: ID of the described pin.
- * @mux_id: ID of the mux setup.
- * @config: Configuration of the pin (currently only pullup-enable).
- */
-struct imx1_pin {
- unsigned int pin_id;
- unsigned int mux_id;
- unsigned long config;
-};
-
-/**
- * struct imx1_pin_group - describes an IMX pin group
- * @name: the name of this specific pin group
- * @pins: an array of imx1_pin structs used in this group
- * @npins: the number of pins in this group array, i.e. the number of
- * elements in .pins so we can iterate over that array
- */
-struct imx1_pin_group {
- const char *name;
- unsigned int *pin_ids;
- struct imx1_pin *pins;
- unsigned npins;
-};
-
-/**
- * struct imx1_pmx_func - describes IMX pinmux functions
- * @name: the name of this specific function
- * @groups: corresponding pin groups
- * @num_groups: the number of groups
- */
-struct imx1_pmx_func {
- const char *name;
- const char **groups;
- unsigned num_groups;
-};
-
-struct imx1_pinctrl_soc_info {
- struct device *dev;
- const struct pinctrl_pin_desc *pins;
- unsigned int npins;
- struct imx1_pin_group *groups;
- unsigned int ngroups;
- struct imx1_pmx_func *functions;
- unsigned int nfunctions;
-};
-
-#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
-
-int imx1_pinctrl_core_probe(struct platform_device *pdev,
- struct imx1_pinctrl_soc_info *info);
-int imx1_pinctrl_core_remove(struct platform_device *pdev);
-#endif /* __DRIVERS_PINCTRL_IMX1_H */
+++ /dev/null
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include "pinctrl-mxs.h"
-
-enum imx23_pin_enum {
- GPMI_D00 = PINID(0, 0),
- GPMI_D01 = PINID(0, 1),
- GPMI_D02 = PINID(0, 2),
- GPMI_D03 = PINID(0, 3),
- GPMI_D04 = PINID(0, 4),
- GPMI_D05 = PINID(0, 5),
- GPMI_D06 = PINID(0, 6),
- GPMI_D07 = PINID(0, 7),
- GPMI_D08 = PINID(0, 8),
- GPMI_D09 = PINID(0, 9),
- GPMI_D10 = PINID(0, 10),
- GPMI_D11 = PINID(0, 11),
- GPMI_D12 = PINID(0, 12),
- GPMI_D13 = PINID(0, 13),
- GPMI_D14 = PINID(0, 14),
- GPMI_D15 = PINID(0, 15),
- GPMI_CLE = PINID(0, 16),
- GPMI_ALE = PINID(0, 17),
- GPMI_CE2N = PINID(0, 18),
- GPMI_RDY0 = PINID(0, 19),
- GPMI_RDY1 = PINID(0, 20),
- GPMI_RDY2 = PINID(0, 21),
- GPMI_RDY3 = PINID(0, 22),
- GPMI_WPN = PINID(0, 23),
- GPMI_WRN = PINID(0, 24),
- GPMI_RDN = PINID(0, 25),
- AUART1_CTS = PINID(0, 26),
- AUART1_RTS = PINID(0, 27),
- AUART1_RX = PINID(0, 28),
- AUART1_TX = PINID(0, 29),
- I2C_SCL = PINID(0, 30),
- I2C_SDA = PINID(0, 31),
- LCD_D00 = PINID(1, 0),
- LCD_D01 = PINID(1, 1),
- LCD_D02 = PINID(1, 2),
- LCD_D03 = PINID(1, 3),
- LCD_D04 = PINID(1, 4),
- LCD_D05 = PINID(1, 5),
- LCD_D06 = PINID(1, 6),
- LCD_D07 = PINID(1, 7),
- LCD_D08 = PINID(1, 8),
- LCD_D09 = PINID(1, 9),
- LCD_D10 = PINID(1, 10),
- LCD_D11 = PINID(1, 11),
- LCD_D12 = PINID(1, 12),
- LCD_D13 = PINID(1, 13),
- LCD_D14 = PINID(1, 14),
- LCD_D15 = PINID(1, 15),
- LCD_D16 = PINID(1, 16),
- LCD_D17 = PINID(1, 17),
- LCD_RESET = PINID(1, 18),
- LCD_RS = PINID(1, 19),
- LCD_WR = PINID(1, 20),
- LCD_CS = PINID(1, 21),
- LCD_DOTCK = PINID(1, 22),
- LCD_ENABLE = PINID(1, 23),
- LCD_HSYNC = PINID(1, 24),
- LCD_VSYNC = PINID(1, 25),
- PWM0 = PINID(1, 26),
- PWM1 = PINID(1, 27),
- PWM2 = PINID(1, 28),
- PWM3 = PINID(1, 29),
- PWM4 = PINID(1, 30),
- SSP1_CMD = PINID(2, 0),
- SSP1_DETECT = PINID(2, 1),
- SSP1_DATA0 = PINID(2, 2),
- SSP1_DATA1 = PINID(2, 3),
- SSP1_DATA2 = PINID(2, 4),
- SSP1_DATA3 = PINID(2, 5),
- SSP1_SCK = PINID(2, 6),
- ROTARYA = PINID(2, 7),
- ROTARYB = PINID(2, 8),
- EMI_A00 = PINID(2, 9),
- EMI_A01 = PINID(2, 10),
- EMI_A02 = PINID(2, 11),
- EMI_A03 = PINID(2, 12),
- EMI_A04 = PINID(2, 13),
- EMI_A05 = PINID(2, 14),
- EMI_A06 = PINID(2, 15),
- EMI_A07 = PINID(2, 16),
- EMI_A08 = PINID(2, 17),
- EMI_A09 = PINID(2, 18),
- EMI_A10 = PINID(2, 19),
- EMI_A11 = PINID(2, 20),
- EMI_A12 = PINID(2, 21),
- EMI_BA0 = PINID(2, 22),
- EMI_BA1 = PINID(2, 23),
- EMI_CASN = PINID(2, 24),
- EMI_CE0N = PINID(2, 25),
- EMI_CE1N = PINID(2, 26),
- GPMI_CE1N = PINID(2, 27),
- GPMI_CE0N = PINID(2, 28),
- EMI_CKE = PINID(2, 29),
- EMI_RASN = PINID(2, 30),
- EMI_WEN = PINID(2, 31),
- EMI_D00 = PINID(3, 0),
- EMI_D01 = PINID(3, 1),
- EMI_D02 = PINID(3, 2),
- EMI_D03 = PINID(3, 3),
- EMI_D04 = PINID(3, 4),
- EMI_D05 = PINID(3, 5),
- EMI_D06 = PINID(3, 6),
- EMI_D07 = PINID(3, 7),
- EMI_D08 = PINID(3, 8),
- EMI_D09 = PINID(3, 9),
- EMI_D10 = PINID(3, 10),
- EMI_D11 = PINID(3, 11),
- EMI_D12 = PINID(3, 12),
- EMI_D13 = PINID(3, 13),
- EMI_D14 = PINID(3, 14),
- EMI_D15 = PINID(3, 15),
- EMI_DQM0 = PINID(3, 16),
- EMI_DQM1 = PINID(3, 17),
- EMI_DQS0 = PINID(3, 18),
- EMI_DQS1 = PINID(3, 19),
- EMI_CLK = PINID(3, 20),
- EMI_CLKN = PINID(3, 21),
-};
-
-static const struct pinctrl_pin_desc imx23_pins[] = {
- MXS_PINCTRL_PIN(GPMI_D00),
- MXS_PINCTRL_PIN(GPMI_D01),
- MXS_PINCTRL_PIN(GPMI_D02),
- MXS_PINCTRL_PIN(GPMI_D03),
- MXS_PINCTRL_PIN(GPMI_D04),
- MXS_PINCTRL_PIN(GPMI_D05),
- MXS_PINCTRL_PIN(GPMI_D06),
- MXS_PINCTRL_PIN(GPMI_D07),
- MXS_PINCTRL_PIN(GPMI_D08),
- MXS_PINCTRL_PIN(GPMI_D09),
- MXS_PINCTRL_PIN(GPMI_D10),
- MXS_PINCTRL_PIN(GPMI_D11),
- MXS_PINCTRL_PIN(GPMI_D12),
- MXS_PINCTRL_PIN(GPMI_D13),
- MXS_PINCTRL_PIN(GPMI_D14),
- MXS_PINCTRL_PIN(GPMI_D15),
- MXS_PINCTRL_PIN(GPMI_CLE),
- MXS_PINCTRL_PIN(GPMI_ALE),
- MXS_PINCTRL_PIN(GPMI_CE2N),
- MXS_PINCTRL_PIN(GPMI_RDY0),
- MXS_PINCTRL_PIN(GPMI_RDY1),
- MXS_PINCTRL_PIN(GPMI_RDY2),
- MXS_PINCTRL_PIN(GPMI_RDY3),
- MXS_PINCTRL_PIN(GPMI_WPN),
- MXS_PINCTRL_PIN(GPMI_WRN),
- MXS_PINCTRL_PIN(GPMI_RDN),
- MXS_PINCTRL_PIN(AUART1_CTS),
- MXS_PINCTRL_PIN(AUART1_RTS),
- MXS_PINCTRL_PIN(AUART1_RX),
- MXS_PINCTRL_PIN(AUART1_TX),
- MXS_PINCTRL_PIN(I2C_SCL),
- MXS_PINCTRL_PIN(I2C_SDA),
- MXS_PINCTRL_PIN(LCD_D00),
- MXS_PINCTRL_PIN(LCD_D01),
- MXS_PINCTRL_PIN(LCD_D02),
- MXS_PINCTRL_PIN(LCD_D03),
- MXS_PINCTRL_PIN(LCD_D04),
- MXS_PINCTRL_PIN(LCD_D05),
- MXS_PINCTRL_PIN(LCD_D06),
- MXS_PINCTRL_PIN(LCD_D07),
- MXS_PINCTRL_PIN(LCD_D08),
- MXS_PINCTRL_PIN(LCD_D09),
- MXS_PINCTRL_PIN(LCD_D10),
- MXS_PINCTRL_PIN(LCD_D11),
- MXS_PINCTRL_PIN(LCD_D12),
- MXS_PINCTRL_PIN(LCD_D13),
- MXS_PINCTRL_PIN(LCD_D14),
- MXS_PINCTRL_PIN(LCD_D15),
- MXS_PINCTRL_PIN(LCD_D16),
- MXS_PINCTRL_PIN(LCD_D17),
- MXS_PINCTRL_PIN(LCD_RESET),
- MXS_PINCTRL_PIN(LCD_RS),
- MXS_PINCTRL_PIN(LCD_WR),
- MXS_PINCTRL_PIN(LCD_CS),
- MXS_PINCTRL_PIN(LCD_DOTCK),
- MXS_PINCTRL_PIN(LCD_ENABLE),
- MXS_PINCTRL_PIN(LCD_HSYNC),
- MXS_PINCTRL_PIN(LCD_VSYNC),
- MXS_PINCTRL_PIN(PWM0),
- MXS_PINCTRL_PIN(PWM1),
- MXS_PINCTRL_PIN(PWM2),
- MXS_PINCTRL_PIN(PWM3),
- MXS_PINCTRL_PIN(PWM4),
- MXS_PINCTRL_PIN(SSP1_CMD),
- MXS_PINCTRL_PIN(SSP1_DETECT),
- MXS_PINCTRL_PIN(SSP1_DATA0),
- MXS_PINCTRL_PIN(SSP1_DATA1),
- MXS_PINCTRL_PIN(SSP1_DATA2),
- MXS_PINCTRL_PIN(SSP1_DATA3),
- MXS_PINCTRL_PIN(SSP1_SCK),
- MXS_PINCTRL_PIN(ROTARYA),
- MXS_PINCTRL_PIN(ROTARYB),
- MXS_PINCTRL_PIN(EMI_A00),
- MXS_PINCTRL_PIN(EMI_A01),
- MXS_PINCTRL_PIN(EMI_A02),
- MXS_PINCTRL_PIN(EMI_A03),
- MXS_PINCTRL_PIN(EMI_A04),
- MXS_PINCTRL_PIN(EMI_A05),
- MXS_PINCTRL_PIN(EMI_A06),
- MXS_PINCTRL_PIN(EMI_A07),
- MXS_PINCTRL_PIN(EMI_A08),
- MXS_PINCTRL_PIN(EMI_A09),
- MXS_PINCTRL_PIN(EMI_A10),
- MXS_PINCTRL_PIN(EMI_A11),
- MXS_PINCTRL_PIN(EMI_A12),
- MXS_PINCTRL_PIN(EMI_BA0),
- MXS_PINCTRL_PIN(EMI_BA1),
- MXS_PINCTRL_PIN(EMI_CASN),
- MXS_PINCTRL_PIN(EMI_CE0N),
- MXS_PINCTRL_PIN(EMI_CE1N),
- MXS_PINCTRL_PIN(GPMI_CE1N),
- MXS_PINCTRL_PIN(GPMI_CE0N),
- MXS_PINCTRL_PIN(EMI_CKE),
- MXS_PINCTRL_PIN(EMI_RASN),
- MXS_PINCTRL_PIN(EMI_WEN),
- MXS_PINCTRL_PIN(EMI_D00),
- MXS_PINCTRL_PIN(EMI_D01),
- MXS_PINCTRL_PIN(EMI_D02),
- MXS_PINCTRL_PIN(EMI_D03),
- MXS_PINCTRL_PIN(EMI_D04),
- MXS_PINCTRL_PIN(EMI_D05),
- MXS_PINCTRL_PIN(EMI_D06),
- MXS_PINCTRL_PIN(EMI_D07),
- MXS_PINCTRL_PIN(EMI_D08),
- MXS_PINCTRL_PIN(EMI_D09),
- MXS_PINCTRL_PIN(EMI_D10),
- MXS_PINCTRL_PIN(EMI_D11),
- MXS_PINCTRL_PIN(EMI_D12),
- MXS_PINCTRL_PIN(EMI_D13),
- MXS_PINCTRL_PIN(EMI_D14),
- MXS_PINCTRL_PIN(EMI_D15),
- MXS_PINCTRL_PIN(EMI_DQM0),
- MXS_PINCTRL_PIN(EMI_DQM1),
- MXS_PINCTRL_PIN(EMI_DQS0),
- MXS_PINCTRL_PIN(EMI_DQS1),
- MXS_PINCTRL_PIN(EMI_CLK),
- MXS_PINCTRL_PIN(EMI_CLKN),
-};
-
-static struct mxs_regs imx23_regs = {
- .muxsel = 0x100,
- .drive = 0x200,
- .pull = 0x400,
-};
-
-static struct mxs_pinctrl_soc_data imx23_pinctrl_data = {
- .regs = &imx23_regs,
- .pins = imx23_pins,
- .npins = ARRAY_SIZE(imx23_pins),
-};
-
-static int imx23_pinctrl_probe(struct platform_device *pdev)
-{
- return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
-}
-
-static struct of_device_id imx23_pinctrl_of_match[] = {
- { .compatible = "fsl,imx23-pinctrl", },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match);
-
-static struct platform_driver imx23_pinctrl_driver = {
- .driver = {
- .name = "imx23-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = imx23_pinctrl_of_match,
- },
- .probe = imx23_pinctrl_probe,
- .remove = mxs_pinctrl_remove,
-};
-
-static int __init imx23_pinctrl_init(void)
-{
- return platform_driver_register(&imx23_pinctrl_driver);
-}
-postcore_initcall(imx23_pinctrl_init);
-
-static void __exit imx23_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx23_pinctrl_driver);
-}
-module_exit(imx23_pinctrl_exit);
-
-MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
-MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * imx25 pinctrl driver.
- *
- * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
- *
- * This driver was mostly copied from the imx51 pinctrl driver which has:
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro, Inc.
- *
- * Author: Denis Carikli <denis@eukrea.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#include "pinctrl-imx.h"
-
-enum imx25_pads {
- MX25_PAD_RESERVE0 = 1,
- MX25_PAD_RESERVE1 = 2,
- MX25_PAD_A10 = 3,
- MX25_PAD_A13 = 4,
- MX25_PAD_A14 = 5,
- MX25_PAD_A15 = 6,
- MX25_PAD_A16 = 7,
- MX25_PAD_A17 = 8,
- MX25_PAD_A18 = 9,
- MX25_PAD_A19 = 10,
- MX25_PAD_A20 = 11,
- MX25_PAD_A21 = 12,
- MX25_PAD_A22 = 13,
- MX25_PAD_A23 = 14,
- MX25_PAD_A24 = 15,
- MX25_PAD_A25 = 16,
- MX25_PAD_EB0 = 17,
- MX25_PAD_EB1 = 18,
- MX25_PAD_OE = 19,
- MX25_PAD_CS0 = 20,
- MX25_PAD_CS1 = 21,
- MX25_PAD_CS4 = 22,
- MX25_PAD_CS5 = 23,
- MX25_PAD_NF_CE0 = 24,
- MX25_PAD_ECB = 25,
- MX25_PAD_LBA = 26,
- MX25_PAD_BCLK = 27,
- MX25_PAD_RW = 28,
- MX25_PAD_NFWE_B = 29,
- MX25_PAD_NFRE_B = 30,
- MX25_PAD_NFALE = 31,
- MX25_PAD_NFCLE = 32,
- MX25_PAD_NFWP_B = 33,
- MX25_PAD_NFRB = 34,
- MX25_PAD_D15 = 35,
- MX25_PAD_D14 = 36,
- MX25_PAD_D13 = 37,
- MX25_PAD_D12 = 38,
- MX25_PAD_D11 = 39,
- MX25_PAD_D10 = 40,
- MX25_PAD_D9 = 41,
- MX25_PAD_D8 = 42,
- MX25_PAD_D7 = 43,
- MX25_PAD_D6 = 44,
- MX25_PAD_D5 = 45,
- MX25_PAD_D4 = 46,
- MX25_PAD_D3 = 47,
- MX25_PAD_D2 = 48,
- MX25_PAD_D1 = 49,
- MX25_PAD_D0 = 50,
- MX25_PAD_LD0 = 51,
- MX25_PAD_LD1 = 52,
- MX25_PAD_LD2 = 53,
- MX25_PAD_LD3 = 54,
- MX25_PAD_LD4 = 55,
- MX25_PAD_LD5 = 56,
- MX25_PAD_LD6 = 57,
- MX25_PAD_LD7 = 58,
- MX25_PAD_LD8 = 59,
- MX25_PAD_LD9 = 60,
- MX25_PAD_LD10 = 61,
- MX25_PAD_LD11 = 62,
- MX25_PAD_LD12 = 63,
- MX25_PAD_LD13 = 64,
- MX25_PAD_LD14 = 65,
- MX25_PAD_LD15 = 66,
- MX25_PAD_HSYNC = 67,
- MX25_PAD_VSYNC = 68,
- MX25_PAD_LSCLK = 69,
- MX25_PAD_OE_ACD = 70,
- MX25_PAD_CONTRAST = 71,
- MX25_PAD_PWM = 72,
- MX25_PAD_CSI_D2 = 73,
- MX25_PAD_CSI_D3 = 74,
- MX25_PAD_CSI_D4 = 75,
- MX25_PAD_CSI_D5 = 76,
- MX25_PAD_CSI_D6 = 77,
- MX25_PAD_CSI_D7 = 78,
- MX25_PAD_CSI_D8 = 79,
- MX25_PAD_CSI_D9 = 80,
- MX25_PAD_CSI_MCLK = 81,
- MX25_PAD_CSI_VSYNC = 82,
- MX25_PAD_CSI_HSYNC = 83,
- MX25_PAD_CSI_PIXCLK = 84,
- MX25_PAD_I2C1_CLK = 85,
- MX25_PAD_I2C1_DAT = 86,
- MX25_PAD_CSPI1_MOSI = 87,
- MX25_PAD_CSPI1_MISO = 88,
- MX25_PAD_CSPI1_SS0 = 89,
- MX25_PAD_CSPI1_SS1 = 90,
- MX25_PAD_CSPI1_SCLK = 91,
- MX25_PAD_CSPI1_RDY = 92,
- MX25_PAD_UART1_RXD = 93,
- MX25_PAD_UART1_TXD = 94,
- MX25_PAD_UART1_RTS = 95,
- MX25_PAD_UART1_CTS = 96,
- MX25_PAD_UART2_RXD = 97,
- MX25_PAD_UART2_TXD = 98,
- MX25_PAD_UART2_RTS = 99,
- MX25_PAD_UART2_CTS = 100,
- MX25_PAD_SD1_CMD = 101,
- MX25_PAD_SD1_CLK = 102,
- MX25_PAD_SD1_DATA0 = 103,
- MX25_PAD_SD1_DATA1 = 104,
- MX25_PAD_SD1_DATA2 = 105,
- MX25_PAD_SD1_DATA3 = 106,
- MX25_PAD_KPP_ROW0 = 107,
- MX25_PAD_KPP_ROW1 = 108,
- MX25_PAD_KPP_ROW2 = 109,
- MX25_PAD_KPP_ROW3 = 110,
- MX25_PAD_KPP_COL0 = 111,
- MX25_PAD_KPP_COL1 = 112,
- MX25_PAD_KPP_COL2 = 113,
- MX25_PAD_KPP_COL3 = 114,
- MX25_PAD_FEC_MDC = 115,
- MX25_PAD_FEC_MDIO = 116,
- MX25_PAD_FEC_TDATA0 = 117,
- MX25_PAD_FEC_TDATA1 = 118,
- MX25_PAD_FEC_TX_EN = 119,
- MX25_PAD_FEC_RDATA0 = 120,
- MX25_PAD_FEC_RDATA1 = 121,
- MX25_PAD_FEC_RX_DV = 122,
- MX25_PAD_FEC_TX_CLK = 123,
- MX25_PAD_RTCK = 124,
- MX25_PAD_DE_B = 125,
- MX25_PAD_GPIO_A = 126,
- MX25_PAD_GPIO_B = 127,
- MX25_PAD_GPIO_C = 128,
- MX25_PAD_GPIO_D = 129,
- MX25_PAD_GPIO_E = 130,
- MX25_PAD_GPIO_F = 131,
- MX25_PAD_EXT_ARMCLK = 132,
- MX25_PAD_UPLL_BYPCLK = 133,
- MX25_PAD_VSTBY_REQ = 134,
- MX25_PAD_VSTBY_ACK = 135,
- MX25_PAD_POWER_FAIL = 136,
- MX25_PAD_CLKO = 137,
- MX25_PAD_BOOT_MODE0 = 138,
- MX25_PAD_BOOT_MODE1 = 139,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(MX25_PAD_RESERVE0),
- IMX_PINCTRL_PIN(MX25_PAD_RESERVE1),
- IMX_PINCTRL_PIN(MX25_PAD_A10),
- IMX_PINCTRL_PIN(MX25_PAD_A13),
- IMX_PINCTRL_PIN(MX25_PAD_A14),
- IMX_PINCTRL_PIN(MX25_PAD_A15),
- IMX_PINCTRL_PIN(MX25_PAD_A16),
- IMX_PINCTRL_PIN(MX25_PAD_A17),
- IMX_PINCTRL_PIN(MX25_PAD_A18),
- IMX_PINCTRL_PIN(MX25_PAD_A19),
- IMX_PINCTRL_PIN(MX25_PAD_A20),
- IMX_PINCTRL_PIN(MX25_PAD_A21),
- IMX_PINCTRL_PIN(MX25_PAD_A22),
- IMX_PINCTRL_PIN(MX25_PAD_A23),
- IMX_PINCTRL_PIN(MX25_PAD_A24),
- IMX_PINCTRL_PIN(MX25_PAD_A25),
- IMX_PINCTRL_PIN(MX25_PAD_EB0),
- IMX_PINCTRL_PIN(MX25_PAD_EB1),
- IMX_PINCTRL_PIN(MX25_PAD_OE),
- IMX_PINCTRL_PIN(MX25_PAD_CS0),
- IMX_PINCTRL_PIN(MX25_PAD_CS1),
- IMX_PINCTRL_PIN(MX25_PAD_CS4),
- IMX_PINCTRL_PIN(MX25_PAD_CS5),
- IMX_PINCTRL_PIN(MX25_PAD_NF_CE0),
- IMX_PINCTRL_PIN(MX25_PAD_ECB),
- IMX_PINCTRL_PIN(MX25_PAD_LBA),
- IMX_PINCTRL_PIN(MX25_PAD_BCLK),
- IMX_PINCTRL_PIN(MX25_PAD_RW),
- IMX_PINCTRL_PIN(MX25_PAD_NFWE_B),
- IMX_PINCTRL_PIN(MX25_PAD_NFRE_B),
- IMX_PINCTRL_PIN(MX25_PAD_NFALE),
- IMX_PINCTRL_PIN(MX25_PAD_NFCLE),
- IMX_PINCTRL_PIN(MX25_PAD_NFWP_B),
- IMX_PINCTRL_PIN(MX25_PAD_NFRB),
- IMX_PINCTRL_PIN(MX25_PAD_D15),
- IMX_PINCTRL_PIN(MX25_PAD_D14),
- IMX_PINCTRL_PIN(MX25_PAD_D13),
- IMX_PINCTRL_PIN(MX25_PAD_D12),
- IMX_PINCTRL_PIN(MX25_PAD_D11),
- IMX_PINCTRL_PIN(MX25_PAD_D10),
- IMX_PINCTRL_PIN(MX25_PAD_D9),
- IMX_PINCTRL_PIN(MX25_PAD_D8),
- IMX_PINCTRL_PIN(MX25_PAD_D7),
- IMX_PINCTRL_PIN(MX25_PAD_D6),
- IMX_PINCTRL_PIN(MX25_PAD_D5),
- IMX_PINCTRL_PIN(MX25_PAD_D4),
- IMX_PINCTRL_PIN(MX25_PAD_D3),
- IMX_PINCTRL_PIN(MX25_PAD_D2),
- IMX_PINCTRL_PIN(MX25_PAD_D1),
- IMX_PINCTRL_PIN(MX25_PAD_D0),
- IMX_PINCTRL_PIN(MX25_PAD_LD0),
- IMX_PINCTRL_PIN(MX25_PAD_LD1),
- IMX_PINCTRL_PIN(MX25_PAD_LD2),
- IMX_PINCTRL_PIN(MX25_PAD_LD3),
- IMX_PINCTRL_PIN(MX25_PAD_LD4),
- IMX_PINCTRL_PIN(MX25_PAD_LD5),
- IMX_PINCTRL_PIN(MX25_PAD_LD6),
- IMX_PINCTRL_PIN(MX25_PAD_LD7),
- IMX_PINCTRL_PIN(MX25_PAD_LD8),
- IMX_PINCTRL_PIN(MX25_PAD_LD9),
- IMX_PINCTRL_PIN(MX25_PAD_LD10),
- IMX_PINCTRL_PIN(MX25_PAD_LD11),
- IMX_PINCTRL_PIN(MX25_PAD_LD12),
- IMX_PINCTRL_PIN(MX25_PAD_LD13),
- IMX_PINCTRL_PIN(MX25_PAD_LD14),
- IMX_PINCTRL_PIN(MX25_PAD_LD15),
- IMX_PINCTRL_PIN(MX25_PAD_HSYNC),
- IMX_PINCTRL_PIN(MX25_PAD_VSYNC),
- IMX_PINCTRL_PIN(MX25_PAD_LSCLK),
- IMX_PINCTRL_PIN(MX25_PAD_OE_ACD),
- IMX_PINCTRL_PIN(MX25_PAD_CONTRAST),
- IMX_PINCTRL_PIN(MX25_PAD_PWM),
- IMX_PINCTRL_PIN(MX25_PAD_CSI_D2),
- IMX_PINCTRL_PIN(MX25_PAD_CSI_D3),
- IMX_PINCTRL_PIN(MX25_PAD_CSI_D4),
- IMX_PINCTRL_PIN(MX25_PAD_CSI_D5),
- IMX_PINCTRL_PIN(MX25_PAD_CSI_D6),
- IMX_PINCTRL_PIN(MX25_PAD_CSI_D7),
- IMX_PINCTRL_PIN(MX25_PAD_CSI_D8),
- IMX_PINCTRL_PIN(MX25_PAD_CSI_D9),
- IMX_PINCTRL_PIN(MX25_PAD_CSI_MCLK),
- IMX_PINCTRL_PIN(MX25_PAD_CSI_VSYNC),
- IMX_PINCTRL_PIN(MX25_PAD_CSI_HSYNC),
- IMX_PINCTRL_PIN(MX25_PAD_CSI_PIXCLK),
- IMX_PINCTRL_PIN(MX25_PAD_I2C1_CLK),
- IMX_PINCTRL_PIN(MX25_PAD_I2C1_DAT),
- IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MOSI),
- IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MISO),
- IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS0),
- IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS1),
- IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SCLK),
- IMX_PINCTRL_PIN(MX25_PAD_CSPI1_RDY),
- IMX_PINCTRL_PIN(MX25_PAD_UART1_RXD),
- IMX_PINCTRL_PIN(MX25_PAD_UART1_TXD),
- IMX_PINCTRL_PIN(MX25_PAD_UART1_RTS),
- IMX_PINCTRL_PIN(MX25_PAD_UART1_CTS),
- IMX_PINCTRL_PIN(MX25_PAD_UART2_RXD),
- IMX_PINCTRL_PIN(MX25_PAD_UART2_TXD),
- IMX_PINCTRL_PIN(MX25_PAD_UART2_RTS),
- IMX_PINCTRL_PIN(MX25_PAD_UART2_CTS),
- IMX_PINCTRL_PIN(MX25_PAD_SD1_CMD),
- IMX_PINCTRL_PIN(MX25_PAD_SD1_CLK),
- IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA0),
- IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA1),
- IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA2),
- IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA3),
- IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW0),
- IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW1),
- IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW2),
- IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW3),
- IMX_PINCTRL_PIN(MX25_PAD_KPP_COL0),
- IMX_PINCTRL_PIN(MX25_PAD_KPP_COL1),
- IMX_PINCTRL_PIN(MX25_PAD_KPP_COL2),
- IMX_PINCTRL_PIN(MX25_PAD_KPP_COL3),
- IMX_PINCTRL_PIN(MX25_PAD_FEC_MDC),
- IMX_PINCTRL_PIN(MX25_PAD_FEC_MDIO),
- IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA0),
- IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA1),
- IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_EN),
- IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA0),
- IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA1),
- IMX_PINCTRL_PIN(MX25_PAD_FEC_RX_DV),
- IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_CLK),
- IMX_PINCTRL_PIN(MX25_PAD_RTCK),
- IMX_PINCTRL_PIN(MX25_PAD_DE_B),
- IMX_PINCTRL_PIN(MX25_PAD_GPIO_A),
- IMX_PINCTRL_PIN(MX25_PAD_GPIO_B),
- IMX_PINCTRL_PIN(MX25_PAD_GPIO_C),
- IMX_PINCTRL_PIN(MX25_PAD_GPIO_D),
- IMX_PINCTRL_PIN(MX25_PAD_GPIO_E),
- IMX_PINCTRL_PIN(MX25_PAD_GPIO_F),
- IMX_PINCTRL_PIN(MX25_PAD_EXT_ARMCLK),
- IMX_PINCTRL_PIN(MX25_PAD_UPLL_BYPCLK),
- IMX_PINCTRL_PIN(MX25_PAD_VSTBY_REQ),
- IMX_PINCTRL_PIN(MX25_PAD_VSTBY_ACK),
- IMX_PINCTRL_PIN(MX25_PAD_POWER_FAIL),
- IMX_PINCTRL_PIN(MX25_PAD_CLKO),
- IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE0),
- IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1),
-};
-
-static struct imx_pinctrl_soc_info imx25_pinctrl_info = {
- .pins = imx25_pinctrl_pads,
- .npins = ARRAY_SIZE(imx25_pinctrl_pads),
-};
-
-static struct of_device_id imx25_pinctrl_of_match[] = {
- { .compatible = "fsl,imx25-iomuxc", },
- { /* sentinel */ }
-};
-
-static int imx25_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &imx25_pinctrl_info);
-}
-
-static struct platform_driver imx25_pinctrl_driver = {
- .driver = {
- .name = "imx25-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = of_match_ptr(imx25_pinctrl_of_match),
- },
- .probe = imx25_pinctrl_probe,
- .remove = imx_pinctrl_remove,
-};
-
-static int __init imx25_pinctrl_init(void)
-{
- return platform_driver_register(&imx25_pinctrl_driver);
-}
-arch_initcall(imx25_pinctrl_init);
-
-static void __exit imx25_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx25_pinctrl_driver);
-}
-module_exit(imx25_pinctrl_exit);
-MODULE_AUTHOR("Denis Carikli <denis@eukrea.com>");
-MODULE_DESCRIPTION("Freescale IMX25 pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * imx27 pinctrl driver based on imx pinmux core
- *
- * Copyright (C) 2013 Pengutronix
- *
- * Author: Markus Pargmann <mpa@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#include "pinctrl-imx1.h"
-
-#define PAD_ID(port, pin) (port*32 + pin)
-#define PA 0
-#define PB 1
-#define PC 2
-#define PD 3
-#define PE 4
-#define PF 5
-
-enum imx27_pads {
- MX27_PAD_USBH2_CLK = PAD_ID(PA, 0),
- MX27_PAD_USBH2_DIR = PAD_ID(PA, 1),
- MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2),
- MX27_PAD_USBH2_NXT = PAD_ID(PA, 3),
- MX27_PAD_USBH2_STP = PAD_ID(PA, 4),
- MX27_PAD_LSCLK = PAD_ID(PA, 5),
- MX27_PAD_LD0 = PAD_ID(PA, 6),
- MX27_PAD_LD1 = PAD_ID(PA, 7),
- MX27_PAD_LD2 = PAD_ID(PA, 8),
- MX27_PAD_LD3 = PAD_ID(PA, 9),
- MX27_PAD_LD4 = PAD_ID(PA, 10),
- MX27_PAD_LD5 = PAD_ID(PA, 11),
- MX27_PAD_LD6 = PAD_ID(PA, 12),
- MX27_PAD_LD7 = PAD_ID(PA, 13),
- MX27_PAD_LD8 = PAD_ID(PA, 14),
- MX27_PAD_LD9 = PAD_ID(PA, 15),
- MX27_PAD_LD10 = PAD_ID(PA, 16),
- MX27_PAD_LD11 = PAD_ID(PA, 17),
- MX27_PAD_LD12 = PAD_ID(PA, 18),
- MX27_PAD_LD13 = PAD_ID(PA, 19),
- MX27_PAD_LD14 = PAD_ID(PA, 20),
- MX27_PAD_LD15 = PAD_ID(PA, 21),
- MX27_PAD_LD16 = PAD_ID(PA, 22),
- MX27_PAD_LD17 = PAD_ID(PA, 23),
- MX27_PAD_REV = PAD_ID(PA, 24),
- MX27_PAD_CLS = PAD_ID(PA, 25),
- MX27_PAD_PS = PAD_ID(PA, 26),
- MX27_PAD_SPL_SPR = PAD_ID(PA, 27),
- MX27_PAD_HSYNC = PAD_ID(PA, 28),
- MX27_PAD_VSYNC = PAD_ID(PA, 29),
- MX27_PAD_CONTRAST = PAD_ID(PA, 30),
- MX27_PAD_OE_ACD = PAD_ID(PA, 31),
-
- MX27_PAD_SD2_D0 = PAD_ID(PB, 4),
- MX27_PAD_SD2_D1 = PAD_ID(PB, 5),
- MX27_PAD_SD2_D2 = PAD_ID(PB, 6),
- MX27_PAD_SD2_D3 = PAD_ID(PB, 7),
- MX27_PAD_SD2_CMD = PAD_ID(PB, 8),
- MX27_PAD_SD2_CLK = PAD_ID(PB, 9),
- MX27_PAD_CSI_D0 = PAD_ID(PB, 10),
- MX27_PAD_CSI_D1 = PAD_ID(PB, 11),
- MX27_PAD_CSI_D2 = PAD_ID(PB, 12),
- MX27_PAD_CSI_D3 = PAD_ID(PB, 13),
- MX27_PAD_CSI_D4 = PAD_ID(PB, 14),
- MX27_PAD_CSI_MCLK = PAD_ID(PB, 15),
- MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
- MX27_PAD_CSI_D5 = PAD_ID(PB, 17),
- MX27_PAD_CSI_D6 = PAD_ID(PB, 18),
- MX27_PAD_CSI_D7 = PAD_ID(PB, 19),
- MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20),
- MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21),
- MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22),
- MX27_PAD_USB_PWR = PAD_ID(PB, 23),
- MX27_PAD_USB_OC_B = PAD_ID(PB, 24),
- MX27_PAD_USBH1_RCV = PAD_ID(PB, 25),
- MX27_PAD_USBH1_FS = PAD_ID(PB, 26),
- MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27),
- MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28),
- MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29),
- MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30),
- MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31),
-
- MX27_PAD_I2C2_SDA = PAD_ID(PC, 5),
- MX27_PAD_I2C2_SCL = PAD_ID(PC, 6),
- MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7),
- MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8),
- MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9),
- MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10),
- MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11),
- MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12),
- MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13),
- MX27_PAD_TOUT = PAD_ID(PC, 14),
- MX27_PAD_TIN = PAD_ID(PC, 15),
- MX27_PAD_SSI4_FS = PAD_ID(PC, 16),
- MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17),
- MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18),
- MX27_PAD_SSI4_CLK = PAD_ID(PC, 19),
- MX27_PAD_SSI1_FS = PAD_ID(PC, 20),
- MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21),
- MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22),
- MX27_PAD_SSI1_CLK = PAD_ID(PC, 23),
- MX27_PAD_SSI2_FS = PAD_ID(PC, 24),
- MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25),
- MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26),
- MX27_PAD_SSI2_CLK = PAD_ID(PC, 27),
- MX27_PAD_SSI3_FS = PAD_ID(PC, 28),
- MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29),
- MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30),
- MX27_PAD_SSI3_CLK = PAD_ID(PC, 31),
-
- MX27_PAD_SD3_CMD = PAD_ID(PD, 0),
- MX27_PAD_SD3_CLK = PAD_ID(PD, 1),
- MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2),
- MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3),
- MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4),
- MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5),
- MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6),
- MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7),
- MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8),
- MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9),
- MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10),
- MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11),
- MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12),
- MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13),
- MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14),
- MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15),
- MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16),
- MX27_PAD_I2C_DATA = PAD_ID(PD, 17),
- MX27_PAD_I2C_CLK = PAD_ID(PD, 18),
- MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
- MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
- MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
- MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
- MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23),
- MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
- MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25),
- MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
- MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
- MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
- MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
- MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30),
- MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
-
- MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0),
- MX27_PAD_USBOTG_STP = PAD_ID(PE, 1),
- MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2),
- MX27_PAD_UART2_CTS = PAD_ID(PE, 3),
- MX27_PAD_UART2_RTS = PAD_ID(PE, 4),
- MX27_PAD_PWMO = PAD_ID(PE, 5),
- MX27_PAD_UART2_TXD = PAD_ID(PE, 6),
- MX27_PAD_UART2_RXD = PAD_ID(PE, 7),
- MX27_PAD_UART3_TXD = PAD_ID(PE, 8),
- MX27_PAD_UART3_RXD = PAD_ID(PE, 9),
- MX27_PAD_UART3_CTS = PAD_ID(PE, 10),
- MX27_PAD_UART3_RTS = PAD_ID(PE, 11),
- MX27_PAD_UART1_TXD = PAD_ID(PE, 12),
- MX27_PAD_UART1_RXD = PAD_ID(PE, 13),
- MX27_PAD_UART1_CTS = PAD_ID(PE, 14),
- MX27_PAD_UART1_RTS = PAD_ID(PE, 15),
- MX27_PAD_RTCK = PAD_ID(PE, 16),
- MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17),
- MX27_PAD_SD1_D0 = PAD_ID(PE, 18),
- MX27_PAD_SD1_D1 = PAD_ID(PE, 19),
- MX27_PAD_SD1_D2 = PAD_ID(PE, 20),
- MX27_PAD_SD1_D3 = PAD_ID(PE, 21),
- MX27_PAD_SD1_CMD = PAD_ID(PE, 22),
- MX27_PAD_SD1_CLK = PAD_ID(PE, 23),
- MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24),
- MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25),
-
- MX27_PAD_NFRB = PAD_ID(PF, 0),
- MX27_PAD_NFCLE = PAD_ID(PF, 1),
- MX27_PAD_NFWP_B = PAD_ID(PF, 2),
- MX27_PAD_NFCE_B = PAD_ID(PF, 3),
- MX27_PAD_NFALE = PAD_ID(PF, 4),
- MX27_PAD_NFRE_B = PAD_ID(PF, 5),
- MX27_PAD_NFWE_B = PAD_ID(PF, 6),
- MX27_PAD_PC_POE = PAD_ID(PF, 7),
- MX27_PAD_PC_RW_B = PAD_ID(PF, 8),
- MX27_PAD_IOIS16 = PAD_ID(PF, 9),
- MX27_PAD_PC_RST = PAD_ID(PF, 10),
- MX27_PAD_PC_BVD2 = PAD_ID(PF, 11),
- MX27_PAD_PC_BVD1 = PAD_ID(PF, 12),
- MX27_PAD_PC_VS2 = PAD_ID(PF, 13),
- MX27_PAD_PC_VS1 = PAD_ID(PF, 14),
- MX27_PAD_CLKO = PAD_ID(PF, 15),
- MX27_PAD_PC_PWRON = PAD_ID(PF, 16),
- MX27_PAD_PC_READY = PAD_ID(PF, 17),
- MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18),
- MX27_PAD_PC_CD2_B = PAD_ID(PF, 19),
- MX27_PAD_PC_CD1_B = PAD_ID(PF, 20),
- MX27_PAD_CS4_B = PAD_ID(PF, 21),
- MX27_PAD_CS5_B = PAD_ID(PF, 22),
- MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK),
- IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR),
- IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7),
- IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT),
- IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP),
- IMX_PINCTRL_PIN(MX27_PAD_LSCLK),
- IMX_PINCTRL_PIN(MX27_PAD_LD0),
- IMX_PINCTRL_PIN(MX27_PAD_LD1),
- IMX_PINCTRL_PIN(MX27_PAD_LD2),
- IMX_PINCTRL_PIN(MX27_PAD_LD3),
- IMX_PINCTRL_PIN(MX27_PAD_LD4),
- IMX_PINCTRL_PIN(MX27_PAD_LD5),
- IMX_PINCTRL_PIN(MX27_PAD_LD6),
- IMX_PINCTRL_PIN(MX27_PAD_LD7),
- IMX_PINCTRL_PIN(MX27_PAD_LD8),
- IMX_PINCTRL_PIN(MX27_PAD_LD9),
- IMX_PINCTRL_PIN(MX27_PAD_LD10),
- IMX_PINCTRL_PIN(MX27_PAD_LD11),
- IMX_PINCTRL_PIN(MX27_PAD_LD12),
- IMX_PINCTRL_PIN(MX27_PAD_LD13),
- IMX_PINCTRL_PIN(MX27_PAD_LD14),
- IMX_PINCTRL_PIN(MX27_PAD_LD15),
- IMX_PINCTRL_PIN(MX27_PAD_LD16),
- IMX_PINCTRL_PIN(MX27_PAD_LD17),
- IMX_PINCTRL_PIN(MX27_PAD_REV),
- IMX_PINCTRL_PIN(MX27_PAD_CLS),
- IMX_PINCTRL_PIN(MX27_PAD_PS),
- IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR),
- IMX_PINCTRL_PIN(MX27_PAD_HSYNC),
- IMX_PINCTRL_PIN(MX27_PAD_VSYNC),
- IMX_PINCTRL_PIN(MX27_PAD_CONTRAST),
- IMX_PINCTRL_PIN(MX27_PAD_OE_ACD),
-
- IMX_PINCTRL_PIN(MX27_PAD_SD2_D0),
- IMX_PINCTRL_PIN(MX27_PAD_SD2_D1),
- IMX_PINCTRL_PIN(MX27_PAD_SD2_D2),
- IMX_PINCTRL_PIN(MX27_PAD_SD2_D3),
- IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD),
- IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK),
- IMX_PINCTRL_PIN(MX27_PAD_CSI_D0),
- IMX_PINCTRL_PIN(MX27_PAD_CSI_D1),
- IMX_PINCTRL_PIN(MX27_PAD_CSI_D2),
- IMX_PINCTRL_PIN(MX27_PAD_CSI_D3),
- IMX_PINCTRL_PIN(MX27_PAD_CSI_D4),
- IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK),
- IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK),
- IMX_PINCTRL_PIN(MX27_PAD_CSI_D5),
- IMX_PINCTRL_PIN(MX27_PAD_CSI_D6),
- IMX_PINCTRL_PIN(MX27_PAD_CSI_D7),
- IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC),
- IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC),
- IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP),
- IMX_PINCTRL_PIN(MX27_PAD_USB_PWR),
- IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B),
- IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV),
- IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS),
- IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B),
- IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM),
- IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP),
- IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM),
- IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP),
-
- IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA),
- IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL),
- IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5),
- IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6),
- IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0),
- IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2),
- IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1),
- IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4),
- IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3),
- IMX_PINCTRL_PIN(MX27_PAD_TOUT),
- IMX_PINCTRL_PIN(MX27_PAD_TIN),
- IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS),
- IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT),
- IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT),
- IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK),
- IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS),
- IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT),
- IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT),
- IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK),
- IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS),
- IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT),
- IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT),
- IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK),
- IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS),
- IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT),
- IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT),
- IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK),
-
- IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD),
- IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14),
- IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA),
- IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK),
- IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2),
- IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1),
- IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0),
- IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK),
- IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO),
- IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI),
- IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY),
- IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2),
- IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1),
- IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0),
- IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK),
- IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO),
- IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI),
-
- IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT),
- IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP),
- IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR),
- IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS),
- IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS),
- IMX_PINCTRL_PIN(MX27_PAD_PWMO),
- IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD),
- IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD),
- IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD),
- IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD),
- IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS),
- IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS),
- IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD),
- IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD),
- IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS),
- IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS),
- IMX_PINCTRL_PIN(MX27_PAD_RTCK),
- IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B),
- IMX_PINCTRL_PIN(MX27_PAD_SD1_D0),
- IMX_PINCTRL_PIN(MX27_PAD_SD1_D1),
- IMX_PINCTRL_PIN(MX27_PAD_SD1_D2),
- IMX_PINCTRL_PIN(MX27_PAD_SD1_D3),
- IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD),
- IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK),
- IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK),
- IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7),
-
- IMX_PINCTRL_PIN(MX27_PAD_NFRB),
- IMX_PINCTRL_PIN(MX27_PAD_NFCLE),
- IMX_PINCTRL_PIN(MX27_PAD_NFWP_B),
- IMX_PINCTRL_PIN(MX27_PAD_NFCE_B),
- IMX_PINCTRL_PIN(MX27_PAD_NFALE),
- IMX_PINCTRL_PIN(MX27_PAD_NFRE_B),
- IMX_PINCTRL_PIN(MX27_PAD_NFWE_B),
- IMX_PINCTRL_PIN(MX27_PAD_PC_POE),
- IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B),
- IMX_PINCTRL_PIN(MX27_PAD_IOIS16),
- IMX_PINCTRL_PIN(MX27_PAD_PC_RST),
- IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2),
- IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1),
- IMX_PINCTRL_PIN(MX27_PAD_PC_VS2),
- IMX_PINCTRL_PIN(MX27_PAD_PC_VS1),
- IMX_PINCTRL_PIN(MX27_PAD_CLKO),
- IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON),
- IMX_PINCTRL_PIN(MX27_PAD_PC_READY),
- IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B),
- IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B),
- IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B),
- IMX_PINCTRL_PIN(MX27_PAD_CS4_B),
- IMX_PINCTRL_PIN(MX27_PAD_CS5_B),
- IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15),
-};
-
-static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
- .pins = imx27_pinctrl_pads,
- .npins = ARRAY_SIZE(imx27_pinctrl_pads),
-};
-
-static struct of_device_id imx27_pinctrl_of_match[] = {
- { .compatible = "fsl,imx27-iomuxc", },
- { /* sentinel */ }
-};
-
-static int imx27_pinctrl_probe(struct platform_device *pdev)
-{
- return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info);
-}
-
-static struct platform_driver imx27_pinctrl_driver = {
- .driver = {
- .name = "imx27-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = of_match_ptr(imx27_pinctrl_of_match),
- },
- .probe = imx27_pinctrl_probe,
- .remove = imx1_pinctrl_core_remove,
-};
-
-static int __init imx27_pinctrl_init(void)
-{
- return platform_driver_register(&imx27_pinctrl_driver);
-}
-arch_initcall(imx27_pinctrl_init);
-
-static void __exit imx27_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx27_pinctrl_driver);
-}
-module_exit(imx27_pinctrl_exit);
-MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>");
-MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include "pinctrl-mxs.h"
-
-enum imx28_pin_enum {
- GPMI_D00 = PINID(0, 0),
- GPMI_D01 = PINID(0, 1),
- GPMI_D02 = PINID(0, 2),
- GPMI_D03 = PINID(0, 3),
- GPMI_D04 = PINID(0, 4),
- GPMI_D05 = PINID(0, 5),
- GPMI_D06 = PINID(0, 6),
- GPMI_D07 = PINID(0, 7),
- GPMI_CE0N = PINID(0, 16),
- GPMI_CE1N = PINID(0, 17),
- GPMI_CE2N = PINID(0, 18),
- GPMI_CE3N = PINID(0, 19),
- GPMI_RDY0 = PINID(0, 20),
- GPMI_RDY1 = PINID(0, 21),
- GPMI_RDY2 = PINID(0, 22),
- GPMI_RDY3 = PINID(0, 23),
- GPMI_RDN = PINID(0, 24),
- GPMI_WRN = PINID(0, 25),
- GPMI_ALE = PINID(0, 26),
- GPMI_CLE = PINID(0, 27),
- GPMI_RESETN = PINID(0, 28),
- LCD_D00 = PINID(1, 0),
- LCD_D01 = PINID(1, 1),
- LCD_D02 = PINID(1, 2),
- LCD_D03 = PINID(1, 3),
- LCD_D04 = PINID(1, 4),
- LCD_D05 = PINID(1, 5),
- LCD_D06 = PINID(1, 6),
- LCD_D07 = PINID(1, 7),
- LCD_D08 = PINID(1, 8),
- LCD_D09 = PINID(1, 9),
- LCD_D10 = PINID(1, 10),
- LCD_D11 = PINID(1, 11),
- LCD_D12 = PINID(1, 12),
- LCD_D13 = PINID(1, 13),
- LCD_D14 = PINID(1, 14),
- LCD_D15 = PINID(1, 15),
- LCD_D16 = PINID(1, 16),
- LCD_D17 = PINID(1, 17),
- LCD_D18 = PINID(1, 18),
- LCD_D19 = PINID(1, 19),
- LCD_D20 = PINID(1, 20),
- LCD_D21 = PINID(1, 21),
- LCD_D22 = PINID(1, 22),
- LCD_D23 = PINID(1, 23),
- LCD_RD_E = PINID(1, 24),
- LCD_WR_RWN = PINID(1, 25),
- LCD_RS = PINID(1, 26),
- LCD_CS = PINID(1, 27),
- LCD_VSYNC = PINID(1, 28),
- LCD_HSYNC = PINID(1, 29),
- LCD_DOTCLK = PINID(1, 30),
- LCD_ENABLE = PINID(1, 31),
- SSP0_DATA0 = PINID(2, 0),
- SSP0_DATA1 = PINID(2, 1),
- SSP0_DATA2 = PINID(2, 2),
- SSP0_DATA3 = PINID(2, 3),
- SSP0_DATA4 = PINID(2, 4),
- SSP0_DATA5 = PINID(2, 5),
- SSP0_DATA6 = PINID(2, 6),
- SSP0_DATA7 = PINID(2, 7),
- SSP0_CMD = PINID(2, 8),
- SSP0_DETECT = PINID(2, 9),
- SSP0_SCK = PINID(2, 10),
- SSP1_SCK = PINID(2, 12),
- SSP1_CMD = PINID(2, 13),
- SSP1_DATA0 = PINID(2, 14),
- SSP1_DATA3 = PINID(2, 15),
- SSP2_SCK = PINID(2, 16),
- SSP2_MOSI = PINID(2, 17),
- SSP2_MISO = PINID(2, 18),
- SSP2_SS0 = PINID(2, 19),
- SSP2_SS1 = PINID(2, 20),
- SSP2_SS2 = PINID(2, 21),
- SSP3_SCK = PINID(2, 24),
- SSP3_MOSI = PINID(2, 25),
- SSP3_MISO = PINID(2, 26),
- SSP3_SS0 = PINID(2, 27),
- AUART0_RX = PINID(3, 0),
- AUART0_TX = PINID(3, 1),
- AUART0_CTS = PINID(3, 2),
- AUART0_RTS = PINID(3, 3),
- AUART1_RX = PINID(3, 4),
- AUART1_TX = PINID(3, 5),
- AUART1_CTS = PINID(3, 6),
- AUART1_RTS = PINID(3, 7),
- AUART2_RX = PINID(3, 8),
- AUART2_TX = PINID(3, 9),
- AUART2_CTS = PINID(3, 10),
- AUART2_RTS = PINID(3, 11),
- AUART3_RX = PINID(3, 12),
- AUART3_TX = PINID(3, 13),
- AUART3_CTS = PINID(3, 14),
- AUART3_RTS = PINID(3, 15),
- PWM0 = PINID(3, 16),
- PWM1 = PINID(3, 17),
- PWM2 = PINID(3, 18),
- SAIF0_MCLK = PINID(3, 20),
- SAIF0_LRCLK = PINID(3, 21),
- SAIF0_BITCLK = PINID(3, 22),
- SAIF0_SDATA0 = PINID(3, 23),
- I2C0_SCL = PINID(3, 24),
- I2C0_SDA = PINID(3, 25),
- SAIF1_SDATA0 = PINID(3, 26),
- SPDIF = PINID(3, 27),
- PWM3 = PINID(3, 28),
- PWM4 = PINID(3, 29),
- LCD_RESET = PINID(3, 30),
- ENET0_MDC = PINID(4, 0),
- ENET0_MDIO = PINID(4, 1),
- ENET0_RX_EN = PINID(4, 2),
- ENET0_RXD0 = PINID(4, 3),
- ENET0_RXD1 = PINID(4, 4),
- ENET0_TX_CLK = PINID(4, 5),
- ENET0_TX_EN = PINID(4, 6),
- ENET0_TXD0 = PINID(4, 7),
- ENET0_TXD1 = PINID(4, 8),
- ENET0_RXD2 = PINID(4, 9),
- ENET0_RXD3 = PINID(4, 10),
- ENET0_TXD2 = PINID(4, 11),
- ENET0_TXD3 = PINID(4, 12),
- ENET0_RX_CLK = PINID(4, 13),
- ENET0_COL = PINID(4, 14),
- ENET0_CRS = PINID(4, 15),
- ENET_CLK = PINID(4, 16),
- JTAG_RTCK = PINID(4, 20),
- EMI_D00 = PINID(5, 0),
- EMI_D01 = PINID(5, 1),
- EMI_D02 = PINID(5, 2),
- EMI_D03 = PINID(5, 3),
- EMI_D04 = PINID(5, 4),
- EMI_D05 = PINID(5, 5),
- EMI_D06 = PINID(5, 6),
- EMI_D07 = PINID(5, 7),
- EMI_D08 = PINID(5, 8),
- EMI_D09 = PINID(5, 9),
- EMI_D10 = PINID(5, 10),
- EMI_D11 = PINID(5, 11),
- EMI_D12 = PINID(5, 12),
- EMI_D13 = PINID(5, 13),
- EMI_D14 = PINID(5, 14),
- EMI_D15 = PINID(5, 15),
- EMI_ODT0 = PINID(5, 16),
- EMI_DQM0 = PINID(5, 17),
- EMI_ODT1 = PINID(5, 18),
- EMI_DQM1 = PINID(5, 19),
- EMI_DDR_OPEN_FB = PINID(5, 20),
- EMI_CLK = PINID(5, 21),
- EMI_DQS0 = PINID(5, 22),
- EMI_DQS1 = PINID(5, 23),
- EMI_DDR_OPEN = PINID(5, 26),
- EMI_A00 = PINID(6, 0),
- EMI_A01 = PINID(6, 1),
- EMI_A02 = PINID(6, 2),
- EMI_A03 = PINID(6, 3),
- EMI_A04 = PINID(6, 4),
- EMI_A05 = PINID(6, 5),
- EMI_A06 = PINID(6, 6),
- EMI_A07 = PINID(6, 7),
- EMI_A08 = PINID(6, 8),
- EMI_A09 = PINID(6, 9),
- EMI_A10 = PINID(6, 10),
- EMI_A11 = PINID(6, 11),
- EMI_A12 = PINID(6, 12),
- EMI_A13 = PINID(6, 13),
- EMI_A14 = PINID(6, 14),
- EMI_BA0 = PINID(6, 16),
- EMI_BA1 = PINID(6, 17),
- EMI_BA2 = PINID(6, 18),
- EMI_CASN = PINID(6, 19),
- EMI_RASN = PINID(6, 20),
- EMI_WEN = PINID(6, 21),
- EMI_CE0N = PINID(6, 22),
- EMI_CE1N = PINID(6, 23),
- EMI_CKE = PINID(6, 24),
-};
-
-static const struct pinctrl_pin_desc imx28_pins[] = {
- MXS_PINCTRL_PIN(GPMI_D00),
- MXS_PINCTRL_PIN(GPMI_D01),
- MXS_PINCTRL_PIN(GPMI_D02),
- MXS_PINCTRL_PIN(GPMI_D03),
- MXS_PINCTRL_PIN(GPMI_D04),
- MXS_PINCTRL_PIN(GPMI_D05),
- MXS_PINCTRL_PIN(GPMI_D06),
- MXS_PINCTRL_PIN(GPMI_D07),
- MXS_PINCTRL_PIN(GPMI_CE0N),
- MXS_PINCTRL_PIN(GPMI_CE1N),
- MXS_PINCTRL_PIN(GPMI_CE2N),
- MXS_PINCTRL_PIN(GPMI_CE3N),
- MXS_PINCTRL_PIN(GPMI_RDY0),
- MXS_PINCTRL_PIN(GPMI_RDY1),
- MXS_PINCTRL_PIN(GPMI_RDY2),
- MXS_PINCTRL_PIN(GPMI_RDY3),
- MXS_PINCTRL_PIN(GPMI_RDN),
- MXS_PINCTRL_PIN(GPMI_WRN),
- MXS_PINCTRL_PIN(GPMI_ALE),
- MXS_PINCTRL_PIN(GPMI_CLE),
- MXS_PINCTRL_PIN(GPMI_RESETN),
- MXS_PINCTRL_PIN(LCD_D00),
- MXS_PINCTRL_PIN(LCD_D01),
- MXS_PINCTRL_PIN(LCD_D02),
- MXS_PINCTRL_PIN(LCD_D03),
- MXS_PINCTRL_PIN(LCD_D04),
- MXS_PINCTRL_PIN(LCD_D05),
- MXS_PINCTRL_PIN(LCD_D06),
- MXS_PINCTRL_PIN(LCD_D07),
- MXS_PINCTRL_PIN(LCD_D08),
- MXS_PINCTRL_PIN(LCD_D09),
- MXS_PINCTRL_PIN(LCD_D10),
- MXS_PINCTRL_PIN(LCD_D11),
- MXS_PINCTRL_PIN(LCD_D12),
- MXS_PINCTRL_PIN(LCD_D13),
- MXS_PINCTRL_PIN(LCD_D14),
- MXS_PINCTRL_PIN(LCD_D15),
- MXS_PINCTRL_PIN(LCD_D16),
- MXS_PINCTRL_PIN(LCD_D17),
- MXS_PINCTRL_PIN(LCD_D18),
- MXS_PINCTRL_PIN(LCD_D19),
- MXS_PINCTRL_PIN(LCD_D20),
- MXS_PINCTRL_PIN(LCD_D21),
- MXS_PINCTRL_PIN(LCD_D22),
- MXS_PINCTRL_PIN(LCD_D23),
- MXS_PINCTRL_PIN(LCD_RD_E),
- MXS_PINCTRL_PIN(LCD_WR_RWN),
- MXS_PINCTRL_PIN(LCD_RS),
- MXS_PINCTRL_PIN(LCD_CS),
- MXS_PINCTRL_PIN(LCD_VSYNC),
- MXS_PINCTRL_PIN(LCD_HSYNC),
- MXS_PINCTRL_PIN(LCD_DOTCLK),
- MXS_PINCTRL_PIN(LCD_ENABLE),
- MXS_PINCTRL_PIN(SSP0_DATA0),
- MXS_PINCTRL_PIN(SSP0_DATA1),
- MXS_PINCTRL_PIN(SSP0_DATA2),
- MXS_PINCTRL_PIN(SSP0_DATA3),
- MXS_PINCTRL_PIN(SSP0_DATA4),
- MXS_PINCTRL_PIN(SSP0_DATA5),
- MXS_PINCTRL_PIN(SSP0_DATA6),
- MXS_PINCTRL_PIN(SSP0_DATA7),
- MXS_PINCTRL_PIN(SSP0_CMD),
- MXS_PINCTRL_PIN(SSP0_DETECT),
- MXS_PINCTRL_PIN(SSP0_SCK),
- MXS_PINCTRL_PIN(SSP1_SCK),
- MXS_PINCTRL_PIN(SSP1_CMD),
- MXS_PINCTRL_PIN(SSP1_DATA0),
- MXS_PINCTRL_PIN(SSP1_DATA3),
- MXS_PINCTRL_PIN(SSP2_SCK),
- MXS_PINCTRL_PIN(SSP2_MOSI),
- MXS_PINCTRL_PIN(SSP2_MISO),
- MXS_PINCTRL_PIN(SSP2_SS0),
- MXS_PINCTRL_PIN(SSP2_SS1),
- MXS_PINCTRL_PIN(SSP2_SS2),
- MXS_PINCTRL_PIN(SSP3_SCK),
- MXS_PINCTRL_PIN(SSP3_MOSI),
- MXS_PINCTRL_PIN(SSP3_MISO),
- MXS_PINCTRL_PIN(SSP3_SS0),
- MXS_PINCTRL_PIN(AUART0_RX),
- MXS_PINCTRL_PIN(AUART0_TX),
- MXS_PINCTRL_PIN(AUART0_CTS),
- MXS_PINCTRL_PIN(AUART0_RTS),
- MXS_PINCTRL_PIN(AUART1_RX),
- MXS_PINCTRL_PIN(AUART1_TX),
- MXS_PINCTRL_PIN(AUART1_CTS),
- MXS_PINCTRL_PIN(AUART1_RTS),
- MXS_PINCTRL_PIN(AUART2_RX),
- MXS_PINCTRL_PIN(AUART2_TX),
- MXS_PINCTRL_PIN(AUART2_CTS),
- MXS_PINCTRL_PIN(AUART2_RTS),
- MXS_PINCTRL_PIN(AUART3_RX),
- MXS_PINCTRL_PIN(AUART3_TX),
- MXS_PINCTRL_PIN(AUART3_CTS),
- MXS_PINCTRL_PIN(AUART3_RTS),
- MXS_PINCTRL_PIN(PWM0),
- MXS_PINCTRL_PIN(PWM1),
- MXS_PINCTRL_PIN(PWM2),
- MXS_PINCTRL_PIN(SAIF0_MCLK),
- MXS_PINCTRL_PIN(SAIF0_LRCLK),
- MXS_PINCTRL_PIN(SAIF0_BITCLK),
- MXS_PINCTRL_PIN(SAIF0_SDATA0),
- MXS_PINCTRL_PIN(I2C0_SCL),
- MXS_PINCTRL_PIN(I2C0_SDA),
- MXS_PINCTRL_PIN(SAIF1_SDATA0),
- MXS_PINCTRL_PIN(SPDIF),
- MXS_PINCTRL_PIN(PWM3),
- MXS_PINCTRL_PIN(PWM4),
- MXS_PINCTRL_PIN(LCD_RESET),
- MXS_PINCTRL_PIN(ENET0_MDC),
- MXS_PINCTRL_PIN(ENET0_MDIO),
- MXS_PINCTRL_PIN(ENET0_RX_EN),
- MXS_PINCTRL_PIN(ENET0_RXD0),
- MXS_PINCTRL_PIN(ENET0_RXD1),
- MXS_PINCTRL_PIN(ENET0_TX_CLK),
- MXS_PINCTRL_PIN(ENET0_TX_EN),
- MXS_PINCTRL_PIN(ENET0_TXD0),
- MXS_PINCTRL_PIN(ENET0_TXD1),
- MXS_PINCTRL_PIN(ENET0_RXD2),
- MXS_PINCTRL_PIN(ENET0_RXD3),
- MXS_PINCTRL_PIN(ENET0_TXD2),
- MXS_PINCTRL_PIN(ENET0_TXD3),
- MXS_PINCTRL_PIN(ENET0_RX_CLK),
- MXS_PINCTRL_PIN(ENET0_COL),
- MXS_PINCTRL_PIN(ENET0_CRS),
- MXS_PINCTRL_PIN(ENET_CLK),
- MXS_PINCTRL_PIN(JTAG_RTCK),
- MXS_PINCTRL_PIN(EMI_D00),
- MXS_PINCTRL_PIN(EMI_D01),
- MXS_PINCTRL_PIN(EMI_D02),
- MXS_PINCTRL_PIN(EMI_D03),
- MXS_PINCTRL_PIN(EMI_D04),
- MXS_PINCTRL_PIN(EMI_D05),
- MXS_PINCTRL_PIN(EMI_D06),
- MXS_PINCTRL_PIN(EMI_D07),
- MXS_PINCTRL_PIN(EMI_D08),
- MXS_PINCTRL_PIN(EMI_D09),
- MXS_PINCTRL_PIN(EMI_D10),
- MXS_PINCTRL_PIN(EMI_D11),
- MXS_PINCTRL_PIN(EMI_D12),
- MXS_PINCTRL_PIN(EMI_D13),
- MXS_PINCTRL_PIN(EMI_D14),
- MXS_PINCTRL_PIN(EMI_D15),
- MXS_PINCTRL_PIN(EMI_ODT0),
- MXS_PINCTRL_PIN(EMI_DQM0),
- MXS_PINCTRL_PIN(EMI_ODT1),
- MXS_PINCTRL_PIN(EMI_DQM1),
- MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
- MXS_PINCTRL_PIN(EMI_CLK),
- MXS_PINCTRL_PIN(EMI_DQS0),
- MXS_PINCTRL_PIN(EMI_DQS1),
- MXS_PINCTRL_PIN(EMI_DDR_OPEN),
- MXS_PINCTRL_PIN(EMI_A00),
- MXS_PINCTRL_PIN(EMI_A01),
- MXS_PINCTRL_PIN(EMI_A02),
- MXS_PINCTRL_PIN(EMI_A03),
- MXS_PINCTRL_PIN(EMI_A04),
- MXS_PINCTRL_PIN(EMI_A05),
- MXS_PINCTRL_PIN(EMI_A06),
- MXS_PINCTRL_PIN(EMI_A07),
- MXS_PINCTRL_PIN(EMI_A08),
- MXS_PINCTRL_PIN(EMI_A09),
- MXS_PINCTRL_PIN(EMI_A10),
- MXS_PINCTRL_PIN(EMI_A11),
- MXS_PINCTRL_PIN(EMI_A12),
- MXS_PINCTRL_PIN(EMI_A13),
- MXS_PINCTRL_PIN(EMI_A14),
- MXS_PINCTRL_PIN(EMI_BA0),
- MXS_PINCTRL_PIN(EMI_BA1),
- MXS_PINCTRL_PIN(EMI_BA2),
- MXS_PINCTRL_PIN(EMI_CASN),
- MXS_PINCTRL_PIN(EMI_RASN),
- MXS_PINCTRL_PIN(EMI_WEN),
- MXS_PINCTRL_PIN(EMI_CE0N),
- MXS_PINCTRL_PIN(EMI_CE1N),
- MXS_PINCTRL_PIN(EMI_CKE),
-};
-
-static struct mxs_regs imx28_regs = {
- .muxsel = 0x100,
- .drive = 0x300,
- .pull = 0x600,
-};
-
-static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
- .regs = &imx28_regs,
- .pins = imx28_pins,
- .npins = ARRAY_SIZE(imx28_pins),
-};
-
-static int imx28_pinctrl_probe(struct platform_device *pdev)
-{
- return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
-}
-
-static struct of_device_id imx28_pinctrl_of_match[] = {
- { .compatible = "fsl,imx28-pinctrl", },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match);
-
-static struct platform_driver imx28_pinctrl_driver = {
- .driver = {
- .name = "imx28-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = imx28_pinctrl_of_match,
- },
- .probe = imx28_pinctrl_probe,
- .remove = mxs_pinctrl_remove,
-};
-
-static int __init imx28_pinctrl_init(void)
-{
- return platform_driver_register(&imx28_pinctrl_driver);
-}
-postcore_initcall(imx28_pinctrl_init);
-
-static void __exit imx28_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx28_pinctrl_driver);
-}
-module_exit(imx28_pinctrl_exit);
-
-MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
-MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * imx35 pinctrl driver.
- *
- * This driver was mostly copied from the imx51 pinctrl driver which has:
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro, Inc.
- *
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#include "pinctrl-imx.h"
-
-enum imx35_pads {
- MX35_PAD_RESERVE0 = 0,
- MX35_PAD_CAPTURE = 1,
- MX35_PAD_COMPARE = 2,
- MX35_PAD_WDOG_RST = 3,
- MX35_PAD_GPIO1_0 = 4,
- MX35_PAD_GPIO1_1 = 5,
- MX35_PAD_GPIO2_0 = 6,
- MX35_PAD_GPIO3_0 = 7,
- MX35_PAD_CLKO = 8,
- MX35_PAD_VSTBY = 9,
- MX35_PAD_A0 = 10,
- MX35_PAD_A1 = 11,
- MX35_PAD_A2 = 12,
- MX35_PAD_A3 = 13,
- MX35_PAD_A4 = 14,
- MX35_PAD_A5 = 15,
- MX35_PAD_A6 = 16,
- MX35_PAD_A7 = 17,
- MX35_PAD_A8 = 18,
- MX35_PAD_A9 = 19,
- MX35_PAD_A10 = 20,
- MX35_PAD_MA10 = 21,
- MX35_PAD_A11 = 22,
- MX35_PAD_A12 = 23,
- MX35_PAD_A13 = 24,
- MX35_PAD_A14 = 25,
- MX35_PAD_A15 = 26,
- MX35_PAD_A16 = 27,
- MX35_PAD_A17 = 28,
- MX35_PAD_A18 = 29,
- MX35_PAD_A19 = 30,
- MX35_PAD_A20 = 31,
- MX35_PAD_A21 = 32,
- MX35_PAD_A22 = 33,
- MX35_PAD_A23 = 34,
- MX35_PAD_A24 = 35,
- MX35_PAD_A25 = 36,
- MX35_PAD_EB0 = 37,
- MX35_PAD_EB1 = 38,
- MX35_PAD_OE = 39,
- MX35_PAD_CS0 = 40,
- MX35_PAD_CS1 = 41,
- MX35_PAD_CS2 = 42,
- MX35_PAD_CS3 = 43,
- MX35_PAD_CS4 = 44,
- MX35_PAD_CS5 = 45,
- MX35_PAD_NF_CE0 = 46,
- MX35_PAD_LBA = 47,
- MX35_PAD_BCLK = 48,
- MX35_PAD_RW = 49,
- MX35_PAD_NFWE_B = 50,
- MX35_PAD_NFRE_B = 51,
- MX35_PAD_NFALE = 52,
- MX35_PAD_NFCLE = 53,
- MX35_PAD_NFWP_B = 54,
- MX35_PAD_NFRB = 55,
- MX35_PAD_CSI_D8 = 56,
- MX35_PAD_CSI_D9 = 57,
- MX35_PAD_CSI_D10 = 58,
- MX35_PAD_CSI_D11 = 59,
- MX35_PAD_CSI_D12 = 60,
- MX35_PAD_CSI_D13 = 61,
- MX35_PAD_CSI_D14 = 62,
- MX35_PAD_CSI_D15 = 63,
- MX35_PAD_CSI_MCLK = 64,
- MX35_PAD_CSI_VSYNC = 65,
- MX35_PAD_CSI_HSYNC = 66,
- MX35_PAD_CSI_PIXCLK = 67,
- MX35_PAD_I2C1_CLK = 68,
- MX35_PAD_I2C1_DAT = 69,
- MX35_PAD_I2C2_CLK = 70,
- MX35_PAD_I2C2_DAT = 71,
- MX35_PAD_STXD4 = 72,
- MX35_PAD_SRXD4 = 73,
- MX35_PAD_SCK4 = 74,
- MX35_PAD_STXFS4 = 75,
- MX35_PAD_STXD5 = 76,
- MX35_PAD_SRXD5 = 77,
- MX35_PAD_SCK5 = 78,
- MX35_PAD_STXFS5 = 79,
- MX35_PAD_SCKR = 80,
- MX35_PAD_FSR = 81,
- MX35_PAD_HCKR = 82,
- MX35_PAD_SCKT = 83,
- MX35_PAD_FST = 84,
- MX35_PAD_HCKT = 85,
- MX35_PAD_TX5_RX0 = 86,
- MX35_PAD_TX4_RX1 = 87,
- MX35_PAD_TX3_RX2 = 88,
- MX35_PAD_TX2_RX3 = 89,
- MX35_PAD_TX1 = 90,
- MX35_PAD_TX0 = 91,
- MX35_PAD_CSPI1_MOSI = 92,
- MX35_PAD_CSPI1_MISO = 93,
- MX35_PAD_CSPI1_SS0 = 94,
- MX35_PAD_CSPI1_SS1 = 95,
- MX35_PAD_CSPI1_SCLK = 96,
- MX35_PAD_CSPI1_SPI_RDY = 97,
- MX35_PAD_RXD1 = 98,
- MX35_PAD_TXD1 = 99,
- MX35_PAD_RTS1 = 100,
- MX35_PAD_CTS1 = 101,
- MX35_PAD_RXD2 = 102,
- MX35_PAD_TXD2 = 103,
- MX35_PAD_RTS2 = 104,
- MX35_PAD_CTS2 = 105,
- MX35_PAD_USBOTG_PWR = 106,
- MX35_PAD_USBOTG_OC = 107,
- MX35_PAD_LD0 = 108,
- MX35_PAD_LD1 = 109,
- MX35_PAD_LD2 = 110,
- MX35_PAD_LD3 = 111,
- MX35_PAD_LD4 = 112,
- MX35_PAD_LD5 = 113,
- MX35_PAD_LD6 = 114,
- MX35_PAD_LD7 = 115,
- MX35_PAD_LD8 = 116,
- MX35_PAD_LD9 = 117,
- MX35_PAD_LD10 = 118,
- MX35_PAD_LD11 = 119,
- MX35_PAD_LD12 = 120,
- MX35_PAD_LD13 = 121,
- MX35_PAD_LD14 = 122,
- MX35_PAD_LD15 = 123,
- MX35_PAD_LD16 = 124,
- MX35_PAD_LD17 = 125,
- MX35_PAD_LD18 = 126,
- MX35_PAD_LD19 = 127,
- MX35_PAD_LD20 = 128,
- MX35_PAD_LD21 = 129,
- MX35_PAD_LD22 = 130,
- MX35_PAD_LD23 = 131,
- MX35_PAD_D3_HSYNC = 132,
- MX35_PAD_D3_FPSHIFT = 133,
- MX35_PAD_D3_DRDY = 134,
- MX35_PAD_CONTRAST = 135,
- MX35_PAD_D3_VSYNC = 136,
- MX35_PAD_D3_REV = 137,
- MX35_PAD_D3_CLS = 138,
- MX35_PAD_D3_SPL = 139,
- MX35_PAD_SD1_CMD = 140,
- MX35_PAD_SD1_CLK = 141,
- MX35_PAD_SD1_DATA0 = 142,
- MX35_PAD_SD1_DATA1 = 143,
- MX35_PAD_SD1_DATA2 = 144,
- MX35_PAD_SD1_DATA3 = 145,
- MX35_PAD_SD2_CMD = 146,
- MX35_PAD_SD2_CLK = 147,
- MX35_PAD_SD2_DATA0 = 148,
- MX35_PAD_SD2_DATA1 = 149,
- MX35_PAD_SD2_DATA2 = 150,
- MX35_PAD_SD2_DATA3 = 151,
- MX35_PAD_ATA_CS0 = 152,
- MX35_PAD_ATA_CS1 = 153,
- MX35_PAD_ATA_DIOR = 154,
- MX35_PAD_ATA_DIOW = 155,
- MX35_PAD_ATA_DMACK = 156,
- MX35_PAD_ATA_RESET_B = 157,
- MX35_PAD_ATA_IORDY = 158,
- MX35_PAD_ATA_DATA0 = 159,
- MX35_PAD_ATA_DATA1 = 160,
- MX35_PAD_ATA_DATA2 = 161,
- MX35_PAD_ATA_DATA3 = 162,
- MX35_PAD_ATA_DATA4 = 163,
- MX35_PAD_ATA_DATA5 = 164,
- MX35_PAD_ATA_DATA6 = 165,
- MX35_PAD_ATA_DATA7 = 166,
- MX35_PAD_ATA_DATA8 = 167,
- MX35_PAD_ATA_DATA9 = 168,
- MX35_PAD_ATA_DATA10 = 169,
- MX35_PAD_ATA_DATA11 = 170,
- MX35_PAD_ATA_DATA12 = 171,
- MX35_PAD_ATA_DATA13 = 172,
- MX35_PAD_ATA_DATA14 = 173,
- MX35_PAD_ATA_DATA15 = 174,
- MX35_PAD_ATA_INTRQ = 175,
- MX35_PAD_ATA_BUFF_EN = 176,
- MX35_PAD_ATA_DMARQ = 177,
- MX35_PAD_ATA_DA0 = 178,
- MX35_PAD_ATA_DA1 = 179,
- MX35_PAD_ATA_DA2 = 180,
- MX35_PAD_MLB_CLK = 181,
- MX35_PAD_MLB_DAT = 182,
- MX35_PAD_MLB_SIG = 183,
- MX35_PAD_FEC_TX_CLK = 184,
- MX35_PAD_FEC_RX_CLK = 185,
- MX35_PAD_FEC_RX_DV = 186,
- MX35_PAD_FEC_COL = 187,
- MX35_PAD_FEC_RDATA0 = 188,
- MX35_PAD_FEC_TDATA0 = 189,
- MX35_PAD_FEC_TX_EN = 190,
- MX35_PAD_FEC_MDC = 191,
- MX35_PAD_FEC_MDIO = 192,
- MX35_PAD_FEC_TX_ERR = 193,
- MX35_PAD_FEC_RX_ERR = 194,
- MX35_PAD_FEC_CRS = 195,
- MX35_PAD_FEC_RDATA1 = 196,
- MX35_PAD_FEC_TDATA1 = 197,
- MX35_PAD_FEC_RDATA2 = 198,
- MX35_PAD_FEC_TDATA2 = 199,
- MX35_PAD_FEC_RDATA3 = 200,
- MX35_PAD_FEC_TDATA3 = 201,
- MX35_PAD_RESERVE1 = 202,
- MX35_PAD_RESERVE2 = 203,
- MX35_PAD_RESERVE3 = 204,
- MX35_PAD_RESERVE4 = 205,
- MX35_PAD_RESERVE5 = 206,
- MX35_PAD_RESERVE6 = 207,
- MX35_PAD_RESERVE7 = 208,
- MX35_PAD_RESET_IN_B = 209,
- MX35_PAD_POR_B = 210,
- MX35_PAD_RESERVE8 = 211,
- MX35_PAD_BOOT_MODE0 = 212,
- MX35_PAD_BOOT_MODE1 = 213,
- MX35_PAD_CLK_MODE0 = 214,
- MX35_PAD_CLK_MODE1 = 215,
- MX35_PAD_POWER_FAIL = 216,
- MX35_PAD_RESERVE9 = 217,
- MX35_PAD_RESERVE10 = 218,
- MX35_PAD_RESERVE11 = 219,
- MX35_PAD_RESERVE12 = 220,
- MX35_PAD_RESERVE13 = 221,
- MX35_PAD_RESERVE14 = 222,
- MX35_PAD_RESERVE15 = 223,
- MX35_PAD_RESERVE16 = 224,
- MX35_PAD_RESERVE17 = 225,
- MX35_PAD_RESERVE18 = 226,
- MX35_PAD_RESERVE19 = 227,
- MX35_PAD_RESERVE20 = 228,
- MX35_PAD_RESERVE21 = 229,
- MX35_PAD_RESERVE22 = 230,
- MX35_PAD_RESERVE23 = 231,
- MX35_PAD_RESERVE24 = 232,
- MX35_PAD_RESERVE25 = 233,
- MX35_PAD_RESERVE26 = 234,
- MX35_PAD_RESERVE27 = 235,
- MX35_PAD_RESERVE28 = 236,
- MX35_PAD_RESERVE29 = 237,
- MX35_PAD_RESERVE30 = 238,
- MX35_PAD_RESERVE31 = 239,
- MX35_PAD_RESERVE32 = 240,
- MX35_PAD_RESERVE33 = 241,
- MX35_PAD_RESERVE34 = 242,
- MX35_PAD_RESERVE35 = 243,
- MX35_PAD_RESERVE36 = 244,
- MX35_PAD_SDBA1 = 245,
- MX35_PAD_SDBA0 = 246,
- MX35_PAD_SD0 = 247,
- MX35_PAD_SD1 = 248,
- MX35_PAD_SD2 = 249,
- MX35_PAD_SD3 = 250,
- MX35_PAD_SD4 = 251,
- MX35_PAD_SD5 = 252,
- MX35_PAD_SD6 = 253,
- MX35_PAD_SD7 = 254,
- MX35_PAD_SD8 = 255,
- MX35_PAD_SD9 = 256,
- MX35_PAD_SD10 = 257,
- MX35_PAD_SD11 = 258,
- MX35_PAD_SD12 = 259,
- MX35_PAD_SD13 = 260,
- MX35_PAD_SD14 = 261,
- MX35_PAD_SD15 = 262,
- MX35_PAD_SD16 = 263,
- MX35_PAD_SD17 = 264,
- MX35_PAD_SD18 = 265,
- MX35_PAD_SD19 = 266,
- MX35_PAD_SD20 = 267,
- MX35_PAD_SD21 = 268,
- MX35_PAD_SD22 = 269,
- MX35_PAD_SD23 = 270,
- MX35_PAD_SD24 = 271,
- MX35_PAD_SD25 = 272,
- MX35_PAD_SD26 = 273,
- MX35_PAD_SD27 = 274,
- MX35_PAD_SD28 = 275,
- MX35_PAD_SD29 = 276,
- MX35_PAD_SD30 = 277,
- MX35_PAD_SD31 = 278,
- MX35_PAD_DQM0 = 279,
- MX35_PAD_DQM1 = 280,
- MX35_PAD_DQM2 = 281,
- MX35_PAD_DQM3 = 282,
- MX35_PAD_RESERVE37 = 283,
- MX35_PAD_RESERVE38 = 284,
- MX35_PAD_RESERVE39 = 285,
- MX35_PAD_RESERVE40 = 286,
- MX35_PAD_RESERVE41 = 287,
- MX35_PAD_RESERVE42 = 288,
- MX35_PAD_RESERVE43 = 289,
- MX35_PAD_RESERVE44 = 290,
- MX35_PAD_RESERVE45 = 291,
- MX35_PAD_RESERVE46 = 292,
- MX35_PAD_ECB = 293,
- MX35_PAD_RESERVE47 = 294,
- MX35_PAD_RESERVE48 = 295,
- MX35_PAD_RESERVE49 = 296,
- MX35_PAD_RAS = 297,
- MX35_PAD_CAS = 298,
- MX35_PAD_SDWE = 299,
- MX35_PAD_SDCKE0 = 300,
- MX35_PAD_SDCKE1 = 301,
- MX35_PAD_SDCLK = 302,
- MX35_PAD_SDQS0 = 303,
- MX35_PAD_SDQS1 = 304,
- MX35_PAD_SDQS2 = 305,
- MX35_PAD_SDQS3 = 306,
- MX35_PAD_RESERVE50 = 307,
- MX35_PAD_RESERVE51 = 308,
- MX35_PAD_RESERVE52 = 309,
- MX35_PAD_RESERVE53 = 310,
- MX35_PAD_RESERVE54 = 311,
- MX35_PAD_RESERVE55 = 312,
- MX35_PAD_D15 = 313,
- MX35_PAD_D14 = 314,
- MX35_PAD_D13 = 315,
- MX35_PAD_D12 = 316,
- MX35_PAD_D11 = 317,
- MX35_PAD_D10 = 318,
- MX35_PAD_D9 = 319,
- MX35_PAD_D8 = 320,
- MX35_PAD_D7 = 321,
- MX35_PAD_D6 = 322,
- MX35_PAD_D5 = 323,
- MX35_PAD_D4 = 324,
- MX35_PAD_D3 = 325,
- MX35_PAD_D2 = 326,
- MX35_PAD_D1 = 327,
- MX35_PAD_D0 = 328,
- MX35_PAD_RESERVE56 = 329,
- MX35_PAD_RESERVE57 = 330,
- MX35_PAD_RESERVE58 = 331,
- MX35_PAD_RESERVE59 = 332,
- MX35_PAD_RESERVE60 = 333,
- MX35_PAD_RESERVE61 = 334,
- MX35_PAD_RESERVE62 = 335,
- MX35_PAD_RESERVE63 = 336,
- MX35_PAD_RESERVE64 = 337,
- MX35_PAD_RESERVE65 = 338,
- MX35_PAD_RESERVE66 = 339,
- MX35_PAD_RESERVE67 = 340,
- MX35_PAD_RESERVE68 = 341,
- MX35_PAD_RESERVE69 = 342,
- MX35_PAD_RESERVE70 = 343,
- MX35_PAD_RESERVE71 = 344,
- MX35_PAD_RESERVE72 = 345,
- MX35_PAD_RESERVE73 = 346,
- MX35_PAD_RESERVE74 = 347,
- MX35_PAD_RESERVE75 = 348,
- MX35_PAD_RESERVE76 = 349,
- MX35_PAD_RESERVE77 = 350,
- MX35_PAD_RESERVE78 = 351,
- MX35_PAD_RESERVE79 = 352,
- MX35_PAD_RESERVE80 = 353,
- MX35_PAD_RESERVE81 = 354,
- MX35_PAD_RESERVE82 = 355,
- MX35_PAD_RESERVE83 = 356,
- MX35_PAD_RESERVE84 = 357,
- MX35_PAD_RESERVE85 = 358,
- MX35_PAD_RESERVE86 = 359,
- MX35_PAD_RESERVE87 = 360,
- MX35_PAD_RESERVE88 = 361,
- MX35_PAD_RESERVE89 = 362,
- MX35_PAD_RESERVE90 = 363,
- MX35_PAD_RESERVE91 = 364,
- MX35_PAD_RESERVE92 = 365,
- MX35_PAD_RESERVE93 = 366,
- MX35_PAD_RESERVE94 = 367,
- MX35_PAD_RESERVE95 = 368,
- MX35_PAD_RESERVE96 = 369,
- MX35_PAD_RESERVE97 = 370,
- MX35_PAD_RESERVE98 = 371,
- MX35_PAD_RESERVE99 = 372,
- MX35_PAD_RESERVE100 = 373,
- MX35_PAD_RESERVE101 = 374,
- MX35_PAD_RESERVE102 = 375,
- MX35_PAD_RESERVE103 = 376,
- MX35_PAD_RESERVE104 = 377,
- MX35_PAD_RESERVE105 = 378,
- MX35_PAD_RTCK = 379,
- MX35_PAD_TCK = 380,
- MX35_PAD_TMS = 381,
- MX35_PAD_TDI = 382,
- MX35_PAD_TDO = 383,
- MX35_PAD_TRSTB = 384,
- MX35_PAD_DE_B = 385,
- MX35_PAD_SJC_MOD = 386,
- MX35_PAD_RESERVE106 = 387,
- MX35_PAD_RESERVE107 = 388,
- MX35_PAD_RESERVE108 = 389,
- MX35_PAD_RESERVE109 = 390,
- MX35_PAD_RESERVE110 = 391,
- MX35_PAD_RESERVE111 = 392,
- MX35_PAD_RESERVE112 = 393,
- MX35_PAD_RESERVE113 = 394,
- MX35_PAD_RESERVE114 = 395,
- MX35_PAD_RESERVE115 = 396,
- MX35_PAD_RESERVE116 = 397,
- MX35_PAD_RESERVE117 = 398,
- MX35_PAD_RESERVE118 = 399,
- MX35_PAD_RESERVE119 = 400,
- MX35_PAD_RESERVE120 = 401,
- MX35_PAD_RESERVE121 = 402,
- MX35_PAD_RESERVE122 = 403,
- MX35_PAD_RESERVE123 = 404,
- MX35_PAD_RESERVE124 = 405,
- MX35_PAD_RESERVE125 = 406,
- MX35_PAD_RESERVE126 = 407,
- MX35_PAD_RESERVE127 = 408,
- MX35_PAD_RESERVE128 = 409,
- MX35_PAD_RESERVE129 = 410,
- MX35_PAD_RESERVE130 = 411,
- MX35_PAD_RESERVE131 = 412,
- MX35_PAD_RESERVE132 = 413,
- MX35_PAD_RESERVE133 = 414,
- MX35_PAD_RESERVE134 = 415,
- MX35_PAD_RESERVE135 = 416,
- MX35_PAD_RESERVE136 = 417,
- MX35_PAD_RESERVE137 = 418,
- MX35_PAD_RESERVE138 = 419,
- MX35_PAD_RESERVE139 = 420,
- MX35_PAD_RESERVE140 = 421,
- MX35_PAD_RESERVE141 = 422,
- MX35_PAD_RESERVE142 = 423,
- MX35_PAD_RESERVE143 = 424,
- MX35_PAD_RESERVE144 = 425,
- MX35_PAD_RESERVE145 = 426,
- MX35_PAD_RESERVE146 = 427,
- MX35_PAD_RESERVE147 = 428,
- MX35_PAD_RESERVE148 = 429,
- MX35_PAD_RESERVE149 = 430,
- MX35_PAD_RESERVE150 = 431,
- MX35_PAD_RESERVE151 = 432,
- MX35_PAD_RESERVE152 = 433,
- MX35_PAD_RESERVE153 = 434,
- MX35_PAD_RESERVE154 = 435,
- MX35_PAD_RESERVE155 = 436,
- MX35_PAD_RESERVE156 = 437,
- MX35_PAD_RESERVE157 = 438,
- MX35_PAD_RESERVE158 = 439,
- MX35_PAD_RESERVE159 = 440,
- MX35_PAD_RESERVE160 = 441,
- MX35_PAD_RESERVE161 = 442,
- MX35_PAD_RESERVE162 = 443,
- MX35_PAD_RESERVE163 = 444,
- MX35_PAD_RESERVE164 = 445,
- MX35_PAD_RESERVE165 = 446,
- MX35_PAD_RESERVE166 = 447,
- MX35_PAD_RESERVE167 = 448,
- MX35_PAD_RESERVE168 = 449,
- MX35_PAD_RESERVE169 = 450,
- MX35_PAD_RESERVE170 = 451,
- MX35_PAD_RESERVE171 = 452,
- MX35_PAD_RESERVE172 = 453,
- MX35_PAD_RESERVE173 = 454,
- MX35_PAD_RESERVE174 = 455,
- MX35_PAD_RESERVE175 = 456,
- MX35_PAD_RESERVE176 = 457,
- MX35_PAD_RESERVE177 = 458,
- MX35_PAD_RESERVE178 = 459,
- MX35_PAD_RESERVE179 = 460,
- MX35_PAD_RESERVE180 = 461,
- MX35_PAD_RESERVE181 = 462,
- MX35_PAD_RESERVE182 = 463,
- MX35_PAD_RESERVE183 = 464,
- MX35_PAD_RESERVE184 = 465,
- MX35_PAD_RESERVE185 = 466,
- MX35_PAD_RESERVE186 = 467,
- MX35_PAD_RESERVE187 = 468,
- MX35_PAD_RESERVE188 = 469,
- MX35_PAD_RESERVE189 = 470,
- MX35_PAD_RESERVE190 = 471,
- MX35_PAD_RESERVE191 = 472,
- MX35_PAD_RESERVE192 = 473,
- MX35_PAD_RESERVE193 = 474,
- MX35_PAD_RESERVE194 = 475,
- MX35_PAD_RESERVE195 = 476,
- MX35_PAD_RESERVE196 = 477,
- MX35_PAD_RESERVE197 = 478,
- MX35_PAD_RESERVE198 = 479,
- MX35_PAD_RESERVE199 = 480,
- MX35_PAD_RESERVE200 = 481,
- MX35_PAD_RESERVE201 = 482,
- MX35_PAD_EXT_ARMCLK = 483,
- MX35_PAD_TEST_MODE = 484,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE0),
- IMX_PINCTRL_PIN(MX35_PAD_CAPTURE),
- IMX_PINCTRL_PIN(MX35_PAD_COMPARE),
- IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST),
- IMX_PINCTRL_PIN(MX35_PAD_GPIO1_0),
- IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1),
- IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0),
- IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0),
- IMX_PINCTRL_PIN(MX35_PAD_CLKO),
- IMX_PINCTRL_PIN(MX35_PAD_VSTBY),
- IMX_PINCTRL_PIN(MX35_PAD_A0),
- IMX_PINCTRL_PIN(MX35_PAD_A1),
- IMX_PINCTRL_PIN(MX35_PAD_A2),
- IMX_PINCTRL_PIN(MX35_PAD_A3),
- IMX_PINCTRL_PIN(MX35_PAD_A4),
- IMX_PINCTRL_PIN(MX35_PAD_A5),
- IMX_PINCTRL_PIN(MX35_PAD_A6),
- IMX_PINCTRL_PIN(MX35_PAD_A7),
- IMX_PINCTRL_PIN(MX35_PAD_A8),
- IMX_PINCTRL_PIN(MX35_PAD_A9),
- IMX_PINCTRL_PIN(MX35_PAD_A10),
- IMX_PINCTRL_PIN(MX35_PAD_MA10),
- IMX_PINCTRL_PIN(MX35_PAD_A11),
- IMX_PINCTRL_PIN(MX35_PAD_A12),
- IMX_PINCTRL_PIN(MX35_PAD_A13),
- IMX_PINCTRL_PIN(MX35_PAD_A14),
- IMX_PINCTRL_PIN(MX35_PAD_A15),
- IMX_PINCTRL_PIN(MX35_PAD_A16),
- IMX_PINCTRL_PIN(MX35_PAD_A17),
- IMX_PINCTRL_PIN(MX35_PAD_A18),
- IMX_PINCTRL_PIN(MX35_PAD_A19),
- IMX_PINCTRL_PIN(MX35_PAD_A20),
- IMX_PINCTRL_PIN(MX35_PAD_A21),
- IMX_PINCTRL_PIN(MX35_PAD_A22),
- IMX_PINCTRL_PIN(MX35_PAD_A23),
- IMX_PINCTRL_PIN(MX35_PAD_A24),
- IMX_PINCTRL_PIN(MX35_PAD_A25),
- IMX_PINCTRL_PIN(MX35_PAD_EB0),
- IMX_PINCTRL_PIN(MX35_PAD_EB1),
- IMX_PINCTRL_PIN(MX35_PAD_OE),
- IMX_PINCTRL_PIN(MX35_PAD_CS0),
- IMX_PINCTRL_PIN(MX35_PAD_CS1),
- IMX_PINCTRL_PIN(MX35_PAD_CS2),
- IMX_PINCTRL_PIN(MX35_PAD_CS3),
- IMX_PINCTRL_PIN(MX35_PAD_CS4),
- IMX_PINCTRL_PIN(MX35_PAD_CS5),
- IMX_PINCTRL_PIN(MX35_PAD_NF_CE0),
- IMX_PINCTRL_PIN(MX35_PAD_LBA),
- IMX_PINCTRL_PIN(MX35_PAD_BCLK),
- IMX_PINCTRL_PIN(MX35_PAD_RW),
- IMX_PINCTRL_PIN(MX35_PAD_NFWE_B),
- IMX_PINCTRL_PIN(MX35_PAD_NFRE_B),
- IMX_PINCTRL_PIN(MX35_PAD_NFALE),
- IMX_PINCTRL_PIN(MX35_PAD_NFCLE),
- IMX_PINCTRL_PIN(MX35_PAD_NFWP_B),
- IMX_PINCTRL_PIN(MX35_PAD_NFRB),
- IMX_PINCTRL_PIN(MX35_PAD_CSI_D8),
- IMX_PINCTRL_PIN(MX35_PAD_CSI_D9),
- IMX_PINCTRL_PIN(MX35_PAD_CSI_D10),
- IMX_PINCTRL_PIN(MX35_PAD_CSI_D11),
- IMX_PINCTRL_PIN(MX35_PAD_CSI_D12),
- IMX_PINCTRL_PIN(MX35_PAD_CSI_D13),
- IMX_PINCTRL_PIN(MX35_PAD_CSI_D14),
- IMX_PINCTRL_PIN(MX35_PAD_CSI_D15),
- IMX_PINCTRL_PIN(MX35_PAD_CSI_MCLK),
- IMX_PINCTRL_PIN(MX35_PAD_CSI_VSYNC),
- IMX_PINCTRL_PIN(MX35_PAD_CSI_HSYNC),
- IMX_PINCTRL_PIN(MX35_PAD_CSI_PIXCLK),
- IMX_PINCTRL_PIN(MX35_PAD_I2C1_CLK),
- IMX_PINCTRL_PIN(MX35_PAD_I2C1_DAT),
- IMX_PINCTRL_PIN(MX35_PAD_I2C2_CLK),
- IMX_PINCTRL_PIN(MX35_PAD_I2C2_DAT),
- IMX_PINCTRL_PIN(MX35_PAD_STXD4),
- IMX_PINCTRL_PIN(MX35_PAD_SRXD4),
- IMX_PINCTRL_PIN(MX35_PAD_SCK4),
- IMX_PINCTRL_PIN(MX35_PAD_STXFS4),
- IMX_PINCTRL_PIN(MX35_PAD_STXD5),
- IMX_PINCTRL_PIN(MX35_PAD_SRXD5),
- IMX_PINCTRL_PIN(MX35_PAD_SCK5),
- IMX_PINCTRL_PIN(MX35_PAD_STXFS5),
- IMX_PINCTRL_PIN(MX35_PAD_SCKR),
- IMX_PINCTRL_PIN(MX35_PAD_FSR),
- IMX_PINCTRL_PIN(MX35_PAD_HCKR),
- IMX_PINCTRL_PIN(MX35_PAD_SCKT),
- IMX_PINCTRL_PIN(MX35_PAD_FST),
- IMX_PINCTRL_PIN(MX35_PAD_HCKT),
- IMX_PINCTRL_PIN(MX35_PAD_TX5_RX0),
- IMX_PINCTRL_PIN(MX35_PAD_TX4_RX1),
- IMX_PINCTRL_PIN(MX35_PAD_TX3_RX2),
- IMX_PINCTRL_PIN(MX35_PAD_TX2_RX3),
- IMX_PINCTRL_PIN(MX35_PAD_TX1),
- IMX_PINCTRL_PIN(MX35_PAD_TX0),
- IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MOSI),
- IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MISO),
- IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS0),
- IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS1),
- IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SCLK),
- IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SPI_RDY),
- IMX_PINCTRL_PIN(MX35_PAD_RXD1),
- IMX_PINCTRL_PIN(MX35_PAD_TXD1),
- IMX_PINCTRL_PIN(MX35_PAD_RTS1),
- IMX_PINCTRL_PIN(MX35_PAD_CTS1),
- IMX_PINCTRL_PIN(MX35_PAD_RXD2),
- IMX_PINCTRL_PIN(MX35_PAD_TXD2),
- IMX_PINCTRL_PIN(MX35_PAD_RTS2),
- IMX_PINCTRL_PIN(MX35_PAD_CTS2),
- IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR),
- IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC),
- IMX_PINCTRL_PIN(MX35_PAD_LD0),
- IMX_PINCTRL_PIN(MX35_PAD_LD1),
- IMX_PINCTRL_PIN(MX35_PAD_LD2),
- IMX_PINCTRL_PIN(MX35_PAD_LD3),
- IMX_PINCTRL_PIN(MX35_PAD_LD4),
- IMX_PINCTRL_PIN(MX35_PAD_LD5),
- IMX_PINCTRL_PIN(MX35_PAD_LD6),
- IMX_PINCTRL_PIN(MX35_PAD_LD7),
- IMX_PINCTRL_PIN(MX35_PAD_LD8),
- IMX_PINCTRL_PIN(MX35_PAD_LD9),
- IMX_PINCTRL_PIN(MX35_PAD_LD10),
- IMX_PINCTRL_PIN(MX35_PAD_LD11),
- IMX_PINCTRL_PIN(MX35_PAD_LD12),
- IMX_PINCTRL_PIN(MX35_PAD_LD13),
- IMX_PINCTRL_PIN(MX35_PAD_LD14),
- IMX_PINCTRL_PIN(MX35_PAD_LD15),
- IMX_PINCTRL_PIN(MX35_PAD_LD16),
- IMX_PINCTRL_PIN(MX35_PAD_LD17),
- IMX_PINCTRL_PIN(MX35_PAD_LD18),
- IMX_PINCTRL_PIN(MX35_PAD_LD19),
- IMX_PINCTRL_PIN(MX35_PAD_LD20),
- IMX_PINCTRL_PIN(MX35_PAD_LD21),
- IMX_PINCTRL_PIN(MX35_PAD_LD22),
- IMX_PINCTRL_PIN(MX35_PAD_LD23),
- IMX_PINCTRL_PIN(MX35_PAD_D3_HSYNC),
- IMX_PINCTRL_PIN(MX35_PAD_D3_FPSHIFT),
- IMX_PINCTRL_PIN(MX35_PAD_D3_DRDY),
- IMX_PINCTRL_PIN(MX35_PAD_CONTRAST),
- IMX_PINCTRL_PIN(MX35_PAD_D3_VSYNC),
- IMX_PINCTRL_PIN(MX35_PAD_D3_REV),
- IMX_PINCTRL_PIN(MX35_PAD_D3_CLS),
- IMX_PINCTRL_PIN(MX35_PAD_D3_SPL),
- IMX_PINCTRL_PIN(MX35_PAD_SD1_CMD),
- IMX_PINCTRL_PIN(MX35_PAD_SD1_CLK),
- IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA0),
- IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA1),
- IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA2),
- IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA3),
- IMX_PINCTRL_PIN(MX35_PAD_SD2_CMD),
- IMX_PINCTRL_PIN(MX35_PAD_SD2_CLK),
- IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA0),
- IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA1),
- IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA2),
- IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA3),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_CS0),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_CS1),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOR),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOW),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DMACK),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_RESET_B),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_IORDY),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA0),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA1),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA2),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA3),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA4),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA5),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA6),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA7),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA8),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA9),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA10),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA11),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA12),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA13),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA14),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA15),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_INTRQ),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_BUFF_EN),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DMARQ),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DA0),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DA1),
- IMX_PINCTRL_PIN(MX35_PAD_ATA_DA2),
- IMX_PINCTRL_PIN(MX35_PAD_MLB_CLK),
- IMX_PINCTRL_PIN(MX35_PAD_MLB_DAT),
- IMX_PINCTRL_PIN(MX35_PAD_MLB_SIG),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_CLK),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_CLK),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_DV),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_COL),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA0),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA0),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_EN),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_MDC),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_MDIO),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_ERR),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_ERR),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_CRS),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA1),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA1),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA2),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3),
- IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE1),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE2),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE3),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE4),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE5),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE6),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE7),
- IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B),
- IMX_PINCTRL_PIN(MX35_PAD_POR_B),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE8),
- IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0),
- IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1),
- IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0),
- IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1),
- IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE9),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE10),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE11),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE12),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE13),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE14),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE15),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE16),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE17),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE18),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE19),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE20),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE21),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE22),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE23),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE24),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE25),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE26),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE27),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE28),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE29),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE30),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE31),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE32),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE33),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE34),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE35),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE36),
- IMX_PINCTRL_PIN(MX35_PAD_SDBA1),
- IMX_PINCTRL_PIN(MX35_PAD_SDBA0),
- IMX_PINCTRL_PIN(MX35_PAD_SD0),
- IMX_PINCTRL_PIN(MX35_PAD_SD1),
- IMX_PINCTRL_PIN(MX35_PAD_SD2),
- IMX_PINCTRL_PIN(MX35_PAD_SD3),
- IMX_PINCTRL_PIN(MX35_PAD_SD4),
- IMX_PINCTRL_PIN(MX35_PAD_SD5),
- IMX_PINCTRL_PIN(MX35_PAD_SD6),
- IMX_PINCTRL_PIN(MX35_PAD_SD7),
- IMX_PINCTRL_PIN(MX35_PAD_SD8),
- IMX_PINCTRL_PIN(MX35_PAD_SD9),
- IMX_PINCTRL_PIN(MX35_PAD_SD10),
- IMX_PINCTRL_PIN(MX35_PAD_SD11),
- IMX_PINCTRL_PIN(MX35_PAD_SD12),
- IMX_PINCTRL_PIN(MX35_PAD_SD13),
- IMX_PINCTRL_PIN(MX35_PAD_SD14),
- IMX_PINCTRL_PIN(MX35_PAD_SD15),
- IMX_PINCTRL_PIN(MX35_PAD_SD16),
- IMX_PINCTRL_PIN(MX35_PAD_SD17),
- IMX_PINCTRL_PIN(MX35_PAD_SD18),
- IMX_PINCTRL_PIN(MX35_PAD_SD19),
- IMX_PINCTRL_PIN(MX35_PAD_SD20),
- IMX_PINCTRL_PIN(MX35_PAD_SD21),
- IMX_PINCTRL_PIN(MX35_PAD_SD22),
- IMX_PINCTRL_PIN(MX35_PAD_SD23),
- IMX_PINCTRL_PIN(MX35_PAD_SD24),
- IMX_PINCTRL_PIN(MX35_PAD_SD25),
- IMX_PINCTRL_PIN(MX35_PAD_SD26),
- IMX_PINCTRL_PIN(MX35_PAD_SD27),
- IMX_PINCTRL_PIN(MX35_PAD_SD28),
- IMX_PINCTRL_PIN(MX35_PAD_SD29),
- IMX_PINCTRL_PIN(MX35_PAD_SD30),
- IMX_PINCTRL_PIN(MX35_PAD_SD31),
- IMX_PINCTRL_PIN(MX35_PAD_DQM0),
- IMX_PINCTRL_PIN(MX35_PAD_DQM1),
- IMX_PINCTRL_PIN(MX35_PAD_DQM2),
- IMX_PINCTRL_PIN(MX35_PAD_DQM3),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE37),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE38),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE39),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE40),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE41),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE42),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE43),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE44),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE45),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE46),
- IMX_PINCTRL_PIN(MX35_PAD_ECB),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE47),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE48),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE49),
- IMX_PINCTRL_PIN(MX35_PAD_RAS),
- IMX_PINCTRL_PIN(MX35_PAD_CAS),
- IMX_PINCTRL_PIN(MX35_PAD_SDWE),
- IMX_PINCTRL_PIN(MX35_PAD_SDCKE0),
- IMX_PINCTRL_PIN(MX35_PAD_SDCKE1),
- IMX_PINCTRL_PIN(MX35_PAD_SDCLK),
- IMX_PINCTRL_PIN(MX35_PAD_SDQS0),
- IMX_PINCTRL_PIN(MX35_PAD_SDQS1),
- IMX_PINCTRL_PIN(MX35_PAD_SDQS2),
- IMX_PINCTRL_PIN(MX35_PAD_SDQS3),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE50),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE51),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE52),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE53),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE54),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE55),
- IMX_PINCTRL_PIN(MX35_PAD_D15),
- IMX_PINCTRL_PIN(MX35_PAD_D14),
- IMX_PINCTRL_PIN(MX35_PAD_D13),
- IMX_PINCTRL_PIN(MX35_PAD_D12),
- IMX_PINCTRL_PIN(MX35_PAD_D11),
- IMX_PINCTRL_PIN(MX35_PAD_D10),
- IMX_PINCTRL_PIN(MX35_PAD_D9),
- IMX_PINCTRL_PIN(MX35_PAD_D8),
- IMX_PINCTRL_PIN(MX35_PAD_D7),
- IMX_PINCTRL_PIN(MX35_PAD_D6),
- IMX_PINCTRL_PIN(MX35_PAD_D5),
- IMX_PINCTRL_PIN(MX35_PAD_D4),
- IMX_PINCTRL_PIN(MX35_PAD_D3),
- IMX_PINCTRL_PIN(MX35_PAD_D2),
- IMX_PINCTRL_PIN(MX35_PAD_D1),
- IMX_PINCTRL_PIN(MX35_PAD_D0),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE56),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE57),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE58),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE59),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE60),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE61),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE62),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE63),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE64),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE65),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE66),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE67),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE68),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE69),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE70),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE71),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE72),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE73),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE74),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE75),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE76),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE77),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE78),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE79),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE80),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE81),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE82),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE83),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE84),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE85),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE86),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE87),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE88),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE89),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE90),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE91),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE92),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE93),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE94),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE95),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE96),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE97),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE98),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE99),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE100),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE101),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE102),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE103),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE104),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE105),
- IMX_PINCTRL_PIN(MX35_PAD_RTCK),
- IMX_PINCTRL_PIN(MX35_PAD_TCK),
- IMX_PINCTRL_PIN(MX35_PAD_TMS),
- IMX_PINCTRL_PIN(MX35_PAD_TDI),
- IMX_PINCTRL_PIN(MX35_PAD_TDO),
- IMX_PINCTRL_PIN(MX35_PAD_TRSTB),
- IMX_PINCTRL_PIN(MX35_PAD_DE_B),
- IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE106),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE107),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE108),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE109),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE110),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE111),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE112),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE113),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE114),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE115),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE116),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE117),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE118),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE119),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE120),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE121),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE122),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE123),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE124),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE125),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE126),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE127),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE128),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE129),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE130),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE131),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE132),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE133),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE134),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE135),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE136),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE137),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE138),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE139),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE140),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE141),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE142),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE143),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE144),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE145),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE146),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE147),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE148),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE149),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE150),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE151),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE152),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE153),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE154),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE155),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE156),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE157),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE158),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE159),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE160),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE161),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE162),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE163),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE164),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE165),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE166),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE167),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE168),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE169),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE170),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE171),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE172),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE173),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE174),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE175),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE176),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE177),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE178),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE179),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE180),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE181),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE182),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE183),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE184),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE185),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE186),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE187),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE188),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE189),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE190),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE191),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE192),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE193),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE194),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE195),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE196),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE197),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE198),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE199),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE200),
- IMX_PINCTRL_PIN(MX35_PAD_RESERVE201),
- IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK),
- IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE),
-};
-
-static struct imx_pinctrl_soc_info imx35_pinctrl_info = {
- .pins = imx35_pinctrl_pads,
- .npins = ARRAY_SIZE(imx35_pinctrl_pads),
-};
-
-static struct of_device_id imx35_pinctrl_of_match[] = {
- { .compatible = "fsl,imx35-iomuxc", },
- { /* sentinel */ }
-};
-
-static int imx35_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &imx35_pinctrl_info);
-}
-
-static struct platform_driver imx35_pinctrl_driver = {
- .driver = {
- .name = "imx35-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = imx35_pinctrl_of_match,
- },
- .probe = imx35_pinctrl_probe,
- .remove = imx_pinctrl_remove,
-};
-
-static int __init imx35_pinctrl_init(void)
-{
- return platform_driver_register(&imx35_pinctrl_driver);
-}
-arch_initcall(imx35_pinctrl_init);
-
-static void __exit imx35_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx35_pinctrl_driver);
-}
-module_exit(imx35_pinctrl_exit);
-MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
-MODULE_DESCRIPTION("Freescale IMX35 pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * imx50 pinctrl driver based on imx pinmux core
- *
- * Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#include "pinctrl-imx.h"
-
-enum imx50_pads {
- MX50_PAD_RESERVE0 = 0,
- MX50_PAD_RESERVE1 = 1,
- MX50_PAD_RESERVE2 = 2,
- MX50_PAD_RESERVE3 = 3,
- MX50_PAD_RESERVE4 = 4,
- MX50_PAD_RESERVE5 = 5,
- MX50_PAD_RESERVE6 = 6,
- MX50_PAD_RESERVE7 = 7,
- MX50_PAD_KEY_COL0 = 8,
- MX50_PAD_KEY_ROW0 = 9,
- MX50_PAD_KEY_COL1 = 10,
- MX50_PAD_KEY_ROW1 = 11,
- MX50_PAD_KEY_COL2 = 12,
- MX50_PAD_KEY_ROW2 = 13,
- MX50_PAD_KEY_COL3 = 14,
- MX50_PAD_KEY_ROW3 = 15,
- MX50_PAD_I2C1_SCL = 16,
- MX50_PAD_I2C1_SDA = 17,
- MX50_PAD_I2C2_SCL = 18,
- MX50_PAD_I2C2_SDA = 19,
- MX50_PAD_I2C3_SCL = 20,
- MX50_PAD_I2C3_SDA = 21,
- MX50_PAD_PWM1 = 22,
- MX50_PAD_PWM2 = 23,
- MX50_PAD_0WIRE = 24,
- MX50_PAD_EPITO = 25,
- MX50_PAD_WDOG = 26,
- MX50_PAD_SSI_TXFS = 27,
- MX50_PAD_SSI_TXC = 28,
- MX50_PAD_SSI_TXD = 29,
- MX50_PAD_SSI_RXD = 30,
- MX50_PAD_SSI_RXF = 31,
- MX50_PAD_SSI_RXC = 32,
- MX50_PAD_UART1_TXD = 33,
- MX50_PAD_UART1_RXD = 34,
- MX50_PAD_UART1_CTS = 35,
- MX50_PAD_UART1_RTS = 36,
- MX50_PAD_UART2_TXD = 37,
- MX50_PAD_UART2_RXD = 38,
- MX50_PAD_UART2_CTS = 39,
- MX50_PAD_UART2_RTS = 40,
- MX50_PAD_UART3_TXD = 41,
- MX50_PAD_UART3_RXD = 42,
- MX50_PAD_UART4_TXD = 43,
- MX50_PAD_UART4_RXD = 44,
- MX50_PAD_CSPI_CLK = 45,
- MX50_PAD_CSPI_MOSI = 46,
- MX50_PAD_CSPI_MISO = 47,
- MX50_PAD_CSPI_SS0 = 48,
- MX50_PAD_ECSPI1_CLK = 49,
- MX50_PAD_ECSPI1_MOSI = 50,
- MX50_PAD_ECSPI1_MISO = 51,
- MX50_PAD_ECSPI1_SS0 = 52,
- MX50_PAD_ECSPI2_CLK = 53,
- MX50_PAD_ECSPI2_MOSI = 54,
- MX50_PAD_ECSPI2_MISO = 55,
- MX50_PAD_ECSPI2_SS0 = 56,
- MX50_PAD_SD1_CLK = 57,
- MX50_PAD_SD1_CMD = 58,
- MX50_PAD_SD1_D0 = 59,
- MX50_PAD_SD1_D1 = 60,
- MX50_PAD_SD1_D2 = 61,
- MX50_PAD_SD1_D3 = 62,
- MX50_PAD_SD2_CLK = 63,
- MX50_PAD_SD2_CMD = 64,
- MX50_PAD_SD2_D0 = 65,
- MX50_PAD_SD2_D1 = 66,
- MX50_PAD_SD2_D2 = 67,
- MX50_PAD_SD2_D3 = 68,
- MX50_PAD_SD2_D4 = 69,
- MX50_PAD_SD2_D5 = 70,
- MX50_PAD_SD2_D6 = 71,
- MX50_PAD_SD2_D7 = 72,
- MX50_PAD_SD2_WP = 73,
- MX50_PAD_SD2_CD = 74,
- MX50_PAD_DISP_D0 = 75,
- MX50_PAD_DISP_D1 = 76,
- MX50_PAD_DISP_D2 = 77,
- MX50_PAD_DISP_D3 = 78,
- MX50_PAD_DISP_D4 = 79,
- MX50_PAD_DISP_D5 = 80,
- MX50_PAD_DISP_D6 = 81,
- MX50_PAD_DISP_D7 = 82,
- MX50_PAD_DISP_WR = 83,
- MX50_PAD_DISP_RD = 84,
- MX50_PAD_DISP_RS = 85,
- MX50_PAD_DISP_CS = 86,
- MX50_PAD_DISP_BUSY = 87,
- MX50_PAD_DISP_RESET = 88,
- MX50_PAD_SD3_CLK = 89,
- MX50_PAD_SD3_CMD = 90,
- MX50_PAD_SD3_D0 = 91,
- MX50_PAD_SD3_D1 = 92,
- MX50_PAD_SD3_D2 = 93,
- MX50_PAD_SD3_D3 = 94,
- MX50_PAD_SD3_D4 = 95,
- MX50_PAD_SD3_D5 = 96,
- MX50_PAD_SD3_D6 = 97,
- MX50_PAD_SD3_D7 = 98,
- MX50_PAD_SD3_WP = 99,
- MX50_PAD_DISP_D8 = 100,
- MX50_PAD_DISP_D9 = 101,
- MX50_PAD_DISP_D10 = 102,
- MX50_PAD_DISP_D11 = 103,
- MX50_PAD_DISP_D12 = 104,
- MX50_PAD_DISP_D13 = 105,
- MX50_PAD_DISP_D14 = 106,
- MX50_PAD_DISP_D15 = 107,
- MX50_PAD_EPDC_D0 = 108,
- MX50_PAD_EPDC_D1 = 109,
- MX50_PAD_EPDC_D2 = 110,
- MX50_PAD_EPDC_D3 = 111,
- MX50_PAD_EPDC_D4 = 112,
- MX50_PAD_EPDC_D5 = 113,
- MX50_PAD_EPDC_D6 = 114,
- MX50_PAD_EPDC_D7 = 115,
- MX50_PAD_EPDC_D8 = 116,
- MX50_PAD_EPDC_D9 = 117,
- MX50_PAD_EPDC_D10 = 118,
- MX50_PAD_EPDC_D11 = 119,
- MX50_PAD_EPDC_D12 = 120,
- MX50_PAD_EPDC_D13 = 121,
- MX50_PAD_EPDC_D14 = 122,
- MX50_PAD_EPDC_D15 = 123,
- MX50_PAD_EPDC_GDCLK = 124,
- MX50_PAD_EPDC_GDSP = 125,
- MX50_PAD_EPDC_GDOE = 126,
- MX50_PAD_EPDC_GDRL = 127,
- MX50_PAD_EPDC_SDCLK = 128,
- MX50_PAD_EPDC_SDOEZ = 129,
- MX50_PAD_EPDC_SDOED = 130,
- MX50_PAD_EPDC_SDOE = 131,
- MX50_PAD_EPDC_SDLE = 132,
- MX50_PAD_EPDC_SDCLKN = 133,
- MX50_PAD_EPDC_SDSHR = 134,
- MX50_PAD_EPDC_PWRCOM = 135,
- MX50_PAD_EPDC_PWRSTAT = 136,
- MX50_PAD_EPDC_PWRCTRL0 = 137,
- MX50_PAD_EPDC_PWRCTRL1 = 138,
- MX50_PAD_EPDC_PWRCTRL2 = 139,
- MX50_PAD_EPDC_PWRCTRL3 = 140,
- MX50_PAD_EPDC_VCOM0 = 141,
- MX50_PAD_EPDC_VCOM1 = 142,
- MX50_PAD_EPDC_BDR0 = 143,
- MX50_PAD_EPDC_BDR1 = 144,
- MX50_PAD_EPDC_SDCE0 = 145,
- MX50_PAD_EPDC_SDCE1 = 146,
- MX50_PAD_EPDC_SDCE2 = 147,
- MX50_PAD_EPDC_SDCE3 = 148,
- MX50_PAD_EPDC_SDCE4 = 149,
- MX50_PAD_EPDC_SDCE5 = 150,
- MX50_PAD_EIM_DA0 = 151,
- MX50_PAD_EIM_DA1 = 152,
- MX50_PAD_EIM_DA2 = 153,
- MX50_PAD_EIM_DA3 = 154,
- MX50_PAD_EIM_DA4 = 155,
- MX50_PAD_EIM_DA5 = 156,
- MX50_PAD_EIM_DA6 = 157,
- MX50_PAD_EIM_DA7 = 158,
- MX50_PAD_EIM_DA8 = 159,
- MX50_PAD_EIM_DA9 = 160,
- MX50_PAD_EIM_DA10 = 161,
- MX50_PAD_EIM_DA11 = 162,
- MX50_PAD_EIM_DA12 = 163,
- MX50_PAD_EIM_DA13 = 164,
- MX50_PAD_EIM_DA14 = 165,
- MX50_PAD_EIM_DA15 = 166,
- MX50_PAD_EIM_CS2 = 167,
- MX50_PAD_EIM_CS1 = 168,
- MX50_PAD_EIM_CS0 = 169,
- MX50_PAD_EIM_EB0 = 170,
- MX50_PAD_EIM_EB1 = 171,
- MX50_PAD_EIM_WAIT = 172,
- MX50_PAD_EIM_BCLK = 173,
- MX50_PAD_EIM_RDY = 174,
- MX50_PAD_EIM_OE = 175,
- MX50_PAD_EIM_RW = 176,
- MX50_PAD_EIM_LBA = 177,
- MX50_PAD_EIM_CRE = 178,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
- IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
- IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
- IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
- IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
- IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
- IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
- IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
- IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
- IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
- IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
- IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
- IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
- IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
- IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
- IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
- IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL),
- IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA),
- IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL),
- IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA),
- IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL),
- IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA),
- IMX_PINCTRL_PIN(MX50_PAD_PWM1),
- IMX_PINCTRL_PIN(MX50_PAD_PWM2),
- IMX_PINCTRL_PIN(MX50_PAD_0WIRE),
- IMX_PINCTRL_PIN(MX50_PAD_EPITO),
- IMX_PINCTRL_PIN(MX50_PAD_WDOG),
- IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS),
- IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC),
- IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD),
- IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD),
- IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF),
- IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC),
- IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD),
- IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD),
- IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS),
- IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS),
- IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD),
- IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD),
- IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS),
- IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS),
- IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD),
- IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD),
- IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD),
- IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD),
- IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK),
- IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI),
- IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO),
- IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0),
- IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK),
- IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI),
- IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO),
- IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0),
- IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK),
- IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI),
- IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO),
- IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0),
- IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK),
- IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD),
- IMX_PINCTRL_PIN(MX50_PAD_SD1_D0),
- IMX_PINCTRL_PIN(MX50_PAD_SD1_D1),
- IMX_PINCTRL_PIN(MX50_PAD_SD1_D2),
- IMX_PINCTRL_PIN(MX50_PAD_SD1_D3),
- IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK),
- IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD),
- IMX_PINCTRL_PIN(MX50_PAD_SD2_D0),
- IMX_PINCTRL_PIN(MX50_PAD_SD2_D1),
- IMX_PINCTRL_PIN(MX50_PAD_SD2_D2),
- IMX_PINCTRL_PIN(MX50_PAD_SD2_D3),
- IMX_PINCTRL_PIN(MX50_PAD_SD2_D4),
- IMX_PINCTRL_PIN(MX50_PAD_SD2_D5),
- IMX_PINCTRL_PIN(MX50_PAD_SD2_D6),
- IMX_PINCTRL_PIN(MX50_PAD_SD2_D7),
- IMX_PINCTRL_PIN(MX50_PAD_SD2_WP),
- IMX_PINCTRL_PIN(MX50_PAD_SD2_CD),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D0),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D1),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D2),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D3),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D4),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D5),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D6),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D7),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_WR),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_RD),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_RS),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_CS),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET),
- IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK),
- IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD),
- IMX_PINCTRL_PIN(MX50_PAD_SD3_D0),
- IMX_PINCTRL_PIN(MX50_PAD_SD3_D1),
- IMX_PINCTRL_PIN(MX50_PAD_SD3_D2),
- IMX_PINCTRL_PIN(MX50_PAD_SD3_D3),
- IMX_PINCTRL_PIN(MX50_PAD_SD3_D4),
- IMX_PINCTRL_PIN(MX50_PAD_SD3_D5),
- IMX_PINCTRL_PIN(MX50_PAD_SD3_D6),
- IMX_PINCTRL_PIN(MX50_PAD_SD3_D7),
- IMX_PINCTRL_PIN(MX50_PAD_SD3_WP),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D8),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D9),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D10),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D11),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D12),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D13),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D14),
- IMX_PINCTRL_PIN(MX50_PAD_DISP_D15),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4),
- IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_OE),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_RW),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA),
- IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
-};
-
-static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
- .pins = imx50_pinctrl_pads,
- .npins = ARRAY_SIZE(imx50_pinctrl_pads),
-};
-
-static struct of_device_id imx50_pinctrl_of_match[] = {
- { .compatible = "fsl,imx50-iomuxc", },
- { /* sentinel */ }
-};
-
-static int imx50_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &imx50_pinctrl_info);
-}
-
-static struct platform_driver imx50_pinctrl_driver = {
- .driver = {
- .name = "imx50-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = of_match_ptr(imx50_pinctrl_of_match),
- },
- .probe = imx50_pinctrl_probe,
- .remove = imx_pinctrl_remove,
-};
-
-static int __init imx50_pinctrl_init(void)
-{
- return platform_driver_register(&imx50_pinctrl_driver);
-}
-arch_initcall(imx50_pinctrl_init);
-
-static void __exit imx50_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx50_pinctrl_driver);
-}
-module_exit(imx50_pinctrl_exit);
-MODULE_DESCRIPTION("Freescale IMX50 pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * imx51 pinctrl driver based on imx pinmux core
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro, Inc.
- *
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#include "pinctrl-imx.h"
-
-enum imx51_pads {
- MX51_PAD_RESERVE0 = 0,
- MX51_PAD_RESERVE1 = 1,
- MX51_PAD_RESERVE2 = 2,
- MX51_PAD_RESERVE3 = 3,
- MX51_PAD_RESERVE4 = 4,
- MX51_PAD_RESERVE5 = 5,
- MX51_PAD_RESERVE6 = 6,
- MX51_PAD_EIM_DA0 = 7,
- MX51_PAD_EIM_DA1 = 8,
- MX51_PAD_EIM_DA2 = 9,
- MX51_PAD_EIM_DA3 = 10,
- MX51_PAD_EIM_DA4 = 11,
- MX51_PAD_EIM_DA5 = 12,
- MX51_PAD_EIM_DA6 = 13,
- MX51_PAD_EIM_DA7 = 14,
- MX51_PAD_EIM_DA8 = 15,
- MX51_PAD_EIM_DA9 = 16,
- MX51_PAD_EIM_DA10 = 17,
- MX51_PAD_EIM_DA11 = 18,
- MX51_PAD_EIM_DA12 = 19,
- MX51_PAD_EIM_DA13 = 20,
- MX51_PAD_EIM_DA14 = 21,
- MX51_PAD_EIM_DA15 = 22,
- MX51_PAD_EIM_D16 = 23,
- MX51_PAD_EIM_D17 = 24,
- MX51_PAD_EIM_D18 = 25,
- MX51_PAD_EIM_D19 = 26,
- MX51_PAD_EIM_D20 = 27,
- MX51_PAD_EIM_D21 = 28,
- MX51_PAD_EIM_D22 = 29,
- MX51_PAD_EIM_D23 = 30,
- MX51_PAD_EIM_D24 = 31,
- MX51_PAD_EIM_D25 = 32,
- MX51_PAD_EIM_D26 = 33,
- MX51_PAD_EIM_D27 = 34,
- MX51_PAD_EIM_D28 = 35,
- MX51_PAD_EIM_D29 = 36,
- MX51_PAD_EIM_D30 = 37,
- MX51_PAD_EIM_D31 = 38,
- MX51_PAD_EIM_A16 = 39,
- MX51_PAD_EIM_A17 = 40,
- MX51_PAD_EIM_A18 = 41,
- MX51_PAD_EIM_A19 = 42,
- MX51_PAD_EIM_A20 = 43,
- MX51_PAD_EIM_A21 = 44,
- MX51_PAD_EIM_A22 = 45,
- MX51_PAD_EIM_A23 = 46,
- MX51_PAD_EIM_A24 = 47,
- MX51_PAD_EIM_A25 = 48,
- MX51_PAD_EIM_A26 = 49,
- MX51_PAD_EIM_A27 = 50,
- MX51_PAD_EIM_EB0 = 51,
- MX51_PAD_EIM_EB1 = 52,
- MX51_PAD_EIM_EB2 = 53,
- MX51_PAD_EIM_EB3 = 54,
- MX51_PAD_EIM_OE = 55,
- MX51_PAD_EIM_CS0 = 56,
- MX51_PAD_EIM_CS1 = 57,
- MX51_PAD_EIM_CS2 = 58,
- MX51_PAD_EIM_CS3 = 59,
- MX51_PAD_EIM_CS4 = 60,
- MX51_PAD_EIM_CS5 = 61,
- MX51_PAD_EIM_DTACK = 62,
- MX51_PAD_EIM_LBA = 63,
- MX51_PAD_EIM_CRE = 64,
- MX51_PAD_DRAM_CS1 = 65,
- MX51_PAD_NANDF_WE_B = 66,
- MX51_PAD_NANDF_RE_B = 67,
- MX51_PAD_NANDF_ALE = 68,
- MX51_PAD_NANDF_CLE = 69,
- MX51_PAD_NANDF_WP_B = 70,
- MX51_PAD_NANDF_RB0 = 71,
- MX51_PAD_NANDF_RB1 = 72,
- MX51_PAD_NANDF_RB2 = 73,
- MX51_PAD_NANDF_RB3 = 74,
- MX51_PAD_GPIO_NAND = 75,
- MX51_PAD_NANDF_CS0 = 76,
- MX51_PAD_NANDF_CS1 = 77,
- MX51_PAD_NANDF_CS2 = 78,
- MX51_PAD_NANDF_CS3 = 79,
- MX51_PAD_NANDF_CS4 = 80,
- MX51_PAD_NANDF_CS5 = 81,
- MX51_PAD_NANDF_CS6 = 82,
- MX51_PAD_NANDF_CS7 = 83,
- MX51_PAD_NANDF_RDY_INT = 84,
- MX51_PAD_NANDF_D15 = 85,
- MX51_PAD_NANDF_D14 = 86,
- MX51_PAD_NANDF_D13 = 87,
- MX51_PAD_NANDF_D12 = 88,
- MX51_PAD_NANDF_D11 = 89,
- MX51_PAD_NANDF_D10 = 90,
- MX51_PAD_NANDF_D9 = 91,
- MX51_PAD_NANDF_D8 = 92,
- MX51_PAD_NANDF_D7 = 93,
- MX51_PAD_NANDF_D6 = 94,
- MX51_PAD_NANDF_D5 = 95,
- MX51_PAD_NANDF_D4 = 96,
- MX51_PAD_NANDF_D3 = 97,
- MX51_PAD_NANDF_D2 = 98,
- MX51_PAD_NANDF_D1 = 99,
- MX51_PAD_NANDF_D0 = 100,
- MX51_PAD_CSI1_D8 = 101,
- MX51_PAD_CSI1_D9 = 102,
- MX51_PAD_CSI1_D10 = 103,
- MX51_PAD_CSI1_D11 = 104,
- MX51_PAD_CSI1_D12 = 105,
- MX51_PAD_CSI1_D13 = 106,
- MX51_PAD_CSI1_D14 = 107,
- MX51_PAD_CSI1_D15 = 108,
- MX51_PAD_CSI1_D16 = 109,
- MX51_PAD_CSI1_D17 = 110,
- MX51_PAD_CSI1_D18 = 111,
- MX51_PAD_CSI1_D19 = 112,
- MX51_PAD_CSI1_VSYNC = 113,
- MX51_PAD_CSI1_HSYNC = 114,
- MX51_PAD_CSI2_D12 = 115,
- MX51_PAD_CSI2_D13 = 116,
- MX51_PAD_CSI2_D14 = 117,
- MX51_PAD_CSI2_D15 = 118,
- MX51_PAD_CSI2_D16 = 119,
- MX51_PAD_CSI2_D17 = 120,
- MX51_PAD_CSI2_D18 = 121,
- MX51_PAD_CSI2_D19 = 122,
- MX51_PAD_CSI2_VSYNC = 123,
- MX51_PAD_CSI2_HSYNC = 124,
- MX51_PAD_CSI2_PIXCLK = 125,
- MX51_PAD_I2C1_CLK = 126,
- MX51_PAD_I2C1_DAT = 127,
- MX51_PAD_AUD3_BB_TXD = 128,
- MX51_PAD_AUD3_BB_RXD = 129,
- MX51_PAD_AUD3_BB_CK = 130,
- MX51_PAD_AUD3_BB_FS = 131,
- MX51_PAD_CSPI1_MOSI = 132,
- MX51_PAD_CSPI1_MISO = 133,
- MX51_PAD_CSPI1_SS0 = 134,
- MX51_PAD_CSPI1_SS1 = 135,
- MX51_PAD_CSPI1_RDY = 136,
- MX51_PAD_CSPI1_SCLK = 137,
- MX51_PAD_UART1_RXD = 138,
- MX51_PAD_UART1_TXD = 139,
- MX51_PAD_UART1_RTS = 140,
- MX51_PAD_UART1_CTS = 141,
- MX51_PAD_UART2_RXD = 142,
- MX51_PAD_UART2_TXD = 143,
- MX51_PAD_UART3_RXD = 144,
- MX51_PAD_UART3_TXD = 145,
- MX51_PAD_OWIRE_LINE = 146,
- MX51_PAD_KEY_ROW0 = 147,
- MX51_PAD_KEY_ROW1 = 148,
- MX51_PAD_KEY_ROW2 = 149,
- MX51_PAD_KEY_ROW3 = 150,
- MX51_PAD_KEY_COL0 = 151,
- MX51_PAD_KEY_COL1 = 152,
- MX51_PAD_KEY_COL2 = 153,
- MX51_PAD_KEY_COL3 = 154,
- MX51_PAD_KEY_COL4 = 155,
- MX51_PAD_KEY_COL5 = 156,
- MX51_PAD_RESERVE7 = 157,
- MX51_PAD_USBH1_CLK = 158,
- MX51_PAD_USBH1_DIR = 159,
- MX51_PAD_USBH1_STP = 160,
- MX51_PAD_USBH1_NXT = 161,
- MX51_PAD_USBH1_DATA0 = 162,
- MX51_PAD_USBH1_DATA1 = 163,
- MX51_PAD_USBH1_DATA2 = 164,
- MX51_PAD_USBH1_DATA3 = 165,
- MX51_PAD_USBH1_DATA4 = 166,
- MX51_PAD_USBH1_DATA5 = 167,
- MX51_PAD_USBH1_DATA6 = 168,
- MX51_PAD_USBH1_DATA7 = 169,
- MX51_PAD_DI1_PIN11 = 170,
- MX51_PAD_DI1_PIN12 = 171,
- MX51_PAD_DI1_PIN13 = 172,
- MX51_PAD_DI1_D0_CS = 173,
- MX51_PAD_DI1_D1_CS = 174,
- MX51_PAD_DISPB2_SER_DIN = 175,
- MX51_PAD_DISPB2_SER_DIO = 176,
- MX51_PAD_DISPB2_SER_CLK = 177,
- MX51_PAD_DISPB2_SER_RS = 178,
- MX51_PAD_DISP1_DAT0 = 179,
- MX51_PAD_DISP1_DAT1 = 180,
- MX51_PAD_DISP1_DAT2 = 181,
- MX51_PAD_DISP1_DAT3 = 182,
- MX51_PAD_DISP1_DAT4 = 183,
- MX51_PAD_DISP1_DAT5 = 184,
- MX51_PAD_DISP1_DAT6 = 185,
- MX51_PAD_DISP1_DAT7 = 186,
- MX51_PAD_DISP1_DAT8 = 187,
- MX51_PAD_DISP1_DAT9 = 188,
- MX51_PAD_DISP1_DAT10 = 189,
- MX51_PAD_DISP1_DAT11 = 190,
- MX51_PAD_DISP1_DAT12 = 191,
- MX51_PAD_DISP1_DAT13 = 192,
- MX51_PAD_DISP1_DAT14 = 193,
- MX51_PAD_DISP1_DAT15 = 194,
- MX51_PAD_DISP1_DAT16 = 195,
- MX51_PAD_DISP1_DAT17 = 196,
- MX51_PAD_DISP1_DAT18 = 197,
- MX51_PAD_DISP1_DAT19 = 198,
- MX51_PAD_DISP1_DAT20 = 199,
- MX51_PAD_DISP1_DAT21 = 200,
- MX51_PAD_DISP1_DAT22 = 201,
- MX51_PAD_DISP1_DAT23 = 202,
- MX51_PAD_DI1_PIN3 = 203,
- MX51_PAD_DI1_PIN2 = 204,
- MX51_PAD_RESERVE8 = 205,
- MX51_PAD_DI_GP2 = 206,
- MX51_PAD_DI_GP3 = 207,
- MX51_PAD_DI2_PIN4 = 208,
- MX51_PAD_DI2_PIN2 = 209,
- MX51_PAD_DI2_PIN3 = 210,
- MX51_PAD_DI2_DISP_CLK = 211,
- MX51_PAD_DI_GP4 = 212,
- MX51_PAD_DISP2_DAT0 = 213,
- MX51_PAD_DISP2_DAT1 = 214,
- MX51_PAD_DISP2_DAT2 = 215,
- MX51_PAD_DISP2_DAT3 = 216,
- MX51_PAD_DISP2_DAT4 = 217,
- MX51_PAD_DISP2_DAT5 = 218,
- MX51_PAD_DISP2_DAT6 = 219,
- MX51_PAD_DISP2_DAT7 = 220,
- MX51_PAD_DISP2_DAT8 = 221,
- MX51_PAD_DISP2_DAT9 = 222,
- MX51_PAD_DISP2_DAT10 = 223,
- MX51_PAD_DISP2_DAT11 = 224,
- MX51_PAD_DISP2_DAT12 = 225,
- MX51_PAD_DISP2_DAT13 = 226,
- MX51_PAD_DISP2_DAT14 = 227,
- MX51_PAD_DISP2_DAT15 = 228,
- MX51_PAD_SD1_CMD = 229,
- MX51_PAD_SD1_CLK = 230,
- MX51_PAD_SD1_DATA0 = 231,
- MX51_PAD_SD1_DATA1 = 232,
- MX51_PAD_SD1_DATA2 = 233,
- MX51_PAD_SD1_DATA3 = 234,
- MX51_PAD_GPIO1_0 = 235,
- MX51_PAD_GPIO1_1 = 236,
- MX51_PAD_SD2_CMD = 237,
- MX51_PAD_SD2_CLK = 238,
- MX51_PAD_SD2_DATA0 = 239,
- MX51_PAD_SD2_DATA1 = 240,
- MX51_PAD_SD2_DATA2 = 241,
- MX51_PAD_SD2_DATA3 = 242,
- MX51_PAD_GPIO1_2 = 243,
- MX51_PAD_GPIO1_3 = 244,
- MX51_PAD_PMIC_INT_REQ = 245,
- MX51_PAD_GPIO1_4 = 246,
- MX51_PAD_GPIO1_5 = 247,
- MX51_PAD_GPIO1_6 = 248,
- MX51_PAD_GPIO1_7 = 249,
- MX51_PAD_GPIO1_8 = 250,
- MX51_PAD_GPIO1_9 = 251,
- MX51_PAD_RESERVE9 = 252,
- MX51_PAD_RESERVE10 = 253,
- MX51_PAD_RESERVE11 = 254,
- MX51_PAD_RESERVE12 = 255,
- MX51_PAD_RESERVE13 = 256,
- MX51_PAD_RESERVE14 = 257,
- MX51_PAD_RESERVE15 = 258,
- MX51_PAD_RESERVE16 = 259,
- MX51_PAD_RESERVE17 = 260,
- MX51_PAD_RESERVE18 = 261,
- MX51_PAD_RESERVE19 = 262,
- MX51_PAD_RESERVE20 = 263,
- MX51_PAD_RESERVE21 = 264,
- MX51_PAD_RESERVE22 = 265,
- MX51_PAD_RESERVE23 = 266,
- MX51_PAD_RESERVE24 = 267,
- MX51_PAD_RESERVE25 = 268,
- MX51_PAD_RESERVE26 = 269,
- MX51_PAD_RESERVE27 = 270,
- MX51_PAD_RESERVE28 = 271,
- MX51_PAD_RESERVE29 = 272,
- MX51_PAD_RESERVE30 = 273,
- MX51_PAD_RESERVE31 = 274,
- MX51_PAD_RESERVE32 = 275,
- MX51_PAD_RESERVE33 = 276,
- MX51_PAD_RESERVE34 = 277,
- MX51_PAD_RESERVE35 = 278,
- MX51_PAD_RESERVE36 = 279,
- MX51_PAD_RESERVE37 = 280,
- MX51_PAD_RESERVE38 = 281,
- MX51_PAD_RESERVE39 = 282,
- MX51_PAD_RESERVE40 = 283,
- MX51_PAD_RESERVE41 = 284,
- MX51_PAD_RESERVE42 = 285,
- MX51_PAD_RESERVE43 = 286,
- MX51_PAD_RESERVE44 = 287,
- MX51_PAD_RESERVE45 = 288,
- MX51_PAD_RESERVE46 = 289,
- MX51_PAD_RESERVE47 = 290,
- MX51_PAD_RESERVE48 = 291,
- MX51_PAD_RESERVE49 = 292,
- MX51_PAD_RESERVE50 = 293,
- MX51_PAD_RESERVE51 = 294,
- MX51_PAD_RESERVE52 = 295,
- MX51_PAD_RESERVE53 = 296,
- MX51_PAD_RESERVE54 = 297,
- MX51_PAD_RESERVE55 = 298,
- MX51_PAD_RESERVE56 = 299,
- MX51_PAD_RESERVE57 = 300,
- MX51_PAD_RESERVE58 = 301,
- MX51_PAD_RESERVE59 = 302,
- MX51_PAD_RESERVE60 = 303,
- MX51_PAD_RESERVE61 = 304,
- MX51_PAD_RESERVE62 = 305,
- MX51_PAD_RESERVE63 = 306,
- MX51_PAD_RESERVE64 = 307,
- MX51_PAD_RESERVE65 = 308,
- MX51_PAD_RESERVE66 = 309,
- MX51_PAD_RESERVE67 = 310,
- MX51_PAD_RESERVE68 = 311,
- MX51_PAD_RESERVE69 = 312,
- MX51_PAD_RESERVE70 = 313,
- MX51_PAD_RESERVE71 = 314,
- MX51_PAD_RESERVE72 = 315,
- MX51_PAD_RESERVE73 = 316,
- MX51_PAD_RESERVE74 = 317,
- MX51_PAD_RESERVE75 = 318,
- MX51_PAD_RESERVE76 = 319,
- MX51_PAD_RESERVE77 = 320,
- MX51_PAD_RESERVE78 = 321,
- MX51_PAD_RESERVE79 = 322,
- MX51_PAD_RESERVE80 = 323,
- MX51_PAD_RESERVE81 = 324,
- MX51_PAD_RESERVE82 = 325,
- MX51_PAD_RESERVE83 = 326,
- MX51_PAD_RESERVE84 = 327,
- MX51_PAD_RESERVE85 = 328,
- MX51_PAD_RESERVE86 = 329,
- MX51_PAD_RESERVE87 = 330,
- MX51_PAD_RESERVE88 = 331,
- MX51_PAD_RESERVE89 = 332,
- MX51_PAD_RESERVE90 = 333,
- MX51_PAD_RESERVE91 = 334,
- MX51_PAD_RESERVE92 = 335,
- MX51_PAD_RESERVE93 = 336,
- MX51_PAD_RESERVE94 = 337,
- MX51_PAD_RESERVE95 = 338,
- MX51_PAD_RESERVE96 = 339,
- MX51_PAD_RESERVE97 = 340,
- MX51_PAD_RESERVE98 = 341,
- MX51_PAD_RESERVE99 = 342,
- MX51_PAD_RESERVE100 = 343,
- MX51_PAD_RESERVE101 = 344,
- MX51_PAD_RESERVE102 = 345,
- MX51_PAD_RESERVE103 = 346,
- MX51_PAD_RESERVE104 = 347,
- MX51_PAD_RESERVE105 = 348,
- MX51_PAD_RESERVE106 = 349,
- MX51_PAD_RESERVE107 = 350,
- MX51_PAD_RESERVE108 = 351,
- MX51_PAD_RESERVE109 = 352,
- MX51_PAD_RESERVE110 = 353,
- MX51_PAD_RESERVE111 = 354,
- MX51_PAD_RESERVE112 = 355,
- MX51_PAD_RESERVE113 = 356,
- MX51_PAD_RESERVE114 = 357,
- MX51_PAD_RESERVE115 = 358,
- MX51_PAD_RESERVE116 = 359,
- MX51_PAD_RESERVE117 = 360,
- MX51_PAD_RESERVE118 = 361,
- MX51_PAD_RESERVE119 = 362,
- MX51_PAD_RESERVE120 = 363,
- MX51_PAD_RESERVE121 = 364,
- MX51_PAD_CSI1_PIXCLK = 365,
- MX51_PAD_CSI1_MCLK = 366,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE0),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE1),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE2),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE3),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE4),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE5),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE6),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D16),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D17),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D18),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D19),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D20),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D21),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D22),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D23),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D24),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D25),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D26),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D27),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D28),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D29),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D30),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_D31),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_A16),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_A17),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_A18),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_A19),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_A20),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_A21),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_A22),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_A23),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_A24),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_A25),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_A26),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_A27),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_EB0),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_EB1),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_EB2),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_EB3),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_OE),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_CS0),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_CS1),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_CS2),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_CS3),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_CS4),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_CS5),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_DTACK),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_LBA),
- IMX_PINCTRL_PIN(MX51_PAD_EIM_CRE),
- IMX_PINCTRL_PIN(MX51_PAD_DRAM_CS1),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_WE_B),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_RE_B),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_ALE),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_CLE),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_WP_B),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB0),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB1),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB2),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB3),
- IMX_PINCTRL_PIN(MX51_PAD_GPIO_NAND),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS0),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS1),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS2),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS3),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS4),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS5),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS6),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS7),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_RDY_INT),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D15),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D14),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D13),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D12),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D11),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D10),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D9),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D8),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D7),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D6),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D5),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D4),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D3),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D2),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D1),
- IMX_PINCTRL_PIN(MX51_PAD_NANDF_D0),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_D8),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_D9),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_D10),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_D11),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_D12),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_D13),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_D14),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_D15),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_D16),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_D17),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_D18),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC),
- IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12),
- IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13),
- IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14),
- IMX_PINCTRL_PIN(MX51_PAD_CSI2_D15),
- IMX_PINCTRL_PIN(MX51_PAD_CSI2_D16),
- IMX_PINCTRL_PIN(MX51_PAD_CSI2_D17),
- IMX_PINCTRL_PIN(MX51_PAD_CSI2_D18),
- IMX_PINCTRL_PIN(MX51_PAD_CSI2_D19),
- IMX_PINCTRL_PIN(MX51_PAD_CSI2_VSYNC),
- IMX_PINCTRL_PIN(MX51_PAD_CSI2_HSYNC),
- IMX_PINCTRL_PIN(MX51_PAD_CSI2_PIXCLK),
- IMX_PINCTRL_PIN(MX51_PAD_I2C1_CLK),
- IMX_PINCTRL_PIN(MX51_PAD_I2C1_DAT),
- IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_TXD),
- IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_RXD),
- IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_CK),
- IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_FS),
- IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MOSI),
- IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MISO),
- IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS0),
- IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS1),
- IMX_PINCTRL_PIN(MX51_PAD_CSPI1_RDY),
- IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SCLK),
- IMX_PINCTRL_PIN(MX51_PAD_UART1_RXD),
- IMX_PINCTRL_PIN(MX51_PAD_UART1_TXD),
- IMX_PINCTRL_PIN(MX51_PAD_UART1_RTS),
- IMX_PINCTRL_PIN(MX51_PAD_UART1_CTS),
- IMX_PINCTRL_PIN(MX51_PAD_UART2_RXD),
- IMX_PINCTRL_PIN(MX51_PAD_UART2_TXD),
- IMX_PINCTRL_PIN(MX51_PAD_UART3_RXD),
- IMX_PINCTRL_PIN(MX51_PAD_UART3_TXD),
- IMX_PINCTRL_PIN(MX51_PAD_OWIRE_LINE),
- IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW0),
- IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW1),
- IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW2),
- IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW3),
- IMX_PINCTRL_PIN(MX51_PAD_KEY_COL0),
- IMX_PINCTRL_PIN(MX51_PAD_KEY_COL1),
- IMX_PINCTRL_PIN(MX51_PAD_KEY_COL2),
- IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3),
- IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4),
- IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE7),
- IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK),
- IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR),
- IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP),
- IMX_PINCTRL_PIN(MX51_PAD_USBH1_NXT),
- IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA0),
- IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA1),
- IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA2),
- IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA3),
- IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA4),
- IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA5),
- IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA6),
- IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA7),
- IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN11),
- IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN12),
- IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN13),
- IMX_PINCTRL_PIN(MX51_PAD_DI1_D0_CS),
- IMX_PINCTRL_PIN(MX51_PAD_DI1_D1_CS),
- IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIN),
- IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIO),
- IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_CLK),
- IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_RS),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT0),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT1),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT2),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT3),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT4),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT5),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT6),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT7),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT8),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT9),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT10),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT11),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT12),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT13),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT14),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT15),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT16),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT17),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT18),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT19),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT20),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT21),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT22),
- IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23),
- IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3),
- IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE8),
- IMX_PINCTRL_PIN(MX51_PAD_DI_GP2),
- IMX_PINCTRL_PIN(MX51_PAD_DI_GP3),
- IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4),
- IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN2),
- IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN3),
- IMX_PINCTRL_PIN(MX51_PAD_DI2_DISP_CLK),
- IMX_PINCTRL_PIN(MX51_PAD_DI_GP4),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT0),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT1),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT2),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT3),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT4),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT5),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT6),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT7),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT8),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT9),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT10),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT11),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT12),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT13),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT14),
- IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT15),
- IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD),
- IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK),
- IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0),
- IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1),
- IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2),
- IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3),
- IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0),
- IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1),
- IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD),
- IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK),
- IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0),
- IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA1),
- IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA2),
- IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA3),
- IMX_PINCTRL_PIN(MX51_PAD_GPIO1_2),
- IMX_PINCTRL_PIN(MX51_PAD_GPIO1_3),
- IMX_PINCTRL_PIN(MX51_PAD_PMIC_INT_REQ),
- IMX_PINCTRL_PIN(MX51_PAD_GPIO1_4),
- IMX_PINCTRL_PIN(MX51_PAD_GPIO1_5),
- IMX_PINCTRL_PIN(MX51_PAD_GPIO1_6),
- IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7),
- IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8),
- IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE9),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE10),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE11),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE12),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE13),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE14),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE15),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE16),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE17),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE18),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE19),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE20),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE21),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE22),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE23),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE24),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE25),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE26),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE27),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE28),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE29),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE30),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE31),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE32),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE33),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE34),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE35),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE36),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE37),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE38),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE39),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE40),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE41),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE42),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE43),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE44),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE45),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE46),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE47),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE48),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE49),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE50),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE51),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE52),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE53),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE54),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE55),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE56),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE57),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE58),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE59),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE60),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE61),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE62),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE63),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE64),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE65),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE66),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE67),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE68),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE69),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE70),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE71),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE72),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE73),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE74),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE75),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE76),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE77),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE78),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE79),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE80),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE81),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE82),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE83),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE84),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE85),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE86),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE87),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE88),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE89),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE90),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE91),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE92),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE93),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE94),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE95),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE96),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE97),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE98),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE99),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE100),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE101),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE102),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE103),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE104),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE105),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE106),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE107),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE108),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE109),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE110),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE111),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE112),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE113),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE114),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE115),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE116),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE117),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE118),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE119),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE120),
- IMX_PINCTRL_PIN(MX51_PAD_RESERVE121),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK),
- IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK),
-};
-
-static struct imx_pinctrl_soc_info imx51_pinctrl_info = {
- .pins = imx51_pinctrl_pads,
- .npins = ARRAY_SIZE(imx51_pinctrl_pads),
-};
-
-static struct of_device_id imx51_pinctrl_of_match[] = {
- { .compatible = "fsl,imx51-iomuxc", },
- { /* sentinel */ }
-};
-
-static int imx51_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &imx51_pinctrl_info);
-}
-
-static struct platform_driver imx51_pinctrl_driver = {
- .driver = {
- .name = "imx51-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = imx51_pinctrl_of_match,
- },
- .probe = imx51_pinctrl_probe,
- .remove = imx_pinctrl_remove,
-};
-
-static int __init imx51_pinctrl_init(void)
-{
- return platform_driver_register(&imx51_pinctrl_driver);
-}
-arch_initcall(imx51_pinctrl_init);
-
-static void __exit imx51_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx51_pinctrl_driver);
-}
-module_exit(imx51_pinctrl_exit);
-MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
-MODULE_DESCRIPTION("Freescale IMX51 pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * imx53 pinctrl driver based on imx pinmux core
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro, Inc.
- *
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#include "pinctrl-imx.h"
-
-enum imx53_pads {
- MX53_PAD_RESERVE0 = 0,
- MX53_PAD_RESERVE1 = 1,
- MX53_PAD_RESERVE2 = 2,
- MX53_PAD_RESERVE3 = 3,
- MX53_PAD_RESERVE4 = 4,
- MX53_PAD_RESERVE5 = 5,
- MX53_PAD_RESERVE6 = 6,
- MX53_PAD_RESERVE7 = 7,
- MX53_PAD_GPIO_19 = 8,
- MX53_PAD_KEY_COL0 = 9,
- MX53_PAD_KEY_ROW0 = 10,
- MX53_PAD_KEY_COL1 = 11,
- MX53_PAD_KEY_ROW1 = 12,
- MX53_PAD_KEY_COL2 = 13,
- MX53_PAD_KEY_ROW2 = 14,
- MX53_PAD_KEY_COL3 = 15,
- MX53_PAD_KEY_ROW3 = 16,
- MX53_PAD_KEY_COL4 = 17,
- MX53_PAD_KEY_ROW4 = 18,
- MX53_PAD_DI0_DISP_CLK = 19,
- MX53_PAD_DI0_PIN15 = 20,
- MX53_PAD_DI0_PIN2 = 21,
- MX53_PAD_DI0_PIN3 = 22,
- MX53_PAD_DI0_PIN4 = 23,
- MX53_PAD_DISP0_DAT0 = 24,
- MX53_PAD_DISP0_DAT1 = 25,
- MX53_PAD_DISP0_DAT2 = 26,
- MX53_PAD_DISP0_DAT3 = 27,
- MX53_PAD_DISP0_DAT4 = 28,
- MX53_PAD_DISP0_DAT5 = 29,
- MX53_PAD_DISP0_DAT6 = 30,
- MX53_PAD_DISP0_DAT7 = 31,
- MX53_PAD_DISP0_DAT8 = 32,
- MX53_PAD_DISP0_DAT9 = 33,
- MX53_PAD_DISP0_DAT10 = 34,
- MX53_PAD_DISP0_DAT11 = 35,
- MX53_PAD_DISP0_DAT12 = 36,
- MX53_PAD_DISP0_DAT13 = 37,
- MX53_PAD_DISP0_DAT14 = 38,
- MX53_PAD_DISP0_DAT15 = 39,
- MX53_PAD_DISP0_DAT16 = 40,
- MX53_PAD_DISP0_DAT17 = 41,
- MX53_PAD_DISP0_DAT18 = 42,
- MX53_PAD_DISP0_DAT19 = 43,
- MX53_PAD_DISP0_DAT20 = 44,
- MX53_PAD_DISP0_DAT21 = 45,
- MX53_PAD_DISP0_DAT22 = 46,
- MX53_PAD_DISP0_DAT23 = 47,
- MX53_PAD_CSI0_PIXCLK = 48,
- MX53_PAD_CSI0_MCLK = 49,
- MX53_PAD_CSI0_DATA_EN = 50,
- MX53_PAD_CSI0_VSYNC = 51,
- MX53_PAD_CSI0_DAT4 = 52,
- MX53_PAD_CSI0_DAT5 = 53,
- MX53_PAD_CSI0_DAT6 = 54,
- MX53_PAD_CSI0_DAT7 = 55,
- MX53_PAD_CSI0_DAT8 = 56,
- MX53_PAD_CSI0_DAT9 = 57,
- MX53_PAD_CSI0_DAT10 = 58,
- MX53_PAD_CSI0_DAT11 = 59,
- MX53_PAD_CSI0_DAT12 = 60,
- MX53_PAD_CSI0_DAT13 = 61,
- MX53_PAD_CSI0_DAT14 = 62,
- MX53_PAD_CSI0_DAT15 = 63,
- MX53_PAD_CSI0_DAT16 = 64,
- MX53_PAD_CSI0_DAT17 = 65,
- MX53_PAD_CSI0_DAT18 = 66,
- MX53_PAD_CSI0_DAT19 = 67,
- MX53_PAD_EIM_A25 = 68,
- MX53_PAD_EIM_EB2 = 69,
- MX53_PAD_EIM_D16 = 70,
- MX53_PAD_EIM_D17 = 71,
- MX53_PAD_EIM_D18 = 72,
- MX53_PAD_EIM_D19 = 73,
- MX53_PAD_EIM_D20 = 74,
- MX53_PAD_EIM_D21 = 75,
- MX53_PAD_EIM_D22 = 76,
- MX53_PAD_EIM_D23 = 77,
- MX53_PAD_EIM_EB3 = 78,
- MX53_PAD_EIM_D24 = 79,
- MX53_PAD_EIM_D25 = 80,
- MX53_PAD_EIM_D26 = 81,
- MX53_PAD_EIM_D27 = 82,
- MX53_PAD_EIM_D28 = 83,
- MX53_PAD_EIM_D29 = 84,
- MX53_PAD_EIM_D30 = 85,
- MX53_PAD_EIM_D31 = 86,
- MX53_PAD_EIM_A24 = 87,
- MX53_PAD_EIM_A23 = 88,
- MX53_PAD_EIM_A22 = 89,
- MX53_PAD_EIM_A21 = 90,
- MX53_PAD_EIM_A20 = 91,
- MX53_PAD_EIM_A19 = 92,
- MX53_PAD_EIM_A18 = 93,
- MX53_PAD_EIM_A17 = 94,
- MX53_PAD_EIM_A16 = 95,
- MX53_PAD_EIM_CS0 = 96,
- MX53_PAD_EIM_CS1 = 97,
- MX53_PAD_EIM_OE = 98,
- MX53_PAD_EIM_RW = 99,
- MX53_PAD_EIM_LBA = 100,
- MX53_PAD_EIM_EB0 = 101,
- MX53_PAD_EIM_EB1 = 102,
- MX53_PAD_EIM_DA0 = 103,
- MX53_PAD_EIM_DA1 = 104,
- MX53_PAD_EIM_DA2 = 105,
- MX53_PAD_EIM_DA3 = 106,
- MX53_PAD_EIM_DA4 = 107,
- MX53_PAD_EIM_DA5 = 108,
- MX53_PAD_EIM_DA6 = 109,
- MX53_PAD_EIM_DA7 = 110,
- MX53_PAD_EIM_DA8 = 111,
- MX53_PAD_EIM_DA9 = 112,
- MX53_PAD_EIM_DA10 = 113,
- MX53_PAD_EIM_DA11 = 114,
- MX53_PAD_EIM_DA12 = 115,
- MX53_PAD_EIM_DA13 = 116,
- MX53_PAD_EIM_DA14 = 117,
- MX53_PAD_EIM_DA15 = 118,
- MX53_PAD_NANDF_WE_B = 119,
- MX53_PAD_NANDF_RE_B = 120,
- MX53_PAD_EIM_WAIT = 121,
- MX53_PAD_RESERVE8 = 122,
- MX53_PAD_LVDS1_TX3_P = 123,
- MX53_PAD_LVDS1_TX2_P = 124,
- MX53_PAD_LVDS1_CLK_P = 125,
- MX53_PAD_LVDS1_TX1_P = 126,
- MX53_PAD_LVDS1_TX0_P = 127,
- MX53_PAD_LVDS0_TX3_P = 128,
- MX53_PAD_LVDS0_CLK_P = 129,
- MX53_PAD_LVDS0_TX2_P = 130,
- MX53_PAD_LVDS0_TX1_P = 131,
- MX53_PAD_LVDS0_TX0_P = 132,
- MX53_PAD_GPIO_10 = 133,
- MX53_PAD_GPIO_11 = 134,
- MX53_PAD_GPIO_12 = 135,
- MX53_PAD_GPIO_13 = 136,
- MX53_PAD_GPIO_14 = 137,
- MX53_PAD_NANDF_CLE = 138,
- MX53_PAD_NANDF_ALE = 139,
- MX53_PAD_NANDF_WP_B = 140,
- MX53_PAD_NANDF_RB0 = 141,
- MX53_PAD_NANDF_CS0 = 142,
- MX53_PAD_NANDF_CS1 = 143,
- MX53_PAD_NANDF_CS2 = 144,
- MX53_PAD_NANDF_CS3 = 145,
- MX53_PAD_FEC_MDIO = 146,
- MX53_PAD_FEC_REF_CLK = 147,
- MX53_PAD_FEC_RX_ER = 148,
- MX53_PAD_FEC_CRS_DV = 149,
- MX53_PAD_FEC_RXD1 = 150,
- MX53_PAD_FEC_RXD0 = 151,
- MX53_PAD_FEC_TX_EN = 152,
- MX53_PAD_FEC_TXD1 = 153,
- MX53_PAD_FEC_TXD0 = 154,
- MX53_PAD_FEC_MDC = 155,
- MX53_PAD_PATA_DIOW = 156,
- MX53_PAD_PATA_DMACK = 157,
- MX53_PAD_PATA_DMARQ = 158,
- MX53_PAD_PATA_BUFFER_EN = 159,
- MX53_PAD_PATA_INTRQ = 160,
- MX53_PAD_PATA_DIOR = 161,
- MX53_PAD_PATA_RESET_B = 162,
- MX53_PAD_PATA_IORDY = 163,
- MX53_PAD_PATA_DA_0 = 164,
- MX53_PAD_PATA_DA_1 = 165,
- MX53_PAD_PATA_DA_2 = 166,
- MX53_PAD_PATA_CS_0 = 167,
- MX53_PAD_PATA_CS_1 = 168,
- MX53_PAD_PATA_DATA0 = 169,
- MX53_PAD_PATA_DATA1 = 170,
- MX53_PAD_PATA_DATA2 = 171,
- MX53_PAD_PATA_DATA3 = 172,
- MX53_PAD_PATA_DATA4 = 173,
- MX53_PAD_PATA_DATA5 = 174,
- MX53_PAD_PATA_DATA6 = 175,
- MX53_PAD_PATA_DATA7 = 176,
- MX53_PAD_PATA_DATA8 = 177,
- MX53_PAD_PATA_DATA9 = 178,
- MX53_PAD_PATA_DATA10 = 179,
- MX53_PAD_PATA_DATA11 = 180,
- MX53_PAD_PATA_DATA12 = 181,
- MX53_PAD_PATA_DATA13 = 182,
- MX53_PAD_PATA_DATA14 = 183,
- MX53_PAD_PATA_DATA15 = 184,
- MX53_PAD_SD1_DATA0 = 185,
- MX53_PAD_SD1_DATA1 = 186,
- MX53_PAD_SD1_CMD = 187,
- MX53_PAD_SD1_DATA2 = 188,
- MX53_PAD_SD1_CLK = 189,
- MX53_PAD_SD1_DATA3 = 190,
- MX53_PAD_SD2_CLK = 191,
- MX53_PAD_SD2_CMD = 192,
- MX53_PAD_SD2_DATA3 = 193,
- MX53_PAD_SD2_DATA2 = 194,
- MX53_PAD_SD2_DATA1 = 195,
- MX53_PAD_SD2_DATA0 = 196,
- MX53_PAD_GPIO_0 = 197,
- MX53_PAD_GPIO_1 = 198,
- MX53_PAD_GPIO_9 = 199,
- MX53_PAD_GPIO_3 = 200,
- MX53_PAD_GPIO_6 = 201,
- MX53_PAD_GPIO_2 = 202,
- MX53_PAD_GPIO_4 = 203,
- MX53_PAD_GPIO_5 = 204,
- MX53_PAD_GPIO_7 = 205,
- MX53_PAD_GPIO_8 = 206,
- MX53_PAD_GPIO_16 = 207,
- MX53_PAD_GPIO_17 = 208,
- MX53_PAD_GPIO_18 = 209,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(MX53_PAD_RESERVE0),
- IMX_PINCTRL_PIN(MX53_PAD_RESERVE1),
- IMX_PINCTRL_PIN(MX53_PAD_RESERVE2),
- IMX_PINCTRL_PIN(MX53_PAD_RESERVE3),
- IMX_PINCTRL_PIN(MX53_PAD_RESERVE4),
- IMX_PINCTRL_PIN(MX53_PAD_RESERVE5),
- IMX_PINCTRL_PIN(MX53_PAD_RESERVE6),
- IMX_PINCTRL_PIN(MX53_PAD_RESERVE7),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_19),
- IMX_PINCTRL_PIN(MX53_PAD_KEY_COL0),
- IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW0),
- IMX_PINCTRL_PIN(MX53_PAD_KEY_COL1),
- IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW1),
- IMX_PINCTRL_PIN(MX53_PAD_KEY_COL2),
- IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW2),
- IMX_PINCTRL_PIN(MX53_PAD_KEY_COL3),
- IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW3),
- IMX_PINCTRL_PIN(MX53_PAD_KEY_COL4),
- IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW4),
- IMX_PINCTRL_PIN(MX53_PAD_DI0_DISP_CLK),
- IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN15),
- IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN2),
- IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN3),
- IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN4),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT0),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT1),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT2),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT3),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT4),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT5),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT6),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT7),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT8),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT9),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT10),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT11),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT12),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT13),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT14),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT15),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT16),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT17),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT18),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT19),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT20),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT21),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT22),
- IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT23),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_PIXCLK),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_MCLK),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DATA_EN),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_VSYNC),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT4),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT5),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT6),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT7),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT8),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT9),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT10),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT11),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT12),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT13),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT14),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT15),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT16),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT17),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT18),
- IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT19),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_A25),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_EB2),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D16),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D17),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D18),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D19),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D20),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D21),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D22),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D23),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_EB3),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D24),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D25),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D26),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D27),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D28),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D29),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D30),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_D31),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_A24),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_A23),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_A22),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_A21),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_A20),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_A19),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_A18),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_A17),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_A16),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_CS0),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_CS1),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_OE),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_RW),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_LBA),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_EB0),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_EB1),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA0),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA1),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA2),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA3),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA4),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA5),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA6),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA7),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA8),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA9),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA10),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA11),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA12),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA13),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA14),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_DA15),
- IMX_PINCTRL_PIN(MX53_PAD_NANDF_WE_B),
- IMX_PINCTRL_PIN(MX53_PAD_NANDF_RE_B),
- IMX_PINCTRL_PIN(MX53_PAD_EIM_WAIT),
- IMX_PINCTRL_PIN(MX53_PAD_RESERVE8),
- IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX3_P),
- IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX2_P),
- IMX_PINCTRL_PIN(MX53_PAD_LVDS1_CLK_P),
- IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX1_P),
- IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX0_P),
- IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX3_P),
- IMX_PINCTRL_PIN(MX53_PAD_LVDS0_CLK_P),
- IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX2_P),
- IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX1_P),
- IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX0_P),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_10),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_11),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_12),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_13),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_14),
- IMX_PINCTRL_PIN(MX53_PAD_NANDF_CLE),
- IMX_PINCTRL_PIN(MX53_PAD_NANDF_ALE),
- IMX_PINCTRL_PIN(MX53_PAD_NANDF_WP_B),
- IMX_PINCTRL_PIN(MX53_PAD_NANDF_RB0),
- IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS0),
- IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS1),
- IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS2),
- IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS3),
- IMX_PINCTRL_PIN(MX53_PAD_FEC_MDIO),
- IMX_PINCTRL_PIN(MX53_PAD_FEC_REF_CLK),
- IMX_PINCTRL_PIN(MX53_PAD_FEC_RX_ER),
- IMX_PINCTRL_PIN(MX53_PAD_FEC_CRS_DV),
- IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD1),
- IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD0),
- IMX_PINCTRL_PIN(MX53_PAD_FEC_TX_EN),
- IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD1),
- IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD0),
- IMX_PINCTRL_PIN(MX53_PAD_FEC_MDC),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOW),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DMACK),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DMARQ),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_BUFFER_EN),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_INTRQ),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOR),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_RESET_B),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_IORDY),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_0),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_1),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_2),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_0),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_1),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA0),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA1),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA2),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA3),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA4),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA5),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA6),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA7),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA8),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA9),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA10),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA11),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA12),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA13),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA14),
- IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA15),
- IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA0),
- IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA1),
- IMX_PINCTRL_PIN(MX53_PAD_SD1_CMD),
- IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA2),
- IMX_PINCTRL_PIN(MX53_PAD_SD1_CLK),
- IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA3),
- IMX_PINCTRL_PIN(MX53_PAD_SD2_CLK),
- IMX_PINCTRL_PIN(MX53_PAD_SD2_CMD),
- IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA3),
- IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA2),
- IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA1),
- IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA0),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_0),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_1),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_9),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_3),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_6),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_2),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_4),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_5),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_7),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_8),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_16),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_17),
- IMX_PINCTRL_PIN(MX53_PAD_GPIO_18),
-};
-
-static struct imx_pinctrl_soc_info imx53_pinctrl_info = {
- .pins = imx53_pinctrl_pads,
- .npins = ARRAY_SIZE(imx53_pinctrl_pads),
-};
-
-static struct of_device_id imx53_pinctrl_of_match[] = {
- { .compatible = "fsl,imx53-iomuxc", },
- { /* sentinel */ }
-};
-
-static int imx53_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &imx53_pinctrl_info);
-}
-
-static struct platform_driver imx53_pinctrl_driver = {
- .driver = {
- .name = "imx53-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = imx53_pinctrl_of_match,
- },
- .probe = imx53_pinctrl_probe,
- .remove = imx_pinctrl_remove,
-};
-
-static int __init imx53_pinctrl_init(void)
-{
- return platform_driver_register(&imx53_pinctrl_driver);
-}
-arch_initcall(imx53_pinctrl_init);
-
-static void __exit imx53_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx53_pinctrl_driver);
-}
-module_exit(imx53_pinctrl_exit);
-MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
-MODULE_DESCRIPTION("Freescale IMX53 pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#include "pinctrl-imx.h"
-
-enum imx6dl_pads {
- MX6DL_PAD_RESERVE0 = 0,
- MX6DL_PAD_RESERVE1 = 1,
- MX6DL_PAD_RESERVE2 = 2,
- MX6DL_PAD_RESERVE3 = 3,
- MX6DL_PAD_RESERVE4 = 4,
- MX6DL_PAD_RESERVE5 = 5,
- MX6DL_PAD_RESERVE6 = 6,
- MX6DL_PAD_RESERVE7 = 7,
- MX6DL_PAD_RESERVE8 = 8,
- MX6DL_PAD_RESERVE9 = 9,
- MX6DL_PAD_RESERVE10 = 10,
- MX6DL_PAD_RESERVE11 = 11,
- MX6DL_PAD_RESERVE12 = 12,
- MX6DL_PAD_RESERVE13 = 13,
- MX6DL_PAD_RESERVE14 = 14,
- MX6DL_PAD_RESERVE15 = 15,
- MX6DL_PAD_RESERVE16 = 16,
- MX6DL_PAD_RESERVE17 = 17,
- MX6DL_PAD_RESERVE18 = 18,
- MX6DL_PAD_CSI0_DAT10 = 19,
- MX6DL_PAD_CSI0_DAT11 = 20,
- MX6DL_PAD_CSI0_DAT12 = 21,
- MX6DL_PAD_CSI0_DAT13 = 22,
- MX6DL_PAD_CSI0_DAT14 = 23,
- MX6DL_PAD_CSI0_DAT15 = 24,
- MX6DL_PAD_CSI0_DAT16 = 25,
- MX6DL_PAD_CSI0_DAT17 = 26,
- MX6DL_PAD_CSI0_DAT18 = 27,
- MX6DL_PAD_CSI0_DAT19 = 28,
- MX6DL_PAD_CSI0_DAT4 = 29,
- MX6DL_PAD_CSI0_DAT5 = 30,
- MX6DL_PAD_CSI0_DAT6 = 31,
- MX6DL_PAD_CSI0_DAT7 = 32,
- MX6DL_PAD_CSI0_DAT8 = 33,
- MX6DL_PAD_CSI0_DAT9 = 34,
- MX6DL_PAD_CSI0_DATA_EN = 35,
- MX6DL_PAD_CSI0_MCLK = 36,
- MX6DL_PAD_CSI0_PIXCLK = 37,
- MX6DL_PAD_CSI0_VSYNC = 38,
- MX6DL_PAD_DI0_DISP_CLK = 39,
- MX6DL_PAD_DI0_PIN15 = 40,
- MX6DL_PAD_DI0_PIN2 = 41,
- MX6DL_PAD_DI0_PIN3 = 42,
- MX6DL_PAD_DI0_PIN4 = 43,
- MX6DL_PAD_DISP0_DAT0 = 44,
- MX6DL_PAD_DISP0_DAT1 = 45,
- MX6DL_PAD_DISP0_DAT10 = 46,
- MX6DL_PAD_DISP0_DAT11 = 47,
- MX6DL_PAD_DISP0_DAT12 = 48,
- MX6DL_PAD_DISP0_DAT13 = 49,
- MX6DL_PAD_DISP0_DAT14 = 50,
- MX6DL_PAD_DISP0_DAT15 = 51,
- MX6DL_PAD_DISP0_DAT16 = 52,
- MX6DL_PAD_DISP0_DAT17 = 53,
- MX6DL_PAD_DISP0_DAT18 = 54,
- MX6DL_PAD_DISP0_DAT19 = 55,
- MX6DL_PAD_DISP0_DAT2 = 56,
- MX6DL_PAD_DISP0_DAT20 = 57,
- MX6DL_PAD_DISP0_DAT21 = 58,
- MX6DL_PAD_DISP0_DAT22 = 59,
- MX6DL_PAD_DISP0_DAT23 = 60,
- MX6DL_PAD_DISP0_DAT3 = 61,
- MX6DL_PAD_DISP0_DAT4 = 62,
- MX6DL_PAD_DISP0_DAT5 = 63,
- MX6DL_PAD_DISP0_DAT6 = 64,
- MX6DL_PAD_DISP0_DAT7 = 65,
- MX6DL_PAD_DISP0_DAT8 = 66,
- MX6DL_PAD_DISP0_DAT9 = 67,
- MX6DL_PAD_EIM_A16 = 68,
- MX6DL_PAD_EIM_A17 = 69,
- MX6DL_PAD_EIM_A18 = 70,
- MX6DL_PAD_EIM_A19 = 71,
- MX6DL_PAD_EIM_A20 = 72,
- MX6DL_PAD_EIM_A21 = 73,
- MX6DL_PAD_EIM_A22 = 74,
- MX6DL_PAD_EIM_A23 = 75,
- MX6DL_PAD_EIM_A24 = 76,
- MX6DL_PAD_EIM_A25 = 77,
- MX6DL_PAD_EIM_BCLK = 78,
- MX6DL_PAD_EIM_CS0 = 79,
- MX6DL_PAD_EIM_CS1 = 80,
- MX6DL_PAD_EIM_D16 = 81,
- MX6DL_PAD_EIM_D17 = 82,
- MX6DL_PAD_EIM_D18 = 83,
- MX6DL_PAD_EIM_D19 = 84,
- MX6DL_PAD_EIM_D20 = 85,
- MX6DL_PAD_EIM_D21 = 86,
- MX6DL_PAD_EIM_D22 = 87,
- MX6DL_PAD_EIM_D23 = 88,
- MX6DL_PAD_EIM_D24 = 89,
- MX6DL_PAD_EIM_D25 = 90,
- MX6DL_PAD_EIM_D26 = 91,
- MX6DL_PAD_EIM_D27 = 92,
- MX6DL_PAD_EIM_D28 = 93,
- MX6DL_PAD_EIM_D29 = 94,
- MX6DL_PAD_EIM_D30 = 95,
- MX6DL_PAD_EIM_D31 = 96,
- MX6DL_PAD_EIM_DA0 = 97,
- MX6DL_PAD_EIM_DA1 = 98,
- MX6DL_PAD_EIM_DA10 = 99,
- MX6DL_PAD_EIM_DA11 = 100,
- MX6DL_PAD_EIM_DA12 = 101,
- MX6DL_PAD_EIM_DA13 = 102,
- MX6DL_PAD_EIM_DA14 = 103,
- MX6DL_PAD_EIM_DA15 = 104,
- MX6DL_PAD_EIM_DA2 = 105,
- MX6DL_PAD_EIM_DA3 = 106,
- MX6DL_PAD_EIM_DA4 = 107,
- MX6DL_PAD_EIM_DA5 = 108,
- MX6DL_PAD_EIM_DA6 = 109,
- MX6DL_PAD_EIM_DA7 = 110,
- MX6DL_PAD_EIM_DA8 = 111,
- MX6DL_PAD_EIM_DA9 = 112,
- MX6DL_PAD_EIM_EB0 = 113,
- MX6DL_PAD_EIM_EB1 = 114,
- MX6DL_PAD_EIM_EB2 = 115,
- MX6DL_PAD_EIM_EB3 = 116,
- MX6DL_PAD_EIM_LBA = 117,
- MX6DL_PAD_EIM_OE = 118,
- MX6DL_PAD_EIM_RW = 119,
- MX6DL_PAD_EIM_WAIT = 120,
- MX6DL_PAD_ENET_CRS_DV = 121,
- MX6DL_PAD_ENET_MDC = 122,
- MX6DL_PAD_ENET_MDIO = 123,
- MX6DL_PAD_ENET_REF_CLK = 124,
- MX6DL_PAD_ENET_RX_ER = 125,
- MX6DL_PAD_ENET_RXD0 = 126,
- MX6DL_PAD_ENET_RXD1 = 127,
- MX6DL_PAD_ENET_TX_EN = 128,
- MX6DL_PAD_ENET_TXD0 = 129,
- MX6DL_PAD_ENET_TXD1 = 130,
- MX6DL_PAD_GPIO_0 = 131,
- MX6DL_PAD_GPIO_1 = 132,
- MX6DL_PAD_GPIO_16 = 133,
- MX6DL_PAD_GPIO_17 = 134,
- MX6DL_PAD_GPIO_18 = 135,
- MX6DL_PAD_GPIO_19 = 136,
- MX6DL_PAD_GPIO_2 = 137,
- MX6DL_PAD_GPIO_3 = 138,
- MX6DL_PAD_GPIO_4 = 139,
- MX6DL_PAD_GPIO_5 = 140,
- MX6DL_PAD_GPIO_6 = 141,
- MX6DL_PAD_GPIO_7 = 142,
- MX6DL_PAD_GPIO_8 = 143,
- MX6DL_PAD_GPIO_9 = 144,
- MX6DL_PAD_KEY_COL0 = 145,
- MX6DL_PAD_KEY_COL1 = 146,
- MX6DL_PAD_KEY_COL2 = 147,
- MX6DL_PAD_KEY_COL3 = 148,
- MX6DL_PAD_KEY_COL4 = 149,
- MX6DL_PAD_KEY_ROW0 = 150,
- MX6DL_PAD_KEY_ROW1 = 151,
- MX6DL_PAD_KEY_ROW2 = 152,
- MX6DL_PAD_KEY_ROW3 = 153,
- MX6DL_PAD_KEY_ROW4 = 154,
- MX6DL_PAD_NANDF_ALE = 155,
- MX6DL_PAD_NANDF_CLE = 156,
- MX6DL_PAD_NANDF_CS0 = 157,
- MX6DL_PAD_NANDF_CS1 = 158,
- MX6DL_PAD_NANDF_CS2 = 159,
- MX6DL_PAD_NANDF_CS3 = 160,
- MX6DL_PAD_NANDF_D0 = 161,
- MX6DL_PAD_NANDF_D1 = 162,
- MX6DL_PAD_NANDF_D2 = 163,
- MX6DL_PAD_NANDF_D3 = 164,
- MX6DL_PAD_NANDF_D4 = 165,
- MX6DL_PAD_NANDF_D5 = 166,
- MX6DL_PAD_NANDF_D6 = 167,
- MX6DL_PAD_NANDF_D7 = 168,
- MX6DL_PAD_NANDF_RB0 = 169,
- MX6DL_PAD_NANDF_WP_B = 170,
- MX6DL_PAD_RGMII_RD0 = 171,
- MX6DL_PAD_RGMII_RD1 = 172,
- MX6DL_PAD_RGMII_RD2 = 173,
- MX6DL_PAD_RGMII_RD3 = 174,
- MX6DL_PAD_RGMII_RX_CTL = 175,
- MX6DL_PAD_RGMII_RXC = 176,
- MX6DL_PAD_RGMII_TD0 = 177,
- MX6DL_PAD_RGMII_TD1 = 178,
- MX6DL_PAD_RGMII_TD2 = 179,
- MX6DL_PAD_RGMII_TD3 = 180,
- MX6DL_PAD_RGMII_TX_CTL = 181,
- MX6DL_PAD_RGMII_TXC = 182,
- MX6DL_PAD_SD1_CLK = 183,
- MX6DL_PAD_SD1_CMD = 184,
- MX6DL_PAD_SD1_DAT0 = 185,
- MX6DL_PAD_SD1_DAT1 = 186,
- MX6DL_PAD_SD1_DAT2 = 187,
- MX6DL_PAD_SD1_DAT3 = 188,
- MX6DL_PAD_SD2_CLK = 189,
- MX6DL_PAD_SD2_CMD = 190,
- MX6DL_PAD_SD2_DAT0 = 191,
- MX6DL_PAD_SD2_DAT1 = 192,
- MX6DL_PAD_SD2_DAT2 = 193,
- MX6DL_PAD_SD2_DAT3 = 194,
- MX6DL_PAD_SD3_CLK = 195,
- MX6DL_PAD_SD3_CMD = 196,
- MX6DL_PAD_SD3_DAT0 = 197,
- MX6DL_PAD_SD3_DAT1 = 198,
- MX6DL_PAD_SD3_DAT2 = 199,
- MX6DL_PAD_SD3_DAT3 = 200,
- MX6DL_PAD_SD3_DAT4 = 201,
- MX6DL_PAD_SD3_DAT5 = 202,
- MX6DL_PAD_SD3_DAT6 = 203,
- MX6DL_PAD_SD3_DAT7 = 204,
- MX6DL_PAD_SD3_RST = 205,
- MX6DL_PAD_SD4_CLK = 206,
- MX6DL_PAD_SD4_CMD = 207,
- MX6DL_PAD_SD4_DAT0 = 208,
- MX6DL_PAD_SD4_DAT1 = 209,
- MX6DL_PAD_SD4_DAT2 = 210,
- MX6DL_PAD_SD4_DAT3 = 211,
- MX6DL_PAD_SD4_DAT4 = 212,
- MX6DL_PAD_SD4_DAT5 = 213,
- MX6DL_PAD_SD4_DAT6 = 214,
- MX6DL_PAD_SD4_DAT7 = 215,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE0),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE1),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE2),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE3),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE4),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE5),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE6),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE7),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE8),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE9),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE10),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE11),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE12),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE13),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE14),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE15),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE16),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE17),
- IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE18),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT10),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT11),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT12),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT13),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT14),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT15),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT16),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT17),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT18),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT19),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT4),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT5),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT6),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT7),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT8),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT9),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DATA_EN),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_MCLK),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_PIXCLK),
- IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_VSYNC),
- IMX_PINCTRL_PIN(MX6DL_PAD_DI0_DISP_CLK),
- IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN15),
- IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN2),
- IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN3),
- IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN4),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT0),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT1),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT10),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT11),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT12),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT13),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT14),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT15),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT16),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT17),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT18),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT19),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT2),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT20),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT21),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT22),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT23),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT3),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT4),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT5),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT6),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT7),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT8),
- IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT9),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A16),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A17),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A18),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A19),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A20),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A21),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A22),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A23),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A24),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A25),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_BCLK),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS0),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS1),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D16),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D17),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D18),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D19),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D20),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D21),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D22),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D23),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D24),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D25),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D26),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D27),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D28),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D29),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D30),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D31),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA0),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA1),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA10),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA11),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA12),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA13),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA14),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA15),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA2),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA3),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA4),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA5),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA6),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA7),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA8),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA9),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB0),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB1),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB2),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB3),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_LBA),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_OE),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_RW),
- IMX_PINCTRL_PIN(MX6DL_PAD_EIM_WAIT),
- IMX_PINCTRL_PIN(MX6DL_PAD_ENET_CRS_DV),
- IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDC),
- IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDIO),
- IMX_PINCTRL_PIN(MX6DL_PAD_ENET_REF_CLK),
- IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RX_ER),
- IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD0),
- IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD1),
- IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TX_EN),
- IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD0),
- IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD1),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_0),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_1),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_16),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_17),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_18),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_19),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_2),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_3),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_4),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_5),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_6),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_7),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_8),
- IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_9),
- IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL0),
- IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL1),
- IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL2),
- IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL3),
- IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL4),
- IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW0),
- IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW1),
- IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW2),
- IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW3),
- IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW4),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_ALE),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CLE),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS0),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS1),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS2),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS3),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D0),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D1),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D2),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D3),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D4),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D5),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D6),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D7),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_RB0),
- IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_WP_B),
- IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD0),
- IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD1),
- IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD2),
- IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD3),
- IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RX_CTL),
- IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RXC),
- IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD0),
- IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD1),
- IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD2),
- IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD3),
- IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TX_CTL),
- IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TXC),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CLK),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CMD),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT0),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT1),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT2),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT3),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CLK),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CMD),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT0),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT1),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT2),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT3),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CLK),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CMD),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT0),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT1),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT2),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT3),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT4),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT5),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT6),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT7),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD3_RST),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CLK),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CMD),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT0),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT1),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT2),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT3),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT4),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT5),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT6),
- IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7),
-};
-
-static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
- .pins = imx6dl_pinctrl_pads,
- .npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
-};
-
-static struct of_device_id imx6dl_pinctrl_of_match[] = {
- { .compatible = "fsl,imx6dl-iomuxc", },
- { /* sentinel */ }
-};
-
-static int imx6dl_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &imx6dl_pinctrl_info);
-}
-
-static struct platform_driver imx6dl_pinctrl_driver = {
- .driver = {
- .name = "imx6dl-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = imx6dl_pinctrl_of_match,
- },
- .probe = imx6dl_pinctrl_probe,
- .remove = imx_pinctrl_remove,
-};
-
-static int __init imx6dl_pinctrl_init(void)
-{
- return platform_driver_register(&imx6dl_pinctrl_driver);
-}
-arch_initcall(imx6dl_pinctrl_init);
-
-static void __exit imx6dl_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx6dl_pinctrl_driver);
-}
-module_exit(imx6dl_pinctrl_exit);
-
-MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
-MODULE_DESCRIPTION("Freescale imx6dl pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * imx6q pinctrl driver based on imx pinmux core
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro, Inc.
- *
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#include "pinctrl-imx.h"
-
-enum imx6q_pads {
- MX6Q_PAD_RESERVE0 = 0,
- MX6Q_PAD_RESERVE1 = 1,
- MX6Q_PAD_RESERVE2 = 2,
- MX6Q_PAD_RESERVE3 = 3,
- MX6Q_PAD_RESERVE4 = 4,
- MX6Q_PAD_RESERVE5 = 5,
- MX6Q_PAD_RESERVE6 = 6,
- MX6Q_PAD_RESERVE7 = 7,
- MX6Q_PAD_RESERVE8 = 8,
- MX6Q_PAD_RESERVE9 = 9,
- MX6Q_PAD_RESERVE10 = 10,
- MX6Q_PAD_RESERVE11 = 11,
- MX6Q_PAD_RESERVE12 = 12,
- MX6Q_PAD_RESERVE13 = 13,
- MX6Q_PAD_RESERVE14 = 14,
- MX6Q_PAD_RESERVE15 = 15,
- MX6Q_PAD_RESERVE16 = 16,
- MX6Q_PAD_RESERVE17 = 17,
- MX6Q_PAD_RESERVE18 = 18,
- MX6Q_PAD_SD2_DAT1 = 19,
- MX6Q_PAD_SD2_DAT2 = 20,
- MX6Q_PAD_SD2_DAT0 = 21,
- MX6Q_PAD_RGMII_TXC = 22,
- MX6Q_PAD_RGMII_TD0 = 23,
- MX6Q_PAD_RGMII_TD1 = 24,
- MX6Q_PAD_RGMII_TD2 = 25,
- MX6Q_PAD_RGMII_TD3 = 26,
- MX6Q_PAD_RGMII_RX_CTL = 27,
- MX6Q_PAD_RGMII_RD0 = 28,
- MX6Q_PAD_RGMII_TX_CTL = 29,
- MX6Q_PAD_RGMII_RD1 = 30,
- MX6Q_PAD_RGMII_RD2 = 31,
- MX6Q_PAD_RGMII_RD3 = 32,
- MX6Q_PAD_RGMII_RXC = 33,
- MX6Q_PAD_EIM_A25 = 34,
- MX6Q_PAD_EIM_EB2 = 35,
- MX6Q_PAD_EIM_D16 = 36,
- MX6Q_PAD_EIM_D17 = 37,
- MX6Q_PAD_EIM_D18 = 38,
- MX6Q_PAD_EIM_D19 = 39,
- MX6Q_PAD_EIM_D20 = 40,
- MX6Q_PAD_EIM_D21 = 41,
- MX6Q_PAD_EIM_D22 = 42,
- MX6Q_PAD_EIM_D23 = 43,
- MX6Q_PAD_EIM_EB3 = 44,
- MX6Q_PAD_EIM_D24 = 45,
- MX6Q_PAD_EIM_D25 = 46,
- MX6Q_PAD_EIM_D26 = 47,
- MX6Q_PAD_EIM_D27 = 48,
- MX6Q_PAD_EIM_D28 = 49,
- MX6Q_PAD_EIM_D29 = 50,
- MX6Q_PAD_EIM_D30 = 51,
- MX6Q_PAD_EIM_D31 = 52,
- MX6Q_PAD_EIM_A24 = 53,
- MX6Q_PAD_EIM_A23 = 54,
- MX6Q_PAD_EIM_A22 = 55,
- MX6Q_PAD_EIM_A21 = 56,
- MX6Q_PAD_EIM_A20 = 57,
- MX6Q_PAD_EIM_A19 = 58,
- MX6Q_PAD_EIM_A18 = 59,
- MX6Q_PAD_EIM_A17 = 60,
- MX6Q_PAD_EIM_A16 = 61,
- MX6Q_PAD_EIM_CS0 = 62,
- MX6Q_PAD_EIM_CS1 = 63,
- MX6Q_PAD_EIM_OE = 64,
- MX6Q_PAD_EIM_RW = 65,
- MX6Q_PAD_EIM_LBA = 66,
- MX6Q_PAD_EIM_EB0 = 67,
- MX6Q_PAD_EIM_EB1 = 68,
- MX6Q_PAD_EIM_DA0 = 69,
- MX6Q_PAD_EIM_DA1 = 70,
- MX6Q_PAD_EIM_DA2 = 71,
- MX6Q_PAD_EIM_DA3 = 72,
- MX6Q_PAD_EIM_DA4 = 73,
- MX6Q_PAD_EIM_DA5 = 74,
- MX6Q_PAD_EIM_DA6 = 75,
- MX6Q_PAD_EIM_DA7 = 76,
- MX6Q_PAD_EIM_DA8 = 77,
- MX6Q_PAD_EIM_DA9 = 78,
- MX6Q_PAD_EIM_DA10 = 79,
- MX6Q_PAD_EIM_DA11 = 80,
- MX6Q_PAD_EIM_DA12 = 81,
- MX6Q_PAD_EIM_DA13 = 82,
- MX6Q_PAD_EIM_DA14 = 83,
- MX6Q_PAD_EIM_DA15 = 84,
- MX6Q_PAD_EIM_WAIT = 85,
- MX6Q_PAD_EIM_BCLK = 86,
- MX6Q_PAD_DI0_DISP_CLK = 87,
- MX6Q_PAD_DI0_PIN15 = 88,
- MX6Q_PAD_DI0_PIN2 = 89,
- MX6Q_PAD_DI0_PIN3 = 90,
- MX6Q_PAD_DI0_PIN4 = 91,
- MX6Q_PAD_DISP0_DAT0 = 92,
- MX6Q_PAD_DISP0_DAT1 = 93,
- MX6Q_PAD_DISP0_DAT2 = 94,
- MX6Q_PAD_DISP0_DAT3 = 95,
- MX6Q_PAD_DISP0_DAT4 = 96,
- MX6Q_PAD_DISP0_DAT5 = 97,
- MX6Q_PAD_DISP0_DAT6 = 98,
- MX6Q_PAD_DISP0_DAT7 = 99,
- MX6Q_PAD_DISP0_DAT8 = 100,
- MX6Q_PAD_DISP0_DAT9 = 101,
- MX6Q_PAD_DISP0_DAT10 = 102,
- MX6Q_PAD_DISP0_DAT11 = 103,
- MX6Q_PAD_DISP0_DAT12 = 104,
- MX6Q_PAD_DISP0_DAT13 = 105,
- MX6Q_PAD_DISP0_DAT14 = 106,
- MX6Q_PAD_DISP0_DAT15 = 107,
- MX6Q_PAD_DISP0_DAT16 = 108,
- MX6Q_PAD_DISP0_DAT17 = 109,
- MX6Q_PAD_DISP0_DAT18 = 110,
- MX6Q_PAD_DISP0_DAT19 = 111,
- MX6Q_PAD_DISP0_DAT20 = 112,
- MX6Q_PAD_DISP0_DAT21 = 113,
- MX6Q_PAD_DISP0_DAT22 = 114,
- MX6Q_PAD_DISP0_DAT23 = 115,
- MX6Q_PAD_ENET_MDIO = 116,
- MX6Q_PAD_ENET_REF_CLK = 117,
- MX6Q_PAD_ENET_RX_ER = 118,
- MX6Q_PAD_ENET_CRS_DV = 119,
- MX6Q_PAD_ENET_RXD1 = 120,
- MX6Q_PAD_ENET_RXD0 = 121,
- MX6Q_PAD_ENET_TX_EN = 122,
- MX6Q_PAD_ENET_TXD1 = 123,
- MX6Q_PAD_ENET_TXD0 = 124,
- MX6Q_PAD_ENET_MDC = 125,
- MX6Q_PAD_KEY_COL0 = 126,
- MX6Q_PAD_KEY_ROW0 = 127,
- MX6Q_PAD_KEY_COL1 = 128,
- MX6Q_PAD_KEY_ROW1 = 129,
- MX6Q_PAD_KEY_COL2 = 130,
- MX6Q_PAD_KEY_ROW2 = 131,
- MX6Q_PAD_KEY_COL3 = 132,
- MX6Q_PAD_KEY_ROW3 = 133,
- MX6Q_PAD_KEY_COL4 = 134,
- MX6Q_PAD_KEY_ROW4 = 135,
- MX6Q_PAD_GPIO_0 = 136,
- MX6Q_PAD_GPIO_1 = 137,
- MX6Q_PAD_GPIO_9 = 138,
- MX6Q_PAD_GPIO_3 = 139,
- MX6Q_PAD_GPIO_6 = 140,
- MX6Q_PAD_GPIO_2 = 141,
- MX6Q_PAD_GPIO_4 = 142,
- MX6Q_PAD_GPIO_5 = 143,
- MX6Q_PAD_GPIO_7 = 144,
- MX6Q_PAD_GPIO_8 = 145,
- MX6Q_PAD_GPIO_16 = 146,
- MX6Q_PAD_GPIO_17 = 147,
- MX6Q_PAD_GPIO_18 = 148,
- MX6Q_PAD_GPIO_19 = 149,
- MX6Q_PAD_CSI0_PIXCLK = 150,
- MX6Q_PAD_CSI0_MCLK = 151,
- MX6Q_PAD_CSI0_DATA_EN = 152,
- MX6Q_PAD_CSI0_VSYNC = 153,
- MX6Q_PAD_CSI0_DAT4 = 154,
- MX6Q_PAD_CSI0_DAT5 = 155,
- MX6Q_PAD_CSI0_DAT6 = 156,
- MX6Q_PAD_CSI0_DAT7 = 157,
- MX6Q_PAD_CSI0_DAT8 = 158,
- MX6Q_PAD_CSI0_DAT9 = 159,
- MX6Q_PAD_CSI0_DAT10 = 160,
- MX6Q_PAD_CSI0_DAT11 = 161,
- MX6Q_PAD_CSI0_DAT12 = 162,
- MX6Q_PAD_CSI0_DAT13 = 163,
- MX6Q_PAD_CSI0_DAT14 = 164,
- MX6Q_PAD_CSI0_DAT15 = 165,
- MX6Q_PAD_CSI0_DAT16 = 166,
- MX6Q_PAD_CSI0_DAT17 = 167,
- MX6Q_PAD_CSI0_DAT18 = 168,
- MX6Q_PAD_CSI0_DAT19 = 169,
- MX6Q_PAD_SD3_DAT7 = 170,
- MX6Q_PAD_SD3_DAT6 = 171,
- MX6Q_PAD_SD3_DAT5 = 172,
- MX6Q_PAD_SD3_DAT4 = 173,
- MX6Q_PAD_SD3_CMD = 174,
- MX6Q_PAD_SD3_CLK = 175,
- MX6Q_PAD_SD3_DAT0 = 176,
- MX6Q_PAD_SD3_DAT1 = 177,
- MX6Q_PAD_SD3_DAT2 = 178,
- MX6Q_PAD_SD3_DAT3 = 179,
- MX6Q_PAD_SD3_RST = 180,
- MX6Q_PAD_NANDF_CLE = 181,
- MX6Q_PAD_NANDF_ALE = 182,
- MX6Q_PAD_NANDF_WP_B = 183,
- MX6Q_PAD_NANDF_RB0 = 184,
- MX6Q_PAD_NANDF_CS0 = 185,
- MX6Q_PAD_NANDF_CS1 = 186,
- MX6Q_PAD_NANDF_CS2 = 187,
- MX6Q_PAD_NANDF_CS3 = 188,
- MX6Q_PAD_SD4_CMD = 189,
- MX6Q_PAD_SD4_CLK = 190,
- MX6Q_PAD_NANDF_D0 = 191,
- MX6Q_PAD_NANDF_D1 = 192,
- MX6Q_PAD_NANDF_D2 = 193,
- MX6Q_PAD_NANDF_D3 = 194,
- MX6Q_PAD_NANDF_D4 = 195,
- MX6Q_PAD_NANDF_D5 = 196,
- MX6Q_PAD_NANDF_D6 = 197,
- MX6Q_PAD_NANDF_D7 = 198,
- MX6Q_PAD_SD4_DAT0 = 199,
- MX6Q_PAD_SD4_DAT1 = 200,
- MX6Q_PAD_SD4_DAT2 = 201,
- MX6Q_PAD_SD4_DAT3 = 202,
- MX6Q_PAD_SD4_DAT4 = 203,
- MX6Q_PAD_SD4_DAT5 = 204,
- MX6Q_PAD_SD4_DAT6 = 205,
- MX6Q_PAD_SD4_DAT7 = 206,
- MX6Q_PAD_SD1_DAT1 = 207,
- MX6Q_PAD_SD1_DAT0 = 208,
- MX6Q_PAD_SD1_DAT3 = 209,
- MX6Q_PAD_SD1_CMD = 210,
- MX6Q_PAD_SD1_DAT2 = 211,
- MX6Q_PAD_SD1_CLK = 212,
- MX6Q_PAD_SD2_CLK = 213,
- MX6Q_PAD_SD2_CMD = 214,
- MX6Q_PAD_SD2_DAT3 = 215,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE0),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE1),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE2),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE3),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE4),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE5),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE6),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE7),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE8),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE9),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE10),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE11),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE12),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE13),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE14),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE15),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE16),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE17),
- IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE18),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
- IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC),
- IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0),
- IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1),
- IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2),
- IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3),
- IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL),
- IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0),
- IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL),
- IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1),
- IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2),
- IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3),
- IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT),
- IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK),
- IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK),
- IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15),
- IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2),
- IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3),
- IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22),
- IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23),
- IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO),
- IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK),
- IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER),
- IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV),
- IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1),
- IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0),
- IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN),
- IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
- IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
- IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
- IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
- IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
- IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
- IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1),
- IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2),
- IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2),
- IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3),
- IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3),
- IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4),
- IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18),
- IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
- IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6),
- IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD),
- IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
-};
-
-static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
- .pins = imx6q_pinctrl_pads,
- .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
-};
-
-static struct of_device_id imx6q_pinctrl_of_match[] = {
- { .compatible = "fsl,imx6q-iomuxc", },
- { /* sentinel */ }
-};
-
-static int imx6q_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info);
-}
-
-static struct platform_driver imx6q_pinctrl_driver = {
- .driver = {
- .name = "imx6q-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = imx6q_pinctrl_of_match,
- },
- .probe = imx6q_pinctrl_probe,
- .remove = imx_pinctrl_remove,
-};
-
-static int __init imx6q_pinctrl_init(void)
-{
- return platform_driver_register(&imx6q_pinctrl_driver);
-}
-arch_initcall(imx6q_pinctrl_init);
-
-static void __exit imx6q_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx6q_pinctrl_driver);
-}
-module_exit(imx6q_pinctrl_exit);
-MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
-MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#include "pinctrl-imx.h"
-
-enum imx6sl_pads {
- MX6SL_PAD_RESERVE0 = 0,
- MX6SL_PAD_RESERVE1 = 1,
- MX6SL_PAD_RESERVE2 = 2,
- MX6SL_PAD_RESERVE3 = 3,
- MX6SL_PAD_RESERVE4 = 4,
- MX6SL_PAD_RESERVE5 = 5,
- MX6SL_PAD_RESERVE6 = 6,
- MX6SL_PAD_RESERVE7 = 7,
- MX6SL_PAD_RESERVE8 = 8,
- MX6SL_PAD_RESERVE9 = 9,
- MX6SL_PAD_RESERVE10 = 10,
- MX6SL_PAD_RESERVE11 = 11,
- MX6SL_PAD_RESERVE12 = 12,
- MX6SL_PAD_RESERVE13 = 13,
- MX6SL_PAD_RESERVE14 = 14,
- MX6SL_PAD_RESERVE15 = 15,
- MX6SL_PAD_RESERVE16 = 16,
- MX6SL_PAD_RESERVE17 = 17,
- MX6SL_PAD_RESERVE18 = 18,
- MX6SL_PAD_AUD_MCLK = 19,
- MX6SL_PAD_AUD_RXC = 20,
- MX6SL_PAD_AUD_RXD = 21,
- MX6SL_PAD_AUD_RXFS = 22,
- MX6SL_PAD_AUD_TXC = 23,
- MX6SL_PAD_AUD_TXD = 24,
- MX6SL_PAD_AUD_TXFS = 25,
- MX6SL_PAD_ECSPI1_MISO = 26,
- MX6SL_PAD_ECSPI1_MOSI = 27,
- MX6SL_PAD_ECSPI1_SCLK = 28,
- MX6SL_PAD_ECSPI1_SS0 = 29,
- MX6SL_PAD_ECSPI2_MISO = 30,
- MX6SL_PAD_ECSPI2_MOSI = 31,
- MX6SL_PAD_ECSPI2_SCLK = 32,
- MX6SL_PAD_ECSPI2_SS0 = 33,
- MX6SL_PAD_EPDC_BDR0 = 34,
- MX6SL_PAD_EPDC_BDR1 = 35,
- MX6SL_PAD_EPDC_D0 = 36,
- MX6SL_PAD_EPDC_D1 = 37,
- MX6SL_PAD_EPDC_D10 = 38,
- MX6SL_PAD_EPDC_D11 = 39,
- MX6SL_PAD_EPDC_D12 = 40,
- MX6SL_PAD_EPDC_D13 = 41,
- MX6SL_PAD_EPDC_D14 = 42,
- MX6SL_PAD_EPDC_D15 = 43,
- MX6SL_PAD_EPDC_D2 = 44,
- MX6SL_PAD_EPDC_D3 = 45,
- MX6SL_PAD_EPDC_D4 = 46,
- MX6SL_PAD_EPDC_D5 = 47,
- MX6SL_PAD_EPDC_D6 = 48,
- MX6SL_PAD_EPDC_D7 = 49,
- MX6SL_PAD_EPDC_D8 = 50,
- MX6SL_PAD_EPDC_D9 = 51,
- MX6SL_PAD_EPDC_GDCLK = 52,
- MX6SL_PAD_EPDC_GDOE = 53,
- MX6SL_PAD_EPDC_GDRL = 54,
- MX6SL_PAD_EPDC_GDSP = 55,
- MX6SL_PAD_EPDC_PWRCOM = 56,
- MX6SL_PAD_EPDC_PWRCTRL0 = 57,
- MX6SL_PAD_EPDC_PWRCTRL1 = 58,
- MX6SL_PAD_EPDC_PWRCTRL2 = 59,
- MX6SL_PAD_EPDC_PWRCTRL3 = 60,
- MX6SL_PAD_EPDC_PWRINT = 61,
- MX6SL_PAD_EPDC_PWRSTAT = 62,
- MX6SL_PAD_EPDC_PWRWAKEUP = 63,
- MX6SL_PAD_EPDC_SDCE0 = 64,
- MX6SL_PAD_EPDC_SDCE1 = 65,
- MX6SL_PAD_EPDC_SDCE2 = 66,
- MX6SL_PAD_EPDC_SDCE3 = 67,
- MX6SL_PAD_EPDC_SDCLK = 68,
- MX6SL_PAD_EPDC_SDLE = 69,
- MX6SL_PAD_EPDC_SDOE = 70,
- MX6SL_PAD_EPDC_SDSHR = 71,
- MX6SL_PAD_EPDC_VCOM0 = 72,
- MX6SL_PAD_EPDC_VCOM1 = 73,
- MX6SL_PAD_FEC_CRS_DV = 74,
- MX6SL_PAD_FEC_MDC = 75,
- MX6SL_PAD_FEC_MDIO = 76,
- MX6SL_PAD_FEC_REF_CLK = 77,
- MX6SL_PAD_FEC_RX_ER = 78,
- MX6SL_PAD_FEC_RXD0 = 79,
- MX6SL_PAD_FEC_RXD1 = 80,
- MX6SL_PAD_FEC_TX_CLK = 81,
- MX6SL_PAD_FEC_TX_EN = 82,
- MX6SL_PAD_FEC_TXD0 = 83,
- MX6SL_PAD_FEC_TXD1 = 84,
- MX6SL_PAD_HSIC_DAT = 85,
- MX6SL_PAD_HSIC_STROBE = 86,
- MX6SL_PAD_I2C1_SCL = 87,
- MX6SL_PAD_I2C1_SDA = 88,
- MX6SL_PAD_I2C2_SCL = 89,
- MX6SL_PAD_I2C2_SDA = 90,
- MX6SL_PAD_KEY_COL0 = 91,
- MX6SL_PAD_KEY_COL1 = 92,
- MX6SL_PAD_KEY_COL2 = 93,
- MX6SL_PAD_KEY_COL3 = 94,
- MX6SL_PAD_KEY_COL4 = 95,
- MX6SL_PAD_KEY_COL5 = 96,
- MX6SL_PAD_KEY_COL6 = 97,
- MX6SL_PAD_KEY_COL7 = 98,
- MX6SL_PAD_KEY_ROW0 = 99,
- MX6SL_PAD_KEY_ROW1 = 100,
- MX6SL_PAD_KEY_ROW2 = 101,
- MX6SL_PAD_KEY_ROW3 = 102,
- MX6SL_PAD_KEY_ROW4 = 103,
- MX6SL_PAD_KEY_ROW5 = 104,
- MX6SL_PAD_KEY_ROW6 = 105,
- MX6SL_PAD_KEY_ROW7 = 106,
- MX6SL_PAD_LCD_CLK = 107,
- MX6SL_PAD_LCD_DAT0 = 108,
- MX6SL_PAD_LCD_DAT1 = 109,
- MX6SL_PAD_LCD_DAT10 = 110,
- MX6SL_PAD_LCD_DAT11 = 111,
- MX6SL_PAD_LCD_DAT12 = 112,
- MX6SL_PAD_LCD_DAT13 = 113,
- MX6SL_PAD_LCD_DAT14 = 114,
- MX6SL_PAD_LCD_DAT15 = 115,
- MX6SL_PAD_LCD_DAT16 = 116,
- MX6SL_PAD_LCD_DAT17 = 117,
- MX6SL_PAD_LCD_DAT18 = 118,
- MX6SL_PAD_LCD_DAT19 = 119,
- MX6SL_PAD_LCD_DAT2 = 120,
- MX6SL_PAD_LCD_DAT20 = 121,
- MX6SL_PAD_LCD_DAT21 = 122,
- MX6SL_PAD_LCD_DAT22 = 123,
- MX6SL_PAD_LCD_DAT23 = 124,
- MX6SL_PAD_LCD_DAT3 = 125,
- MX6SL_PAD_LCD_DAT4 = 126,
- MX6SL_PAD_LCD_DAT5 = 127,
- MX6SL_PAD_LCD_DAT6 = 128,
- MX6SL_PAD_LCD_DAT7 = 129,
- MX6SL_PAD_LCD_DAT8 = 130,
- MX6SL_PAD_LCD_DAT9 = 131,
- MX6SL_PAD_LCD_ENABLE = 132,
- MX6SL_PAD_LCD_HSYNC = 133,
- MX6SL_PAD_LCD_RESET = 134,
- MX6SL_PAD_LCD_VSYNC = 135,
- MX6SL_PAD_PWM1 = 136,
- MX6SL_PAD_REF_CLK_24M = 137,
- MX6SL_PAD_REF_CLK_32K = 138,
- MX6SL_PAD_SD1_CLK = 139,
- MX6SL_PAD_SD1_CMD = 140,
- MX6SL_PAD_SD1_DAT0 = 141,
- MX6SL_PAD_SD1_DAT1 = 142,
- MX6SL_PAD_SD1_DAT2 = 143,
- MX6SL_PAD_SD1_DAT3 = 144,
- MX6SL_PAD_SD1_DAT4 = 145,
- MX6SL_PAD_SD1_DAT5 = 146,
- MX6SL_PAD_SD1_DAT6 = 147,
- MX6SL_PAD_SD1_DAT7 = 148,
- MX6SL_PAD_SD2_CLK = 149,
- MX6SL_PAD_SD2_CMD = 150,
- MX6SL_PAD_SD2_DAT0 = 151,
- MX6SL_PAD_SD2_DAT1 = 152,
- MX6SL_PAD_SD2_DAT2 = 153,
- MX6SL_PAD_SD2_DAT3 = 154,
- MX6SL_PAD_SD2_DAT4 = 155,
- MX6SL_PAD_SD2_DAT5 = 156,
- MX6SL_PAD_SD2_DAT6 = 157,
- MX6SL_PAD_SD2_DAT7 = 158,
- MX6SL_PAD_SD2_RST = 159,
- MX6SL_PAD_SD3_CLK = 160,
- MX6SL_PAD_SD3_CMD = 161,
- MX6SL_PAD_SD3_DAT0 = 162,
- MX6SL_PAD_SD3_DAT1 = 163,
- MX6SL_PAD_SD3_DAT2 = 164,
- MX6SL_PAD_SD3_DAT3 = 165,
- MX6SL_PAD_UART1_RXD = 166,
- MX6SL_PAD_UART1_TXD = 167,
- MX6SL_PAD_WDOG_B = 168,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE0),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE1),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE2),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE3),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE4),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE5),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE6),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE7),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE8),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE9),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE10),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE11),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE12),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE13),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE14),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE15),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE16),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE17),
- IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE18),
- IMX_PINCTRL_PIN(MX6SL_PAD_AUD_MCLK),
- IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXC),
- IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXD),
- IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXFS),
- IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXC),
- IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXD),
- IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXFS),
- IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MISO),
- IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MOSI),
- IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SCLK),
- IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SS0),
- IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MISO),
- IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MOSI),
- IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SCLK),
- IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SS0),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR0),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR1),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D0),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D1),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D10),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D11),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D12),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D13),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D14),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D15),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D2),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D3),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D4),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D5),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D6),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D7),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D8),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D9),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDCLK),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDOE),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDRL),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDSP),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCOM),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL0),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL1),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL2),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL3),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRINT),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRSTAT),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRWAKEUP),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE0),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE1),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE2),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE3),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCLK),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDLE),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDOE),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDSHR),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM0),
- IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM1),
- IMX_PINCTRL_PIN(MX6SL_PAD_FEC_CRS_DV),
- IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDC),
- IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDIO),
- IMX_PINCTRL_PIN(MX6SL_PAD_FEC_REF_CLK),
- IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RX_ER),
- IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD0),
- IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD1),
- IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_CLK),
- IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_EN),
- IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD0),
- IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD1),
- IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_DAT),
- IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_STROBE),
- IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SCL),
- IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SDA),
- IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SCL),
- IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SDA),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL0),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL1),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL2),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL3),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL4),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL5),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL6),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL7),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW0),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW1),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW2),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW3),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW4),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW5),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW6),
- IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW7),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_CLK),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT0),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT1),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT10),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT11),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT12),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT13),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT14),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT15),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT16),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT17),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT18),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT19),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT2),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT20),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT21),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT22),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT23),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT3),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT4),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT5),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT6),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT7),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT8),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT9),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_ENABLE),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_HSYNC),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_RESET),
- IMX_PINCTRL_PIN(MX6SL_PAD_LCD_VSYNC),
- IMX_PINCTRL_PIN(MX6SL_PAD_PWM1),
- IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_24M),
- IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_32K),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CLK),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CMD),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT0),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT1),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT2),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT3),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT4),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT5),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT6),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT7),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CLK),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CMD),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT0),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT1),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT2),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT3),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT4),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT5),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT6),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT7),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD2_RST),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CLK),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CMD),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT0),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT1),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT2),
- IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT3),
- IMX_PINCTRL_PIN(MX6SL_PAD_UART1_RXD),
- IMX_PINCTRL_PIN(MX6SL_PAD_UART1_TXD),
- IMX_PINCTRL_PIN(MX6SL_PAD_WDOG_B),
-};
-
-static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
- .pins = imx6sl_pinctrl_pads,
- .npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
-};
-
-static struct of_device_id imx6sl_pinctrl_of_match[] = {
- { .compatible = "fsl,imx6sl-iomuxc", },
- { /* sentinel */ }
-};
-
-static int imx6sl_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &imx6sl_pinctrl_info);
-}
-
-static struct platform_driver imx6sl_pinctrl_driver = {
- .driver = {
- .name = "imx6sl-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = imx6sl_pinctrl_of_match,
- },
- .probe = imx6sl_pinctrl_probe,
- .remove = imx_pinctrl_remove,
-};
-
-static int __init imx6sl_pinctrl_init(void)
-{
- return platform_driver_register(&imx6sl_pinctrl_driver);
-}
-arch_initcall(imx6sl_pinctrl_init);
-
-static void __exit imx6sl_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx6sl_pinctrl_driver);
-}
-module_exit(imx6sl_pinctrl_exit);
-
-MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
-MODULE_DESCRIPTION("Freescale imx6sl pinctrl driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#include "pinctrl-imx.h"
-
-enum imx6sx_pads {
- MX6Sx_PAD_RESERVE0 = 0,
- MX6Sx_PAD_RESERVE1 = 1,
- MX6Sx_PAD_RESERVE2 = 2,
- MX6Sx_PAD_RESERVE3 = 3,
- MX6Sx_PAD_RESERVE4 = 4,
- MX6SX_PAD_GPIO1_IO00 = 5,
- MX6SX_PAD_GPIO1_IO01 = 6,
- MX6SX_PAD_GPIO1_IO02 = 7,
- MX6SX_PAD_GPIO1_IO03 = 8,
- MX6SX_PAD_GPIO1_IO04 = 9,
- MX6SX_PAD_GPIO1_IO05 = 10,
- MX6SX_PAD_GPIO1_IO06 = 11,
- MX6SX_PAD_GPIO1_IO07 = 12,
- MX6SX_PAD_GPIO1_IO08 = 13,
- MX6SX_PAD_GPIO1_IO09 = 14,
- MX6SX_PAD_GPIO1_IO10 = 15,
- MX6SX_PAD_GPIO1_IO11 = 16,
- MX6SX_PAD_GPIO1_IO12 = 17,
- MX6SX_PAD_GPIO1_IO13 = 18,
- MX6SX_PAD_CSI_DATA00 = 19,
- MX6SX_PAD_CSI_DATA01 = 20,
- MX6SX_PAD_CSI_DATA02 = 21,
- MX6SX_PAD_CSI_DATA03 = 22,
- MX6SX_PAD_CSI_DATA04 = 23,
- MX6SX_PAD_CSI_DATA05 = 24,
- MX6SX_PAD_CSI_DATA06 = 25,
- MX6SX_PAD_CSI_DATA07 = 26,
- MX6SX_PAD_CSI_HSYNC = 27,
- MX6SX_PAD_CSI_MCLK = 28,
- MX6SX_PAD_CSI_PIXCLK = 29,
- MX6SX_PAD_CSI_VSYNC = 30,
- MX6SX_PAD_ENET1_COL = 31,
- MX6SX_PAD_ENET1_CRS = 32,
- MX6SX_PAD_ENET1_MDC = 33,
- MX6SX_PAD_ENET1_MDIO = 34,
- MX6SX_PAD_ENET1_RX_CLK = 35,
- MX6SX_PAD_ENET1_TX_CLK = 36,
- MX6SX_PAD_ENET2_COL = 37,
- MX6SX_PAD_ENET2_CRS = 38,
- MX6SX_PAD_ENET2_RX_CLK = 39,
- MX6SX_PAD_ENET2_TX_CLK = 40,
- MX6SX_PAD_KEY_COL0 = 41,
- MX6SX_PAD_KEY_COL1 = 42,
- MX6SX_PAD_KEY_COL2 = 43,
- MX6SX_PAD_KEY_COL3 = 44,
- MX6SX_PAD_KEY_COL4 = 45,
- MX6SX_PAD_KEY_ROW0 = 46,
- MX6SX_PAD_KEY_ROW1 = 47,
- MX6SX_PAD_KEY_ROW2 = 48,
- MX6SX_PAD_KEY_ROW3 = 49,
- MX6SX_PAD_KEY_ROW4 = 50,
- MX6SX_PAD_LCD1_CLK = 51,
- MX6SX_PAD_LCD1_DATA00 = 52,
- MX6SX_PAD_LCD1_DATA01 = 53,
- MX6SX_PAD_LCD1_DATA02 = 54,
- MX6SX_PAD_LCD1_DATA03 = 55,
- MX6SX_PAD_LCD1_DATA04 = 56,
- MX6SX_PAD_LCD1_DATA05 = 57,
- MX6SX_PAD_LCD1_DATA06 = 58,
- MX6SX_PAD_LCD1_DATA07 = 59,
- MX6SX_PAD_LCD1_DATA08 = 60,
- MX6SX_PAD_LCD1_DATA09 = 61,
- MX6SX_PAD_LCD1_DATA10 = 62,
- MX6SX_PAD_LCD1_DATA11 = 63,
- MX6SX_PAD_LCD1_DATA12 = 64,
- MX6SX_PAD_LCD1_DATA13 = 65,
- MX6SX_PAD_LCD1_DATA14 = 66,
- MX6SX_PAD_LCD1_DATA15 = 67,
- MX6SX_PAD_LCD1_DATA16 = 68,
- MX6SX_PAD_LCD1_DATA17 = 69,
- MX6SX_PAD_LCD1_DATA18 = 70,
- MX6SX_PAD_LCD1_DATA19 = 71,
- MX6SX_PAD_LCD1_DATA20 = 72,
- MX6SX_PAD_LCD1_DATA21 = 73,
- MX6SX_PAD_LCD1_DATA22 = 74,
- MX6SX_PAD_LCD1_DATA23 = 75,
- MX6SX_PAD_LCD1_ENABLE = 76,
- MX6SX_PAD_LCD1_HSYNC = 77,
- MX6SX_PAD_LCD1_RESET = 78,
- MX6SX_PAD_LCD1_VSYNC = 79,
- MX6SX_PAD_NAND_ALE = 80,
- MX6SX_PAD_NAND_CE0_B = 81,
- MX6SX_PAD_NAND_CE1_B = 82,
- MX6SX_PAD_NAND_CLE = 83,
- MX6SX_PAD_NAND_DATA00 = 84 ,
- MX6SX_PAD_NAND_DATA01 = 85,
- MX6SX_PAD_NAND_DATA02 = 86,
- MX6SX_PAD_NAND_DATA03 = 87,
- MX6SX_PAD_NAND_DATA04 = 88,
- MX6SX_PAD_NAND_DATA05 = 89,
- MX6SX_PAD_NAND_DATA06 = 90,
- MX6SX_PAD_NAND_DATA07 = 91,
- MX6SX_PAD_NAND_RE_B = 92,
- MX6SX_PAD_NAND_READY_B = 93,
- MX6SX_PAD_NAND_WE_B = 94,
- MX6SX_PAD_NAND_WP_B = 95,
- MX6SX_PAD_QSPI1A_DATA0 = 96,
- MX6SX_PAD_QSPI1A_DATA1 = 97,
- MX6SX_PAD_QSPI1A_DATA2 = 98,
- MX6SX_PAD_QSPI1A_DATA3 = 99,
- MX6SX_PAD_QSPI1A_DQS = 100,
- MX6SX_PAD_QSPI1A_SCLK = 101,
- MX6SX_PAD_QSPI1A_SS0_B = 102,
- MX6SX_PAD_QSPI1A_SS1_B = 103,
- MX6SX_PAD_QSPI1B_DATA0 = 104,
- MX6SX_PAD_QSPI1B_DATA1 = 105,
- MX6SX_PAD_QSPI1B_DATA2 = 106,
- MX6SX_PAD_QSPI1B_DATA3 = 107,
- MX6SX_PAD_QSPI1B_DQS = 108,
- MX6SX_PAD_QSPI1B_SCLK = 109,
- MX6SX_PAD_QSPI1B_SS0_B = 110,
- MX6SX_PAD_QSPI1B_SS1_B = 111,
- MX6SX_PAD_RGMII1_RD0 = 112,
- MX6SX_PAD_RGMII1_RD1 = 113,
- MX6SX_PAD_RGMII1_RD2 = 114,
- MX6SX_PAD_RGMII1_RD3 = 115,
- MX6SX_PAD_RGMII1_RX_CTL = 116,
- MX6SX_PAD_RGMII1_RXC = 117,
- MX6SX_PAD_RGMII1_TD0 = 118,
- MX6SX_PAD_RGMII1_TD1 = 119,
- MX6SX_PAD_RGMII1_TD2 = 120,
- MX6SX_PAD_RGMII1_TD3 = 121,
- MX6SX_PAD_RGMII1_TX_CTL = 122,
- MX6SX_PAD_RGMII1_TXC = 123,
- MX6SX_PAD_RGMII2_RD0 = 124,
- MX6SX_PAD_RGMII2_RD1 = 125,
- MX6SX_PAD_RGMII2_RD2 = 126,
- MX6SX_PAD_RGMII2_RD3 = 127,
- MX6SX_PAD_RGMII2_RX_CTL = 128,
- MX6SX_PAD_RGMII2_RXC = 129,
- MX6SX_PAD_RGMII2_TD0 = 130,
- MX6SX_PAD_RGMII2_TD1 = 131,
- MX6SX_PAD_RGMII2_TD2 = 132,
- MX6SX_PAD_RGMII2_TD3 = 133,
- MX6SX_PAD_RGMII2_TX_CTL = 134,
- MX6SX_PAD_RGMII2_TXC = 135,
- MX6SX_PAD_SD1_CLK = 136,
- MX6SX_PAD_SD1_CMD = 137,
- MX6SX_PAD_SD1_DATA0 = 138,
- MX6SX_PAD_SD1_DATA1 = 139,
- MX6SX_PAD_SD1_DATA2 = 140,
- MX6SX_PAD_SD1_DATA3 = 141,
- MX6SX_PAD_SD2_CLK = 142,
- MX6SX_PAD_SD2_CMD = 143,
- MX6SX_PAD_SD2_DATA0 = 144,
- MX6SX_PAD_SD2_DATA1 = 145,
- MX6SX_PAD_SD2_DATA2 = 146,
- MX6SX_PAD_SD2_DATA3 = 147,
- MX6SX_PAD_SD3_CLK = 148,
- MX6SX_PAD_SD3_CMD = 149,
- MX6SX_PAD_SD3_DATA0 = 150,
- MX6SX_PAD_SD3_DATA1 = 151,
- MX6SX_PAD_SD3_DATA2 = 152,
- MX6SX_PAD_SD3_DATA3 = 153,
- MX6SX_PAD_SD3_DATA4 = 154,
- MX6SX_PAD_SD3_DATA5 = 155,
- MX6SX_PAD_SD3_DATA6 = 156,
- MX6SX_PAD_SD3_DATA7 = 157,
- MX6SX_PAD_SD4_CLK = 158,
- MX6SX_PAD_SD4_CMD = 159,
- MX6SX_PAD_SD4_DATA0 = 160,
- MX6SX_PAD_SD4_DATA1 = 161,
- MX6SX_PAD_SD4_DATA2 = 162,
- MX6SX_PAD_SD4_DATA3 = 163,
- MX6SX_PAD_SD4_DATA4 = 164,
- MX6SX_PAD_SD4_DATA5 = 165,
- MX6SX_PAD_SD4_DATA6 = 166,
- MX6SX_PAD_SD4_DATA7 = 167,
- MX6SX_PAD_SD4_RESET_B = 168,
- MX6SX_PAD_USB_H_DATA = 169,
- MX6SX_PAD_USB_H_STROBE = 170,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE0),
- IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE1),
- IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE2),
- IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE3),
- IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE4),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO00),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO01),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO02),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO03),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO04),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO05),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO06),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO07),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO08),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO09),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO10),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO11),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO12),
- IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO13),
- IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA00),
- IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA01),
- IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA02),
- IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA03),
- IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA04),
- IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA05),
- IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA06),
- IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA07),
- IMX_PINCTRL_PIN(MX6SX_PAD_CSI_HSYNC),
- IMX_PINCTRL_PIN(MX6SX_PAD_CSI_MCLK),
- IMX_PINCTRL_PIN(MX6SX_PAD_CSI_PIXCLK),
- IMX_PINCTRL_PIN(MX6SX_PAD_CSI_VSYNC),
- IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_COL),
- IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_CRS),
- IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDC),
- IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDIO),
- IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_RX_CLK),
- IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_TX_CLK),
- IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_COL),
- IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_CRS),
- IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_RX_CLK),
- IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_TX_CLK),
- IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL0),
- IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL1),
- IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL2),
- IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL3),
- IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL4),
- IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW0),
- IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW1),
- IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW2),
- IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW3),
- IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW4),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_CLK),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA00),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA01),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA02),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA03),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA04),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA05),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA06),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA07),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA08),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA09),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA10),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA11),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA12),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA13),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA14),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA15),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA16),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA17),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA18),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA19),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA20),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA21),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA22),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA23),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_ENABLE),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_HSYNC),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_RESET),
- IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_VSYNC),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_ALE),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE0_B),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE1_B),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CLE),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA00),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA01),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA02),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA03),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA04),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA05),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA06),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA07),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_RE_B),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_READY_B),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WE_B),
- IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WP_B),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA0),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA1),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA2),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA3),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DQS),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SCLK),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS0_B),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS1_B),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA0),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA1),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA2),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA3),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DQS),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SCLK),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS0_B),
- IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS1_B),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD0),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD1),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD2),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD3),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RX_CTL),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RXC),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD0),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD1),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD2),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD3),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TX_CTL),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TXC),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD0),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD1),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD2),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD3),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RX_CTL),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RXC),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD0),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD1),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD2),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD3),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TX_CTL),
- IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TXC),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CLK),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CMD),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA0),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA1),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA2),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA3),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CLK),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CMD),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA0),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA1),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA2),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA3),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CLK),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CMD),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA0),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA1),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA2),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA3),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA4),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA5),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA6),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA7),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CLK),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CMD),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA0),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA1),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA2),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA3),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA4),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA5),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA6),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA7),
- IMX_PINCTRL_PIN(MX6SX_PAD_SD4_RESET_B),
- IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_DATA),
- IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE),
-};
-
-static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
- .pins = imx6sx_pinctrl_pads,
- .npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
-};
-
-static struct of_device_id imx6sx_pinctrl_of_match[] = {
- { .compatible = "fsl,imx6sx-iomuxc", },
- { /* sentinel */ }
-};
-
-static int imx6sx_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &imx6sx_pinctrl_info);
-}
-
-static struct platform_driver imx6sx_pinctrl_driver = {
- .driver = {
- .name = "imx6sx-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = of_match_ptr(imx6sx_pinctrl_of_match),
- },
- .probe = imx6sx_pinctrl_probe,
- .remove = imx_pinctrl_remove,
-};
-
-static int __init imx6sx_pinctrl_init(void)
-{
- return platform_driver_register(&imx6sx_pinctrl_driver);
-}
-arch_initcall(imx6sx_pinctrl_init);
-
-static void __exit imx6sx_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx6sx_pinctrl_driver);
-}
-module_exit(imx6sx_pinctrl_exit);
-
-MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>");
-MODULE_DESCRIPTION("Freescale imx6sx pinctrl driver");
-MODULE_LICENSE("GPL v2");
return ret;
}
-static int ltq_pmx_enable(struct pinctrl_dev *pctrldev,
- unsigned func,
- unsigned group)
+static int ltq_pmx_set(struct pinctrl_dev *pctrldev,
+ unsigned func,
+ unsigned group)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
const struct ltq_pin_group *pin_grp = &info->grps[group];
.get_functions_count = ltq_pmx_func_count,
.get_function_name = ltq_pmx_func_name,
.get_function_groups = ltq_pmx_get_groups,
- .enable = ltq_pmx_enable,
+ .set_mux = ltq_pmx_set,
.gpio_request_enable = ltq_pmx_gpio_request_enable,
};
+++ /dev/null
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include "core.h"
-#include "pinctrl-mxs.h"
-
-#define SUFFIX_LEN 4
-
-struct mxs_pinctrl_data {
- struct device *dev;
- struct pinctrl_dev *pctl;
- void __iomem *base;
- struct mxs_pinctrl_soc_data *soc;
-};
-
-static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
-{
- struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
-
- return d->soc->ngroups;
-}
-
-static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
- unsigned group)
-{
- struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
-
- return d->soc->groups[group].name;
-}
-
-static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
- const unsigned **pins, unsigned *num_pins)
-{
- struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
-
- *pins = d->soc->groups[group].pins;
- *num_pins = d->soc->groups[group].npins;
-
- return 0;
-}
-
-static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
- unsigned offset)
-{
- seq_printf(s, " %s", dev_name(pctldev->dev));
-}
-
-static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np,
- struct pinctrl_map **map, unsigned *num_maps)
-{
- struct pinctrl_map *new_map;
- char *group = NULL;
- unsigned new_num = 1;
- unsigned long config = 0;
- unsigned long *pconfig;
- int length = strlen(np->name) + SUFFIX_LEN;
- bool purecfg = false;
- u32 val, reg;
- int ret, i = 0;
-
- /* Check for pin config node which has no 'reg' property */
- if (of_property_read_u32(np, "reg", ®))
- purecfg = true;
-
- ret = of_property_read_u32(np, "fsl,drive-strength", &val);
- if (!ret)
- config = val | MA_PRESENT;
- ret = of_property_read_u32(np, "fsl,voltage", &val);
- if (!ret)
- config |= val << VOL_SHIFT | VOL_PRESENT;
- ret = of_property_read_u32(np, "fsl,pull-up", &val);
- if (!ret)
- config |= val << PULL_SHIFT | PULL_PRESENT;
-
- /* Check for group node which has both mux and config settings */
- if (!purecfg && config)
- new_num = 2;
-
- new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
- if (!new_map)
- return -ENOMEM;
-
- if (!purecfg) {
- new_map[i].type = PIN_MAP_TYPE_MUX_GROUP;
- new_map[i].data.mux.function = np->name;
-
- /* Compose group name */
- group = kzalloc(length, GFP_KERNEL);
- if (!group) {
- ret = -ENOMEM;
- goto free;
- }
- snprintf(group, length, "%s.%d", np->name, reg);
- new_map[i].data.mux.group = group;
- i++;
- }
-
- if (config) {
- pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
- if (!pconfig) {
- ret = -ENOMEM;
- goto free_group;
- }
-
- new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
- new_map[i].data.configs.group_or_pin = purecfg ? np->name :
- group;
- new_map[i].data.configs.configs = pconfig;
- new_map[i].data.configs.num_configs = 1;
- }
-
- *map = new_map;
- *num_maps = new_num;
-
- return 0;
-
-free_group:
- if (!purecfg)
- kfree(group);
-free:
- kfree(new_map);
- return ret;
-}
-
-static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
- struct pinctrl_map *map, unsigned num_maps)
-{
- u32 i;
-
- for (i = 0; i < num_maps; i++) {
- if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
- kfree(map[i].data.mux.group);
- if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
- kfree(map[i].data.configs.configs);
- }
-
- kfree(map);
-}
-
-static const struct pinctrl_ops mxs_pinctrl_ops = {
- .get_groups_count = mxs_get_groups_count,
- .get_group_name = mxs_get_group_name,
- .get_group_pins = mxs_get_group_pins,
- .pin_dbg_show = mxs_pin_dbg_show,
- .dt_node_to_map = mxs_dt_node_to_map,
- .dt_free_map = mxs_dt_free_map,
-};
-
-static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
-{
- struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
-
- return d->soc->nfunctions;
-}
-
-static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
- unsigned function)
-{
- struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
-
- return d->soc->functions[function].name;
-}
-
-static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
- unsigned group,
- const char * const **groups,
- unsigned * const num_groups)
-{
- struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
-
- *groups = d->soc->functions[group].groups;
- *num_groups = d->soc->functions[group].ngroups;
-
- return 0;
-}
-
-static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
- unsigned group)
-{
- struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
- struct mxs_group *g = &d->soc->groups[group];
- void __iomem *reg;
- u8 bank, shift;
- u16 pin;
- u32 i;
-
- for (i = 0; i < g->npins; i++) {
- bank = PINID_TO_BANK(g->pins[i]);
- pin = PINID_TO_PIN(g->pins[i]);
- reg = d->base + d->soc->regs->muxsel;
- reg += bank * 0x20 + pin / 16 * 0x10;
- shift = pin % 16 * 2;
-
- writel(0x3 << shift, reg + CLR);
- writel(g->muxsel[i] << shift, reg + SET);
- }
-
- return 0;
-}
-
-static const struct pinmux_ops mxs_pinmux_ops = {
- .get_functions_count = mxs_pinctrl_get_funcs_count,
- .get_function_name = mxs_pinctrl_get_func_name,
- .get_function_groups = mxs_pinctrl_get_func_groups,
- .enable = mxs_pinctrl_enable,
-};
-
-static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
- unsigned pin, unsigned long *config)
-{
- return -ENOTSUPP;
-}
-
-static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
- unsigned pin, unsigned long *configs,
- unsigned num_configs)
-{
- return -ENOTSUPP;
-}
-
-static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
- unsigned group, unsigned long *config)
-{
- struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
-
- *config = d->soc->groups[group].config;
-
- return 0;
-}
-
-static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
- unsigned group, unsigned long *configs,
- unsigned num_configs)
-{
- struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
- struct mxs_group *g = &d->soc->groups[group];
- void __iomem *reg;
- u8 ma, vol, pull, bank, shift;
- u16 pin;
- u32 i;
- int n;
- unsigned long config;
-
- for (n = 0; n < num_configs; n++) {
- config = configs[n];
-
- ma = CONFIG_TO_MA(config);
- vol = CONFIG_TO_VOL(config);
- pull = CONFIG_TO_PULL(config);
-
- for (i = 0; i < g->npins; i++) {
- bank = PINID_TO_BANK(g->pins[i]);
- pin = PINID_TO_PIN(g->pins[i]);
-
- /* drive */
- reg = d->base + d->soc->regs->drive;
- reg += bank * 0x40 + pin / 8 * 0x10;
-
- /* mA */
- if (config & MA_PRESENT) {
- shift = pin % 8 * 4;
- writel(0x3 << shift, reg + CLR);
- writel(ma << shift, reg + SET);
- }
-
- /* vol */
- if (config & VOL_PRESENT) {
- shift = pin % 8 * 4 + 2;
- if (vol)
- writel(1 << shift, reg + SET);
- else
- writel(1 << shift, reg + CLR);
- }
-
- /* pull */
- if (config & PULL_PRESENT) {
- reg = d->base + d->soc->regs->pull;
- reg += bank * 0x10;
- shift = pin;
- if (pull)
- writel(1 << shift, reg + SET);
- else
- writel(1 << shift, reg + CLR);
- }
- }
-
- /* cache the config value for mxs_pinconf_group_get() */
- g->config = config;
-
- } /* for each config */
-
- return 0;
-}
-
-static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned pin)
-{
- /* Not support */
-}
-
-static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned group)
-{
- unsigned long config;
-
- if (!mxs_pinconf_group_get(pctldev, group, &config))
- seq_printf(s, "0x%lx", config);
-}
-
-static const struct pinconf_ops mxs_pinconf_ops = {
- .pin_config_get = mxs_pinconf_get,
- .pin_config_set = mxs_pinconf_set,
- .pin_config_group_get = mxs_pinconf_group_get,
- .pin_config_group_set = mxs_pinconf_group_set,
- .pin_config_dbg_show = mxs_pinconf_dbg_show,
- .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
-};
-
-static struct pinctrl_desc mxs_pinctrl_desc = {
- .pctlops = &mxs_pinctrl_ops,
- .pmxops = &mxs_pinmux_ops,
- .confops = &mxs_pinconf_ops,
- .owner = THIS_MODULE,
-};
-
-static int mxs_pinctrl_parse_group(struct platform_device *pdev,
- struct device_node *np, int idx,
- const char **out_name)
-{
- struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
- struct mxs_group *g = &d->soc->groups[idx];
- struct property *prop;
- const char *propname = "fsl,pinmux-ids";
- char *group;
- int length = strlen(np->name) + SUFFIX_LEN;
- u32 val, i;
-
- group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
- if (!group)
- return -ENOMEM;
- if (of_property_read_u32(np, "reg", &val))
- snprintf(group, length, "%s", np->name);
- else
- snprintf(group, length, "%s.%d", np->name, val);
- g->name = group;
-
- prop = of_find_property(np, propname, &length);
- if (!prop)
- return -EINVAL;
- g->npins = length / sizeof(u32);
-
- g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
- GFP_KERNEL);
- if (!g->pins)
- return -ENOMEM;
-
- g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
- GFP_KERNEL);
- if (!g->muxsel)
- return -ENOMEM;
-
- of_property_read_u32_array(np, propname, g->pins, g->npins);
- for (i = 0; i < g->npins; i++) {
- g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
- g->pins[i] = MUXID_TO_PINID(g->pins[i]);
- }
-
- if (out_name)
- *out_name = g->name;
-
- return 0;
-}
-
-static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
- struct mxs_pinctrl_data *d)
-{
- struct mxs_pinctrl_soc_data *soc = d->soc;
- struct device_node *np = pdev->dev.of_node;
- struct device_node *child;
- struct mxs_function *f;
- const char *gpio_compat = "fsl,mxs-gpio";
- const char *fn, *fnull = "";
- int i = 0, idxf = 0, idxg = 0;
- int ret;
- u32 val;
-
- child = of_get_next_child(np, NULL);
- if (!child) {
- dev_err(&pdev->dev, "no group is defined\n");
- return -ENOENT;
- }
-
- /* Count total functions and groups */
- fn = fnull;
- for_each_child_of_node(np, child) {
- if (of_device_is_compatible(child, gpio_compat))
- continue;
- soc->ngroups++;
- /* Skip pure pinconf node */
- if (of_property_read_u32(child, "reg", &val))
- continue;
- if (strcmp(fn, child->name)) {
- fn = child->name;
- soc->nfunctions++;
- }
- }
-
- soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
- sizeof(*soc->functions), GFP_KERNEL);
- if (!soc->functions)
- return -ENOMEM;
-
- soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
- sizeof(*soc->groups), GFP_KERNEL);
- if (!soc->groups)
- return -ENOMEM;
-
- /* Count groups for each function */
- fn = fnull;
- f = &soc->functions[idxf];
- for_each_child_of_node(np, child) {
- if (of_device_is_compatible(child, gpio_compat))
- continue;
- if (of_property_read_u32(child, "reg", &val))
- continue;
- if (strcmp(fn, child->name)) {
- f = &soc->functions[idxf++];
- f->name = fn = child->name;
- }
- f->ngroups++;
- };
-
- /* Get groups for each function */
- idxf = 0;
- fn = fnull;
- for_each_child_of_node(np, child) {
- if (of_device_is_compatible(child, gpio_compat))
- continue;
- if (of_property_read_u32(child, "reg", &val)) {
- ret = mxs_pinctrl_parse_group(pdev, child,
- idxg++, NULL);
- if (ret)
- return ret;
- continue;
- }
-
- if (strcmp(fn, child->name)) {
- f = &soc->functions[idxf++];
- f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
- sizeof(*f->groups),
- GFP_KERNEL);
- if (!f->groups)
- return -ENOMEM;
- fn = child->name;
- i = 0;
- }
- ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
- &f->groups[i++]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-int mxs_pinctrl_probe(struct platform_device *pdev,
- struct mxs_pinctrl_soc_data *soc)
-{
- struct device_node *np = pdev->dev.of_node;
- struct mxs_pinctrl_data *d;
- int ret;
-
- d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
- if (!d)
- return -ENOMEM;
-
- d->dev = &pdev->dev;
- d->soc = soc;
-
- d->base = of_iomap(np, 0);
- if (!d->base)
- return -EADDRNOTAVAIL;
-
- mxs_pinctrl_desc.pins = d->soc->pins;
- mxs_pinctrl_desc.npins = d->soc->npins;
- mxs_pinctrl_desc.name = dev_name(&pdev->dev);
-
- platform_set_drvdata(pdev, d);
-
- ret = mxs_pinctrl_probe_dt(pdev, d);
- if (ret) {
- dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
- goto err;
- }
-
- d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
- if (!d->pctl) {
- dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
- ret = -EINVAL;
- goto err;
- }
-
- return 0;
-
-err:
- iounmap(d->base);
- return ret;
-}
-EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
-
-int mxs_pinctrl_remove(struct platform_device *pdev)
-{
- struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
-
- pinctrl_unregister(d->pctl);
- iounmap(d->base);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);
+++ /dev/null
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __PINCTRL_MXS_H
-#define __PINCTRL_MXS_H
-
-#include <linux/platform_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#define SET 0x4
-#define CLR 0x8
-#define TOG 0xc
-
-#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
-#define PINID(bank, pin) ((bank) * 32 + (pin))
-
-/*
- * pinmux-id bit field definitions
- *
- * bank: 15..12 (4)
- * pin: 11..4 (8)
- * muxsel: 3..0 (4)
- */
-#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
-#define MUXID_TO_MUXSEL(m) ((m) & 0xf)
-
-#define PINID_TO_BANK(p) ((p) >> 5)
-#define PINID_TO_PIN(p) ((p) % 32)
-
-/*
- * pin config bit field definitions
- *
- * pull-up: 6..5 (2)
- * voltage: 4..3 (2)
- * mA: 2..0 (3)
- *
- * MSB of each field is presence bit for the config.
- */
-#define PULL_PRESENT (1 << 6)
-#define PULL_SHIFT 5
-#define VOL_PRESENT (1 << 4)
-#define VOL_SHIFT 3
-#define MA_PRESENT (1 << 2)
-#define MA_SHIFT 0
-#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
-#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
-#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
-
-struct mxs_function {
- const char *name;
- const char **groups;
- unsigned ngroups;
-};
-
-struct mxs_group {
- const char *name;
- unsigned int *pins;
- unsigned npins;
- u8 *muxsel;
- u8 config;
-};
-
-struct mxs_regs {
- u16 muxsel;
- u16 drive;
- u16 pull;
-};
-
-struct mxs_pinctrl_soc_data {
- const struct mxs_regs *regs;
- const struct pinctrl_pin_desc *pins;
- unsigned npins;
- struct mxs_function *functions;
- unsigned nfunctions;
- struct mxs_group *groups;
- unsigned ngroups;
-};
-
-int mxs_pinctrl_probe(struct platform_device *pdev,
- struct mxs_pinctrl_soc_data *soc);
-int mxs_pinctrl_remove(struct platform_device *pdev);
-
-#endif /* __PINCTRL_MXS_H */
return 0;
}
-static int palmas_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
+static int palmas_pinctrl_set_mux(struct pinctrl_dev *pctldev,
+ unsigned function,
unsigned group)
{
struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
.get_functions_count = palmas_pinctrl_get_funcs_count,
.get_function_name = palmas_pinctrl_get_func_name,
.get_function_groups = palmas_pinctrl_get_func_groups,
- .enable = palmas_pinctrl_enable,
+ .set_mux = palmas_pinctrl_set_mux,
};
static int palmas_pinconf_get(struct pinctrl_dev *pctldev,
return 0;
}
-static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
- unsigned group)
+static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
const unsigned int *pins = info->groups[group].pins;
.get_functions_count = rockchip_pmx_get_funcs_count,
.get_function_name = rockchip_pmx_get_func_name,
.get_function_groups = rockchip_pmx_get_groups,
- .enable = rockchip_pmx_enable,
+ .set_mux = rockchip_pmx_set,
.gpio_set_direction = rockchip_pmx_gpio_set_direction,
};
return 0;
}
-static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
+static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
unsigned group)
{
struct pcs_device *pcs;
.get_functions_count = pcs_get_functions_count,
.get_function_name = pcs_get_function_name,
.get_function_groups = pcs_get_function_groups,
- .enable = pcs_enable,
+ .set_mux = pcs_set_mux,
.gpio_request_enable = pcs_request_gpio,
};
.irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
};
+static const struct pcs_soc_data pinctrl_single_dra7 = {
+ .flags = PCS_QUIRK_SHARED_IRQ,
+ .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
+ .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
+};
+
+static const struct pcs_soc_data pinctrl_single_am437x = {
+ .flags = PCS_QUIRK_SHARED_IRQ,
+ .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
+ .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
+};
+
static const struct pcs_soc_data pinctrl_single = {
};
{ .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
{ .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
{ .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
+ { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
+ { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
{ .compatible = "pinctrl-single", .data = &pinctrl_single },
{ .compatible = "pinconf-single", .data = &pinconf_single },
{ },
return &bank->pc;
}
-static int st_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector,
- unsigned group)
+static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
+ unsigned group)
{
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct st_pinconf *conf = info->groups[group].pin_conf;
.get_functions_count = st_pmx_get_funcs_count,
.get_function_name = st_pmx_get_fname,
.get_function_groups = st_pmx_get_groups,
- .enable = st_pmx_enable,
+ .set_mux = st_pmx_set_mux,
.gpio_set_direction = st_pmx_set_gpio_direction,
};
0, handle_simple_irq,
IRQ_TYPE_LEVEL_LOW);
if (err) {
+ gpiochip_remove(&bank->gpio_chip);
dev_info(dev, "could not add irqchip\n");
return err;
}
mutex_unlock(&state->mutex);
}
-static int tb10x_pctl_enable(struct pinctrl_dev *pctl,
+static int tb10x_pctl_set_mux(struct pinctrl_dev *pctl,
unsigned func_selector, unsigned group_selector)
{
struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
.get_function_groups = tb10x_get_function_groups,
.gpio_request_enable = tb10x_gpio_request_enable,
.gpio_disable_free = tb10x_gpio_disable_free,
- .enable = tb10x_pctl_enable,
+ .set_mux = tb10x_pctl_set_mux,
};
static struct pinctrl_desc tb10x_pindesc = {
return 0;
}
-static int tegra_xusb_padctl_pinmux_enable(struct pinctrl_dev *pinctrl,
- unsigned int function,
- unsigned int group)
+static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
+ unsigned int function,
+ unsigned int group)
{
struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
const struct tegra_xusb_padctl_lane *lane;
.get_functions_count = tegra_xusb_padctl_get_functions_count,
.get_function_name = tegra_xusb_padctl_get_function_name,
.get_function_groups = tegra_xusb_padctl_get_function_groups,
- .enable = tegra_xusb_padctl_pinmux_enable,
+ .set_mux = tegra_xusb_padctl_pinmux_set,
};
static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
return 0;
}
-static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
- unsigned group)
+static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
+ unsigned function,
+ unsigned group)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tegra_pingroup *g;
.get_functions_count = tegra_pinctrl_get_funcs_count,
.get_function_name = tegra_pinctrl_get_func_name,
.get_function_groups = tegra_pinctrl_get_func_groups,
- .enable = tegra_pinctrl_enable,
+ .set_mux = tegra_pinctrl_set_mux,
};
static int tegra_pinconf_reg(struct tegra_pmx *pmx,
return tegra_pinctrl_probe(pdev, &tegra114_pinctrl);
}
-static struct of_device_id tegra114_pinctrl_of_match[] = {
+static const struct of_device_id tegra114_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra114-pinmux", },
{ },
};
#define TEGRA_PIN_OWR _PIN(5)
#define TEGRA_PIN_CLK_32K_IN _PIN(6)
#define TEGRA_PIN_JTAG_RTCK _PIN(7)
+#define TEGRA_PIN_DSI_B_CLK_P _PIN(8)
+#define TEGRA_PIN_DSI_B_CLK_N _PIN(9)
+#define TEGRA_PIN_DSI_B_D0_P _PIN(10)
+#define TEGRA_PIN_DSI_B_D0_N _PIN(11)
+#define TEGRA_PIN_DSI_B_D1_P _PIN(12)
+#define TEGRA_PIN_DSI_B_D1_N _PIN(13)
+#define TEGRA_PIN_DSI_B_D2_P _PIN(14)
+#define TEGRA_PIN_DSI_B_D2_N _PIN(15)
+#define TEGRA_PIN_DSI_B_D3_P _PIN(16)
+#define TEGRA_PIN_DSI_B_D3_N _PIN(17)
static const struct pinctrl_pin_desc tegra124_pins[] = {
PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"),
+ PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"),
};
static const unsigned clk_32k_out_pa0_pins[] = {
TEGRA_PIN_JTAG_RTCK,
};
+static const unsigned mipi_pad_ctrl_dsi_b_pins[] = {
+ TEGRA_PIN_DSI_B_CLK_P,
+ TEGRA_PIN_DSI_B_CLK_N,
+ TEGRA_PIN_DSI_B_D0_P,
+ TEGRA_PIN_DSI_B_D0_N,
+ TEGRA_PIN_DSI_B_D1_P,
+ TEGRA_PIN_DSI_B_D1_N,
+ TEGRA_PIN_DSI_B_D2_P,
+ TEGRA_PIN_DSI_B_D2_N,
+ TEGRA_PIN_DSI_B_D3_P,
+ TEGRA_PIN_DSI_B_D3_N,
+};
+
enum tegra_mux {
TEGRA_MUX_BLINK,
TEGRA_MUX_CCLA,
TEGRA_MUX_VI_ALT3,
TEGRA_MUX_VIMCLK2,
TEGRA_MUX_VIMCLK2_ALT,
+ TEGRA_MUX_CSI,
+ TEGRA_MUX_DSI_B,
};
#define FUNCTION(fname) \
FUNCTION(vi_alt3),
FUNCTION(vimclk2),
FUNCTION(vimclk2_alt),
+ FUNCTION(csi),
+ FUNCTION(dsi_b),
};
#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
#define PINGROUP_REG_A 0x3000 /* bank 1 */
+#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
.drvtype_bit = PINGROUP_BIT_##drvtype(6), \
}
+#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
+
+#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \
+ { \
+ .name = "mipi_pad_ctrl_" #pg_name, \
+ .pins = mipi_pad_ctrl_##pg_name##_pins, \
+ .npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins), \
+ .funcs = { \
+ TEGRA_MUX_ ## f0, \
+ TEGRA_MUX_ ## f1, \
+ TEGRA_MUX_RSVD3, \
+ TEGRA_MUX_RSVD4, \
+ }, \
+ .mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r), \
+ .mux_bank = 2, \
+ .mux_bit = b, \
+ .pupd_reg = -1, \
+ .tri_reg = -1, \
+ .einput_bit = -1, \
+ .odrain_bit = -1, \
+ .lock_bit = -1, \
+ .ioreset_bit = -1, \
+ .rcv_sel_bit = -1, \
+ .drv_reg = -1, \
+ }
+
static const struct tegra_pingroup tegra124_groups[] = {
/* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
+
+ /* pg_name, r b f0, f1 */
+ MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B)
};
static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
}
-static struct of_device_id tegra124_pinctrl_of_match[] = {
+static const struct of_device_id tegra124_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra124-pinmux", },
{ },
};
return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
}
-static struct of_device_id tegra20_pinctrl_of_match[] = {
+static const struct of_device_id tegra20_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra20-pinmux", },
{ },
};
return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
}
-static struct of_device_id tegra30_pinctrl_of_match[] = {
+static const struct of_device_id tegra30_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra30-pinmux", },
{ },
};
__global_unlock2(flags);
}
-static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev,
- unsigned int function, unsigned int group)
+static int tz1090_pdc_pinctrl_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ unsigned int group)
{
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
.get_functions_count = tz1090_pdc_pinctrl_get_funcs_count,
.get_function_name = tz1090_pdc_pinctrl_get_func_name,
.get_function_groups = tz1090_pdc_pinctrl_get_func_groups,
- .enable = tz1090_pdc_pinctrl_enable,
+ .set_mux = tz1090_pdc_pinctrl_set_mux,
.gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable,
.gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free,
};
* the effect is the same as enabling the function on each individual pin in the
* group.
*/
-static int tz1090_pinctrl_enable(struct pinctrl_dev *pctldev,
- unsigned int function, unsigned int group)
+static int tz1090_pinctrl_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int function, unsigned int group)
{
struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
struct tz1090_pingroup *grp;
.get_functions_count = tz1090_pinctrl_get_funcs_count,
.get_function_name = tz1090_pinctrl_get_func_name,
.get_function_groups = tz1090_pinctrl_get_func_groups,
- .enable = tz1090_pinctrl_enable,
+ .set_mux = tz1090_pinctrl_set_mux,
.gpio_request_enable = tz1090_pinctrl_gpio_request_enable,
.gpio_disable_free = tz1090_pinctrl_gpio_disable_free,
};
}
}
-static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
- unsigned group)
+static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
{
struct u300_pmx *upmx;
.get_functions_count = u300_pmx_get_funcs_count,
.get_function_name = u300_pmx_get_func_name,
.get_function_groups = u300_pmx_get_groups,
- .enable = u300_pmx_enable,
+ .set_mux = u300_pmx_set_mux,
};
static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
+++ /dev/null
-/*
- * VF610 pinctrl driver based on imx pinmux and pinconf core
- *
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-
-#include "pinctrl-imx.h"
-
-enum vf610_pads {
- VF610_PAD_PTA6 = 0,
- VF610_PAD_PTA8 = 1,
- VF610_PAD_PTA9 = 2,
- VF610_PAD_PTA10 = 3,
- VF610_PAD_PTA11 = 4,
- VF610_PAD_PTA12 = 5,
- VF610_PAD_PTA16 = 6,
- VF610_PAD_PTA17 = 7,
- VF610_PAD_PTA18 = 8,
- VF610_PAD_PTA19 = 9,
- VF610_PAD_PTA20 = 10,
- VF610_PAD_PTA21 = 11,
- VF610_PAD_PTA22 = 12,
- VF610_PAD_PTA23 = 13,
- VF610_PAD_PTA24 = 14,
- VF610_PAD_PTA25 = 15,
- VF610_PAD_PTA26 = 16,
- VF610_PAD_PTA27 = 17,
- VF610_PAD_PTA28 = 18,
- VF610_PAD_PTA29 = 19,
- VF610_PAD_PTA30 = 20,
- VF610_PAD_PTA31 = 21,
- VF610_PAD_PTB0 = 22,
- VF610_PAD_PTB1 = 23,
- VF610_PAD_PTB2 = 24,
- VF610_PAD_PTB3 = 25,
- VF610_PAD_PTB4 = 26,
- VF610_PAD_PTB5 = 27,
- VF610_PAD_PTB6 = 28,
- VF610_PAD_PTB7 = 29,
- VF610_PAD_PTB8 = 30,
- VF610_PAD_PTB9 = 31,
- VF610_PAD_PTB10 = 32,
- VF610_PAD_PTB11 = 33,
- VF610_PAD_PTB12 = 34,
- VF610_PAD_PTB13 = 35,
- VF610_PAD_PTB14 = 36,
- VF610_PAD_PTB15 = 37,
- VF610_PAD_PTB16 = 38,
- VF610_PAD_PTB17 = 39,
- VF610_PAD_PTB18 = 40,
- VF610_PAD_PTB19 = 41,
- VF610_PAD_PTB20 = 42,
- VF610_PAD_PTB21 = 43,
- VF610_PAD_PTB22 = 44,
- VF610_PAD_PTC0 = 45,
- VF610_PAD_PTC1 = 46,
- VF610_PAD_PTC2 = 47,
- VF610_PAD_PTC3 = 48,
- VF610_PAD_PTC4 = 49,
- VF610_PAD_PTC5 = 50,
- VF610_PAD_PTC6 = 51,
- VF610_PAD_PTC7 = 52,
- VF610_PAD_PTC8 = 53,
- VF610_PAD_PTC9 = 54,
- VF610_PAD_PTC10 = 55,
- VF610_PAD_PTC11 = 56,
- VF610_PAD_PTC12 = 57,
- VF610_PAD_PTC13 = 58,
- VF610_PAD_PTC14 = 59,
- VF610_PAD_PTC15 = 60,
- VF610_PAD_PTC16 = 61,
- VF610_PAD_PTC17 = 62,
- VF610_PAD_PTD31 = 63,
- VF610_PAD_PTD30 = 64,
- VF610_PAD_PTD29 = 65,
- VF610_PAD_PTD28 = 66,
- VF610_PAD_PTD27 = 67,
- VF610_PAD_PTD26 = 68,
- VF610_PAD_PTD25 = 69,
- VF610_PAD_PTD24 = 70,
- VF610_PAD_PTD23 = 71,
- VF610_PAD_PTD22 = 72,
- VF610_PAD_PTD21 = 73,
- VF610_PAD_PTD20 = 74,
- VF610_PAD_PTD19 = 75,
- VF610_PAD_PTD18 = 76,
- VF610_PAD_PTD17 = 77,
- VF610_PAD_PTD16 = 78,
- VF610_PAD_PTD0 = 79,
- VF610_PAD_PTD1 = 80,
- VF610_PAD_PTD2 = 81,
- VF610_PAD_PTD3 = 82,
- VF610_PAD_PTD4 = 83,
- VF610_PAD_PTD5 = 84,
- VF610_PAD_PTD6 = 85,
- VF610_PAD_PTD7 = 86,
- VF610_PAD_PTD8 = 87,
- VF610_PAD_PTD9 = 88,
- VF610_PAD_PTD10 = 89,
- VF610_PAD_PTD11 = 90,
- VF610_PAD_PTD12 = 91,
- VF610_PAD_PTD13 = 92,
- VF610_PAD_PTB23 = 93,
- VF610_PAD_PTB24 = 94,
- VF610_PAD_PTB25 = 95,
- VF610_PAD_PTB26 = 96,
- VF610_PAD_PTB27 = 97,
- VF610_PAD_PTB28 = 98,
- VF610_PAD_PTC26 = 99,
- VF610_PAD_PTC27 = 100,
- VF610_PAD_PTC28 = 101,
- VF610_PAD_PTC29 = 102,
- VF610_PAD_PTC30 = 103,
- VF610_PAD_PTC31 = 104,
- VF610_PAD_PTE0 = 105,
- VF610_PAD_PTE1 = 106,
- VF610_PAD_PTE2 = 107,
- VF610_PAD_PTE3 = 108,
- VF610_PAD_PTE4 = 109,
- VF610_PAD_PTE5 = 110,
- VF610_PAD_PTE6 = 111,
- VF610_PAD_PTE7 = 112,
- VF610_PAD_PTE8 = 113,
- VF610_PAD_PTE9 = 114,
- VF610_PAD_PTE10 = 115,
- VF610_PAD_PTE11 = 116,
- VF610_PAD_PTE12 = 117,
- VF610_PAD_PTE13 = 118,
- VF610_PAD_PTE14 = 119,
- VF610_PAD_PTE15 = 120,
- VF610_PAD_PTE16 = 121,
- VF610_PAD_PTE17 = 122,
- VF610_PAD_PTE18 = 123,
- VF610_PAD_PTE19 = 124,
- VF610_PAD_PTE20 = 125,
- VF610_PAD_PTE21 = 126,
- VF610_PAD_PTE22 = 127,
- VF610_PAD_PTE23 = 128,
- VF610_PAD_PTE24 = 129,
- VF610_PAD_PTE25 = 130,
- VF610_PAD_PTE26 = 131,
- VF610_PAD_PTE27 = 132,
- VF610_PAD_PTE28 = 133,
- VF610_PAD_PTA7 = 134,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(VF610_PAD_PTA6),
- IMX_PINCTRL_PIN(VF610_PAD_PTA8),
- IMX_PINCTRL_PIN(VF610_PAD_PTA9),
- IMX_PINCTRL_PIN(VF610_PAD_PTA10),
- IMX_PINCTRL_PIN(VF610_PAD_PTA11),
- IMX_PINCTRL_PIN(VF610_PAD_PTA12),
- IMX_PINCTRL_PIN(VF610_PAD_PTA16),
- IMX_PINCTRL_PIN(VF610_PAD_PTA17),
- IMX_PINCTRL_PIN(VF610_PAD_PTA18),
- IMX_PINCTRL_PIN(VF610_PAD_PTA19),
- IMX_PINCTRL_PIN(VF610_PAD_PTA20),
- IMX_PINCTRL_PIN(VF610_PAD_PTA21),
- IMX_PINCTRL_PIN(VF610_PAD_PTA22),
- IMX_PINCTRL_PIN(VF610_PAD_PTA23),
- IMX_PINCTRL_PIN(VF610_PAD_PTA24),
- IMX_PINCTRL_PIN(VF610_PAD_PTA25),
- IMX_PINCTRL_PIN(VF610_PAD_PTA26),
- IMX_PINCTRL_PIN(VF610_PAD_PTA27),
- IMX_PINCTRL_PIN(VF610_PAD_PTA28),
- IMX_PINCTRL_PIN(VF610_PAD_PTA29),
- IMX_PINCTRL_PIN(VF610_PAD_PTA30),
- IMX_PINCTRL_PIN(VF610_PAD_PTA31),
- IMX_PINCTRL_PIN(VF610_PAD_PTB0),
- IMX_PINCTRL_PIN(VF610_PAD_PTB1),
- IMX_PINCTRL_PIN(VF610_PAD_PTB2),
- IMX_PINCTRL_PIN(VF610_PAD_PTB3),
- IMX_PINCTRL_PIN(VF610_PAD_PTB4),
- IMX_PINCTRL_PIN(VF610_PAD_PTB5),
- IMX_PINCTRL_PIN(VF610_PAD_PTB6),
- IMX_PINCTRL_PIN(VF610_PAD_PTB7),
- IMX_PINCTRL_PIN(VF610_PAD_PTB8),
- IMX_PINCTRL_PIN(VF610_PAD_PTB9),
- IMX_PINCTRL_PIN(VF610_PAD_PTB10),
- IMX_PINCTRL_PIN(VF610_PAD_PTB11),
- IMX_PINCTRL_PIN(VF610_PAD_PTB12),
- IMX_PINCTRL_PIN(VF610_PAD_PTB13),
- IMX_PINCTRL_PIN(VF610_PAD_PTB14),
- IMX_PINCTRL_PIN(VF610_PAD_PTB15),
- IMX_PINCTRL_PIN(VF610_PAD_PTB16),
- IMX_PINCTRL_PIN(VF610_PAD_PTB17),
- IMX_PINCTRL_PIN(VF610_PAD_PTB18),
- IMX_PINCTRL_PIN(VF610_PAD_PTB19),
- IMX_PINCTRL_PIN(VF610_PAD_PTB20),
- IMX_PINCTRL_PIN(VF610_PAD_PTB21),
- IMX_PINCTRL_PIN(VF610_PAD_PTB22),
- IMX_PINCTRL_PIN(VF610_PAD_PTC0),
- IMX_PINCTRL_PIN(VF610_PAD_PTC1),
- IMX_PINCTRL_PIN(VF610_PAD_PTC2),
- IMX_PINCTRL_PIN(VF610_PAD_PTC3),
- IMX_PINCTRL_PIN(VF610_PAD_PTC4),
- IMX_PINCTRL_PIN(VF610_PAD_PTC5),
- IMX_PINCTRL_PIN(VF610_PAD_PTC6),
- IMX_PINCTRL_PIN(VF610_PAD_PTC7),
- IMX_PINCTRL_PIN(VF610_PAD_PTC8),
- IMX_PINCTRL_PIN(VF610_PAD_PTC9),
- IMX_PINCTRL_PIN(VF610_PAD_PTC10),
- IMX_PINCTRL_PIN(VF610_PAD_PTC11),
- IMX_PINCTRL_PIN(VF610_PAD_PTC12),
- IMX_PINCTRL_PIN(VF610_PAD_PTC13),
- IMX_PINCTRL_PIN(VF610_PAD_PTC14),
- IMX_PINCTRL_PIN(VF610_PAD_PTC15),
- IMX_PINCTRL_PIN(VF610_PAD_PTC16),
- IMX_PINCTRL_PIN(VF610_PAD_PTC17),
- IMX_PINCTRL_PIN(VF610_PAD_PTD31),
- IMX_PINCTRL_PIN(VF610_PAD_PTD30),
- IMX_PINCTRL_PIN(VF610_PAD_PTD29),
- IMX_PINCTRL_PIN(VF610_PAD_PTD28),
- IMX_PINCTRL_PIN(VF610_PAD_PTD27),
- IMX_PINCTRL_PIN(VF610_PAD_PTD26),
- IMX_PINCTRL_PIN(VF610_PAD_PTD25),
- IMX_PINCTRL_PIN(VF610_PAD_PTD24),
- IMX_PINCTRL_PIN(VF610_PAD_PTD23),
- IMX_PINCTRL_PIN(VF610_PAD_PTD22),
- IMX_PINCTRL_PIN(VF610_PAD_PTD21),
- IMX_PINCTRL_PIN(VF610_PAD_PTD20),
- IMX_PINCTRL_PIN(VF610_PAD_PTD19),
- IMX_PINCTRL_PIN(VF610_PAD_PTD18),
- IMX_PINCTRL_PIN(VF610_PAD_PTD17),
- IMX_PINCTRL_PIN(VF610_PAD_PTD16),
- IMX_PINCTRL_PIN(VF610_PAD_PTD0),
- IMX_PINCTRL_PIN(VF610_PAD_PTD1),
- IMX_PINCTRL_PIN(VF610_PAD_PTD2),
- IMX_PINCTRL_PIN(VF610_PAD_PTD3),
- IMX_PINCTRL_PIN(VF610_PAD_PTD4),
- IMX_PINCTRL_PIN(VF610_PAD_PTD5),
- IMX_PINCTRL_PIN(VF610_PAD_PTD6),
- IMX_PINCTRL_PIN(VF610_PAD_PTD7),
- IMX_PINCTRL_PIN(VF610_PAD_PTD8),
- IMX_PINCTRL_PIN(VF610_PAD_PTD9),
- IMX_PINCTRL_PIN(VF610_PAD_PTD10),
- IMX_PINCTRL_PIN(VF610_PAD_PTD11),
- IMX_PINCTRL_PIN(VF610_PAD_PTD12),
- IMX_PINCTRL_PIN(VF610_PAD_PTD13),
- IMX_PINCTRL_PIN(VF610_PAD_PTB23),
- IMX_PINCTRL_PIN(VF610_PAD_PTB24),
- IMX_PINCTRL_PIN(VF610_PAD_PTB25),
- IMX_PINCTRL_PIN(VF610_PAD_PTB26),
- IMX_PINCTRL_PIN(VF610_PAD_PTB27),
- IMX_PINCTRL_PIN(VF610_PAD_PTB28),
- IMX_PINCTRL_PIN(VF610_PAD_PTC26),
- IMX_PINCTRL_PIN(VF610_PAD_PTC27),
- IMX_PINCTRL_PIN(VF610_PAD_PTC28),
- IMX_PINCTRL_PIN(VF610_PAD_PTC29),
- IMX_PINCTRL_PIN(VF610_PAD_PTC30),
- IMX_PINCTRL_PIN(VF610_PAD_PTC31),
- IMX_PINCTRL_PIN(VF610_PAD_PTE0),
- IMX_PINCTRL_PIN(VF610_PAD_PTE1),
- IMX_PINCTRL_PIN(VF610_PAD_PTE2),
- IMX_PINCTRL_PIN(VF610_PAD_PTE3),
- IMX_PINCTRL_PIN(VF610_PAD_PTE4),
- IMX_PINCTRL_PIN(VF610_PAD_PTE5),
- IMX_PINCTRL_PIN(VF610_PAD_PTE6),
- IMX_PINCTRL_PIN(VF610_PAD_PTE7),
- IMX_PINCTRL_PIN(VF610_PAD_PTE8),
- IMX_PINCTRL_PIN(VF610_PAD_PTE9),
- IMX_PINCTRL_PIN(VF610_PAD_PTE10),
- IMX_PINCTRL_PIN(VF610_PAD_PTE11),
- IMX_PINCTRL_PIN(VF610_PAD_PTE12),
- IMX_PINCTRL_PIN(VF610_PAD_PTE13),
- IMX_PINCTRL_PIN(VF610_PAD_PTE14),
- IMX_PINCTRL_PIN(VF610_PAD_PTE15),
- IMX_PINCTRL_PIN(VF610_PAD_PTE16),
- IMX_PINCTRL_PIN(VF610_PAD_PTE17),
- IMX_PINCTRL_PIN(VF610_PAD_PTE18),
- IMX_PINCTRL_PIN(VF610_PAD_PTE19),
- IMX_PINCTRL_PIN(VF610_PAD_PTE20),
- IMX_PINCTRL_PIN(VF610_PAD_PTE21),
- IMX_PINCTRL_PIN(VF610_PAD_PTE22),
- IMX_PINCTRL_PIN(VF610_PAD_PTE23),
- IMX_PINCTRL_PIN(VF610_PAD_PTE24),
- IMX_PINCTRL_PIN(VF610_PAD_PTE25),
- IMX_PINCTRL_PIN(VF610_PAD_PTE26),
- IMX_PINCTRL_PIN(VF610_PAD_PTE27),
- IMX_PINCTRL_PIN(VF610_PAD_PTE28),
- IMX_PINCTRL_PIN(VF610_PAD_PTA7),
-};
-
-static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
- .pins = vf610_pinctrl_pads,
- .npins = ARRAY_SIZE(vf610_pinctrl_pads),
- .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
-};
-
-static struct of_device_id vf610_pinctrl_of_match[] = {
- { .compatible = "fsl,vf610-iomuxc", },
- { /* sentinel */ }
-};
-
-static int vf610_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &vf610_pinctrl_info);
-}
-
-static struct platform_driver vf610_pinctrl_driver = {
- .driver = {
- .name = "vf610-pinctrl",
- .owner = THIS_MODULE,
- .of_match_table = vf610_pinctrl_of_match,
- },
- .probe = vf610_pinctrl_probe,
- .remove = imx_pinctrl_remove,
-};
-
-static int __init vf610_pinctrl_init(void)
-{
- return platform_driver_register(&vf610_pinctrl_driver);
-}
-arch_initcall(vf610_pinctrl_init);
-
-static void __exit vf610_pinctrl_exit(void)
-{
- platform_driver_unregister(&vf610_pinctrl_driver);
-}
-module_exit(vf610_pinctrl_exit);
-
-MODULE_DESCRIPTION("Freescale VF610 pinctrl driver");
-MODULE_LICENSE("GPL v2");
of_gpiochip_add(&xway_chip);
ret = gpiochip_add(&xway_chip);
if (ret) {
+ of_gpiochip_remove(&xway_chip);
dev_err(&pdev->dev, "Failed to register gpio chip\n");
return ret;
}
/* register with the generic lantiq layer */
ret = ltq_pinctrl_register(pdev, &xway_info);
if (ret) {
+ gpiochip_remove(&xway_chip);
dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
return ret;
}
!ops->get_functions_count ||
!ops->get_function_name ||
!ops->get_function_groups ||
- !ops->enable) {
+ !ops->set_mux) {
dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n");
return -EINVAL;
}
desc->mux_setting = &(setting->data.mux);
}
- ret = ops->enable(pctldev, setting->data.mux.func,
- setting->data.mux.group);
+ ret = ops->set_mux(pctldev, setting->data.mux.func,
+ setting->data.mux.group);
if (ret)
- goto err_enable;
+ goto err_set_mux;
return 0;
-err_enable:
+err_set_mux:
for (i = 0; i < num_pins; i++) {
desc = pin_desc_get(pctldev, pins[i]);
if (desc)
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
+config PINCTRL_APQ8084
+ tristate "Qualcomm APQ8084 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
+
config PINCTRL_IPQ8064
tristate "Qualcomm IPQ8064 pin controller driver"
depends on GPIOLIB && OF
# Qualcomm pin control drivers
obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
+obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
.intr_status_bit = 0, \
.intr_ack_high = 1, \
.intr_target_bit = 0, \
+ .intr_target_kpss_val = 4, \
.intr_raw_status_bit = 3, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \
APQ_MUX_tsif1,
APQ_MUX_tsif2,
APQ_MUX_usb2_hsic,
+ APQ_MUX_ps_hold,
APQ_MUX_NA,
};
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
"gpio85", "gpio86", "gpio87", "gpio88", "gpio89"
};
+static const char * const ps_hold_groups[] = {
+ "gpio78"
+};
static const char * const gsbi1_groups[] = {
"gpio18", "gpio19", "gpio20", "gpio21"
};
FUNCTION(tsif1),
FUNCTION(tsif2),
FUNCTION(usb2_hsic),
+ FUNCTION(ps_hold),
};
static const struct msm_pingroup apq8064_groups[] = {
PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(78, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--- /dev/null
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+static const struct pinctrl_pin_desc apq8084_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "GPIO_108"),
+ PINCTRL_PIN(109, "GPIO_109"),
+ PINCTRL_PIN(110, "GPIO_110"),
+ PINCTRL_PIN(111, "GPIO_111"),
+ PINCTRL_PIN(112, "GPIO_112"),
+ PINCTRL_PIN(113, "GPIO_113"),
+ PINCTRL_PIN(114, "GPIO_114"),
+ PINCTRL_PIN(115, "GPIO_115"),
+ PINCTRL_PIN(116, "GPIO_116"),
+ PINCTRL_PIN(117, "GPIO_117"),
+ PINCTRL_PIN(118, "GPIO_118"),
+ PINCTRL_PIN(119, "GPIO_119"),
+ PINCTRL_PIN(120, "GPIO_120"),
+ PINCTRL_PIN(121, "GPIO_121"),
+ PINCTRL_PIN(122, "GPIO_122"),
+ PINCTRL_PIN(123, "GPIO_123"),
+ PINCTRL_PIN(124, "GPIO_124"),
+ PINCTRL_PIN(125, "GPIO_125"),
+ PINCTRL_PIN(126, "GPIO_126"),
+ PINCTRL_PIN(127, "GPIO_127"),
+ PINCTRL_PIN(128, "GPIO_128"),
+ PINCTRL_PIN(129, "GPIO_129"),
+ PINCTRL_PIN(130, "GPIO_130"),
+ PINCTRL_PIN(131, "GPIO_131"),
+ PINCTRL_PIN(132, "GPIO_132"),
+ PINCTRL_PIN(133, "GPIO_133"),
+ PINCTRL_PIN(134, "GPIO_134"),
+ PINCTRL_PIN(135, "GPIO_135"),
+ PINCTRL_PIN(136, "GPIO_136"),
+ PINCTRL_PIN(137, "GPIO_137"),
+ PINCTRL_PIN(138, "GPIO_138"),
+ PINCTRL_PIN(139, "GPIO_139"),
+ PINCTRL_PIN(140, "GPIO_140"),
+ PINCTRL_PIN(141, "GPIO_141"),
+ PINCTRL_PIN(142, "GPIO_142"),
+ PINCTRL_PIN(143, "GPIO_143"),
+ PINCTRL_PIN(144, "GPIO_144"),
+ PINCTRL_PIN(145, "GPIO_145"),
+ PINCTRL_PIN(146, "GPIO_146"),
+
+ PINCTRL_PIN(147, "SDC1_CLK"),
+ PINCTRL_PIN(148, "SDC1_CMD"),
+ PINCTRL_PIN(149, "SDC1_DATA"),
+ PINCTRL_PIN(150, "SDC2_CLK"),
+ PINCTRL_PIN(151, "SDC2_CMD"),
+ PINCTRL_PIN(152, "SDC2_DATA"),
+};
+
+#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
+
+DECLARE_APQ_GPIO_PINS(0);
+DECLARE_APQ_GPIO_PINS(1);
+DECLARE_APQ_GPIO_PINS(2);
+DECLARE_APQ_GPIO_PINS(3);
+DECLARE_APQ_GPIO_PINS(4);
+DECLARE_APQ_GPIO_PINS(5);
+DECLARE_APQ_GPIO_PINS(6);
+DECLARE_APQ_GPIO_PINS(7);
+DECLARE_APQ_GPIO_PINS(8);
+DECLARE_APQ_GPIO_PINS(9);
+DECLARE_APQ_GPIO_PINS(10);
+DECLARE_APQ_GPIO_PINS(11);
+DECLARE_APQ_GPIO_PINS(12);
+DECLARE_APQ_GPIO_PINS(13);
+DECLARE_APQ_GPIO_PINS(14);
+DECLARE_APQ_GPIO_PINS(15);
+DECLARE_APQ_GPIO_PINS(16);
+DECLARE_APQ_GPIO_PINS(17);
+DECLARE_APQ_GPIO_PINS(18);
+DECLARE_APQ_GPIO_PINS(19);
+DECLARE_APQ_GPIO_PINS(20);
+DECLARE_APQ_GPIO_PINS(21);
+DECLARE_APQ_GPIO_PINS(22);
+DECLARE_APQ_GPIO_PINS(23);
+DECLARE_APQ_GPIO_PINS(24);
+DECLARE_APQ_GPIO_PINS(25);
+DECLARE_APQ_GPIO_PINS(26);
+DECLARE_APQ_GPIO_PINS(27);
+DECLARE_APQ_GPIO_PINS(28);
+DECLARE_APQ_GPIO_PINS(29);
+DECLARE_APQ_GPIO_PINS(30);
+DECLARE_APQ_GPIO_PINS(31);
+DECLARE_APQ_GPIO_PINS(32);
+DECLARE_APQ_GPIO_PINS(33);
+DECLARE_APQ_GPIO_PINS(34);
+DECLARE_APQ_GPIO_PINS(35);
+DECLARE_APQ_GPIO_PINS(36);
+DECLARE_APQ_GPIO_PINS(37);
+DECLARE_APQ_GPIO_PINS(38);
+DECLARE_APQ_GPIO_PINS(39);
+DECLARE_APQ_GPIO_PINS(40);
+DECLARE_APQ_GPIO_PINS(41);
+DECLARE_APQ_GPIO_PINS(42);
+DECLARE_APQ_GPIO_PINS(43);
+DECLARE_APQ_GPIO_PINS(44);
+DECLARE_APQ_GPIO_PINS(45);
+DECLARE_APQ_GPIO_PINS(46);
+DECLARE_APQ_GPIO_PINS(47);
+DECLARE_APQ_GPIO_PINS(48);
+DECLARE_APQ_GPIO_PINS(49);
+DECLARE_APQ_GPIO_PINS(50);
+DECLARE_APQ_GPIO_PINS(51);
+DECLARE_APQ_GPIO_PINS(52);
+DECLARE_APQ_GPIO_PINS(53);
+DECLARE_APQ_GPIO_PINS(54);
+DECLARE_APQ_GPIO_PINS(55);
+DECLARE_APQ_GPIO_PINS(56);
+DECLARE_APQ_GPIO_PINS(57);
+DECLARE_APQ_GPIO_PINS(58);
+DECLARE_APQ_GPIO_PINS(59);
+DECLARE_APQ_GPIO_PINS(60);
+DECLARE_APQ_GPIO_PINS(61);
+DECLARE_APQ_GPIO_PINS(62);
+DECLARE_APQ_GPIO_PINS(63);
+DECLARE_APQ_GPIO_PINS(64);
+DECLARE_APQ_GPIO_PINS(65);
+DECLARE_APQ_GPIO_PINS(66);
+DECLARE_APQ_GPIO_PINS(67);
+DECLARE_APQ_GPIO_PINS(68);
+DECLARE_APQ_GPIO_PINS(69);
+DECLARE_APQ_GPIO_PINS(70);
+DECLARE_APQ_GPIO_PINS(71);
+DECLARE_APQ_GPIO_PINS(72);
+DECLARE_APQ_GPIO_PINS(73);
+DECLARE_APQ_GPIO_PINS(74);
+DECLARE_APQ_GPIO_PINS(75);
+DECLARE_APQ_GPIO_PINS(76);
+DECLARE_APQ_GPIO_PINS(77);
+DECLARE_APQ_GPIO_PINS(78);
+DECLARE_APQ_GPIO_PINS(79);
+DECLARE_APQ_GPIO_PINS(80);
+DECLARE_APQ_GPIO_PINS(81);
+DECLARE_APQ_GPIO_PINS(82);
+DECLARE_APQ_GPIO_PINS(83);
+DECLARE_APQ_GPIO_PINS(84);
+DECLARE_APQ_GPIO_PINS(85);
+DECLARE_APQ_GPIO_PINS(86);
+DECLARE_APQ_GPIO_PINS(87);
+DECLARE_APQ_GPIO_PINS(88);
+DECLARE_APQ_GPIO_PINS(89);
+DECLARE_APQ_GPIO_PINS(90);
+DECLARE_APQ_GPIO_PINS(91);
+DECLARE_APQ_GPIO_PINS(92);
+DECLARE_APQ_GPIO_PINS(93);
+DECLARE_APQ_GPIO_PINS(94);
+DECLARE_APQ_GPIO_PINS(95);
+DECLARE_APQ_GPIO_PINS(96);
+DECLARE_APQ_GPIO_PINS(97);
+DECLARE_APQ_GPIO_PINS(98);
+DECLARE_APQ_GPIO_PINS(99);
+DECLARE_APQ_GPIO_PINS(100);
+DECLARE_APQ_GPIO_PINS(101);
+DECLARE_APQ_GPIO_PINS(102);
+DECLARE_APQ_GPIO_PINS(103);
+DECLARE_APQ_GPIO_PINS(104);
+DECLARE_APQ_GPIO_PINS(105);
+DECLARE_APQ_GPIO_PINS(106);
+DECLARE_APQ_GPIO_PINS(107);
+DECLARE_APQ_GPIO_PINS(108);
+DECLARE_APQ_GPIO_PINS(109);
+DECLARE_APQ_GPIO_PINS(110);
+DECLARE_APQ_GPIO_PINS(111);
+DECLARE_APQ_GPIO_PINS(112);
+DECLARE_APQ_GPIO_PINS(113);
+DECLARE_APQ_GPIO_PINS(114);
+DECLARE_APQ_GPIO_PINS(115);
+DECLARE_APQ_GPIO_PINS(116);
+DECLARE_APQ_GPIO_PINS(117);
+DECLARE_APQ_GPIO_PINS(118);
+DECLARE_APQ_GPIO_PINS(119);
+DECLARE_APQ_GPIO_PINS(120);
+DECLARE_APQ_GPIO_PINS(121);
+DECLARE_APQ_GPIO_PINS(122);
+DECLARE_APQ_GPIO_PINS(123);
+DECLARE_APQ_GPIO_PINS(124);
+DECLARE_APQ_GPIO_PINS(125);
+DECLARE_APQ_GPIO_PINS(126);
+DECLARE_APQ_GPIO_PINS(127);
+DECLARE_APQ_GPIO_PINS(128);
+DECLARE_APQ_GPIO_PINS(129);
+DECLARE_APQ_GPIO_PINS(130);
+DECLARE_APQ_GPIO_PINS(131);
+DECLARE_APQ_GPIO_PINS(132);
+DECLARE_APQ_GPIO_PINS(133);
+DECLARE_APQ_GPIO_PINS(134);
+DECLARE_APQ_GPIO_PINS(135);
+DECLARE_APQ_GPIO_PINS(136);
+DECLARE_APQ_GPIO_PINS(137);
+DECLARE_APQ_GPIO_PINS(138);
+DECLARE_APQ_GPIO_PINS(139);
+DECLARE_APQ_GPIO_PINS(140);
+DECLARE_APQ_GPIO_PINS(141);
+DECLARE_APQ_GPIO_PINS(142);
+DECLARE_APQ_GPIO_PINS(143);
+DECLARE_APQ_GPIO_PINS(144);
+DECLARE_APQ_GPIO_PINS(145);
+DECLARE_APQ_GPIO_PINS(146);
+
+static const unsigned int sdc1_clk_pins[] = { 147 };
+static const unsigned int sdc1_cmd_pins[] = { 148 };
+static const unsigned int sdc1_data_pins[] = { 149 };
+static const unsigned int sdc2_clk_pins[] = { 150 };
+static const unsigned int sdc2_cmd_pins[] = { 151 };
+static const unsigned int sdc2_data_pins[] = { 152 };
+
+#define FUNCTION(fname) \
+ [APQ_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ APQ_MUX_gpio, \
+ APQ_MUX_##f1, \
+ APQ_MUX_##f2, \
+ APQ_MUX_##f3, \
+ APQ_MUX_##f4, \
+ APQ_MUX_##f5, \
+ APQ_MUX_##f6, \
+ APQ_MUX_##f7 \
+ }, \
+ .nfuncs = 8, \
+ .ctl_reg = 0x1000 + 0x10 * id, \
+ .io_reg = 0x1004 + 0x10 * id, \
+ .intr_cfg_reg = 0x1008 + 0x10 * id, \
+ .intr_status_reg = 0x100c + 0x10 * id, \
+ .intr_target_reg = 0x1008 + 0x10 * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_ack_high = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+enum apq8084_functions {
+ APQ_MUX_adsp_ext,
+ APQ_MUX_audio_ref,
+ APQ_MUX_blsp_i2c1,
+ APQ_MUX_blsp_i2c2,
+ APQ_MUX_blsp_i2c3,
+ APQ_MUX_blsp_i2c4,
+ APQ_MUX_blsp_i2c5,
+ APQ_MUX_blsp_i2c6,
+ APQ_MUX_blsp_i2c7,
+ APQ_MUX_blsp_i2c8,
+ APQ_MUX_blsp_i2c9,
+ APQ_MUX_blsp_i2c10,
+ APQ_MUX_blsp_i2c11,
+ APQ_MUX_blsp_i2c12,
+ APQ_MUX_blsp_spi1,
+ APQ_MUX_blsp_spi1_cs1,
+ APQ_MUX_blsp_spi1_cs2,
+ APQ_MUX_blsp_spi1_cs3,
+ APQ_MUX_blsp_spi2,
+ APQ_MUX_blsp_spi3,
+ APQ_MUX_blsp_spi3_cs1,
+ APQ_MUX_blsp_spi3_cs2,
+ APQ_MUX_blsp_spi3_cs3,
+ APQ_MUX_blsp_spi4,
+ APQ_MUX_blsp_spi5,
+ APQ_MUX_blsp_spi6,
+ APQ_MUX_blsp_spi7,
+ APQ_MUX_blsp_spi8,
+ APQ_MUX_blsp_spi9,
+ APQ_MUX_blsp_spi10,
+ APQ_MUX_blsp_spi10_cs1,
+ APQ_MUX_blsp_spi10_cs2,
+ APQ_MUX_blsp_spi10_cs3,
+ APQ_MUX_blsp_spi11,
+ APQ_MUX_blsp_spi12,
+ APQ_MUX_blsp_uart1,
+ APQ_MUX_blsp_uart2,
+ APQ_MUX_blsp_uart3,
+ APQ_MUX_blsp_uart4,
+ APQ_MUX_blsp_uart5,
+ APQ_MUX_blsp_uart6,
+ APQ_MUX_blsp_uart7,
+ APQ_MUX_blsp_uart8,
+ APQ_MUX_blsp_uart9,
+ APQ_MUX_blsp_uart10,
+ APQ_MUX_blsp_uart11,
+ APQ_MUX_blsp_uart12,
+ APQ_MUX_blsp_uim1,
+ APQ_MUX_blsp_uim2,
+ APQ_MUX_blsp_uim3,
+ APQ_MUX_blsp_uim4,
+ APQ_MUX_blsp_uim5,
+ APQ_MUX_blsp_uim6,
+ APQ_MUX_blsp_uim7,
+ APQ_MUX_blsp_uim8,
+ APQ_MUX_blsp_uim9,
+ APQ_MUX_blsp_uim10,
+ APQ_MUX_blsp_uim11,
+ APQ_MUX_blsp_uim12,
+ APQ_MUX_cam_mclk0,
+ APQ_MUX_cam_mclk1,
+ APQ_MUX_cam_mclk2,
+ APQ_MUX_cam_mclk3,
+ APQ_MUX_cci_async,
+ APQ_MUX_cci_async_in0,
+ APQ_MUX_cci_i2c0,
+ APQ_MUX_cci_i2c1,
+ APQ_MUX_cci_timer0,
+ APQ_MUX_cci_timer1,
+ APQ_MUX_cci_timer2,
+ APQ_MUX_cci_timer3,
+ APQ_MUX_cci_timer4,
+ APQ_MUX_edp_hpd,
+ APQ_MUX_gcc_gp1,
+ APQ_MUX_gcc_gp2,
+ APQ_MUX_gcc_gp3,
+ APQ_MUX_gcc_obt,
+ APQ_MUX_gcc_vtt,
+ APQ_MUX_gp_mn,
+ APQ_MUX_gp_pdm0,
+ APQ_MUX_gp_pdm1,
+ APQ_MUX_gp_pdm2,
+ APQ_MUX_gp0_clk,
+ APQ_MUX_gp1_clk,
+ APQ_MUX_gpio,
+ APQ_MUX_hdmi_cec,
+ APQ_MUX_hdmi_ddc,
+ APQ_MUX_hdmi_dtest,
+ APQ_MUX_hdmi_hpd,
+ APQ_MUX_hdmi_rcv,
+ APQ_MUX_hsic,
+ APQ_MUX_ldo_en,
+ APQ_MUX_ldo_update,
+ APQ_MUX_mdp_vsync,
+ APQ_MUX_pci_e0,
+ APQ_MUX_pci_e0_n,
+ APQ_MUX_pci_e0_rst,
+ APQ_MUX_pci_e1,
+ APQ_MUX_pci_e1_rst,
+ APQ_MUX_pci_e1_rst_n,
+ APQ_MUX_pci_e1_clkreq_n,
+ APQ_MUX_pri_mi2s,
+ APQ_MUX_qua_mi2s,
+ APQ_MUX_sata_act,
+ APQ_MUX_sata_devsleep,
+ APQ_MUX_sata_devsleep_n,
+ APQ_MUX_sd_write,
+ APQ_MUX_sdc_emmc_mode,
+ APQ_MUX_sdc3,
+ APQ_MUX_sdc4,
+ APQ_MUX_sec_mi2s,
+ APQ_MUX_slimbus,
+ APQ_MUX_spdif_tx,
+ APQ_MUX_spkr_i2s,
+ APQ_MUX_spkr_i2s_ws,
+ APQ_MUX_spss_geni,
+ APQ_MUX_ter_mi2s,
+ APQ_MUX_tsif1,
+ APQ_MUX_tsif2,
+ APQ_MUX_uim,
+ APQ_MUX_uim_batt_alarm,
+ APQ_MUX_NA,
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
+ "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
+ "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
+ "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
+ "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
+ "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146"
+};
+
+static const char * const adsp_ext_groups[] = {
+ "gpio34"
+};
+static const char * const audio_ref_groups[] = {
+ "gpio100"
+};
+static const char * const blsp_i2c1_groups[] = {
+ "gpio2", "gpio3"
+};
+static const char * const blsp_i2c2_groups[] = {
+ "gpio6", "gpio7"
+};
+static const char * const blsp_i2c3_groups[] = {
+ "gpio10", "gpio11"
+};
+static const char * const blsp_i2c4_groups[] = {
+ "gpio29", "gpio30"
+};
+static const char * const blsp_i2c5_groups[] = {
+ "gpio41", "gpio42"
+};
+static const char * const blsp_i2c6_groups[] = {
+ "gpio45", "gpio46"
+};
+static const char * const blsp_i2c7_groups[] = {
+ "gpio132", "gpio133"
+};
+static const char * const blsp_i2c8_groups[] = {
+ "gpio53", "gpio54"
+};
+static const char * const blsp_i2c9_groups[] = {
+ "gpio57", "gpio58"
+};
+static const char * const blsp_i2c10_groups[] = {
+ "gpio61", "gpio62"
+};
+static const char * const blsp_i2c11_groups[] = {
+ "gpio65", "gpio66"
+};
+static const char * const blsp_i2c12_groups[] = {
+ "gpio49", "gpio50"
+};
+static const char * const blsp_spi1_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3"
+};
+static const char * const blsp_spi2_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7"
+};
+static const char * const blsp_spi3_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char * const blsp_spi4_groups[] = {
+ "gpio27", "gpio28", "gpio29", "gpio30"
+};
+static const char * const blsp_spi5_groups[] = {
+ "gpio39", "gpio40", "gpio41", "gpio42"
+};
+static const char * const blsp_spi6_groups[] = {
+ "gpio43", "gpio44", "gpio45", "gpio46"
+};
+static const char * const blsp_spi7_groups[] = {
+ "gpio130", "gpio131", "gpio132", "gpio133"
+};
+static const char * const blsp_spi8_groups[] = {
+ "gpio51", "gpio52", "gpio53", "gpio54"
+};
+static const char * const blsp_spi9_groups[] = {
+ "gpio55", "gpio56", "gpio57", "gpio58"
+};
+static const char * const blsp_spi10_groups[] = {
+ "gpio59", "gpio60", "gpio61", "gpio62"
+};
+static const char * const blsp_spi11_groups[] = {
+ "gpio63", "gpio64", "gpio65", "gpio66"
+};
+static const char * const blsp_spi12_groups[] = {
+ "gpio47", "gpio48", "gpio49", "gpio50"
+};
+static const char * const blsp_uart1_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3"
+};
+static const char * const blsp_uart2_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7"
+};
+static const char * const blsp_uart3_groups[] = {
+ "gpio8"
+};
+static const char * const blsp_uart4_groups[] = {
+ "gpio27", "gpio28", "gpio29", "gpio30"
+};
+static const char * const blsp_uart5_groups[] = {
+ "gpio39", "gpio40", "gpio41", "gpio42"
+};
+static const char * const blsp_uart6_groups[] = {
+ "gpio43", "gpio44", "gpio45", "gpio46"
+};
+static const char * const blsp_uart7_groups[] = {
+ "gpio130", "gpio131", "gpio132", "gpio133"
+};
+static const char * const blsp_uart8_groups[] = {
+ "gpio51", "gpio52", "gpio53", "gpio54"
+};
+static const char * const blsp_uart9_groups[] = {
+ "gpio55", "gpio56", "gpio57", "gpio58"
+};
+static const char * const blsp_uart10_groups[] = {
+ "gpio59", "gpio60", "gpio61", "gpio62"
+};
+static const char * const blsp_uart11_groups[] = {
+ "gpio63", "gpio64", "gpio65", "gpio66"
+};
+static const char * const blsp_uart12_groups[] = {
+ "gpio47", "gpio48", "gpio49", "gpio50"
+};
+static const char * const blsp_uim1_groups[] = {
+ "gpio0", "gpio1"
+};
+static const char * const blsp_uim2_groups[] = {
+ "gpio4", "gpio5"
+};
+static const char * const blsp_uim3_groups[] = {
+ "gpio8", "gpio9"
+};
+static const char * const blsp_uim4_groups[] = {
+ "gpio27", "gpio28"
+};
+static const char * const blsp_uim5_groups[] = {
+ "gpio39", "gpio40"
+};
+static const char * const blsp_uim6_groups[] = {
+ "gpio43", "gpio44"
+};
+static const char * const blsp_uim7_groups[] = {
+ "gpio130", "gpio131"
+};
+static const char * const blsp_uim8_groups[] = {
+ "gpio51", "gpio52"
+};
+static const char * const blsp_uim9_groups[] = {
+ "gpio55", "gpio56"
+};
+static const char * const blsp_uim10_groups[] = {
+ "gpio59", "gpio60"
+};
+static const char * const blsp_uim11_groups[] = {
+ "gpio63", "gpio64"
+};
+static const char * const blsp_uim12_groups[] = {
+ "gpio47", "gpio48"
+};
+static const char * const blsp_spi1_cs1_groups[] = {
+ "gpio116"
+};
+static const char * const blsp_spi1_cs2_groups[] = {
+ "gpio117"
+};
+static const char * const blsp_spi1_cs3_groups[] = {
+ "gpio118"
+};
+static const char * const blsp_spi3_cs1_groups[] = {
+ "gpio67"
+};
+static const char * const blsp_spi3_cs2_groups[] = {
+ "gpio71"
+};
+static const char * const blsp_spi3_cs3_groups[] = {
+ "gpio72"
+};
+static const char * const blsp_spi10_cs1_groups[] = {
+ "gpio106"
+};
+static const char * const blsp_spi10_cs2_groups[] = {
+ "gpio111"
+};
+static const char * const blsp_spi10_cs3_groups[] = {
+ "gpio128"
+};
+static const char * const cam_mclk0_groups[] = {
+ "gpio15"
+};
+static const char * const cam_mclk1_groups[] = {
+ "gpio16"
+};
+static const char * const cam_mclk2_groups[] = {
+ "gpio17"
+};
+static const char * const cam_mclk3_groups[] = {
+ "gpio18"
+};
+static const char * const cci_async_groups[] = {
+ "gpio26", "gpio119"
+};
+static const char * const cci_async_in0_groups[] = {
+ "gpio120"
+};
+static const char * const cci_i2c0_groups[] = {
+ "gpio19", "gpio20"
+};
+static const char * const cci_i2c1_groups[] = {
+ "gpio21", "gpio22"
+};
+static const char * const cci_timer0_groups[] = {
+ "gpio23"
+};
+static const char * const cci_timer1_groups[] = {
+ "gpio24"
+};
+static const char * const cci_timer2_groups[] = {
+ "gpio25"
+};
+static const char * const cci_timer3_groups[] = {
+ "gpio26"
+};
+static const char * const cci_timer4_groups[] = {
+ "gpio119"
+};
+static const char * const edp_hpd_groups[] = {
+ "gpio103"
+};
+static const char * const gcc_gp1_groups[] = {
+ "gpio37"
+};
+static const char * const gcc_gp2_groups[] = {
+ "gpio38"
+};
+static const char * const gcc_gp3_groups[] = {
+ "gpio86"
+};
+static const char * const gcc_obt_groups[] = {
+ "gpio127"
+};
+static const char * const gcc_vtt_groups[] = {
+ "gpio126"
+};
+static const char * const gp_mn_groups[] = {
+ "gpio29"
+};
+static const char * const gp_pdm0_groups[] = {
+ "gpio48", "gpio83"
+};
+static const char * const gp_pdm1_groups[] = {
+ "gpio84", "gpio101"
+};
+static const char * const gp_pdm2_groups[] = {
+ "gpio85", "gpio110"
+};
+static const char * const gp0_clk_groups[] = {
+ "gpio25"
+};
+static const char * const gp1_clk_groups[] = {
+ "gpio26"
+};
+static const char * const hdmi_cec_groups[] = {
+ "gpio31"
+};
+static const char * const hdmi_ddc_groups[] = {
+ "gpio32", "gpio33"
+};
+static const char * const hdmi_dtest_groups[] = {
+ "gpio123"
+};
+static const char * const hdmi_hpd_groups[] = {
+ "gpio34"
+};
+static const char * const hdmi_rcv_groups[] = {
+ "gpio125"
+};
+static const char * const hsic_groups[] = {
+ "gpio134", "gpio135"
+};
+static const char * const ldo_en_groups[] = {
+ "gpio124"
+};
+static const char * const ldo_update_groups[] = {
+ "gpio125"
+};
+static const char * const mdp_vsync_groups[] = {
+ "gpio12", "gpio13", "gpio14"
+};
+static const char * const pci_e0_groups[] = {
+ "gpio68", "gpio70"
+};
+static const char * const pci_e0_n_groups[] = {
+ "gpio68", "gpio70"
+};
+static const char * const pci_e0_rst_groups[] = {
+ "gpio70"
+};
+static const char * const pci_e1_groups[] = {
+ "gpio140"
+};
+static const char * const pci_e1_rst_groups[] = {
+ "gpio140"
+};
+static const char * const pci_e1_rst_n_groups[] = {
+ "gpio140"
+};
+static const char * const pci_e1_clkreq_n_groups[] = {
+ "gpio141"
+};
+static const char * const pri_mi2s_groups[] = {
+ "gpio76", "gpio77", "gpio78", "gpio79", "gpio80"
+};
+static const char * const qua_mi2s_groups[] = {
+ "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"
+};
+static const char * const sata_act_groups[] = {
+ "gpio129"
+};
+static const char * const sata_devsleep_groups[] = {
+ "gpio119"
+};
+static const char * const sata_devsleep_n_groups[] = {
+ "gpio119"
+};
+static const char * const sd_write_groups[] = {
+ "gpio75"
+};
+static const char * const sdc_emmc_mode_groups[] = {
+ "gpio146"
+};
+static const char * const sdc3_groups[] = {
+ "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72"
+};
+static const char * const sdc4_groups[] = {
+ "gpio82", "gpio83", "gpio84", "gpio85", "gpio86",
+ "gpio91", "gpio95", "gpio96", "gpio97", "gpio101"
+};
+static const char * const sec_mi2s_groups[] = {
+ "gpio81", "gpio82", "gpio83", "gpio84", "gpio85"
+};
+static const char * const slimbus_groups[] = {
+ "gpio98", "gpio99"
+};
+static const char * const spdif_tx_groups[] = {
+ "gpio124", "gpio136", "gpio142"
+};
+static const char * const spkr_i2s_groups[] = {
+ "gpio98", "gpio99", "gpio100"
+};
+static const char * const spkr_i2s_ws_groups[] = {
+ "gpio104"
+};
+static const char * const spss_geni_groups[] = {
+ "gpio8", "gpio9"
+};
+static const char * const ter_mi2s_groups[] = {
+ "gpio86", "gpio87", "gpio88", "gpio89", "gpio90"
+};
+static const char * const tsif1_groups[] = {
+ "gpio82", "gpio83", "gpio84", "gpio85", "gpio86"
+};
+static const char * const tsif2_groups[] = {
+ "gpio91", "gpio95", "gpio96", "gpio97", "gpio101"
+};
+static const char * const uim_groups[] = {
+ "gpio130", "gpio131", "gpio132", "gpio133"
+};
+static const char * const uim_batt_alarm_groups[] = {
+ "gpio102"
+};
+static const struct msm_function apq8084_functions[] = {
+ FUNCTION(adsp_ext),
+ FUNCTION(audio_ref),
+ FUNCTION(blsp_i2c1),
+ FUNCTION(blsp_i2c2),
+ FUNCTION(blsp_i2c3),
+ FUNCTION(blsp_i2c4),
+ FUNCTION(blsp_i2c5),
+ FUNCTION(blsp_i2c6),
+ FUNCTION(blsp_i2c7),
+ FUNCTION(blsp_i2c8),
+ FUNCTION(blsp_i2c9),
+ FUNCTION(blsp_i2c10),
+ FUNCTION(blsp_i2c11),
+ FUNCTION(blsp_i2c12),
+ FUNCTION(blsp_spi1),
+ FUNCTION(blsp_spi1_cs1),
+ FUNCTION(blsp_spi1_cs2),
+ FUNCTION(blsp_spi1_cs3),
+ FUNCTION(blsp_spi2),
+ FUNCTION(blsp_spi3),
+ FUNCTION(blsp_spi3_cs1),
+ FUNCTION(blsp_spi3_cs2),
+ FUNCTION(blsp_spi3_cs3),
+ FUNCTION(blsp_spi4),
+ FUNCTION(blsp_spi5),
+ FUNCTION(blsp_spi6),
+ FUNCTION(blsp_spi7),
+ FUNCTION(blsp_spi8),
+ FUNCTION(blsp_spi9),
+ FUNCTION(blsp_spi10),
+ FUNCTION(blsp_spi10_cs1),
+ FUNCTION(blsp_spi10_cs2),
+ FUNCTION(blsp_spi10_cs3),
+ FUNCTION(blsp_spi11),
+ FUNCTION(blsp_spi12),
+ FUNCTION(blsp_uart1),
+ FUNCTION(blsp_uart2),
+ FUNCTION(blsp_uart3),
+ FUNCTION(blsp_uart4),
+ FUNCTION(blsp_uart5),
+ FUNCTION(blsp_uart6),
+ FUNCTION(blsp_uart7),
+ FUNCTION(blsp_uart8),
+ FUNCTION(blsp_uart9),
+ FUNCTION(blsp_uart10),
+ FUNCTION(blsp_uart11),
+ FUNCTION(blsp_uart12),
+ FUNCTION(blsp_uim1),
+ FUNCTION(blsp_uim2),
+ FUNCTION(blsp_uim3),
+ FUNCTION(blsp_uim4),
+ FUNCTION(blsp_uim5),
+ FUNCTION(blsp_uim6),
+ FUNCTION(blsp_uim7),
+ FUNCTION(blsp_uim8),
+ FUNCTION(blsp_uim9),
+ FUNCTION(blsp_uim10),
+ FUNCTION(blsp_uim11),
+ FUNCTION(blsp_uim12),
+ FUNCTION(cam_mclk0),
+ FUNCTION(cam_mclk1),
+ FUNCTION(cam_mclk2),
+ FUNCTION(cam_mclk3),
+ FUNCTION(cci_async),
+ FUNCTION(cci_async_in0),
+ FUNCTION(cci_i2c0),
+ FUNCTION(cci_i2c1),
+ FUNCTION(cci_timer0),
+ FUNCTION(cci_timer1),
+ FUNCTION(cci_timer2),
+ FUNCTION(cci_timer3),
+ FUNCTION(cci_timer4),
+ FUNCTION(edp_hpd),
+ FUNCTION(gcc_gp1),
+ FUNCTION(gcc_gp2),
+ FUNCTION(gcc_gp3),
+ FUNCTION(gcc_obt),
+ FUNCTION(gcc_vtt),
+ FUNCTION(gp_mn),
+ FUNCTION(gp_pdm0),
+ FUNCTION(gp_pdm1),
+ FUNCTION(gp_pdm2),
+ FUNCTION(gp0_clk),
+ FUNCTION(gp1_clk),
+ FUNCTION(gpio),
+ FUNCTION(hdmi_cec),
+ FUNCTION(hdmi_ddc),
+ FUNCTION(hdmi_dtest),
+ FUNCTION(hdmi_hpd),
+ FUNCTION(hdmi_rcv),
+ FUNCTION(hsic),
+ FUNCTION(ldo_en),
+ FUNCTION(ldo_update),
+ FUNCTION(mdp_vsync),
+ FUNCTION(pci_e0),
+ FUNCTION(pci_e0_n),
+ FUNCTION(pci_e0_rst),
+ FUNCTION(pci_e1),
+ FUNCTION(pci_e1_rst),
+ FUNCTION(pci_e1_rst_n),
+ FUNCTION(pci_e1_clkreq_n),
+ FUNCTION(pri_mi2s),
+ FUNCTION(qua_mi2s),
+ FUNCTION(sata_act),
+ FUNCTION(sata_devsleep),
+ FUNCTION(sata_devsleep_n),
+ FUNCTION(sd_write),
+ FUNCTION(sdc_emmc_mode),
+ FUNCTION(sdc3),
+ FUNCTION(sdc4),
+ FUNCTION(sec_mi2s),
+ FUNCTION(slimbus),
+ FUNCTION(spdif_tx),
+ FUNCTION(spkr_i2s),
+ FUNCTION(spkr_i2s_ws),
+ FUNCTION(spss_geni),
+ FUNCTION(ter_mi2s),
+ FUNCTION(tsif1),
+ FUNCTION(tsif2),
+ FUNCTION(uim),
+ FUNCTION(uim_batt_alarm),
+};
+
+static const struct msm_pingroup apq8084_groups[] = {
+ PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
+ PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
+ PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
+ PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
+ PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
+ PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
+ PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
+ PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
+ PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, spss_geni, NA, NA, NA),
+ PINGROUP(9, blsp_spi3, blsp_uim3, blsp_uart3, spss_geni, NA, NA, NA),
+ PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
+ PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
+ PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA),
+ PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA),
+ PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA),
+ PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA),
+ PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA),
+ PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA),
+ PINGROUP(19, cci_i2c0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(20, cci_i2c0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(21, cci_i2c1, NA, NA, NA, NA, NA, NA),
+ PINGROUP(22, cci_i2c1, NA, NA, NA, NA, NA, NA),
+ PINGROUP(23, cci_timer0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(24, cci_timer1, NA, NA, NA, NA, NA, NA),
+ PINGROUP(25, cci_timer2, gp0_clk, NA, NA, NA, NA, NA),
+ PINGROUP(26, cci_timer3, cci_async, gp1_clk, NA, NA, NA, NA),
+ PINGROUP(27, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
+ PINGROUP(28, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
+ PINGROUP(29, blsp_spi4, blsp_uart4, blsp_i2c4, gp_mn, NA, NA, NA),
+ PINGROUP(30, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA),
+ PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA),
+ PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA),
+ PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA),
+ PINGROUP(34, hdmi_hpd, NA, adsp_ext, NA, NA, NA, NA),
+ PINGROUP(35, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(36, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(37, gcc_gp1, NA, NA, NA, NA, NA, NA),
+ PINGROUP(38, gcc_gp2, NA, NA, NA, NA, NA, NA),
+ PINGROUP(39, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
+ PINGROUP(40, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
+ PINGROUP(41, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
+ PINGROUP(42, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
+ PINGROUP(43, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA),
+ PINGROUP(44, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA),
+ PINGROUP(45, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
+ PINGROUP(46, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
+ PINGROUP(47, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA),
+ PINGROUP(48, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm0, NA, NA, NA),
+ PINGROUP(49, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
+ PINGROUP(50, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
+ PINGROUP(51, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
+ PINGROUP(52, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
+ PINGROUP(53, blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA),
+ PINGROUP(54, blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA),
+ PINGROUP(55, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA),
+ PINGROUP(56, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA),
+ PINGROUP(57, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA),
+ PINGROUP(58, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA),
+ PINGROUP(59, blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA),
+ PINGROUP(60, blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA),
+ PINGROUP(61, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
+ PINGROUP(62, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
+ PINGROUP(63, blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA),
+ PINGROUP(64, blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA),
+ PINGROUP(65, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
+ PINGROUP(66, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
+ PINGROUP(67, sdc3, blsp_spi3_cs1, NA, NA, NA, NA, NA),
+ PINGROUP(68, sdc3, pci_e0, NA, NA, NA, NA, NA),
+ PINGROUP(69, sdc3, NA, NA, NA, NA, NA, NA),
+ PINGROUP(70, sdc3, pci_e0_n, pci_e0, NA, NA, NA, NA),
+ PINGROUP(71, sdc3, blsp_spi3_cs2, NA, NA, NA, NA, NA),
+ PINGROUP(72, sdc3, blsp_spi3_cs3, NA, NA, NA, NA, NA),
+ PINGROUP(73, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(74, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(75, sd_write, NA, NA, NA, NA, NA, NA),
+ PINGROUP(76, pri_mi2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(77, pri_mi2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(78, pri_mi2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(79, pri_mi2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(80, pri_mi2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(81, sec_mi2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(82, sec_mi2s, sdc4, tsif1, NA, NA, NA, NA),
+ PINGROUP(83, sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm0),
+ PINGROUP(84, sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm1),
+ PINGROUP(85, sec_mi2s, sdc4, tsif1, NA, gp_pdm2, NA, NA),
+ PINGROUP(86, ter_mi2s, sdc4, tsif1, NA, NA, NA, gcc_gp3),
+ PINGROUP(87, ter_mi2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(88, ter_mi2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(89, ter_mi2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(90, ter_mi2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(91, qua_mi2s, sdc4, tsif2, NA, NA, NA, NA),
+ PINGROUP(92, qua_mi2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(93, qua_mi2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(94, qua_mi2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(95, qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp1),
+ PINGROUP(96, qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp2),
+ PINGROUP(97, qua_mi2s, sdc4, tsif2, NA, gcc_gp3, NA, NA),
+ PINGROUP(98, slimbus, spkr_i2s, NA, NA, NA, NA, NA),
+ PINGROUP(99, slimbus, spkr_i2s, NA, NA, NA, NA, NA),
+ PINGROUP(100, audio_ref, spkr_i2s, NA, NA, NA, NA, NA),
+ PINGROUP(101, sdc4, tsif2, gp_pdm1, NA, NA, NA, NA),
+ PINGROUP(102, uim_batt_alarm, NA, NA, NA, NA, NA, NA),
+ PINGROUP(103, edp_hpd, NA, NA, NA, NA, NA, NA),
+ PINGROUP(104, spkr_i2s, NA, NA, NA, NA, NA, NA),
+ PINGROUP(105, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(106, blsp_spi10_cs1, NA, NA, NA, NA, NA, NA),
+ PINGROUP(107, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(108, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(109, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(110, gp_pdm2, NA, NA, NA, NA, NA, NA),
+ PINGROUP(111, blsp_spi10_cs2, NA, NA, NA, NA, NA, NA),
+ PINGROUP(112, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(113, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(114, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(115, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(116, blsp_spi1_cs1, NA, NA, NA, NA, NA, NA),
+ PINGROUP(117, blsp_spi1_cs2, NA, NA, NA, NA, NA, NA),
+ PINGROUP(118, blsp_spi1_cs3, NA, NA, NA, NA, NA, NA),
+ PINGROUP(119, cci_timer4, cci_async, sata_devsleep, sata_devsleep_n, NA, NA, NA),
+ PINGROUP(120, cci_async, NA, NA, NA, NA, NA, NA),
+ PINGROUP(121, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(122, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(123, hdmi_dtest, NA, NA, NA, NA, NA, NA),
+ PINGROUP(124, spdif_tx, ldo_en, NA, NA, NA, NA, NA),
+ PINGROUP(125, ldo_update, hdmi_rcv, NA, NA, NA, NA, NA),
+ PINGROUP(126, gcc_vtt, NA, NA, NA, NA, NA, NA),
+ PINGROUP(127, gcc_obt, NA, NA, NA, NA, NA, NA),
+ PINGROUP(128, blsp_spi10_cs3, NA, NA, NA, NA, NA, NA),
+ PINGROUP(129, sata_act, NA, NA, NA, NA, NA, NA),
+ PINGROUP(130, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
+ PINGROUP(131, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
+ PINGROUP(132, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
+ PINGROUP(133, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
+ PINGROUP(134, hsic, NA, NA, NA, NA, NA, NA),
+ PINGROUP(135, hsic, NA, NA, NA, NA, NA, NA),
+ PINGROUP(136, spdif_tx, NA, NA, NA, NA, NA, NA),
+ PINGROUP(137, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(138, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(139, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(140, pci_e1_rst_n, pci_e1_rst, NA, NA, NA, NA, NA),
+ PINGROUP(141, pci_e1_clkreq_n, NA, NA, NA, NA, NA, NA),
+ PINGROUP(142, spdif_tx, NA, NA, NA, NA, NA, NA),
+ PINGROUP(143, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(144, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(145, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(146, sdc_emmc_mode, NA, NA, NA, NA, NA, NA),
+
+ SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
+ SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
+ SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
+ SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
+ SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
+ SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
+};
+
+#define NUM_GPIO_PINGROUPS 147
+
+static const struct msm_pinctrl_soc_data apq8084_pinctrl = {
+ .pins = apq8084_pins,
+ .npins = ARRAY_SIZE(apq8084_pins),
+ .functions = apq8084_functions,
+ .nfunctions = ARRAY_SIZE(apq8084_functions),
+ .groups = apq8084_groups,
+ .ngroups = ARRAY_SIZE(apq8084_groups),
+ .ngpios = NUM_GPIO_PINGROUPS,
+};
+
+static int apq8084_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &apq8084_pinctrl);
+}
+
+static const struct of_device_id apq8084_pinctrl_of_match[] = {
+ { .compatible = "qcom,apq8084-pinctrl", },
+ { },
+};
+
+static struct platform_driver apq8084_pinctrl_driver = {
+ .driver = {
+ .name = "apq8084-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = apq8084_pinctrl_of_match,
+ },
+ .probe = apq8084_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init apq8084_pinctrl_init(void)
+{
+ return platform_driver_register(&apq8084_pinctrl_driver);
+}
+arch_initcall(apq8084_pinctrl_init);
+
+static void __exit apq8084_pinctrl_exit(void)
+{
+ platform_driver_unregister(&apq8084_pinctrl_driver);
+}
+module_exit(apq8084_pinctrl_exit);
+
+MODULE_DESCRIPTION("Qualcomm APQ8084 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, apq8084_pinctrl_of_match);
.intr_status_bit = 0, \
.intr_ack_high = 1, \
.intr_target_bit = 0, \
+ .intr_target_kpss_val = 4, \
.intr_raw_status_bit = 3, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \
* GNU General Public License for more details.
*/
+#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
+#include <linux/reboot.h>
#include "../core.h"
#include "../pinconf.h"
#include "../pinctrl-utils.h"
#define MAX_NR_GPIO 300
+#define PS_HOLD_OFFSET 0x820
/**
* struct msm_pinctrl - state for a pinctrl-msm device
* @dev: device handle.
* @pctrl: pinctrl handle.
* @chip: gpiochip handle.
+ * @restart_nb: restart notifier block.
* @irq: parent irq for the TLMM irq_chip.
* @lock: Spinlock to protect register resources as well
* as msm_pinctrl data structures.
struct device *dev;
struct pinctrl_dev *pctrl;
struct gpio_chip chip;
+ struct notifier_block restart_nb;
int irq;
spinlock_t lock;
return 0;
}
-static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
- unsigned function,
- unsigned group)
+static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
+ unsigned function,
+ unsigned group)
{
struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct msm_pingroup *g;
.get_functions_count = msm_get_functions_count,
.get_function_name = msm_get_function_name,
.get_function_groups = msm_get_function_groups,
- .enable = msm_pinmux_enable,
+ .set_mux = msm_pinmux_set_mux,
};
static int msm_config_reg(struct msm_pinctrl *pctrl,
spin_unlock_irqrestore(&pctrl->lock, flags);
}
-#define INTR_TARGET_PROC_APPS 4
-
static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
/* Route interrupts to application cpu */
val = readl(pctrl->regs + g->intr_target_reg);
val &= ~(7 << g->intr_target_bit);
- val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
+ val |= g->intr_target_kpss_val << g->intr_target_bit;
writel(val, pctrl->regs + g->intr_target_reg);
/* Update configuration for gpio.
ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
if (ret) {
dev_err(pctrl->dev, "Failed to add pin range\n");
+ gpiochip_remove(&pctrl->chip);
return ret;
}
IRQ_TYPE_NONE);
if (ret) {
dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
+ gpiochip_remove(&pctrl->chip);
return -ENOSYS;
}
return 0;
}
+static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
+ void *data)
+{
+ struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
+
+ writel(0, pctrl->regs + PS_HOLD_OFFSET);
+ mdelay(1000);
+ return NOTIFY_DONE;
+}
+
+static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
+{
+ int i = 0;
+ const struct msm_function *func = pctrl->soc->functions;
+
+ for (; i <= pctrl->soc->nfunctions; i++)
+ if (!strcmp(func[i].name, "ps_hold")) {
+ pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
+ pctrl->restart_nb.priority = 128;
+ if (register_restart_handler(&pctrl->restart_nb))
+ dev_err(pctrl->dev,
+ "failed to setup restart handler.\n");
+ break;
+ }
+}
+
int msm_pinctrl_probe(struct platform_device *pdev,
const struct msm_pinctrl_soc_data *soc_data)
{
if (IS_ERR(pctrl->regs))
return PTR_ERR(pctrl->regs);
+ msm_pinctrl_setup_pm_reset(pctrl);
+
pctrl->irq = platform_get_irq(pdev, 0);
if (pctrl->irq < 0) {
dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
pinctrl_unregister(pctrl->pctrl);
+ unregister_restart_handler(&pctrl->restart_nb);
+
return 0;
}
EXPORT_SYMBOL(msm_pinctrl_remove);
* @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
* status.
* @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
+ * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
+ * this gpio should get routed to the KPSS processor.
* @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
* @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
* @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
unsigned intr_ack_high:1;
unsigned intr_target_bit:5;
+ unsigned intr_target_kpss_val:5;
unsigned intr_raw_status_bit:5;
unsigned intr_polarity_bit:5;
unsigned intr_detection_bit:5;
.intr_status_bit = 0, \
.intr_ack_high = 1, \
.intr_target_bit = 0, \
+ .intr_target_kpss_val = 4, \
.intr_raw_status_bit = 3, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_target_bit = 5, \
+ .intr_target_kpss_val = 4, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \
}
/* enable a specified pinmux by writing to registers */
-static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
- unsigned group)
+static int exynos5440_pinmux_set_mux(struct pinctrl_dev *pctldev,
+ unsigned selector,
+ unsigned group)
{
exynos5440_pinmux_setup(pctldev, selector, group, true);
return 0;
.get_functions_count = exynos5440_get_functions_count,
.get_function_name = exynos5440_pinmux_get_fname,
.get_function_groups = exynos5440_pinmux_get_groups,
- .enable = exynos5440_pinmux_enable,
+ .set_mux = exynos5440_pinmux_set_mux,
.gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
};
}
/* enable a specified pinmux by writing to registers */
-static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
- unsigned group)
+static int samsung_pinmux_set_mux(struct pinctrl_dev *pctldev,
+ unsigned selector,
+ unsigned group)
{
samsung_pinmux_setup(pctldev, selector, group, true);
return 0;
.get_functions_count = samsung_get_functions_count,
.get_function_name = samsung_pinmux_get_fname,
.get_function_groups = samsung_pinmux_get_groups,
- .enable = samsung_pinmux_enable,
+ .set_mux = samsung_pinmux_set_mux,
};
/* set or get the pin config settings for a specified pin */
*/
ret = sh_pfc_register_pinctrl(pfc);
if (unlikely(ret != 0))
- goto error;
+ return ret;
#ifdef CONFIG_GPIO_SH_PFC
/*
dev_info(pfc->dev, "%s support registered\n", info->name);
return 0;
-
-error:
- if (info->ops && info->ops->exit)
- info->ops->exit(pfc);
- return ret;
}
static int sh_pfc_remove(struct platform_device *pdev)
#endif
sh_pfc_unregister_pinctrl(pfc);
- if (pfc->info->ops && pfc->info->ops->exit)
- pfc->info->ops->exit(pfc);
-
return 0;
}
struct sh_pfc {
struct device *dev;
const struct sh_pfc_soc_info *info;
- void *soc_data;
spinlock_t lock;
unsigned int num_windows;
iowrite8(value, addr);
}
-static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
+static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
.get_bias = r8a73a4_pinmux_get_bias,
.set_bias = r8a73a4_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
.name = "r8a73a4_pfc",
- .ops = &r8a73a4_pinmux_ops,
+ .ops = &r8a73a4_pfc_ops,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
iowrite8(value, addr);
}
-static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
+static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
.get_bias = r8a7740_pinmux_get_bias,
.set_bias = r8a7740_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a7740_pinmux_info = {
.name = "r8a7740_pfc",
- .ops = &r8a7740_pinmux_ops,
+ .ops = &r8a7740_pfc_ops,
.input = { PINMUX_INPUT_BEGIN,
PINMUX_INPUT_END },
iowrite8(value, addr);
}
-static const struct sh_pfc_soc_operations sh7372_pinmux_ops = {
+static const struct sh_pfc_soc_operations sh7372_pfc_ops = {
.get_bias = sh7372_pinmux_get_bias,
.set_bias = sh7372_pinmux_set_bias,
};
const struct sh_pfc_soc_info sh7372_pinmux_info = {
.name = "sh7372_pfc",
- .ops = &sh7372_pinmux_ops,
+ .ops = &sh7372_pfc_ops,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
* SoC information
*/
-struct sh73a0_pinmux_data {
- struct regulator_dev *vccq_mc0;
-};
-
static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
{
- struct sh73a0_pinmux_data *data;
struct regulator_config cfg = { };
+ struct regulator_dev *vccq;
int ret;
- data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
- if (data == NULL)
- return -ENOMEM;
-
cfg.dev = pfc->dev;
cfg.init_data = &sh73a0_vccq_mc0_init_data;
cfg.driver_data = pfc;
- data->vccq_mc0 = devm_regulator_register(pfc->dev,
- &sh73a0_vccq_mc0_desc, &cfg);
- if (IS_ERR(data->vccq_mc0)) {
- ret = PTR_ERR(data->vccq_mc0);
+ vccq = devm_regulator_register(pfc->dev, &sh73a0_vccq_mc0_desc, &cfg);
+ if (IS_ERR(vccq)) {
+ ret = PTR_ERR(vccq);
dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
ret);
return ret;
}
- pfc->soc_data = data;
-
return 0;
}
-static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
+static const struct sh_pfc_soc_operations sh73a0_pfc_ops = {
.init = sh73a0_pinmux_soc_init,
.get_bias = sh73a0_pinmux_get_bias,
.set_bias = sh73a0_pinmux_set_bias,
const struct sh_pfc_soc_info sh73a0_pinmux_info = {
.name = "sh73a0_pfc",
- .ops = &sh73a0_pinmux_ops,
+ .ops = &sh73a0_pfc_ops,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
return 0;
}
-static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
- unsigned group)
+static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
.get_functions_count = sh_pfc_get_functions_count,
.get_function_name = sh_pfc_get_function_name,
.get_function_groups = sh_pfc_get_function_groups,
- .enable = sh_pfc_func_enable,
+ .set_mux = sh_pfc_func_set_mux,
.gpio_request_enable = sh_pfc_gpio_request_enable,
.gpio_disable_free = sh_pfc_gpio_disable_free,
.gpio_set_direction = sh_pfc_gpio_set_direction,
struct sh_pfc_soc_operations {
int (*init)(struct sh_pfc *pfc);
- void (*exit)(struct sh_pfc *pfc);
unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias);
.mask = BIT(30) | BIT(31),
}, {
.group = 2,
- .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
- BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
+ .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
+ BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
+ BIT(16) | BIT(17) | BIT(18) | BIT(19) |
BIT(20) | BIT(21) | BIT(22) | BIT(31),
},
};
.funcval = 0,
};
-static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
- 84, 85, 86, 95 };
+static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75,
+ 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
{
.group = 2,
- .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
- BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
+ .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
+ BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
+ BIT(16) | BIT(17) | BIT(18) | BIT(19) |
BIT(20) | BIT(21) | BIT(22) | BIT(31),
}, {
.group = 1,
.funcval = 0,
};
-static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
- 84, 85, 86, 95 };
+static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73,
+ 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
{
.group = 2,
- .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
- BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
+ .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
+ BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
+ BIT(16) | BIT(17) | BIT(18) | BIT(19) |
BIT(20) | BIT(21) | BIT(22) | BIT(31),
}, {
.group = 1,
.mask = BIT(30) | BIT(31),
}, {
.group = 0,
- .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
+ .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
+ BIT(21) | BIT(22) | BIT(23),
},
};
.funcval = 0,
};
-static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79,
- 80, 81, 82, 83, 84, 85, 86, 95};
+static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62,
+ 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84,
+ 85, 86, 95};
static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
{
.group = 2,
- .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
- BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
+ .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) |
+ BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT(16) |
+ BIT(17) | BIT(18) | BIT(19) |
BIT(20) | BIT(21) | BIT(22) | BIT(31),
}, {
.group = 1,
.funcval = BIT(4),
};
-static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
- 84, 85, 86, 95};
+static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75,
+ 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95};
static const struct sirfsoc_muxmask uart0_muxmask[] = {
{
static const unsigned cko1_pins[] = { 42 };
-static const struct sirfsoc_muxmask i2s_muxmask[] = {
+static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
{
.group = 1,
.mask = BIT(10),
- }, {
+ },
+};
+
+static const struct sirfsoc_padmux i2s_mclk_padmux = {
+ .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
+ .muxmask = i2s_mclk_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
+ .funcmask = BIT(3),
+ .funcval = BIT(3),
+};
+
+static const unsigned i2s_mclk_pins[] = { 42 };
+
+static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(19),
+ },
+};
+
+static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
+ .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
+ .muxmask = i2s_ext_clk_input_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
+ .funcmask = BIT(2),
+ .funcval = BIT(2),
+};
+
+static const unsigned i2s_ext_clk_input_pins[] = { 51 };
+
+static const struct sirfsoc_muxmask i2s_muxmask[] = {
+ {
.group = 3,
.mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
},
.muxmask_counts = ARRAY_SIZE(i2s_muxmask),
.muxmask = i2s_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(3),
- .funcval = BIT(3),
};
-static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 };
+static const unsigned i2s_pins[] = { 98, 99, 100, 101 };
static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
{
- .group = 1,
- .mask = BIT(10),
- }, {
.group = 3,
.mask = BIT(2) | BIT(3) | BIT(4),
},
.muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
.muxmask = i2s_no_din_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(3),
- .funcval = BIT(3),
};
-static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 };
+static const unsigned i2s_no_din_pins[] = { 98, 99, 100 };
static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
{
- .group = 1,
- .mask = BIT(10) | BIT(20) | BIT(23),
- }, {
.group = 3,
.mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
},
.muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
.muxmask = i2s_6chn_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(1) | BIT(3) | BIT(9),
- .funcval = BIT(1) | BIT(3) | BIT(9),
+ .funcmask = BIT(1) | BIT(9),
+ .funcval = BIT(1) | BIT(9),
};
-static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 };
+static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 };
static const struct sirfsoc_muxmask ac97_muxmask[] = {
{
.funcval = BIT(18),
};
-static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, 60, 61 };
+static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59,
+ 60, 61 };
static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
{
.funcval = BIT(15),
};
-static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 87, 88, 89 };
+static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
+ 87, 88, 89 };
static const struct sirfsoc_muxmask i2c0_muxmask[] = {
{
.funcval = 0,
};
-static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, 41, 56, 57, 58, 59, 60, 61 };
+static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40,
+ 41, 56, 57, 58, 59, 60, 61 };
static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
{
SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
+ SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
+ SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
-static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
+static const char * const
+ uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
static const char * const pulse_countgrp[] = { "pulse_countgrp" };
+static const char * const i2smclkgrp[] = { "i2smclkgrp" };
+static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
static const char * const i2sgrp[] = { "i2sgrp" };
static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
uart0_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
- SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
+ SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
+ uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
usp0_uart_nostreamctrl_grp,
SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
- SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
- SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
- SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
+ SIRFSOC_PMX_FUNCTION("sdmmc2_nowp",
+ sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
+ SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus",
+ usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
+ SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
+ usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
- SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
+ SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
+ uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
+ SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
+ SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
+ i2s_ext_clk_input_padmux),
SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
{
.group = 3,
- .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
- BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
+ .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
+ BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
+ BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(17) | BIT(18),
}, {
.group = 2,
.funcval = 0,
};
-static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
- 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
+static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102,
+ 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
{
.group = 3,
- .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
- BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
+ .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
+ BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
+ BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(17) | BIT(18),
}, {
.group = 2,
.funcval = 0,
};
-static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
- 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
+static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100,
+ 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
{
.group = 3,
- .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
- BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
+ .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
+ BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
+ BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(17) | BIT(18),
}, {
.group = 2,
.mask = BIT(31),
}, {
.group = 0,
- .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
+ .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
+ BIT(21) | BIT(22) | BIT(23),
},
};
.funcval = 0,
};
-static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
- 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
+static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
+ 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
+ 110, 111, 112, 113, 114 };
static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
{
.group = 3,
- .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
- BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
+ .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
+ BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
+ BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(17) | BIT(18),
}, {
.group = 2,
.funcval = BIT(4),
};
-static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
- 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
+static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102,
+ 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
static const struct sirfsoc_muxmask uart0_muxmask[] = {
{
static const unsigned cko1_pins[] = { 42 };
+static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(10),
+ },
+};
+
+static const struct sirfsoc_padmux i2s_mclk_padmux = {
+ .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
+ .muxmask = i2s_mclk_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
+ .funcmask = BIT(3),
+ .funcval = BIT(3),
+};
+
+static const unsigned i2s_mclk_pins[] = { 42 };
+
+static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(19),
+ },
+};
+
+static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
+ .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
+ .muxmask = i2s_ext_clk_input_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
+ .funcmask = BIT(2),
+ .funcval = BIT(2),
+};
+
+static const unsigned i2s_ext_clk_input_pins[] = { 51 };
+
static const struct sirfsoc_muxmask i2s_muxmask[] = {
{
.group = 1,
- .mask =
- BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19)
- | BIT(23) | BIT(28),
+ .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
},
};
.muxmask_counts = ARRAY_SIZE(i2s_muxmask),
.muxmask = i2s_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
- .funcmask = BIT(3) | BIT(9),
- .funcval = BIT(3),
};
-static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 };
+static const unsigned i2s_pins[] = { 43, 44, 45, 46 };
+
+static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(11) | BIT(12) | BIT(14),
+ },
+};
+
+static const struct sirfsoc_padmux i2s_no_din_padmux = {
+ .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
+ .muxmask = i2s_no_din_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
+};
+
+static const unsigned i2s_no_din_pins[] = { 43, 44, 46 };
+
+static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14)
+ | BIT(23) | BIT(28),
+ },
+};
+
+static const struct sirfsoc_padmux i2s_6chn_padmux = {
+ .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
+ .muxmask = i2s_6chn_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
+ .funcmask = BIT(1) | BIT(9),
+ .funcval = BIT(1) | BIT(9),
+};
+
+static const unsigned i2s_6chn_pins[] = { 43, 44, 45, 46, 55, 60 };
static const struct sirfsoc_muxmask ac97_muxmask[] = {
{
.funcval = 0,
};
-static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
+static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87,
+ 88, 89 };
static const struct sirfsoc_muxmask i2c0_muxmask[] = {
{
.funcval = BIT(0),
};
-static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
+static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86,
+ 87, 88, 89 };
static const struct sirfsoc_muxmask pwm0_muxmask[] = {
{
SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
+ SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
+ SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
+ SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
+ SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
static const char * const uart2grp[] = { "uart2grp" };
static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
static const char * const usp0grp[] = { "usp0grp" };
-static const char * const usp0_uart_nostreamctrl_grp[] =
- { "usp0_uart_nostreamctrl_grp" };
+static const char * const usp0_uart_nostreamctrl_grp[] = {
+ "usp0_uart_nostreamctrl_grp"
+};
static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
static const char * const usp1grp[] = { "usp1grp" };
-static const char * const usp1_uart_nostreamctrl_grp[] =
- { "usp1_uart_nostreamctrl_grp" };
+static const char * const usp1_uart_nostreamctrl_grp[] = {
+ "usp1_uart_nostreamctrl_grp"
+};
static const char * const usp2grp[] = { "usp2grp" };
-static const char * const usp2_uart_nostreamctrl_grp[] =
- { "usp2_uart_nostreamctrl_grp" };
+static const char * const usp2_uart_nostreamctrl_grp[] = {
+ "usp2_uart_nostreamctrl_grp"
+};
static const char * const i2c0grp[] = { "i2c0grp" };
static const char * const i2c1grp[] = { "i2c1grp" };
static const char * const pwm0grp[] = { "pwm0grp" };
static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
-static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
+static const char * const
+ uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
static const char * const pulse_countgrp[] = { "pulse_countgrp" };
+static const char * const i2smclkgrp[] = { "i2smclkgrp" };
+static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
static const char * const i2sgrp[] = { "i2sgrp" };
+static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
+static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
static const char * const ac97grp[] = { "ac97grp" };
static const char * const nandgrp[] = { "nandgrp" };
static const char * const spi0grp[] = { "spi0grp" };
SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
- SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
+ SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl",
+ uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
- SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
+ SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
+ uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
- SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, usp0_only_utfs_padmux),
- SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, usp0_only_urfs_padmux),
+ SIRFSOC_PMX_FUNCTION("usp0_only_utfs",
+ usp0_only_utfs_grp, usp0_only_utfs_padmux),
+ SIRFSOC_PMX_FUNCTION("usp0_only_urfs",
+ usp0_only_urfs_grp, usp0_only_urfs_padmux),
SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
- SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
- SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
+ SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus",
+ usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
+ SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
+ usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
- SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
+ SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
+ uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
+ SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
+ SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
+ i2s_ext_clk_input_padmux),
SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
+ SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
+ SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
return sirfsoc_pin_groups[selector].name;
}
-static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
- const unsigned **pins,
- unsigned *num_pins)
+static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned selector,
+ const unsigned **pins,
+ unsigned *num_pins)
{
*pins = sirfsoc_pin_groups[selector].pins;
*num_pins = sirfsoc_pin_groups[selector].num_pins;
return 0;
}
-static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
- unsigned offset)
+static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned offset)
{
seq_printf(s, " " DRIVER_NAME);
}
static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
static int sirfsoc_pmxfunc_cnt;
-static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
- bool enable)
+static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
+ unsigned selector, bool enable)
{
int i;
- const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
+ const struct sirfsoc_padmux *mux =
+ sirfsoc_pmx_functions[selector].padmux;
const struct sirfsoc_muxmask *mask = mux->muxmask;
for (i = 0; i < mux->muxmask_counts; i++) {
u32 muxval;
if (!spmx->is_marco) {
- muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
+ muxval = readl(spmx->gpio_virtbase +
+ SIRFSOC_GPIO_PAD_EN(mask[i].group));
if (enable)
muxval = muxval & ~mask[i].mask;
else
muxval = muxval | mask[i].mask;
- writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
+ writel(muxval, spmx->gpio_virtbase +
+ SIRFSOC_GPIO_PAD_EN(mask[i].group));
} else {
if (enable)
writel(mask[i].mask, spmx->gpio_virtbase +
}
}
-static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
- unsigned group)
+static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev,
+ unsigned selector,
+ unsigned group)
{
struct sirfsoc_pmx *spmx;
return sirfsoc_pmx_functions[selector].name;
}
-static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
- const char * const **groups,
- unsigned * const num_groups)
+static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev,
+ unsigned selector,
+ const char * const **groups,
+ unsigned * const num_groups)
{
*groups = sirfsoc_pmx_functions[selector].groups;
*num_groups = sirfsoc_pmx_functions[selector].num_groups;
spmx = pinctrl_dev_get_drvdata(pmxdev);
if (!spmx->is_marco) {
- muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
+ muxval = readl(spmx->gpio_virtbase +
+ SIRFSOC_GPIO_PAD_EN(group));
muxval = muxval | (1 << (offset - range->pin_base));
- writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
+ writel(muxval, spmx->gpio_virtbase +
+ SIRFSOC_GPIO_PAD_EN(group));
} else {
writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
SIRFSOC_GPIO_PAD_EN(group));
}
static struct pinmux_ops sirfsoc_pinmux_ops = {
- .enable = sirfsoc_pinmux_enable,
+ .set_mux = sirfsoc_pinmux_set_mux,
.get_functions_count = sirfsoc_pinmux_get_funcs_count,
.get_function_name = sirfsoc_pinmux_get_func_name,
.get_function_groups = sirfsoc_pinmux_get_groups,
case IRQ_TYPE_NONE:
break;
case IRQ_TYPE_EDGE_RISING:
- val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
+ val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
+ SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
break;
case IRQ_TYPE_EDGE_FALLING:
val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
- val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
+ val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
+ SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
break;
case IRQ_TYPE_EDGE_BOTH:
- val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
- SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
+ val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
+ SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
+ SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
break;
case IRQ_TYPE_LEVEL_LOW:
- val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
+ val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
+ SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
break;
case IRQ_TYPE_LEVEL_HIGH:
val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
- val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
+ val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
+ SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
break;
}
spin_unlock_irqrestore(&bank->lock, flags);
}
-static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
+static int sirfsoc_gpio_direction_output(struct gpio_chip *chip,
+ unsigned gpio, int value)
{
struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
if (err) {
dev_err(&pdev->dev,
"could not connect irqchip to gpiochip\n");
- goto out;
+ goto out_banks;
}
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
}
subsys_initcall(sirfsoc_gpio_init);
-MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
- "Yuping Luo <yuping.luo@csr.com>, "
- "Barry Song <baohua.song@csr.com>");
+MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>");
+MODULE_AUTHOR("Yuping Luo <yuping.luo@csr.com>");
+MODULE_AUTHOR("Barry Song <baohua.song@csr.com>");
MODULE_DESCRIPTION("SIRFSOC pin control driver");
MODULE_LICENSE("GPL");
return 0;
}
-static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
+static int spear_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned function,
unsigned group)
{
return spear_pinctrl_endisable(pctldev, function, group, true);
.get_functions_count = spear_pinctrl_get_funcs_count,
.get_function_name = spear_pinctrl_get_func_name,
.get_function_groups = spear_pinctrl_get_func_groups,
- .enable = spear_pinctrl_enable,
+ .set_mux = spear_pinctrl_set_mux,
.gpio_request_enable = gpio_request_enable,
.gpio_disable_free = gpio_disable_free,
};
.modes_supported = false,
};
-static struct of_device_id spear1310_pinctrl_of_match[] = {
+static const struct of_device_id spear1310_pinctrl_of_match[] = {
{
.compatible = "st,spear1310-pinmux",
},
.modes_supported = false,
};
-static struct of_device_id spear1340_pinctrl_of_match[] = {
+static const struct of_device_id spear1340_pinctrl_of_match[] = {
{
.compatible = "st,spear1340-pinmux",
},
&gpio1_function,
};
-static struct of_device_id spear300_pinctrl_of_match[] = {
+static const struct of_device_id spear300_pinctrl_of_match[] = {
{
.compatible = "st,spear300-pinmux",
},
&tdm_function,
};
-static struct of_device_id spear310_pinctrl_of_match[] = {
+static const struct of_device_id spear310_pinctrl_of_match[] = {
{
.compatible = "st,spear310-pinmux",
},
&i2c2_function,
};
-static struct of_device_id spear320_pinctrl_of_match[] = {
+static const struct of_device_id spear320_pinctrl_of_match[] = {
{
.compatible = "st,spear320-pinmux",
},
spin_unlock_irqrestore(&pctl->lock, flags);
}
-static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
- unsigned function,
- unsigned group)
+static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
+ unsigned function,
+ unsigned group)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sunxi_pinctrl_group *g = pctl->groups + group;
.get_functions_count = sunxi_pmx_get_funcs_cnt,
.get_function_name = sunxi_pmx_get_func_name,
.get_function_groups = sunxi_pmx_get_func_groups,
- .enable = sunxi_pmx_enable,
+ .set_mux = sunxi_pmx_set_mux,
.gpio_set_direction = sunxi_pmx_gpio_set_direction,
};
return 0;
}
-static int wmt_pmx_enable(struct pinctrl_dev *pctldev,
- unsigned func_selector,
- unsigned group_selector)
+static int wmt_pmx_set_mux(struct pinctrl_dev *pctldev,
+ unsigned func_selector,
+ unsigned group_selector)
{
struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
u32 pinnum = data->pins[group_selector].number;
.get_functions_count = wmt_pmx_get_functions_count,
.get_function_name = wmt_pmx_get_function_name,
.get_function_groups = wmt_pmx_get_function_groups,
- .enable = wmt_pmx_enable,
+ .set_mux = wmt_pmx_set_mux,
.gpio_disable_free = wmt_pmx_gpio_disable_free,
.gpio_set_direction = wmt_pmx_gpio_set_direction,
};
if (event_dev->priv_flags & IFF_802_1Q_VLAN)
event_dev = vlan_dev_real_dev(event_dev);
- cdev = cxgbi_device_find_by_netdev(event_dev, NULL);
+ cdev = cxgbi_device_find_by_netdev_rcu(event_dev, NULL);
if (!cdev)
return ret;
static LIST_HEAD(cdev_list);
static DEFINE_MUTEX(cdev_mutex);
+static LIST_HEAD(cdev_rcu_list);
+static DEFINE_SPINLOCK(cdev_rcu_lock);
+
int cxgbi_device_portmap_create(struct cxgbi_device *cdev, unsigned int base,
unsigned int max_conn)
{
list_add_tail(&cdev->list_head, &cdev_list);
mutex_unlock(&cdev_mutex);
+ spin_lock(&cdev_rcu_lock);
+ list_add_tail_rcu(&cdev->rcu_node, &cdev_rcu_list);
+ spin_unlock(&cdev_rcu_lock);
+
log_debug(1 << CXGBI_DBG_DEV,
"cdev 0x%p, p# %u.\n", cdev, nports);
return cdev;
log_debug(1 << CXGBI_DBG_DEV,
"cdev 0x%p, p# %u,%s.\n",
cdev, cdev->nports, cdev->nports ? cdev->ports[0]->name : "");
+
mutex_lock(&cdev_mutex);
list_del(&cdev->list_head);
mutex_unlock(&cdev_mutex);
+
+ spin_lock(&cdev_rcu_lock);
+ list_del_rcu(&cdev->rcu_node);
+ spin_unlock(&cdev_rcu_lock);
+ synchronize_rcu();
+
cxgbi_device_destroy(cdev);
}
EXPORT_SYMBOL_GPL(cxgbi_device_unregister);
mutex_lock(&cdev_mutex);
list_for_each_entry_safe(cdev, tmp, &cdev_list, list_head) {
if ((cdev->flags & flag) == flag) {
- log_debug(1 << CXGBI_DBG_DEV,
- "cdev 0x%p, p# %u,%s.\n",
- cdev, cdev->nports, cdev->nports ?
- cdev->ports[0]->name : "");
- list_del(&cdev->list_head);
- cxgbi_device_destroy(cdev);
+ mutex_unlock(&cdev_mutex);
+ cxgbi_device_unregister(cdev);
+ mutex_lock(&cdev_mutex);
}
}
mutex_unlock(&cdev_mutex);
}
}
mutex_unlock(&cdev_mutex);
+
log_debug(1 << CXGBI_DBG_DEV,
"lldev 0x%p, NO match found.\n", lldev);
return NULL;
}
EXPORT_SYMBOL_GPL(cxgbi_device_find_by_netdev);
+struct cxgbi_device *cxgbi_device_find_by_netdev_rcu(struct net_device *ndev,
+ int *port)
+{
+ struct net_device *vdev = NULL;
+ struct cxgbi_device *cdev;
+ int i;
+
+ if (ndev->priv_flags & IFF_802_1Q_VLAN) {
+ vdev = ndev;
+ ndev = vlan_dev_real_dev(ndev);
+ pr_info("vlan dev %s -> %s.\n", vdev->name, ndev->name);
+ }
+
+ rcu_read_lock();
+ list_for_each_entry_rcu(cdev, &cdev_rcu_list, rcu_node) {
+ for (i = 0; i < cdev->nports; i++) {
+ if (ndev == cdev->ports[i]) {
+ cdev->hbas[i]->vdev = vdev;
+ rcu_read_unlock();
+ if (port)
+ *port = i;
+ return cdev;
+ }
+ }
+ }
+ rcu_read_unlock();
+
+ log_debug(1 << CXGBI_DBG_DEV,
+ "ndev 0x%p, %s, NO match found.\n", ndev, ndev->name);
+ return NULL;
+}
+EXPORT_SYMBOL_GPL(cxgbi_device_find_by_netdev_rcu);
+
static struct cxgbi_device *cxgbi_device_find_by_mac(struct net_device *ndev,
int *port)
{
#define CXGBI_FLAG_IPV4_SET 0x10
struct cxgbi_device {
struct list_head list_head;
+ struct list_head rcu_node;
unsigned int flags;
struct net_device **ports;
void *lldev;
void cxgbi_device_unregister_all(unsigned int flag);
struct cxgbi_device *cxgbi_device_find_by_lldev(void *);
struct cxgbi_device *cxgbi_device_find_by_netdev(struct net_device *, int *);
+struct cxgbi_device *cxgbi_device_find_by_netdev_rcu(struct net_device *,
+ int *);
int cxgbi_hbas_add(struct cxgbi_device *, u64, unsigned int,
struct scsi_host_template *,
struct scsi_transport_template *);
#ifdef CONFIG_SERIAL_8250_RSA
__module_param_call(MODULE_PARAM_PREFIX, probe_rsa,
¶m_array_ops, .arr = &__param_arr_probe_rsa,
- 0444, -1);
+ 0444, -1, 0);
#endif
}
#else
.cmd_per_lun = 1, /* until we override it */
.skip_settle_delay = 1,
.ordered_tag = 1,
+
+ /*
+ * The uas drivers expects tags not to be bigger than the maximum
+ * per-device queue depth, which is not true with the blk-mq tag
+ * allocator.
+ */
+ .disable_blk_mq = true,
};
#define UNUSUAL_DEV(id_vendor, id_product, bcdDeviceMin, bcdDeviceMax, \
lru_cache_add_file(page);
unlock_page(page);
page_cache_release(page);
- if (rc == -EAGAIN)
- list_add_tail(&page->lru, &tmplist);
}
+ /* Fallback to the readpage in error/reconnect cases */
kref_put(&rdata->refcount, cifs_readdata_release);
- if (rc == -EAGAIN) {
- /* Re-add pages to the page_list and retry */
- list_splice(&tmplist, page_list);
- continue;
- }
break;
}
tmprc = CIFS_open(xid, &oparms, &oplock, NULL);
if (tmprc == -EOPNOTSUPP)
*symlink = true;
- else
+ else if (tmprc == 0)
CIFSSMBClose(xid, tcon, fid.netfid);
}
{STATUS_DLL_MIGHT_BE_INCOMPATIBLE, -EIO,
"STATUS_DLL_MIGHT_BE_INCOMPATIBLE"},
{STATUS_STOPPED_ON_SYMLINK, -EOPNOTSUPP, "STATUS_STOPPED_ON_SYMLINK"},
+ {STATUS_IO_REPARSE_TAG_NOT_HANDLED, -EOPNOTSUPP,
+ "STATUS_REPARSE_NOT_HANDLED"},
{STATUS_DEVICE_REQUIRES_CLEANING, -EIO,
"STATUS_DEVICE_REQUIRES_CLEANING"},
{STATUS_DEVICE_DOOR_OPEN, -EIO, "STATUS_DEVICE_DOOR_OPEN"},
buf->page_len = maxcount;
buf->len += maxcount;
- xdr->page_ptr += (maxcount + PAGE_SIZE - 1) / PAGE_SIZE;
+ xdr->page_ptr += (buf->page_base + maxcount + PAGE_SIZE - 1)
+ / PAGE_SIZE;
/* Use rest of head for padding and remaining ops: */
buf->tail[0].iov_base = xdr->p;
"and killing the other node now! This node is OK and can continue.\n");
__dlm_print_one_lock_resource(res);
spin_unlock(&res->spinlock);
+ spin_lock(&dlm->master_lock);
+ if (mle)
+ __dlm_put_mle(mle);
+ spin_unlock(&dlm->master_lock);
spin_unlock(&dlm->spinlock);
*ret_data = (void *)res;
dlm_put(dlm);
#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
+#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
+
#define AT91_PIOA 0
#define AT91_PIOB 1
#define AT91_PIOC 2
#define RK_FUNC_GPIO 0
#define RK_FUNC_1 1
#define RK_FUNC_2 2
+#define RK_FUNC_3 3
+#define RK_FUNC_4 4
#endif
}
#endif
-#ifdef CONFIG_NET_DMA
-#define net_dmaengine_get() dmaengine_get()
-#define net_dmaengine_put() dmaengine_put()
-#else
-static inline void net_dmaengine_get(void)
-{
-}
-static inline void net_dmaengine_put(void)
-{
-}
-#endif
-
#ifdef CONFIG_ASYNC_TX_DMA
#define async_dmaengine_get() dmaengine_get()
#define async_dmaengine_put() dmaengine_put()
return NULL;
}
#endif /* CONFIG_ASYNC_TX_DMA */
-
-dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
- void *dest, void *src, size_t len);
-dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
- struct page *page, unsigned int offset, void *kdata, size_t len);
-dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
- struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
- unsigned int src_off, size_t len);
void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
- struct dma_chan *chan);
+ struct dma_chan *chan);
static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
{
* NOARG - the parameter allows for no argument (foo instead of foo=1)
*/
enum {
- KERNEL_PARAM_FL_NOARG = (1 << 0)
+ KERNEL_PARAM_OPS_FL_NOARG = (1 << 0)
};
struct kernel_param_ops {
void (*free)(void *arg);
};
+/*
+ * Flags available for kernel_param
+ *
+ * UNSAFE - the parameter is dangerous and setting it will taint the kernel
+ */
+enum {
+ KERNEL_PARAM_FL_UNSAFE = (1 << 0)
+};
+
struct kernel_param {
const char *name;
const struct kernel_param_ops *ops;
u16 perm;
- s16 level;
+ s8 level;
+ u8 flags;
union {
void *arg;
const struct kparam_string *str;
#define module_param(name, type, perm) \
module_param_named(name, name, type, perm)
+/**
+ * module_param_unsafe - same as module_param but taints kernel
+ */
+#define module_param_unsafe(name, type, perm) \
+ module_param_named_unsafe(name, name, type, perm)
+
/**
* module_param_named - typesafe helper for a renamed module/cmdline parameter
* @name: a valid C identifier which is the parameter name.
module_param_cb(name, ¶m_ops_##type, &value, perm); \
__MODULE_PARM_TYPE(name, #type)
+/**
+ * module_param_named_unsafe - same as module_param_named but taints kernel
+ */
+#define module_param_named_unsafe(name, value, type, perm) \
+ param_check_##type(name, &(value)); \
+ module_param_cb_unsafe(name, ¶m_ops_##type, &value, perm); \
+ __MODULE_PARM_TYPE(name, #type)
+
/**
* module_param_cb - general callback for a module/cmdline parameter
* @name: a valid C identifier which is the parameter name.
* The ops can have NULL set or get functions.
*/
#define module_param_cb(name, ops, arg, perm) \
- __module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, -1)
+ __module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, -1, 0)
+
+#define module_param_cb_unsafe(name, ops, arg, perm) \
+ __module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, -1, \
+ KERNEL_PARAM_FL_UNSAFE)
/**
* <level>_param_cb - general callback for a module/cmdline parameter
* The ops can have NULL set or get functions.
*/
#define __level_param_cb(name, ops, arg, perm, level) \
- __module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, level)
+ __module_param_call(MODULE_PARAM_PREFIX, name, ops, arg, perm, level, 0)
#define core_param_cb(name, ops, arg, perm) \
__level_param_cb(name, ops, arg, perm, 1)
/* This is the fundamental function for registering boot/module
parameters. */
-#define __module_param_call(prefix, name, ops, arg, perm, level) \
+#define __module_param_call(prefix, name, ops, arg, perm, level, flags) \
/* Default value instead of permissions? */ \
static const char __param_str_##name[] = prefix #name; \
static struct kernel_param __moduleparam_const __param_##name \
__used \
__attribute__ ((unused,__section__ ("__param"),aligned(sizeof(void *)))) \
= { __param_str_##name, ops, VERIFY_OCTAL_PERMISSIONS(perm), \
- level, { arg } }
+ level, flags, { arg } }
/* Obsolete - use module_param_cb() */
#define module_param_call(name, set, get, arg, perm) \
static struct kernel_param_ops __param_ops_##name = \
- { 0, (void *)set, (void *)get }; \
+ { .flags = 0, (void *)set, (void *)get }; \
__module_param_call(MODULE_PARAM_PREFIX, \
name, &__param_ops_##name, arg, \
- (perm) + sizeof(__check_old_set_param(set))*0, -1)
+ (perm) + sizeof(__check_old_set_param(set))*0, -1, 0)
/* We don't get oldget: it's often a new-style param_get_uint, etc. */
static inline int
*/
#define core_param(name, var, type, perm) \
param_check_##type(name, &(var)); \
- __module_param_call("", name, ¶m_ops_##type, &var, perm, -1)
+ __module_param_call("", name, ¶m_ops_##type, &var, perm, -1, 0)
#endif /* !MODULE */
/**
= { len, string }; \
__module_param_call(MODULE_PARAM_PREFIX, name, \
¶m_ops_string, \
- .str = &__param_string_##name, perm, -1); \
+ .str = &__param_string_##name, perm, -1, 0);\
__MODULE_PARM_TYPE(name, "string")
/**
__module_param_call(MODULE_PARAM_PREFIX, name, \
¶m_array_ops, \
.arr = &__param_arr_##name, \
- perm, -1); \
+ perm, -1, 0); \
__MODULE_PARM_TYPE(name, "array of " #type)
extern struct kernel_param_ops param_array_ops;
* which are then pulled up with an external resistor. Setting this
* config will enable open drain mode, the argument is ignored.
* @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source
- * (open emitter). Setting this config will enable open drain mode, the
+ * (open emitter). Setting this config will enable open source mode, the
* argument is ignored.
* @PIN_CONFIG_DRIVE_STRENGTH: the pin will sink or source at most the current
* passed as argument. The argument is in mA.
* name can be used with the generic @pinctrl_ops to retrieve the
* actual pins affected. The applicable groups will be returned in
* @groups and the number of groups in @num_groups
- * @enable: enable a certain muxing function with a certain pin group. The
+ * @set_mux: enable a certain muxing function with a certain pin group. The
* driver does not need to figure out whether enabling this function
* conflicts some other use of the pins in that group, such collisions
* are handled by the pinmux subsystem. The @func_selector selects a
* certain function whereas @group_selector selects a certain set of pins
* to be used. On simple controllers the latter argument may be ignored
- * @disable: disable a certain muxing selector with a certain pin group
* @gpio_request_enable: requests and enables GPIO on a certain pin.
* Implement this only if you can mux every pin individually as GPIO. The
* affected GPIO range is passed along with an offset(pin number) into that
unsigned selector,
const char * const **groups,
unsigned * const num_groups);
- int (*enable) (struct pinctrl_dev *pctldev, unsigned func_selector,
- unsigned group_selector);
+ int (*set_mux) (struct pinctrl_dev *pctldev, unsigned func_selector,
+ unsigned group_selector);
int (*gpio_request_enable) (struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset);
#include <linux/textsearch.h>
#include <net/checksum.h>
#include <linux/rcupdate.h>
-#include <linux/dmaengine.h>
#include <linux/hrtimer.h>
#include <linux/dma-mapping.h>
#include <linux/netdev_features.h>
/* 2/4 bit hole (depending on ndisc_nodetype presence) */
kmemcheck_bitfield_end(flags2);
-#if defined CONFIG_NET_DMA || defined CONFIG_NET_RX_BUSY_POLL
- union {
- unsigned int napi_id;
- dma_cookie_t dma_cookie;
- };
+#ifdef CONFIG_NET_RX_BUSY_POLL
+ unsigned int napi_id;
#endif
#ifdef CONFIG_NETWORK_SECMARK
__u32 secmark;
#include <linux/skbuff.h>
-#include <linux/dmaengine.h>
#include <net/sock.h>
#include <net/inet_connection_sock.h>
#include <net/inet_timewait_sock.h>
struct iovec *iov;
int memory;
int len;
-#ifdef CONFIG_NET_DMA
- /* members for async copy */
- struct dma_chan *dma_chan;
- int wakeup;
- struct dma_pinned_list *pinned_list;
- dma_cookie_t dma_cookie;
-#endif
} ucopy;
u32 snd_wl1; /* Sequence for window update */
u32 rt6i_flags;
struct rt6key rt6i_src;
struct rt6key rt6i_prefsrc;
- u32 rt6i_metric;
struct inet6_dev *rt6i_idev;
unsigned long _rt6i_peer;
- u32 rt6i_genid;
-
+ u32 rt6i_metric;
/* more non-fragment space at head required */
unsigned short rt6i_nfheader_len;
-
u8 rt6i_protocol;
};
atomic_inc(&net->ipv4.rt_genid);
}
-#if IS_ENABLED(CONFIG_IPV6)
-static inline int rt_genid_ipv6(struct net *net)
-{
- return atomic_read(&net->ipv6.rt_genid);
-}
-
-static inline void rt_genid_bump_ipv6(struct net *net)
-{
- atomic_inc(&net->ipv6.rt_genid);
-}
-#else
-static inline int rt_genid_ipv6(struct net *net)
-{
- return 0;
-}
-
+extern void (*__fib6_flush_trees)(struct net *net);
static inline void rt_genid_bump_ipv6(struct net *net)
{
+ if (__fib6_flush_trees)
+ __fib6_flush_trees(net);
}
-#endif
#if IS_ENABLED(CONFIG_IEEE802154_6LOWPAN)
static inline struct netns_ieee802154_lowpan *
+++ /dev/null
-/*
- * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59
- * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * The full GNU General Public License is included in this distribution in the
- * file called COPYING.
- */
-#ifndef NETDMA_H
-#define NETDMA_H
-#ifdef CONFIG_NET_DMA
-#include <linux/dmaengine.h>
-#include <linux/skbuff.h>
-
-int dma_skb_copy_datagram_iovec(struct dma_chan* chan,
- struct sk_buff *skb, int offset, struct iovec *to,
- size_t len, struct dma_pinned_list *pinned_list);
-
-#endif /* CONFIG_NET_DMA */
-#endif /* NETDMA_H */
* @sk_receive_queue: incoming packets
* @sk_wmem_alloc: transmit queue bytes committed
* @sk_write_queue: Packet sending queue
- * @sk_async_wait_queue: DMA copied packets
* @sk_omem_alloc: "o" is "option" or "other"
* @sk_wmem_queued: persistent queue size
* @sk_forward_alloc: space allocated forward
struct sk_filter __rcu *sk_filter;
struct socket_wq __rcu *sk_wq;
-#ifdef CONFIG_NET_DMA
- struct sk_buff_head sk_async_wait_queue;
-#endif
-
#ifdef CONFIG_XFRM
struct xfrm_policy *sk_policy[2];
#endif
* sk_eat_skb - Release a skb if it is no longer needed
* @sk: socket to eat this skb from
* @skb: socket buffer to eat
- * @copied_early: flag indicating whether DMA operations copied this data early
*
* This routine must be called with interrupts disabled or with the socket
* locked so that the sk_buff queue operation is ok.
*/
-#ifdef CONFIG_NET_DMA
-static inline void sk_eat_skb(struct sock *sk, struct sk_buff *skb, bool copied_early)
-{
- __skb_unlink(skb, &sk->sk_receive_queue);
- if (!copied_early)
- __kfree_skb(skb);
- else
- __skb_queue_tail(&sk->sk_async_wait_queue, skb);
-}
-#else
-static inline void sk_eat_skb(struct sock *sk, struct sk_buff *skb, bool copied_early)
+static inline void sk_eat_skb(struct sock *sk, struct sk_buff *skb)
{
__skb_unlink(skb, &sk->sk_receive_queue);
__kfree_skb(skb);
}
-#endif
static inline
struct net *sock_net(const struct sock *sk)
#include <linux/cache.h>
#include <linux/percpu.h>
#include <linux/skbuff.h>
-#include <linux/dmaengine.h>
#include <linux/crypto.h>
#include <linux/cryptohash.h>
#include <linux/kref.h>
extern int sysctl_tcp_tw_reuse;
extern int sysctl_tcp_frto;
extern int sysctl_tcp_low_latency;
-extern int sysctl_tcp_dma_copybreak;
extern int sysctl_tcp_nometrics_save;
extern int sysctl_tcp_moderate_rcvbuf;
extern int sysctl_tcp_tso_win_divisor;
void tcp_rcv_established(struct sock *sk, struct sk_buff *skb,
const struct tcphdr *th, unsigned int len);
void tcp_rcv_space_adjust(struct sock *sk);
-void tcp_cleanup_rbuf(struct sock *sk, int copied);
int tcp_twsk_unique(struct sock *sk, struct sock *sktw, void *twp);
void tcp_twsk_destructor(struct sock *sk);
ssize_t tcp_splice_read(struct socket *sk, loff_t *ppos,
tp->ucopy.len = 0;
tp->ucopy.memory = 0;
skb_queue_head_init(&tp->ucopy.prequeue);
-#ifdef CONFIG_NET_DMA
- tp->ucopy.dma_chan = NULL;
- tp->ucopy.wakeup = 0;
- tp->ucopy.pinned_list = NULL;
- tp->ucopy.dma_cookie = 0;
-#endif
}
bool tcp_prequeue(struct sock *sk, struct sk_buff *skb);
int "Kernel log buffer size (16 => 64KB, 17 => 128KB)"
range 12 21
default 17
+ depends on PRINTK
help
Select the minimal kernel log buffer size as a power of 2.
The final size is affected by LOG_CPU_MAX_BUF_SHIFT config
range 0 21
default 12 if !BASE_SMALL
default 0 if BASE_SMALL
+ depends on PRINTK
help
This option allows to increase the default ring buffer size
according to the number of CPUs. The value defines the contribution
config HAVE_FUTEX_CMPXCHG
bool
+ depends on FUTEX
help
Architectures should select this if futex_atomic_cmpxchg_inatomic()
is implemented and always working. This removes a couple of runtime
by some high performance threaded applications. Disabling
this option saves about 7k.
+config ADVISE_SYSCALLS
+ bool "Enable madvise/fadvise syscalls" if EXPERT
+ default y
+ help
+ This option enables the madvise and fadvise syscalls, used by
+ applications to advise the kernel about their future memory or file
+ usage, improving performance. If building an embedded system where no
+ applications use these syscalls, you can disable this option to save
+ space.
+
config PCI_QUIRKS
default y
bool "Enable PCI quirk workarounds" if EXPERT
default "sha384" if MODULE_SIG_SHA384
default "sha512" if MODULE_SIG_SHA512
+config MODULE_COMPRESS
+ bool "Compress modules on installation"
+ depends on MODULES
+ help
+ This option compresses the kernel modules when 'make
+ modules_install' is run.
+
+ The modules will be compressed either using gzip or xz depend on the
+ choice made in "Compression algorithm".
+
+ module-init-tools has support for gzip format while kmod handle gzip
+ and xz compressed modules.
+
+ When a kernel module is installed from outside of the main kernel
+ source and uses the Kbuild system for installing modules then that
+ kernel module will also be compressed when it is installed.
+
+ This option provides little benefit when the modules are to be used inside
+ an initrd or initramfs, it generally is more efficient to compress the whole
+ initrd or initramfs instead.
+
+ This is fully compatible with signed modules while the signed module is
+ compressed. module-init-tools or kmod handles decompression and provide to
+ other layer the uncompressed but signed payload.
+
+choice
+ prompt "Compression algorithm"
+ depends on MODULE_COMPRESS
+ default MODULE_COMPRESS_GZIP
+ help
+ This determines which sort of compression will be used during
+ 'make modules_install'.
+
+ GZIP (default) and XZ are supported.
+
+config MODULE_COMPRESS_GZIP
+ bool "GZIP"
+
+config MODULE_COMPRESS_XZ
+ bool "XZ"
+
+endchoice
+
endif # MODULES
config INIT_ALL_POSSIBLE
--- /dev/null
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_KERNEL_XZ=y
+CONFIG_OPTIMIZE_INLINING=y
+CONFIG_SLOB=y
for_each_task_context_nr(ctxn) {
ret = perf_event_init_context(child, ctxn);
- if (ret)
+ if (ret) {
+ perf_event_free_task(child);
return ret;
+ }
}
return 0;
goto bad_fork_cleanup_policy;
retval = audit_alloc(p);
if (retval)
- goto bad_fork_cleanup_policy;
+ goto bad_fork_cleanup_perf;
/* copy all the process information */
shm_init_task(p);
retval = copy_semundo(clone_flags, p);
exit_sem(p);
bad_fork_cleanup_audit:
audit_free(p);
-bad_fork_cleanup_policy:
+bad_fork_cleanup_perf:
perf_event_free_task(p);
+bad_fork_cleanup_policy:
#ifdef CONFIG_NUMA
mpol_put(p->mempolicy);
bad_fork_cleanup_threadgroup_lock:
}
static const struct kernel_param_ops param_ops_bool_enable_only = {
- .flags = KERNEL_PARAM_FL_NOARG,
+ .flags = KERNEL_PARAM_OPS_FL_NOARG,
.set = param_set_bool_enable_only,
.get = param_get_bool,
};
return parameqn(a, b, strlen(a)+1);
}
+static void param_check_unsafe(const struct kernel_param *kp)
+{
+ if (kp->flags & KERNEL_PARAM_FL_UNSAFE) {
+ pr_warn("Setting dangerous option %s - tainting kernel\n",
+ kp->name);
+ add_taint(TAINT_USER, LOCKDEP_STILL_OK);
+ }
+}
+
static int parse_one(char *param,
char *val,
const char *doing,
return 0;
/* No one handled NULL, so do it here. */
if (!val &&
- !(params[i].ops->flags & KERNEL_PARAM_FL_NOARG))
+ !(params[i].ops->flags & KERNEL_PARAM_OPS_FL_NOARG))
return -EINVAL;
pr_debug("handling %s with %p\n", param,
params[i].ops->set);
mutex_lock(¶m_lock);
+ param_check_unsafe(¶ms[i]);
err = params[i].ops->set(val, ¶ms[i]);
mutex_unlock(¶m_lock);
return err;
EXPORT_SYMBOL(param_get_bool);
struct kernel_param_ops param_ops_bool = {
- .flags = KERNEL_PARAM_FL_NOARG,
+ .flags = KERNEL_PARAM_OPS_FL_NOARG,
.set = param_set_bool,
.get = param_get_bool,
};
EXPORT_SYMBOL(param_set_bint);
struct kernel_param_ops param_ops_bint = {
- .flags = KERNEL_PARAM_FL_NOARG,
+ .flags = KERNEL_PARAM_OPS_FL_NOARG,
.set = param_set_bint,
.get = param_get_int,
};
return -EPERM;
mutex_lock(¶m_lock);
+ param_check_unsafe(attribute->param);
err = attribute->param->ops->set(buf, attribute->param);
mutex_unlock(¶m_lock);
if (!err)
cond_syscall(compat_sys_process_vm_readv);
cond_syscall(compat_sys_process_vm_writev);
cond_syscall(sys_uselib);
+cond_syscall(sys_fadvise64);
+cond_syscall(sys_fadvise64_64);
+cond_syscall(sys_madvise);
/* arch-specific weak syscall entries */
cond_syscall(sys_pciconfig_read);
{ CTL_INT, NET_TCP_MTU_PROBING, "tcp_mtu_probing" },
{ CTL_INT, NET_TCP_BASE_MSS, "tcp_base_mss" },
{ CTL_INT, NET_IPV4_TCP_WORKAROUND_SIGNED_WINDOWS, "tcp_workaround_signed_windows" },
- { CTL_INT, NET_TCP_DMA_COPYBREAK, "tcp_dma_copybreak" },
{ CTL_INT, NET_TCP_SLOW_START_AFTER_IDLE, "tcp_slow_start_after_idle" },
{ CTL_INT, NET_CIPSOV4_CACHE_ENABLE, "cipso_cache_enable" },
{ CTL_INT, NET_CIPSOV4_CACHE_BUCKET_SIZE, "cipso_cache_bucket_size" },
iter->head = cpu_buffer->reader_page->read;
iter->cache_reader_page = iter->head_page;
- iter->cache_read = iter->head;
+ iter->cache_read = cpu_buffer->read;
if (iter->head)
iter->read_stamp = cpu_buffer->read_stamp;
* rhashtable_destroy - destroy hash table
* @ht: the hash table to destroy
*
- * Frees the bucket array.
+ * Frees the bucket array. This function is not rcu safe, therefore the caller
+ * has to make sure that no resizing may happen by unpublishing the hashtable
+ * and waiting for the quiescent cycle before releasing the bucket array.
*/
void rhashtable_destroy(const struct rhashtable *ht)
{
- const struct bucket_table *tbl = rht_dereference(ht->tbl, ht);
-
- bucket_table_free(tbl);
+ bucket_table_free(ht->tbl);
}
EXPORT_SYMBOL_GPL(rhashtable_destroy);
#
mmu-y := nommu.o
-mmu-$(CONFIG_MMU) := fremap.o gup.o highmem.o madvise.o memory.o mincore.o \
+mmu-$(CONFIG_MMU) := fremap.o gup.o highmem.o memory.o mincore.o \
mlock.o mmap.o mprotect.o mremap.o msync.o rmap.o \
vmalloc.o pagewalk.o pgtable-generic.o
mmu-$(CONFIG_MMU) += process_vm_access.o
endif
-obj-y := filemap.o mempool.o oom_kill.o fadvise.o \
+obj-y := filemap.o mempool.o oom_kill.o \
maccess.o page_alloc.o page-writeback.o \
readahead.o swap.o truncate.o vmscan.o shmem.o \
util.o mmzone.o vmstat.o backing-dev.o \
obj-y += bootmem.o
endif
+ifdef CONFIG_MMU
+ obj-$(CONFIG_ADVISE_SYSCALLS) += fadvise.o madvise.o
+endif
obj-$(CONFIG_HAVE_MEMBLOCK) += memblock.o
obj-$(CONFIG_SWAP) += page_io.o swap_state.o swapfile.o
for (i = 0; i < HPAGE_PMD_NR; i++, haddr += PAGE_SIZE) {
pte_t *pte, entry;
BUG_ON(PageCompound(page+i));
+ /*
+ * Note that pmd_numa is not transferred deliberately
+ * to avoid any possibility that pte_numa leaks to
+ * a PROT_NONE VMA by accident.
+ */
entry = mk_pte(page + i, vma->vm_page_prot);
entry = maybe_mkwrite(pte_mkdirty(entry), vma);
if (!pmd_write(*pmd))
entry = pte_wrprotect(entry);
if (!pmd_young(*pmd))
entry = pte_mkold(entry);
- if (pmd_numa(*pmd))
- entry = pte_mknuma(entry);
pte = pte_offset_map(&_pmd, haddr);
BUG_ON(!pte_none(*pte));
set_pte_at(mm, haddr, pte, entry);
/* vmpressure notifications */
struct vmpressure vmpressure;
+ /* css_online() has been completed */
+ int initialized;
+
/*
* the counter to account for mem+swap usage.
*/
* skipping css reference should be safe.
*/
if (next_css) {
- if ((next_css == &root->css) ||
- ((next_css->flags & CSS_ONLINE) &&
- css_tryget_online(next_css)))
- return mem_cgroup_from_css(next_css);
+ struct mem_cgroup *memcg = mem_cgroup_from_css(next_css);
+
+ if (next_css == &root->css)
+ return memcg;
+
+ if (css_tryget_online(next_css)) {
+ /*
+ * Make sure the memcg is initialized:
+ * mem_cgroup_css_online() orders the the
+ * initialization against setting the flag.
+ */
+ if (smp_load_acquire(&memcg->initialized))
+ return memcg;
+ css_put(next_css);
+ }
prev_css = next_css;
goto skip_node;
{
struct mem_cgroup *memcg = mem_cgroup_from_css(css);
struct mem_cgroup *parent = mem_cgroup_from_css(css->parent);
+ int ret;
if (css->id > MEM_CGROUP_ID_MAX)
return -ENOSPC;
}
mutex_unlock(&memcg_create_mutex);
- return memcg_init_kmem(memcg, &memory_cgrp_subsys);
+ ret = memcg_init_kmem(memcg, &memory_cgrp_subsys);
+ if (ret)
+ return ret;
+
+ /*
+ * Make sure the memcg is initialized: mem_cgroup_iter()
+ * orders reading memcg->initialized against its callers
+ * reading the memcg members.
+ */
+ smp_store_release(&memcg->initialized, 1);
+
+ return 0;
}
/*
pte = pte_mkold(mk_pte(new, vma->vm_page_prot));
if (pte_swp_soft_dirty(*ptep))
pte = pte_mksoft_dirty(pte);
+
+ /* Recheck VMA as permissions can change since migration started */
if (is_write_migration_entry(entry))
- pte = pte_mkwrite(pte);
+ pte = maybe_mkwrite(pte, vma);
+
#ifdef CONFIG_HUGETLB_PAGE
if (PageHuge(new)) {
pte = pte_mkhuge(pte);
}
__mod_zone_page_state(zone, NR_ALLOC_BATCH, -(1 << order));
- if (zone_page_state(zone, NR_ALLOC_BATCH) == 0 &&
+ if (atomic_long_read(&zone->vm_stat[NR_ALLOC_BATCH]) <= 0 &&
!zone_is_fair_depleted(zone))
zone_set_flag(zone, ZONE_FAIR_DEPLETED);
zone->watermark[WMARK_HIGH] = min_wmark_pages(zone) + (tmp >> 1);
__mod_zone_page_state(zone, NR_ALLOC_BATCH,
- high_wmark_pages(zone) -
- low_wmark_pages(zone) -
- zone_page_state(zone, NR_ALLOC_BATCH));
+ high_wmark_pages(zone) - low_wmark_pages(zone) -
+ atomic_long_read(&zone->vm_stat[NR_ALLOC_BATCH]));
setup_zone_migrate_reserve(zone);
spin_unlock_irqrestore(&zone->lock, flags);
obj-$(CONFIG_PROC_FS) += net-procfs.o
obj-$(CONFIG_NET_PKTGEN) += pktgen.o
obj-$(CONFIG_NETPOLL) += netpoll.o
-obj-$(CONFIG_NET_DMA) += user_dma.o
obj-$(CONFIG_FIB_RULES) += fib_rules.o
obj-$(CONFIG_TRACEPOINTS) += net-traces.o
obj-$(CONFIG_NET_DROP_MONITOR) += drop_monitor.o
clear_bit(__LINK_STATE_START, &dev->state);
else {
dev->flags |= IFF_UP;
- net_dmaengine_get();
dev_set_rx_mode(dev);
dev_activate(dev);
add_device_randomness(dev->dev_addr, dev->addr_len);
ops->ndo_stop(dev);
dev->flags &= ~IFF_UP;
- net_dmaengine_put();
netpoll_poll_enable(dev);
}
out:
net_rps_action_and_irq_enable(sd);
-#ifdef CONFIG_NET_DMA
- /*
- * There may not be any more sk_buffs coming right now, so push
- * any pending DMA copies to hardware
- */
- dma_issue_pending_all();
-#endif
-
return;
softnet_break:
NAPI_GRO_CB(skb)->free = NAPI_GRO_FREE_STOLEN_HEAD;
goto done;
}
+ /* switch back to head shinfo */
+ pinfo = skb_shinfo(p);
+
if (pinfo->frag_list)
goto merge;
if (skb_gro_len(p) != pinfo->gso_size)
atomic_set(&newsk->sk_omem_alloc, 0);
skb_queue_head_init(&newsk->sk_receive_queue);
skb_queue_head_init(&newsk->sk_write_queue);
-#ifdef CONFIG_NET_DMA
- skb_queue_head_init(&newsk->sk_async_wait_queue);
-#endif
spin_lock_init(&newsk->sk_dst_lock);
rwlock_init(&newsk->sk_callback_lock);
skb_queue_head_init(&sk->sk_receive_queue);
skb_queue_head_init(&sk->sk_write_queue);
skb_queue_head_init(&sk->sk_error_queue);
-#ifdef CONFIG_NET_DMA
- skb_queue_head_init(&sk->sk_async_wait_queue);
-#endif
sk->sk_send_head = NULL;
+++ /dev/null
-/*
- * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
- * Portions based on net/core/datagram.c and copyrighted by their authors.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59
- * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * The full GNU General Public License is included in this distribution in the
- * file called COPYING.
- */
-
-/*
- * This code allows the net stack to make use of a DMA engine for
- * skb to iovec copies.
- */
-
-#include <linux/dmaengine.h>
-#include <linux/socket.h>
-#include <linux/export.h>
-#include <net/tcp.h>
-#include <net/netdma.h>
-
-#define NET_DMA_DEFAULT_COPYBREAK 4096
-
-int sysctl_tcp_dma_copybreak = NET_DMA_DEFAULT_COPYBREAK;
-EXPORT_SYMBOL(sysctl_tcp_dma_copybreak);
-
-/**
- * dma_skb_copy_datagram_iovec - Copy a datagram to an iovec.
- * @skb - buffer to copy
- * @offset - offset in the buffer to start copying from
- * @iovec - io vector to copy to
- * @len - amount of data to copy from buffer to iovec
- * @pinned_list - locked iovec buffer data
- *
- * Note: the iovec is modified during the copy.
- */
-int dma_skb_copy_datagram_iovec(struct dma_chan *chan,
- struct sk_buff *skb, int offset, struct iovec *to,
- size_t len, struct dma_pinned_list *pinned_list)
-{
- int start = skb_headlen(skb);
- int i, copy = start - offset;
- struct sk_buff *frag_iter;
- dma_cookie_t cookie = 0;
-
- /* Copy header. */
- if (copy > 0) {
- if (copy > len)
- copy = len;
- cookie = dma_memcpy_to_iovec(chan, to, pinned_list,
- skb->data + offset, copy);
- if (cookie < 0)
- goto fault;
- len -= copy;
- if (len == 0)
- goto end;
- offset += copy;
- }
-
- /* Copy paged appendix. Hmm... why does this look so complicated? */
- for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
- int end;
- const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
-
- WARN_ON(start > offset + len);
-
- end = start + skb_frag_size(frag);
- copy = end - offset;
- if (copy > 0) {
- struct page *page = skb_frag_page(frag);
-
- if (copy > len)
- copy = len;
-
- cookie = dma_memcpy_pg_to_iovec(chan, to, pinned_list, page,
- frag->page_offset + offset - start, copy);
- if (cookie < 0)
- goto fault;
- len -= copy;
- if (len == 0)
- goto end;
- offset += copy;
- }
- start = end;
- }
-
- skb_walk_frags(skb, frag_iter) {
- int end;
-
- WARN_ON(start > offset + len);
-
- end = start + frag_iter->len;
- copy = end - offset;
- if (copy > 0) {
- if (copy > len)
- copy = len;
- cookie = dma_skb_copy_datagram_iovec(chan, frag_iter,
- offset - start,
- to, copy,
- pinned_list);
- if (cookie < 0)
- goto fault;
- len -= copy;
- if (len == 0)
- goto end;
- offset += copy;
- }
- start = end;
- }
-
-end:
- if (!len) {
- skb->dma_cookie = cookie;
- return cookie;
- }
-
-fault:
- return -EFAULT;
-}
default:
dccp_pr_debug("packet_type=%s\n",
dccp_packet_name(dh->dccph_type));
- sk_eat_skb(sk, skb, false);
+ sk_eat_skb(sk, skb);
}
verify_sock_status:
if (sock_flag(sk, SOCK_DONE)) {
len = skb->len;
found_fin_ok:
if (!(flags & MSG_PEEK))
- sk_eat_skb(sk, skb, false);
+ sk_eat_skb(sk, skb);
break;
} while (1);
out:
t = ip_tunnel_find(itn, p, itn->fb_tunnel_dev->type);
- if (!t && (cmd == SIOCADDTUNNEL)) {
- t = ip_tunnel_create(net, itn, p);
- err = PTR_ERR_OR_ZERO(t);
+ if (cmd == SIOCADDTUNNEL) {
+ if (!t) {
+ t = ip_tunnel_create(net, itn, p);
+ err = PTR_ERR_OR_ZERO(t);
+ break;
+ }
+
+ err = -EEXIST;
break;
}
if (dev != itn->fb_tunnel_dev && cmd == SIOCCHGTUNNEL) {
}
n = ipv4_neigh_lookup(&rt->dst, NULL, &new_gw);
- if (n) {
+ if (!IS_ERR(n)) {
if (!(n->nud_state & NUD_VALID)) {
neigh_event_send(n, NULL);
} else {
.mode = 0644,
.proc_handler = proc_dointvec
},
-#ifdef CONFIG_NET_DMA
- {
- .procname = "tcp_dma_copybreak",
- .data = &sysctl_tcp_dma_copybreak,
- .maxlen = sizeof(int),
- .mode = 0644,
- .proc_handler = proc_dointvec
- },
-#endif
{
.procname = "tcp_slow_start_after_idle",
.data = &sysctl_tcp_slow_start_after_idle,
#include <net/tcp.h>
#include <net/xfrm.h>
#include <net/ip.h>
-#include <net/netdma.h>
#include <net/sock.h>
#include <asm/uaccess.h>
* calculation of whether or not we must ACK for the sake of
* a window update.
*/
-void tcp_cleanup_rbuf(struct sock *sk, int copied)
+static void tcp_cleanup_rbuf(struct sock *sk, int copied)
{
struct tcp_sock *tp = tcp_sk(sk);
bool time_to_ack = false;
tp->ucopy.memory = 0;
}
-#ifdef CONFIG_NET_DMA
-static void tcp_service_net_dma(struct sock *sk, bool wait)
-{
- dma_cookie_t done, used;
- dma_cookie_t last_issued;
- struct tcp_sock *tp = tcp_sk(sk);
-
- if (!tp->ucopy.dma_chan)
- return;
-
- last_issued = tp->ucopy.dma_cookie;
- dma_async_issue_pending(tp->ucopy.dma_chan);
-
- do {
- if (dma_async_is_tx_complete(tp->ucopy.dma_chan,
- last_issued, &done,
- &used) == DMA_COMPLETE) {
- /* Safe to free early-copied skbs now */
- __skb_queue_purge(&sk->sk_async_wait_queue);
- break;
- } else {
- struct sk_buff *skb;
- while ((skb = skb_peek(&sk->sk_async_wait_queue)) &&
- (dma_async_is_complete(skb->dma_cookie, done,
- used) == DMA_COMPLETE)) {
- __skb_dequeue(&sk->sk_async_wait_queue);
- kfree_skb(skb);
- }
- }
- } while (wait);
-}
-#endif
-
static struct sk_buff *tcp_recv_skb(struct sock *sk, u32 seq, u32 *off)
{
struct sk_buff *skb;
* splitted a fat GRO packet, while we released socket lock
* in skb_splice_bits()
*/
- sk_eat_skb(sk, skb, false);
+ sk_eat_skb(sk, skb);
}
return NULL;
}
continue;
}
if (tcp_hdr(skb)->fin) {
- sk_eat_skb(sk, skb, false);
+ sk_eat_skb(sk, skb);
++seq;
break;
}
- sk_eat_skb(sk, skb, false);
+ sk_eat_skb(sk, skb);
if (!desc->count)
break;
tp->copied_seq = seq;
int target; /* Read at least this many bytes */
long timeo;
struct task_struct *user_recv = NULL;
- bool copied_early = false;
struct sk_buff *skb;
u32 urg_hole = 0;
target = sock_rcvlowat(sk, flags & MSG_WAITALL, len);
-#ifdef CONFIG_NET_DMA
- tp->ucopy.dma_chan = NULL;
- preempt_disable();
- skb = skb_peek_tail(&sk->sk_receive_queue);
- {
- int available = 0;
-
- if (skb)
- available = TCP_SKB_CB(skb)->seq + skb->len - (*seq);
- if ((available < target) &&
- (len > sysctl_tcp_dma_copybreak) && !(flags & MSG_PEEK) &&
- !sysctl_tcp_low_latency &&
- net_dma_find_channel()) {
- preempt_enable();
- tp->ucopy.pinned_list =
- dma_pin_iovec_pages(msg->msg_iov, len);
- } else {
- preempt_enable();
- }
- }
-#endif
-
do {
u32 offset;
/* __ Set realtime policy in scheduler __ */
}
-#ifdef CONFIG_NET_DMA
- if (tp->ucopy.dma_chan) {
- if (tp->rcv_wnd == 0 &&
- !skb_queue_empty(&sk->sk_async_wait_queue)) {
- tcp_service_net_dma(sk, true);
- tcp_cleanup_rbuf(sk, copied);
- } else
- dma_async_issue_pending(tp->ucopy.dma_chan);
- }
-#endif
if (copied >= target) {
/* Do not sleep, just process backlog. */
release_sock(sk);
} else
sk_wait_data(sk, &timeo);
-#ifdef CONFIG_NET_DMA
- tcp_service_net_dma(sk, false); /* Don't block */
- tp->ucopy.wakeup = 0;
-#endif
-
if (user_recv) {
int chunk;
}
if (!(flags & MSG_TRUNC)) {
-#ifdef CONFIG_NET_DMA
- if (!tp->ucopy.dma_chan && tp->ucopy.pinned_list)
- tp->ucopy.dma_chan = net_dma_find_channel();
-
- if (tp->ucopy.dma_chan) {
- tp->ucopy.dma_cookie = dma_skb_copy_datagram_iovec(
- tp->ucopy.dma_chan, skb, offset,
- msg->msg_iov, used,
- tp->ucopy.pinned_list);
-
- if (tp->ucopy.dma_cookie < 0) {
-
- pr_alert("%s: dma_cookie < 0\n",
- __func__);
-
- /* Exception. Bailout! */
- if (!copied)
- copied = -EFAULT;
- break;
- }
-
- dma_async_issue_pending(tp->ucopy.dma_chan);
-
- if ((offset + used) == skb->len)
- copied_early = true;
-
- } else
-#endif
- {
- err = skb_copy_datagram_iovec(skb, offset,
- msg->msg_iov, used);
- if (err) {
- /* Exception. Bailout! */
- if (!copied)
- copied = -EFAULT;
- break;
- }
+ err = skb_copy_datagram_iovec(skb, offset,
+ msg->msg_iov, used);
+ if (err) {
+ /* Exception. Bailout! */
+ if (!copied)
+ copied = -EFAULT;
+ break;
}
}
if (tcp_hdr(skb)->fin)
goto found_fin_ok;
- if (!(flags & MSG_PEEK)) {
- sk_eat_skb(sk, skb, copied_early);
- copied_early = false;
- }
+ if (!(flags & MSG_PEEK))
+ sk_eat_skb(sk, skb);
continue;
found_fin_ok:
/* Process the FIN. */
++*seq;
- if (!(flags & MSG_PEEK)) {
- sk_eat_skb(sk, skb, copied_early);
- copied_early = false;
- }
+ if (!(flags & MSG_PEEK))
+ sk_eat_skb(sk, skb);
break;
} while (len > 0);
tp->ucopy.len = 0;
}
-#ifdef CONFIG_NET_DMA
- tcp_service_net_dma(sk, true); /* Wait for queue to drain */
- tp->ucopy.dma_chan = NULL;
-
- if (tp->ucopy.pinned_list) {
- dma_unpin_iovec_pages(tp->ucopy.pinned_list);
- tp->ucopy.pinned_list = NULL;
- }
-#endif
-
/* According to UNIX98, msg_name/msg_namelen are ignored
* on connected socket. I was just happy when found this 8) --ANK
*/
__skb_queue_purge(&sk->sk_receive_queue);
tcp_write_queue_purge(sk);
__skb_queue_purge(&tp->out_of_order_queue);
-#ifdef CONFIG_NET_DMA
- __skb_queue_purge(&sk->sk_async_wait_queue);
-#endif
inet->inet_dport = 0;
#include <net/inet_common.h>
#include <linux/ipsec.h>
#include <asm/unaligned.h>
-#include <net/netdma.h>
#include <linux/errqueue.h>
int sysctl_tcp_timestamps __read_mostly = 1;
__tcp_checksum_complete_user(sk, skb);
}
-#ifdef CONFIG_NET_DMA
-static bool tcp_dma_try_early_copy(struct sock *sk, struct sk_buff *skb,
- int hlen)
-{
- struct tcp_sock *tp = tcp_sk(sk);
- int chunk = skb->len - hlen;
- int dma_cookie;
- bool copied_early = false;
-
- if (tp->ucopy.wakeup)
- return false;
-
- if (!tp->ucopy.dma_chan && tp->ucopy.pinned_list)
- tp->ucopy.dma_chan = net_dma_find_channel();
-
- if (tp->ucopy.dma_chan && skb_csum_unnecessary(skb)) {
-
- dma_cookie = dma_skb_copy_datagram_iovec(tp->ucopy.dma_chan,
- skb, hlen,
- tp->ucopy.iov, chunk,
- tp->ucopy.pinned_list);
-
- if (dma_cookie < 0)
- goto out;
-
- tp->ucopy.dma_cookie = dma_cookie;
- copied_early = true;
-
- tp->ucopy.len -= chunk;
- tp->copied_seq += chunk;
- tcp_rcv_space_adjust(sk);
-
- if ((tp->ucopy.len == 0) ||
- (tcp_flag_word(tcp_hdr(skb)) & TCP_FLAG_PSH) ||
- (atomic_read(&sk->sk_rmem_alloc) > (sk->sk_rcvbuf >> 1))) {
- tp->ucopy.wakeup = 1;
- sk->sk_data_ready(sk);
- }
- } else if (chunk > 0) {
- tp->ucopy.wakeup = 1;
- sk->sk_data_ready(sk);
- }
-out:
- return copied_early;
-}
-#endif /* CONFIG_NET_DMA */
-
/* Does PAWS and seqno based validation of an incoming segment, flags will
* play significant role here.
*/
}
} else {
int eaten = 0;
- int copied_early = 0;
bool fragstolen = false;
- if (tp->copied_seq == tp->rcv_nxt &&
- len - tcp_header_len <= tp->ucopy.len) {
-#ifdef CONFIG_NET_DMA
- if (tp->ucopy.task == current &&
- sock_owned_by_user(sk) &&
- tcp_dma_try_early_copy(sk, skb, tcp_header_len)) {
- copied_early = 1;
- eaten = 1;
- }
-#endif
- if (tp->ucopy.task == current &&
- sock_owned_by_user(sk) && !copied_early) {
- __set_current_state(TASK_RUNNING);
+ if (tp->ucopy.task == current &&
+ tp->copied_seq == tp->rcv_nxt &&
+ len - tcp_header_len <= tp->ucopy.len &&
+ sock_owned_by_user(sk)) {
+ __set_current_state(TASK_RUNNING);
- if (!tcp_copy_to_iovec(sk, skb, tcp_header_len))
- eaten = 1;
- }
- if (eaten) {
+ if (!tcp_copy_to_iovec(sk, skb, tcp_header_len)) {
/* Predicted packet is in window by definition.
* seq == rcv_nxt and rcv_wup <= rcv_nxt.
* Hence, check seq<=rcv_wup reduces to:
__skb_pull(skb, tcp_header_len);
tp->rcv_nxt = TCP_SKB_CB(skb)->end_seq;
NET_INC_STATS_BH(sock_net(sk), LINUX_MIB_TCPHPHITSTOUSER);
+ eaten = 1;
}
- if (copied_early)
- tcp_cleanup_rbuf(sk, skb->len);
}
if (!eaten) {
if (tcp_checksum_complete_user(sk, skb))
goto no_ack;
}
- if (!copied_early || tp->rcv_nxt != tp->rcv_wup)
- __tcp_ack_snd_check(sk, 0);
+ __tcp_ack_snd_check(sk, 0);
no_ack:
-#ifdef CONFIG_NET_DMA
- if (copied_early)
- __skb_queue_tail(&sk->sk_async_wait_queue, skb);
- else
-#endif
if (eaten)
kfree_skb_partial(skb, fragstolen);
sk->sk_data_ready(sk);
#include <net/inet_common.h>
#include <net/timewait_sock.h>
#include <net/xfrm.h>
-#include <net/netdma.h>
#include <net/secure_seq.h>
#include <net/tcp_memcontrol.h>
#include <net/busy_poll.h>
bh_lock_sock_nested(sk);
ret = 0;
if (!sock_owned_by_user(sk)) {
-#ifdef CONFIG_NET_DMA
- struct tcp_sock *tp = tcp_sk(sk);
- if (!tp->ucopy.dma_chan && tp->ucopy.pinned_list)
- tp->ucopy.dma_chan = net_dma_find_channel();
- if (tp->ucopy.dma_chan)
+ if (!tcp_prequeue(sk, skb))
ret = tcp_v4_do_rcv(sk, skb);
- else
-#endif
- {
- if (!tcp_prequeue(sk, skb))
- ret = tcp_v4_do_rcv(sk, skb);
- }
} else if (unlikely(sk_add_backlog(sk, skb,
sk->sk_rcvbuf + sk->sk_sndbuf))) {
bh_unlock_sock(sk);
}
#endif
-#ifdef CONFIG_NET_DMA
- /* Cleans up our sk_async_wait_queue */
- __skb_queue_purge(&sk->sk_async_wait_queue);
-#endif
-
/* Clean prequeue, it must be empty really */
__skb_queue_purge(&tp->ucopy.prequeue);
if (ip6_del_rt(ifp->rt))
dst_free(&ifp->rt->dst);
+
+ rt_genid_bump_ipv6(net);
break;
}
atomic_inc(&net->ipv6.dev_addr_genid);
- rt_genid_bump_ipv6(net);
}
static void ipv6_ifa_notify(int event, struct inet6_ifaddr *ifp)
#include <net/addrconf.h>
#include <net/ip.h>
+/* if ipv6 module registers this function is used by xfrm to force all
+ * sockets to relookup their nodes - this is fairly expensive, be
+ * careful
+ */
+void (*__fib6_flush_trees)(struct net *);
+EXPORT_SYMBOL(__fib6_flush_trees);
+
#define IPV6_ADDR_SCOPE_TYPE(scope) ((scope) << 16)
static inline unsigned int ipv6_addr_scope2type(unsigned int scope)
fib6_clean_tree(net, fn, fib6_prune_clone, 1, NULL);
}
+static int fib6_update_sernum(struct rt6_info *rt, void *arg)
+{
+ __u32 sernum = *(__u32 *)arg;
+
+ if (rt->rt6i_node &&
+ rt->rt6i_node->fn_sernum != sernum)
+ rt->rt6i_node->fn_sernum = sernum;
+
+ return 0;
+}
+
+static void fib6_flush_trees(struct net *net)
+{
+ __u32 new_sernum = fib6_new_sernum();
+
+ fib6_clean_all(net, fib6_update_sernum, &new_sernum);
+}
+
/*
* Garbage collection
*/
NULL);
if (ret)
goto out_unregister_subsys;
+
+ __fib6_flush_trees = fib6_flush_trees;
out:
return ret;
struct ip6gre_net *ign = net_generic(net, ip6gre_net_id);
t = ip6gre_tunnel_find(net, parms, ARPHRD_IP6GRE);
+ if (t && create)
+ return NULL;
if (t || !create)
return t;
MODULE_AUTHOR("D. Kozlov (xeb@mail.ru)");
MODULE_DESCRIPTION("GRE over IPv6 tunneling device");
MODULE_ALIAS_RTNL_LINK("ip6gre");
+MODULE_ALIAS_RTNL_LINK("ip6gretap");
MODULE_ALIAS_NETDEV("ip6gre0");
(t = rtnl_dereference(*tp)) != NULL;
tp = &t->next) {
if (ipv6_addr_equal(local, &t->parms.laddr) &&
- ipv6_addr_equal(remote, &t->parms.raddr))
+ ipv6_addr_equal(remote, &t->parms.raddr)) {
+ if (create)
+ return NULL;
+
return t;
+ }
}
if (!create)
return NULL;
(t = rtnl_dereference(*tp)) != NULL;
tp = &t->next) {
if (ipv6_addr_equal(local, &t->parms.laddr) &&
- ipv6_addr_equal(remote, &t->parms.raddr))
+ ipv6_addr_equal(remote, &t->parms.raddr)) {
+ if (create)
+ return NULL;
+
return t;
+ }
}
if (!create)
return NULL;
memset(dst + 1, 0, sizeof(*rt) - sizeof(*dst));
rt6_init_peer(rt, table ? &table->tb6_peers : net->ipv6.peers);
- rt->rt6i_genid = rt_genid_ipv6(net);
INIT_LIST_HEAD(&rt->rt6i_siblings);
}
return rt;
* DST_OBSOLETE_FORCE_CHK which forces validation calls down
* into this function always.
*/
- if (rt->rt6i_genid != rt_genid_ipv6(dev_net(rt->dst.dev)))
- return NULL;
-
if (!rt->rt6i_node || (rt->rt6i_node->fn_sernum != cookie))
return NULL;
#include <net/snmp.h>
#include <net/dsfield.h>
#include <net/timewait_sock.h>
-#include <net/netdma.h>
#include <net/inet_common.h>
#include <net/secure_seq.h>
#include <net/tcp_memcontrol.h>
bh_lock_sock_nested(sk);
ret = 0;
if (!sock_owned_by_user(sk)) {
-#ifdef CONFIG_NET_DMA
- struct tcp_sock *tp = tcp_sk(sk);
- if (!tp->ucopy.dma_chan && tp->ucopy.pinned_list)
- tp->ucopy.dma_chan = net_dma_find_channel();
- if (tp->ucopy.dma_chan)
+ if (!tcp_prequeue(sk, skb))
ret = tcp_v6_do_rcv(sk, skb);
- else
-#endif
- {
- if (!tcp_prequeue(sk, skb))
- ret = tcp_v6_do_rcv(sk, skb);
- }
} else if (unlikely(sk_add_backlog(sk, skb,
sk->sk_rcvbuf + sk->sk_sndbuf))) {
bh_unlock_sock(sk);
if (!(flags & MSG_PEEK)) {
spin_lock_irqsave(&sk->sk_receive_queue.lock, cpu_flags);
- sk_eat_skb(sk, skb, false);
+ sk_eat_skb(sk, skb);
spin_unlock_irqrestore(&sk->sk_receive_queue.lock, cpu_flags);
*seq = 0;
}
llc_cmsg_rcv(msg, skb);
if (!(flags & MSG_PEEK)) {
- spin_lock_irqsave(&sk->sk_receive_queue.lock, cpu_flags);
- sk_eat_skb(sk, skb, false);
- spin_unlock_irqrestore(&sk->sk_receive_queue.lock, cpu_flags);
- *seq = 0;
+ spin_lock_irqsave(&sk->sk_receive_queue.lock, cpu_flags);
+ sk_eat_skb(sk, skb);
+ spin_unlock_irqrestore(&sk->sk_receive_queue.lock, cpu_flags);
+ *seq = 0;
}
goto out;
tristate '"TPROXY" target transparent proxying support'
depends on NETFILTER_XTABLES
depends on NETFILTER_ADVANCED
+ depends on (IPV6 || IPV6=n)
depends on IP_NF_MANGLE
select NF_DEFRAG_IPV4
select NF_DEFRAG_IPV6 if IP6_NF_IPTABLES
}
}
+struct nfnl_err {
+ struct list_head head;
+ struct nlmsghdr *nlh;
+ int err;
+};
+
+static int nfnl_err_add(struct list_head *list, struct nlmsghdr *nlh, int err)
+{
+ struct nfnl_err *nfnl_err;
+
+ nfnl_err = kmalloc(sizeof(struct nfnl_err), GFP_KERNEL);
+ if (nfnl_err == NULL)
+ return -ENOMEM;
+
+ nfnl_err->nlh = nlh;
+ nfnl_err->err = err;
+ list_add_tail(&nfnl_err->head, list);
+
+ return 0;
+}
+
+static void nfnl_err_del(struct nfnl_err *nfnl_err)
+{
+ list_del(&nfnl_err->head);
+ kfree(nfnl_err);
+}
+
+static void nfnl_err_reset(struct list_head *err_list)
+{
+ struct nfnl_err *nfnl_err, *next;
+
+ list_for_each_entry_safe(nfnl_err, next, err_list, head)
+ nfnl_err_del(nfnl_err);
+}
+
+static void nfnl_err_deliver(struct list_head *err_list, struct sk_buff *skb)
+{
+ struct nfnl_err *nfnl_err, *next;
+
+ list_for_each_entry_safe(nfnl_err, next, err_list, head) {
+ netlink_ack(skb, nfnl_err->nlh, nfnl_err->err);
+ nfnl_err_del(nfnl_err);
+ }
+}
+
static void nfnetlink_rcv_batch(struct sk_buff *skb, struct nlmsghdr *nlh,
u_int16_t subsys_id)
{
const struct nfnetlink_subsystem *ss;
const struct nfnl_callback *nc;
bool success = true, done = false;
+ static LIST_HEAD(err_list);
int err;
if (subsys_id >= NFNL_SUBSYS_COUNT)
type = nlh->nlmsg_type;
if (type == NFNL_MSG_BATCH_BEGIN) {
/* Malformed: Batch begin twice */
+ nfnl_err_reset(&err_list);
success = false;
goto done;
} else if (type == NFNL_MSG_BATCH_END) {
* original skb.
*/
if (err == -EAGAIN) {
+ nfnl_err_reset(&err_list);
ss->abort(skb);
nfnl_unlock(subsys_id);
kfree_skb(nskb);
}
ack:
if (nlh->nlmsg_flags & NLM_F_ACK || err) {
+ /* Errors are delivered once the full batch has been
+ * processed, this avoids that the same error is
+ * reported several times when replaying the batch.
+ */
+ if (nfnl_err_add(&err_list, nlh, err) < 0) {
+ /* We failed to enqueue an error, reset the
+ * list of errors and send OOM to userspace
+ * pointing to the batch header.
+ */
+ nfnl_err_reset(&err_list);
+ netlink_ack(skb, nlmsg_hdr(oskb), -ENOMEM);
+ success = false;
+ goto done;
+ }
/* We don't stop processing the batch on errors, thus,
* userspace gets all the errors that the batch
* triggers.
*/
- netlink_ack(skb, nlh, err);
if (err)
success = false;
}
else
ss->abort(skb);
+ nfnl_err_deliver(&err_list, oskb);
nfnl_unlock(subsys_id);
kfree_skb(nskb);
}
static void nft_hash_destroy(const struct nft_set *set)
{
const struct rhashtable *priv = nft_set_priv(set);
- const struct bucket_table *tbl;
+ const struct bucket_table *tbl = priv->tbl;
struct nft_hash_elem *he, *next;
unsigned int i;
- tbl = rht_dereference(priv->tbl, priv);
- for (i = 0; i < tbl->size; i++)
- rht_for_each_entry_safe(he, next, tbl->buckets[i], priv, node)
+ for (i = 0; i < tbl->size; i++) {
+ for (he = rht_entry(tbl->buckets[i], struct nft_hash_elem, node);
+ he != NULL; he = next) {
+ next = rht_entry(he->node.next, struct nft_hash_elem, node);
nft_hash_elem_destroy(set, he);
-
+ }
+ }
rhashtable_destroy(priv);
}
struct nft_rbtree_elem *rbe;
struct rb_node *node;
- spin_lock_bh(&nft_rbtree_lock);
while ((node = priv->root.rb_node) != NULL) {
rb_erase(node, &priv->root);
rbe = rb_entry(node, struct nft_rbtree_elem, node);
nft_rbtree_elem_destroy(set, rbe);
}
- spin_unlock_bh(&nft_rbtree_lock);
}
static bool nft_rbtree_estimate(const struct nft_set_desc *desc, u32 features,
match_idx = stack[--stackp];
cur_match = tcf_em_get_match(tree, match_idx);
- if (tcf_em_early_end(cur_match, res))
+ if (tcf_em_early_end(cur_match, res)) {
+ if (tcf_em_is_inverted(cur_match))
+ res = !res;
goto pop_stack;
- else {
+ } else {
match_idx++;
goto proceed;
}
# Don't stop modules_install if we can't sign external modules.
quiet_cmd_modules_install = INSTALL $@
- cmd_modules_install = mkdir -p $(2); cp $@ $(2) ; $(mod_strip_cmd) $(2)/$(notdir $@) ; $(mod_sign_cmd) $(2)/$(notdir $@) $(patsubst %,|| true,$(KBUILD_EXTMOD))
+ cmd_modules_install = \
+ mkdir -p $(2) ; \
+ cp $@ $(2) ; \
+ $(mod_strip_cmd) $(2)/$(notdir $@) ; \
+ $(mod_sign_cmd) $(2)/$(notdir $@) $(patsubst %,|| true,$(KBUILD_EXTMOD)) ; \
+ $(mod_compress_cmd) $(2)/$(notdir $@)
# Modules built outside the kernel source tree go into extra by default
INSTALL_MOD_DIR ?= extra
include scripts/Kbuild.include
-__modules := $(sort $(shell grep -h '\.ko' /dev/null $(wildcard $(MODVERDIR)/*.mod)))
+__modules := $(sort $(shell grep -h '\.ko$$' /dev/null $(wildcard $(MODVERDIR)/*.mod)))
modules := $(patsubst %.o,%.ko,$(wildcard $(__modules:.ko=.o)))
PHONY += $(modules)
if type in "tTdDbBrR":
# strip generated symbols
if name.startswith("__mod_"): continue
+ if name.startswith("SyS_"): continue
+ if name.startswith("compat_SyS_"): continue
if name == "linux_banner": continue
# statics and some other optimizations adds random .NUMBER
name = re.sub(r'\.[0-9]+', '', name)
%_defconfig: $(obj)/conf
$(Q)$< --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig)
+configfiles=$(wildcard $(srctree)/kernel/configs/$(1).config $(srctree)/arch/$(SRCARCH)/configs/$(1).config)
+
+define mergeconfig
+$(if $(wildcard $(objtree)/.config),, $(error You need an existing .config for this target))
+$(if $(call configfiles,$(1)),, $(error No configuration exists for this target on this architecture))
+$(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh -m -O $(objtree) $(objtree)/.config $(call configfiles,$(1))
+$(Q)yes "" | $(MAKE) -f $(srctree)/Makefile oldconfig
+endef
+
+PHONY += kvmconfig
+kvmconfig:
+ $(call mergeconfig,kvm_guest)
+
+PHONY += tinyconfig
+tinyconfig: allnoconfig
+ $(call mergeconfig,tiny)
+
# Help text used by make help
help:
@echo ' config - Update current config utilising a line-oriented program'
@echo ' randconfig - New config with random answer to all options'
@echo ' listnewconfig - List new options'
@echo ' olddefconfig - Same as silentoldconfig but sets new symbols to their default value'
+ @echo ' kvmconfig - Enable additional options for guest kernel support'
+ @echo ' tinyconfig - Configure the tiniest possible kernel'
# lxdialog stuff
check-lxdialog := $(srctree)/$(src)/lxdialog/check-lxdialog.sh
#include "../../include/linux/export.h"
/* Are we using CONFIG_MODVERSIONS? */
-int modversions = 0;
+static int modversions = 0;
/* Warn about undefined symbols? (do so if we have vmlinux) */
-int have_vmlinux = 0;
+static int have_vmlinux = 0;
/* Is CONFIG_MODULE_SRCVERSION_ALL set? */
static int all_versions = 0;
/* If we are modposting external module set to 1 */
return NULL;
}
-static struct {
+static const struct {
const char *str;
enum export export;
} export_list[] = {
}
/* sections that we do not want to do full section mismatch check on */
-static const char *section_white_list[] =
+static const char *const section_white_list[] =
{
".comment*",
".debug*",
#define MEM_EXIT_SECTIONS ".memexit.*"
/* init data sections */
-static const char *init_data_sections[] = { ALL_INIT_DATA_SECTIONS, NULL };
+static const char *const init_data_sections[] =
+ { ALL_INIT_DATA_SECTIONS, NULL };
/* all init sections */
-static const char *init_sections[] = { ALL_INIT_SECTIONS, NULL };
+static const char *const init_sections[] = { ALL_INIT_SECTIONS, NULL };
/* All init and exit sections (code + data) */
-static const char *init_exit_sections[] =
+static const char *const init_exit_sections[] =
{ALL_INIT_SECTIONS, ALL_EXIT_SECTIONS, NULL };
/* data section */
-static const char *data_sections[] = { DATA_SECTIONS, NULL };
+static const char *const data_sections[] = { DATA_SECTIONS, NULL };
/* symbols in .data that may refer to init/exit sections */
"*_probe_one", \
"*_console"
-static const char *head_sections[] = { ".head.text*", NULL };
-static const char *linker_symbols[] =
+static const char *const head_sections[] = { ".head.text*", NULL };
+static const char *const linker_symbols[] =
{ "__init_begin", "_sinittext", "_einittext", NULL };
enum mismatch {
const char *symbol_white_list[20];
};
-const struct sectioncheck sectioncheck[] = {
+static const struct sectioncheck sectioncheck[] = {
/* Do not reference init/exit code/data from
* normal code and data
*/
err = 0;
for (mod = modules; mod; mod = mod->next) {
- char fname[strlen(mod->name) + 10];
+ char fname[PATH_MAX];
if (mod->skip)
continue;
static int param_get_aabool(char *buffer, const struct kernel_param *kp);
#define param_check_aabool param_check_bool
static struct kernel_param_ops param_ops_aabool = {
- .flags = KERNEL_PARAM_FL_NOARG,
+ .flags = KERNEL_PARAM_OPS_FL_NOARG,
.set = param_set_aabool,
.get = param_get_aabool
};
static int param_get_aalockpolicy(char *buffer, const struct kernel_param *kp);
#define param_check_aalockpolicy param_check_bool
static struct kernel_param_ops param_ops_aalockpolicy = {
- .flags = KERNEL_PARAM_FL_NOARG,
+ .flags = KERNEL_PARAM_OPS_FL_NOARG,
.set = param_set_aalockpolicy,
.get = param_get_aalockpolicy
};
{ 0x04, 0xaf01 },
{ 0x08, 0x000d },
{ 0x09, 0xd810 },
- { 0x0a, 0x0060 },
+ { 0x0a, 0x0120 },
{ 0x0b, 0x0000 },
{ 0x0d, 0x2800 },
{ 0x0f, 0x0000 },
{ 0x33, 0x0208 },
{ 0x49, 0x0004 },
{ 0x4f, 0x50e9 },
- { 0x50, 0x2c00 },
+ { 0x50, 0x2000 },
{ 0x63, 0x2902 },
{ 0x67, 0x1111 },
{ 0x68, 0x1016 },
{ 0x02170700, 0x00000000 },
{ 0x02270100, 0x00000000 },
{ 0x02370100, 0x00000000 },
- { 0x02040000, 0x00004002 },
{ 0x01870700, 0x00000020 },
{ 0x00830000, 0x000000c3 },
{ 0x00930000, 0x000000c3 },
/*handle index registers*/
if (reg <= 0xff) {
rt286_hw_write(client, RT286_COEF_INDEX, reg);
- reg = RT286_PROC_COEF;
for (i = 0; i < INDEX_CACHE_SIZE; i++) {
if (reg == rt286->index_cache[i].reg) {
rt286->index_cache[i].def = value;
}
}
+ reg = RT286_PROC_COEF;
}
data[0] = (reg >> 24) & 0xff;
return -ENOMEM;
dev_set_drvdata(dev, ssm2602);
- ssm2602->type = SSM2602;
+ ssm2602->type = type;
ssm2602->regmap = regmap;
return snd_soc_register_codec(dev, &soc_codec_dev_ssm2602,
return 0;
}
-static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private,
- unsigned int fmt)
+static int _fsl_ssi_set_dai_fmt(struct device *dev,
+ struct fsl_ssi_private *ssi_private,
+ unsigned int fmt)
{
struct regmap *regs = ssi_private->regs;
u32 strcr = 0, stcr, srcr, scr, mask;
ssi_private->dai_fmt = fmt;
if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
- dev_err(&ssi_private->pdev->dev, "baudclk is missing which is necessary for master mode\n");
+ dev_err(dev, "baudclk is missing which is necessary for master mode\n");
return -EINVAL;
}
{
struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
- return _fsl_ssi_set_dai_fmt(ssi_private, fmt);
+ return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
}
/**
done:
if (ssi_private->dai_fmt)
- _fsl_ssi_set_dai_fmt(ssi_private, ssi_private->dai_fmt);
+ _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
+ ssi_private->dai_fmt);
return 0;
fe->dpcm[stream].runtime = fe_substream->runtime;
ret = dpcm_path_get(fe, stream, &list);
- if (ret < 0) {
- mutex_unlock(&fe->card->mutex);
+ if (ret < 0)
goto fe_err;
- } else if (ret == 0) {
+ else if (ret == 0)
dev_dbg(fe->dev, "ASoC: %s no valid %s route\n",
fe->dai_link->name, stream ? "capture" : "playback");
- }
/* calculate valid and active FE <-> BE dpcms */
dpcm_process_paths(fe, stream, &list, 1);
unsigned int val, mask;
void *data;
- if (!component->regmap)
+ if (!component->regmap || !params->num_regs)
return -EINVAL;
len = params->num_regs * component->val_bytes;
projects / cascardo / linux.git / commitdiff