drm/i915/bxt: backlight clock gating workaround
authorImre Deak <imre.deak@intel.com>
Tue, 1 Dec 2015 08:23:52 +0000 (10:23 +0200)
committerJani Nikula <jani.nikula@intel.com>
Wed, 2 Dec 2015 08:10:39 +0000 (10:10 +0200)
Per bspec, "Backlight PWM may stop in the asserted state, causing
backlight to stay fully on. WA: Before disabling PWM, set CLKGATE_DIS_0
0x46530 bit 13 PWM1 Gating Dis (for PWM1) or bit 14 PWM2 Gating Dis (for
PWM2). The bits can remain set without harm." (There's no workaround
name for this.)

This fixes some Broxton backlight issues.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[Jani: cleanup & commit message]
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1448958232-26520-3-git-send-email-jani.nikula@intel.com
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c

index 1a12d44..04439e8 100644 (file)
@@ -2972,6 +2972,13 @@ enum skl_disp_power_wells {
 #define OGAMC1                 _MMIO(0x30020)
 #define OGAMC0                 _MMIO(0x30024)
 
+/*
+ * GEN9 clock gating regs
+ */
+#define GEN9_CLKGATE_DIS_0             _MMIO(0x46530)
+#define   PWM2_GATING_DIS              (1 << 14)
+#define   PWM1_GATING_DIS              (1 << 13)
+
 /*
  * Display engine regs
  */
index 96f45d7..612a8b4 100644 (file)
@@ -66,6 +66,14 @@ static void bxt_init_clock_gating(struct drm_device *dev)
         */
        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
                   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
+
+       /*
+        * Wa: Backlight PWM may stop in the asserted state, causing backlight
+        * to stay fully on.
+        */
+       if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
+               I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
+                          PWM1_GATING_DIS | PWM2_GATING_DIS);
 }
 
 static void i915_pineview_get_mem_freq(struct drm_device *dev)