From: Arnd Bergmann Date: Fri, 28 Nov 2014 21:33:09 +0000 (+0100) Subject: Merge tag 'depends/phy-dt-header' into next/dt2 X-Git-Tag: v3.19-rc1~57^2~2 X-Git-Url: http://git.cascardo.info/?a=commitdiff_plain;h=b6072143e53b2e23ca3f0d404efd7b14f1456e7f;hp=2fbbc96d16009276153fd33823616877dcca30d8;p=cascardo%2Flinux.git Merge tag 'depends/phy-dt-header' into next/dt2 This is a commit that is shared with Kishon's phy repository. * tag 'depends/phy-dt-header' phy: Add PHY header file for DT x Driver defines Signed-off-by: Arnd Bergmann --- diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards index c554ed3d44fb..556c8665fdbf 100644 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ b/Documentation/devicetree/bindings/arm/arm-boards @@ -92,3 +92,68 @@ Required nodes: - core-module: the root node to the Versatile platforms must have a core-module with regs and the compatible strings "arm,core-module-versatile", "syscon" + +ARM RealView Boards +------------------- +The RealView boards cover tailored evaluation boards that are used to explore +the ARM11 and Cortex A-8 and Cortex A-9 processors. + +Required properties (in root node): + /* RealView Emulation Baseboard */ + compatible = "arm,realview-eb"; + /* RealView Platform Baseboard for ARM1176JZF-S */ + compatible = "arm,realview-pb1176"; + /* RealView Platform Baseboard for ARM11 MPCore */ + compatible = "arm,realview-pb11mp"; + /* RealView Platform Baseboard for Cortex A-8 */ + compatible = "arm,realview-pba8"; + /* RealView Platform Baseboard Explore for Cortex A-9 */ + compatible = "arm,realview-pbx"; + +Required nodes: + +- soc: some node of the RealView platforms must be the SoC + node that contain the SoC-specific devices, withe the compatible + string set to one of these tuples: + "arm,realview-eb-soc", "simple-bus" + "arm,realview-pb1176-soc", "simple-bus" + "arm,realview-pb11mp-soc", "simple-bus" + "arm,realview-pba8-soc", "simple-bus" + "arm,realview-pbx-soc", "simple-bus" + +- syscon: some subnode of the RealView SoC node must be a + system controller node pointing to the control registers, + with the compatible string set to one of these tuples: + "arm,realview-eb-syscon", "syscon" + "arm,realview-pb1176-syscon", "syscon" + "arm,realview-pb11mp-syscon", "syscon" + "arm,realview-pba8-syscon", "syscon" + "arm,realview-pbx-syscon", "syscon" + + Required properties for the system controller: + - regs: the location and size of the system controller registers, + one range of 0x1000 bytes. + +Example: + +/dts-v1/; +#include +#include "skeleton.dtsi" + +/ { + model = "ARM RealView PB1176 with device tree"; + compatible = "arm,realview-pb1176"; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,realview-pb1176-soc", "simple-bus"; + ranges; + + syscon: syscon@10000000 { + compatible = "arm,realview-syscon", "syscon"; + reg = <0x10000000 0x1000>; + }; + + }; +}; diff --git a/Documentation/devicetree/bindings/arm/bcm/cygnus.txt b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt new file mode 100644 index 000000000000..4c77169bb534 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt @@ -0,0 +1,31 @@ +Broadcom Cygnus device tree bindings +------------------------------------ + + +Boards with Cygnus SoCs shall have the following properties: + +Required root node property: + +BCM11300 +compatible = "brcm,bcm11300", "brcm,cygnus"; + +BCM11320 +compatible = "brcm,bcm11320", "brcm,cygnus"; + +BCM11350 +compatible = "brcm,bcm11350", "brcm,cygnus"; + +BCM11360 +compatible = "brcm,bcm11360", "brcm,cygnus"; + +BCM58300 +compatible = "brcm,bcm58300", "brcm,cygnus"; + +BCM58302 +compatible = "brcm,bcm58302", "brcm,cygnus"; + +BCM58303 +compatible = "brcm,bcm58303", "brcm,cygnus"; + +BCM58305 +compatible = "brcm,bcm58305", "brcm,cygnus"; diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt index c7d2fa156678..b38608af66db 100644 --- a/Documentation/devicetree/bindings/arm/gic.txt +++ b/Documentation/devicetree/bindings/arm/gic.txt @@ -17,6 +17,7 @@ Main node required properties: "arm,cortex-a7-gic" "arm,arm11mp-gic" "brcm,brahma-b15-gic" + "arm,arm1176jzf-devchip-gic" - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. The type shall be a and the value shall be 3. diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt index 904de5781f44..a99eb9eb14c0 100644 --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt @@ -106,11 +106,21 @@ Required subnode-properties: - groups: a list of strings describing the group names. - function: a string describing the function used to mux the groups. +* Reset controller binding + +A reset controller is part of the chip control registers set. The chip control +node also provides the reset. The register set is not at the same offset between +Berlin SoCs. + +Required property: +- #reset-cells: must be set to 2 + Example: chip: chip-control@ea0000 { compatible = "marvell,berlin2-chip-ctrl"; #clock-cells = <1>; + #reset-cells = <2>; reg = <0xea0000 0x400>; clocks = <&refclk>, <&externaldev 0>; clock-names = "refclk", "video_ext0"; diff --git a/Documentation/devicetree/bindings/arm/ste-nomadik.txt b/Documentation/devicetree/bindings/arm/ste-nomadik.txt index 6256ec31666d..2fdff5a806cf 100644 --- a/Documentation/devicetree/bindings/arm/ste-nomadik.txt +++ b/Documentation/devicetree/bindings/arm/ste-nomadik.txt @@ -10,6 +10,12 @@ Required root node property: src Boards with the Nomadik SoC include: +Nomadik NHK-15 board manufactured by ST Microelectronics: + +Required root node property: + +compatible="st,nomadik-nhk-15"; + S8815 "MiniKit" manufactured by Calao Systems: Required root node property: diff --git a/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt new file mode 100644 index 000000000000..00d26edec8bc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt @@ -0,0 +1,34 @@ +Broadcom Cygnus Clocks + +This binding uses the common clock binding: +Documentation/devicetree/bindings/clock/clock-bindings.txt + +Currently various "fixed" clocks are declared for peripheral drivers that use +the common clock framework to reference their core clocks. Proper support of +these clocks will be added later + +Device tree example: + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + }; + + apb_clk: apb_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + periph_clk: periph_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + }; + }; diff --git a/Documentation/devicetree/bindings/dma/atmel-xdma.txt b/Documentation/devicetree/bindings/dma/atmel-xdma.txt new file mode 100644 index 000000000000..0eb2b3207e08 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/atmel-xdma.txt @@ -0,0 +1,54 @@ +* Atmel Extensible Direct Memory Access Controller (XDMAC) + +* XDMA Controller +Required properties: +- compatible: Should be "atmel,-dma". + compatible description: + - sama5d4: first SoC adding the XDMAC +- reg: Should contain DMA registers location and length. +- interrupts: Should contain DMA interrupt. +- #dma-cells: Must be <1>, used to represent the number of integer cells in +the dmas property of client devices. + - The 1st cell specifies the channel configuration register: + - bit 13: SIF, source interface identifier, used to get the memory + interface identifier, + - bit 14: DIF, destination interface identifier, used to get the peripheral + interface identifier, + - bit 30-24: PERID, peripheral identifier. + +Example: + +dma1: dma-controller@f0004000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0004000 0x200>; + interrupts = <50 4 0>; + #dma-cells = <1>; +}; + + +* DMA clients +DMA clients connected to the Atmel XDMA controller must use the format +described in the dma.txt file, using a one-cell specifier for each channel. +The two cells in order are: +1. A phandle pointing to the DMA controller. +2. Channel configuration register. Configurable fields are: + - bit 13: SIF, source interface identifier, used to get the memory + interface identifier, + - bit 14: DIF, destination interface identifier, used to get the peripheral + interface identifier, + - bit 30-24: PERID, peripheral identifier. + +Example: + +i2c2: i2c@f8024000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8024000 0x4000>; + interrupts = <34 4 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(6))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; +}; diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index fbde415078e6..605dcca5dbec 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -56,6 +56,8 @@ gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire In infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) isl,isl12057 Intersil ISL12057 I2C RTC Chip +isil,isl29028 (deprecated, use isl) +isl,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface diff --git a/Documentation/devicetree/bindings/timer/renesas,mtu2.txt b/Documentation/devicetree/bindings/timer/renesas,mtu2.txt index d9a8d5af1a21..ba0a34d97eb8 100644 --- a/Documentation/devicetree/bindings/timer/renesas,mtu2.txt +++ b/Documentation/devicetree/bindings/timer/renesas,mtu2.txt @@ -1,4 +1,4 @@ -* Renesas R-Car Multi-Function Timer Pulse Unit 2 (MTU2) +* Renesas Multi-Function Timer Pulse Unit 2 (MTU2) The MTU2 is a multi-purpose, multi-channel timer/counter with configurable clock inputs and programmable compare match. diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.txt b/Documentation/devicetree/bindings/timer/renesas,tmu.txt index 7db89fb25444..cd5f20bf2582 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.txt +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.txt @@ -1,4 +1,4 @@ -* Renesas R-Car Timer Unit (TMU) +* Renesas R-Mobile/R-Car Timer Unit (TMU) The TMU is a 32-bit timer/counter with configurable clock inputs and programmable compare match. @@ -9,6 +9,8 @@ are independent. The TMU hardware supports up to three channels. Required Properties: - compatible: must contain one or more of the following: + - "renesas,tmu-r8a7740" for the r8a7740 TMU + - "renesas,tmu-r8a7778" for the r8a7778 TMU - "renesas,tmu-r8a7779" for the r8a7779 TMU - "renesas,tmu" for any TMU. This is a fallback for the above renesas,tmu-* entries diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 723999d73744..bfbd93e06bae 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -77,6 +77,7 @@ innolux Innolux Corporation intel Intel Corporation intercontrol Inter Control Group isee ISEE 2007 S.L. +isil Intersil (deprecated, use isl) isl Intersil karo Ka-Ro electronics GmbH keymile Keymile GmbH diff --git a/MAINTAINERS b/MAINTAINERS index ea4d0058fd1b..2b87aee48ab0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1714,6 +1714,13 @@ F: drivers/dma/at_hdmac.c F: drivers/dma/at_hdmac_regs.h F: include/linux/platform_data/dma-atmel.h +ATMEL XDMA DRIVER +M: Ludovic Desroches +L: linux-arm-kernel@lists.infradead.org +L: dmaengine@vger.kernel.org +S: Supported +F: drivers/dma/at_xdmac.c + ATMEL I2C DRIVER M: Ludovic Desroches L: linux-i2c@vger.kernel.org diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 38c89cafa1ab..bbce4f434178 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -54,8 +54,12 @@ dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b-plus.dtb dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb +dtb-$(CONFIG_ARCH_BCM_CYGNUS) += bcm911360_entphn.dtb \ + bcm911360k.dtb \ + bcm958300k.dtb dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ bcm21664-garnet.dtb dtb-$(CONFIG_ARCH_BERLIN) += \ @@ -81,6 +85,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ + exynos5250-spring.dtb \ exynos5260-xyref5260.dtb \ exynos5410-smdk5410.dtb \ exynos5420-arndale-octa.dtb \ @@ -104,6 +109,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ kirkwood-d2net.dtb \ kirkwood-db-88f6281.dtb \ kirkwood-db-88f6282.dtb \ + kirkwood-dir665.dtb \ kirkwood-dns320.dtb \ kirkwood-dns325.dtb \ kirkwood-dockstar.dtb \ @@ -274,7 +280,8 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx28-m28evk.dtb \ imx28-sps1.dtb \ imx28-tx28.dtb -dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb +dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb \ + ste-nomadik-nhk15.dtb dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ nspire-tp.dtb \ nspire-clp.dtb @@ -302,7 +309,9 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ omap3-ha.dtb \ omap3-ha-lcd.dtb \ omap3-igep0020.dtb \ + omap3-igep0020-rev-f.dtb \ omap3-igep0030.dtb \ + omap3-igep0030-rev-g.dtb \ omap3-ldp.dtb \ omap3-lilly-dbb056.dtb \ omap3-n900.dtb \ @@ -347,6 +356,7 @@ dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ omap5-sbc-t54.dtb \ omap5-uevm.dtb dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \ + am57xx-beagle-x15.dtb \ dra72-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ orion5x-lacie-ethernet-disk-mini-v2.dtb \ @@ -363,6 +373,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ qcom-msm8974-sony-xperia-honami.dtb +dtb-$(CONFIG_ARCH_REALVIEW) += arm-realview-pb1176.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3066a-bqcurie2.dtb \ rk3188-radxarock.dtb \ @@ -376,25 +387,25 @@ dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \ s5pv210-smdkc110.dtb \ s5pv210-smdkv210.dtb \ s5pv210-torbreck.dtb -dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \ +dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \ + r8a73a4-ape6evm.dtb \ + r8a73a4-ape6evm-reference.dtb \ r8a7740-armadillo800eva.dtb \ r8a7778-bockw.dtb \ r8a7778-bockw-reference.dtb \ r8a7779-marzen.dtb \ - r8a7791-koelsch.dtb \ r8a7790-lager.dtb \ + r8a7791-koelsch.dtb \ + sh7372-mackerel.dtb \ sh73a0-kzm9g.dtb \ - sh73a0-kzm9g-reference.dtb \ - r8a73a4-ape6evm.dtb \ - r8a73a4-ape6evm-reference.dtb \ - sh7372-mackerel.dtb + sh73a0-kzm9g-reference.dtb dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ r7s72100-genmai.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7779-marzen.dtb \ + r8a7790-lager.dtb \ r8a7791-henninger.dtb \ r8a7791-koelsch.dtb \ - r8a7790-lager.dtb \ - r8a7779-marzen.dtb \ r8a7794-alt.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ socfpga_cyclone5_socdk.dtb \ diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index e2156a583de7..43a536c08c9f 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -437,9 +437,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nandflash_pins_s0>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index a1a0cc5eb35c..c0e1135256cc 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -126,10 +126,10 @@ pinctrl-names = "default"; pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; gpmc,device-width = <1>; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 831810583823..62bf053d2cb8 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -204,6 +204,8 @@ reg = <0x44e09000 0x2000>; interrupts = <72>; status = "disabled"; + dmas = <&edma 26>, <&edma 27>; + dma-names = "tx", "rx"; }; uart1: serial@48022000 { @@ -213,6 +215,8 @@ reg = <0x48022000 0x2000>; interrupts = <73>; status = "disabled"; + dmas = <&edma 28>, <&edma 29>; + dma-names = "tx", "rx"; }; uart2: serial@48024000 { @@ -222,6 +226,8 @@ reg = <0x48024000 0x2000>; interrupts = <74>; status = "disabled"; + dmas = <&edma 30>, <&edma 31>; + dma-names = "tx", "rx"; }; uart3: serial@481a6000 { @@ -356,6 +362,7 @@ reg = <0x480C8000 0x200>; interrupts = <77>; ti,hwmods = "mailbox"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; mbox_wkupm3: wkup_m3 { diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 46660ffd2b65..4367f7550183 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -168,6 +168,7 @@ reg = <0x480C8000 0x200>; interrupts = ; ti,hwmods = "mailbox"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; mbox_wkupm3: wkup_m3 { diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index ac3e4859935f..bb4cb8554b4a 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -438,9 +438,9 @@ status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ pinctrl-names = "default"; pinctrl-0 = <&nand_flash_x8>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts new file mode 100644 index 000000000000..49edbda68cd5 --- /dev/null +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -0,0 +1,405 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra74x.dtsi" +#include +#include +#include + +/ { + model = "TI AM5728 BeagleBoard-X15"; + compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; + + aliases { + rtc0 = &mcp_rtc; + rtc1 = &tps659038_rtc; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + vdd_3v3: fixedregulator-vdd_3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <®en1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&smps3_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>; + + led@0 { + label = "beagle-x15:usr0"; + gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@1 { + label = "beagle-x15:usr1"; + gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led@2 { + label = "beagle-x15:usr2"; + gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@3 { + label = "beagle-x15:usr3"; + gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "ide-disk"; + default-state = "off"; + }; + }; +}; + +&dra7_pmx_core { + leds_pins_default: leds_pins_default { + pinctrl-single,pins = < + 0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */ + 0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */ + 0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */ + 0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */ + >; + }; + + i2c1_pins_default: i2c1_pins_default { + pinctrl-single,pins = < + 0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ + 0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ + >; + }; + + i2c3_pins_default: i2c3_pins_default { + pinctrl-single,pins = < + 0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ + 0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ + >; + }; + + uart3_pins_default: uart3_pins_default { + pinctrl-single,pins = < + 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */ + 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */ + >; + }; + + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + tps659038_pins_default: tps659038_pins_default { + pinctrl-single,pins = < + 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ + >; + }; + + tmp102_pins_default: tmp102_pins_default { + pinctrl-single,pins = < + 0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */ + >; + }; + + mcp79410_pins_default: mcp79410_pins_default { + pinctrl-single,pins = < + 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ + >; + }; + + usb1_pins: pinmux_usb1_pins { + pinctrl-single,pins = < + 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ + >; + }; + +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_default>; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&tps659038_pins_default>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + regulators { + smps12_reg: smps12 { + /* VDD_MPU */ + regulator-name = "smps12"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps3_reg: smps3 { + /* VDD_DDR */ + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_CORE */ + regulator-name = "smps6"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1030000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS7 unused */ + + smps8_reg: smps8 { + /* VDD_1V8 */ + regulator-name = "smps8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS9 unused */ + + ldo1_reg: ldo1 { + /* VDD_SD */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + ldo2_reg: ldo2 { + /* VDD_SHV5 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + }; + + tmp102: tmp102@48 { + compatible = "ti,tmp102"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&tmp102_pins_default>; + interrupt-parent = <&gpio7>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_default>; + clock-frequency = <400000>; + + mcp_rtc: rtc@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + interrupt-parent = <&gic>; + interrupts = ; /* IRQ_SYS_1N */ + + pinctrl-names = "default"; + pinctrl-0 = <&mcp79410_pins_default>; + + vcc-supply = <&vdd_3v3>; + wakeup-source; + }; +}; + +&gpio7 { + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&cpu0 { + cpu0-supply = <&smps12_reg>; + voltage-tolerance = <1>; +}; + +&uart3 { + status = "okay"; + interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x248>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_default>; +}; + +&mmc1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + + vmmc-supply = <&ldo1_reg>; + vmmc_aux-supply = <&vdd_3v3>; + pbias-supply = <&pbias_mmc_reg>; + bus-width = <4>; + cd-gpios = <&gpio6 27 0>; /* gpio 219 */ +}; + +&mmc2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; + + vmmc-supply = <&vdd_3v3>; + bus-width = <8>; + ti,non-removable; + cap-mmc-dual-data-rate; +}; + +&sata { + status = "okay"; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; +}; diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts new file mode 100644 index 000000000000..ff26c7ed8c41 --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -0,0 +1,412 @@ +/* + * Copyright 2014 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include +#include +#include "skeleton.dtsi" + +/ { + model = "ARM RealView PB1176"; + compatible = "arm,realview-pb1176"; + + chosen { }; + + aliases { + serial0 = &pb1176_serial0; + serial1 = &pb1176_serial1; + serial2 = &pb1176_serial2; + serial3 = &pb1176_serial3; + serial4 = &fpga_serial; + }; + + memory { + /* 128 MiB memory @ 0x0 */ + reg = <0x00000000 0x08000000>; + }; + + /* The voltage to the MMC card is hardwired at 3.3V */ + vmmc: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + xtal24mhz: xtal24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + mclk: mclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + kmiclk: kmiclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + sspclk: sspclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + uartclk: uartclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + /* FIXME: this actually hangs off the PLL clocks */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,realview-pb1176-soc", "simple-bus"; + regmap = <&syscon>; + ranges; + + syscon: syscon@10000000 { + compatible = "arm,realview-pb1176-syscon", "syscon"; + reg = <0x10000000 0x1000>; + + led@08.0 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x01>; + label = "versatile:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@08.1 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x02>; + label = "versatile:1"; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + led@08.2 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x04>; + label = "versatile:2"; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + led@08.3 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x08>; + label = "versatile:3"; + default-state = "off"; + }; + led@08.4 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x10>; + label = "versatile:4"; + default-state = "off"; + }; + led@08.5 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x20>; + label = "versatile:5"; + default-state = "off"; + }; + led@08.6 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x40>; + label = "versatile:6"; + default-state = "off"; + }; + led@08.7 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x80>; + label = "versatile:7"; + default-state = "off"; + }; + }; + + /* Primary DevChip GIC synthesized with the CPU */ + intc_dc1176: interrupt-controller@10120000 { + compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x10121000 0x1000>, + <0x10120000 0x100>; + }; + + L2: l2-cache { + compatible = "arm,l220-cache"; + reg = <0x10110000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + /* + * Override default cache size, sets and + * associativity as these may be erroneously set + * up by boot loader(s). + */ + arm,override-auxreg; + cache-size = <131072>; // 128kB + cache-sets = <512>; + cache-line-size = <32>; + }; + + pmu { + compatible = "arm,arm1176-pmu"; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer01: timer@10104000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10104000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer23: timer@10105000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10105000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + arm,sp804-has-irq = <1>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + pb1176_rtc: rtc@10108000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x10108000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + pb1176_gpio0: gpio@1010a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1010a000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + pb1176_ssp: ssp@1010b000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x1010b000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sspclk>, <&pclk>; + clock-names = "SSPCLK", "apb_pclk"; + }; + + pb1176_serial0: serial@1010c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1010c000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + pb1176_serial1: serial@1010d000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1010d000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + pb1176_serial2: serial@1010e000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1010e000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + pb1176_serial3: serial@1010f000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1010f000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + }; + + /* These peripherals are inside the FPGA rather than the DevChip */ + fpga { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + fpga_mci: mmcsd@10005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x10005000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>; + /* Due to frequent FIFO overruns, use just 500 kHz */ + max-frequency = <500000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + clocks = <&mclk>, <&pclk>; + clock-names = "mclk", "apb_pclk"; + vmmc-supply = <&vmmc>; + cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; + }; + + fpga_kmi0: kmi@10006000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10006000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + fpga_kmi1: kmi@10007000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10007000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + fpga_charlcd: charlcd@10008000 { + compatible = "arm,versatile-lcd"; + reg = <0x10008000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + fpga_serial: serial@10009000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x10009000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + /* This GIC on the board is cascaded off the DevChip GIC */ + intc_fpga1176: interrupt-controller@10040000 { + compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x10041000 0x1000>, + <0x10040000 0x100>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + }; + + fpga_gpio0: gpio@10014000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10014000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + fpga_gpio1: gpio@10015000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10015000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + fpga_rtc: rtc@10017000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x10017000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + + }; +}; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 3aebd93cc33c..1e38628f4060 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -35,7 +35,7 @@ pcie-controller { status = "okay"; - /* Connected to Marvell SATA controller */ + /* Connected to Marvell 88SE9170 SATA controller */ pcie@1,0 { /* Port 0, Lane 0 */ status = "okay"; @@ -53,8 +53,9 @@ status = "okay"; }; + /* eSATA interface */ sata@a0000 { - nr-ports = <2>; + nr-ports = <1>; status = "okay"; }; @@ -204,20 +205,20 @@ default-state = "keep"; }; - green-sata1-led { - label = "rn102:green:sata1"; + blue-sata1-led { + label = "rn102:blue:sata1"; gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; default-state = "on"; }; - green-sata2-led { - label = "rn102:green:sata2"; + blue-sata2-led { + label = "rn102:blue:sata2"; gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; default-state = "on"; }; - green-backup-led { - label = "rn102:green:backup"; + blue-backup-led { + label = "rn102:blue:backup"; gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; default-state = "on"; }; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 6b3c23b1e138..7851942e244a 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -95,6 +95,7 @@ compatible = "marvell,aurora-outer-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; + cache-unified; wt-override; }; diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index de6571445cef..9721e55384ce 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -36,6 +36,12 @@ #clock-cells = <0>; clock-frequency = <2000000000>; }; + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; }; cpus { @@ -366,13 +372,15 @@ <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <&mpic 5>, <&mpic 6>; - clocks = <&coreclk 0>; + clocks = <&coreclk 0>, <&refclk>; + clock-names = "nbclk", "fixed"; }; watchdog@20300 { compatible = "marvell,armada-375-wdt"; reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; - clocks = <&coreclk 0>; + clocks = <&coreclk 0>, <&refclk>; + clock-names = "nbclk", "fixed"; }; cpurst@20800 { diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index a55a97a70505..0e53fad111de 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -60,40 +60,6 @@ }; internal-regs { - pinctrl { - pinctrl-0 = <&pmx_phy_int>; - pinctrl-names = "default"; - - pmx_ge0: pmx-ge0 { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", "mpp11"; - marvell,function = "ge0"; - }; - - pmx_ge1: pmx-ge1 { - marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", - "mpp16", "mpp17", "mpp18", "mpp19", - "mpp20", "mpp21", "mpp22", "mpp23"; - marvell,function = "ge1"; - }; - - pmx_keys: pmx-keys { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - pmx_spi: pmx-spi { - marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; - marvell,function = "spi"; - }; - - pmx_phy_int: pmx-phy-int { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - }; - serial@12000 { status = "okay"; }; @@ -118,14 +84,14 @@ }; ethernet@70000 { - pinctrl-0 = <&pmx_ge0>; + pinctrl-0 = <&pmx_ge0_rgmii>; pinctrl-names = "default"; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@74000 { - pinctrl-0 = <&pmx_ge1>; + pinctrl-0 = <&pmx_ge1_rgmii>; pinctrl-names = "default"; status = "okay"; phy = <&phy1>; @@ -162,3 +128,23 @@ }; }; }; + +&pinctrl { + pinctrl-0 = <&pmx_phy_int>; + pinctrl-names = "default"; + + pmx_keys: pmx-keys { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + pmx_spi: pmx-spi { + marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; + marvell,function = "spi"; + }; + + pmx_phy_int: pmx-phy-int { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts index 469cf7137595..aa5463c91924 100644 --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts @@ -51,37 +51,6 @@ }; internal-regs { - pinctrl { - poweroff_pin: poweroff-pin { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - select_button_pin: select-button-pin { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - scroll_button_pin: scroll-button-pin { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - hdd_led_pin: hdd-led-pin { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - }; - serial@12000 { status = "okay"; }; @@ -97,12 +66,16 @@ }; ethernet@70000 { + pinctrl-0 = <&pmx_ge0_rgmii>; + pinctrl-names = "default"; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@74000 { + pinctrl-0 = <&pmx_ge1_rgmii>; + pinctrl-names = "default"; status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; @@ -125,6 +98,11 @@ reg = <0x2e>; }; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + pcf8563@51 { compatible = "nxp,pcf8563"; reg = <0x51>; @@ -226,7 +204,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0>; - registers-number = <2>; + registers-number = <1>; spi-max-frequency = <100000>; }; }; @@ -282,3 +260,34 @@ gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; }; }; + +&pinctrl { + poweroff_pin: poweroff-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + select_button_pin: select-button-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + scroll_button_pin: scroll-button-pin { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + hdd_led_pin: hdd-led-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 2592e1c13560..281ccd24295c 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -167,17 +167,6 @@ }; internal-regs { - pinctrl { - compatible = "marvell,mv78230-pinctrl"; - reg = <0x18000 0x38>; - - sdio_pins: sdio-pins { - marvell,pins = "mpp30", "mpp31", "mpp32", - "mpp33", "mpp34", "mpp35"; - marvell,function = "sd0"; - }; - }; - gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; reg = <0x18100 0x40>; @@ -202,3 +191,7 @@ }; }; }; + +&pinctrl { + compatible = "marvell,mv78230-pinctrl"; +}; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 480e237a870f..d7a8d0b0f385 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -251,17 +251,6 @@ }; internal-regs { - pinctrl { - compatible = "marvell,mv78260-pinctrl"; - reg = <0x18000 0x38>; - - sdio_pins: sdio-pins { - marvell,pins = "mpp30", "mpp31", "mpp32", - "mpp33", "mpp34", "mpp35"; - marvell,function = "sd0"; - }; - }; - gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; reg = <0x18100 0x40>; @@ -305,3 +294,7 @@ }; }; }; + +&pinctrl { + compatible = "marvell,mv78260-pinctrl"; +}; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 2c7b1fef4703..9c40c130d11a 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -289,17 +289,6 @@ }; internal-regs { - pinctrl { - compatible = "marvell,mv78460-pinctrl"; - reg = <0x18000 0x38>; - - sdio_pins: sdio-pins { - marvell,pins = "mpp30", "mpp31", "mpp32", - "mpp33", "mpp34", "mpp35"; - marvell,function = "sd0"; - }; - }; - gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; reg = <0x18100 0x40>; @@ -343,3 +332,7 @@ }; }; }; + +&pinctrl { + compatible = "marvell,mv78460-pinctrl"; +}; diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index 7d8f32873e82..d81430aa4ab3 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -55,86 +55,10 @@ }; internal-regs { - pinctrl { - poweroff: poweroff { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - sata1_led_pin: sata1-led-pin { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - sata2_led_pin: sata2-led-pin { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - sata3_led_pin: sata3-led-pin { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - sata4_led_pin: sata4-led-pin { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - sata1_power_pin: sata1-power-pin { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - sata2_power_pin: sata2-power-pin { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - sata3_power_pin: sata3-power-pin { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - sata4_power_pin: sata4-power-pin { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - sata1_pres_pin: sata1-pres-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - sata2_pres_pin: sata2-pres-pin { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - sata3_pres_pin: sata3-pres-pin { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - sata4_pres_pin: sata4-pres-pin { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - - err_led_pin: err-led-pin { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; + /* Two rear eSATA ports */ + sata@a0000 { + nr-ports = <2>; + status = "okay"; }; serial@12000 { @@ -328,3 +252,85 @@ gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; }; + +&pinctrl { + poweroff: poweroff { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + sata1_led_pin: sata1-led-pin { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + sata2_led_pin: sata2-led-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + sata3_led_pin: sata3-led-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + sata4_led_pin: sata4-led-pin { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + sata1_power_pin: sata1-power-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + sata2_power_pin: sata2-power-pin { + marvell,pins = "mpp25"; + marvell,function = "gpio"; + }; + + sata3_power_pin: sata3-power-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + sata4_power_pin: sata4-power-pin { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + sata1_pres_pin: sata1-pres-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + + sata2_pres_pin: sata2-pres-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + sata3_pres_pin: sata3-pres-pin { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + sata4_pres_pin: sata4-pres-pin { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + err_led_pin: err-led-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 4e5a59ee1501..6f6b0916df48 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -77,12 +77,7 @@ serial@12100 { status = "okay"; }; - pinctrl { - led_pins: led-pins-0 { - marvell,pins = "mpp49", "mpp51", "mpp53"; - marvell,function = "gpio"; - }; - }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -187,3 +182,10 @@ }; }; }; + +&pinctrl { + led_pins: led-pins-0 { + marvell,pins = "mpp49", "mpp51", "mpp53"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index bff9f6c18db1..a3919b644737 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -39,6 +39,7 @@ compatible = "marvell,aurora-system-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; + cache-unified; wt-override; }; @@ -71,6 +72,43 @@ status = "disabled"; }; + pinctrl: pin-ctrl@18000 { + reg = <0x18000 0x38>; + + pmx_ge0_gmii: pmx-ge0-gmii { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11", + "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19", + "mpp20", "mpp21", "mpp22", "mpp23"; + marvell,function = "ge0"; + }; + + pmx_ge0_rgmii: pmx-ge0-rgmii { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11"; + marvell,function = "ge0"; + }; + + pmx_ge1_rgmii: pmx-ge1-rgmii { + marvell,pins = + "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19", + "mpp20", "mpp21", "mpp22", "mpp23"; + marvell,function = "ge1"; + }; + + sdio_pins: sdio-pins { + marvell,pins = "mpp30", "mpp31", "mpp32", + "mpp33", "mpp34", "mpp35"; + marvell,function = "sd0"; + }; + }; + system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; reg = <0x18200 0x500>; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index b5b84006469e..9198b719d0ef 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -9,12 +9,12 @@ * licensing only applies to this file, and not this project as a * whole. * - * a) This library is free software; you can redistribute it and/or + * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * - * This library is distributed in the hope that it will be useful, + * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index cb100b03a362..dd1313cbc314 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -956,6 +956,14 @@ }; }; + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + watchdog@fffffd40 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; @@ -966,6 +974,12 @@ atmel,idle-halt; status = "disabled"; }; + + gpbr: syscon@fffffd50 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd50 0x10>; + status = "disabled"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index a81aab4281a7..cdb9ed612109 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -828,12 +828,26 @@ clocks = <&mck>; }; + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + watchdog@fffffd40 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; status = "disabled"; }; + + gpbr: syscon@fffffd50 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd50 0x10>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 51416c7d0625..1467750e3377 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -677,6 +677,14 @@ }; }; + can { + pinctrl_can_rx_tx: can_rx_tx { + atmel,pins = + ; /* CANTX, conflicts with PCK0 */ + }; + }; + pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; @@ -905,6 +913,38 @@ clock-names = "pwm_clk"; status = "disabled"; }; + + can: can@fffac000 { + compatible = "atmel,at91sam9263-can"; + reg = <0xfffac000 0x300>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_rx_tx>; + clocks = <&can_clk>; + clock-names = "can_clk"; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + + rtc@fffffd50 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd50 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + + gpbr: syscon@fffffd60 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd60 0x50>; + status = "disabled"; + }; }; fb0: fb@0x00700000 { diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index d2919108e92d..dfaacb113f2e 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -112,9 +112,23 @@ }; }; + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + watchdog@fffffd40 { status = "okay"; }; + + gpbr: syscon@fffffd50 { + status = "okay"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index d3f65130a1f8..c13424228d06 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -492,6 +492,27 @@ }; }; + isi { + pinctrl_isi: isi-0 { + atmel,pins = ; + }; + }; + usart0 { pinctrl_usart0: usart0-0 { atmel,pins = @@ -1028,6 +1049,17 @@ }; }; + isi@fffb4000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xfffb4000 0x4000>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&isi_clk>; + clock-names = "isi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi>; + status = "disabled"; + }; + pwm0: pwm@fffb8000 { compatible = "atmel,at91sam9rl-pwm"; reg = <0xfffb8000 0x300>; @@ -1192,12 +1224,26 @@ }; }; + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + rtc@fffffdb0 { compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffdb0 0x30>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; status = "disabled"; }; + + gpbr: syscon@fffffd60 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd60 0x10>; + status = "disabled"; + }; }; fb0: fb@0x00500000 { diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index d8dd22651090..33ce7ca2c404 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -161,6 +161,15 @@ pinctrl-0 = <&pinctrl_pwm_leds>; }; + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + + gpbr: syscon@fffffd60 { + status = "okay"; + }; + rtc@fffffdb0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index f0b4352650ed..72424371413e 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -1059,6 +1059,27 @@ clocks = <&slow_rc_osc &slow_osc>; }; }; + + rtc@fffffeb0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffeb0 0x40>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + status = "disabled"; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + gpbr: syscon@fffffd60 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd60 0x10>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi index c2554219f7a4..3c5fa3388997 100644 --- a/arch/arm/boot/dts/at91sam9x25.dtsi +++ b/arch/arm/boot/dts/at91sam9x25.dtsi @@ -10,6 +10,7 @@ #include "at91sam9x5_usart3.dtsi" #include "at91sam9x5_macb0.dtsi" #include "at91sam9x5_macb1.dtsi" +#include "at91sam9x5_can.dtsi" / { model = "Atmel AT91SAM9X25 SoC"; diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi index 8eac66ce0ab7..499cdc81f4c0 100644 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ b/arch/arm/boot/dts/at91sam9x35.dtsi @@ -8,6 +8,7 @@ #include "at91sam9x5.dtsi" #include "at91sam9x5_macb0.dtsi" +#include "at91sam9x5_can.dtsi" / { model = "Atmel AT91SAM9X35 SoC"; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 726274f7959b..bbb3ba65165f 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -860,6 +860,9 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; clocks = <&mck>; clock-names = "usart"; status = "disabled"; @@ -871,6 +874,9 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; clocks = <&usart0_clk>; clock-names = "usart"; status = "disabled"; @@ -882,6 +888,9 @@ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>, + <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; clocks = <&usart1_clk>; clock-names = "usart"; status = "disabled"; @@ -893,6 +902,9 @@ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; clocks = <&usart2_clk>; clock-names = "usart"; status = "disabled"; diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi index f44ab7702a12..8eb2f9c1b978 100644 --- a/arch/arm/boot/dts/at91sam9x5_can.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi @@ -1,5 +1,5 @@ /* - * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 + * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 * Ethernet interface. * * Copyright (C) 2013 Boris BREZILLON @@ -20,10 +20,50 @@ reg = <29>; }; - can1_clk: can1_clk { - #clock-cells = <0>; - reg = <30>; - }; + can1_clk: can1_clk { + #clock-cells = <0>; + reg = <30>; + }; + }; + }; + + can0: can@f8000000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8000000 0x300>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + clocks = <&can0_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + + can1: can@f8004000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8004000 0x300>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + clocks = <&can1_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + + pinctrl@fffff400 { + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + ; /* CANTX0, conflicts with DTXD */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + ; /* CANTX1, conflicts with TXD1 */ + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi index 140217a54384..43bb5b51caa6 100644 --- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi @@ -57,6 +57,9 @@ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; clocks = <&usart3_clk>; clock-names = "usart"; status = "disabled"; diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi new file mode 100644 index 000000000000..60d8389fdb6c --- /dev/null +++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi @@ -0,0 +1,91 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + }; + + apb_clk: apb_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + periph_clk: periph_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + }; + + sdio_clk: lcpll_ch2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + axi81_clk: axi81_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + keypad_clk: keypad_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <31806>; + }; + + adc_clk: adc_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1562500>; + }; + + pwm_clk: pwm_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + + lcd_clk: mipipll_ch1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi new file mode 100644 index 000000000000..5126f9e77a98 --- /dev/null +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -0,0 +1,140 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "skeleton.dtsi" + +/ { + compatible = "brcm,cygnus"; + model = "Broadcom Cygnus SoC"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + }; + + /include/ "bcm-cygnus-clock.dtsi" + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus", "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + wdt@18009000 { + compatible = "arm,sp805" , "arm,primecell"; + reg = <0x18009000 0x1000>; + interrupts = ; + clocks = <&axi81_clk>; + clock-names = "apb_pclk"; + }; + }; + + uart0: serial@18020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x18020000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&axi81_clk>; + clock-frequency = <100000000>; + status = "disabled"; + }; + + uart1: serial@18021000 { + compatible = "snps,dw-apb-uart"; + reg = <0x18021000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&axi81_clk>; + clock-frequency = <100000000>; + status = "disabled"; + }; + + uart2: serial@18022000 { + compatible = "snps,dw-apb-uart"; + reg = <0x18020000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&axi81_clk>; + clock-frequency = <100000000>; + status = "disabled"; + }; + + uart3: serial@18023000 { + compatible = "snps,dw-apb-uart"; + reg = <0x18023000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&axi81_clk>; + clock-frequency = <100000000>; + status = "disabled"; + }; + + gic: interrupt-controller@19021000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x19021000 0x1000>, + <0x19020100 0x100>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0x19022000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + timer@19020200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x19020200 0x100>; + interrupts = ; + clocks = <&periph_clk>; + }; + +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts new file mode 100644 index 000000000000..e479515099c3 --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -0,0 +1,30 @@ +/dts-v1/; +/include/ "bcm2835-rpi.dtsi" + +/ { + compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; + model = "Raspberry Pi Model B+"; + + leds { + act { + gpios = <&gpio 47 0>; + }; + + pwr { + label = "PWR"; + gpios = <&gpio 35 0>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; + }; +}; + +&gpio { + pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; + + /* I2S interface */ + i2s_alt0: i2s_alt0 { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 58a0d60b95f1..bafa46fc226a 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -1,63 +1,23 @@ /dts-v1/; -/include/ "bcm2835.dtsi" +/include/ "bcm2835-rpi.dtsi" / { compatible = "raspberrypi,model-b", "brcm,bcm2835"; model = "Raspberry Pi Model B"; - memory { - reg = <0 0x10000000>; - }; - leds { - compatible = "gpio-leds"; - act { - label = "ACT"; gpios = <&gpio 16 1>; - default-state = "keep"; - linux,default-trigger = "heartbeat"; }; }; }; &gpio { - pinctrl-names = "default"; - pinctrl-0 = <&gpioout &alt0 &alt2 &alt3>; - - gpioout: gpioout { - brcm,pins = <6>; - brcm,function = <1>; /* GPIO out */ - }; - - alt0: alt0 { - brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; - brcm,function = <4>; /* alt0 */ - }; - - alt3: alt3 { - brcm,pins = <48 49 50 51 52 53>; - brcm,function = <7>; /* alt3 */ - }; + pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; /* I2S interface */ - alt2: alt2 { + i2s_alt2: i2s_alt2 { brcm,pins = <28 29 30 31>; brcm,function = <6>; /* alt2 */ }; }; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; -}; - -&sdhci { - status = "okay"; - bus-width = <4>; -}; diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi new file mode 100644 index 000000000000..c7064487017d --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -0,0 +1,51 @@ +/include/ "bcm2835.dtsi" + +/ { + memory { + reg = <0 0x10000000>; + }; + + leds { + compatible = "gpio-leds"; + + act { + label = "ACT"; + default-state = "keep"; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + + gpioout: gpioout { + brcm,pins = <6>; + brcm,function = <1>; /* GPIO out */ + }; + + alt0: alt0 { + brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; + brcm,function = <4>; /* alt0 */ + }; + + alt3: alt3 { + brcm,pins = <48 49 50 51 52 53>; + brcm,function = <7>; /* alt3 */ + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; +}; + +&sdhci { + status = "okay"; + bus-width = <4>; +}; diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts new file mode 100644 index 000000000000..d2ee95280548 --- /dev/null +++ b/arch/arm/boot/dts/bcm911360_entphn.dts @@ -0,0 +1,53 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-cygnus.dtsi" + +/ { + model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)"; + compatible = "brcm,bcm11360", "brcm,cygnus"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS0,115200"; + }; + + uart3: serial@18023000 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts new file mode 100644 index 000000000000..9658d4f62d59 --- /dev/null +++ b/arch/arm/boot/dts/bcm911360k.dts @@ -0,0 +1,53 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-cygnus.dtsi" + +/ { + model = "Cygnus SVK (BCM911360K)"; + compatible = "brcm,bcm11360", "brcm,cygnus"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS0,115200"; + }; + + uart3: serial@18023000 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts new file mode 100644 index 000000000000..f1bb36f3975c --- /dev/null +++ b/arch/arm/boot/dts/bcm958300k.dts @@ -0,0 +1,53 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-cygnus.dtsi" + +/ { + model = "Cygnus SVK (BCM958300K)"; + compatible = "brcm,bcm58300", "brcm,cygnus"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS0,115200"; + }; + + uart3: serial@18023000 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts index c72bfd468d10..04f391b5c124 100644 --- a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts +++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts @@ -26,4 +26,13 @@ }; }; +ð1 { status = "okay"; }; + +/* Samsung M8G2FA 8GB eMMC */ +&sdhci2 { + non-removable; + bus-width = <8>; + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 9d7c810ebd0b..20e7c394a008 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -53,6 +53,35 @@ ranges = <0 0xf7000000 0x1000000>; + sdhci0: sdhci@ab0000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0000 0x200>; + clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; + clock-names = "io", "core"; + interrupts = ; + status = "disabled"; + }; + + sdhci1: sdhci@ab0800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0800 0x200>; + clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; + clock-names = "io", "core"; + interrupts = ; + status = "disabled"; + }; + + sdhci2: sdhci@ab1000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab1000 0x200>; + interrupts = ; + clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; + clock-names = "io", "core"; + pinctrl-0 = <&emmc_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + l2: l2-cache-controller@ac0000 { compatible = "marvell,tauros3-cache", "arm,pl310-cache"; reg = <0xac0000 0x1000>; @@ -79,11 +108,47 @@ clocks = <&chip CLKID_TWD>; }; + eth1: ethernet@b90000 { + compatible = "marvell,pxa168-eth"; + reg = <0xb90000 0x10000>; + clocks = <&chip CLKID_GETH1>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy1>; + status = "disabled"; + + ethphy1: ethernet-phy@0 { + reg = <0>; + }; + }; + cpu-ctrl@dd0000 { compatible = "marvell,berlin-cpu-ctrl"; reg = <0xdd0000 0x10000>; }; + eth0: ethernet@e50000 { + compatible = "marvell,pxa168-eth"; + reg = <0xe50000 0x10000>; + clocks = <&chip CLKID_GETH0>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>; @@ -249,9 +314,15 @@ chip: chip-control@ea0000 { compatible = "marvell,berlin2-chip-ctrl"; #clock-cells = <1>; + #reset-cells = <2>; reg = <0xea0000 0x400>; clocks = <&refclk>; clock-names = "refclk"; + + emmc_pmux: emmc-pmux { + groups = "G26"; + function = "emmc"; + }; }; apb@fc0000 { diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts index bcd81ffc495d..bdcaff7c321e 100644 --- a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts +++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "berlin2cd.dtsi" +#include / { model = "Google Chromecast"; @@ -24,6 +25,31 @@ device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; + + leds { + compatible = "gpio-leds"; + + white { + label = "white"; + gpios = <&portc 1 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + red { + label = "red"; + gpios = <&portc 2 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; +}; + +/* + * AzureWave AW-NH387 (Marvell 88W8787) + * 802.11b/g/n + Bluetooth 2.1 + */ +&sdhci0 { + non-removable; + status = "okay"; }; &uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index cc1df65da504..9e338ff80fd3 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -45,6 +45,15 @@ ranges = <0 0xf7000000 0x1000000>; + sdhci0: sdhci@ab0000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0000 0x200>; + clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; + clock-names = "io", "core"; + interrupts = ; + status = "disabled"; + }; + l2: l2-cache-controller@ac0000 { compatible = "arm,pl310-cache"; reg = <0xac0000 0x1000>; @@ -66,6 +75,42 @@ clocks = <&chip CLKID_TWD>; }; + eth1: ethernet@b90000 { + compatible = "marvell,pxa168-eth"; + reg = <0xb90000 0x10000>; + clocks = <&chip CLKID_GETH1>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy1>; + status = "disabled"; + + ethphy1: ethernet-phy@0 { + reg = <0>; + }; + }; + + eth0: ethernet@e50000 { + compatible = "marvell,pxa168-eth"; + reg = <0xe50000 0x10000>; + clocks = <&chip CLKID_GETH0>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>; @@ -231,6 +276,7 @@ chip: chip-control@ea0000 { compatible = "marvell,berlin2cd-chip-ctrl"; #clock-cells = <1>; + #reset-cells = <2>; reg = <0xea0000 0x400>; clocks = <&refclk>; clock-names = "refclk"; diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts index ea1f99b8eed6..a403b0a5ba91 100644 --- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts +++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts @@ -49,3 +49,11 @@ ð0 { status = "okay"; }; + +&sata0 { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 891d56b03922..a35deb37ffb5 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -123,6 +123,7 @@ local-mac-address = [00 00 00 00 00 00]; #address-cells = <1>; #size-cells = <0>; + phy-connection-type = "mii"; phy-handle = <ðphy0>; status = "disabled"; @@ -255,7 +256,6 @@ reg = <0x2c14 0x14>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; - status = "disabled"; }; timer2: timer@2c28 { @@ -349,6 +349,7 @@ chip: chip-control@ea0000 { compatible = "marvell,berlin2q-chip-ctrl"; #clock-cells = <1>; + #reset-cells = <2>; reg = <0xea0000 0x400>, <0xdd0170 0x10>; clocks = <&refclk>; clock-names = "refclk"; @@ -364,6 +365,45 @@ }; }; + ahci: sata@e90000 { + compatible = "marvell,berlin2q-ahci", "generic-ahci"; + reg = <0xe90000 0x1000>; + interrupts = ; + clocks = <&chip CLKID_SATA>; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy 0>; + status = "disabled"; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy 1>; + status = "disabled"; + }; + }; + + sata_phy: phy@e900a0 { + compatible = "marvell,berlin2q-sata-phy"; + reg = <0xe900a0 0x200>; + clocks = <&chip CLKID_SATA>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + sata-phy@0 { + reg = <0>; + }; + + sata-phy@1 { + reg = <1>; + }; + }; + apb@fc0000 { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index c6ce6258434f..0d8a3bd0f00d 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -171,6 +171,86 @@ 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ >; }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ + 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ + 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ + 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ + 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ + 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ + 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ + 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ + 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ + 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ + 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ + 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ + + /* Slave 2 */ + 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ + 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ + 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ + 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ + 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ + 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ + 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ + 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ + 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ + 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ + 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ + 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ + >; + + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 */ + 0x250 (MUX_MODE15) + 0x254 (MUX_MODE15) + 0x258 (MUX_MODE15) + 0x25c (MUX_MODE15) + 0x260 (MUX_MODE15) + 0x264 (MUX_MODE15) + 0x268 (MUX_MODE15) + 0x26c (MUX_MODE15) + 0x270 (MUX_MODE15) + 0x274 (MUX_MODE15) + 0x278 (MUX_MODE15) + 0x27c (MUX_MODE15) + + /* Slave 2 */ + 0x198 (MUX_MODE15) + 0x19c (MUX_MODE15) + 0x1a0 (MUX_MODE15) + 0x1a4 (MUX_MODE15) + 0x1a8 (MUX_MODE15) + 0x1ac (MUX_MODE15) + 0x1b0 (MUX_MODE15) + 0x1b4 (MUX_MODE15) + 0x1b8 (MUX_MODE15) + 0x1bc (MUX_MODE15) + 0x1c0 (MUX_MODE15) + 0x1c4 (MUX_MODE15) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ + 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + 0x23c (MUX_MODE15) + 0x240 (MUX_MODE15) + >; + }; + }; &i2c1 { @@ -201,6 +281,7 @@ regulator-name = "smps45"; regulator-min-microvolt = < 850000>; regulator-max-microvolt = <1150000>; + regulator-always-on; regulator-boot-on; }; @@ -209,6 +290,7 @@ regulator-name = "smps6"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <12500000>; + regulator-always-on; regulator-boot-on; }; @@ -226,6 +308,7 @@ regulator-name = "smps8"; regulator-min-microvolt = < 850000>; regulator-max-microvolt = <1250000>; + regulator-always-on; regulator-boot-on; }; @@ -252,6 +335,7 @@ regulator-name = "ldo2"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; regulator-boot-on; }; @@ -269,6 +353,7 @@ regulator-name = "ldo9"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; + regulator-always-on; regulator-boot-on; }; @@ -528,3 +613,29 @@ ti,no-reset-on-init; ti,no-idle-on-init; }; + +&mac { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <3>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; +}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 9cc98436a982..9cd99b931302 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -34,6 +34,12 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + serial8 = &uart9; + serial9 = &uart10; + ethernet0 = &cpsw_emac0; + ethernet1 = &cpsw_emac1; }; timer { @@ -335,6 +341,8 @@ ti,hwmods = "uart1"; clock-frequency = <48000000>; status = "disabled"; + dmas = <&sdma 49>, <&sdma 50>; + dma-names = "tx", "rx"; }; uart2: serial@4806c000 { @@ -344,6 +352,8 @@ ti,hwmods = "uart2"; clock-frequency = <48000000>; status = "disabled"; + dmas = <&sdma 51>, <&sdma 52>; + dma-names = "tx", "rx"; }; uart3: serial@48020000 { @@ -353,6 +363,8 @@ ti,hwmods = "uart3"; clock-frequency = <48000000>; status = "disabled"; + dmas = <&sdma 53>, <&sdma 54>; + dma-names = "tx", "rx"; }; uart4: serial@4806e000 { @@ -362,6 +374,8 @@ ti,hwmods = "uart4"; clock-frequency = <48000000>; status = "disabled"; + dmas = <&sdma 55>, <&sdma 56>; + dma-names = "tx", "rx"; }; uart5: serial@48066000 { @@ -371,6 +385,8 @@ ti,hwmods = "uart5"; clock-frequency = <48000000>; status = "disabled"; + dmas = <&sdma 63>, <&sdma 64>; + dma-names = "tx", "rx"; }; uart6: serial@48068000 { @@ -380,6 +396,8 @@ ti,hwmods = "uart6"; clock-frequency = <48000000>; status = "disabled"; + dmas = <&sdma 79>, <&sdma 80>; + dma-names = "tx", "rx"; }; uart7: serial@48420000 { @@ -421,7 +439,11 @@ mailbox1: mailbox@4a0f4000 { compatible = "ti,omap4-mailbox"; reg = <0x4a0f4000 0x200>; + interrupts = , + , + ; ti,hwmods = "mailbox1"; + #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; status = "disabled"; @@ -430,7 +452,12 @@ mailbox2: mailbox@4883a000 { compatible = "ti,omap4-mailbox"; reg = <0x4883a000 0x200>; + interrupts = , + , + , + ; ti,hwmods = "mailbox2"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -439,7 +466,12 @@ mailbox3: mailbox@4883c000 { compatible = "ti,omap4-mailbox"; reg = <0x4883c000 0x200>; + interrupts = , + , + , + ; ti,hwmods = "mailbox3"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -448,7 +480,12 @@ mailbox4: mailbox@4883e000 { compatible = "ti,omap4-mailbox"; reg = <0x4883e000 0x200>; + interrupts = , + , + , + ; ti,hwmods = "mailbox4"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -457,7 +494,12 @@ mailbox5: mailbox@48840000 { compatible = "ti,omap4-mailbox"; reg = <0x48840000 0x200>; + interrupts = , + , + , + ; ti,hwmods = "mailbox5"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -466,7 +508,12 @@ mailbox6: mailbox@48842000 { compatible = "ti,omap4-mailbox"; reg = <0x48842000 0x200>; + interrupts = , + , + , + ; ti,hwmods = "mailbox6"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -475,7 +522,12 @@ mailbox7: mailbox@48844000 { compatible = "ti,omap4-mailbox"; reg = <0x48844000 0x200>; + interrupts = , + , + , + ; ti,hwmods = "mailbox7"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -484,7 +536,12 @@ mailbox8: mailbox@48846000 { compatible = "ti,omap4-mailbox"; reg = <0x48846000 0x200>; + interrupts = , + , + , + ; ti,hwmods = "mailbox8"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -493,7 +550,12 @@ mailbox9: mailbox@4885e000 { compatible = "ti,omap4-mailbox"; reg = <0x4885e000 0x200>; + interrupts = , + , + , + ; ti,hwmods = "mailbox9"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -502,7 +564,12 @@ mailbox10: mailbox@48860000 { compatible = "ti,omap4-mailbox"; reg = <0x48860000 0x200>; + interrupts = , + , + , + ; ti,hwmods = "mailbox10"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -511,7 +578,12 @@ mailbox11: mailbox@48862000 { compatible = "ti,omap4-mailbox"; reg = <0x48862000 0x200>; + interrupts = , + , + , + ; ti,hwmods = "mailbox11"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -520,7 +592,12 @@ mailbox12: mailbox@48864000 { compatible = "ti,omap4-mailbox"; reg = <0x48864000 0x200>; + interrupts = , + , + , + ; ti,hwmods = "mailbox12"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -529,7 +606,12 @@ mailbox13: mailbox@48802000 { compatible = "ti,omap4-mailbox"; reg = <0x48802000 0x200>; + interrupts = , + , + , + ; ti,hwmods = "mailbox13"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -1141,7 +1223,7 @@ }; }; - omap_dwc3_1@48880000 { + omap_dwc3_1: omap_dwc3_1@48880000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss1"; reg = <0x48880000 0x10000>; @@ -1162,7 +1244,7 @@ }; }; - omap_dwc3_2@488c0000 { + omap_dwc3_2: omap_dwc3_2@488c0000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss2"; reg = <0x488c0000 0x10000>; @@ -1184,7 +1266,7 @@ }; /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ - omap_dwc3_3@48900000 { + omap_dwc3_3: omap_dwc3_3@48900000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss3"; reg = <0x48900000 0x10000>; @@ -1204,26 +1286,6 @@ }; }; - omap_dwc3_4@48940000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss4"; - reg = <0x48940000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - status = "disabled"; - usb4: usb@48950000 { - compatible = "snps,dwc3"; - reg = <0x48950000 0x17000>; - interrupts = ; - tx-fifo-resize; - maximum-speed = "high-speed"; - dr_mode = "otg"; - }; - }; - elm: elm@48078000 { compatible = "ti,am3352-elm"; reg = <0x48078000 0xfc0>; /* device IO registers */ @@ -1265,6 +1327,65 @@ ti,irqs-skip = <10 133 139 140>; ti,irqs-safe-map = <0>; }; + + mac: ethernet@4a100000 { + compatible = "ti,cpsw"; + ti,hwmods = "gmac"; + clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; + clock-names = "fck", "cpts"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + no_bd_ram = <0>; + rx_descs = <64>; + mac_control = <0x20>; + slaves = <2>; + active_slave = <0>; + cpts_clock_mult = <0x80000000>; + cpts_clock_shift = <29>; + reg = <0x48484000 0x1000 + 0x48485200 0x2E00>; + #address-cells = <1>; + #size-cells = <1>; + /* + * rx_thresh_pend + * rx_pend + * tx_pend + * misc_pend + */ + interrupts = , + , + , + ; + ranges; + status = "disabled"; + + davinci_mdio: mdio@48485000 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "davinci_mdio"; + bus_freq = <1000000>; + reg = <0x48485000 0x100>; + }; + + cpsw_emac0: slave@48480200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + cpsw_emac1: slave@48480300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + phy_sel: cpsw-phy-sel@4a002554 { + compatible = "ti,dra7xx-cpsw-phy-sel"; + reg= <0x4a002554 0x4>; + reg-names = "gmii-sel"; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 41074288adfa..abbaaa782f88 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -17,6 +17,13 @@ device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1024 MB */ }; + + evm_3v3: fixedregulator-evm_3v3 { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &dra7_pmx_core { @@ -26,6 +33,78 @@ 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ >; }; + + nand_default: nand_default { + pinctrl-single,pins = < + 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ + 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ + 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ + 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ + 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ + 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ + 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ + 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ + 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ + 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ + 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ + 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ + 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ + 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ + 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ + 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ + 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ + 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ + 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ + 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ + 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ + 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ + >; + }; + + usb1_pins: pinmux_usb1_pins { + pinctrl-single,pins = < + 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ + >; + }; + + usb2_pins: pinmux_usb2_pins { + pinctrl-single,pins = < + 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ + >; + }; + + tps65917_pins_default: tps65917_pins_default { + pinctrl-single,pins = < + 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ + >; + }; + + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; }; &i2c1 { @@ -38,6 +117,9 @@ compatible = "ti,tps65917"; reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&tps65917_pins_default>; + interrupts = ; /* IRQ_SYS_1N */ interrupt-parent = <&gic>; interrupt-controller; @@ -136,9 +218,223 @@ }; }; }; + + tps65917_power_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps65917>; + interrupts = <1 IRQ_TYPE_NONE>; + wakeup-source; + ti,palmas-long-press-seconds = <6>; + }; }; }; &uart1 { status = "okay"; }; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_default>; + ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ + nand@0,0 { + /* To use NAND, DIP switch SW5 must be set like so: + * SW5.1 (NAND_SELn) = ON (LOW) + * SW5.9 (GPMC_WPN) = OFF (HIGH) + */ + reg = <0 0 4>; /* device IO registers */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <80>; + gpmc,cs-wr-off-ns = <80>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <60>; + gpmc,adv-wr-off-ns = <60>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <50>; + gpmc,oe-on-ns = <4>; + gpmc,oe-off-ns = <40>; + gpmc,access-ns = <40>; + gpmc,wr-access-ns = <80>; + gpmc,rd-cycle-ns = <80>; + gpmc,wr-cycle-ns = <80>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x000020000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00020000 0x00020000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00040000 0x00020000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x00060000 0x00020000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00080000 0x00040000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x000c0000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x001c0000 0x00020000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x001e0000 0x00020000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00200000 0x00800000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x0f600000>; + }; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldo4_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldo4_reg>; +}; + +&usb1 { + dr_mode = "peripheral"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; +}; + +&usb2 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_pins>; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + + vmmc-supply = <&ldo1_reg>; + bus-width = <4>; + /* + * SDCD signal is not being used here - using the fact that GPIO mode + * is a viable alternative + */ + cd-gpios = <&gpio6 27 0>; +}; + +&mmc2 { + /* SW5-3 in ON position */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; + + vmmc-supply = <&evm_3v3>; + bus-width = <8>; + ti,non-removable; +}; + +&dra7_pmx_core { + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 2 */ + 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ + 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ + 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ + 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ + 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ + 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ + 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ + 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ + 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ + 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ + 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ + 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ + >; + + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 2 */ + 0x198 (MUX_MODE15) + 0x19c (MUX_MODE15) + 0x1a0 (MUX_MODE15) + 0x1a4 (MUX_MODE15) + 0x1a8 (MUX_MODE15) + 0x1ac (MUX_MODE15) + 0x1b0 (MUX_MODE15) + 0x1b4 (MUX_MODE15) + 0x1b8 (MUX_MODE15) + 0x1bc (MUX_MODE15) + 0x1c0 (MUX_MODE15) + 0x1c4 (MUX_MODE15) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ + 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + 0x23c (MUX_MODE15) + 0x240 (MUX_MODE15) + >; + }; +}; + +&mac { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <3>; + phy-mode = "rgmii"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + active_slave = <1>; +}; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 3be544c4891f..10173fab1a15 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -44,4 +44,26 @@ interrupts = , ; }; + + ocp { + omap_dwc3_4: omap_dwc3_4@48940000 { + compatible = "ti,dwc3"; + ti,hwmods = "usb_otg_ss4"; + reg = <0x48940000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + status = "disabled"; + usb4: usb@48950000 { + compatible = "snps,dwc3"; + reg = <0x48950000 0x17000>; + interrupts = ; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 50ccd151091e..667d323e80a3 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -25,37 +25,7 @@ chosen { bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp"; - }; - - reg_1p8v: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - lan9220@20000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x20000000 0x10000>; - phy-mode = "mii"; - interrupt-parent = <&gpio0>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vddvario-supply = <®_1p8v>; - vdd33a-supply = <®_3p3v>; + stdout-path = &uart1; }; gpio_keys { @@ -92,4 +62,35 @@ gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; }; }; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + lan9220@20000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x20000000 0x10000>; + phy-mode = "mii"; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vddvario-supply = <®_1p8v>; + vdd33a-supply = <®_3p3v>; + }; }; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index 00eeed3721b6..cc7bfe0ba40a 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -55,7 +55,7 @@ <0 121 IRQ_TYPE_LEVEL_HIGH>; }; - smu@e0110000 { + clocks@e0110000 { compatible = "renesas,emev2-smu"; reg = <0xe0110000 0x10000>; #address-cells = <2>; @@ -129,7 +129,7 @@ }; }; - sti@e0180000 { + timer@e0180000 { compatible = "renesas,em-sti"; reg = <0xe0180000 0x54>; interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; @@ -137,7 +137,7 @@ clock-names = "sclk"; }; - uart@e1020000 { + uart0: serial@e1020000 { compatible = "renesas,em-uart"; reg = <0xe1020000 0x38>; interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; @@ -145,7 +145,7 @@ clock-names = "sclk"; }; - uart@e1030000 { + uart1: serial@e1030000 { compatible = "renesas,em-uart"; reg = <0xe1030000 0x38>; interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; @@ -153,7 +153,7 @@ clock-names = "sclk"; }; - uart@e1040000 { + uart2: serial@e1040000 { compatible = "renesas,em-uart"; reg = <0xe1040000 0x38>; interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; @@ -161,7 +161,7 @@ clock-names = "sclk"; }; - uart@e1050000 { + uart3: serial@e1050000 { compatible = "renesas,em-uart"; reg = <0xe1050000 0x38>; interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 693a3275606f..242ddda0a8cd 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -320,6 +320,16 @@ status = "disabled"; }; + mfc: codec@13400000 { + compatible = "samsung,mfc-v7"; + reg = <0x13400000 0x10000>; + interrupts = <0 102 0>; + clock-names = "mfc", "sclk_mfc"; + clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; + samsung,power-domain = <&pd_mfc>; + status = "disabled"; + }; + serial_0: serial@13800000 { compatible = "samsung,exynos4210-uart"; reg = <0x13800000 0x100>; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 807bb5bf91fc..bcc9e63c8070 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -31,6 +31,23 @@ pinctrl2 = &pinctrl_2; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@900 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x900>; + }; + + cpu@901 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x901>; + }; + }; + pmu_system_controller: system-controller@10020000 { clock-names = "clkout0", "clkout1", "clkout2", "clkout3", "clkout4", "clkout8", "clkout9"; diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index 3c00e6ec9302..dd0a43ec56da 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -22,6 +22,23 @@ / { compatible = "samsung,exynos4212", "samsung,exynos4"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@A00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA00>; + }; + + cpu@A01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA01>; + }; + }; + combiner: interrupt-controller@10440000 { samsung,combiner-nr = <18>; }; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 5e066cd87f66..dd9ac66770f7 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -14,6 +14,7 @@ /dts-v1/; #include "exynos4412.dtsi" +#include / { model = "Samsung Trats 2 based on Exynos4412"; @@ -22,6 +23,7 @@ aliases { i2c9 = &i2c_ak8975; i2c10 = &i2c_cm36651; + i2c11 = &i2c_max77693; }; memory { @@ -399,8 +401,6 @@ regulator-name = "VMEM_VDD_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-mem-off; }; ldo23_reg: ldo23 { @@ -503,8 +503,6 @@ regulator-name = "VMEM_VDDF_3.0V"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-mem-off; }; buck9_reg: buck9 { @@ -518,6 +516,36 @@ }; }; + i2c_max77693: i2c-gpio-1 { + compatible = "i2c-gpio"; + gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + max77693@66 { + compatible = "maxim,max77693"; + interrupt-parent = <&gpx1>; + interrupts = <5 2>; + reg = <0x66>; + + regulators { + esafeout1_reg: ESAFEOUT1@1 { + regulator-name = "ESAFEOUT1"; + }; + esafeout2_reg: ESAFEOUT2@2 { + regulator-name = "ESAFEOUT2"; + }; + charger_reg: CHARGER@0 { + regulator-name = "CHARGER"; + regulator-min-microamp = <60000>; + regulator-max-microamp = <2580000>; + }; + }; + }; + }; + mmc@12550000 { num-slots = <1>; broken-cd; @@ -782,3 +810,319 @@ io-channels = <&adc 2>; /* Battery temperature */ }; }; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + sleep0: sleep-states { + PIN_SLP(gpa0-0, INPUT, NONE); + PIN_SLP(gpa0-1, OUT0, NONE); + PIN_SLP(gpa0-2, INPUT, NONE); + PIN_SLP(gpa0-3, INPUT, UP); + PIN_SLP(gpa0-4, INPUT, NONE); + PIN_SLP(gpa0-5, INPUT, DOWN); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, INPUT, UP); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, INPUT, DOWN); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, INPUT, DOWN); + PIN_SLP(gpa1-4, INPUT, DOWN); + PIN_SLP(gpa1-5, INPUT, DOWN); + + PIN_SLP(gpb-0, INPUT, NONE); + PIN_SLP(gpb-1, INPUT, NONE); + PIN_SLP(gpb-2, INPUT, NONE); + PIN_SLP(gpb-3, INPUT, NONE); + PIN_SLP(gpb-4, INPUT, DOWN); + PIN_SLP(gpb-5, INPUT, UP); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, INPUT, DOWN); + + PIN_SLP(gpc0-0, INPUT, DOWN); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, INPUT, DOWN); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, INPUT, DOWN); + + PIN_SLP(gpc1-0, INPUT, NONE); + PIN_SLP(gpc1-1, PREV, NONE); + PIN_SLP(gpc1-2, INPUT, NONE); + PIN_SLP(gpc1-3, INPUT, NONE); + PIN_SLP(gpc1-4, INPUT, NONE); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, INPUT, DOWN); + PIN_SLP(gpd0-2, INPUT, NONE); + PIN_SLP(gpd0-3, INPUT, NONE); + + PIN_SLP(gpd1-0, INPUT, DOWN); + PIN_SLP(gpd1-1, INPUT, DOWN); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + + PIN_SLP(gpf0-0, INPUT, NONE); + PIN_SLP(gpf0-1, INPUT, NONE); + PIN_SLP(gpf0-2, INPUT, DOWN); + PIN_SLP(gpf0-3, INPUT, DOWN); + PIN_SLP(gpf0-4, INPUT, NONE); + PIN_SLP(gpf0-5, INPUT, DOWN); + PIN_SLP(gpf0-6, INPUT, NONE); + PIN_SLP(gpf0-7, INPUT, DOWN); + + PIN_SLP(gpf1-0, INPUT, DOWN); + PIN_SLP(gpf1-1, INPUT, DOWN); + PIN_SLP(gpf1-2, INPUT, DOWN); + PIN_SLP(gpf1-3, INPUT, DOWN); + PIN_SLP(gpf1-4, INPUT, NONE); + PIN_SLP(gpf1-5, INPUT, NONE); + PIN_SLP(gpf1-6, INPUT, DOWN); + PIN_SLP(gpf1-7, PREV, NONE); + + PIN_SLP(gpf2-0, PREV, NONE); + PIN_SLP(gpf2-1, INPUT, DOWN); + PIN_SLP(gpf2-2, INPUT, DOWN); + PIN_SLP(gpf2-3, INPUT, DOWN); + PIN_SLP(gpf2-4, INPUT, DOWN); + PIN_SLP(gpf2-5, INPUT, DOWN); + PIN_SLP(gpf2-6, INPUT, NONE); + PIN_SLP(gpf2-7, INPUT, NONE); + + PIN_SLP(gpf3-0, INPUT, NONE); + PIN_SLP(gpf3-1, PREV, NONE); + PIN_SLP(gpf3-2, PREV, NONE); + PIN_SLP(gpf3-3, PREV, NONE); + PIN_SLP(gpf3-4, OUT1, NONE); + PIN_SLP(gpf3-5, INPUT, DOWN); + + PIN_SLP(gpj0-0, PREV, NONE); + PIN_SLP(gpj0-1, PREV, NONE); + PIN_SLP(gpj0-2, PREV, NONE); + PIN_SLP(gpj0-3, INPUT, DOWN); + PIN_SLP(gpj0-4, PREV, NONE); + PIN_SLP(gpj0-5, PREV, NONE); + PIN_SLP(gpj0-6, INPUT, DOWN); + PIN_SLP(gpj0-7, INPUT, DOWN); + + PIN_SLP(gpj1-0, INPUT, DOWN); + PIN_SLP(gpj1-1, PREV, NONE); + PIN_SLP(gpj1-2, PREV, NONE); + PIN_SLP(gpj1-3, INPUT, DOWN); + PIN_SLP(gpj1-4, INPUT, DOWN); + }; +}; + +&pinctrl_1 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep1>; + + sleep1: sleep-states { + PIN_SLP(gpk0-0, PREV, NONE); + PIN_SLP(gpk0-1, PREV, NONE); + PIN_SLP(gpk0-2, OUT0, NONE); + PIN_SLP(gpk0-3, PREV, NONE); + PIN_SLP(gpk0-4, PREV, NONE); + PIN_SLP(gpk0-5, PREV, NONE); + PIN_SLP(gpk0-6, PREV, NONE); + + PIN_SLP(gpk1-0, INPUT, DOWN); + PIN_SLP(gpk1-1, INPUT, DOWN); + PIN_SLP(gpk1-2, INPUT, DOWN); + PIN_SLP(gpk1-3, PREV, NONE); + PIN_SLP(gpk1-4, PREV, NONE); + PIN_SLP(gpk1-5, PREV, NONE); + PIN_SLP(gpk1-6, PREV, NONE); + + PIN_SLP(gpk2-0, INPUT, DOWN); + PIN_SLP(gpk2-1, INPUT, DOWN); + PIN_SLP(gpk2-2, INPUT, DOWN); + PIN_SLP(gpk2-3, INPUT, DOWN); + PIN_SLP(gpk2-4, INPUT, DOWN); + PIN_SLP(gpk2-5, INPUT, DOWN); + PIN_SLP(gpk2-6, INPUT, DOWN); + + PIN_SLP(gpk3-0, OUT0, NONE); + PIN_SLP(gpk3-1, INPUT, NONE); + PIN_SLP(gpk3-2, INPUT, DOWN); + PIN_SLP(gpk3-3, INPUT, NONE); + PIN_SLP(gpk3-4, INPUT, NONE); + PIN_SLP(gpk3-5, INPUT, NONE); + PIN_SLP(gpk3-6, INPUT, NONE); + + PIN_SLP(gpl0-0, INPUT, DOWN); + PIN_SLP(gpl0-1, INPUT, DOWN); + PIN_SLP(gpl0-2, INPUT, DOWN); + PIN_SLP(gpl0-3, INPUT, DOWN); + PIN_SLP(gpl0-4, PREV, NONE); + PIN_SLP(gpl0-6, PREV, NONE); + + PIN_SLP(gpl1-0, INPUT, DOWN); + PIN_SLP(gpl1-1, INPUT, DOWN); + PIN_SLP(gpl2-0, INPUT, DOWN); + PIN_SLP(gpl2-1, INPUT, DOWN); + PIN_SLP(gpl2-2, INPUT, DOWN); + PIN_SLP(gpl2-3, INPUT, DOWN); + PIN_SLP(gpl2-4, INPUT, DOWN); + PIN_SLP(gpl2-5, INPUT, DOWN); + PIN_SLP(gpl2-6, PREV, NONE); + PIN_SLP(gpl2-7, INPUT, DOWN); + + PIN_SLP(gpm0-0, INPUT, DOWN); + PIN_SLP(gpm0-1, INPUT, DOWN); + PIN_SLP(gpm0-2, INPUT, DOWN); + PIN_SLP(gpm0-3, INPUT, DOWN); + PIN_SLP(gpm0-4, INPUT, DOWN); + PIN_SLP(gpm0-5, INPUT, DOWN); + PIN_SLP(gpm0-6, INPUT, DOWN); + PIN_SLP(gpm0-7, INPUT, DOWN); + + PIN_SLP(gpm1-0, INPUT, DOWN); + PIN_SLP(gpm1-1, INPUT, DOWN); + PIN_SLP(gpm1-2, INPUT, NONE); + PIN_SLP(gpm1-3, INPUT, NONE); + PIN_SLP(gpm1-4, INPUT, NONE); + PIN_SLP(gpm1-5, INPUT, NONE); + PIN_SLP(gpm1-6, INPUT, DOWN); + + PIN_SLP(gpm2-0, INPUT, NONE); + PIN_SLP(gpm2-1, INPUT, NONE); + PIN_SLP(gpm2-2, INPUT, DOWN); + PIN_SLP(gpm2-3, INPUT, DOWN); + PIN_SLP(gpm2-4, INPUT, DOWN); + + PIN_SLP(gpm3-0, PREV, NONE); + PIN_SLP(gpm3-1, PREV, NONE); + PIN_SLP(gpm3-2, PREV, NONE); + PIN_SLP(gpm3-3, OUT1, NONE); + PIN_SLP(gpm3-4, INPUT, DOWN); + PIN_SLP(gpm3-5, INPUT, DOWN); + PIN_SLP(gpm3-6, INPUT, DOWN); + PIN_SLP(gpm3-7, INPUT, DOWN); + + PIN_SLP(gpm4-0, INPUT, DOWN); + PIN_SLP(gpm4-1, INPUT, DOWN); + PIN_SLP(gpm4-2, INPUT, DOWN); + PIN_SLP(gpm4-3, INPUT, DOWN); + PIN_SLP(gpm4-4, INPUT, DOWN); + PIN_SLP(gpm4-5, INPUT, DOWN); + PIN_SLP(gpm4-6, INPUT, DOWN); + PIN_SLP(gpm4-7, INPUT, DOWN); + + PIN_SLP(gpy0-0, INPUT, DOWN); + PIN_SLP(gpy0-1, INPUT, DOWN); + PIN_SLP(gpy0-2, INPUT, DOWN); + PIN_SLP(gpy0-3, INPUT, DOWN); + PIN_SLP(gpy0-4, INPUT, DOWN); + PIN_SLP(gpy0-5, INPUT, DOWN); + + PIN_SLP(gpy1-0, INPUT, DOWN); + PIN_SLP(gpy1-1, INPUT, DOWN); + PIN_SLP(gpy1-2, INPUT, DOWN); + PIN_SLP(gpy1-3, INPUT, DOWN); + + PIN_SLP(gpy2-0, PREV, NONE); + PIN_SLP(gpy2-1, INPUT, DOWN); + PIN_SLP(gpy2-2, INPUT, NONE); + PIN_SLP(gpy2-3, INPUT, NONE); + PIN_SLP(gpy2-4, INPUT, NONE); + PIN_SLP(gpy2-5, INPUT, NONE); + + PIN_SLP(gpy3-0, INPUT, DOWN); + PIN_SLP(gpy3-1, INPUT, DOWN); + PIN_SLP(gpy3-2, INPUT, DOWN); + PIN_SLP(gpy3-3, INPUT, DOWN); + PIN_SLP(gpy3-4, INPUT, DOWN); + PIN_SLP(gpy3-5, INPUT, DOWN); + PIN_SLP(gpy3-6, INPUT, DOWN); + PIN_SLP(gpy3-7, INPUT, DOWN); + + PIN_SLP(gpy4-0, INPUT, DOWN); + PIN_SLP(gpy4-1, INPUT, DOWN); + PIN_SLP(gpy4-2, INPUT, DOWN); + PIN_SLP(gpy4-3, INPUT, DOWN); + PIN_SLP(gpy4-4, INPUT, DOWN); + PIN_SLP(gpy4-5, INPUT, DOWN); + PIN_SLP(gpy4-6, INPUT, DOWN); + PIN_SLP(gpy4-7, INPUT, DOWN); + + PIN_SLP(gpy5-0, INPUT, DOWN); + PIN_SLP(gpy5-1, INPUT, DOWN); + PIN_SLP(gpy5-2, INPUT, DOWN); + PIN_SLP(gpy5-3, INPUT, DOWN); + PIN_SLP(gpy5-4, INPUT, DOWN); + PIN_SLP(gpy5-5, INPUT, DOWN); + PIN_SLP(gpy5-6, INPUT, DOWN); + PIN_SLP(gpy5-7, INPUT, DOWN); + + PIN_SLP(gpy6-0, INPUT, DOWN); + PIN_SLP(gpy6-1, INPUT, DOWN); + PIN_SLP(gpy6-2, INPUT, DOWN); + PIN_SLP(gpy6-3, INPUT, DOWN); + PIN_SLP(gpy6-4, INPUT, DOWN); + PIN_SLP(gpy6-5, INPUT, DOWN); + PIN_SLP(gpy6-6, INPUT, DOWN); + PIN_SLP(gpy6-7, INPUT, DOWN); + }; +}; + +&pinctrl_2 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep2>; + + sleep2: sleep-states { + PIN_SLP(gpz-0, INPUT, DOWN); + PIN_SLP(gpz-1, INPUT, DOWN); + PIN_SLP(gpz-2, INPUT, DOWN); + PIN_SLP(gpz-3, INPUT, DOWN); + PIN_SLP(gpz-4, INPUT, DOWN); + PIN_SLP(gpz-5, INPUT, DOWN); + PIN_SLP(gpz-6, INPUT, DOWN); + }; +}; + +&pinctrl_3 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep3>; + + sleep3: sleep-states { + PIN_SLP(gpv0-0, INPUT, DOWN); + PIN_SLP(gpv0-1, INPUT, DOWN); + PIN_SLP(gpv0-2, INPUT, DOWN); + PIN_SLP(gpv0-3, INPUT, DOWN); + PIN_SLP(gpv0-4, INPUT, DOWN); + PIN_SLP(gpv0-5, INPUT, DOWN); + PIN_SLP(gpv0-6, INPUT, DOWN); + PIN_SLP(gpv0-7, INPUT, DOWN); + + PIN_SLP(gpv1-0, INPUT, DOWN); + PIN_SLP(gpv1-1, INPUT, DOWN); + PIN_SLP(gpv1-2, INPUT, DOWN); + PIN_SLP(gpv1-3, INPUT, DOWN); + PIN_SLP(gpv1-4, INPUT, DOWN); + PIN_SLP(gpv1-5, INPUT, DOWN); + PIN_SLP(gpv1-6, INPUT, DOWN); + PIN_SLP(gpv1-7, INPUT, DOWN); + + PIN_SLP(gpv2-0, INPUT, DOWN); + PIN_SLP(gpv2-1, INPUT, DOWN); + PIN_SLP(gpv2-2, INPUT, DOWN); + PIN_SLP(gpv2-3, INPUT, DOWN); + PIN_SLP(gpv2-4, INPUT, DOWN); + PIN_SLP(gpv2-5, INPUT, DOWN); + PIN_SLP(gpv2-6, INPUT, DOWN); + PIN_SLP(gpv2-7, INPUT, DOWN); + + PIN_SLP(gpv3-0, INPUT, DOWN); + PIN_SLP(gpv3-1, INPUT, DOWN); + PIN_SLP(gpv3-2, INPUT, DOWN); + PIN_SLP(gpv3-3, INPUT, DOWN); + PIN_SLP(gpv3-4, INPUT, DOWN); + PIN_SLP(gpv3-5, INPUT, DOWN); + PIN_SLP(gpv3-6, INPUT, DOWN); + PIN_SLP(gpv3-7, INPUT, DOWN); + + PIN_SLP(gpv4-0, INPUT, DOWN); + }; +}; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index d8bc059e172f..0f6ec93bb1d8 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -22,6 +22,35 @@ / { compatible = "samsung,exynos4412", "samsung,exynos4"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@A00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA00>; + }; + + cpu@A01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA01>; + }; + + cpu@A02 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA02>; + }; + + cpu@A03 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA03>; + }; + }; + combiner: interrupt-controller@10440000 { samsung,combiner-nr = <20>; }; diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 0865a2e33f97..c141931378e7 100644 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -12,6 +12,22 @@ * published by the Free Software Foundation. */ +#define PIN_PULL_NONE 0 +#define PIN_PULL_DOWN 1 +#define PIN_PULL_UP 3 + +#define PIN_PDN_OUT0 0 +#define PIN_PDN_OUT1 1 +#define PIN_PDN_INPUT 2 +#define PIN_PDN_PREV 3 + +#define PIN_SLP(_pin, _mode, _pull) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-con-pdn = ; \ + samsung,pin-pud-pdn = ; \ + } + / { pinctrl@11400000 { gpa0: gpa0 { diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 3acd97eb6630..7e728a1b5559 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -7,12 +7,13 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. -*/ + */ /dts-v1/; -#include "exynos5250.dtsi" +#include #include #include +#include "exynos5250.dtsi" / { model = "Insignal Arndale evaluation board based on EXYNOS5250"; @@ -26,465 +27,52 @@ bootargs = "console=ttySAC2,115200"; }; - rtc@101E0000 { - status = "okay"; - }; - - codec@11000000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; - }; - - i2c@12C60000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - samsung,i2c-slave-addr = <0x66>; - status = "okay"; - - s5m8767_pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - vinb1-supply = <&main_dc_reg>; - vinb2-supply = <&main_dc_reg>; - vinb3-supply = <&main_dc_reg>; - vinb4-supply = <&main_dc_reg>; - vinb5-supply = <&main_dc_reg>; - vinb6-supply = <&main_dc_reg>; - vinb7-supply = <&main_dc_reg>; - vinb8-supply = <&main_dc_reg>; - vinb9-supply = <&main_dc_reg>; - - vinl1-supply = <&buck7_reg>; - vinl2-supply = <&buck7_reg>; - vinl3-supply = <&buck7_reg>; - vinl4-supply = <&main_dc_reg>; - vinl5-supply = <&main_dc_reg>; - vinl6-supply = <&main_dc_reg>; - vinl7-supply = <&main_dc_reg>; - vinl8-supply = <&buck8_reg>; - vinl9-supply = <&buck8_reg>; - - s5m8767,pmic-buck2-dvs-voltage = <1300000>; - s5m8767,pmic-buck3-dvs-voltage = <1100000>; - s5m8767,pmic-buck4-dvs-voltage = <1200000>; - s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 0>, - <&gpd1 1 0>, - <&gpd1 2 0>; - s5m8767,pmic-buck-ds-gpios = <&gpx2 3 0>, - <&gpx2 4 0>, - <&gpx2 5 0>; - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_1.0V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_28IO_DP_1.35V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDD_COMMON1_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD_IOPERI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD_EXT_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD_MPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD_XPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD_COMMON2_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD_33ON_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD_COMMON3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_ABB2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD_USB_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDQ_C2C_W_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB0_3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_COMMON4_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo17_reg: LDO17 { - regulator-name = "VDDQ_MMC2_3_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo18_reg: LDO18 { - regulator-name = "VDD_33ON_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; - }; - - ldo22_reg: LDO22 { - regulator-name = "EXT_33_OFF"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - op_mode = <1>; - }; - - ldo23_reg: LDO23 { - regulator-name = "EXT_28_OFF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; - }; - - ldo25_reg: LDO25 { - regulator-name = "PVDD_LDO25"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - op_mode = <1>; - }; - - ldo26_reg: LDO26 { - regulator-name = "EXT_18_OFF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDD_MEM_1.35V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1355000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck7_reg: BUCK7 { - regulator-name = "PVDD_BUCK7"; - regulator-always-on; - op_mode = <1>; - }; - - buck8_reg: BUCK8 { - regulator-name = "PVDD_BUCK8"; - regulator-always-on; - op_mode = <1>; - }; - - buck9_reg: BUCK9 { - regulator-name = "VDD_33_OFF_EXT1"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; - }; - }; - }; - }; - - i2c@12C80000 { - status = "okay"; - - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; - }; - - i2c@12C90000 { - status = "okay"; - - wm1811a@1a { - - compatible = "wlf,wm1811"; - reg = <0x1a>; - - AVDD2-supply = <&main_dc_reg>; - CPVDD-supply = <&main_dc_reg>; - DBVDD1-supply = <&main_dc_reg>; - DBVDD2-supply = <&main_dc_reg>; - DBVDD3-supply = <&main_dc_reg>; - LDO1VDD-supply = <&main_dc_reg>; - SPKVDD1-supply = <&main_dc_reg>; - SPKVDD2-supply = <&main_dc_reg>; - - wlf,ldo1ena = <&gpb0 0 0>; - wlf,ldo2ena = <&gpb0 1 0>; - }; - }; - - i2c@12CE0000 { - status = "okay"; - - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x38>; - - hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; - }; - - i2c@121D0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <40000>; - samsung,i2c-slave-addr = <0x38>; - - sata_phy_i2c:sata-phy@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - }; - }; - - sata@122F0000 { - status = "okay"; - }; - - sata-phy@12170000 { - status = "okay"; - samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; - }; - - mmc_0: mmc@12200000 { - status = "okay"; - num-slots = <1>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - vmmc-supply = <&mmc_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; - }; - - mmc_2: mmc@12220000 { - status = "okay"; - num-slots = <1>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - vmmc-supply = <&mmc_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - }; - - i2s0: i2s@03830000 { - status = "okay"; - }; - gpio_keys { compatible = "gpio-keys"; menu { label = "SW-TACT2"; - gpios = <&gpx1 4 1>; + gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; linux,code = ; gpio-key,wakeup; }; home { label = "SW-TACT3"; - gpios = <&gpx1 5 1>; + gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; linux,code = ; gpio-key,wakeup; }; up { label = "SW-TACT4"; - gpios = <&gpx1 6 1>; + gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; linux,code = ; gpio-key,wakeup; }; down { label = "SW-TACT5"; - gpios = <&gpx1 7 1>; + gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; linux,code = ; gpio-key,wakeup; }; back { label = "SW-TACT6"; - gpios = <&gpx2 0 1>; + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; linux,code = ; gpio-key,wakeup; }; wakeup { label = "SW-TACT7"; - gpios = <&gpx2 1 1>; + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; linux,code = ; gpio-key,wakeup; }; }; - hdmi { - hpd-gpio = <&gpx3 7 2>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; - vdd-supply = <&ldo8_reg>; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -502,7 +90,7 @@ regulator-name = "VDD_33ON_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 1>; + gpio = <&gpx1 1 GPIO_ACTIVE_LOW>; enable-active-high; }; @@ -520,46 +108,455 @@ }; }; - dp-controller@145B0000 { - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - status = "okay"; + // SMSC USB3503 connected in hardware only mode as a PHY + usb_hub: usb-hub { + compatible = "smsc,usb3503a"; + + reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + connect-gpios = <&gpd1 7 GPIO_ACTIVE_LOW>; }; +}; - fimd: fimd@14400000 { - status = "okay"; - display-timings { - native-mode = <&timing0>; - timing0: timing@0 { - /* 2560x1600 DP panel */ - clock-frequency = <50000>; - hactive = <2560>; - vactive = <1600>; - hfront-porch = <48>; - hback-porch = <80>; - hsync-len = <32>; - vback-porch = <16>; - vfront-porch = <8>; - vsync-len = <6>; - }; +&dp { + status = "okay"; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <4>; +}; + +&fimd { + status = "okay"; + + display-timings { + native-mode = <&timing0>; + + timing0: timing@0 { + /* 2560x1600 DP panel */ + clock-frequency = <50000>; + hactive = <2560>; + vactive = <1600>; + hfront-porch = <48>; + hback-porch = <80>; + hsync-len = <32>; + vback-porch = <16>; + vfront-porch = <8>; + vsync-len = <6>; }; }; +}; - usb_hub_bus { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; +&hdmi { + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_LOW>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; + vdd-supply = <&ldo8_reg>; +}; + +&i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + samsung,i2c-slave-addr = <0x66>; + + s5m8767_pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + vinb1-supply = <&main_dc_reg>; + vinb2-supply = <&main_dc_reg>; + vinb3-supply = <&main_dc_reg>; + vinb4-supply = <&main_dc_reg>; + vinb5-supply = <&main_dc_reg>; + vinb6-supply = <&main_dc_reg>; + vinb7-supply = <&main_dc_reg>; + vinb8-supply = <&main_dc_reg>; + vinb9-supply = <&main_dc_reg>; + + vinl1-supply = <&buck7_reg>; + vinl2-supply = <&buck7_reg>; + vinl3-supply = <&buck7_reg>; + vinl4-supply = <&main_dc_reg>; + vinl5-supply = <&main_dc_reg>; + vinl6-supply = <&main_dc_reg>; + vinl7-supply = <&main_dc_reg>; + vinl8-supply = <&buck8_reg>; + vinl9-supply = <&buck8_reg>; + + s5m8767,pmic-buck2-dvs-voltage = <1300000>; + s5m8767,pmic-buck3-dvs-voltage = <1100000>; + s5m8767,pmic-buck4-dvs-voltage = <1200000>; + s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>, + <&gpd1 1 GPIO_ACTIVE_HIGH>, + <&gpd1 2 GPIO_ACTIVE_HIGH>; + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, + <&gpx2 4 GPIO_ACTIVE_HIGH>, + <&gpx2 5 GPIO_ACTIVE_HIGH>; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE_1.0V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; - // SMSC USB3503 connected in hardware only mode as a PHY - usb_hub: usb_hub { - compatible = "smsc,usb3503a"; + ldo2_reg: LDO2 { + regulator-name = "VDD_28IO_DP_1.35V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDD_COMMON1_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_IOPERI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; + }; + + ldo5_reg: LDO5 { + regulator-name = "VDD_EXT_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD_MPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; - reset-gpios = <&gpx3 5 1>; - connect-gpios = <&gpd1 7 1>; + ldo7_reg: LDO7 { + regulator-name = "VDD_XPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD_COMMON2_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD_33ON_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + op_mode = <1>; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDD_COMMON3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_ABB2_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD_USB_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDDQ_C2C_W_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD18_ABB0_3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD10_COMMON4_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD18_HSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo17_reg: LDO17 { + regulator-name = "VDDQ_MMC2_3_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo18_reg: LDO18 { + regulator-name = "VDD_33ON_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + }; + + ldo22_reg: LDO22 { + regulator-name = "EXT_33_OFF"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; + }; + + ldo23_reg: LDO23 { + regulator-name = "EXT_28_OFF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + }; + + ldo25_reg: LDO25 { + regulator-name = "PVDD_LDO25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + op_mode = <1>; + }; + + ldo26_reg: LDO26 { + regulator-name = "EXT_18_OFF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDD_MEM_1.35V"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1355000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck7_reg: BUCK7 { + regulator-name = "PVDD_BUCK7"; + regulator-always-on; + op_mode = <1>; + }; + + buck8_reg: BUCK8 { + regulator-name = "PVDD_BUCK8"; + regulator-always-on; + op_mode = <1>; + }; + + buck9_reg: BUCK9 { + regulator-name = "VDD_33_OFF_EXT1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3000000>; + op_mode = <1>; + }; }; }; }; + +&i2c_2 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + samsung,i2c-slave-addr = <0x50>; + + hdmiddc@50 { + compatible = "samsung,exynos4210-hdmiddc"; + reg = <0x50>; + }; +}; + +&i2c_3 { + status = "okay"; + + wm1811a@1a { + compatible = "wlf,wm1811"; + reg = <0x1a>; + + AVDD2-supply = <&main_dc_reg>; + CPVDD-supply = <&main_dc_reg>; + DBVDD1-supply = <&main_dc_reg>; + DBVDD2-supply = <&main_dc_reg>; + DBVDD3-supply = <&main_dc_reg>; + LDO1VDD-supply = <&main_dc_reg>; + SPKVDD1-supply = <&main_dc_reg>; + SPKVDD2-supply = <&main_dc_reg>; + + wlf,ldo1ena = <&gpb0 0 GPIO_ACTIVE_HIGH>; + wlf,ldo2ena = <&gpb0 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c_8 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + samsung,i2c-slave-addr = <0x38>; + + hdmiphy@38 { + compatible = "samsung,exynos4212-hdmiphy"; + reg = <0x38>; + }; +}; + +&i2c_9 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <40000>; + samsung,i2c-slave-addr = <0x38>; + + sata_phy_i2c:sata-phy@38 { + compatible = "samsung,exynos-sataphy-i2c"; + reg = <0x38>; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&mfc { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; +}; + +&mmc_0 { + status = "okay"; + num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + vmmc-supply = <&mmc_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&mmc_2 { + status = "okay"; + num-slots = <1>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + vmmc-supply = <&mmc_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sata_phy { + status = "okay"; + samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; +}; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 6a0f4c0ff763..bc27cc2558fe 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -7,9 +7,11 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. -*/ + */ /dts-v1/; +#include +#include #include "exynos5250.dtsi" / { @@ -27,165 +29,6 @@ bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; - rtc@101E0000 { - status = "okay"; - }; - - i2c@12C60000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - status = "okay"; - - eeprom@50 { - compatible = "samsung,s524ad0xd1"; - reg = <0x50>; - }; - - max77686@09 { - compatible = "maxim,max77686"; - reg = <0x09>; - interrupt-parent = <&gpx3>; - interrupts = <2 0>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "P1.0V_LDO_OUT1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "P1.2V_LDO_OUT2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "P1.8V_LDO_OUT3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "P2.8V_LDO_OUT4"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "P1.8V_LDO_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "P1.1V_LDO_OUT6"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo11_reg: LDO11 { - regulator-name = "P1.8V_LDO_OUT11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "P1.8V_LDO_OUT13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - }; - vdd: fixed-regulator@0 { compatible = "regulator-fixed"; regulator-name = "vdd-supply"; @@ -210,199 +53,360 @@ regulator-always-on; }; - i2c@12C70000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - status = "okay"; + sound { + compatible = "samsung,smdk-wm8994"; - eeprom@51 { - compatible = "samsung,s524ad0xd1"; - reg = <0x51>; + samsung,i2s-controller = <&i2s0>; + samsung,audio-codec = <&wm8994>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <24000000>; }; - wm8994: wm8994@1a { - compatible = "wlf,wm8994"; - reg = <0x1a>; + codec_mclk: codec-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16934000>; + }; + }; +}; - gpio-controller; - #gpio-cells = <2>; +&dp { + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <4>; + + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd>; + status = "okay"; +}; - clocks = <&codec_mclk>; - clock-names = "MCLK1"; +&ehci { + samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; +}; - AVDD2-supply = <&vdd>; - CPVDD-supply = <&vdd>; - DBVDD-supply = <&dbvdd>; - SPKVDD1-supply = <&spkvdd>; - SPKVDD2-supply = <&spkvdd>; +&fimd { + status = "okay"; + + display-timings { + native-mode = <&timing0>; + + timing0: timing@0 { + /* 1280x800 */ + clock-frequency = <50000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <4>; + hback-porch = <4>; + hsync-len = <4>; + vback-porch = <4>; + vfront-porch = <4>; + vsync-len = <4>; }; }; +}; - i2c@121D0000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <40000>; - samsung,i2c-slave-addr = <0x38>; - status = "okay"; +&hdmi { + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; +}; - sata_phy_i2c:sata-phy@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - }; +&i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + + eeprom@50 { + compatible = "samsung,s524ad0xd1"; + reg = <0x50>; }; - i2c@12C80000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - status = "okay"; + max77686@09 { + compatible = "maxim,max77686"; + reg = <0x09>; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_NONE>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "P1.0V_LDO_OUT1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; - }; + ldo2_reg: LDO2 { + regulator-name = "P1.2V_LDO_OUT2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; - i2c@12CE0000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - status = "okay"; + ldo3_reg: LDO3 { + regulator-name = "P1.8V_LDO_OUT3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; - hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; - }; + ldo4_reg: LDO4 { + regulator-name = "P2.8V_LDO_OUT4"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; - sata@122F0000 { - status = "okay"; - }; + ldo5_reg: LDO5 { + regulator-name = "P1.8V_LDO_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - sata-phy@12170000 { - status = "okay"; - samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; - }; + ldo6_reg: LDO6 { + regulator-name = "P1.1V_LDO_OUT6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; - mmc@12200000 { - status = "okay"; - num-slots = <1>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; - }; + ldo7_reg: LDO7 { + regulator-name = "P1.1V_LDO_OUT7"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; - mmc@12220000 { - status = "okay"; - num-slots = <1>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - }; + ldo8_reg: LDO8 { + regulator-name = "P1.0V_LDO_OUT8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo10_reg: LDO10 { + regulator-name = "P1.8V_LDO_OUT10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - spi_1: spi@12d30000 { - cs-gpios = <&gpa2 5 0>; - status = "okay"; + ldo11_reg: LDO11 { + regulator-name = "P1.8V_LDO_OUT11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - w25q80bw@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25x80"; - reg = <0>; - spi-max-frequency = <1000000>; + ldo12_reg: LDO12 { + regulator-name = "P3.0V_LDO_OUT12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; - controller-data { - samsung,spi-feedback-delay = <0>; + ldo13_reg: LDO13 { + regulator-name = "P1.8V_LDO_OUT13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; + ldo14_reg: LDO14 { + regulator-name = "P1.8V_LDO_OUT14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; - partition@40000 { - label = "Kernel"; - reg = <0x40000 0xc0000>; + ldo15_reg: LDO15 { + regulator-name = "P1.0V_LDO_OUT15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "P1.8V_LDO_OUT16"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "P1.8V_BUCK_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; }; }; }; +}; - hdmi { - hpd-gpio = <&gpx3 7 0>; - }; +&i2c_1 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; - codec@11000000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; + eeprom@51 { + compatible = "samsung,s524ad0xd1"; + reg = <0x51>; }; - i2s0: i2s@03830000 { - status = "okay"; + wm8994: wm8994@1a { + compatible = "wlf,wm8994"; + reg = <0x1a>; + + gpio-controller; + #gpio-cells = <2>; + + clocks = <&codec_mclk>; + clock-names = "MCLK1"; + + AVDD2-supply = <&vdd>; + CPVDD-supply = <&vdd>; + DBVDD-supply = <&dbvdd>; + SPKVDD1-supply = <&spkvdd>; + SPKVDD2-supply = <&spkvdd>; }; +}; - sound { - compatible = "samsung,smdk-wm8994"; +&i2c_2 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&wm8994>; + hdmiddc@50 { + compatible = "samsung,exynos4210-hdmiddc"; + reg = <0x50>; }; +}; + +&i2c_8 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; - usb@12110000 { - samsung,vbus-gpio = <&gpx2 6 0>; + hdmiphy@38 { + compatible = "samsung,exynos4212-hdmiphy"; + reg = <0x38>; }; +}; + +&i2c_9 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <40000>; + samsung,i2c-slave-addr = <0x38>; - dp-controller@145B0000 { - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - status = "okay"; + sata_phy_i2c: sata-phy@38 { + compatible = "samsung,exynos-sataphy-i2c"; + reg = <0x38>; }; +}; - fimd@14400000 { - status = "okay"; - display-timings { - native-mode = <&timing0>; - timing0: timing@0 { - /* 1280x800 */ - clock-frequency = <50000>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <4>; - hback-porch = <4>; - hsync-len = <4>; - vback-porch = <4>; - vfront-porch = <4>; - vsync-len = <4>; - }; +&i2s0 { + status = "okay"; +}; + +&mfc { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; +}; + +&mmc_0 { + status = "okay"; + num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&mmc_2 { + status = "okay"; + num-slots = <1>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sata_phy { + status = "okay"; + samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; +}; + +&spi_1 { + status = "okay"; + cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; + + w25q80bw@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25x80"; + reg = <0>; + spi-max-frequency = <1000000>; + + controller-data { + samsung,spi-feedback-delay = <0>; }; - }; - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; }; - codec_mclk: codec-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16934000>; + partition@40000 { + label = "Kernel"; + reg = <0x40000 0xc0000>; }; }; }; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index e51fcef884a4..f9bc04b8f7b3 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -6,10 +6,13 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. -*/ + */ /dts-v1/; #include +#include +#include +#include #include "exynos5250.dtsi" / { @@ -25,76 +28,7 @@ }; chosen { - }; - - rtc@101E0000 { - status = "okay"; - }; - - pinctrl@11400000 { - ec_irq: ec-irq { - samsung,pins = "gpx1-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - sd3_clk: sd3-clk { - samsung,pin-drv = <0>; - }; - - sd3_cmd: sd3-cmd { - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pin-drv = <0>; - }; - - max98095_en: max98095-en { - samsung,pins = "gpx1-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - tps65090_irq: tps65090-irq { - samsung,pins = "gpx2-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - usb3_vbus_en: usb3-vbus-en { - samsung,pins = "gpx2-7"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; - }; - }; - - pinctrl@13400000 { - arb_their_claim: arb-their-claim { - samsung,pins = "gpe0-4"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - arb_our_claim: arb-our-claim { - samsung,pins = "gpf0-3"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; + bootargs = "console=tty1"; }; gpio-keys { @@ -102,14 +36,14 @@ power { label = "Power"; - gpios = <&gpx1 3 1>; - linux,code = <116>; /* KEY_POWER */ + gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; + linux,code = ; gpio-key,wakeup; }; lid-switch { label = "Lid"; - gpios = <&gpx3 5 1>; + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; linux,input-type = <5>; /* EV_SW */ linux,code = <0>; /* SW_LID */ debounce-interval = <1>; @@ -130,8 +64,8 @@ i2c-parent = <&{/i2c@12CA0000}>; - our-claim-gpio = <&gpf0 3 1>; - their-claim-gpios = <&gpe0 4 1>; + our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>; + their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; slew-delay-us = <10>; wait-retry-us = <3000>; wait-free-us = <50000>; @@ -154,7 +88,7 @@ cros_ec: embedded-controller { compatible = "google,cros-ec-i2c"; reg = <0x1e>; - interrupts = <6 0>; + interrupts = <6 IRQ_TYPE_NONE>; interrupt-parent = <&gpx1>; pinctrl-names = "default"; pinctrl-0 = <&ec_irq>; @@ -241,13 +175,6 @@ }; i2c@12CD0000 { - max98095: codec@11 { - compatible = "maxim,max98095"; - reg = <0x11>; - pinctrl-0 = <&max98095_en>; - pinctrl-names = "default"; - }; - ptn3460: lvds-bridge@20 { compatible = "nxp,ptn3460"; reg = <0x20>; @@ -258,10 +185,6 @@ }; }; - i2s0: i2s@03830000 { - status = "okay"; - }; - sound { compatible = "google,snow-audio-max98095"; @@ -275,20 +198,12 @@ regulator-name = "P5.0V_USB3CON"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpx2 7 0>; + gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb3_vbus_en>; enable-active-high; }; - phy@12100000 { - vbus-supply = <&usb3_vbus_reg>; - }; - - usb@12110000 { - samsung,vbus-gpio = <&gpx1 1 0>; - }; - fixed-rate-clocks { xxti { compatible = "samsung,clock-xxti"; @@ -296,18 +211,6 @@ }; }; - hdmi { - hpd-gpio = <&gpx3 7 0>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - phy = <&hdmiphy>; - ddc = <&i2c_2>; - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; - }; - backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 1000000 0>; @@ -319,30 +222,46 @@ pinctrl-names = "default"; }; - fimd@14400000 { - status = "okay"; - samsung,invert-vclk; - }; - panel: panel { compatible = "auo,b116xw03"; power-supply = <&fet6>; backlight = <&backlight>; }; +}; - dp-controller@145B0000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <2>; - samsung,hpd-gpio = <&gpx0 7 0>; - bridge = <&ptn3460>; - }; +&dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <2>; + samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>; + bridge = <&ptn3460>; +}; + +&ehci { + samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; +}; + +&fimd { + status = "okay"; + samsung,invert-vclk; +}; + +&hdmi { + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + phy = <&hdmiphy>; + ddc = <&i2c_2>; + hdmi-en-supply = <&tps65090_fet7>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; }; &i2c_0 { @@ -350,10 +269,10 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - max77686@09 { + max77686: max77686@09 { compatible = "maxim,max77686"; interrupt-parent = <&gpx3>; - interrupts = <2 0>; + interrupts = <2 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&max77686_irq>; wakeup-source; @@ -503,7 +422,7 @@ trackpad { reg = <0x67>; compatible = "cypress,cyapa"; - interrupts = <2 0>; + interrupts = <2 IRQ_TYPE_NONE>; interrupt-parent = <&gpx1>; wakeup-source; }; @@ -550,6 +469,13 @@ status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + + max98095: codec@11 { + compatible = "maxim,max98095"; + reg = <0x11>; + pinctrl-0 = <&max98095_en>; + pinctrl-names = "default"; + }; }; &i2c_8 { @@ -563,6 +489,10 @@ }; }; +&i2s0 { + status = "okay"; +}; + &mmc_0 { status = "okay"; num-slots = <1>; @@ -587,7 +517,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; bus-width = <4>; - wp-gpios = <&gpc2 1 0>; + wp-gpios = <&gpc2 1 GPIO_ACTIVE_HIGH>; cap-sd-highspeed; }; @@ -610,12 +540,82 @@ }; &pinctrl_0 { + ec_irq: ec-irq { + samsung,pins = "gpx1-6"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + max98095_en: max98095-en { + samsung,pins = "gpx1-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + tps65090_irq: tps65090-irq { + samsung,pins = "gpx2-6"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + usb3_vbus_en: usb3-vbus-en { + samsung,pins = "gpx2-7"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + max77686_irq: max77686-irq { samsung,pins = "gpx3-2"; samsung,pin-function = <0>; samsung,pin-pud = <0>; samsung,pin-drv = <0>; }; + + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_1 { + arb_their_claim: arb-their-claim { + samsung,pins = "gpe0-4"; + samsung,pin-function = <0>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + arb_our_claim: arb-our-claim { + samsung,pins = "gpf0-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&sd3_bus4 { + samsung,pin-drv = <0>; +}; + +&sd3_clk { + samsung,pin-drv = <0>; +}; + +&sd3_cmd { + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; }; &spi_1 { @@ -624,4 +624,8 @@ num-cs = <1>; }; +&usbdrd_phy { + vbus-supply = <&usb3_vbus_reg>; +}; + #include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts new file mode 100644 index 000000000000..f5566f84d885 --- /dev/null +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -0,0 +1,536 @@ +/* + * Google Spring board device tree source + * + * Copyright (c) 2013 Google, Inc + * Copyright (c) 2014 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include +#include +#include +#include "exynos5250.dtsi" + +/ { + model = "Google Spring"; + compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5"; + + memory { + reg = <0x40000000 0x80000000>; + }; + + chosen { + bootargs = "console=tty1"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&power_key_irq>, <&lid_irq>; + + power { + label = "Power"; + gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + }; + + lid-switch { + label = "Lid"; + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + gpio-key,wakeup; + }; + }; + + usb-hub { + compatible = "smsc,usb3503a"; + reset-gpios = <&gpe1 0 GPIO_ACTIVE_LOW>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <24000000>; + }; + }; +}; + +&dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd_gpio>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <1>; + samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>; +}; + +&ehci { + samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; +}; + +&fimd { + status = "okay"; + samsung,invert-vclk; +}; + +&hdmi { + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + phy = <&hdmiphy>; + ddc = <&i2c_2>; + hdmi-en-supply = <&ldo8_reg>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; +}; + +&i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + s5m8767-pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; + wakeup-source; + + s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */ + <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */ + <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */ + + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */ + <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */ + <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */ + + /* + * The following arrays of DVS voltages are not used, since we are + * not using GPIOs to control PMIC bucks, but they must be defined + * to please the driver. + */ + s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1000000>, <1000000>, + <1000000>, <1000000>; + + s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "en32khz_ap", + "en32khz_cp", + "en32khz_bt"; + }; + + regulators { + ldo4_reg: LDO4 { + regulator-name = "P1.0V_LDO_OUT4"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo5_reg: LDO5 { + regulator-name = "P1.0V_LDO_OUT5"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_mydp"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo7_reg: LDO7 { + regulator-name = "P1.1V_LDO_OUT7"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo8_reg: LDO8 { + regulator-name = "P1.0V_LDO_OUT8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo10_reg: LDO10 { + regulator-name = "P1.8V_LDO_OUT10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo11_reg: LDO11 { + regulator-name = "P1.8V_LDO_OUT11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo12_reg: LDO12 { + regulator-name = "P3.0V_LDO_OUT12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo13_reg: LDO13 { + regulator-name = "P1.8V_LDO_OUT13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo14_reg: LDO14 { + regulator-name = "P1.8V_LDO_OUT14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo15_reg: LDO15 { + regulator-name = "P1.0V_LDO_OUT15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo16_reg: LDO16 { + regulator-name = "P1.8V_LDO_OUT16"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo17_reg: LDO17 { + regulator-name = "P2.8V_LDO_OUT17"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo25_reg: LDO25 { + regulator-name = "vdd_bridge"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + op_mode = <1>; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + op_mode = <3>; + }; + + buck5_reg: BUCK5 { + regulator-name = "P1.8V_BUCK_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck6_reg: BUCK6 { + regulator-name = "P1.2V_BUCK_OUT6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <0>; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_ummc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + }; + }; +}; + +&i2c_1 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; +}; + +/* + * Disabled pullups since external part has its own pullups and + * double-pulling gets us out of spec in some cases. + */ +&i2c2_bus { + samsung,pin-pud = <0>; +}; + +&i2c_2 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + hdmiddc@50 { + compatible = "samsung,exynos4210-hdmiddc"; + reg = <0x50>; + }; +}; + +&i2c_3 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_4 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + cros_ec: embedded-controller { + compatible = "google,cros-ec-i2c"; + reg = <0x1e>; + interrupts = <6 IRQ_TYPE_NONE>; + interrupt-parent = <&gpx1>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&ec_irq>; + }; +}; + +&i2c_5 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_7 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_8 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + hdmiphy: hdmiphy@38 { + compatible = "samsung,exynos4212-hdmiphy"; + reg = <0x38>; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&mfc { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; +}; + +&mmc_0 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +/* + * On Spring we've got SIP WiFi and so can keep drive strengths low to + * reduce EMI. + */ +&mmc_1 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&pinctrl_0 { + s5m8767_dvs: s5m8767-dvs { + samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + dp_hpd_gpio: dp-hpd-gpio { + samsung,pins = "gpc3-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + power_key_irq: power-key-irq { + samsung,pins = "gpx1-3"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + ec_irq: ec-irq { + samsung,pins = "gpx1-6"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + s5m8767_ds: s5m8767-ds { + samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + s5m8767_irq: s5m8767-irq { + samsung,pins = "gpx3-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lid_irq: lid-irq { + samsung,pins = "gpx3-5"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_1 { + hsic_reset: hsic-reset { + samsung,pins = "gpe1-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&sd1_bus4 { + samsung,pin-drv = <0>; +}; + +&sd1_cd { + samsung,pin-drv = <0>; +}; + +&sd1_clk { + samsung,pin-drv = <0>; +}; + +&sd1_cmd { + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; +}; + +&spi_1 { + status = "okay"; + samsung,spi-src-clk = <0>; + num-cs = <1>; +}; + +#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index f21b9aa00fbb..012b0211afed 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -218,7 +218,7 @@ clock-names = "fimg2d"; }; - codec@11000000 { + mfc: codec@11000000 { compatible = "samsung,mfc-v6"; reg = <0x11000000 0x10000>; interrupts = <0 96 0>; @@ -227,7 +227,7 @@ clock-names = "mfc"; }; - rtc@101E0000 { + rtc: rtc@101E0000 { clocks = <&clock CLK_RTC>; clock-names = "rtc"; status = "disabled"; @@ -261,7 +261,7 @@ clock-names = "uart", "clk_uart_baud0"; }; - sata@122F0000 { + sata: sata@122F0000 { compatible = "snps,dwc-ahci"; samsung,sata-freq = <66>; reg = <0x122F0000 0x1ff>; @@ -573,7 +573,7 @@ #phy-cells = <1>; }; - usb@12110000 { + ehci: usb@12110000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12110000 0x100>; interrupts = <0 71 0>; @@ -588,7 +588,7 @@ }; }; - usb@12120000 { + ohci: usb@12120000 { compatible = "samsung,exynos4210-ohci"; reg = <0x12120000 0x100>; interrupts = <0 71 0>; @@ -710,7 +710,7 @@ clock-names = "gscl"; }; - hdmi { + hdmi: hdmi { compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x70000>; interrupts = <0 95 0>; @@ -736,14 +736,14 @@ #phy-cells = <0>; }; - dp-controller@145B0000 { + dp: dp-controller@145B0000 { clocks = <&clock CLK_DP>; clock-names = "dp"; phys = <&dp_phy>; phy-names = "dp"; }; - fimd@14400000 { + fimd: fimd@14400000 { clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; clock-names = "sclk_fimd", "fimd"; }; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 82cdb74484cc..9a050e19a4dc 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -12,6 +12,7 @@ #include #include #include +#include #include "exynos5420.dtsi" / { @@ -151,7 +152,7 @@ status = "okay"; clock-frequency = <400000>; - max77802-pmic@9 { + max77802: max77802-pmic@9 { compatible = "maxim,max77802"; interrupt-parent = <&gpx3>; interrupts = <1 IRQ_TYPE_NONE>; @@ -560,7 +561,7 @@ status = "okay"; num-slots = <1>; broken-cd; - caps2-mmc-hs200-1_8v; + mmc-hs200-1_8v; cap-mmc-highspeed; non-removable; card-detect-delay = <200>; @@ -727,6 +728,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; + clock-names = "rtc", "rtc_src"; }; &spi_2 { diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 7bb1c8dd42dd..e8fdda827fc9 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -12,6 +12,7 @@ #include #include #include +#include #include "exynos5800.dtsi" / { @@ -150,7 +151,7 @@ status = "okay"; clock-frequency = <400000>; - max77802-pmic@9 { + max77802: max77802-pmic@9 { compatible = "maxim,max77802"; interrupt-parent = <&gpx3>; interrupts = <1 IRQ_TYPE_NONE>; @@ -548,7 +549,7 @@ status = "okay"; num-slots = <1>; broken-cd; - caps2-mmc-hs200-1_8v; + mmc-hs200-1_8v; cap-mmc-highspeed; non-removable; card-detect-delay = <200>; @@ -715,6 +716,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; + clock-names = "rtc", "rtc_src"; }; &spi_2 { diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts index 05b44c272c9a..721b09238f58 100644 --- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts +++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts @@ -51,3 +51,36 @@ &uart0 { status = "okay"; }; + +&gmac0 { + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&phy2>; + phy-mode = "mii"; + /* Placeholder, overwritten by bootloader */ + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + phy2: ethernet-phy@2 { + reg = <2>; + }; +}; + +&gmac1 { + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + /* Placeholder, overwritten by bootloader */ + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&ahci { + phys = <&sata_phy>; + phy-names = "sata-phy"; +}; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index f85ba2924ff7..c52722b14e4a 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -131,6 +131,249 @@ clock-names = "apb_pclk"; status = "disabled"; }; + + gpio0: gpio@b20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb20000 0x1000>; + interrupts = <0 108 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@b21000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb21000 0x1000>; + interrupts = <0 109 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio2: gpio@b22000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb22000 0x1000>; + interrupts = <0 110 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio3: gpio@b23000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb23000 0x1000>; + interrupts = <0 111 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio4: gpio@b24000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb24000 0x1000>; + interrupts = <0 112 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio5: gpio@004000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x004000 0x1000>; + interrupts = <0 113 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio6: gpio@b26000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb26000 0x1000>; + interrupts = <0 114 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio7: gpio@b27000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb27000 0x1000>; + interrupts = <0 115 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio8: gpio@b28000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb28000 0x1000>; + interrupts = <0 116 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio9: gpio@b29000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb29000 0x1000>; + interrupts = <0 117 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio10: gpio@b2a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2a000 0x1000>; + interrupts = <0 118 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio11: gpio@b2b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2b000 0x1000>; + interrupts = <0 119 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio12: gpio@b2c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2c000 0x1000>; + interrupts = <0 120 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio13: gpio@b2d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2d000 0x1000>; + interrupts = <0 121 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio14: gpio@b2e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2e000 0x1000>; + interrupts = <0 122 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio15: gpio@b2f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2f000 0x1000>; + interrupts = <0 123 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio16: gpio@b30000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb30000 0x1000>; + interrupts = <0 124 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio17: gpio@b31000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb31000 0x1000>; + interrupts = <0 125 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + wdt0: watchdog@a2c000 { + compatible = "arm,sp805", "arm,primecell"; + arm,primecell-periphid = <0x00141805>; + reg = <0xa2c000 0x1000>; + interrupts = <0 29 4>; + clocks = <&clock HIX5HD2_WDG0_RST>; + clock-names = "apb_pclk"; + }; }; local_timer@00a00600 { @@ -148,9 +391,15 @@ }; sysctrl: system-controller@00000000 { - compatible = "hisilicon,sysctrl"; + compatible = "hisilicon,sysctrl", "syscon"; reg = <0x00000000 0x1000>; - reboot-offset = <0x4>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&sysctrl>; + offset = <0x4>; + mask = <0xdeadbeef>; }; cpuctrl@00a22000 { @@ -166,5 +415,142 @@ #clock-cells = <1>; }; }; + + /* unremovable emmc as mmcblk0 */ + mmc: mmc@1830000 { + compatible = "snps,dw-mshc"; + reg = <0x1830000 0x1000>; + interrupts = <0 35 4>; + clocks = <&clock HIX5HD2_MMC_CIU_RST>, + <&clock HIX5HD2_MMC_BIU_CLK>; + clock-names = "ciu", "biu"; + }; + + sd: mmc@1820000 { + compatible = "snps,dw-mshc"; + reg = <0x1820000 0x1000>; + interrupts = <0 34 4>; + clocks = <&clock HIX5HD2_SD_CIU_RST>, + <&clock HIX5HD2_SD_BIU_CLK>; + clock-names = "ciu","biu"; + }; + + gmac0: ethernet@1840000 { + compatible = "hisilicon,hix5hd2-gmac"; + reg = <0x1840000 0x1000>,<0x184300c 0x4>; + interrupts = <0 71 4>; + clocks = <&clock HIX5HD2_MAC0_CLK>; + status = "disabled"; + }; + + gmac1: ethernet@1841000 { + compatible = "hisilicon,hix5hd2-gmac"; + reg = <0x1841000 0x1000>,<0x1843010 0x4>; + interrupts = <0 72 4>; + clocks = <&clock HIX5HD2_MAC1_CLK>; + status = "disabled"; + }; + + usb0: ehci@1890000 { + compatible = "generic-ehci"; + reg = <0x1890000 0x1000>; + interrupts = <0 66 4>; + clocks = <&clock HIX5HD2_USB_CLK>; + }; + + usb1: ohci@1880000 { + compatible = "generic-ohci"; + reg = <0x1880000 0x1000>; + interrupts = <0 67 4>; + clocks = <&clock HIX5HD2_USB_CLK>; + }; + + peripheral_ctrl: syscon@a20000 { + compatible = "syscon"; + reg = <0xa20000 0x1000>; + }; + + sata_phy: phy@1900000 { + compatible = "hisilicon,hix5hd2-sata-phy"; + reg = <0x1900000 0x10000>; + #phy-cells = <0>; + hisilicon,peripheral-syscon = <&peripheral_ctrl>; + hisilicon,power-reg = <0x8 10>; + }; + + ahci: sata@1900000 { + compatible = "hisilicon,hisi-ahci"; + reg = <0x1900000 0x10000>; + interrupts = <0 70 4>; + clocks = <&clock HIX5HD2_SATA_CLK>; + }; + + ir: ir@001000 { + compatible = "hisilicon,hix5hd2-ir"; + reg = <0x001000 0x1000>; + interrupts = <0 47 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + hisilicon,power-syscon = <&sysctrl>; + }; + + i2c0: i2c@b10000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb10000 0x1000>; + interrupts = <0 38 4>; + clocks = <&clock HIX5HD2_I2C0_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@b11000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb11000 0x1000>; + interrupts = <0 39 4>; + clocks = <&clock HIX5HD2_I2C1_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@b12000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb12000 0x1000>; + interrupts = <0 40 4>; + clocks = <&clock HIX5HD2_I2C2_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@b13000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb13000 0x1000>; + interrupts = <0 41 4>; + clocks = <&clock HIX5HD2_I2C3_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@b16000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb16000 0x1000>; + interrupts = <0 43 4>; + clocks = <&clock HIX5HD2_I2C4_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@b17000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb17000 0x1000>; + interrupts = <0 44 4>; + clocks = <&clock HIX5HD2_I2C5_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/k2e-evm.dts index c568f067604d..560d62150ade 100644 --- a/arch/arm/boot/dts/k2e-evm.dts +++ b/arch/arm/boot/dts/k2e-evm.dts @@ -139,3 +139,15 @@ }; }; }; + +&mdio { + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi index c358b4b9a073..5fc14683d6df 100644 --- a/arch/arm/boot/dts/k2e.dtsi +++ b/arch/arm/boot/dts/k2e.dtsi @@ -85,6 +85,51 @@ #gpio-cells = <2>; gpio,syscon-dev = <&devctrl 0x240>; }; + + pcie@21020000 { + compatible = "ti,keystone-pcie","snps,dw-pcie"; + clocks = <&clkpcie1>; + clock-names = "pcie"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; + ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000 + 0x82000000 0 0x60000000 0x60000000 0 0x10000000>; + + device_type = "pci"; + num-lanes = <2>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ + <0 0 0 2 &pcie_intc1 1>, /* INT B */ + <0 0 0 3 &pcie_intc1 2>, /* INT C */ + <0 0 0 4 &pcie_intc1 3>; /* INT D */ + + pcie_msi_intc1: msi-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + pcie_intc1: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + }; }; }; diff --git a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/k2l-evm.dts index fec43128a2e0..85cc7f2872d7 100644 --- a/arch/arm/boot/dts/k2l-evm.dts +++ b/arch/arm/boot/dts/k2l-evm.dts @@ -116,3 +116,15 @@ }; }; }; + +&mdio { + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 5d3e83fa2242..c06542b2c954 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -285,5 +285,50 @@ #interrupt-cells = <1>; ti,syscon-dev = <&devctrl 0x2a0>; }; + + pcie@21800000 { + compatible = "ti,keystone-pcie", "snps,dw-pcie"; + clocks = <&clkpcie>; + clock-names = "pcie"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; + ranges = <0x81000000 0 0 0x23250000 0 0x4000 + 0x82000000 0 0x50000000 0x50000000 0 0x10000000>; + + device_type = "pci"; + num-lanes = <2>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ + <0 0 0 2 &pcie_intc0 1>, /* INT B */ + <0 0 0 3 &pcie_intc0 2>, /* INT C */ + <0 0 0 4 &pcie_intc0 3>; /* INT D */ + + pcie_msi_intc0: msi-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + pcie_intc0: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts new file mode 100644 index 000000000000..786959ee9cbe --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-dir665.dts @@ -0,0 +1,278 @@ +/* + * Copyright (C) 2014 Claudio Leite + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "D-Link DIR-665"; + compatible = "dlink,dir-665", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; /* 128 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 =< &pmx_led_usb + &pmx_led_internet_blue + &pmx_led_internet_amber + &pmx_led_5g &pmx_led_status_blue + &pmx_led_wps &pmx_led_status_amber + &pmx_led_24g + &pmx_btn_restart &pmx_btn_wps>; + pinctrl-names = "default"; + + pmx_led_usb: pmx-led-usb { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + pmx_led_internet_blue: pmx-led-internet-blue { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_led_internet_amber: pmx-led-internet-amber { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_led_5g: pmx-led-5g { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_led_status_blue: pmx-led-status-blue { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + pmx_led_wps: pmx-led-wps { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_led_status_amber: pmx-led-status-amber { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + pmx_led_24g: pmx-led-24g { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + pmx_btn_restart: pmx-btn-restart { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + pmx_btn_wps: pmx-btn-wps { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + }; + + spi@10600 { + status = "okay"; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25l12805d"; + spi-max-frequency = <50000000>; + reg = <0>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "nvram"; + reg = <0x30000 0x10000>; + read-only; + }; + + partition@40000 { + label = "kernel"; + reg = <0x40000 0x180000>; + }; + + partition@1c0000 { + label = "rootfs"; + reg = <0x1c0000 0xe00000>; + }; + + cal_data: partition@fc0000 { + label = "cal_data"; + reg = <0xfc0000 0x10000>; + read-only; + }; + + partition@fd0000 { + label = "lang_pack"; + reg = <0xfd0000 0x30000>; + read-only; + }; + }; + }; + + serial@12000 { + status = "okay"; + }; + + i2c@11000 { + status = "okay"; + }; + + ehci@50000 { + status = "okay"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + blue-usb { + label = "dir665:blue:usb"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + blue-internet { + /* Can only be turned on if the Internet + * Ethernet port has Link + */ + label = "dir665:blue:internet"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + amber-internet { + label = "dir665:amber:internet"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + blue-wifi5g { + label = "dir665:blue:5g"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + }; + blue-status { + label = "dir665:blue:status"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + blue-wps { + label = "dir665:blue:wps"; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + amber-status { + label = "dir665:amber:status"; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; + blue-24g { + label = "dir665:blue:24g"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + wps { + label = "wps"; + linux,code = ; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + }; + + dsa@0 { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <ð0port>; + dsa,mii-bus = <&mdio>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0>; /* MDIO address 0, switch 0 in tree */ + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + }; + }; + }; +}; + +&mdio { + status = "okay"; +}; + +/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set + * fixed speed and duplex. */ +ð0 { + status = "okay"; + + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +/* eth1 is connected to the switch as well. However DSA only supports a + * single CPU port. So leave this port disabled to avoid confusion. */ + +ð1 { + status = "disabled"; +}; + +/* There is no battery on the boards, so the RTC does not keep time + * when there is no power, making it useless. */ +&rtc { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi index 521c587acaee..445fafc73254 100644 --- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi +++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi @@ -23,24 +23,29 @@ ethernet@gpmc { compatible = "smsc,lan9221", "smsc,lan9115"; bank-width = <2>; - gpmc,mux-add-data; - gpmc,cs-on-ns = <1>; - gpmc,cs-rd-off-ns = <180>; - gpmc,cs-wr-off-ns = <180>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <144>; - gpmc,page-burst-access-ns = <24>; - gpmc,bus-turnaround-ns = <90>; - gpmc,cycle2cycle-delay-ns = <90>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; + gpmc,device-width = <1>; + gpmc,cycle2cycle-samecsen = <1>; + gpmc,cycle2cycle-diffcsen = <1>; + gpmc,cs-on-ns = <5>; + gpmc,cs-rd-off-ns = <150>; + gpmc,cs-wr-off-ns = <150>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <15>; + gpmc,adv-wr-off-ns = <40>; + gpmc,oe-on-ns = <45>; + gpmc,oe-off-ns = <140>; + gpmc,we-on-ns = <45>; + gpmc,we-off-ns = <140>; + gpmc,rd-cycle-ns = <155>; + gpmc,wr-cycle-ns = <155>; + gpmc,access-ns = <120>; + gpmc,page-burst-access-ns = <20>; + gpmc,bus-turnaround-ns = <75>; + gpmc,cycle2cycle-delay-ns = <75>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,wr-access-ns = <0>; vddvario-supply = <&vddvario>; vdd33a-supply = <&vdd33a>; reg-io-width = <4>; diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi index 68221fab978d..46ef3e443861 100644 --- a/arch/arm/boot/dts/omap-zoom-common.dtsi +++ b/arch/arm/boot/dts/omap-zoom-common.dtsi @@ -5,7 +5,7 @@ #include "omap-gpmc-smsc911x.dtsi" &gpmc { - ranges = <3 0 0x10000000 0x00000400>, + ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */ <7 0 0x2c000000 0x01000000>; /* @@ -15,7 +15,65 @@ */ uart@3,0 { compatible = "ns16550a"; - reg = <3 0 0x100>; + reg = <3 0 8>; /* CS3, offset 0, IO size 8 */ + bank-width = <2>; + reg-shift = <1>; + reg-io-width = <1>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ + clock-frequency = <1843200>; + current-speed = <115200>; + gpmc,mux-add-data = <0>; + gpmc,device-width = <1>; + gpmc,wait-pin = <1>; + gpmc,cycle2cycle-samecsen = <1>; + gpmc,cycle2cycle-diffcsen = <1>; + gpmc,cs-on-ns = <5>; + gpmc,cs-rd-off-ns = <155>; + gpmc,cs-wr-off-ns = <155>; + gpmc,adv-on-ns = <15>; + gpmc,adv-rd-off-ns = <40>; + gpmc,adv-wr-off-ns = <40>; + gpmc,oe-on-ns = <45>; + gpmc,oe-off-ns = <145>; + gpmc,we-on-ns = <45>; + gpmc,we-off-ns = <145>; + gpmc,rd-cycle-ns = <155>; + gpmc,wr-cycle-ns = <155>; + gpmc,access-ns = <145>; + gpmc,page-burst-access-ns = <20>; + gpmc,bus-turnaround-ns = <20>; + gpmc,cycle2cycle-delay-ns = <20>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <45>; + gpmc,wr-access-ns = <145>; + }; + uart@3,1 { + compatible = "ns16550a"; + reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */ + bank-width = <2>; + reg-shift = <1>; + reg-io-width = <1>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ + clock-frequency = <1843200>; + current-speed = <115200>; + }; + uart@3,2 { + compatible = "ns16550a"; + reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */ + bank-width = <2>; + reg-shift = <1>; + reg-io-width = <1>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ + clock-frequency = <1843200>; + current-speed = <115200>; + }; + uart@3,3 { + compatible = "ns16550a"; + reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */ bank-width = <2>; reg-shift = <1>; reg-io-width = <1>; diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi index 24c50db2a478..c9f1e93a95ae 100644 --- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi +++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi @@ -40,14 +40,14 @@ }; &gpmc { - ranges = <0 0 0x04000000 0x10000000>; + ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ /* gpio-irq for dma: 26 */ onenand@0,0 { #address-cells = <1>; #size-cells = <1>; - reg = <0 0 0x10000000>; + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ gpmc,sync-read; gpmc,burst-length = <16>; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index ae89aad01595..e2b2e93d7b61 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -157,6 +157,7 @@ interrupts = <26>, <34>; interrupt-names = "dsp", "iva"; ti,hwmods = "mailbox"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <6>; mbox_dsp: dsp { diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/omap2430-sdp.dts index 2c90d29b4cad..05eca2e4430f 100644 --- a/arch/arm/boot/dts/omap2430-sdp.dts +++ b/arch/arm/boot/dts/omap2430-sdp.dts @@ -43,7 +43,31 @@ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */ reg = <5 0x300 0xf>; bank-width = <2>; - gpmc,mux-add-data; - }; + gpmc,sync-clk-ps = <0>; + gpmc,mux-add-data = <2>; + gpmc,device-width = <1>; + gpmc,cycle2cycle-samecsen = <1>; + gpmc,cycle2cycle-diffcsen = <1>; + gpmc,cs-on-ns = <7>; + gpmc,cs-rd-off-ns = <233>; + gpmc,cs-wr-off-ns = <233>; + gpmc,adv-on-ns = <22>; + gpmc,adv-rd-off-ns = <60>; + gpmc,adv-wr-off-ns = <60>; + gpmc,oe-on-ns = <67>; + gpmc,oe-off-ns = <210>; + gpmc,we-on-ns = <67>; + gpmc,we-off-ns = <210>; + gpmc,rd-cycle-ns = <233>; + gpmc,wr-cycle-ns = <233>; + gpmc,access-ns = <233>; + gpmc,page-burst-access-ns = <30>; + gpmc,bus-turnaround-ns = <30>; + gpmc,cycle2cycle-delay-ns = <30>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,wr-access-ns = <0>; + }; }; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index b56d71611026..0dc8de2782b1 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -247,6 +247,7 @@ reg = <0x48094000 0x200>; interrupts = <26>; ti,hwmods = "mailbox"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <6>; mbox_dsp: dsp { diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts index d00502f4fd9b..0ab748cf7749 100644 --- a/arch/arm/boot/dts/omap3-cm-t3517.dts +++ b/arch/arm/boot/dts/omap3-cm-t3517.dts @@ -134,3 +134,14 @@ bus-width = <4>; cap-power-off-card; }; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins_common + &dss_dpi_pins_cm_t35x + >; +}; + diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts index d1458496520e..8dd14fcf6825 100644 --- a/arch/arm/boot/dts/omap3-cm-t3530.dts +++ b/arch/arm/boot/dts/omap3-cm-t3530.dts @@ -46,3 +46,14 @@ bus-width = <4>; cap-power-off-card; }; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins_common + &dss_dpi_pins_cm_t35x + >; +}; + diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts index b3f9a50b3bc8..46eadb21b5ef 100644 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ b/arch/arm/boot/dts/omap3-cm-t3730.dts @@ -31,6 +31,19 @@ }; }; +&omap3_pmx_wkup { + dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ + OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ + OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ + OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ + OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ + >; + }; +}; + &omap3_pmx_core { mmc2_pins: pinmux_mmc2_pins { @@ -61,3 +74,14 @@ bus-width = <4>; cap-power-off-card; }; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins_common + &dss_dpi_pins_cm_t3730 + >; +}; + diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi index c671a2299ea8..b074673703bf 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi @@ -76,6 +76,45 @@ OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ >; }; + + dss_dpi_pins_common: pinmux_dss_dpi_pins_common { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + >; + }; }; &uart3 { diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts index da402f0fdab4..169037e5ff53 100644 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts @@ -106,10 +106,10 @@ }; &gpmc { - ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; gpmc,sync-clk-ps = <0>; diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index a8bd4349c7d2..16e8ce350dda 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -154,13 +154,14 @@ }; &gpmc { - ranges = <0 0 0x00000000 0x20000000>, + ranges = <0 0 0x00000000 0x1000000>, /* CS0: 16MB for NAND */ <5 0 0x2c000000 0x01000000>; nand@0,0 { linux,mtd-name= "hynix,h8kds0un0mer-4em"; - reg = <0 0 0>; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; + gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; gpmc,sync-clk-ps = <0>; diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index fd34f913ace3..655d6e920a86 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -104,67 +104,67 @@ uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */ + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < - 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < - 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ >; }; dss_dpi_pins: pinmux_dss_dpi_pins { pinctrl-single,pins = < - 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; }; }; @@ -397,10 +397,10 @@ }; &gpmc { - ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index e2d163bf0619..8a63ad2286aa 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -31,18 +31,6 @@ regulator-always-on; }; - lbee1usjyc_vmmc: lbee1usjyc_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&lbee1usjyc_pins>; - compatible = "regulator-fixed"; - regulator-name = "regulator-lbee1usjyc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 WIFI_PDN */ - startup-delay-us = <10000>; - enable-active-high; - vin-supply = <&vdd33>; - }; }; &omap3_pmx_core { @@ -53,13 +41,6 @@ >; }; - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ @@ -67,15 +48,6 @@ >; }; - /* WiFi/BT combo */ - lbee1usjyc_pins: pinmux_lbee1usjyc_pins { - pinctrl-single,pins = < - 0x136 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 */ - 0x138 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ - 0x13a (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ - >; - }; - mcbsp2_pins: pinmux_mcbsp2_pins { pinctrl-single,pins = < 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ @@ -120,13 +92,6 @@ >; }; - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - 0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ - 0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ - >; - }; - i2c3_pins: pinmux_i2c3_pins { pinctrl-single,pins = < 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ @@ -135,6 +100,55 @@ }; }; +&gpmc { + nand@0,0 { + linux,mtd-name= "micron,mt29c4g96maz"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SPL"; + reg = <0 0x100000>; + }; + partition@80000 { + label = "U-Boot"; + reg = <0x100000 0x180000>; + }; + partition@1c0000 { + label = "Environment"; + reg = <0x280000 0x100000>; + }; + partition@280000 { + label = "Kernel"; + reg = <0x380000 0x300000>; + }; + partition@780000 { + label = "Filesystem"; + reg = <0x680000 0x1f980000>; + }; + }; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -156,12 +170,6 @@ #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; -}; - &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; @@ -181,14 +189,6 @@ bus-width = <4>; }; -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&lbee1usjyc_vmmc>; - bus-width = <4>; - non-removable; -}; - &mmc3 { status = "disabled"; }; @@ -198,11 +198,6 @@ pinctrl-0 = <&uart1_pins>; }; -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi new file mode 100644 index 000000000000..e458c2185e3c --- /dev/null +++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi @@ -0,0 +1,246 @@ +/* + * Common Device Tree Source for IGEPv2 + * + * Copyright (C) 2014 Javier Martinez Canillas + * Copyright (C) 2014 Enric Balletbo i Serra + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-igep.dtsi" +#include "omap-gpmc-smsc9221.dtsi" + +/ { + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + compatible = "gpio-leds"; + + boot { + label = "omap3:green:boot"; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user0 { + label = "omap3:red:user0"; + gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + user1 { + label = "omap3:red:user1"; + gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + user2 { + label = "omap3:green:user1"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; + }; + }; + + /* HS USB Port 1 Power */ + hsusb1_power: hsusb1_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ + vcc-supply = <&hsusb1_power>; + }; + + tfp410: encoder@0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint@0 { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint@0 { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector@0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c3>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &tfp410_pins + &dss_dpi_pins + >; + + tfp410_pins: pinmux_tfp410_pins { + pinctrl-single,pins = < + 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ + >; + }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb1_pins + >; + + hsusbb1_pins: pinmux_hsusbb1_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ + OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ + OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ + OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ + OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ + OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ + >; + }; + + leds_pins: pinmux_leds_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ + >; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + + /* + * Display monitor features are burnt in the EEPROM + * as EDID data. + */ + eeprom@50 { + compatible = "ti,eeprom"; + reg = <0x50>; + }; +}; + +&gpmc { + ranges = <0 0 0x00000000 0x20000000>, + <5 0 0x2c000000 0x01000000>; + + ethernet@gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&smsc9221_pins>; + reg = <5 0 0xff>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&usbhshost { + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; + +&vpll2 { + /* Needed for DSS */ + regulator-name = "vdds_dsi"; +}; + +&dss { + status = "ok"; + + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts new file mode 100644 index 000000000000..cc8bd0cd8cf8 --- /dev/null +++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts @@ -0,0 +1,45 @@ +/* + * Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x) + * + * Copyright (C) 2012 Javier Martinez Canillas + * Copyright (C) 2012 Enric Balletbo i Serra + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-igep0020-common.dtsi" + +/ { + model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)"; + compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3"; + + /* Regulator to trigger the WL_EN signal of the Wifi module */ + lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbep5clwmc-wlen"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ + enable-active-high; + }; +}; + +&omap3_pmx_core { + lbep5clwmc_pins: pinmux_lbep5clwmc_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ + >; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; + vmmc-supply = <&lbep5clwmc_wlen>; + bus-width = <4>; + non-removable; +}; diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index b22caaaf774b..fea7f7edb45d 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts @@ -1,5 +1,5 @@ /* - * Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x) + * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x) * * Copyright (C) 2012 Javier Martinez Canillas * Copyright (C) 2012 Enric Balletbo i Serra @@ -9,272 +9,59 @@ * published by the Free Software Foundation. */ -#include "omap3-igep.dtsi" -#include "omap-gpmc-smsc9221.dtsi" +#include "omap3-igep0020-common.dtsi" / { - model = "IGEPv2 (TI OMAP AM/DM37x)"; + model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)"; compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3"; - leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - compatible = "gpio-leds"; - - boot { - label = "omap3:green:boot"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - user0 { - label = "omap3:red:user0"; - gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - user1 { - label = "omap3:red:user1"; - gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - user2 { - label = "omap3:green:user1"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; - }; + /* Regulator to trigger the WIFI_PDN signal of the Wifi module */ + lbee1usjyc_pdn: lbee1usjyc_pdn { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbee1usjyc-pdn"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 - WIFI_PDN */ + startup-delay-us = <10000>; + enable-active-high; }; - /* HS USB Port 1 Power */ - hsusb1_power: hsusb1_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ - vcc-supply = <&hsusb1_power>; - }; - - tfp410: encoder@0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint@0 { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint@0 { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector@0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; + /* Regulator to trigger the RESET_N_W signal of the Wifi module */ + lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbee1usjyc-reset-n-w"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - RESET_N_W */ + enable-active-high; }; }; &omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &tfp410_pins - &dss_dpi_pins - >; - - tfp410_pins: pinmux_tfp410_pins { + lbee1usjyc_pins: pinmux_lbee1usjyc_pins { pinctrl-single,pins = < - 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < - 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ >; }; }; -&omap3_pmx_core2 { +/* On board Wifi module */ +&mmc2 { pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_pins - >; - - hsusbb1_pins: pinmux_hsusbb1_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ - OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ - OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ - OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ - >; - }; - - leds_pins: pinmux_leds_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ - >; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - - /* - * Display monitor features are burnt in the EEPROM - * as EDID data. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; -}; - -&gpmc { - ranges = <0 0 0x00000000 0x20000000>, - <5 0 0x2c000000 0x01000000>; - - nand@0,0 { - linux,mtd-name= "micron,mt29c4g96maz"; - reg = <0 0 0>; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SPL"; - reg = <0 0x100000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x100000 0x180000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x280000 0x100000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x380000 0x300000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x680000 0x1f980000>; - }; - }; - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&smsc9221_pins>; - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - -&vpll2 { - /* Needed for DSS */ - regulator-name = "vdds_dsi"; -}; - -&dss { - status = "ok"; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; + pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; + vmmc-supply = <&lbee1usjyc_pdn>; + vmmc_aux-supply = <&lbee1usjyc_reset_n_w>; + bus-width = <4>; + non-removable; }; diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/omap3-igep0030-common.dtsi new file mode 100644 index 000000000000..0cb1527c39d4 --- /dev/null +++ b/arch/arm/boot/dts/omap3-igep0030-common.dtsi @@ -0,0 +1,60 @@ +/* + * Common Device Tree Source for IGEP COM MODULE + * + * Copyright (C) 2014 Javier Martinez Canillas + * Copyright (C) 2014 Enric Balletbo i Serra + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-igep.dtsi" + +/ { + leds: gpio_leds { + compatible = "gpio-leds"; + + user0 { + label = "omap3:red:user0"; + gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ + default-state = "off"; + }; + + user1 { + label = "omap3:green:user1"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */ + default-state = "off"; + }; + + user2 { + label = "omap3:red:user1"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */ + default-state = "off"; + }; + }; +}; + +&omap3_pmx_core { + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ + OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ + OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */ + OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ + >; + }; +}; + +&omap3_pmx_core2 { + leds_core2_pins: pinmux_leds_core2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts new file mode 100644 index 000000000000..9326b282c94a --- /dev/null +++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts @@ -0,0 +1,67 @@ +/* + * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x) + * + * Copyright (C) 2014 Javier Martinez Canillas + * Copyright (C) 2014 Enric Balletbo i Serra + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-igep0030-common.dtsi" + +/ { + model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)"; + compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3"; + + /* Regulator to trigger the WL_EN signal of the Wifi module */ + lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbep5clwmc-wlen"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ + enable-active-high; + }; +}; + +&omap3_pmx_core { + lbep5clwmc_pins: pinmux_lbep5clwmc_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ + >; + }; + + leds_pins: pinmux_leds_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ + >; + }; + +}; + +&i2c2 { + status = "disabled"; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins &leds_core2_pins>; + + boot { + label = "omap3:green:boot"; + gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; + vmmc-supply = <&lbep5clwmc_wlen>; + bus-width = <4>; + non-removable; +}; diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts index 2793749eb1ba..8150f47ccdf5 100644 --- a/arch/arm/boot/dts/omap3-igep0030.dts +++ b/arch/arm/boot/dts/omap3-igep0030.dts @@ -1,5 +1,5 @@ /* - * Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x) + * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x) * * Copyright (C) 2012 Javier Martinez Canillas * Copyright (C) 2012 Enric Balletbo i Serra @@ -9,97 +9,62 @@ * published by the Free Software Foundation. */ -#include "omap3-igep.dtsi" +#include "omap3-igep0030-common.dtsi" / { - model = "IGEP COM MODULE (TI OMAP AM/DM37x)"; + model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)"; compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3"; - leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - compatible = "gpio-leds"; - - boot { - label = "omap3:green:boot"; - gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user0 { - label = "omap3:red:user0"; - gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ - default-state = "off"; - }; - - user1 { - label = "omap3:green:user1"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */ - default-state = "off"; - }; + /* Regulator to trigger the WIFI_PDN signal of the Wifi module */ + lbee1usjyc_pdn: lbee1usjyc_pdn { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbee1usjyc-pdn"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 - WIFI_PDN */ + startup-delay-us = <10000>; + enable-active-high; + }; - user2 { - label = "omap3:red:user1"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; + /* Regulator to trigger the RESET_N_W signal of the Wifi module */ + lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbee1usjyc-reset-n-w"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - RESET_N_W */ + enable-active-high; }; }; -&omap3_pmx_core2 { - leds_pins: pinmux_leds_pins { +&omap3_pmx_core { + lbee1usjyc_pins: pinmux_lbee1usjyc_pins { pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ >; }; }; -&gpmc { - ranges = <0 0 0x00000000 0x20000000>; - - nand@0,0 { - linux,mtd-name= "micron,mt29c4g96maz"; - reg = <0 0 0>; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&leds_core2_pins>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SPL"; - reg = <0 0x100000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x100000 0x180000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x280000 0x100000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x380000 0x300000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x680000 0x1f980000>; - }; + boot { + label = "omap3:green:boot"; + gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */ + default-state = "on"; }; }; + +/* On board Wifi module */ +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; + vmmc-supply = <&lbee1usjyc_pdn>; + vmmc_aux-supply = <&lbee1usjyc_reset_n_w>; + bus-width = <4>; + non-removable; +}; + diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts index 72dca0b7904d..202f95a5a383 100644 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ b/arch/arm/boot/dts/omap3-ldp.dts @@ -101,8 +101,9 @@ nand@0,0 { linux,mtd-name= "micron,nand"; - reg = <0 0 0>; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; + gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; gpmc,sync-clk-ps = <0>; diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index d97308896f0c..e81fb651d5d0 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi @@ -363,7 +363,7 @@ <7 0 0x15000000 0x01000000>; nand@0,0 { - reg = <0 0 0x1000000>; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; ti,nand-ecc-opt = "bch8"; /* no elm on omap3 */ diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index bc82a12d4c2c..08ef71fe5273 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -142,6 +142,33 @@ >; }; + gpmc_pins: pinmux_gpmc_pins { + pinctrl-single,pins = < + + /* address lines */ + OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ + OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ + OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ + + /* data lines, gpmc_d0..d7 not muxable according to TRM */ + OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ + OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ + OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ + OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ + OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ + OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ + OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ + OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ + + /* + * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable + * according to TRM. OneNAND seems to require PIN_INPUT on clock. + */ + OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ + OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ + >; + }; + i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ @@ -585,16 +612,16 @@ }; &gpmc { - ranges = <0 0 0x04000000 0x10000000>; /* 256MB */ ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ + pinctrl-names = "default"; + pinctrl-0 = <&gpmc_pins>; - /* gpio-irq for dma: 65 */ - + /* sys_ndmareq1 could be used by the driver, not as gpio65 though */ onenand@0,0 { #address-cells = <1>; #size-cells = <1>; - reg = <0 0 0x10000000>; + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ gpmc,sync-read; gpmc,sync-write; diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index 70addcba37c5..1e49dfe7e212 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -115,12 +115,12 @@ }; &gpmc { - ranges = <0 0 0x04000000 0x20000000>; + ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ onenand@0,0 { #address-cells = <1>; #size-cells = <1>; - reg = <0 0 0x20000000>; + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ gpmc,sync-read; gpmc,sync-write; diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi index d59e3de1441e..b1cb5774f49a 100644 --- a/arch/arm/boot/dts/omap3-sb-t35.dtsi +++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi @@ -2,6 +2,49 @@ * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 */ +/ { + tfp410: encoder@0 { + compatible = "ti,tfp410"; + + powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ + + pinctrl-names = "default"; + pinctrl-0 = <&tfp410_pins>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint@0 { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint@0 { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector@0 { + compatible = "dvi-connector"; + label = "dvi"; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; +}; + &omap3_pmx_core { smsc2_pins: pinmux_smsc2_pins { pinctrl-single,pins = < @@ -9,6 +52,12 @@ OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ >; }; + + tfp410_pins: pinmux_tfp410_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ + >; + }; }; &gpmc { @@ -22,24 +71,29 @@ interrupts = <1 IRQ_TYPE_LEVEL_LOW>; reg = <4 0 0xff>; bank-width = <2>; - gpmc,mux-add-data; - gpmc,cs-on-ns = <1>; - gpmc,cs-rd-off-ns = <180>; - gpmc,cs-wr-off-ns = <180>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <144>; - gpmc,page-burst-access-ns = <24>; - gpmc,bus-turnaround-ns = <90>; - gpmc,cycle2cycle-delay-ns = <90>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; + gpmc,device-width = <1>; + gpmc,cycle2cycle-samecsen = <1>; + gpmc,cycle2cycle-diffcsen = <1>; + gpmc,cs-on-ns = <5>; + gpmc,cs-rd-off-ns = <150>; + gpmc,cs-wr-off-ns = <150>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <15>; + gpmc,adv-wr-off-ns = <40>; + gpmc,oe-on-ns = <45>; + gpmc,oe-off-ns = <140>; + gpmc,we-on-ns = <45>; + gpmc,we-off-ns = <140>; + gpmc,rd-cycle-ns = <155>; + gpmc,wr-cycle-ns = <155>; + gpmc,access-ns = <120>; + gpmc,page-burst-access-ns = <20>; + gpmc,bus-turnaround-ns = <75>; + gpmc,cycle2cycle-delay-ns = <75>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,wr-access-ns = <0>; vddvario-supply = <&vddvario>; vdd33a-supply = <&vdd33a>; reg-io-width = <4>; diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts index 42189b65d393..4ec5d8684122 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3517.dts +++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts @@ -9,6 +9,10 @@ model = "CompuLab SBC-T3517 with CM-T3517"; compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; + aliases { + display0 = &dvi0; + }; + /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */ vddvario: regulator-vddvario-sb-t35 { compatible = "regulator-fixed"; @@ -54,3 +58,13 @@ wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ }; + +&dss { + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts index bbbeea6b1988..8dfc1df8cc17 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3530.dts +++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts @@ -8,6 +8,10 @@ / { model = "CompuLab SBC-T3530 with CM-T3530"; compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; + + aliases { + display0 = &dvi0; + }; }; &omap3_pmx_core { @@ -34,3 +38,13 @@ &mmc1 { cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; }; + +&dss { + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts index 08e4a7086f22..6b69864bd6ce 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3730.dts +++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts @@ -8,6 +8,10 @@ / { model = "CompuLab SBC-T3730 with CM-T3730"; compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; + + aliases { + display0 = &dvi0; + }; }; &omap3_pmx_core { @@ -25,3 +29,13 @@ ranges = <5 0 0x2c000000 0x01000000>, <4 0 0x2d000000 0x01000000>; }; + +&dss { + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi index b30f387d3a83..e89820a6776e 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -270,7 +270,7 @@ ranges = <0 0 0x00000000 0x01000000>; nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ ti,nand-ecc-opt = "sw"; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index d0e884d3a737..8db7def81c28 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -332,6 +332,7 @@ ti,hwmods = "mailbox"; reg = <0x48094000 0x200>; interrupts = <26>; + #mbox-cells = <1>; ti,mbox-num-users = <2>; ti,mbox-num-fifos = <2>; mbox_dsp: dsp { diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts index 9bad94efe1c8..16b0cdfbee9c 100644 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ b/arch/arm/boot/dts/omap3430-sdp.dts @@ -51,8 +51,8 @@ &gpmc { ranges = <0 0 0x10000000 0x08000000>, - <1 0 0x28000000 0x08000000>, - <2 0 0x20000000 0x10000000>; + <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */ + <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */ nor@0,0 { compatible = "cfi-flash"; @@ -106,7 +106,7 @@ linux,mtd-name= "micron,mt29f1g08abb"; #address-cells = <1>; #size-cells = <1>; - reg = <1 0 0x08000000>; + reg = <1 0 4>; /* CS1, offset 0, IO size 4 */ ti,nand-ecc-opt = "sw"; nand-bus-width = <8>; gpmc,cs-on-ns = <0>; @@ -150,7 +150,7 @@ linux,mtd-name= "samsung,kfm2g16q2m-deb8"; #address-cells = <1>; #size-cells = <1>; - reg = <2 0 0x10000000>; + reg = <2 0 0x20000>; /* CS2, offset 0, IO size 4 */ gpmc,device-width = <2>; gpmc,mux-add-data = <2>; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 878c979203d0..a46eab82d2da 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -661,6 +661,7 @@ reg = <0x4a0f4000 0x200>; interrupts = ; ti,hwmods = "mailbox"; + #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; mbox_ipu: mbox_ipu { diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 256b7f69e45b..b321fdf42c9f 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -651,6 +651,7 @@ reg = <0x4a0f4000 0x200>; interrupts = ; ti,hwmods = "mailbox"; + #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; mbox_ipu: mbox_ipu { diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index a3ed23c0a8f5..1518c5bcca33 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -21,7 +21,8 @@ }; chosen { - bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scif2; }; memory { diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 801a556e264b..277e73c110e5 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -52,16 +52,6 @@ clock-output-names = "usb_x1"; }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@fcfe0000 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-cpg-clocks", - "renesas,rz-cpg-clocks"; - reg = <0xfcfe0000 0x18>; - clocks = <&extal_clk>, <&usb_x1_clk>; - clock-output-names = "pll", "i", "g"; - }; - /* Fixed factor clocks */ b_clk: b_clk { #clock-cells = <0>; @@ -88,6 +78,16 @@ clock-output-names = "p0"; }; + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@fcfe0000 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-cpg-clocks", + "renesas,rz-cpg-clocks"; + reg = <0xfcfe0000 0x18>; + clocks = <&extal_clk>, <&usb_x1_clk>; + clock-output-names = "pll", "i", "g"; + }; + /* MSTP clocks */ mstp3_clks: mstp3_clks@fcfe0420 { #clock-cells = <1>; @@ -148,97 +148,6 @@ }; }; - gic: interrupt-controller@e8201000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0xe8201000 0x1000>, - <0xe8202000 0x1000>; - }; - - i2c0: i2c@fcfee000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee000 0x44>; - interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>, - <0 158 IRQ_TYPE_EDGE_RISING>, - <0 159 IRQ_TYPE_EDGE_RISING>, - <0 160 IRQ_TYPE_LEVEL_HIGH>, - <0 161 IRQ_TYPE_LEVEL_HIGH>, - <0 162 IRQ_TYPE_LEVEL_HIGH>, - <0 163 IRQ_TYPE_LEVEL_HIGH>, - <0 164 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R7S72100_CLK_I2C0>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c1: i2c@fcfee400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee400 0x44>; - interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>, - <0 166 IRQ_TYPE_EDGE_RISING>, - <0 167 IRQ_TYPE_EDGE_RISING>, - <0 168 IRQ_TYPE_LEVEL_HIGH>, - <0 169 IRQ_TYPE_LEVEL_HIGH>, - <0 170 IRQ_TYPE_LEVEL_HIGH>, - <0 171 IRQ_TYPE_LEVEL_HIGH>, - <0 172 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R7S72100_CLK_I2C1>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c2: i2c@fcfee800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee800 0x44>; - interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>, - <0 174 IRQ_TYPE_EDGE_RISING>, - <0 175 IRQ_TYPE_EDGE_RISING>, - <0 176 IRQ_TYPE_LEVEL_HIGH>, - <0 177 IRQ_TYPE_LEVEL_HIGH>, - <0 178 IRQ_TYPE_LEVEL_HIGH>, - <0 179 IRQ_TYPE_LEVEL_HIGH>, - <0 180 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R7S72100_CLK_I2C2>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c3: i2c@fcfeec00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfeec00 0x44>; - interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>, - <0 182 IRQ_TYPE_EDGE_RISING>, - <0 183 IRQ_TYPE_EDGE_RISING>, - <0 184 IRQ_TYPE_LEVEL_HIGH>, - <0 185 IRQ_TYPE_LEVEL_HIGH>, - <0 186 IRQ_TYPE_LEVEL_HIGH>, - <0 187 IRQ_TYPE_LEVEL_HIGH>, - <0 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R7S72100_CLK_I2C3>; - clock-frequency = <100000>; - status = "disabled"; - }; - - mtu2: timer@fcff0000 { - compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; - reg = <0xfcff0000 0x400>; - interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tgi0a"; - clocks = <&mstp3_clks R7S72100_CLK_MTU2>; - clock-names = "fck"; - status = "disabled"; - }; - scif0: serial@e8007000 { compatible = "renesas,scif-r7s72100", "renesas,scif"; reg = <0xe8007000 64>; @@ -404,4 +313,95 @@ #size-cells = <0>; status = "disabled"; }; + + gic: interrupt-controller@e8201000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe8201000 0x1000>, + <0xe8202000 0x1000>; + }; + + i2c0: i2c@fcfee000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee000 0x44>; + interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>, + <0 158 IRQ_TYPE_EDGE_RISING>, + <0 159 IRQ_TYPE_EDGE_RISING>, + <0 160 IRQ_TYPE_LEVEL_HIGH>, + <0 161 IRQ_TYPE_LEVEL_HIGH>, + <0 162 IRQ_TYPE_LEVEL_HIGH>, + <0 163 IRQ_TYPE_LEVEL_HIGH>, + <0 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@fcfee400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee400 0x44>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>, + <0 166 IRQ_TYPE_EDGE_RISING>, + <0 167 IRQ_TYPE_EDGE_RISING>, + <0 168 IRQ_TYPE_LEVEL_HIGH>, + <0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 172 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C1>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@fcfee800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee800 0x44>; + interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>, + <0 174 IRQ_TYPE_EDGE_RISING>, + <0 175 IRQ_TYPE_EDGE_RISING>, + <0 176 IRQ_TYPE_LEVEL_HIGH>, + <0 177 IRQ_TYPE_LEVEL_HIGH>, + <0 178 IRQ_TYPE_LEVEL_HIGH>, + <0 179 IRQ_TYPE_LEVEL_HIGH>, + <0 180 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C2>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@fcfeec00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfeec00 0x44>; + interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>, + <0 182 IRQ_TYPE_EDGE_RISING>, + <0 183 IRQ_TYPE_EDGE_RISING>, + <0 184 IRQ_TYPE_LEVEL_HIGH>, + <0 185 IRQ_TYPE_LEVEL_HIGH>, + <0 186 IRQ_TYPE_LEVEL_HIGH>, + <0 187 IRQ_TYPE_LEVEL_HIGH>, + <0 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C3>; + clock-frequency = <100000>; + status = "disabled"; + }; + + mtu2: timer@fcff0000 { + compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; + reg = <0xfcff0000 0x400>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tgi0a"; + clocks = <&mstp3_clks R7S72100_CLK_MTU2>; + clock-names = "fck"; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts index a860f32bca27..84e05f713c54 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts @@ -21,7 +21,8 @@ }; chosen { - bootargs = "console=ttySC0,115200 ignore_loglevel rw"; + bootargs = "ignore_loglevel rw"; + stdout-path = &scifa0; }; memory@40000000 { @@ -93,6 +94,10 @@ voltage-tolerance = <1>; /* 1% */ }; +&cmt1 { + status = "okay"; +}; + &pfc { scifa0_pins: serial0 { renesas,groups = "scifa0_data"; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index ef152e384822..7f57dc7f392a 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -30,18 +30,6 @@ }; }; - gic: interrupt-controller@f1001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x1000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - timer { compatible = "arm,armv7-timer"; interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -50,6 +38,91 @@ <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + dmac: dma-multiplexer { + compatible = "renesas,shdma-mux"; + #dma-cells = <1>; + dma-channels = <20>; + dma-requests = <256>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dma0: dma-controller@e6700020 { + compatible = "renesas,shdma-r8a73a4"; + reg = <0 0xe6700020 0 0x89e0>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH + 0 200 IRQ_TYPE_LEVEL_HIGH + 0 201 IRQ_TYPE_LEVEL_HIGH + 0 202 IRQ_TYPE_LEVEL_HIGH + 0 203 IRQ_TYPE_LEVEL_HIGH + 0 204 IRQ_TYPE_LEVEL_HIGH + 0 205 IRQ_TYPE_LEVEL_HIGH + 0 206 IRQ_TYPE_LEVEL_HIGH + 0 207 IRQ_TYPE_LEVEL_HIGH + 0 208 IRQ_TYPE_LEVEL_HIGH + 0 209 IRQ_TYPE_LEVEL_HIGH + 0 210 IRQ_TYPE_LEVEL_HIGH + 0 211 IRQ_TYPE_LEVEL_HIGH + 0 212 IRQ_TYPE_LEVEL_HIGH + 0 213 IRQ_TYPE_LEVEL_HIGH + 0 214 IRQ_TYPE_LEVEL_HIGH + 0 215 IRQ_TYPE_LEVEL_HIGH + 0 216 IRQ_TYPE_LEVEL_HIGH + 0 217 IRQ_TYPE_LEVEL_HIGH + 0 218 IRQ_TYPE_LEVEL_HIGH + 0 219 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19"; + }; + }; + + pfc: pfc@e6050000 { + compatible = "renesas,pfc-r8a73a4"; + reg = <0 0xe6050000 0 0x9000>; + gpio-controller; + #gpio-cells = <2>; + interrupts-extended = + <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, + <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, + <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, + <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, + <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, + <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, + <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, + <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, + <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, + <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, + <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, + <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, + <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, + <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, + <&irqc1 24 0>, <&irqc1 25 0>; + }; + + i2c5: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x428>; + interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; + + renesas,channels-mask = <0xff>; + + status = "disabled"; + }; + irqc0: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; #interrupt-cells = <2>; @@ -122,48 +195,6 @@ <0 57 IRQ_TYPE_LEVEL_HIGH>; }; - dmac: dma-multiplexer@0 { - compatible = "renesas,shdma-mux"; - #dma-cells = <1>; - dma-channels = <20>; - dma-requests = <256>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dma0: dma-controller@e6700020 { - compatible = "renesas,shdma-r8a73a4"; - reg = <0 0xe6700020 0 0x89e0>; - interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH - 0 200 IRQ_TYPE_LEVEL_HIGH - 0 201 IRQ_TYPE_LEVEL_HIGH - 0 202 IRQ_TYPE_LEVEL_HIGH - 0 203 IRQ_TYPE_LEVEL_HIGH - 0 204 IRQ_TYPE_LEVEL_HIGH - 0 205 IRQ_TYPE_LEVEL_HIGH - 0 206 IRQ_TYPE_LEVEL_HIGH - 0 207 IRQ_TYPE_LEVEL_HIGH - 0 208 IRQ_TYPE_LEVEL_HIGH - 0 209 IRQ_TYPE_LEVEL_HIGH - 0 210 IRQ_TYPE_LEVEL_HIGH - 0 211 IRQ_TYPE_LEVEL_HIGH - 0 212 IRQ_TYPE_LEVEL_HIGH - 0 213 IRQ_TYPE_LEVEL_HIGH - 0 214 IRQ_TYPE_LEVEL_HIGH - 0 215 IRQ_TYPE_LEVEL_HIGH - 0 216 IRQ_TYPE_LEVEL_HIGH - 0 217 IRQ_TYPE_LEVEL_HIGH - 0 218 IRQ_TYPE_LEVEL_HIGH - 0 219 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19"; - }; - }; - thermal@e61f0000 { compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, @@ -216,15 +247,6 @@ status = "disabled"; }; - i2c5: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x428>; - interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - i2c6: i2c@e6550000 { #address-cells = <1>; #size-cells = <0>; @@ -252,6 +274,20 @@ status = "disabled"; }; + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; reg = <0 0xe6c40000 0 0x100>; @@ -266,73 +302,20 @@ status = "disabled"; }; - scifb2: serial@e6c20000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - scifb3: serial@e6c30000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - scifb4: serial@e6ce0000 { + scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - scifb5: serial@e6cf0000 { + scifb3: serial@e6cf0000 { compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6cf0000 0 0x100>; interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - mmcif0: mmc@ee200000 { - compatible = "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <4>; - status = "disabled"; - }; - - mmcif1: mmc@ee220000 { - compatible = "renesas,sh-mmcif"; - reg = <0 0xee220000 0 0x80>; - interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <4>; - status = "disabled"; - }; - - pfc: pfc@e6050000 { - compatible = "renesas,pfc-r8a73a4"; - reg = <0 0xe6050000 0 0x9000>; - gpio-controller; - #gpio-cells = <2>; - interrupts-extended = - <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, - <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, - <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, - <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, - <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, - <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, - <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, - <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, - <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, - <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, - <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, - <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, - <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, - <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, - <&irqc1 24 0>, <&irqc1 25 0>; - }; - sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee100000 0 0x100>; @@ -356,4 +339,32 @@ cap-sd-highspeed; status = "disabled"; }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + status = "disabled"; + }; + + mmcif1: mmc@ee220000 { + compatible = "renesas,sh-mmcif"; + reg = <0 0xee220000 0 0x80>; + interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; }; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index effb7b46f131..d4af4d86c6b0 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; + stdout-path = &scifa1; }; memory { @@ -77,7 +78,7 @@ regulator-boot-on; }; - gpio-keys { + keyboard { compatible = "gpio-keys"; power-key { @@ -298,3 +299,7 @@ status = "okay"; }; + +&tmu0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index d46c213a17ad..aec8da89ef9a 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -71,6 +71,7 @@ 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; }; /* irqpin1: IRQ8 - IRQ15 */ @@ -91,6 +92,7 @@ 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; }; /* irqpin2: IRQ16 - IRQ23 */ @@ -111,6 +113,7 @@ 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; }; /* irqpin3: IRQ24 - IRQ31 */ @@ -131,6 +134,7 @@ 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; }; ether: ethernet@e9a00000 { @@ -193,7 +197,7 @@ compatible = "renesas,scifa-r8a7740", "renesas,scifa"; reg = <0xe6c60000 0x100>; interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; clock-names = "sci_ick"; status = "disabled"; }; @@ -331,6 +335,34 @@ status = "disabled"; }; + tmu0: timer@fff80000 { + compatible = "renesas,tmu-r8a7740", "renesas,tmu"; + reg = <0xfff80000 0x2c>; + interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, + <0 199 IRQ_TYPE_LEVEL_HIGH>, + <0 200 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7740_CLK_TMU0>; + clock-names = "fck"; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu1: timer@fff90000 { + compatible = "renesas,tmu-r8a7740", "renesas,tmu"; + reg = <0xfff90000 0x2c>; + interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 172 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7740_CLK_TMU1>; + clock-names = "fck"; + + #renesas,channels = <3>; + + status = "disabled"; + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -448,8 +480,8 @@ mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0xe6150138 4>, <0xe6150040 4>; - clocks = <&sub_clk>, <&sub_clk>, - <&cpg_clocks R8A7740_CLK_HP>, + clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, + <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, <&cpg_clocks R8A7740_CLK_HP>, <&cpg_clocks R8A7740_CLK_HP>, <&cpg_clocks R8A7740_CLK_HP>, @@ -458,7 +490,8 @@ <&sub_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7 + R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA + R8A7740_CLK_SCIFA7 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB @@ -467,7 +500,8 @@ R8A7740_CLK_SCIFA4 >; clock-output-names = - "scifa6", "scifa7", "dmac1", "dmac2", "dmac3", + "scifa6", "intca", + "scifa7", "dmac1", "dmac2", "dmac3", "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", "scifa2", "scifa3", "scifa4"; }; diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 3342c74c5de8..04c0c37bb784 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -28,7 +28,8 @@ }; chosen { - bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; + bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw"; + stdout-path = &scif0; }; memory { @@ -73,6 +74,10 @@ status = "okay"; }; +&tmu0 { + status = "okay"; +}; + &pfc { scif0_pins: serial0 { renesas,groups = "scif0_data_a", "scif0_ctrl"; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 315ec62cb96b..ef8533910029 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -162,6 +162,42 @@ status = "disabled"; }; + tmu0: timer@ffd80000 { + compatible = "renesas,tmu-r8a7778", "renesas,tmu"; + reg = <0xffd80000 0x30>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, + <0 33 IRQ_TYPE_LEVEL_HIGH>, + <0 34 IRQ_TYPE_LEVEL_HIGH>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu1: timer@ffd81000 { + compatible = "renesas,tmu-r8a7778", "renesas,tmu"; + reg = <0xffd81000 0x30>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, + <0 37 IRQ_TYPE_LEVEL_HIGH>, + <0 38 IRQ_TYPE_LEVEL_HIGH>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu2: timer@ffd82000 { + compatible = "renesas,tmu-r8a7778", "renesas,tmu"; + reg = <0xffd82000 0x30>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, + <0 41 IRQ_TYPE_LEVEL_HIGH>, + <0 42 IRQ_TYPE_LEVEL_HIGH>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + scif0: serial@ffe40000 { compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe40000 0x100>; @@ -215,8 +251,6 @@ compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4c000 0x100>; interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; @@ -224,8 +258,6 @@ compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4d000 0x100>; interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; @@ -233,8 +265,6 @@ compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4f000 0x100>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index c160404e4d40..e83d40e24bcd 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=ttySC2,115200 ignore_loglevel root=/dev/nfs ip=on"; + stdout-path = &scif2; }; memory { @@ -68,6 +69,78 @@ gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; }; }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + vga_enc_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + port@1 { + reg = <1>; + vga_enc_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&vga_enc_out>; + }; + }; + }; + + lvds-encoder { + compatible = "thine,thc63lvdm83d"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_enc_in: endpoint { + remote-endpoint = <&du_out_rgb1>; + }; + }; + port@1 { + reg = <1>; + lvds_connector: endpoint { + }; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&vga_enc_in>; + }; + }; + port@1 { + endpoint { + remote-endpoint = <&lvds_enc_in>; + }; + }; + }; }; &irqpin0 { @@ -83,6 +156,17 @@ }; &pfc { + du_pins: du { + du0 { + renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0"; + renesas,function = "du0"; + }; + du1 { + renesas,groups = "du1_rgb666", "du1_sync_1", "du1_clk_out"; + renesas,function = "du1"; + }; + }; + lan0_pins: lan0 { intc { renesas,groups = "intc_irq1_b"; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 7cfba9aa1b41..ede9a29e4bc6 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -303,7 +303,7 @@ }; sata: sata@fc600000 { - compatible = "renesas,rcar-sata"; + compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; reg = <0xfc600000 0x2000>; interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7779_CLK_SATA>; @@ -314,8 +314,6 @@ reg = <0xffe4c000 0x100>; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; @@ -324,8 +322,6 @@ reg = <0xffe4d000 0x100>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; @@ -334,8 +330,6 @@ reg = <0xffe4e000 0x100>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; @@ -344,8 +338,6 @@ reg = <0xffe4f000 0x100>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; @@ -379,6 +371,30 @@ status = "disabled"; }; + du: display@fff80000 { + compatible = "renesas,du-r8a7779"; + reg = <0 0xfff80000 0 0x40000>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7779_CLK_DU>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + clocks { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 69098b906b39..bd470bafdb99 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -19,12 +19,13 @@ compatible = "renesas,lager", "renesas,r8a7790"; aliases { - serial6 = &scif0; - serial7 = &scif1; + serial6 = &scifa0; + serial7 = &scifa1; }; chosen { bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scifa0; }; memory@40000000 { @@ -42,7 +43,7 @@ #size-cells = <1>; }; - gpio_keys { + keyboard { compatible = "gpio-keys"; button@1 { @@ -144,6 +145,56 @@ states = <3300000 1 1800000 0>; }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + port@2 { + lvds_connector: endpoint { + }; + }; + }; }; &extal_clk { @@ -151,17 +202,14 @@ }; &pfc { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - du_pins: du { renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; renesas,function = "du"; }; - scif0_pins: serial0 { - renesas,groups = "scif0_data"; - renesas,function = "scif0"; + scifa0_pins: serial0 { + renesas,groups = "scifa0_data"; + renesas,function = "scifa0"; }; ether_pins: ether { @@ -174,9 +222,9 @@ renesas,function = "intc"; }; - scif1_pins: serial1 { - renesas,groups = "scif1_data"; - renesas,function = "scif1"; + scifa1_pins: serial1 { + renesas,groups = "scifa1_data"; + renesas,function = "scifa1"; }; sdhi0_pins: sd0 { @@ -220,6 +268,11 @@ renesas,function = "iic3"; }; + hsusb_pins: hsusb { + renesas,groups = "usb0_ovc_vbus"; + renesas,function = "usb0"; + }; + usb0_pins: usb0 { renesas,groups = "usb0"; renesas,function = "usb0"; @@ -308,15 +361,15 @@ }; }; -&scif0 { - pinctrl-0 = <&scif0_pins>; +&scifa0 { + pinctrl-0 = <&scifa0_pins>; pinctrl-names = "default"; status = "okay"; }; -&scif1 { - pinctrl-0 = <&scif1_pins>; +&scifa1 { + pinctrl-0 = <&scifa1_pins>; pinctrl-names = "default"; status = "okay"; @@ -418,12 +471,29 @@ pinctrl-names = "default"; }; +&xhci { + status = "okay"; + pinctrl-0 = <&usb2_pins>; + pinctrl-names = "default"; +}; + &pci2 { status = "okay"; pinctrl-0 = <&usb2_pins>; pinctrl-names = "default"; }; +&hsusb { + status = "okay"; + pinctrl-0 = <&hsusb_pins>; + pinctrl-names = "default"; + renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>; +}; + +&usbphy { + status = "okay"; +}; + /* composite video input */ &vin1 { pinctrl-0 = <&vin1_pins>; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index d0e17733dc1a..69b7cd0e7fb3 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -392,11 +392,13 @@ status = "disabled"; }; - mmcif0: mmcif@ee200000 { + mmcif0: mmc@ee200000 { compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; + dma-names = "tx", "rx"; reg-io-width = <4>; status = "disabled"; }; @@ -406,6 +408,8 @@ reg = <0 0xee220000 0 0x80>; interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>; + dma-names = "tx", "rx"; reg-io-width = <4>; status = "disabled"; }; @@ -420,7 +424,6 @@ reg = <0 0xee100000 0 0x200>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; - cap-sd-highspeed; status = "disabled"; }; @@ -429,7 +432,6 @@ reg = <0 0xee120000 0 0x200>; interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; - cap-sd-highspeed; status = "disabled"; }; @@ -438,7 +440,6 @@ reg = <0 0xee140000 0 0x100>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; - cap-sd-highspeed; status = "disabled"; }; @@ -447,7 +448,6 @@ reg = <0 0xee160000 0 0x100>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; - cap-sd-highspeed; status = "disabled"; }; @@ -568,6 +568,36 @@ status = "disabled"; }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7790"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7790"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; + clock-names = "usbhs"; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + vin0: video@e6ef0000 { compatible = "renesas,vin-r8a7790"; clocks = <&mstp8_clks R8A7790_CLK_VIN0>; @@ -600,6 +630,96 @@ status = "disabled"; }; + vsp1@fe920000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; + + renesas,has-sru; + renesas,#rpf = <5>; + renesas,#uds = <1>; + renesas,#wpf = <4>; + }; + + vsp1@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; + + renesas,has-lut; + renesas,has-sru; + renesas,#rpf = <5>; + renesas,#uds = <3>; + renesas,#wpf = <4>; + }; + + vsp1@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; + + renesas,has-lif; + renesas,has-lut; + renesas,#rpf = <4>; + renesas,#uds = <1>; + renesas,#wpf = <4>; + }; + + vsp1@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; + + renesas,has-lif; + renesas,has-lut; + renesas,#rpf = <4>; + renesas,#uds = <1>; + renesas,#wpf = <4>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7790"; + reg = <0 0xfeb00000 0 0x70000>, + <0 0xfeb90000 0 0x1c>, + <0 0xfeb94000 0 0x1c>; + reg-names = "du", "lvds.0", "lvds.1"; + interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, + <0 268 IRQ_TYPE_LEVEL_HIGH>, + <0 269 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7790_CLK_DU0>, + <&mstp7_clks R8A7790_CLK_DU1>, + <&mstp7_clks R8A7790_CLK_DU2>, + <&mstp7_clks R8A7790_CLK_LVDS0>, + <&mstp7_clks R8A7790_CLK_LVDS1>; + clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + }; + }; + port@2 { + reg = <2>; + du_out_lvds1: endpoint { + }; + }; + }; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -868,18 +988,25 @@ mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, - <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, - <&zs_clk>; + clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>, + <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>, + <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, + <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 - R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 - R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S + R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 + R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 + R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC + R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0 + R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 + R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0 + R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S >; clock-output-names = - "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", - "vsp1-du0", "vsp1-rt", "vsp1-sy"; + "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1", + "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1", + "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0", + "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy"; }; mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -1070,6 +1197,16 @@ status = "disabled"; }; + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7790"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + pci0: pci@ee090000 { compatible = "renesas,pci-r8a7790"; device_type = "pci"; @@ -1088,6 +1225,20 @@ interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@0,1 { + reg = <0x800 0 0 0 0>; + device_type = "pci"; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@0,2 { + reg = <0x1000 0 0 0 0>; + device_type = "pci"; + phys = <&usb0 0>; + phy-names = "usb"; + }; }; pci1: pci@ee0b0000 { @@ -1128,6 +1279,20 @@ interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@0,1 { + reg = <0x800 0 0 0 0>; + device_type = "pci"; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@0,2 { + reg = <0x1000 0 0 0 0>; + device_type = "pci"; + phys = <&usb2 0>; + phy-names = "usb"; + }; }; pciec: pcie@fe000000 { @@ -1155,7 +1320,7 @@ status = "disabled"; }; - rcar_sound: rcar_sound@0xec500000 { + rcar_sound: rcar_sound@ec500000 { #sound-dai-cells = <1>; compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; reg = <0 0xec500000 0 0x1000>, /* SCU */ diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts index f1b56de10205..740e38678032 100644 --- a/arch/arm/boot/dts/r8a7791-henninger.dts +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -23,6 +23,7 @@ chosen { bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scif0; }; memory@40000000 { @@ -271,6 +272,17 @@ pinctrl-names = "default"; }; +&hsusb { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>; +}; + +&usbphy { + status = "okay"; +}; + &pcie_bus_clk { status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 07550e775e80..0d0cde7e2c41 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -26,6 +26,7 @@ chosen { bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scif0; }; memory@40000000 { @@ -43,7 +44,7 @@ #size-cells = <1>; }; - gpio-keys { + keyboard { compatible = "gpio-keys"; key-1 { @@ -211,14 +212,24 @@ }; }; +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@1 { + lvds_connector: endpoint { + }; + }; + }; +}; + &extal_clk { clock-frequency = <20000000>; }; &pfc { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - i2c2_pins: i2c2 { renesas,groups = "i2c2"; renesas,function = "i2c2"; @@ -463,6 +474,17 @@ pinctrl-names = "default"; }; +&hsusb { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>; +}; + +&usbphy { + status = "okay"; +}; + &pcie_bus_clk { status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index e06c11fa8698..9a57215f54f7 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for the r8a7791 SoC * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded Inc. * @@ -400,6 +400,17 @@ #gpio-range-cells = <3>; }; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; + dma-names = "tx", "rx"; + reg-io-width = <4>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7791"; reg = <0 0xee100000 0 0x200>; @@ -613,6 +624,36 @@ status = "disabled"; }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7791"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7791"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; + clock-names = "usbhs"; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + vin0: video@e6ef0000 { compatible = "renesas,vin-r8a7791"; clocks = <&mstp8_clks R8A7791_CLK_VIN0>; @@ -637,6 +678,75 @@ status = "disabled"; }; + vsp1@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; + + renesas,has-lut; + renesas,has-sru; + renesas,#rpf = <5>; + renesas,#uds = <3>; + renesas,#wpf = <4>; + }; + + vsp1@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; + + renesas,has-lif; + renesas,has-lut; + renesas,#rpf = <4>; + renesas,#uds = <1>; + renesas,#wpf = <4>; + }; + + vsp1@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; + + renesas,has-lif; + renesas,has-lut; + renesas,#rpf = <4>; + renesas,#uds = <1>; + renesas,#wpf = <4>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7791"; + reg = <0 0xfeb00000 0 0x40000>, + <0 0xfeb90000 0 0x1c>; + reg-names = "du", "lvds.0"; + interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, + <0 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_DU0>, + <&mstp7_clks R8A7791_CLK_DU1>, + <&mstp7_clks R8A7791_CLK_LVDS0>; + clock-names = "du.0", "du.1", "lvds.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + }; + }; + }; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -889,17 +999,23 @@ mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, - <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; + clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>, + <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, + <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, + <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 - R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 - R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S + R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU + R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG + R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 + R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 + R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 + R8A7791_CLK_VSP1_S >; clock-output-names = - "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", - "vsp1-du0", "vsp1-sy"; + "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg", + "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0", + "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; }; mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -1088,6 +1204,16 @@ status = "disabled"; }; + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7791"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + pci0: pci@ee090000 { compatible = "renesas,pci-r8a7791"; device_type = "pci"; @@ -1106,6 +1232,20 @@ interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@0,1 { + reg = <0x800 0 0 0 0>; + device_type = "pci"; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@0,2 { + reg = <0x1000 0 0 0 0>; + device_type = "pci"; + phys = <&usb0 0>; + phy-names = "usb"; + }; }; pci1: pci@ee0d0000 { @@ -1126,6 +1266,20 @@ interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@0,1 { + reg = <0x800 0 0 0 0>; + device_type = "pci"; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@0,2 { + reg = <0x1000 0 0 0 0>; + device_type = "pci"; + phys = <&usb2 0>; + phy-names = "usb"; + }; }; pciec: pcie@fe000000 { @@ -1153,7 +1307,7 @@ status = "disabled"; }; - rcar_sound: rcar_sound@0xec500000 { + rcar_sound: rcar_sound@ec500000 { #sound-dai-cells = <1>; compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; reg = <0 0xec500000 0 0x1000>, /* SCU */ diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 79d06ef017a0..f2cf7576bf3f 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -20,7 +20,8 @@ }; chosen { - bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scif2; }; memory@40000000 { diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index d4e8bce1e0b7..088e79c6551c 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -82,6 +82,14 @@ status = "disabled"; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + irqc0: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a7794", "renesas,irqc"; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi new file mode 100644 index 000000000000..65cb50f0c29f --- /dev/null +++ b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi @@ -0,0 +1,41 @@ +/* + * Common file for the AA104XD12 panel connected to Renesas R-Car boards + * + * Copyright (C) 2014 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/ { + panel { + compatible = "mitsubishi,aa104xd12", "panel-dpi"; + + width-mm = <210>; + height-mm = <158>; + + panel-timing { + /* 1024x768 @65Hz */ + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hsync-len = <136>; + hfront-porch = <20>; + hback-porch = <160>; + vfront-porch = <3>; + vback-porch = <29>; + vsync-len = <6>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_connector>; + }; + }; + }; +}; + +&lvds_connector { + remote-endpoint = <&panel_in>; +}; diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index d5344510c676..baf21ac6ce7f 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -60,6 +60,10 @@ }; }; +&cpu0 { + cpu0-supply = <&vdd_arm>; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index ad9c2db59670..0e99470db772 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -26,11 +26,21 @@ #size-cells = <0>; enable-method = "rockchip,rk3066-smp"; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; + operating-points = < + /* kHz uV */ + 1008000 1075000 + 816000 1025000 + 600000 1025000 + 504000 1000000 + 312000 975000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@1 { device_type = "cpu"; @@ -53,6 +63,51 @@ }; }; + i2s0: i2s@10118000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x10118000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + dmas = <&dmac1_s 4>, <&dmac1_s 5>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + status = "disabled"; + }; + + i2s1: i2s@1011a000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>; + status = "disabled"; + }; + + i2s2: i2s@1011c000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011c000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + dmas = <&dmac1_s 9>, <&dmac1_s 10>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>; + status = "disabled"; + }; + cru: clock-controller@20000000 { compatible = "rockchip,rk3066a-cru"; reg = <0x20000000 0x1000>; @@ -405,6 +460,42 @@ ; }; }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = , + , + , + , + , + , + , + , + ; + }; + }; + + i2s1 { + i2s1_bus: i2s1-bus { + rockchip,pins = , + , + , + , + , + ; + }; + }; + + i2s2 { + i2s2_bus: i2s2-bus { + rockchip,pins = , + , + , + , + , + ; + }; + }; }; }; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 15910c9ddbc7..0950a0524947 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -118,6 +118,10 @@ }; }; +&cpu0 { + cpu0-supply = <&vdd_arm>; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -159,7 +163,7 @@ vdd_arm: REG3 { regulator-name = "VDD_ARM"; regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; regulator-always-on; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ddaada788b45..b24e04f6ccc7 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -26,11 +26,24 @@ #size-cells = <0>; enable-method = "rockchip,rk3066-smp"; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; + operating-points = < + /* kHz uV */ + 1608000 1350000 + 1416000 1250000 + 1200000 1150000 + 1008000 1075000 + 816000 975000 + 600000 950000 + 504000 925000 + 312000 875000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@1 { device_type = "cpu"; @@ -65,6 +78,21 @@ }; }; + i2s0: i2s@1011a000 { + compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + status = "disabled"; + }; + cru: clock-controller@20000000 { compatible = "rockchip,rk3188-cru"; reg = <0x20000000 0x1000>; @@ -395,6 +423,17 @@ ; }; }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = , + , + , + , + , + ; + }; + }; }; }; diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts index ff522f8e3df4..d8c775e6d5fe 100644 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -17,6 +17,10 @@ compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; }; +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; @@ -44,7 +48,7 @@ regulator-always-on; regulator-boot-on; regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; regulator-name = "vdd_arm"; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 874e66dbb93b..cfc43789cac6 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -47,10 +47,27 @@ #address-cells = <1>; #size-cells = <0>; - cpu@500 { + cpu0: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x500>; + operating-points = < + /* KHz uV */ + 1608000 1350000 + 1512000 1300000 + 1416000 1200000 + 1200000 1100000 + 1008000 1050000 + 816000 1000000 + 696000 950000 + 600000 900000 + 408000 900000 + 312000 900000 + 216000 900000 + 126000 900000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@501 { device_type = "cpu"; @@ -177,6 +194,8 @@ compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac_peri 11>, <&dmac_peri 12>; + dma-names = "tx", "rx"; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; @@ -190,6 +209,8 @@ compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac_peri 13>, <&dmac_peri 14>; + dma-names = "tx", "rx"; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; @@ -203,6 +224,8 @@ compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac_peri 15>, <&dmac_peri 16>; + dma-names = "tx", "rx"; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; @@ -455,6 +478,16 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, <&cru ACLK_CPU>, + <&cru HCLK_CPU>, <&cru PCLK_CPU>, + <&cru ACLK_PERI>, <&cru HCLK_PERI>, + <&cru PCLK_PERI>; + assigned-clock-rates = <594000000>, <400000000>, + <500000000>, <300000000>, + <150000000>, <75000000>, + <300000000>, <150000000>, + <75000000>; }; grf: syscon@ff770000 { diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 499468d42ada..9ba92de511ca 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -367,6 +367,8 @@ reg = <0x20070000 0x1000>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmac2 10>, <&dmac2 11>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -378,6 +380,8 @@ reg = <0x20074000 0x1000>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmac2 12>, <&dmac2 13>; + dma-names = "tx", "rx"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index 57e00f9bce99..a25debb50401 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -198,10 +198,6 @@ status = "okay"; }; -&pwm { - status = "okay"; -}; - &pinctrl0 { gpio_leds: gpio-leds { samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi index ff5bdaac987a..0ccb414cd268 100644 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ b/arch/arm/boot/dts/s3c64xx.dtsi @@ -172,7 +172,6 @@ clocks = <&clocks PCLK_PWM>; samsung,pwm-outputs = <0>, <1>; #pwm-cells = <3>; - status = "disabled"; }; pinctrl0: pinctrl@7f008000 { diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index e0157b0f075c..1b0f30c2c4a5 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -9,12 +9,12 @@ * licensing only applies to this file, and not this project as a * whole. * - * a) This library is free software; you can redistribute it and/or + * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * - * This library is distributed in the hope that it will be useful, + * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. @@ -45,6 +45,7 @@ #include "skeleton.dtsi" #include +#include #include #include #include @@ -302,6 +303,15 @@ #size-cells = <1>; ranges; + dma1: dma-controller@f0004000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0004000 0x200>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&dma1_clk>; + clock-names = "dma_clk"; + }; + ramc0: ramc@f0010000 { compatible = "atmel,sama5d3-ddramc"; reg = <0xf0010000 0x200>; @@ -309,6 +319,15 @@ clock-names = "ddrck", "mpddr"; }; + dma0: dma-controller@f0014000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0014000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; + }; + pmc: pmc@f0018000 { compatible = "atmel,sama5d3-pmc"; reg = <0xf0018000 0x120>; @@ -761,6 +780,10 @@ compatible = "atmel,hsmci"; reg = <0xf8000000 0x600>; interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(0))>; + dma-names = "rxtx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; status = "disabled"; @@ -776,6 +799,13 @@ compatible = "atmel,at91rm9200-spi"; reg = <0xf8010000 0x100>; interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(10))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; clocks = <&spi0_clk>; @@ -787,6 +817,13 @@ compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8014000 0x4000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(2))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; #address-cells = <1>; @@ -817,7 +854,14 @@ i2c2: i2c@f8024000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8024000 0x4000>; - interrupts = <34 4 6>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(6))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; #address-cells = <1>; @@ -830,6 +874,10 @@ compatible = "atmel,hsmci"; reg = <0xfc000000 0x600>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(1))>; + dma-names = "rxtx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; status = "disabled"; @@ -843,6 +891,13 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xfc008000 0x100>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(16))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; clocks = <&usart2_clk>; @@ -854,6 +909,13 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xfc00c000 0x100>; interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(18))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; clocks = <&usart3_clk>; @@ -865,6 +927,13 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xfc010000 0x100>; interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(20))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart4>; clocks = <&usart4_clk>; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 30ef97e99dc5..3721cd433601 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -40,6 +40,7 @@ chosen { bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw"; + stdout-path = &scifa4; }; memory { @@ -112,7 +113,7 @@ }; }; - gpio-keys { + keyboard { compatible = "gpio-keys"; back-key { @@ -250,7 +251,7 @@ }; }; - ak4648: ak4648@0x12 { + ak4648: ak4648@12 { #sound-dai-cells = <0>; compatible = "asahi-kasei,ak4648"; reg = <0x12>; diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts new file mode 100644 index 000000000000..a8c00ee7522a --- /dev/null +++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts @@ -0,0 +1,151 @@ +/* + * Device Tree for the ST-Ericsson Nomadik S8815 board + * Produced by Calao Systems + */ + +/dts-v1/; +#include +#include +#include "ste-nomadik-stn8815.dtsi" + +/ { + model = "Nomadik STN8815NHK"; + compatible = "st,nomadik-nhk-15"; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; + }; + + aliases { + stmpe-i2c0 = &stmpe0; + stmpe-i2c1 = &stmpe1; + }; + + pinctrl { + stmpe2401_1 { + stmpe2401_1_nhk_mode: stmpe2401_1_nhk { + nhk_cfg1 { + ste,pins = "GPIO76_B20"; // IRQ line + ste,input = <0>; + }; + nhk_cfg2 { + ste,pins = "GPIO77_B8"; // reset line + ste,output = <1>; + }; + }; + }; + stmpe2401_2 { + stmpe2401_2_nhk_mode: stmpe2401_2_nhk { + nhk_cfg1 { + ste,pins = "GPIO78_A8"; // IRQ line + ste,input = <0>; + }; + nhk_cfg2 { + ste,pins = "GPIO79_C9"; // reset line + ste,output = <1>; + }; + }; + }; + }; + + src@101e0000 { + /* These chrystal outputs are not used on this board */ + disable-sxtalo; + disable-mxtalo; + }; + + /* This is where the interrupt is routed on the NHK-15 debug board */ + external-bus@34000000 { + compatible = "simple-bus"; + reg = <0x34000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x34000000 0x1000000>; + ethernet@300 { + compatible = "smsc,lan91c111"; + reg = <0x300 0x0fd00>; + reg-io-width = <2>; + reset-gpios = <&stmpe_gpio44 10 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&stmpe_gpio44>; + interrupts = <11 IRQ_TYPE_EDGE_RISING>; + }; + }; + + i2c0 { + stmpe0: stmpe2401@43 { + compatible = "st,stmpe2401"; + reg = <0x43>; + reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; // GPIO77 + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; // GPIO76 + interrupt-parent = <&gpio2>; + interrupt-controller; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&stmpe2401_1_nhk_mode>; + stmpe_gpio43: stmpe_gpio { + compatible = "st,stmpe-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + /* Some pins in alternate functions */ + st,norequest-mask = <0xf0f002>; + }; + stmpe_keypad { + compatible = "st,stmpe-keypad"; + debounce-interval = <64>; + st,scan-count = <8>; + st,no-autorepeat; + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = <0x00020072 // Vol down + 0x00030073 // Vol up + 0x0100009e // Back + 0x010100e3 // TV out + 0x01020098 // Lock + 0x0103013b // Start + 0x020000a3 // Next + 0x020100a4 // Play + 0x020200a5 // Prev + 0x02030160 // OK + 0x03000069 // Left + 0x0301006a // Right + 0x03020067 // Up + 0x0303006c>; // Down + }; + }; + stmpe1: stmpe2401@44 { + compatible = "st,stmpe2401"; + reg = <0x44>; + reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; // GPIO79 + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; // GPIO78 + interrupt-parent = <&gpio2>; + interrupt-controller; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&stmpe2401_2_nhk_mode>; + stmpe_gpio44: stmpe_gpio { + compatible = "st,stmpe-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + }; + + amba { + mmcsd: sdi@101f6000 { + cd-gpios = <&stmpe_gpio44 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>; + }; + }; + + /* Custom board node with GPIO pins to active etc */ + usb-s8815 { + /* This will turn off SATA so that MMC/SD can thrive */ + mmcsd-gpio { + gpios = <&stmpe_gpio44 2 0x1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts index 90d8b6c7a205..e411ff7769fe 100644 --- a/arch/arm/boot/dts/ste-nomadik-s8815.dts +++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts @@ -4,6 +4,7 @@ */ /dts-v1/; +#include #include "ste-nomadik-stn8815.dtsi" / { @@ -14,14 +15,6 @@ bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; }; - /* This is where the interrupt is routed on the S8815 board */ - external-bus@34000000 { - ethernet@300 { - interrupt-parent = <&gpio3>; - interrupts = <8 0x1>; - }; - }; - src@101e0000 { /* These chrystal drivers are not used on this board */ disable-sxtalo; @@ -47,6 +40,14 @@ }; }; }; + gpioi2c { + gpioi2c_default_mode: gpioi2c_default { + gpioi2c_default_cfg { + ste,pins = "GPIO73_C21", "GPIO74_C20"; + ste,input = <0>; + }; + }; + }; user-led { user_led_default_mode: user_led_default { user_led_default_cfg { @@ -65,6 +66,45 @@ }; }; + /* Ethernet */ + external-bus@34000000 { + compatible = "simple-bus"; + reg = <0x34000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x34000000 0x1000000>; + ethernet@300 { + compatible = "smsc,lan91c111"; + reg = <0x300 0x0fd00>; + interrupt-parent = <&gpio3>; + interrupts = <8 IRQ_TYPE_EDGE_RISING>; + }; + }; + + /* GPIO I2C connected to the USB portions of the STw4811 only */ + gpio-i2c { + compatible = "i2c-gpio"; + gpios = <&gpio2 10 0>, /* sda */ + <&gpio2 9 0>; /* scl */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gpioi2c_default_mode>; + + stw4811@2d { + compatible = "st,stw4811-usb"; + reg = <0x2d>; + }; + }; + + + /* Configure card detect for the uSD slot */ + amba { + mmcsd: sdi@101f6000 { + cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + }; + }; + /* Custom board node with GPIO pins to active etc */ usb-s8815 { /* This will bias the MMC/SD card detect line */ diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index dbcf521b017f..f435ff20aefe 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -117,7 +117,7 @@ mmcsd_default_mux: mmcsd_mux { mmcsd_default_mux { ste,function = "mmcsd"; - ste,pins = "mmcsd_a_1"; + ste,pins = "mmcsd_a_1", "mmcsd_b_1"; }; }; mmcsd_default_mode: mmcsd_default { @@ -127,9 +127,9 @@ ste,output = <0>; }; mmcsd_default_cfg2 { - /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */ + /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 */ ste,pins = "GPIO10_C11", "GPIO15_A12", - "GPIO16_C13"; + "GPIO16_C13", "GPIO23_D15"; ste,output = <1>; }; mmcsd_default_cfg3 { @@ -169,21 +169,11 @@ }; }; }; - i2c2 { - i2c2_default_mode: i2c2_default { - i2c2_default_cfg { - ste,pins = "GPIO73_C21", "GPIO74_C20"; - ste,input = <0>; - }; - }; - }; }; src: src@101e0000 { compatible = "stericsson,nomadik-src"; reg = <0x101e0000 0x1000>; - disable-sxtalo; - disable-mxtalo; /* * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz @@ -683,18 +673,6 @@ }; }; - external-bus@34000000 { - compatible = "simple-bus"; - reg = <0x34000000 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x34000000 0x1000000>; - ethernet@300 { - compatible = "smsc,lan91c111"; - reg = <0x300 0x0fd00>; - }; - }; - /* I2C0 connected to the STw4811 power management chip */ i2c0 { compatible = "st,nomadik-i2c", "arm,primecell"; @@ -749,22 +727,6 @@ }; }; - /* I2C2 connected to the USB portions of the STw4811 only */ - i2c2 { - compatible = "i2c-gpio"; - gpios = <&gpio2 10 0>, /* sda */ - <&gpio2 9 0>; /* scl */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_default_mode>; - - stw4811@2d { - compatible = "st,stw4811-usb"; - reg = <0x2d>; - }; - }; - amba { compatible = "arm,amba-bus"; #address-cells = <1>; @@ -844,7 +806,6 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; vmmc-supply = <&vmmc_regulator>; diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index 800f46f009f3..e65744fc12ab 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -5,8 +5,13 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include / { clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* * Fixed 30MHz oscillator inputs to SoC */ @@ -19,10 +24,59 @@ /* * ARM Peripheral clock for timers */ - arm_periph_clk: arm-periph-clk { + arm_periph_clk: clk-m-a9-periphs { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <600000000>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; + + /* + * A9 PLL. + */ + clockgen-a9@92b0000 { + compatible = "st,clkgen-c32"; + reg = <0x92b0000 0xffff>; + + clockgen_a9_pll: clockgen-a9-pll { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clockgen-a9-pll-odf"; + }; + }; + + /* + * ARM CPU related clocks. + */ + clk_m_a9: clk-m-a9@92b0000 { + #clock-cells = <0>; + compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + reg = <0x92b0000 0x10000>; + + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + }; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; }; /* @@ -35,5 +89,238 @@ clock-frequency = <200000000>; clock-output-names = "clk-s-icn-reg-0"; }; + + clockgen-a@090ff000 { + compatible = "st,clkgen-c32"; + reg = <0x90ff000 0x1000>; + + clk_s_a0_pll: clk-s-a0-pll { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-a0-pll-ofd-0"; + }; + + clk_s_a0_flexgen: clk-s-a0-flexgen { + compatible = "st,flexgen"; + + #clock-cells = <1>; + + clocks = <&clk_s_a0_pll 0>, + <&clk_sysin>; + + clock-output-names = "clk-ic-lmi0"; + }; + }; + + clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-C", "st,quadfs"; + reg = <0x9103000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-c0-fs0-ch0", + "clk-s-c0-fs0-ch1", + "clk-s-c0-fs0-ch2", + "clk-s-c0-fs0-ch3"; + }; + + clk_s_c0: clockgen-c@09103000 { + compatible = "st,clkgen-c32"; + reg = <0x9103000 0x1000>; + + clk_s_c0_pll0: clk-s-c0-pll0 { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-c0-pll0-odf-0"; + }; + + clk_s_c0_pll1: clk-s-c0-pll1 { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-c0-pll1-odf-0"; + }; + + clk_s_c0_flexgen: clk-s-c0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_c0_pll0 0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_quadfs 0>, + <&clk_s_c0_quadfs 1>, + <&clk_s_c0_quadfs 2>, + <&clk_s_c0_quadfs 3>, + <&clk_sysin>; + + clock-output-names = "clk-icn-gpu", + "clk-fdma", + "clk-nand", + "clk-hva", + "clk-proc-stfe", + "clk-proc-tp", + "clk-rx-icn-dmu", + "clk-rx-icn-hva", + "clk-icn-cpu", + "clk-tx-icn-dmu", + "clk-mmc-0", + "clk-mmc-1", + "clk-jpegdec", + "clk-ext2fa9", + "clk-ic-bdisp-0", + "clk-ic-bdisp-1", + "clk-pp-dmu", + "clk-vid-dmu", + "clk-dss-lpc", + "clk-st231-aud-0", + "clk-st231-gp-1", + "clk-st231-dmu", + "clk-icn-lmi", + "clk-tx-icn-disp-1", + "clk-icn-sbc", + "clk-stfe-frc2", + "clk-eth-phy", + "clk-eth-ref-phyclk", + "clk-flash-promip", + "clk-main-disp", + "clk-aux-disp", + "clk-compo-dvp"; + }; + }; + + clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-D", "st,quadfs"; + reg = <0x9104000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-d0-fs0-ch0", + "clk-s-d0-fs0-ch1", + "clk-s-d0-fs0-ch2", + "clk-s-d0-fs0-ch3"; + }; + + clockgen-d0@09104000 { + compatible = "st,clkgen-c32"; + reg = <0x9104000 0x1000>; + + clk_s_d0_flexgen: clk-s-d0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_d0_quadfs 0>, + <&clk_s_d0_quadfs 1>, + <&clk_s_d0_quadfs 2>, + <&clk_s_d0_quadfs 3>, + <&clk_sysin>; + + clock-output-names = "clk-pcm-0", + "clk-pcm-1", + "clk-pcm-2", + "clk-spdiff"; + }; + }; + + clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-D", "st,quadfs"; + reg = <0x9106000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-d2-fs0-ch0", + "clk-s-d2-fs0-ch1", + "clk-s-d2-fs0-ch2", + "clk-s-d2-fs0-ch3"; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + clockgen-d2@x9106000 { + compatible = "st,clkgen-c32"; + reg = <0x9106000 0x1000>; + + clk_s_d2_flexgen: clk-s-d2-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_quadfs 2>, + <&clk_s_d2_quadfs 3>, + <&clk_sysin>, + <&clk_sysin>, + <&clk_tmdsout_hdmi>; + + clock-output-names = "clk-pix-main-disp", + "clk-pix-pip", + "clk-pix-gdp1", + "clk-pix-gdp2", + "clk-pix-gdp3", + "clk-pix-gdp4", + "clk-pix-aux-disp", + "clk-denc", + "clk-pix-hddac", + "clk-hddac", + "clk-sddac", + "clk-pix-dvo", + "clk-dvo", + "clk-pix-hdmi", + "clk-tmds-hdmi", + "clk-ref-hdmiphy"; + }; + }; + + clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-D", "st,quadfs"; + reg = <0x9107000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-d3-fs0-ch0", + "clk-s-d3-fs0-ch1", + "clk-s-d3-fs0-ch2", + "clk-s-d3-fs0-ch3"; + }; + + clockgen-d3@9107000 { + compatible = "st,clkgen-c32"; + reg = <0x9107000 0x1000>; + + clk_s_d3_flexgen: clk-s-d3-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_d3_quadfs 0>, + <&clk_s_d3_quadfs 1>, + <&clk_s_d3_quadfs 2>, + <&clk_s_d3_quadfs 3>, + <&clk_sysin>; + + clock-output-names = "clk-stfe-frc1", + "clk-tsout-0", + "clk-tsout-1", + "clk-mchi", + "clk-vsens-compo", + "clk-frc1-remote", + "clk-lpc-0", + "clk-lpc-1"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index 4f9024f19866..50637f5168d4 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -8,6 +8,7 @@ */ #include "stih407-clock.dtsi" #include "stih407-pinctrl.dtsi" +#include / { #address-cells = <1>; #size-cells = <1>; @@ -63,6 +64,21 @@ ranges; compatible = "simple-bus"; + powerdown: powerdown-controller { + compatible = "st,stih407-powerdown"; + #reset-cells = <1>; + }; + + softreset: softreset-controller { + compatible = "st,stih407-softreset"; + #reset-cells = <1>; + }; + + picophyreset: picophyreset-controller { + compatible = "st,stih407-picophyreset"; + #reset-cells = <1>; + }; + syscfg_sbc: sbc-syscfg@9620000 { compatible = "st,stih407-sbc-syscfg", "syscon"; reg = <0x9620000 0x1000>; @@ -104,7 +120,7 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial0>; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; status = "disabled"; }; @@ -115,7 +131,7 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial1>; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; status = "disabled"; }; @@ -126,7 +142,7 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial2>; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; status = "disabled"; }; @@ -158,7 +174,7 @@ compatible = "st,comms-ssc4-i2c"; interrupts = ; reg = <0x9840000 0x110>; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -171,7 +187,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0x9841000 0x110>; interrupts = ; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -184,7 +200,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0x9842000 0x110>; interrupts = ; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -197,7 +213,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0x9843000 0x110>; interrupts = ; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -210,7 +226,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0x9844000 0x110>; interrupts = ; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -223,7 +239,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0x9845000 0x110>; interrupts = ; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index 8509a037ae21..3791ad95dbaf 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -11,33 +11,33 @@ / { aliases { - gpio0 = &PIO0; - gpio1 = &PIO1; - gpio2 = &PIO2; - gpio3 = &PIO3; - gpio4 = &PIO4; - gpio5 = &PIO5; - gpio6 = &PIO6; - gpio7 = &PIO7; - gpio8 = &PIO8; - gpio9 = &PIO9; - gpio10 = &PIO10; - gpio11 = &PIO11; - gpio12 = &PIO12; - gpio13 = &PIO13; - gpio14 = &PIO14; - gpio15 = &PIO15; - gpio16 = &PIO16; - gpio17 = &PIO17; - gpio18 = &PIO18; - gpio19 = &PIO100; - gpio20 = &PIO101; - gpio21 = &PIO102; - gpio22 = &PIO103; - gpio23 = &PIO104; - gpio24 = &PIO105; - gpio25 = &PIO106; - gpio26 = &PIO107; + gpio0 = &pio0; + gpio1 = &pio1; + gpio2 = &pio2; + gpio3 = &pio3; + gpio4 = &pio4; + gpio5 = &pio5; + gpio6 = &pio6; + gpio7 = &pio7; + gpio8 = &pio8; + gpio9 = &pio9; + gpio10 = &pio10; + gpio11 = &pio11; + gpio12 = &pio12; + gpio13 = &pio13; + gpio14 = &pio14; + gpio15 = &pio15; + gpio16 = &pio16; + gpio17 = &pio17; + gpio18 = &pio18; + gpio19 = &pio100; + gpio20 = &pio101; + gpio21 = &pio102; + gpio22 = &pio103; + gpio23 = &pio104; + gpio24 = &pio105; + gpio25 = &pio106; + gpio26 = &pio107; }; soc { @@ -52,7 +52,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfe610000 0x5000>; - PIO0: gpio@fe610000 { + pio0: gpio@fe610000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -60,7 +60,7 @@ reg = <0 0x100>; st,bank-name = "PIO0"; }; - PIO1: gpio@fe611000 { + pio1: gpio@fe611000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -68,7 +68,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO1"; }; - PIO2: gpio@fe612000 { + pio2: gpio@fe612000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -76,7 +76,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO2"; }; - PIO3: gpio@fe613000 { + pio3: gpio@fe613000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -84,7 +84,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO3"; }; - PIO4: gpio@fe614000 { + pio4: gpio@fe614000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -96,8 +96,8 @@ sbc_serial1 { pinctrl_sbc_serial1:sbc_serial1 { st,pins { - tx = <&PIO2 6 ALT3 OUT>; - rx = <&PIO2 7 ALT3 IN>; + tx = <&pio2 6 ALT3 OUT>; + rx = <&pio2 7 ALT3 IN>; }; }; }; @@ -105,15 +105,15 @@ keyscan { pinctrl_keyscan: keyscan { st,pins { - keyin0 = <&PIO0 2 ALT2 IN>; - keyin1 = <&PIO0 3 ALT2 IN>; - keyin2 = <&PIO0 4 ALT2 IN>; - keyin3 = <&PIO2 6 ALT2 IN>; - - keyout0 = <&PIO1 6 ALT2 OUT>; - keyout1 = <&PIO1 7 ALT2 OUT>; - keyout2 = <&PIO0 6 ALT2 OUT>; - keyout3 = <&PIO2 7 ALT2 OUT>; + keyin0 = <&pio0 2 ALT2 IN>; + keyin1 = <&pio0 3 ALT2 IN>; + keyin2 = <&pio0 4 ALT2 IN>; + keyin3 = <&pio2 6 ALT2 IN>; + + keyout0 = <&pio1 6 ALT2 OUT>; + keyout1 = <&pio1 7 ALT2 OUT>; + keyout2 = <&pio0 6 ALT2 OUT>; + keyout3 = <&pio2 7 ALT2 OUT>; }; }; }; @@ -121,8 +121,8 @@ sbc_i2c0 { pinctrl_sbc_i2c0_default: sbc_i2c0-default { st,pins { - sda = <&PIO4 6 ALT1 BIDIR>; - scl = <&PIO4 5 ALT1 BIDIR>; + sda = <&pio4 6 ALT1 BIDIR>; + scl = <&pio4 5 ALT1 BIDIR>; }; }; }; @@ -130,8 +130,8 @@ sbc_i2c1 { pinctrl_sbc_i2c1_default: sbc_i2c1-default { st,pins { - sda = <&PIO3 2 ALT2 BIDIR>; - scl = <&PIO3 1 ALT2 BIDIR>; + sda = <&pio3 2 ALT2 BIDIR>; + scl = <&pio3 1 ALT2 BIDIR>; }; }; }; @@ -139,7 +139,7 @@ rc{ pinctrl_ir: ir0 { st,pins { - ir = <&PIO4 0 ALT2 IN>; + ir = <&pio4 0 ALT2 IN>; }; }; }; @@ -147,49 +147,49 @@ gmac1 { pinctrl_mii1: mii1 { st,pins { - txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&PIO0 7 ALT1 IN BYPASS 1000>; - mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; - mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&PIO1 2 ALT1 IN BYPASS 1000>; - mdint = <&PIO1 3 ALT1 IN BYPASS 0>; - rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>; + txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; + col = <&pio0 7 ALT1 IN BYPASS 1000>; + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + crs = <&pio1 2 ALT1 IN BYPASS 1000>; + mdint = <&pio1 3 ALT1 IN BYPASS 0>; + rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>; }; }; pinctrl_rgmii1: rgmii1-0 { st,pins { - txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>; - txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>; - txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>; - txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>; - txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; - mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; - mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>; - rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>; - rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>; - rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>; - - rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; + txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>; + txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>; + txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>; + txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; + rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; + rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; + rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; + + rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; + + clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; }; }; }; @@ -206,7 +206,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfee00000 0x8000>; - PIO5: gpio@fee00000 { + pio5: gpio@fee00000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -214,7 +214,7 @@ reg = <0 0x100>; st,bank-name = "PIO5"; }; - PIO6: gpio@fee01000 { + pio6: gpio@fee01000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -222,7 +222,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO6"; }; - PIO7: gpio@fee02000 { + pio7: gpio@fee02000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -230,7 +230,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO7"; }; - PIO8: gpio@fee03000 { + pio8: gpio@fee03000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -238,7 +238,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO8"; }; - PIO9: gpio@fee04000 { + pio9: gpio@fee04000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -246,7 +246,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO9"; }; - PIO10: gpio@fee05000 { + pio10: gpio@fee05000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -254,7 +254,7 @@ reg = <0x5000 0x100>; st,bank-name = "PIO10"; }; - PIO11: gpio@fee06000 { + pio11: gpio@fee06000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -262,7 +262,7 @@ reg = <0x6000 0x100>; st,bank-name = "PIO11"; }; - PIO12: gpio@fee07000 { + pio12: gpio@fee07000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -274,8 +274,8 @@ i2c0 { pinctrl_i2c0_default: i2c0-default { st,pins { - sda = <&PIO9 3 ALT1 BIDIR>; - scl = <&PIO9 2 ALT1 BIDIR>; + sda = <&pio9 3 ALT1 BIDIR>; + scl = <&pio9 2 ALT1 BIDIR>; }; }; }; @@ -283,8 +283,8 @@ i2c1 { pinctrl_i2c1_default: i2c1-default { st,pins { - sda = <&PIO12 1 ALT1 BIDIR>; - scl = <&PIO12 0 ALT1 BIDIR>; + sda = <&pio12 1 ALT1 BIDIR>; + scl = <&pio12 0 ALT1 BIDIR>; }; }; }; @@ -301,7 +301,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfe820000 0x8000>; - PIO13: gpio@fe820000 { + pio13: gpio@fe820000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -309,7 +309,7 @@ reg = <0 0x100>; st,bank-name = "PIO13"; }; - PIO14: gpio@fe821000 { + pio14: gpio@fe821000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -317,7 +317,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO14"; }; - PIO15: gpio@fe822000 { + pio15: gpio@fe822000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -325,7 +325,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO15"; }; - PIO16: gpio@fe823000 { + pio16: gpio@fe823000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -333,7 +333,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO16"; }; - PIO17: gpio@fe824000 { + pio17: gpio@fe824000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -341,7 +341,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO17"; }; - PIO18: gpio@fe825000 { + pio18: gpio@fe825000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -353,8 +353,8 @@ serial2 { pinctrl_serial2: serial2-0 { st,pins { - tx = <&PIO17 4 ALT2 OUT>; - rx = <&PIO17 5 ALT2 IN>; + tx = <&pio17 4 ALT2 OUT>; + rx = <&pio17 5 ALT2 IN>; }; }; }; @@ -362,73 +362,94 @@ gmac0{ pinctrl_mii0: mii0 { st,pins { - mdint = <&PIO13 6 ALT2 IN BYPASS 0>; - txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - - txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&PIO15 2 ALT2 IN BYPASS 1000>; - col = <&PIO15 3 ALT2 IN BYPASS 1000>; - mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; - mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>; + mdint = <&pio13 6 ALT2 IN BYPASS 0>; + txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + + txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + + txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; + txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + crs = <&pio15 2 ALT2 IN BYPASS 1000>; + col = <&pio15 3 ALT2 IN BYPASS 1000>; + mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; + mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; + + rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; + phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>; }; }; pinctrl_gmii0: gmii0 { st,pins { - mdint = <&PIO13 6 ALT2 IN BYPASS 0>; - mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; - mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; - txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - - txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - - txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - crs = <&PIO15 2 ALT2 IN BYPASS 1000>; - col = <&PIO15 3 ALT2 IN BYPASS 1000>; - rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; - clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; + mdint = <&pio13 6 ALT2 IN BYPASS 0>; + mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; + mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; + txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; + + txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; + txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; + txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + + txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; + txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; + crs = <&pio15 2 ALT2 IN BYPASS 1000>; + col = <&pio15 3 ALT2 IN BYPASS 1000>; + rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + + rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + + rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; + clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; }; }; }; + + mmc0 { + pinctrl_mmc0: mmc0 { + st,pins { + mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; + data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; + data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; + data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; + cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; + wp = <&pio15 3 ALT4 IN>; + data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; + data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; + data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; + data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; + pwr = <&pio17 1 ALT4 OUT>; + cd = <&pio17 2 ALT4 IN>; + led = <&pio17 3 ALT4 OUT>; + }; + }; + }; }; pin-controller-left { @@ -442,7 +463,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfd6b0000 0x3000>; - PIO100: gpio@fd6b0000 { + pio100: gpio@fd6b0000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -450,7 +471,7 @@ reg = <0 0x100>; st,bank-name = "PIO100"; }; - PIO101: gpio@fd6b1000 { + pio101: gpio@fd6b1000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -458,7 +479,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO101"; }; - PIO102: gpio@fd6b2000 { + pio102: gpio@fd6b2000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -479,7 +500,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfd330000 0x5000>; - PIO103: gpio@fd330000 { + pio103: gpio@fd330000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -487,7 +508,7 @@ reg = <0 0x100>; st,bank-name = "PIO103"; }; - PIO104: gpio@fd331000 { + pio104: gpio@fd331000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -495,7 +516,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO104"; }; - PIO105: gpio@fd332000 { + pio105: gpio@fd332000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -503,7 +524,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO105"; }; - PIO106: gpio@fd333000 { + pio106: gpio@fd333000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -511,7 +532,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO106"; }; - PIO107: gpio@fd334000 { + pio107: gpio@fd334000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index a0f6f75fe3b5..9198c12765ea 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi @@ -218,5 +218,17 @@ resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, <&softreset STIH415_KEYSCAN_SOFTRESET>; }; + + mmc0: sdhci@fe81e000 { + compatible = "st,sdhci"; + status = "disabled"; + reg = <0xfe81e000 0x1000>; + interrupts = ; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0>; + clock-names = "mmc"; + clocks = <&clk_s_a1_ls 1>; + }; }; }; diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts index 4e2df66b99ea..5d1543babf56 100644 --- a/arch/arm/boot/dts/stih416-b2020.dts +++ b/arch/arm/boot/dts/stih416-b2020.dts @@ -12,4 +12,26 @@ / { model = "STiH416 B2020"; compatible = "st,stih416-b2020", "st,stih416"; + + soc { + mmc1: sdhci@fe81f000 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + miphy365x_phy: miphy365x@fe382000 { + phy_port0: port@fe382000 { + st,sata-gen = <3>; + }; + + phy_port1: port@fe38a000 { + st,pcie-tx-pol-inv; + }; + }; + + sata0: sata@fe380000{ + status = "okay"; + }; + }; }; diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts index ba0fa2caaf18..956fab8b8ffe 100644 --- a/arch/arm/boot/dts/stih416-b2020e.dts +++ b/arch/arm/boot/dts/stih416-b2020e.dts @@ -19,17 +19,37 @@ red { #gpio-cells = <1>; label = "Front Panel LED"; - gpios = <&PIO4 1>; + gpios = <&pio4 1>; linux,default-trigger = "heartbeat"; }; green { - gpios = <&PIO1 3>; + gpios = <&pio1 3>; default-state = "off"; }; }; ethernet1: dwmac@fef08000 { - snps,reset-gpio = <&PIO0 7>; + snps,reset-gpio = <&pio0 7>; + }; + + mmc1: sdhci@fe81f000 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + miphy365x_phy: miphy365x@fe382000 { + phy_port0: port@fe382000 { + st,sata-gen = <3>; + }; + + phy_port1: port@fe38a000 { + st,pcie-tx-pol-inv; + }; + }; + + sata0: sata@fe380000{ + status = "okay"; }; }; }; diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index ee6c119e261e..c2025bc37dd5 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -12,36 +12,36 @@ / { aliases { - gpio0 = &PIO0; - gpio1 = &PIO1; - gpio2 = &PIO2; - gpio3 = &PIO3; - gpio4 = &PIO4; - gpio5 = &PIO40; - gpio6 = &PIO5; - gpio7 = &PIO6; - gpio8 = &PIO7; - gpio9 = &PIO8; - gpio10 = &PIO9; - gpio11 = &PIO10; - gpio12 = &PIO11; - gpio13 = &PIO12; - gpio14 = &PIO30; - gpio15 = &PIO31; - gpio16 = &PIO13; - gpio17 = &PIO14; - gpio18 = &PIO15; - gpio19 = &PIO16; - gpio20 = &PIO17; - gpio21 = &PIO18; - gpio22 = &PIO100; - gpio23 = &PIO101; - gpio24 = &PIO102; - gpio25 = &PIO103; - gpio26 = &PIO104; - gpio27 = &PIO105; - gpio28 = &PIO106; - gpio29 = &PIO107; + gpio0 = &pio0; + gpio1 = &pio1; + gpio2 = &pio2; + gpio3 = &pio3; + gpio4 = &pio4; + gpio5 = &pio40; + gpio6 = &pio5; + gpio7 = &pio6; + gpio8 = &pio7; + gpio9 = &pio8; + gpio10 = &pio9; + gpio11 = &pio10; + gpio12 = &pio11; + gpio13 = &pio12; + gpio14 = &pio30; + gpio15 = &pio31; + gpio16 = &pio13; + gpio17 = &pio14; + gpio18 = &pio15; + gpio19 = &pio16; + gpio20 = &pio17; + gpio21 = &pio18; + gpio22 = &pio100; + gpio23 = &pio101; + gpio24 = &pio102; + gpio25 = &pio103; + gpio26 = &pio104; + gpio27 = &pio105; + gpio28 = &pio106; + gpio29 = &pio107; }; soc { @@ -56,7 +56,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfe610000 0x6000>; - PIO0: gpio@fe610000 { + pio0: gpio@fe610000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -64,7 +64,7 @@ reg = <0 0x100>; st,bank-name = "PIO0"; }; - PIO1: gpio@fe611000 { + pio1: gpio@fe611000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -72,7 +72,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO1"; }; - PIO2: gpio@fe612000 { + pio2: gpio@fe612000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -80,7 +80,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO2"; }; - PIO3: gpio@fe613000 { + pio3: gpio@fe613000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -88,7 +88,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO3"; }; - PIO4: gpio@fe614000 { + pio4: gpio@fe614000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -96,7 +96,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO4"; }; - PIO40: gpio@fe615000 { + pio40: gpio@fe615000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -109,15 +109,15 @@ rc{ pinctrl_ir: ir0 { st,pins { - ir = <&PIO4 0 ALT2 IN>; + ir = <&pio4 0 ALT2 IN>; }; }; }; sbc_serial1 { pinctrl_sbc_serial1: sbc_serial1 { st,pins { - tx = <&PIO2 6 ALT3 OUT>; - rx = <&PIO2 7 ALT3 IN>; + tx = <&pio2 6 ALT3 OUT>; + rx = <&pio2 7 ALT3 IN>; }; }; }; @@ -125,15 +125,15 @@ keyscan { pinctrl_keyscan: keyscan { st,pins { - keyin0 = <&PIO0 2 ALT2 IN>; - keyin1 = <&PIO0 3 ALT2 IN>; - keyin2 = <&PIO0 4 ALT2 IN>; - keyin3 = <&PIO2 6 ALT2 IN>; - - keyout0 = <&PIO1 6 ALT2 OUT>; - keyout1 = <&PIO1 7 ALT2 OUT>; - keyout2 = <&PIO0 6 ALT2 OUT>; - keyout3 = <&PIO2 7 ALT2 OUT>; + keyin0 = <&pio0 2 ALT2 IN>; + keyin1 = <&pio0 3 ALT2 IN>; + keyin2 = <&pio0 4 ALT2 IN>; + keyin3 = <&pio2 6 ALT2 IN>; + + keyout0 = <&pio1 6 ALT2 OUT>; + keyout1 = <&pio1 7 ALT2 OUT>; + keyout2 = <&pio0 6 ALT2 OUT>; + keyout3 = <&pio2 7 ALT2 OUT>; }; }; }; @@ -141,8 +141,8 @@ sbc_i2c0 { pinctrl_sbc_i2c0_default: sbc_i2c0-default { st,pins { - sda = <&PIO4 6 ALT1 BIDIR>; - scl = <&PIO4 5 ALT1 BIDIR>; + sda = <&pio4 6 ALT1 BIDIR>; + scl = <&pio4 5 ALT1 BIDIR>; }; }; }; @@ -150,8 +150,8 @@ sbc_i2c1 { pinctrl_sbc_i2c1_default: sbc_i2c1-default { st,pins { - sda = <&PIO3 2 ALT2 BIDIR>; - scl = <&PIO3 1 ALT2 BIDIR>; + sda = <&pio3 2 ALT2 BIDIR>; + scl = <&pio3 1 ALT2 BIDIR>; }; }; }; @@ -159,51 +159,51 @@ gmac1 { pinctrl_mii1: mii1 { st,pins { - txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&PIO0 7 ALT1 IN BYPASS 1000>; - - mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>; - mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&PIO1 2 ALT1 IN BYPASS 1000>; - mdint = <&PIO1 3 ALT1 IN BYPASS 0>; - rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - - rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>; + txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; + col = <&pio0 7 ALT1 IN BYPASS 1000>; + + mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + crs = <&pio1 2 ALT1 IN BYPASS 1000>; + mdint = <&pio1 3 ALT1 IN BYPASS 0>; + rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + + rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; }; }; pinctrl_rgmii1: rgmii1-0 { st,pins { - txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>; - txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>; - txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>; - txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>; - txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; - - mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; - mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>; - rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>; - rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>; - rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>; - - rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; + txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>; + txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>; + txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>; + txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; + + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>; + rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>; + rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>; + rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>; + + rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; + + clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; }; }; }; @@ -220,7 +220,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfee00000 0x10000>; - PIO5: gpio@fee00000 { + pio5: gpio@fee00000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -228,7 +228,7 @@ reg = <0 0x100>; st,bank-name = "PIO5"; }; - PIO6: gpio@fee01000 { + pio6: gpio@fee01000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -236,7 +236,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO6"; }; - PIO7: gpio@fee02000 { + pio7: gpio@fee02000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -244,7 +244,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO7"; }; - PIO8: gpio@fee03000 { + pio8: gpio@fee03000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -252,7 +252,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO8"; }; - PIO9: gpio@fee04000 { + pio9: gpio@fee04000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -260,7 +260,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO9"; }; - PIO10: gpio@fee05000 { + pio10: gpio@fee05000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -268,7 +268,7 @@ reg = <0x5000 0x100>; st,bank-name = "PIO10"; }; - PIO11: gpio@fee06000 { + pio11: gpio@fee06000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -276,7 +276,7 @@ reg = <0x6000 0x100>; st,bank-name = "PIO11"; }; - PIO12: gpio@fee07000 { + pio12: gpio@fee07000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -284,7 +284,7 @@ reg = <0x7000 0x100>; st,bank-name = "PIO12"; }; - PIO30: gpio@fee08000 { + pio30: gpio@fee08000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -292,7 +292,7 @@ reg = <0x8000 0x100>; st,bank-name = "PIO30"; }; - PIO31: gpio@fee09000 { + pio31: gpio@fee09000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -304,7 +304,7 @@ serial2-oe { pinctrl_serial2_oe: serial2-1 { st,pins { - output-enable = <&PIO11 3 ALT2 OUT>; + output-enable = <&pio11 3 ALT2 OUT>; }; }; }; @@ -312,8 +312,8 @@ i2c0 { pinctrl_i2c0_default: i2c0-default { st,pins { - sda = <&PIO9 3 ALT1 BIDIR>; - scl = <&PIO9 2 ALT1 BIDIR>; + sda = <&pio9 3 ALT1 BIDIR>; + scl = <&pio9 2 ALT1 BIDIR>; }; }; }; @@ -321,8 +321,8 @@ i2c1 { pinctrl_i2c1_default: i2c1-default { st,pins { - sda = <&PIO12 1 ALT1 BIDIR>; - scl = <&PIO12 0 ALT1 BIDIR>; + sda = <&pio12 1 ALT1 BIDIR>; + scl = <&pio12 0 ALT1 BIDIR>; }; }; }; @@ -330,12 +330,12 @@ fsm { pinctrl_fsm: fsm { st,pins { - spi-fsm-clk = <&PIO12 2 ALT1 OUT>; - spi-fsm-cs = <&PIO12 3 ALT1 OUT>; - spi-fsm-mosi = <&PIO12 4 ALT1 OUT>; - spi-fsm-miso = <&PIO12 5 ALT1 IN>; - spi-fsm-hol = <&PIO12 6 ALT1 OUT>; - spi-fsm-wp = <&PIO12 7 ALT1 OUT>; + spi-fsm-clk = <&pio12 2 ALT1 OUT>; + spi-fsm-cs = <&pio12 3 ALT1 OUT>; + spi-fsm-mosi = <&pio12 4 ALT1 OUT>; + spi-fsm-miso = <&pio12 5 ALT1 IN>; + spi-fsm-hol = <&pio12 6 ALT1 OUT>; + spi-fsm-wp = <&pio12 7 ALT1 OUT>; }; }; }; @@ -352,7 +352,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfe820000 0x6000>; - PIO13: gpio@fe820000 { + pio13: gpio@fe820000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -360,7 +360,7 @@ reg = <0 0x100>; st,bank-name = "PIO13"; }; - PIO14: gpio@fe821000 { + pio14: gpio@fe821000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -368,7 +368,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO14"; }; - PIO15: gpio@fe822000 { + pio15: gpio@fe822000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -376,7 +376,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO15"; }; - PIO16: gpio@fe823000 { + pio16: gpio@fe823000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -384,7 +384,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO16"; }; - PIO17: gpio@fe824000 { + pio17: gpio@fe824000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -392,7 +392,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO17"; }; - PIO18: gpio@fe825000 { + pio18: gpio@fe825000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -405,8 +405,8 @@ serial2 { pinctrl_serial2: serial2-0 { st,pins { - tx = <&PIO17 4 ALT2 OUT>; - rx = <&PIO17 5 ALT2 IN>; + tx = <&pio17 4 ALT2 OUT>; + rx = <&pio17 5 ALT2 IN>; }; }; }; @@ -414,28 +414,28 @@ gmac0 { pinctrl_mii0: mii0 { st,pins { - mdint = <&PIO13 6 ALT2 IN BYPASS 0>; - txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&PIO15 2 ALT2 IN BYPASS 1000>; - col = <&PIO15 3 ALT2 IN BYPASS 1000>; - mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>; - mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>; + mdint = <&pio13 6 ALT2 IN BYPASS 0>; + txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + + txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; + txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + crs = <&pio15 2 ALT2 IN BYPASS 1000>; + col = <&pio15 3 ALT2 IN BYPASS 1000>; + mdio= <&pio15 4 ALT2 OUT BYPASS 1500>; + mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; + + rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; + phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>; }; }; @@ -445,25 +445,64 @@ }; pinctrl_rgmii0: rgmii0 { st,pins { - phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; - txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>; - txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>; - txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>; - txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>; - txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>; - txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; - - mdio = <&PIO15 4 ALT2 OUT BYPASS 0>; - mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>; - rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>; - rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>; - rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>; - rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>; - rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>; - - clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; + txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>; + txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>; + txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>; + txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>; + txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>; + txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; + + mdio = <&pio15 4 ALT2 OUT BYPASS 0>; + mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; + + rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>; + rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>; + rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>; + rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>; + rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>; + rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>; + + clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>; + }; + }; + }; + + mmc0 { + pinctrl_mmc0: mmc0 { + st,pins { + mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; + data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; + data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; + data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; + cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; + wp = <&pio15 3 ALT4 IN>; + data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; + data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; + data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; + data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; + pwr = <&pio17 1 ALT4 OUT>; + cd = <&pio17 2 ALT4 IN>; + led = <&pio17 3 ALT4 OUT>; + }; + }; + }; + mmc1 { + pinctrl_mmc1: mmc1 { + st,pins { + mmcclk = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>; + data1 = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>; + data2 = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>; + data3 = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>; + cmd = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>; + data4 = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>; + data5 = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>; + data6 = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>; + data7 = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>; + pwr = <&pio16 2 ALT3 OUT>; + nreset = <&pio13 6 ALT3 OUT>; }; }; }; @@ -480,7 +519,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfd6b0000 0x3000>; - PIO100: gpio@fd6b0000 { + pio100: gpio@fd6b0000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -488,7 +527,7 @@ reg = <0 0x100>; st,bank-name = "PIO100"; }; - PIO101: gpio@fd6b1000 { + pio101: gpio@fd6b1000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -496,7 +535,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO101"; }; - PIO102: gpio@fd6b2000 { + pio102: gpio@fd6b2000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -517,7 +556,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfd330000 0x5000>; - PIO103: gpio@fd330000 { + pio103: gpio@fd330000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -525,7 +564,7 @@ reg = <0 0x100>; st,bank-name = "PIO103"; }; - PIO104: gpio@fd331000 { + pio104: gpio@fd331000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -533,7 +572,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO104"; }; - PIO105: gpio@fd332000 { + pio105: gpio@fd332000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -541,7 +580,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO105"; }; - PIO106: gpio@fd333000 { + pio106: gpio@fd333000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -550,7 +589,7 @@ st,bank-name = "PIO106"; }; - PIO107: gpio@fd334000 { + pio107: gpio@fd334000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 84758d76d064..1137bdfcca1c 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -9,6 +9,8 @@ #include "stih41x.dtsi" #include "stih416-clock.dtsi" #include "stih416-pinctrl.dtsi" + +#include #include #include / { @@ -236,5 +238,83 @@ resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>, <&softreset STIH416_KEYSCAN_SOFTRESET>; }; + + temp0 { + compatible = "st,stih416-sas-thermal"; + clock-names = "thermal"; + clocks = <&clockgen_c_vcc 14>; + + status = "okay"; + }; + + temp1@fdfe8000 { + compatible = "st,stih416-mpe-thermal"; + reg = <0xfdfe8000 0x10>; + clocks = <&clockgen_e 3>; + clock-names = "thermal"; + interrupts = ; + + status = "okay"; + }; + + mmc0: sdhci@fe81e000 { + compatible = "st,sdhci"; + status = "disabled"; + reg = <0xfe81e000 0x1000>; + interrupts = ; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0>; + clock-names = "mmc"; + clocks = <&clk_s_a1_ls 1>; + }; + + mmc1: sdhci@fe81f000 { + compatible = "st,sdhci"; + status = "disabled"; + reg = <0xfe81f000 0x1000>; + interrupts = ; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1>; + clock-names = "mmc"; + clocks = <&clk_s_a1_ls 8>; + }; + + miphy365x_phy: miphy365x@fe382000 { + compatible = "st,miphy365x-phy"; + st,syscfg = <&syscfg_rear>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + phy_port0: port@fe382000 { + #phy-cells = <1>; + reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>; + reg-names = "sata", "pcie", "syscfg"; + }; + + phy_port1: port@fe38a000 { + #phy-cells = <1>; + reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>; + reg-names = "sata", "pcie", "syscfg"; + }; + }; + + sata0: sata@fe380000 { + compatible = "st,sti-ahci"; + reg = <0xfe380000 0x1000>; + interrupts = ; + interrupt-names = "hostc"; + phys = <&phy_port0 MIPHY_TYPE_SATA>; + phy-names = "sata-phy"; + resets = <&powerdown STIH416_SATA0_POWERDOWN>, + <&softreset STIH416_SATA0_SOFTRESET>; + reset-names = "pwr-dwn", "sw-rst"; + clock-names = "ahci_clk"; + clocks = <&clk_s_a0_ls CLK_ICN_REG>; + + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi index b3dd6ca5c2ae..5f91f455f05b 100644 --- a/arch/arm/boot/dts/stih41x-b2000.dtsi +++ b/arch/arm/boot/dts/stih41x-b2000.dtsi @@ -35,7 +35,7 @@ fp_led { #gpio-cells = <1>; label = "Front Panel LED"; - gpios = <&PIO105 7>; + gpios = <&pio105 7>; linux,default-trigger = "heartbeat"; }; }; @@ -55,7 +55,7 @@ phy-mode = "mii"; pinctrl-0 = <&pinctrl_mii0>; - snps,reset-gpio = <&PIO106 2>; + snps,reset-gpio = <&pio106 2>; snps,reset-active-low; snps,reset-delays-us = <0 10000 10000>; }; @@ -65,7 +65,7 @@ phy-mode = "mii"; st,tx-retime-src = "txclk"; - snps,reset-gpio = <&PIO4 7>; + snps,reset-gpio = <&pio4 7>; snps,reset-active-low; snps,reset-delays-us = <0 10000 10000>; }; diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi index d8a84295c328..487d7d87dbef 100644 --- a/arch/arm/boot/dts/stih41x-b2020.dtsi +++ b/arch/arm/boot/dts/stih41x-b2020.dtsi @@ -32,11 +32,11 @@ red { #gpio-cells = <1>; label = "Front Panel LED"; - gpios = <&PIO4 1>; + gpios = <&pio4 1>; linux,default-trigger = "heartbeat"; }; green { - gpios = <&PIO4 7>; + gpios = <&pio4 7>; default-state = "off"; }; }; @@ -68,11 +68,15 @@ phy-mode = "rgmii-id"; max-speed = <1000>; st,tx-retime-src = "clk_125"; - snps,reset-gpio = <&PIO3 0>; + snps,reset-gpio = <&pio3 0>; snps,reset-active-low; snps,reset-delays-us = <0 10000 10000>; pinctrl-0 = <&pinctrl_rgmii1>; }; + + mmc0: sdhci@fe81e000 { + bus-width = <8>; + }; }; }; diff --git a/arch/arm/boot/dts/stih41x-b2020x.dtsi b/arch/arm/boot/dts/stih41x-b2020x.dtsi index df01c1211b32..f797a0607382 100644 --- a/arch/arm/boot/dts/stih41x-b2020x.dtsi +++ b/arch/arm/boot/dts/stih41x-b2020x.dtsi @@ -8,6 +8,10 @@ */ / { soc { + mmc0: sdhci@fe81e000 { + status = "okay"; + }; + spifsm: spifsm@fe902000 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 206379546244..dcc6c75553a4 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -187,7 +187,7 @@ /* ALS and Proximity sensor */ isl29028@44 { - compatible = "isil,isl29028"; + compatible = "isl,isl29028"; reg = <0x44>; interrupt-parent = <&gpio>; interrupts = ; diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig index 263ae3869e32..7d2ad30d9e70 100644 --- a/arch/arm/configs/nhk8815_defconfig +++ b/arch/arm/configs/nhk8815_defconfig @@ -20,7 +20,6 @@ CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_FPE_NWFPE=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -57,14 +56,12 @@ CONFIG_MTD_NAND_FSMC=y CONFIG_MTD_ONENAND=y CONFIG_MTD_ONENAND_VERIFY_WRITE=y CONFIG_MTD_ONENAND_GENERIC=y -CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y -CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y @@ -83,21 +80,21 @@ CONFIG_PPP_SYNC_TTY=m CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_STMPE=y # CONFIG_MOUSE_PS2 is not set # CONFIG_SERIO is not set # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_NOMADIK=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_GPIO=y -CONFIG_I2C_NOMADIK=y CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_STMPE=y # CONFIG_HWMON is not set +CONFIG_MFD_STMPE=y CONFIG_REGULATOR=y CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y # CONFIG_MMC_BLOCK_BOUNCE is not set CONFIG_MMC_ARMMMCI=y CONFIG_NEW_LEDS=y @@ -125,12 +122,12 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y +CONFIG_DEBUG_INFO=y # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_DEBUG_FS=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_PREEMPT is not set # CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_DES=y diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index 9116ca476d7c..9bda46f1fab7 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@ -144,6 +144,7 @@ static int __init cpu8815_mmcsd_init(void) device_initcall(cpu8815_mmcsd_init); static const char * cpu8815_board_compat[] = { + "st,nomadik-nhk-15", "calaosystems,usb-s8815", NULL, }; diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index cec9d6c6442c..2156f69fc282 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -139,8 +140,38 @@ static void __init omap3_sbc_t3530_legacy_init(void) omap_ads7846_init(1, 57, 0, NULL); } -static void __init omap3_igep0020_legacy_init(void) +struct ti_st_plat_data wilink_pdata = { + .nshutdown_gpio = 137, + .dev_name = "/dev/ttyO1", + .flow_cntrl = 1, + .baud_rate = 300000, +}; + +static struct platform_device wl18xx_device = { + .name = "kim", + .id = -1, + .dev = { + .platform_data = &wilink_pdata, + } +}; + +static struct platform_device btwilink_device = { + .name = "btwilink", + .id = -1, +}; + +static void __init omap3_igep0020_rev_f_legacy_init(void) +{ + legacy_init_wl12xx(0, 0, 177); + platform_device_register(&wl18xx_device); + platform_device_register(&btwilink_device); +} + +static void __init omap3_igep0030_rev_g_legacy_init(void) { + legacy_init_wl12xx(0, 0, 136); + platform_device_register(&wl18xx_device); + platform_device_register(&btwilink_device); } static void __init omap3_evm_legacy_init(void) @@ -390,7 +421,8 @@ static struct pdata_init pdata_quirks[] __initdata = { { "nokia,omap3-n900", nokia_n900_legacy_init, }, { "nokia,omap3-n9", hsmmc2_internal_input_clk, }, { "nokia,omap3-n950", hsmmc2_internal_input_clk, }, - { "isee,omap3-igep0020", omap3_igep0020_legacy_init, }, + { "isee,omap3-igep0020-rev-f", omap3_igep0020_rev_f_legacy_init, }, + { "isee,omap3-igep0030-rev-g", omap3_igep0030_rev_g_legacy_init, }, { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, { "ti,omap3-zoom3", omap3_zoom_legacy_init, }, { "ti,am3517-evm", am3517_evm_legacy_init, }, diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 9db2029aa632..565925f37dc5 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -1,6 +1,19 @@ menu "RealView platform type" depends on ARCH_REALVIEW +config REALVIEW_DT + bool "Support RealView(R) Device Tree based boot" + select ARM_GIC + select MFD_SYSCON + select POWER_RESET + select POWER_RESET_VERSATILE + select POWER_SUPPLY + select SOC_REALVIEW + select USE_OF + help + Include support for booting the ARM(R) RealView(R) evaluation + boards using a device tree machine description. + config MACH_REALVIEW_EB bool "Support RealView(R) Emulation Baseboard" select ARM_GIC diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile index 541fa4c109ef..e07fdf7ae8a7 100644 --- a/arch/arm/mach-realview/Makefile +++ b/arch/arm/mach-realview/Makefile @@ -3,6 +3,7 @@ # obj-y := core.o +obj-$(CONFIG_REALVIEW_DT) += realview-dt.o obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o diff --git a/arch/arm/mach-realview/realview-dt.c b/arch/arm/mach-realview/realview-dt.c new file mode 100644 index 000000000000..cc28b89dd48f --- /dev/null +++ b/arch/arm/mach-realview/realview-dt.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2014 Linaro Ltd. + * + * Author: Linus Walleij + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include "core.h" + +static const char *realview_dt_platform_compat[] __initconst = { + "arm,realview-eb", + "arm,realview-pb1176", + "arm,realview-pb11mp", + "arm,realview-pba8", + "arm,realview-pbx", + NULL, +}; + +DT_MACHINE_START(REALVIEW_DT, "ARM RealView Machine (Device Tree Support)") +#ifdef CONFIG_ZONE_DMA + .dma_zone_size = SZ_256M, +#endif + .dt_compat = realview_dt_platform_compat, + .l2c_aux_val = 0x0, + .l2c_aux_mask = ~0x0, +MACHINE_END diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c index a6503d8c77de..3b68370b03a0 100644 --- a/arch/arm/mach-shmobile/board-ape6evm-reference.c +++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include @@ -48,7 +44,6 @@ static void __init ape6evm_add_standard_devices(void) clk_put(parent); clk_put(mp); - r8a73a4_add_dt_devices(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c index b222f68d55b7..66f67816a844 100644 --- a/arch/arm/mach-shmobile/board-ape6evm.c +++ b/arch/arm/mach-shmobile/board-ape6evm.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index e70983534403..0e912aff53de 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -12,11 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * */ #include diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c index 79c47847f200..d649ade4a202 100644 --- a/arch/arm/mach-shmobile/board-bockw-reference.c +++ b/arch/arm/mach-shmobile/board-bockw-reference.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index 1cf2c75dacfb..f27b5a833bf0 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c index 46aa540133d6..451ba624ce6e 100644 --- a/arch/arm/mach-shmobile/board-koelsch-reference.c +++ b/arch/arm/mach-shmobile/board-koelsch-reference.c @@ -13,93 +13,17 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include #include #include -#include #include -#include "clock.h" #include "common.h" -#include "irqs.h" #include "r8a7791.h" #include "rcar-gen2.h" -/* DU */ -static struct rcar_du_encoder_data koelsch_du_encoders[] = { - { - .type = RCAR_DU_ENCODER_NONE, - .output = RCAR_DU_OUTPUT_LVDS0, - .connector.lvds.panel = { - .width_mm = 210, - .height_mm = 158, - .mode = { - .pixelclock = 65000000, - .hactive = 1024, - .hfront_porch = 20, - .hback_porch = 160, - .hsync_len = 136, - .vactive = 768, - .vfront_porch = 3, - .vback_porch = 29, - .vsync_len = 6, - }, - }, - }, -}; - -static struct rcar_du_platform_data koelsch_du_pdata = { - .encoders = koelsch_du_encoders, - .num_encoders = ARRAY_SIZE(koelsch_du_encoders), -}; - -static const struct resource du_resources[] __initconst = { - DEFINE_RES_MEM(0xfeb00000, 0x40000), - DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"), - DEFINE_RES_IRQ(gic_spi(256)), - DEFINE_RES_IRQ(gic_spi(268)), -}; - -static void __init koelsch_add_du_device(void) -{ - struct platform_device_info info = { - .name = "rcar-du-r8a7791", - .id = -1, - .res = du_resources, - .num_res = ARRAY_SIZE(du_resources), - .data = &koelsch_du_pdata, - .size_data = sizeof(koelsch_du_pdata), - .dma_mask = DMA_BIT_MASK(32), - }; - - platform_device_register_full(&info); -} - -/* - * This is a really crude hack to provide clkdev support to platform - * devices until they get moved to DT. - */ -static const struct clk_name clk_names[] __initconst = { - { "du0", "du.0", "rcar-du-r8a7791" }, - { "du1", "du.1", "rcar-du-r8a7791" }, - { "lvds0", "lvds.0", "rcar-du-r8a7791" }, -}; - -static void __init koelsch_add_standard_devices(void) -{ - shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - - koelsch_add_du_device(); -} - static const char * const koelsch_boards_compat_dt[] __initconst = { "renesas,koelsch", "renesas,koelsch-reference", @@ -110,7 +34,6 @@ DT_MACHINE_START(KOELSCH_DT, "koelsch") .smp = smp_ops(r8a7791_smp_ops), .init_early = shmobile_init_delay, .init_time = rcar_gen2_timer_init, - .init_machine = koelsch_add_standard_devices, .init_late = shmobile_init_late, .reserve = rcar_gen2_reserve, .dt_compat = koelsch_boards_compat_dt, diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c index 7111b5c1d67b..3a6a2766dc2b 100644 --- a/arch/arm/mach-shmobile/board-koelsch.c +++ b/arch/arm/mach-shmobile/board-koelsch.c @@ -14,10 +14,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c index d9cdf9a97e23..f2ef759b6e96 100644 --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c @@ -14,10 +14,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index 77e36fa0b142..7c9b63bdde9f 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c index bc4b48357dde..fa06bdba61df 100644 --- a/arch/arm/mach-shmobile/board-lager-reference.c +++ b/arch/arm/mach-shmobile/board-lager-reference.c @@ -12,100 +12,17 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include #include #include -#include #include -#include "clock.h" #include "common.h" -#include "irqs.h" #include "r8a7790.h" #include "rcar-gen2.h" -/* DU */ -static struct rcar_du_encoder_data lager_du_encoders[] = { - { - .type = RCAR_DU_ENCODER_VGA, - .output = RCAR_DU_OUTPUT_DPAD0, - }, { - .type = RCAR_DU_ENCODER_NONE, - .output = RCAR_DU_OUTPUT_LVDS1, - .connector.lvds.panel = { - .width_mm = 210, - .height_mm = 158, - .mode = { - .pixelclock = 65000000, - .hactive = 1024, - .hfront_porch = 20, - .hback_porch = 160, - .hsync_len = 136, - .vactive = 768, - .vfront_porch = 3, - .vback_porch = 29, - .vsync_len = 6, - }, - }, - }, -}; - -static struct rcar_du_platform_data lager_du_pdata = { - .encoders = lager_du_encoders, - .num_encoders = ARRAY_SIZE(lager_du_encoders), -}; - -static const struct resource du_resources[] __initconst = { - DEFINE_RES_MEM(0xfeb00000, 0x70000), - DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"), - DEFINE_RES_MEM_NAMED(0xfeb94000, 0x1c, "lvds.1"), - DEFINE_RES_IRQ(gic_spi(256)), - DEFINE_RES_IRQ(gic_spi(268)), - DEFINE_RES_IRQ(gic_spi(269)), -}; - -static void __init lager_add_du_device(void) -{ - struct platform_device_info info = { - .name = "rcar-du-r8a7790", - .id = -1, - .res = du_resources, - .num_res = ARRAY_SIZE(du_resources), - .data = &lager_du_pdata, - .size_data = sizeof(lager_du_pdata), - .dma_mask = DMA_BIT_MASK(32), - }; - - platform_device_register_full(&info); -} - -/* - * This is a really crude hack to provide clkdev support to platform - * devices until they get moved to DT. - */ -static const struct clk_name clk_names[] __initconst = { - { "du0", "du.0", "rcar-du-r8a7790" }, - { "du1", "du.1", "rcar-du-r8a7790" }, - { "du2", "du.2", "rcar-du-r8a7790" }, - { "lvds0", "lvds.0", "rcar-du-r8a7790" }, - { "lvds1", "lvds.1", "rcar-du-r8a7790" }, -}; - -static void __init lager_add_standard_devices(void) -{ - shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - - lager_add_du_device(); -} - static const char *lager_boards_compat_dt[] __initdata = { "renesas,lager", "renesas,lager-reference", @@ -116,7 +33,6 @@ DT_MACHINE_START(LAGER_DT, "lager") .smp = smp_ops(r8a7790_smp_ops), .init_early = shmobile_init_delay, .init_time = rcar_gen2_timer_init, - .init_machine = lager_add_standard_devices, .init_late = shmobile_init_late, .reserve = rcar_gen2_reserve, .dt_compat = lager_boards_compat_dt, diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index 571327b1c942..b47262afb240 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index ca5d34b92aa7..ed1087031c5d 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -16,10 +16,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c index 38d9cdd26587..f0757bbaff87 100644 --- a/arch/arm/mach-shmobile/board-marzen-reference.c +++ b/arch/arm/mach-shmobile/board-marzen-reference.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index ce33d7825c49..994dc7d86ae2 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index c2330ea1802c..1cf44dc6d718 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 0794f0426e70..969e85dad09b 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include #include diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index 67980a08a601..e8510c35558c 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -17,10 +17,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index c51f9db3f66f..fa8ab2cc9187 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include #include diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index 126ddafad526..c395ff194254 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c index 453b23129cfa..82143ca3bae9 100644 --- a/arch/arm/mach-shmobile/clock-r8a7791.c +++ b/arch/arm/mach-shmobile/clock-r8a7791.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 7071676145c4..3bc92f46060e 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include #include diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 02a6f45a0b9e..6b4c1f313cc9 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include #include diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c index 806f94038cc4..1f81ad747153 100644 --- a/arch/arm/mach-shmobile/clock.c +++ b/arch/arm/mach-shmobile/clock.c @@ -14,10 +14,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * */ #include #include diff --git a/arch/arm/mach-shmobile/console.c b/arch/arm/mach-shmobile/console.c index f2e79f2376e1..e329ccbd0a67 100644 --- a/arch/arm/mach-shmobile/console.c +++ b/arch/arm/mach-shmobile/console.c @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S index f45dde701d7b..69df8bfac167 100644 --- a/arch/arm/mach-shmobile/headsmp-scu.S +++ b/arch/arm/mach-shmobile/headsmp-scu.S @@ -12,11 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA */ #include diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index e2af00b1bd9d..1ccf49cb485f 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c index 44457a94897b..9e3618028acc 100644 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/arch/arm/mach-shmobile/intc-sh73a0.c @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/r8a73a4.h b/arch/arm/mach-shmobile/r8a73a4.h index 5fafd6fcedf7..70dcd847a86e 100644 --- a/arch/arm/mach-shmobile/r8a73a4.h +++ b/arch/arm/mach-shmobile/r8a73a4.h @@ -11,7 +11,6 @@ enum { }; void r8a73a4_add_standard_devices(void); -void r8a73a4_add_dt_devices(void); void r8a73a4_clock_init(void); void r8a73a4_pinmux_init(void); diff --git a/arch/arm/mach-shmobile/r8a7740.h b/arch/arm/mach-shmobile/r8a7740.h index f369b4b0863d..ca7805ad7ea3 100644 --- a/arch/arm/mach-shmobile/r8a7740.h +++ b/arch/arm/mach-shmobile/r8a7740.h @@ -10,10 +10,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef __ASM_R8A7740_H__ diff --git a/arch/arm/mach-shmobile/r8a7778.h b/arch/arm/mach-shmobile/r8a7778.h index f4076a50e970..9086dfc6746a 100644 --- a/arch/arm/mach-shmobile/r8a7778.h +++ b/arch/arm/mach-shmobile/r8a7778.h @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef __ASM_R8A7778_H__ #define __ASM_R8A7778_H__ diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index b06a9e8f59a5..aad97be9cbe1 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c index 4122104359f9..171174777b6f 100644 --- a/arch/arm/mach-shmobile/setup-r7s72100.c +++ b/arch/arm/mach-shmobile/setup-r7s72100.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index 53f40b70680d..c27682291cbf 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include @@ -180,18 +176,13 @@ static struct resource cmt1_resources[] = { DEFINE_RES_IRQ(gic_spi(120)), }; -#define r8a7790_register_cmt(idx) \ +#define r8a73a4_register_cmt(idx) \ platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \ idx, cmt##idx##_resources, \ ARRAY_SIZE(cmt##idx##_resources), \ &cmt##idx##_platform_data, \ sizeof(struct sh_timer_config)) -void __init r8a73a4_add_dt_devices(void) -{ - r8a7790_register_cmt(1); -} - /* DMA */ static const struct sh_dmae_slave_config dma_slaves[] = { { @@ -282,7 +273,7 @@ static struct resource dma_resources[] = { void __init r8a73a4_add_standard_devices(void) { - r8a73a4_add_dt_devices(); + r8a73a4_register_cmt(1); r8a73a4_register_scif(0); r8a73a4_register_scif(1); r8a73a4_register_scif(2); diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 8894e1b7ab0e..fe15dd26d15d 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 85fe016d6a87..7c7223de1e9c 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include @@ -292,8 +288,6 @@ void __init r8a7778_add_dt_devices(void) l2x0_init(base, 0x00400000, 0xc20f0fff); } #endif - - r8a7778_register_tmu(0); } /* HPB-DMA */ @@ -501,6 +495,7 @@ static void __init r8a7778_register_hpb_dmae(void) void __init r8a7778_add_standard_devices(void) { r8a7778_add_dt_devices(); + r8a7778_register_tmu(0); r8a7778_register_scif(0); r8a7778_register_scif(1); r8a7778_register_scif(2); diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 136078ab9407..d08e75cceaab 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index 877fdeb985d0..ec7d97dca4de 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c index 35d78639244f..d930925f8f1a 100644 --- a/arch/arm/mach-shmobile/setup-r8a7791.c +++ b/arch/arm/mach-shmobile/setup-r8a7791.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 42d5b4308923..a669377aea57 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index d646c8d12423..e81c38538e13 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index b7bd8e509668..1c8172dc2c6c 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S index 9782862899e8..146b8de16432 100644 --- a/arch/arm/mach-shmobile/sleep-sh7372.S +++ b/arch/arm/mach-shmobile/sleep-sh7372.S @@ -22,11 +22,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA */ #include diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 6ff1df1df9a7..baff3b5efed8 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 3100e355c3fd..3f761f839043 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 22d8f87b23e9..c16dbfe9836c 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c index 87c6be1e79bd..1081b763e0f3 100644 --- a/arch/arm/mach-shmobile/timer.c +++ b/arch/arm/mach-shmobile/timer.c @@ -12,11 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * */ #include #include diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index 878e9ec97d0f..8825bc9e2553 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -42,4 +42,14 @@ config SOC_STIH416 and other digital audio/video applications using Flattened Device Trees. +config SOC_STIH407 + bool "STiH407 STMicroelectronics Consumer Electronics family" + default y + select STIH407_RESET + help + This enables support for STMicroelectronics Digital Consumer + Electronics family StiH407 parts, targetted at set-top-box + and other digital audio/video applications using Flattened Device + Trees. + endif diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index de469821bc1b..8b6fb0f11007 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -107,6 +107,13 @@ config AT_HDMAC help Support the Atmel AHB DMA controller. +config AT_XDMAC + tristate "Atmel XDMA support" + depends on ARCH_AT91 + select DMA_ENGINE + help + Support the Atmel XDMA controller. + config FSL_DMA tristate "Freescale Elo series DMA support" depends on FSL_SOC diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index cb626c179911..2022b5451377 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ obj-$(CONFIG_MV_XOR) += mv_xor.o obj-$(CONFIG_DW_DMAC_CORE) += dw/ obj-$(CONFIG_AT_HDMAC) += at_hdmac.o +obj-$(CONFIG_AT_XDMAC) += at_xdmac.o obj-$(CONFIG_MX3_IPU) += ipu/ obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o obj-$(CONFIG_SH_DMAE_BASE) += sh/ diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c new file mode 100644 index 000000000000..b60d77a22df6 --- /dev/null +++ b/drivers/dma/at_xdmac.c @@ -0,0 +1,1524 @@ +/* + * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems) + * + * Copyright (C) 2014 Atmel Corporation + * + * Author: Ludovic Desroches + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dmaengine.h" + +/* Global registers */ +#define AT_XDMAC_GTYPE 0x00 /* Global Type Register */ +#define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */ +#define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */ +#define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */ +#define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */ +#define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */ +#define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */ +#define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */ +#define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */ +#define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */ +#define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */ +#define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */ +#define AT_XDMAC_GS 0x24 /* Global Channel Status Register */ +#define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */ +#define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */ +#define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */ +#define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */ +#define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */ +#define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */ +#define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */ +#define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */ + +/* Channel relative registers offsets */ +#define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */ +#define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */ +#define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */ +#define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */ +#define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */ +#define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */ +#define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */ +#define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */ +#define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */ +#define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */ +#define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */ +#define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */ +#define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */ +#define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */ +#define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */ +#define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */ +#define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */ +#define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */ +#define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */ +#define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */ +#define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */ +#define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */ +#define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */ +#define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */ +#define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */ +#define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */ +#define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */ +#define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */ +#define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */ +#define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */ +#define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */ +#define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */ +#define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */ +#define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */ +#define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */ +#define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */ +#define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */ +#define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */ +#define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */ +#define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */ +#define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */ +#define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */ +#define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */ +#define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */ +#define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */ +#define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */ +#define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */ +#define AT_XDMAC_CC 0x28 /* Channel Configuration Register */ +#define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */ +#define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */ +#define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */ +#define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1) +#define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1) +#define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1) +#define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1) +#define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1) +#define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */ +#define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4) +#define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4) +#define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */ +#define AT_XDMAC_CC_PROT_SEC (0x0 << 5) +#define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5) +#define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */ +#define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6) +#define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6) +#define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */ +#define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7) +#define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7) +#define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */ +#define AT_XDMAC_CC_DWIDTH_OFFSET 11 +#define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET) +#define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */ +#define AT_XDMAC_CC_DWIDTH_BYTE 0x0 +#define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1 +#define AT_XDMAC_CC_DWIDTH_WORD 0x2 +#define AT_XDMAC_CC_DWIDTH_DWORD 0x3 +#define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */ +#define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */ +#define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */ +#define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16) +#define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16) +#define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16) +#define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16) +#define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */ +#define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18) +#define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18) +#define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18) +#define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18) +#define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */ +#define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21) +#define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21) +#define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */ +#define AT_XDMAC_CC_RDIP_DONE (0x0 << 22) +#define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22) +#define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */ +#define AT_XDMAC_CC_WRIP_DONE (0x0 << 23) +#define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23) +#define AT_XDMAC_CC_PERID(i) (0x7f & (h) << 24) /* Channel Peripheral Identifier */ +#define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */ +#define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */ +#define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */ + +#define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */ + +/* Microblock control members */ +#define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */ +#define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */ +#define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */ +#define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */ +#define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */ +#define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */ +#define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */ +#define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */ + +#define AT_XDMAC_MAX_CHAN 0x20 + +enum atc_status { + AT_XDMAC_CHAN_IS_CYCLIC = 0, + AT_XDMAC_CHAN_IS_PAUSED, +}; + +/* ----- Channels ----- */ +struct at_xdmac_chan { + struct dma_chan chan; + void __iomem *ch_regs; + u32 mask; /* Channel Mask */ + u32 cfg[3]; /* Channel Configuration Register */ + #define AT_XDMAC_CUR_CFG 0 /* Current channel conf */ + #define AT_XDMAC_DEV_TO_MEM_CFG 1 /* Predifined dev to mem channel conf */ + #define AT_XDMAC_MEM_TO_DEV_CFG 2 /* Predifined mem to dev channel conf */ + u8 perid; /* Peripheral ID */ + u8 perif; /* Peripheral Interface */ + u8 memif; /* Memory Interface */ + u32 per_src_addr; + u32 per_dst_addr; + u32 save_cim; + u32 save_cnda; + u32 save_cndc; + unsigned long status; + struct tasklet_struct tasklet; + + spinlock_t lock; + + struct list_head xfers_list; + struct list_head free_descs_list; +}; + + +/* ----- Controller ----- */ +struct at_xdmac { + struct dma_device dma; + void __iomem *regs; + int irq; + struct clk *clk; + u32 save_gim; + u32 save_gs; + struct dma_pool *at_xdmac_desc_pool; + struct at_xdmac_chan chan[0]; +}; + + +/* ----- Descriptors ----- */ + +/* Linked List Descriptor */ +struct at_xdmac_lld { + dma_addr_t mbr_nda; /* Next Descriptor Member */ + u32 mbr_ubc; /* Microblock Control Member */ + dma_addr_t mbr_sa; /* Source Address Member */ + dma_addr_t mbr_da; /* Destination Address Member */ + u32 mbr_cfg; /* Configuration Register */ +}; + + +struct at_xdmac_desc { + struct at_xdmac_lld lld; + enum dma_transfer_direction direction; + struct dma_async_tx_descriptor tx_dma_desc; + struct list_head desc_node; + /* Following members are only used by the first descriptor */ + bool active_xfer; + unsigned int xfer_size; + struct list_head descs_list; + struct list_head xfer_node; +}; + +static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb) +{ + return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40); +} + +#define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg)) +#define at_xdmac_write(atxdmac, reg, value) \ + writel_relaxed((value), (atxdmac)->regs + (reg)) + +#define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg)) +#define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg)) + +static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan) +{ + return container_of(dchan, struct at_xdmac_chan, chan); +} + +static struct device *chan2dev(struct dma_chan *chan) +{ + return &chan->dev->device; +} + +static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev) +{ + return container_of(ddev, struct at_xdmac, dma); +} + +static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd) +{ + return container_of(txd, struct at_xdmac_desc, tx_dma_desc); +} + +static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan) +{ + return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status); +} + +static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan) +{ + return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); +} + +static inline int at_xdmac_csize(u32 maxburst) +{ + int csize; + + csize = ffs(maxburst) - 1; + if (csize > 4) + csize = -EINVAL; + + return csize; +}; + +static inline u8 at_xdmac_get_dwidth(u32 cfg) +{ + return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET; +}; + +static unsigned int init_nr_desc_per_channel = 64; +module_param(init_nr_desc_per_channel, uint, 0644); +MODULE_PARM_DESC(init_nr_desc_per_channel, + "initial descriptors per channel (default: 64)"); + + +static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan) +{ + return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask; +} + +static void at_xdmac_off(struct at_xdmac *atxdmac) +{ + at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L); + + /* Wait that all chans are disabled. */ + while (at_xdmac_read(atxdmac, AT_XDMAC_GS)) + cpu_relax(); + + at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L); +} + +/* Call with lock hold. */ +static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan, + struct at_xdmac_desc *first) +{ + struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); + u32 reg; + + dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first); + + if (at_xdmac_chan_is_enabled(atchan)) + return; + + /* Set transfer as active to not try to start it again. */ + first->active_xfer = true; + + /* Tell xdmac where to get the first descriptor. */ + reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys) + | AT_XDMAC_CNDA_NDAIF(atchan->memif); + at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg); + + /* + * When doing memory to memory transfer we need to use the next + * descriptor view 2 since some fields of the configuration register + * depend on transfer size and src/dest addresses. + */ + if (is_slave_direction(first->direction)) { + reg = AT_XDMAC_CNDC_NDVIEW_NDV1; + if (first->direction == DMA_MEM_TO_DEV) + atchan->cfg[AT_XDMAC_CUR_CFG] = + atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG]; + else + atchan->cfg[AT_XDMAC_CUR_CFG] = + atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG]; + at_xdmac_chan_write(atchan, AT_XDMAC_CC, + atchan->cfg[AT_XDMAC_CUR_CFG]); + } else { + /* + * No need to write AT_XDMAC_CC reg, it will be done when the + * descriptor is fecthed. + */ + reg = AT_XDMAC_CNDC_NDVIEW_NDV2; + } + + reg |= AT_XDMAC_CNDC_NDDUP + | AT_XDMAC_CNDC_NDSUP + | AT_XDMAC_CNDC_NDE; + at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg); + + dev_vdbg(chan2dev(&atchan->chan), + "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", + __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC), + at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), + at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), + at_xdmac_chan_read(atchan, AT_XDMAC_CSA), + at_xdmac_chan_read(atchan, AT_XDMAC_CDA), + at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); + + at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff); + reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE | AT_XDMAC_CIE_ROIE; + /* + * There is no end of list when doing cyclic dma, we need to get + * an interrupt after each periods. + */ + if (at_xdmac_chan_is_cyclic(atchan)) + at_xdmac_chan_write(atchan, AT_XDMAC_CIE, + reg | AT_XDMAC_CIE_BIE); + else + at_xdmac_chan_write(atchan, AT_XDMAC_CIE, + reg | AT_XDMAC_CIE_LIE); + at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask); + dev_vdbg(chan2dev(&atchan->chan), + "%s: enable channel (0x%08x)\n", __func__, atchan->mask); + wmb(); + at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); + + dev_vdbg(chan2dev(&atchan->chan), + "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", + __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC), + at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), + at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), + at_xdmac_chan_read(atchan, AT_XDMAC_CSA), + at_xdmac_chan_read(atchan, AT_XDMAC_CDA), + at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); + +} + +static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct at_xdmac_desc *desc = txd_to_at_desc(tx); + struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan); + dma_cookie_t cookie; + + spin_lock_bh(&atchan->lock); + cookie = dma_cookie_assign(tx); + + dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n", + __func__, atchan, desc); + list_add_tail(&desc->xfer_node, &atchan->xfers_list); + if (list_is_singular(&atchan->xfers_list)) + at_xdmac_start_xfer(atchan, desc); + + spin_unlock_bh(&atchan->lock); + return cookie; +} + +static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan, + gfp_t gfp_flags) +{ + struct at_xdmac_desc *desc; + struct at_xdmac *atxdmac = to_at_xdmac(chan->device); + dma_addr_t phys; + + desc = dma_pool_alloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys); + if (desc) { + memset(desc, 0, sizeof(*desc)); + INIT_LIST_HEAD(&desc->descs_list); + dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan); + desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit; + desc->tx_dma_desc.phys = phys; + } + + return desc; +} + +/* Call must be protected by lock. */ +static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan) +{ + struct at_xdmac_desc *desc; + + if (list_empty(&atchan->free_descs_list)) { + desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT); + } else { + desc = list_first_entry(&atchan->free_descs_list, + struct at_xdmac_desc, desc_node); + list_del(&desc->desc_node); + desc->active_xfer = false; + } + + return desc; +} + +static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec, + struct of_dma *of_dma) +{ + struct at_xdmac *atxdmac = of_dma->of_dma_data; + struct at_xdmac_chan *atchan; + struct dma_chan *chan; + struct device *dev = atxdmac->dma.dev; + + if (dma_spec->args_count != 1) { + dev_err(dev, "dma phandler args: bad number of args\n"); + return NULL; + } + + chan = dma_get_any_slave_channel(&atxdmac->dma); + if (!chan) { + dev_err(dev, "can't get a dma channel\n"); + return NULL; + } + + atchan = to_at_xdmac_chan(chan); + atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]); + atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]); + atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]); + dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n", + atchan->memif, atchan->perif, atchan->perid); + + return chan; +} + +static int at_xdmac_set_slave_config(struct dma_chan *chan, + struct dma_slave_config *sconfig) +{ + struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); + u8 dwidth; + int csize; + + atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] = + AT91_XDMAC_DT_PERID(atchan->perid) + | AT_XDMAC_CC_DAM_INCREMENTED_AM + | AT_XDMAC_CC_SAM_FIXED_AM + | AT_XDMAC_CC_DIF(atchan->memif) + | AT_XDMAC_CC_SIF(atchan->perif) + | AT_XDMAC_CC_SWREQ_HWR_CONNECTED + | AT_XDMAC_CC_DSYNC_PER2MEM + | AT_XDMAC_CC_MBSIZE_SIXTEEN + | AT_XDMAC_CC_TYPE_PER_TRAN; + csize = at_xdmac_csize(sconfig->src_maxburst); + if (csize < 0) { + dev_err(chan2dev(chan), "invalid src maxburst value\n"); + return -EINVAL; + } + atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] |= AT_XDMAC_CC_CSIZE(csize); + dwidth = ffs(sconfig->src_addr_width) - 1; + atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] |= AT_XDMAC_CC_DWIDTH(dwidth); + + + atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] = + AT91_XDMAC_DT_PERID(atchan->perid) + | AT_XDMAC_CC_DAM_FIXED_AM + | AT_XDMAC_CC_SAM_INCREMENTED_AM + | AT_XDMAC_CC_DIF(atchan->perif) + | AT_XDMAC_CC_SIF(atchan->memif) + | AT_XDMAC_CC_SWREQ_HWR_CONNECTED + | AT_XDMAC_CC_DSYNC_MEM2PER + | AT_XDMAC_CC_MBSIZE_SIXTEEN + | AT_XDMAC_CC_TYPE_PER_TRAN; + csize = at_xdmac_csize(sconfig->dst_maxburst); + if (csize < 0) { + dev_err(chan2dev(chan), "invalid src maxburst value\n"); + return -EINVAL; + } + atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] |= AT_XDMAC_CC_CSIZE(csize); + dwidth = ffs(sconfig->dst_addr_width) - 1; + atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] |= AT_XDMAC_CC_DWIDTH(dwidth); + + /* Src and dst addr are needed to configure the link list descriptor. */ + atchan->per_src_addr = sconfig->src_addr; + atchan->per_dst_addr = sconfig->dst_addr; + + dev_dbg(chan2dev(chan), + "%s: cfg[dev2mem]=0x%08x, cfg[mem2dev]=0x%08x, per_src_addr=0x%08x, per_dst_addr=0x%08x\n", + __func__, atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG], + atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG], + atchan->per_src_addr, atchan->per_dst_addr); + + return 0; +} + +static struct dma_async_tx_descriptor * +at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); + struct at_xdmac_desc *first = NULL, *prev = NULL; + struct scatterlist *sg; + int i; + u32 cfg; + unsigned int xfer_size = 0; + + if (!sgl) + return NULL; + + if (!is_slave_direction(direction)) { + dev_err(chan2dev(chan), "invalid DMA direction\n"); + return NULL; + } + + dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n", + __func__, sg_len, + direction == DMA_MEM_TO_DEV ? "to device" : "from device", + flags); + + /* Protect dma_sconfig field that can be modified by set_slave_conf. */ + spin_lock_bh(&atchan->lock); + + /* Prepare descriptors. */ + for_each_sg(sgl, sg, sg_len, i) { + struct at_xdmac_desc *desc = NULL; + u32 len, mem; + + len = sg_dma_len(sg); + mem = sg_dma_address(sg); + if (unlikely(!len)) { + dev_err(chan2dev(chan), "sg data length is zero\n"); + spin_unlock_bh(&atchan->lock); + return NULL; + } + dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n", + __func__, i, len, mem); + + desc = at_xdmac_get_desc(atchan); + if (!desc) { + dev_err(chan2dev(chan), "can't get descriptor\n"); + if (first) + list_splice_init(&first->descs_list, &atchan->free_descs_list); + spin_unlock_bh(&atchan->lock); + return NULL; + } + + /* Linked list descriptor setup. */ + if (direction == DMA_DEV_TO_MEM) { + desc->lld.mbr_sa = atchan->per_src_addr; + desc->lld.mbr_da = mem; + cfg = atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG]; + } else { + desc->lld.mbr_sa = mem; + desc->lld.mbr_da = atchan->per_dst_addr; + cfg = atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG]; + } + desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1 /* next descriptor view */ + | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */ + | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */ + | (i == sg_len - 1 ? 0 : AT_XDMAC_MBR_UBC_NDE) /* descriptor fetch */ + | len / (1 << at_xdmac_get_dwidth(cfg)); /* microblock length */ + dev_dbg(chan2dev(chan), + "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", + __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); + + /* Chain lld. */ + if (prev) { + prev->lld.mbr_nda = desc->tx_dma_desc.phys; + dev_dbg(chan2dev(chan), + "%s: chain lld: prev=0x%p, mbr_nda=%pad\n", + __func__, prev, &prev->lld.mbr_nda); + } + + prev = desc; + if (!first) + first = desc; + + dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", + __func__, desc, first); + list_add_tail(&desc->desc_node, &first->descs_list); + xfer_size += len; + } + + spin_unlock_bh(&atchan->lock); + + first->tx_dma_desc.flags = flags; + first->xfer_size = xfer_size; + first->direction = direction; + + return &first->tx_dma_desc; +} + +static struct dma_async_tx_descriptor * +at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction direction, + unsigned long flags) +{ + struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); + struct at_xdmac_desc *first = NULL, *prev = NULL; + unsigned int periods = buf_len / period_len; + int i; + u32 cfg; + + dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n", + __func__, &buf_addr, buf_len, period_len, + direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags); + + if (!is_slave_direction(direction)) { + dev_err(chan2dev(chan), "invalid DMA direction\n"); + return NULL; + } + + if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) { + dev_err(chan2dev(chan), "channel currently used\n"); + return NULL; + } + + for (i = 0; i < periods; i++) { + struct at_xdmac_desc *desc = NULL; + + spin_lock_bh(&atchan->lock); + desc = at_xdmac_get_desc(atchan); + if (!desc) { + dev_err(chan2dev(chan), "can't get descriptor\n"); + if (first) + list_splice_init(&first->descs_list, &atchan->free_descs_list); + spin_unlock_bh(&atchan->lock); + return NULL; + } + spin_unlock_bh(&atchan->lock); + dev_dbg(chan2dev(chan), + "%s: desc=0x%p, tx_dma_desc.phys=%pad\n", + __func__, desc, &desc->tx_dma_desc.phys); + + if (direction == DMA_DEV_TO_MEM) { + desc->lld.mbr_sa = atchan->per_src_addr; + desc->lld.mbr_da = buf_addr + i * period_len; + cfg = atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG]; + } else { + desc->lld.mbr_sa = buf_addr + i * period_len; + desc->lld.mbr_da = atchan->per_dst_addr; + cfg = atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG]; + } + desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1 + | AT_XDMAC_MBR_UBC_NDEN + | AT_XDMAC_MBR_UBC_NSEN + | AT_XDMAC_MBR_UBC_NDE + | period_len >> at_xdmac_get_dwidth(cfg); + + dev_dbg(chan2dev(chan), + "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", + __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); + + /* Chain lld. */ + if (prev) { + prev->lld.mbr_nda = desc->tx_dma_desc.phys; + dev_dbg(chan2dev(chan), + "%s: chain lld: prev=0x%p, mbr_nda=%pad\n", + __func__, prev, &prev->lld.mbr_nda); + } + + prev = desc; + if (!first) + first = desc; + + dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", + __func__, desc, first); + list_add_tail(&desc->desc_node, &first->descs_list); + } + + prev->lld.mbr_nda = first->tx_dma_desc.phys; + dev_dbg(chan2dev(chan), + "%s: chain lld: prev=0x%p, mbr_nda=%pad\n", + __func__, prev, &prev->lld.mbr_nda); + first->tx_dma_desc.flags = flags; + first->xfer_size = buf_len; + first->direction = direction; + + return &first->tx_dma_desc; +} + +static struct dma_async_tx_descriptor * +at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, + size_t len, unsigned long flags) +{ + struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); + struct at_xdmac_desc *first = NULL, *prev = NULL; + size_t remaining_size = len, xfer_size = 0, ublen; + dma_addr_t src_addr = src, dst_addr = dest; + u32 dwidth; + /* + * WARNING: We don't know the direction, it involves we can't + * dynamically set the source and dest interface so we have to use the + * same one. Only interface 0 allows EBI access. Hopefully we can + * access DDR through both ports (at least on SAMA5D4x), so we can use + * the same interface for source and dest, that solves the fact we + * don't know the direction. + */ + u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM + | AT_XDMAC_CC_SAM_INCREMENTED_AM + | AT_XDMAC_CC_DIF(0) + | AT_XDMAC_CC_SIF(0) + | AT_XDMAC_CC_MBSIZE_SIXTEEN + | AT_XDMAC_CC_TYPE_MEM_TRAN; + + dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n", + __func__, &src, &dest, len, flags); + + if (unlikely(!len)) + return NULL; + + /* + * Check address alignment to select the greater data width we can use. + * Some XDMAC implementations don't provide dword transfer, in this + * case selecting dword has the same behavior as selecting word transfers. + */ + if (!((src_addr | dst_addr) & 7)) { + dwidth = AT_XDMAC_CC_DWIDTH_DWORD; + dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__); + } else if (!((src_addr | dst_addr) & 3)) { + dwidth = AT_XDMAC_CC_DWIDTH_WORD; + dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__); + } else if (!((src_addr | dst_addr) & 1)) { + dwidth = AT_XDMAC_CC_DWIDTH_HALFWORD; + dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__); + } else { + dwidth = AT_XDMAC_CC_DWIDTH_BYTE; + dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__); + } + + /* Prepare descriptors. */ + while (remaining_size) { + struct at_xdmac_desc *desc = NULL; + + dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size); + + spin_lock_bh(&atchan->lock); + desc = at_xdmac_get_desc(atchan); + spin_unlock_bh(&atchan->lock); + if (!desc) { + dev_err(chan2dev(chan), "can't get descriptor\n"); + if (first) + list_splice_init(&first->descs_list, &atchan->free_descs_list); + return NULL; + } + + /* Update src and dest addresses. */ + src_addr += xfer_size; + dst_addr += xfer_size; + + if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth) + xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth; + else + xfer_size = remaining_size; + + dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size); + + /* Check remaining length and change data width if needed. */ + if (!((src_addr | dst_addr | xfer_size) & 7)) { + dwidth = AT_XDMAC_CC_DWIDTH_DWORD; + dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__); + } else if (!((src_addr | dst_addr | xfer_size) & 3)) { + dwidth = AT_XDMAC_CC_DWIDTH_WORD; + dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__); + } else if (!((src_addr | dst_addr | xfer_size) & 1)) { + dwidth = AT_XDMAC_CC_DWIDTH_HALFWORD; + dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__); + } else if ((src_addr | dst_addr | xfer_size) & 1) { + dwidth = AT_XDMAC_CC_DWIDTH_BYTE; + dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__); + } + chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth); + + ublen = xfer_size >> dwidth; + remaining_size -= xfer_size; + + desc->lld.mbr_sa = src_addr; + desc->lld.mbr_da = dst_addr; + desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 + | AT_XDMAC_MBR_UBC_NDEN + | AT_XDMAC_MBR_UBC_NSEN + | (remaining_size ? AT_XDMAC_MBR_UBC_NDE : 0) + | ublen; + desc->lld.mbr_cfg = chan_cc; + + dev_dbg(chan2dev(chan), + "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", + __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg); + + /* Chain lld. */ + if (prev) { + prev->lld.mbr_nda = desc->tx_dma_desc.phys; + dev_dbg(chan2dev(chan), + "%s: chain lld: prev=0x%p, mbr_nda=0x%08x\n", + __func__, prev, prev->lld.mbr_nda); + } + + prev = desc; + if (!first) + first = desc; + + dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", + __func__, desc, first); + list_add_tail(&desc->desc_node, &first->descs_list); + } + + first->tx_dma_desc.flags = flags; + first->xfer_size = len; + + return &first->tx_dma_desc; +} + +static enum dma_status +at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); + struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); + struct at_xdmac_desc *desc, *_desc; + struct list_head *descs_list; + enum dma_status ret; + int residue; + u32 cur_nda, mask, value; + u8 dwidth = at_xdmac_get_dwidth(atchan->cfg[AT_XDMAC_CUR_CFG]); + + ret = dma_cookie_status(chan, cookie, txstate); + if (ret == DMA_COMPLETE) + return ret; + + if (!txstate) + return ret; + + spin_lock_bh(&atchan->lock); + + desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node); + + /* + * If the transfer has not been started yet, don't need to compute the + * residue, it's the transfer length. + */ + if (!desc->active_xfer) { + dma_set_residue(txstate, desc->xfer_size); + spin_unlock_bh(&atchan->lock); + return ret; + } + + residue = desc->xfer_size; + /* + * Flush FIFO: only relevant when the transfer is source peripheral + * synchronized. + */ + mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC; + value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM; + if ((atchan->cfg[AT_XDMAC_CUR_CFG] & mask) == value) { + at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); + while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) + cpu_relax(); + } + + cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc; + /* + * Remove size of all microblocks already transferred and the current + * one. Then add the remaining size to transfer of the current + * microblock. + */ + descs_list = &desc->descs_list; + list_for_each_entry_safe(desc, _desc, descs_list, desc_node) { + residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth; + if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda) + break; + } + residue += at_xdmac_chan_read(atchan, AT_XDMAC_CUBC) << dwidth; + + spin_unlock_bh(&atchan->lock); + + dma_set_residue(txstate, residue); + + dev_dbg(chan2dev(chan), + "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n", + __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue); + + return ret; +} + +/* Call must be protected by lock. */ +static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan, + struct at_xdmac_desc *desc) +{ + dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); + + /* + * Remove the transfer from the transfer list then move the transfer + * descriptors into the free descriptors list. + */ + list_del(&desc->xfer_node); + list_splice_init(&desc->descs_list, &atchan->free_descs_list); +} + +static void at_xdmac_advance_work(struct at_xdmac_chan *atchan) +{ + struct at_xdmac_desc *desc; + + spin_lock_bh(&atchan->lock); + + /* + * If channel is enabled, do nothing, advance_work will be triggered + * after the interruption. + */ + if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) { + desc = list_first_entry(&atchan->xfers_list, + struct at_xdmac_desc, + xfer_node); + dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); + if (!desc->active_xfer) + at_xdmac_start_xfer(atchan, desc); + } + + spin_unlock_bh(&atchan->lock); +} + +static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan) +{ + struct at_xdmac_desc *desc; + struct dma_async_tx_descriptor *txd; + + desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node); + txd = &desc->tx_dma_desc; + + if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT)) + txd->callback(txd->callback_param); +} + +static void at_xdmac_tasklet(unsigned long data) +{ + struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data; + struct at_xdmac_desc *desc; + u32 error_mask; + + dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08lx\n", + __func__, atchan->status); + + error_mask = AT_XDMAC_CIS_RBEIS + | AT_XDMAC_CIS_WBEIS + | AT_XDMAC_CIS_ROIS; + + if (at_xdmac_chan_is_cyclic(atchan)) { + at_xdmac_handle_cyclic(atchan); + } else if ((atchan->status & AT_XDMAC_CIS_LIS) + || (atchan->status & error_mask)) { + struct dma_async_tx_descriptor *txd; + + if (atchan->status & AT_XDMAC_CIS_RBEIS) + dev_err(chan2dev(&atchan->chan), "read bus error!!!"); + if (atchan->status & AT_XDMAC_CIS_WBEIS) + dev_err(chan2dev(&atchan->chan), "write bus error!!!"); + if (atchan->status & AT_XDMAC_CIS_ROIS) + dev_err(chan2dev(&atchan->chan), "request overflow error!!!"); + + spin_lock_bh(&atchan->lock); + desc = list_first_entry(&atchan->xfers_list, + struct at_xdmac_desc, + xfer_node); + dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); + BUG_ON(!desc->active_xfer); + + txd = &desc->tx_dma_desc; + + at_xdmac_remove_xfer(atchan, desc); + spin_unlock_bh(&atchan->lock); + + if (!at_xdmac_chan_is_cyclic(atchan)) { + dma_cookie_complete(txd); + if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT)) + txd->callback(txd->callback_param); + } + + dma_run_dependencies(txd); + + at_xdmac_advance_work(atchan); + } +} + +static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id) +{ + struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id; + struct at_xdmac_chan *atchan; + u32 imr, status, pending; + u32 chan_imr, chan_status; + int i, ret = IRQ_NONE; + + do { + imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM); + status = at_xdmac_read(atxdmac, AT_XDMAC_GIS); + pending = status & imr; + + dev_vdbg(atxdmac->dma.dev, + "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n", + __func__, status, imr, pending); + + if (!pending) + break; + + /* We have to find which channel has generated the interrupt. */ + for (i = 0; i < atxdmac->dma.chancnt; i++) { + if (!((1 << i) & pending)) + continue; + + atchan = &atxdmac->chan[i]; + chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM); + chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS); + atchan->status = chan_status & chan_imr; + dev_vdbg(atxdmac->dma.dev, + "%s: chan%d: imr=0x%x, status=0x%x\n", + __func__, i, chan_imr, chan_status); + dev_vdbg(chan2dev(&atchan->chan), + "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", + __func__, + at_xdmac_chan_read(atchan, AT_XDMAC_CC), + at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), + at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), + at_xdmac_chan_read(atchan, AT_XDMAC_CSA), + at_xdmac_chan_read(atchan, AT_XDMAC_CDA), + at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); + + if (atchan->status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS)) + at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); + + tasklet_schedule(&atchan->tasklet); + ret = IRQ_HANDLED; + } + + } while (pending); + + return ret; +} + +static void at_xdmac_issue_pending(struct dma_chan *chan) +{ + struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); + + dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__); + + if (!at_xdmac_chan_is_cyclic(atchan)) + at_xdmac_advance_work(atchan); + + return; +} + +static int at_xdmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + unsigned long arg) +{ + struct at_xdmac_desc *desc, *_desc; + struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); + struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); + int ret = 0; + + dev_dbg(chan2dev(chan), "%s: cmd=%d\n", __func__, cmd); + + spin_lock_bh(&atchan->lock); + + switch (cmd) { + case DMA_PAUSE: + at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask); + set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); + break; + + case DMA_RESUME: + if (!at_xdmac_chan_is_paused(atchan)) + break; + + at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask); + clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); + break; + + case DMA_TERMINATE_ALL: + at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); + while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask) + cpu_relax(); + + /* Cancel all pending transfers. */ + list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node) + at_xdmac_remove_xfer(atchan, desc); + + clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status); + break; + + case DMA_SLAVE_CONFIG: + ret = at_xdmac_set_slave_config(chan, + (struct dma_slave_config *)arg); + break; + + default: + dev_err(chan2dev(chan), + "unmanaged or unknown dma control cmd: %d\n", cmd); + ret = -ENXIO; + } + + spin_unlock_bh(&atchan->lock); + + return ret; +} + +static int at_xdmac_alloc_chan_resources(struct dma_chan *chan) +{ + struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); + struct at_xdmac_desc *desc; + int i; + + spin_lock_bh(&atchan->lock); + + if (at_xdmac_chan_is_enabled(atchan)) { + dev_err(chan2dev(chan), + "can't allocate channel resources (channel enabled)\n"); + i = -EIO; + goto spin_unlock; + } + + if (!list_empty(&atchan->free_descs_list)) { + dev_err(chan2dev(chan), + "can't allocate channel resources (channel not free from a previous use)\n"); + i = -EIO; + goto spin_unlock; + } + + for (i = 0; i < init_nr_desc_per_channel; i++) { + desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC); + if (!desc) { + dev_warn(chan2dev(chan), + "only %d descriptors have been allocated\n", i); + break; + } + list_add_tail(&desc->desc_node, &atchan->free_descs_list); + } + + dma_cookie_init(chan); + + dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); + +spin_unlock: + spin_unlock_bh(&atchan->lock); + return i; +} + +static void at_xdmac_free_chan_resources(struct dma_chan *chan) +{ + struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); + struct at_xdmac *atxdmac = to_at_xdmac(chan->device); + struct at_xdmac_desc *desc, *_desc; + + list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) { + dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc); + list_del(&desc->desc_node); + dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys); + } + + return; +} + +#define AT_XDMAC_DMA_BUSWIDTHS\ + (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\ + BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\ + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\ + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\ + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) + +static int at_xdmac_device_slave_caps(struct dma_chan *dchan, + struct dma_slave_caps *caps) +{ + + caps->src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS; + caps->dstn_addr_widths = AT_XDMAC_DMA_BUSWIDTHS; + caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); + caps->cmd_pause = true; + caps->cmd_terminate = true; + caps->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; + + return 0; +} + +#ifdef CONFIG_PM +static int atmel_xdmac_prepare(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct at_xdmac *atxdmac = platform_get_drvdata(pdev); + struct dma_chan *chan, *_chan; + + list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { + struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); + + /* Wait for transfer completion, except in cyclic case. */ + if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan)) + return -EAGAIN; + } + return 0; +} +#else +# define atmel_xdmac_prepare NULL +#endif + +#ifdef CONFIG_PM_SLEEP +static int atmel_xdmac_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct at_xdmac *atxdmac = platform_get_drvdata(pdev); + struct dma_chan *chan, *_chan; + + list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { + struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); + + if (at_xdmac_chan_is_cyclic(atchan)) { + if (!at_xdmac_chan_is_paused(atchan)) + at_xdmac_control(chan, DMA_PAUSE, 0); + atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM); + atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA); + atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC); + } + } + atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM); + + at_xdmac_off(atxdmac); + clk_disable_unprepare(atxdmac->clk); + return 0; +} + +static int atmel_xdmac_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct at_xdmac *atxdmac = platform_get_drvdata(pdev); + struct at_xdmac_chan *atchan; + struct dma_chan *chan, *_chan; + int i; + u32 cfg; + + clk_prepare_enable(atxdmac->clk); + + /* Clear pending interrupts. */ + for (i = 0; i < atxdmac->dma.chancnt; i++) { + atchan = &atxdmac->chan[i]; + while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS)) + cpu_relax(); + } + + at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim); + at_xdmac_write(atxdmac, AT_XDMAC_GE, atxdmac->save_gs); + list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { + atchan = to_at_xdmac_chan(chan); + cfg = atchan->cfg[AT_XDMAC_CUR_CFG]; + at_xdmac_chan_write(atchan, AT_XDMAC_CC, cfg); + if (at_xdmac_chan_is_cyclic(atchan)) { + at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda); + at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc); + at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim); + wmb(); + at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); + } + } + return 0; +} +#endif /* CONFIG_PM_SLEEP */ + +static int at_xdmac_probe(struct platform_device *pdev) +{ + struct resource *res; + struct at_xdmac *atxdmac; + int irq, size, nr_channels, i, ret; + void __iomem *base; + u32 reg; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + /* + * Read number of xdmac channels, read helper function can't be used + * since atxdmac is not yet allocated and we need to know the number + * of channels to do the allocation. + */ + reg = readl_relaxed(base + AT_XDMAC_GTYPE); + nr_channels = AT_XDMAC_NB_CH(reg); + if (nr_channels > AT_XDMAC_MAX_CHAN) { + dev_err(&pdev->dev, "invalid number of channels (%u)\n", + nr_channels); + return -EINVAL; + } + + size = sizeof(*atxdmac); + size += nr_channels * sizeof(struct at_xdmac_chan); + atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); + if (!atxdmac) { + dev_err(&pdev->dev, "can't allocate at_xdmac structure\n"); + return -ENOMEM; + } + + atxdmac->regs = base; + atxdmac->irq = irq; + + atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk"); + if (IS_ERR(atxdmac->clk)) { + dev_err(&pdev->dev, "can't get dma_clk\n"); + return PTR_ERR(atxdmac->clk); + } + + /* Do not use dev res to prevent races with tasklet */ + ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac); + if (ret) { + dev_err(&pdev->dev, "can't request irq\n"); + return ret; + } + + ret = clk_prepare_enable(atxdmac->clk); + if (ret) { + dev_err(&pdev->dev, "can't prepare or enable clock\n"); + goto err_free_irq; + } + + atxdmac->at_xdmac_desc_pool = + dmam_pool_create(dev_name(&pdev->dev), &pdev->dev, + sizeof(struct at_xdmac_desc), 4, 0); + if (!atxdmac->at_xdmac_desc_pool) { + dev_err(&pdev->dev, "no memory for descriptors dma pool\n"); + ret = -ENOMEM; + goto err_clk_disable; + } + + dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask); + dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask); + dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask); + /* + * Without DMA_PRIVATE the driver is not able to allocate more than + * one channel, second allocation fails in private_candidate. + */ + dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask); + atxdmac->dma.dev = &pdev->dev; + atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources; + atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources; + atxdmac->dma.device_tx_status = at_xdmac_tx_status; + atxdmac->dma.device_issue_pending = at_xdmac_issue_pending; + atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic; + atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy; + atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg; + atxdmac->dma.device_control = at_xdmac_control; + atxdmac->dma.device_slave_caps = at_xdmac_device_slave_caps; + + /* Disable all chans and interrupts. */ + at_xdmac_off(atxdmac); + + /* Init channels. */ + INIT_LIST_HEAD(&atxdmac->dma.channels); + for (i = 0; i < nr_channels; i++) { + struct at_xdmac_chan *atchan = &atxdmac->chan[i]; + + atchan->chan.device = &atxdmac->dma; + list_add_tail(&atchan->chan.device_node, + &atxdmac->dma.channels); + + atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i); + atchan->mask = 1 << i; + + spin_lock_init(&atchan->lock); + INIT_LIST_HEAD(&atchan->xfers_list); + INIT_LIST_HEAD(&atchan->free_descs_list); + tasklet_init(&atchan->tasklet, at_xdmac_tasklet, + (unsigned long)atchan); + + /* Clear pending interrupts. */ + while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS)) + cpu_relax(); + } + platform_set_drvdata(pdev, atxdmac); + + ret = dma_async_device_register(&atxdmac->dma); + if (ret) { + dev_err(&pdev->dev, "fail to register DMA engine device\n"); + goto err_clk_disable; + } + + ret = of_dma_controller_register(pdev->dev.of_node, + at_xdmac_xlate, atxdmac); + if (ret) { + dev_err(&pdev->dev, "could not register of dma controller\n"); + goto err_dma_unregister; + } + + dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n", + nr_channels, atxdmac->regs); + + return 0; + +err_dma_unregister: + dma_async_device_unregister(&atxdmac->dma); +err_clk_disable: + clk_disable_unprepare(atxdmac->clk); +err_free_irq: + free_irq(atxdmac->irq, atxdmac->dma.dev); + return ret; +} + +static int at_xdmac_remove(struct platform_device *pdev) +{ + struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev); + int i; + + at_xdmac_off(atxdmac); + of_dma_controller_free(pdev->dev.of_node); + dma_async_device_unregister(&atxdmac->dma); + clk_disable_unprepare(atxdmac->clk); + + synchronize_irq(atxdmac->irq); + + free_irq(atxdmac->irq, atxdmac->dma.dev); + + for (i = 0; i < atxdmac->dma.chancnt; i++) { + struct at_xdmac_chan *atchan = &atxdmac->chan[i]; + + tasklet_kill(&atchan->tasklet); + at_xdmac_free_chan_resources(&atchan->chan); + } + + return 0; +} + +static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = { + .prepare = atmel_xdmac_prepare, + SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume) +}; + +static const struct of_device_id atmel_xdmac_dt_ids[] = { + { + .compatible = "atmel,sama5d4-dma", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids); + +static struct platform_driver at_xdmac_driver = { + .probe = at_xdmac_probe, + .remove = at_xdmac_remove, + .driver = { + .name = "at_xdmac", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(atmel_xdmac_dt_ids), + .pm = &atmel_xdmac_dev_pm_ops, + } +}; + +static int __init at_xdmac_init(void) +{ + return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe); +} +subsys_initcall(at_xdmac_init); + +MODULE_DESCRIPTION("Atmel Extended DMA Controller driver"); +MODULE_AUTHOR("Ludovic Desroches "); +MODULE_LICENSE("GPL"); diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 38493ff28fa5..7f9be0785c6a 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1041,6 +1041,8 @@ gic_of_init(struct device_node *node, struct device_node *parent) return 0; } IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); +IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); +IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); diff --git a/drivers/staging/iio/light/isl29028.c b/drivers/staging/iio/light/isl29028.c index 6014625920b0..e969107ddb47 100644 --- a/drivers/staging/iio/light/isl29028.c +++ b/drivers/staging/iio/light/isl29028.c @@ -537,7 +537,8 @@ static const struct i2c_device_id isl29028_id[] = { MODULE_DEVICE_TABLE(i2c, isl29028_id); static const struct of_device_id isl29028_of_match[] = { - { .compatible = "isil,isl29028", }, + { .compatible = "isl,isl29028", }, + { .compatible = "isil,isl29028", },/* deprecated, don't use */ { }, }; MODULE_DEVICE_TABLE(of, isl29028_of_match); diff --git a/include/dt-bindings/clock/r8a7740-clock.h b/include/dt-bindings/clock/r8a7740-clock.h index f6b4b0fe7a43..476135da0f23 100644 --- a/include/dt-bindings/clock/r8a7740-clock.h +++ b/include/dt-bindings/clock/r8a7740-clock.h @@ -40,6 +40,7 @@ /* MSTP2 */ #define R8A7740_CLK_SCIFA6 30 +#define R8A7740_CLK_INTCA 29 #define R8A7740_CLK_SCIFA7 22 #define R8A7740_CLK_DMAC1 18 #define R8A7740_CLK_DMAC2 17 diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index 8ea7ab0346ad..e3a3fb80feb6 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -26,8 +26,18 @@ #define R8A7790_CLK_MSIOF0 0 /* MSTP1 */ -#define R8A7790_CLK_JPU 6 +#define R8A7790_CLK_VCP1 0 +#define R8A7790_CLK_VCP0 1 +#define R8A7790_CLK_VPC1 2 +#define R8A7790_CLK_VPC0 3 +#define R8A7790_CLK_JPU 6 +#define R8A7790_CLK_SSP1 9 #define R8A7790_CLK_TMU1 11 +#define R8A7790_CLK_3DG 12 +#define R8A7790_CLK_2DDMAC 15 +#define R8A7790_CLK_FDP1_2 17 +#define R8A7790_CLK_FDP1_1 18 +#define R8A7790_CLK_FDP1_0 19 #define R8A7790_CLK_TMU3 21 #define R8A7790_CLK_TMU2 22 #define R8A7790_CLK_CMT0 24 diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h index 58c3f49d068c..dcececd9f4d0 100644 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ b/include/dt-bindings/clock/r8a7791-clock.h @@ -25,8 +25,15 @@ #define R8A7791_CLK_MSIOF0 0 /* MSTP1 */ -#define R8A7791_CLK_JPU 6 +#define R8A7791_CLK_VCP0 1 +#define R8A7791_CLK_VPC0 3 +#define R8A7791_CLK_JPU 6 +#define R8A7791_CLK_SSP1 9 #define R8A7791_CLK_TMU1 11 +#define R8A7791_CLK_3DG 12 +#define R8A7791_CLK_2DDMAC 15 +#define R8A7791_CLK_FDP1_1 18 +#define R8A7791_CLK_FDP1_0 19 #define R8A7791_CLK_TMU3 21 #define R8A7791_CLK_TMU2 22 #define R8A7791_CLK_CMT0 24 diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h new file mode 100644 index 000000000000..7af2b717b3b2 --- /dev/null +++ b/include/dt-bindings/clock/stih407-clks.h @@ -0,0 +1,86 @@ +/* + * This header provides constants clk index STMicroelectronics + * STiH407 SoC. + */ +#ifndef _DT_BINDINGS_CLK_STIH407 +#define _DT_BINDINGS_CLK_STIH407 + +/* CLOCKGEN C0 */ +#define CLK_ICN_GPU 0 +#define CLK_FDMA 1 +#define CLK_NAND 2 +#define CLK_HVA 3 +#define CLK_PROC_STFE 4 +#define CLK_PROC_TP 5 +#define CLK_RX_ICN_DMU 6 +#define CLK_RX_ICN_DISP_0 6 +#define CLK_RX_ICN_DISP_1 6 +#define CLK_RX_ICN_HVA 7 +#define CLK_RX_ICN_TS 7 +#define CLK_ICN_CPU 8 +#define CLK_TX_ICN_DMU 9 +#define CLK_TX_ICN_HVA 9 +#define CLK_TX_ICN_TS 9 +#define CLK_ICN_COMPO 9 +#define CLK_MMC_0 10 +#define CLK_MMC_1 11 +#define CLK_JPEGDEC 12 +#define CLK_ICN_REG 13 +#define CLK_TRACE_A9 13 +#define CLK_PTI_STM 13 +#define CLK_EXT2F_A9 13 +#define CLK_IC_BDISP_0 14 +#define CLK_IC_BDISP_1 15 +#define CLK_PP_DMU 16 +#define CLK_VID_DMU 17 +#define CLK_DSS_LPC 18 +#define CLK_ST231_AUD_0 19 +#define CLK_ST231_GP_0 19 +#define CLK_ST231_GP_1 20 +#define CLK_ST231_DMU 21 +#define CLK_ICN_LMI 22 +#define CLK_TX_ICN_DISP_0 23 +#define CLK_TX_ICN_DISP_1 23 +#define CLK_ICN_SBC 24 +#define CLK_STFE_FRC2 25 +#define CLK_ETH_PHY 26 +#define CLK_ETH_REF_PHYCLK 27 +#define CLK_FLASH_PROMIP 28 +#define CLK_MAIN_DISP 29 +#define CLK_AUX_DISP 30 +#define CLK_COMPO_DVP 31 + +/* CLOCKGEN D0 */ +#define CLK_PCM_0 0 +#define CLK_PCM_1 1 +#define CLK_PCM_2 2 +#define CLK_SPDIFF 3 + +/* CLOCKGEN D2 */ +#define CLK_PIX_MAIN_DISP 0 +#define CLK_PIX_PIP 1 +#define CLK_PIX_GDP1 2 +#define CLK_PIX_GDP2 3 +#define CLK_PIX_GDP3 4 +#define CLK_PIX_GDP4 5 +#define CLK_PIX_AUX_DISP 6 +#define CLK_DENC 7 +#define CLK_PIX_HDDAC 8 +#define CLK_HDDAC 9 +#define CLK_SDDAC 10 +#define CLK_PIX_DVO 11 +#define CLK_DVO 12 +#define CLK_PIX_HDMI 13 +#define CLK_TMDS_HDMI 14 +#define CLK_REF_HDMIPHY 15 + +/* CLOCKGEN D3 */ +#define CLK_STFE_FRC1 0 +#define CLK_TSOUT_0 1 +#define CLK_TSOUT_1 2 +#define CLK_MCHI 3 +#define CLK_VSENS_COMPO 4 +#define CLK_FRC1_REMOTE 5 +#define CLK_LPC_0 6 +#define CLK_LPC_1 7 +#endif diff --git a/include/dt-bindings/dma/at91.h b/include/dt-bindings/dma/at91.h index e835037a77b4..ab6cbba45401 100644 --- a/include/dt-bindings/dma/at91.h +++ b/include/dt-bindings/dma/at91.h @@ -9,6 +9,8 @@ #ifndef __DT_BINDINGS_AT91_DMA_H__ #define __DT_BINDINGS_AT91_DMA_H__ +/* ---------- HDMAC ---------- */ + /* * Source and/or destination peripheral ID */ @@ -24,4 +26,27 @@ #define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ #define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ + +/* ---------- XDMAC ---------- */ +#define AT91_XDMAC_DT_MEM_IF_MASK (0x1) +#define AT91_XDMAC_DT_MEM_IF_OFFSET (13) +#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ + << AT91_XDMAC_DT_MEM_IF_OFFSET) +#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ + & AT91_XDMAC_DT_MEM_IF_MASK) + +#define AT91_XDMAC_DT_PER_IF_MASK (0x1) +#define AT91_XDMAC_DT_PER_IF_OFFSET (14) +#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ + << AT91_XDMAC_DT_PER_IF_OFFSET) +#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ + & AT91_XDMAC_DT_PER_IF_MASK) + +#define AT91_XDMAC_DT_PERID_MASK (0x7f) +#define AT91_XDMAC_DT_PERID_OFFSET (24) +#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ + << AT91_XDMAC_DT_PERID_OFFSET) +#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ + & AT91_XDMAC_DT_PERID_MASK) + #endif /* __DT_BINDINGS_AT91_DMA_H__ */ diff --git a/include/dt-bindings/reset-controller/stih407-resets.h b/include/dt-bindings/reset-controller/stih407-resets.h new file mode 100644 index 000000000000..02d4328fe479 --- /dev/null +++ b/include/dt-bindings/reset-controller/stih407-resets.h @@ -0,0 +1,61 @@ +/* + * This header provides constants for the reset controller + * based peripheral powerdown requests on the STMicroelectronics + * STiH407 SoC. + */ +#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407 +#define _DT_BINDINGS_RESET_CONTROLLER_STIH407 + +/* Powerdown requests control 0 */ +#define STIH407_EMISS_POWERDOWN 0 +#define STIH407_NAND_POWERDOWN 1 + +/* Synp GMAC PowerDown */ +#define STIH407_ETH1_POWERDOWN 2 + +/* Powerdown requests control 1 */ +#define STIH407_USB3_POWERDOWN 3 +#define STIH407_USB2_PORT1_POWERDOWN 4 +#define STIH407_USB2_PORT0_POWERDOWN 5 +#define STIH407_PCIE1_POWERDOWN 6 +#define STIH407_PCIE0_POWERDOWN 7 +#define STIH407_SATA1_POWERDOWN 8 +#define STIH407_SATA0_POWERDOWN 9 + +/* Reset defines */ +#define STIH407_ETH1_SOFTRESET 0 +#define STIH407_MMC1_SOFTRESET 1 +#define STIH407_PICOPHY_SOFTRESET 2 +#define STIH407_IRB_SOFTRESET 3 +#define STIH407_PCIE0_SOFTRESET 4 +#define STIH407_PCIE1_SOFTRESET 5 +#define STIH407_SATA0_SOFTRESET 6 +#define STIH407_SATA1_SOFTRESET 7 +#define STIH407_MIPHY0_SOFTRESET 8 +#define STIH407_MIPHY1_SOFTRESET 9 +#define STIH407_MIPHY2_SOFTRESET 10 +#define STIH407_SATA0_PWR_SOFTRESET 11 +#define STIH407_SATA1_PWR_SOFTRESET 12 +#define STIH407_DELTA_SOFTRESET 13 +#define STIH407_BLITTER_SOFTRESET 14 +#define STIH407_HDTVOUT_SOFTRESET 15 +#define STIH407_HDQVDP_SOFTRESET 16 +#define STIH407_VDP_AUX_SOFTRESET 17 +#define STIH407_COMPO_SOFTRESET 18 +#define STIH407_HDMI_TX_PHY_SOFTRESET 19 +#define STIH407_JPEG_DEC_SOFTRESET 20 +#define STIH407_VP8_DEC_SOFTRESET 21 +#define STIH407_GPU_SOFTRESET 22 +#define STIH407_HVA_SOFTRESET 23 +#define STIH407_ERAM_HVA_SOFTRESET 24 +#define STIH407_LPM_SOFTRESET 25 +#define STIH407_KEYSCAN_SOFTRESET 26 +#define STIH407_USB2_PORT0_SOFTRESET 27 +#define STIH407_USB2_PORT1_SOFTRESET 28 + +/* Picophy reset defines */ +#define STIH407_PICOPHY0_RESET 0 +#define STIH407_PICOPHY1_RESET 1 +#define STIH407_PICOPHY2_RESET 2 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */