Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt

   1 Mediatek infracfg controller
   2 ============================
   3
   4 The Mediatek infracfg controller provides various clocks and reset
   5 outputs to the system.
   6
   7 Required Properties:
   8
   9 - compatible: Should be one of:
  10         - "mediatek,mt2701-infracfg", "syscon"
  11         - "mediatek,mt8135-infracfg", "syscon"
  12         - "mediatek,mt8173-infracfg", "syscon"
  13 - #clock-cells: Must be 1
  14 - #reset-cells: Must be 1
  15
  16 The infracfg controller uses the common clk binding from
  17 Documentation/devicetree/bindings/clock/clock-bindings.txt
  18 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
  19 Also it uses the common reset controller binding from
  20 Documentation/devicetree/bindings/reset/reset.txt.
  21 The available reset outputs are defined in
  22 dt-bindings/reset/mt*-resets.h
  23
  24 Example:
  25
  26 infracfg: power-controller@10001000 {
  27         compatible = "mediatek,mt8173-infracfg", "syscon";
  28         reg = <0 0x10001000 0 0x1000>;
  29         #clock-cells = <1>;
  30         #reset-cells = <1>;
  31 };