Documentation/devicetree/bindings/display/msm/mdp.txt

   1 Qualcomm adreno/snapdragon display controller
   2
   3 Required properties:
   4 - compatible:
   5   * "qcom,mdp4" - mdp4
   6   * "qcom,mdp5" - mdp5
   7 - reg: Physical base address and length of the controller's registers.
   8 - interrupts: The interrupt signal from the display controller.
   9 - connectors: array of phandles for output device(s)
  10 - clocks: device clocks
  11   See ../clocks/clock-bindings.txt for details.
  12 - clock-names: the following clocks are required.
  13   For MDP4:
  14    * "core_clk"
  15    * "iface_clk"
  16    * "lut_clk"
  17    * "src_clk"
  18    * "hdmi_clk"
  19    * "mdp_clk"
  20   For MDP5:
  21    * "bus_clk"
  22    * "iface_clk"
  23    * "core_clk_src"
  24    * "core_clk"
  25    * "lut_clk" (some MDP5 versions may not need this)
  26    * "vsync_clk"
  27
  28 Optional properties:
  29 - gpus: phandle for gpu device
  30 - clock-names: the following clocks are optional:
  31   * "lut_clk"
  32
  33 Example:
  34
  35 / {
  36         ...
  37
  38         mdp: qcom,mdp@5100000 {
  39                 compatible = "qcom,mdp4";
  40                 reg = <0x05100000 0xf0000>;
  41                 interrupts = <GIC_SPI 75 0>;
  42                 connectors = <&hdmi>;
  43                 gpus = <&gpu>;
  44                 clock-names =
  45                     "core_clk",
  46                     "iface_clk",
  47                     "lut_clk",
  48                     "src_clk",
  49                     "hdmi_clk",
  50                     "mdp_clk";
  51                 clocks =
  52                     <&mmcc MDP_SRC>,
  53                     <&mmcc MDP_AHB_CLK>,
  54                     <&mmcc MDP_LUT_CLK>,
  55                     <&mmcc TV_SRC>,
  56                     <&mmcc HDMI_TV_CLK>,
  57                     <&mmcc MDP_TV_CLK>;
  58         };
  59 };