Documentation/devicetree/bindings/gpu/st,stih4xx.txt

   1 STMicroelectronics stih4xx platforms
   2
   3 - sti-vtg: video timing generator
   4   Required properties:
   5   - compatible: "st,vtg"
   6   - reg: Physical base address of the IP registers and length of memory mapped region.
   7   Optional properties:
   8   - interrupts : VTG interrupt number to the CPU.
   9   - st,slave: phandle on a slave vtg
  10
  11 - sti-vtac: video timing advanced inter dye communication Rx and TX
  12   Required properties:
  13   - compatible: "st,vtac-main" or "st,vtac-aux"
  14   - reg: Physical base address of the IP registers and length of memory mapped region.
  15   - clocks: from common clock binding: handle hardware IP needed clocks, the
  16     number of clocks may depend of the SoC type.
  17     See ../clocks/clock-bindings.txt for details.
  18   - clock-names: names of the clocks listed in clocks property in the same
  19     order.
  20
  21 - sti-display-subsystem: Master device for DRM sub-components
  22   This device must be the parent of all the sub-components and is responsible
  23   of bind them.
  24   Required properties:
  25   - compatible: "st,sti-display-subsystem"
  26   - ranges: to allow probing of subdevices
  27
  28 - sti-compositor: frame compositor engine
  29   must be a child of sti-display-subsystem
  30   Required properties:
  31   - compatible: "st,stih<chip>-compositor"
  32   - reg: Physical base address of the IP registers and length of memory mapped region.
  33   - clocks: from common clock binding: handle hardware IP needed clocks, the
  34     number of clocks may depend of the SoC type.
  35     See ../clocks/clock-bindings.txt for details.
  36   - clock-names: names of the clocks listed in clocks property in the same
  37     order.
  38   - resets: resets to be used by the device
  39     See ../reset/reset.txt for details.
  40   - reset-names: names of the resets listed in resets property in the same
  41     order.
  42   - st,vtg: phandle(s) on vtg device (main and aux) nodes.
  43
  44 - sti-tvout: video out hardware block
  45   must be a child of sti-display-subsystem
  46   Required properties:
  47   - compatible: "st,stih<chip>-tvout"
  48   - reg: Physical base address of the IP registers and length of memory mapped region.
  49   - reg-names: names of the mapped memory regions listed in regs property in
  50     the same order.
  51   - resets: resets to be used by the device
  52     See ../reset/reset.txt for details.
  53   - reset-names: names of the resets listed in resets property in the same
  54     order.
  55   - ranges: to allow probing of subdevices
  56
  57 - sti-hdmi: hdmi output block
  58   must be a child of sti-tvout
  59   Required properties:
  60   - compatible: "st,stih<chip>-hdmi";
  61   - reg: Physical base address of the IP registers and length of memory mapped region.
  62   - reg-names: names of the mapped memory regions listed in regs property in
  63     the same order.
  64   - interrupts : HDMI interrupt number to the CPU.
  65   - interrupt-names: name of the interrupts listed in interrupts property in
  66     the same order
  67   - clocks: from common clock binding: handle hardware IP needed clocks, the
  68     number of clocks may depend of the SoC type.
  69   - clock-names: names of the clocks listed in clocks property in the same
  70     order.
  71   - ddc: phandle of an I2C controller used for DDC EDID probing
  72
  73 sti-hda:
  74   Required properties:
  75   must be a child of sti-tvout
  76   - compatible: "st,stih<chip>-hda"
  77   - reg: Physical base address of the IP registers and length of memory mapped region.
  78   - reg-names: names of the mapped memory regions listed in regs property in
  79     the same order.
  80   - clocks: from common clock binding: handle hardware IP needed clocks, the
  81     number of clocks may depend of the SoC type.
  82     See ../clocks/clock-bindings.txt for details.
  83   - clock-names: names of the clocks listed in clocks property in the same
  84     order.
  85
  86 sti-hqvdp:
  87   must be a child of sti-display-subsystem
  88   Required properties:
  89   - compatible: "st,stih<chip>-hqvdp"
  90   - reg: Physical base address of the IP registers and length of memory mapped region.
  91   - clocks: from common clock binding: handle hardware IP needed clocks, the
  92     number of clocks may depend of the SoC type.
  93     See ../clocks/clock-bindings.txt for details.
  94   - clock-names: names of the clocks listed in clocks property in the same
  95     order.
  96   - resets: resets to be used by the device
  97     See ../reset/reset.txt for details.
  98   - reset-names: names of the resets listed in resets property in the same
  99     order.
 100   - st,vtg: phandle on vtg main device node.
 101
 102 Example:
 103
 104 / {
 105         ...
 106
 107         vtg_main_slave: sti-vtg-main-slave@fe85A800 {
 108                 compatible      = "st,vtg";
 109                 reg             = <0xfe85A800 0x300>;
 110                 interrupts      = <GIC_SPI 175 IRQ_TYPE_NONE>;
 111         };
 112
 113         vtg_main: sti-vtg-main-master@fd348000 {
 114                 compatible      = "st,vtg";
 115                 reg             = <0xfd348000 0x400>;
 116                 st,slave        = <&vtg_main_slave>;
 117         };
 118
 119         vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
 120                 compatible      = "st,vtg";
 121                 reg             = <0xfe858200 0x300>;
 122                 interrupts      = <GIC_SPI 176 IRQ_TYPE_NONE>;
 123         };
 124
 125         vtg_aux: sti-vtg-aux-master@fd348400 {
 126                 compatible      = "st,vtg";
 127                 reg             = <0xfd348400 0x400>;
 128                 st,slave        = <&vtg_aux_slave>;
 129         };
 130
 131
 132         sti-vtac-rx-main@fee82800 {
 133                 compatible      = "st,vtac-main";
 134                 reg             = <0xfee82800 0x200>;
 135                 clock-names     = "vtac";
 136                 clocks          = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
 137         };
 138
 139         sti-vtac-rx-aux@fee82a00 {
 140                 compatible      = "st,vtac-aux";
 141                 reg             = <0xfee82a00 0x200>;
 142                 clock-names     = "vtac";
 143                 clocks          = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
 144         };
 145
 146         sti-vtac-tx-main@fd349000 {
 147                 compatible      = "st,vtac-main";
 148                 reg             = <0xfd349000 0x200>, <0xfd320000 0x10000>;
 149                 clock-names     = "vtac";
 150                 clocks           = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
 151         };
 152
 153         sti-vtac-tx-aux@fd349200 {
 154                 compatible      = "st,vtac-aux";
 155                 reg             = <0xfd349200 0x200>, <0xfd320000 0x10000>;
 156                 clock-names     = "vtac";
 157                 clocks          = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
 158         };
 159
 160         sti-display-subsystem {
 161                 compatible = "st,sti-display-subsystem";
 162                 ranges;
 163
 164                 sti-compositor@fd340000 {
 165                         compatible      = "st,stih416-compositor";
 166                         reg             = <0xfd340000 0x1000>;
 167                         clock-names     = "compo_main", "compo_aux",
 168                                           "pix_main", "pix_aux";
 169                         clocks          = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
 170                                           <&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
 171                         reset-names     = "compo-main", "compo-aux";
 172                         resets          = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
 173                         st,vtg          = <&vtg_main>, <&vtg_aux>;
 174                 };
 175
 176                 sti-tvout@fe000000 {
 177                         compatible      = "st,stih416-tvout";
 178                         reg             = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
 179                         reg-names       = "tvout-reg", "hda-reg", "syscfg";
 180                         reset-names     = "tvout";
 181                         resets          = <&softreset STIH416_HDTVOUT_SOFTRESET>;
 182                         ranges;
 183
 184                         sti-hdmi@fe85c000 {
 185                                 compatible      = "st,stih416-hdmi";
 186                                 reg             = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
 187                                 reg-names       = "hdmi-reg", "syscfg";
 188                                 interrupts      = <GIC_SPI 173 IRQ_TYPE_NONE>;
 189                                 interrupt-names = "irq";
 190                                 clock-names     = "pix", "tmds", "phy", "audio";
 191                                 clocks          = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
 192                         };
 193
 194                         sti-hda@fe85a000 {
 195                                 compatible      = "st,stih416-hda";
 196                                 reg             = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
 197                                 reg-names       = "hda-reg", "video-dacs-ctrl";
 198                                 clock-names     = "pix", "hddac";
 199                                 clocks          = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
 200                         };
 201                 };
 202
 203                 sti-hqvdp@9c000000 {
 204                                 compatible      = "st,stih407-hqvdp";
 205                                 reg             = <0x9C00000 0x100000>;
 206                                 clock-names     = "hqvdp", "pix_main";
 207                                 clocks          = <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
 208                                 reset-names     = "hqvdp";
 209                                 resets          = <&softreset STIH407_HDQVDP_SOFTRESET>;
 210                                 st,vtg          = <&vtg_main>;
 211                         };
 212         };
 213         ...
 214 };