1 * Rockchip AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
15 - clock-names: Must include the following entries:
20 - msi-map: Maps a Requester ID to an MSI controller and associated
21 msi-specifier data. See ./pci-msi.txt
22 - phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
23 - phy-names: MUST be "pcie-phy".
24 - interrupts: Three interrupt entries must be specified.
25 - interrupt-names: Must include the following names
29 - resets: Must contain five entries for each entry in reset-names.
30 See ../reset/reset.txt for details.
31 - reset-names: Must include the following names
36 - pinctrl-names : The pin control state names
37 - pinctrl-0: The "default" pinctrl state
38 - #interrupt-cells: specifies the number of cells needed to encode an
39 interrupt source. The value must be 1.
40 - interrupt-map-mask and interrupt-map: standard PCI properties
43 - ep-gpios: contain the entry for pre-reset gpio
44 - num-lanes: number of lanes to use
45 - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
46 - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
47 - vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
49 *Interrupt controller child node*
50 The core controller provides a single interrupt for legacy INTx. The PCIe node
51 should contain an interrupt controller node as a target for the PCI
52 'interrupt-map' property. This node represents the domain at which the four
53 INTx interrupts are decoded and routed.
56 Required properties for Interrupt controller child node:
57 - interrupt-controller: identifies the node as an interrupt controller
58 - #address-cells: specifies the number of cells needed to encode an
59 address. The value must be 0.
60 - #interrupt-cells: specifies the number of cells needed to encode an
61 interrupt source. The value must be 1.
65 pcie0: pcie@f8000000 {
66 compatible = "rockchip,rk3399-pcie";
69 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
70 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
71 clock-names = "aclk", "aclk-perf",
73 bus-range = <0x0 0x1>;
74 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
75 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
76 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
77 interrupt-names = "sys", "legacy", "client";
78 assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
79 assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
80 assigned-clock-rates = <100000000>;
81 ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
82 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
83 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
85 msi-map = <0x0 &its 0x0 0x1000>;
86 reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
87 reg-names = "axi-base", "apb-base";
88 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
89 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
90 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
92 phy-names = "pcie-phy";
93 pinctrl-names = "default";
94 pinctrl-0 = <&pcie_clkreq>;
95 #interrupt-cells = <1>;
96 interrupt-map-mask = <0 0 0 7>;
97 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
98 <0 0 0 2 &pcie0_intc 1>,
99 <0 0 0 3 &pcie0_intc 2>,
100 <0 0 0 4 &pcie0_intc 3>;
101 pcie0_intc: interrupt-controller {
102 interrupt-controller;
103 #address-cells = <0>;
104 #interrupt-cells = <1>;