1 =============================================================================
2 Freescale Frame Manager Device Bindings
8 - FMan dTSEC/XGEC/mEMAC Node
12 =============================================================================
17 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
18 etc.) the FMan node will have child nodes for each of them.
24 Value type: <stringlist>
25 Definition: Must include "fsl,fman"
26 FMan version can be determined via FM_IP_REV_1 register in the
27 FMan block. The offset is 0xc4 from the beginning of the
28 Frame Processing Manager memory map (0xc3000 from the
29 beginning of the FMan node).
34 Definition: Specifies the index of the FMan unit.
36 The cell-index value may be used by the SoC, to identify the
37 FMan unit in the SoC memory map. In the table bellow,
38 there's a description of the cell-index use in each SoC:
41 register[bit] FMan unit cell-index
42 ============================================================
45 - P2041, P3041, P4080 P5020, P5040:
46 register[bit] FMan unit cell-index
47 ============================================================
50 (Second FM available only in P4080 and P5040)
52 - B4860, T1040, T2080, T4240:
53 register[bit] FMan unit cell-index
54 ============================================================
55 DCFG_CCSR_DEVDISR2[24] 1 0
56 DCFG_CCSR_DEVDISR2[25] 2 1
57 (Second FM available only in T4240)
59 DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
60 the specific SoC "Device Configuration/Pin Control" Memory
65 Value type: <prop-encoded-array>
66 Definition: A standard property. Specifies the offset of the
67 following configuration registers:
68 - BMI configuration registers.
69 - QMI configuration registers.
70 - DMA configuration registers.
71 - FPM configuration registers.
72 - FMan controller configuration registers.
76 Value type: <prop-encoded-array>
77 Definition: A standard property.
81 Value type: <prop-encoded-array>
82 Definition: phandle for the fman input clock.
86 Value type: <stringlist>
87 Definition: "fmanclk" for the fman input clock.
91 Value type: <prop-encoded-array>
92 Definition: A pair of IRQs are specified in this property.
93 The first element is associated with the event interrupts and
94 the second element is associated with the error interrupts.
96 - fsl,qman-channel-range
98 Value type: <prop-encoded-array>
99 Definition: Specifies the range of the available dedicated
100 channels in the FMan. The first cell specifies the beginning
101 of the range and the second cell specifies the number of
103 Further information available at:
104 "Work Queue (WQ) Channel Assignments in the QMan" section
105 in DPAA Reference Manual.
110 Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
112 =============================================================================
117 FMan Internal memory - shared between all the FMan modules.
118 It contains data structures that are common and written to or read by
120 FMan internal memory is split into the following parts:
121 Packet buffering (Tx/Rx FIFOs)
122 Frames internal context
128 Value type: <stringlist>
129 Definition: Must include "fsl,fman-muram"
133 Value type: <prop-encoded-array>
134 Definition: A standard property.
135 Specifies the multi-user memory offset and the size within
141 compatible = "fsl,fman-muram";
142 ranges = <0 0x000000 0x28000>;
145 =============================================================================
150 The Frame Manager (FMan) supports several types of hardware ports:
151 Ethernet receiver (RX)
152 Ethernet transmitter (TX)
153 Offline/Host command (O/H)
159 Value type: <stringlist>
160 Definition: A standard property.
161 Must include one of the following:
162 - "fsl,fman-v2-port-oh" for FManV2 OH ports
163 - "fsl,fman-v2-port-rx" for FManV2 RX ports
164 - "fsl,fman-v2-port-tx" for FManV2 TX ports
165 - "fsl,fman-v3-port-oh" for FManV3 OH ports
166 - "fsl,fman-v3-port-rx" for FManV3 RX ports
167 - "fsl,fman-v3-port-tx" for FManV3 TX ports
172 Definition: Specifies the hardware port id.
173 Each hardware port on the FMan has its own hardware PortID.
174 Super set of all hardware Port IDs available at FMan Reference
175 Manual under "FMan Hardware Ports in Freescale Devices" table.
177 Each hardware port is assigned a 4KB, port-specific page in
178 the FMan hardware port memory region (which is part of the
179 FMan memory map). The first 4 KB in the FMan hardware ports
180 memory region is used for what are called common registers.
181 The subsequent 63 4KB pages are allocated to the hardware
183 The page of a specific port is determined by the cell-index.
187 Value type: <prop-encoded-array>
188 Definition: There is one reg region describing the port
189 configuration registers.
195 compatible = "fsl,fman-v2-port-tx";
196 reg = <0xa8000 0x1000>;
201 compatible = "fsl,fman-v2-port-rx";
202 reg = <0x88000 0x1000>;
207 compatible = "fsl,fman-v2-port-oh";
208 reg = <0x81000 0x1000>;
211 =============================================================================
212 FMan dTSEC/XGEC/mEMAC Node
216 mEMAC/dTSEC/XGEC are the Ethernet network interfaces
222 Value type: <stringlist>
223 Definition: A standard property.
224 Must include one of the following:
225 - "fsl,fman-dtsec" for dTSEC MAC
226 - "fsl,fman-xgec" for XGEC MAC
227 - "fsl,fman-memac for mEMAC MAC
232 Definition: Specifies the MAC id.
234 The cell-index value may be used by the FMan or the SoC, to
235 identify the MAC unit in the FMan (or SoC) memory map.
236 In the tables bellow there's a description of the cell-index
237 use, there are two tables, one describes the use of cell-index
238 by the FMan, the second describes the use by the SoC:
243 register[bit] MAC cell-index
244 ============================================================
246 FM_EPI[16+n] dTSECn n-1
247 FM_NPI[11+n] dTSECn n-1
251 register[bit] MAC cell-index
252 ============================================================
253 FM_EPI[16+n] mEMACn n-1
256 FM_NPI[11+n] mEMACn n-1
261 FM_EPI and FM_NPI are located in the FMan memory map.
265 - P2041, P3041, P4080 P5020, P5040:
266 register[bit] FMan MAC cell
268 ============================================================
269 DCFG_DEVDISR2[7] 1 XGEC 8
270 DCFG_DEVDISR2[7+n] 1 dTSECn n-1
271 DCFG_DEVDISR2[15] 2 XGEC 8
272 DCFG_DEVDISR2[15+n] 2 dTSECn n-1
275 - T1040, T2080, T4240, B4860:
276 register[bit] FMan MAC cell
278 ============================================================
279 DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1
280 DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1
283 EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
284 the specific SoC "Device Configuration/Pin Control" Memory
289 Value type: <prop-encoded-array>
290 Definition: A standard property.
294 Value type: <prop-encoded-array>
295 Definition: An array of two phandles - the first references is
296 the FMan RX port and the second is the TX port used by this
301 Value type: <phandle>
302 Definition: A phandle for 1EEE1588 timer.
306 fman1_tx28: port@a8000 {
308 compatible = "fsl,fman-v2-port-tx";
309 reg = <0xa8000 0x1000>;
312 fman1_rx8: port@88000 {
314 compatible = "fsl,fman-v2-port-rx";
315 reg = <0x88000 0x1000>;
318 ptp-timer: ptp_timer@fe000 {
319 compatible = "fsl,fman-ptp-timer";
320 reg = <0xfe000 0x1000>;
324 compatible = "fsl,fman-dtsec";
326 reg = <0xe0000 0x1000>;
327 fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
328 ptp-timer = <&ptp-timer>;
331 ============================================================================
336 The FMan interface to support IEEE 1588
343 Value type: <stringlist>
344 Definition: A standard property.
345 Must include "fsl,fman-ptp-timer".
349 Value type: <prop-encoded-array>
350 Definition: A standard property.
355 compatible = "fsl,fman-ptp-timer";
356 reg = <0xfe000 0x1000>;
359 =============================================================================
363 #address-cells = <1>;
366 compatible = "fsl,fman"
367 ranges = <0 0x400000 0x100000>;
368 reg = <0x400000 0x100000>;
369 clocks = <&fman_clk>;
370 clock-names = "fmanclk";
374 fsl,qman-channel-range = <0x40 0xc>;
377 compatible = "fsl,fman-muram";
383 compatible = "fsl,fman-v2-port-oh";
384 reg = <0x81000 0x1000>;
389 compatible = "fsl,fman-v2-port-oh";
390 reg = <0x82000 0x1000>;
395 compatible = "fsl,fman-v2-port-oh";
396 reg = <0x83000 0x1000>;
401 compatible = "fsl,fman-v2-port-oh";
402 reg = <0x84000 0x1000>;
407 compatible = "fsl,fman-v2-port-oh";
408 reg = <0x85000 0x1000>;
413 compatible = "fsl,fman-v2-port-oh";
414 reg = <0x86000 0x1000>;
417 fman1_rx_0x8: port@88000 {
419 compatible = "fsl,fman-v2-port-rx";
420 reg = <0x88000 0x1000>;
423 fman1_rx_0x9: port@89000 {
425 compatible = "fsl,fman-v2-port-rx";
426 reg = <0x89000 0x1000>;
429 fman1_rx_0xa: port@8a000 {
431 compatible = "fsl,fman-v2-port-rx";
432 reg = <0x8a000 0x1000>;
435 fman1_rx_0xb: port@8b000 {
437 compatible = "fsl,fman-v2-port-rx";
438 reg = <0x8b000 0x1000>;
441 fman1_rx_0xc: port@8c000 {
443 compatible = "fsl,fman-v2-port-rx";
444 reg = <0x8c000 0x1000>;
447 fman1_rx_0x10: port@90000 {
449 compatible = "fsl,fman-v2-port-rx";
450 reg = <0x90000 0x1000>;
453 fman1_tx_0x28: port@a8000 {
455 compatible = "fsl,fman-v2-port-tx";
456 reg = <0xa8000 0x1000>;
459 fman1_tx_0x29: port@a9000 {
461 compatible = "fsl,fman-v2-port-tx";
462 reg = <0xa9000 0x1000>;
465 fman1_tx_0x2a: port@aa000 {
467 compatible = "fsl,fman-v2-port-tx";
468 reg = <0xaa000 0x1000>;
471 fman1_tx_0x2b: port@ab000 {
473 compatible = "fsl,fman-v2-port-tx";
474 reg = <0xab000 0x1000>;
477 fman1_tx_0x2c: port@ac0000 {
479 compatible = "fsl,fman-v2-port-tx";
480 reg = <0xac000 0x1000>;
483 fman1_tx_0x30: port@b0000 {
485 compatible = "fsl,fman-v2-port-tx";
486 reg = <0xb0000 0x1000>;
490 compatible = "fsl,fman-dtsec";
492 reg = <0xe0000 0x1000>;
493 fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
497 compatible = "fsl,fman-dtsec";
499 reg = <0xe2000 0x1000>;
500 fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
504 compatible = "fsl,fman-dtsec";
506 reg = <0xe4000 0x1000>;
507 fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
511 compatible = "fsl,fman-dtsec";
513 reg = <0xe6000 0x1000>;
514 fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
518 compatible = "fsl,fman-dtsec";
520 reg = <0xf0000 0x1000>;
521 fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
525 compatible = "fsl,fman-xgec";
526 reg = <0xf0000 0x1000>;
527 fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
531 compatible = "fsl,fman-ptp-timer";
532 reg = <0xfe000 0x1000>;