arch/arm/boot/dts/am335x-phycore-som.dtsi

   1 /*
   2  * Copyright (C) 2015 Phytec Messtechnik GmbH
   3  * Author: Teresa Remmet <t.remmet@phytec.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include "am33xx.dtsi"
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12
  13 / {
  14         model = "Phytec AM335x phyCORE";
  15         compatible = "phytec,am335x-phycore-som", "ti,am33xx";
  16
  17         aliases {
  18                 rtc0 = &i2c_rtc;
  19                 rtc1 = &rtc;
  20         };
  21
  22         cpus {
  23                 cpu@0 {
  24                         cpu0-supply = <&vdd1_reg>;
  25                 };
  26         };
  27
  28         memory@80000000 {
  29                 device_type = "memory";
  30                 reg = <0x80000000 0x10000000>; /* 256 MB */
  31         };
  32
  33         regulators {
  34                 compatible = "simple-bus";
  35
  36                 vcc5v: fixedregulator0 {
  37                         compatible = "regulator-fixed";
  38                         regulator-name = "vcc5v";
  39                         regulator-min-microvolt = <5000000>;
  40                         regulator-max-microvolt = <5000000>;
  41                         regulator-boot-on;
  42                         regulator-always-on;
  43                 };
  44         };
  45 };
  46
  47 /* Crypto Module */
  48 &aes {
  49         status = "okay";
  50 };
  51
  52 &sham {
  53         status = "okay";
  54 };
  55
  56 /* Ethernet */
  57 &am33xx_pinmux {
  58         ethernet0_pins: pinmux_ethernet0 {
  59                 pinctrl-single,pins = <
  60                         AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_crs.rmii1_crs_dv */
  61                         AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_rxerr.rmii1_rxerr */
  62                         AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1)             /* mii1_txen.rmii1_txen */
  63                         AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1)             /* mii1_txd1.rmii1_txd1 */
  64                         AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1)             /* mii1_txd0.rmii1_txd0 */
  65                         AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_rxd1.rmii1_rxd1 */
  66                         AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_rxd0.rmii1_rxd0 */
  67                         AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* rmii1_refclk.rmii1_refclk */
  68                 >;
  69         };
  70
  71         mdio_pins: pinmux_mdio {
  72                 pinctrl-single,pins = <
  73                         /* MDIO */
  74                         AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
  75                         AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
  76                 >;
  77         };
  78 };
  79
  80 &cpsw_emac0 {
  81         phy_id = <&davinci_mdio>, <0>;
  82         phy-mode = "rmii";
  83         dual_emac_res_vlan = <1>;
  84 };
  85
  86 &davinci_mdio {
  87         pinctrl-names = "default";
  88         pinctrl-0 = <&mdio_pins>;
  89         status = "okay";
  90 };
  91
  92 &mac {
  93         slaves = <1>;
  94         pinctrl-names = "default";
  95         pinctrl-0 = <&ethernet0_pins>;
  96         status = "okay";
  97 };
  98
  99 &phy_sel {
 100         rmii-clock-ext;
 101 };
 102
 103 /* I2C Busses */
 104 &am33xx_pinmux {
 105         i2c0_pins: pinmux_i2c0 {
 106                 pinctrl-single,pins = <
 107                         AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)      /* i2c0_sda.i2c0_sda */
 108                         AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)      /* i2c0_scl.i2c0_scl */
 109                 >;
 110         };
 111 };
 112
 113 &i2c0 {
 114         pinctrl-names = "default";
 115         pinctrl-0 = <&i2c0_pins>;
 116         clock-frequency = <400000>;
 117         status = "okay";
 118
 119         tps: pmic@2d {
 120                 reg = <0x2d>;
 121         };
 122
 123         i2c_eeprom: eeprom@52 {
 124                 compatible = "atmel,24c32";
 125                 pagesize = <32>;
 126                 reg = <0x52>;
 127                 status = "disabled";
 128         };
 129
 130         i2c_rtc: rtc@68 {
 131                 compatible = "rv4162";
 132                 reg = <0x68>;
 133                 status = "disabled";
 134         };
 135 };
 136
 137 /* NAND memory */
 138 &am33xx_pinmux {
 139                 nandflash_pins: pinmux_nandflash {
 140                         pinctrl-single,pins = <
 141                         AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad0.gpmc_ad0 */
 142                         AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad1.gpmc_ad1 */
 143                         AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad2.gpmc_ad2 */
 144                         AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad3.gpmc_ad3 */
 145                         AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad4.gpmc_ad4 */
 146                         AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad5.gpmc_ad5 */
 147                         AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad6.gpmc_ad6 */
 148                         AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_ad7.gpmc_ad7 */
 149                         AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
 150                         AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn0.gpmc_csn0 */
 151                         AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)             /* gpmc_advn_ale.gpmc_advn_ale */
 152                         AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)             /* gpmc_oen_ren.gpmc_oen_ren */
 153                         AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)             /* gpmc_wen.gpmc_wen */
 154                         AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_be0n_cle.gpmc_be0n_cle */
 155                 >;
 156         };
 157 };
 158
 159 &elm {
 160         status = "okay";
 161 };
 162
 163 &gpmc {
 164         status = "okay";
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&nandflash_pins>;
 167         ranges = <0 0 0x08000000 0x1000000>;   /* CS0: NAND */
 168         nandflash: nand@0,0 {
 169                 compatible = "ti,omap2-nand";
 170                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 171                 interrupt-parent = <&gpmc>;
 172                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 173                              <1 IRQ_TYPE_NONE>; /* termcount */
 174                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 175                 nand-bus-width = <8>;
 176                 ti,nand-ecc-opt = "bch8";
 177                 gpmc,device-nand = "true";
 178                 gpmc,device-width = <1>;
 179                 gpmc,sync-clk-ps = <0>;
 180                 gpmc,cs-on-ns = <0>;
 181                 gpmc,cs-rd-off-ns = <30>;
 182                 gpmc,cs-wr-off-ns = <30>;
 183                 gpmc,adv-on-ns = <0>;
 184                 gpmc,adv-rd-off-ns = <30>;
 185                 gpmc,adv-wr-off-ns = <30>;
 186                 gpmc,we-on-ns = <0>;
 187                 gpmc,we-off-ns = <20>;
 188                 gpmc,oe-on-ns = <10>;
 189                 gpmc,oe-off-ns = <30>;
 190                 gpmc,access-ns = <30>;
 191                 gpmc,rd-cycle-ns = <30>;
 192                 gpmc,wr-cycle-ns = <30>;
 193                 gpmc,bus-turnaround-ns = <0>;
 194                 gpmc,cycle2cycle-delay-ns = <50>;
 195                 gpmc,cycle2cycle-diffcsen;
 196                 gpmc,clk-activation-ns = <0>;
 197                 gpmc,wr-access-ns = <30>;
 198                 gpmc,wr-data-mux-bus-ns = <0>;
 199
 200                 ti,elm-id = <&elm>;
 201
 202                 #address-cells = <1>;
 203                 #size-cells = <1>;
 204
 205                 partition@0 {
 206                         label = "xload";
 207                         reg = <0x0 0x20000>;
 208                 };
 209                 partition@1 {
 210                         label = "xload_backup1";
 211                         reg = <0x20000 0x20000>;
 212                 };
 213                 partition@2 {
 214                         label = "xload_backup2";
 215                         reg = <0x40000 0x20000>;
 216                 };
 217                 partition@3 {
 218                         label = "xload_backup3";
 219                         reg = <0x60000 0x20000>;
 220                 };
 221                 partition@4 {
 222                         label = "barebox";
 223                         reg = <0x80000 0x80000>;
 224                 };
 225                 partition@5 {
 226                         label = "bareboxenv";
 227                         reg = <0x100000 0x40000>;
 228                 };
 229                 partition@6 {
 230                         label = "oftree";
 231                         reg = <0x140000 0x40000>;
 232                 };
 233                 partition@7 {
 234                         label = "kernel";
 235                         reg = <0x180000 0x800000>;
 236                 };
 237                 partition@8 {
 238                         label = "root";
 239                         reg = <0x980000 0x0>;
 240                 };
 241         };
 242 };
 243
 244 /* Power */
 245 #include "tps65910.dtsi"
 246
 247 &tps {
 248         vcc1-supply = <&vcc5v>;
 249         vcc2-supply = <&vcc5v>;
 250         vcc3-supply = <&vcc5v>;
 251         vcc4-supply = <&vcc5v>;
 252         vcc5-supply = <&vcc5v>;
 253         vcc6-supply = <&vcc5v>;
 254         vcc7-supply = <&vcc5v>;
 255         vccio-supply = <&vcc5v>;
 256
 257         regulators {
 258                 vrtc_reg: regulator@0 {
 259                         regulator-always-on;
 260                 };
 261
 262                 vio_reg: regulator@1 {
 263                         regulator-always-on;
 264                 };
 265
 266                 vdd1_reg: regulator@2 {
 267                         /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
 268                         regulator-name = "vdd_mpu";
 269                         regulator-min-microvolt = <912500>;
 270                         regulator-max-microvolt = <1378000>;
 271                         regulator-boot-on;
 272                         regulator-always-on;
 273                 };
 274
 275                 vdd2_reg: regulator@3 {
 276                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 277                         regulator-name = "vdd_core";
 278                         regulator-min-microvolt = <912500>;
 279                         regulator-max-microvolt = <1150000>;
 280                         regulator-boot-on;
 281                         regulator-always-on;
 282                 };
 283
 284                 vdd3_reg: regulator@4 {
 285                         regulator-always-on;
 286                 };
 287
 288                 vdig1_reg: regulator@5 {
 289                         regulator-name = "vdig1_1p8v";
 290                         regulator-min-microvolt = <1800000>;
 291                         regulator-max-microvolt = <1800000>;
 292                 };
 293
 294                 vdig2_reg: regulator@6 {
 295                         regulator-always-on;
 296                 };
 297
 298                 vpll_reg: regulator@7 {
 299                         regulator-always-on;
 300                 };
 301
 302                 vdac_reg: regulator@8 {
 303                         regulator-always-on;
 304                 };
 305
 306                 vaux1_reg: regulator@9 {
 307                         regulator-always-on;
 308                 };
 309
 310                 vaux2_reg: regulator@10 {
 311                         regulator-always-on;
 312                 };
 313
 314                 vaux33_reg: regulator@11 {
 315                         regulator-always-on;
 316                 };
 317
 318                 vmmc_reg: regulator@12 {
 319                         regulator-min-microvolt = <3300000>;
 320                         regulator-max-microvolt = <3300000>;
 321                         regulator-always-on;
 322                 };
 323         };
 324 };
 325
 326 /* SPI Busses */
 327 &am33xx_pinmux {
 328         spi0_pins: pinmux_spi0 {
 329                 pinctrl-single,pins = <
 330                         AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* spi0_clk.spi0_clk */
 331                         AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* spi0_d0.spi0_d0 */
 332                         AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)       /* spi0_d1.spi0_d1 */
 333                         AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)       /* spi0_cs0.spi0_cs0 */
 334                 >;
 335         };
 336 };
 337
 338 &spi0 {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&spi0_pins>;
 341         status = "okay";
 342
 343         serial_flash: m25p80@0 {
 344                 compatible = "m25p80";
 345                 spi-max-frequency = <48000000>;
 346                 reg = <0x0>;
 347                 m25p,fast-read;
 348                 status = "disabled";
 349                 #address-cells = <1>;
 350                 #size-cells = <1>;
 351
 352                 partition@0 {
 353                         label = "xload";
 354                         reg = <0x0 0x20000>;
 355                 };
 356                 partition@1 {
 357                         label = "barebox";
 358                         reg = <0x20000 0x80000>;
 359                 };
 360                 partition@2 {
 361                         label = "bareboxenv";
 362                         reg = <0xa0000 0x20000>;
 363                 };
 364                 partition@3 {
 365                         label = "oftree";
 366                         reg = <0xc0000 0x20000>;
 367                 };
 368                 partition@4 {
 369                         label = "kernel";
 370                         reg = <0xe0000 0x0>;
 371                 };
 372         };
 373 };