arch/arm/boot/dts/am43x-epos-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /* AM43x EPOS EVM */
  10
  11 /dts-v1/;
  12
  13 #include "am4372.dtsi"
  14 #include <dt-bindings/pinctrl/am43xx.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pwm/pwm.h>
  17 #include <dt-bindings/sound/tlv320aic31xx-micbias.h>
  18
  19 / {
  20         model = "TI AM43x EPOS EVM";
  21         compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43";
  22
  23         aliases {
  24                 display0 = &lcd0;
  25         };
  26
  27         vmmcsd_fixed: fixedregulator-sd {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "vmmcsd_fixed";
  30                 regulator-min-microvolt = <3300000>;
  31                 regulator-max-microvolt = <3300000>;
  32                 enable-active-high;
  33         };
  34
  35         vbat: fixedregulator0 {
  36                 compatible = "regulator-fixed";
  37                 regulator-name = "vbat";
  38                 regulator-min-microvolt = <5000000>;
  39                 regulator-max-microvolt = <5000000>;
  40                 regulator-boot-on;
  41         };
  42
  43         lcd0: display {
  44                 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
  45                 label = "lcd";
  46
  47                 panel-timing {
  48                         clock-frequency = <33000000>;
  49                         hactive = <800>;
  50                         vactive = <480>;
  51                         hfront-porch = <210>;
  52                         hback-porch = <16>;
  53                         hsync-len = <30>;
  54                         vback-porch = <10>;
  55                         vfront-porch = <22>;
  56                         vsync-len = <13>;
  57                         hsync-active = <0>;
  58                         vsync-active = <0>;
  59                         de-active = <1>;
  60                         pixelclk-active = <1>;
  61                 };
  62
  63                 port {
  64                         lcd_in: endpoint {
  65                                 remote-endpoint = <&dpi_out>;
  66                         };
  67                 };
  68         };
  69
  70         matrix_keypad: matrix_keypad0 {
  71                 compatible = "gpio-matrix-keypad";
  72                 debounce-delay-ms = <5>;
  73                 col-scan-delay-us = <2>;
  74
  75                 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH         /* Bank0, pin12 */
  76                              &gpio0 13 GPIO_ACTIVE_HIGH         /* Bank0, pin13 */
  77                              &gpio0 14 GPIO_ACTIVE_HIGH         /* Bank0, pin14 */
  78                              &gpio0 15 GPIO_ACTIVE_HIGH>;       /* Bank0, pin15 */
  79
  80                 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH          /* Bank3, pin9 */
  81                              &gpio3 10 GPIO_ACTIVE_HIGH         /* Bank3, pin10 */
  82                              &gpio2 18 GPIO_ACTIVE_HIGH         /* Bank2, pin18 */
  83                              &gpio2 19 GPIO_ACTIVE_HIGH>;       /* Bank2, pin19 */
  84
  85                 linux,keymap = <0x00000201      /* P1 */
  86                         0x01000204      /* P4 */
  87                         0x02000207      /* P7 */
  88                         0x0300020a      /* NUMERIC_STAR */
  89                         0x00010202      /* P2 */
  90                         0x01010205      /* P5 */
  91                         0x02010208      /* P8 */
  92                         0x03010200      /* P0 */
  93                         0x00020203      /* P3 */
  94                         0x01020206      /* P6 */
  95                         0x02020209      /* P9 */
  96                         0x0302020b      /* NUMERIC_POUND */
  97                         0x00030067      /* UP */
  98                         0x0103006a      /* RIGHT */
  99                         0x0203006c      /* DOWN */
 100                         0x03030069>;    /* LEFT */
 101         };
 102
 103         backlight {
 104                 compatible = "pwm-backlight";
 105                 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
 106                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
 107                 default-brightness-level = <8>;
 108         };
 109
 110         sound0: sound0 {
 111                 compatible = "simple-audio-card";
 112                 simple-audio-card,name = "AM43-EPOS-EVM";
 113                 simple-audio-card,widgets =
 114                         "Microphone", "Microphone Jack",
 115                         "Headphone", "Headphone Jack",
 116                         "Speaker", "Speaker";
 117                 simple-audio-card,routing =
 118                         "MIC1LP", "Microphone Jack",
 119                         "MIC1RP", "Microphone Jack",
 120                         "MIC1LP", "MICBIAS",
 121                         "MIC1RP", "MICBIAS",
 122                         "Headphone Jack", "HPL",
 123                         "Headphone Jack", "HPR",
 124                         "Speaker", "SPL",
 125                         "Speaker", "SPR";
 126                 simple-audio-card,format = "dsp_b";
 127                 simple-audio-card,bitclock-master = <&sound0_master>;
 128                 simple-audio-card,frame-master = <&sound0_master>;
 129                 simple-audio-card,bitclock-inversion;
 130
 131                 simple-audio-card,cpu {
 132                         sound-dai = <&mcasp1>;
 133                         system-clock-frequency = <12000000>;
 134                 };
 135
 136                 sound0_master: simple-audio-card,codec {
 137                         sound-dai = <&tlv320aic3111>;
 138                         system-clock-frequency = <12000000>;
 139                 };
 140         };
 141 };
 142
 143 &am43xx_pinmux {
 144                 cpsw_default: cpsw_default {
 145                         pinctrl-single,pins = <
 146                                 /* Slave 1 */
 147                                 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_crs.rmii1_crs */
 148                                 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_rxerr.rmii1_rxerr */
 149                                 AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txen.rmii1_txen */
 150                                 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_rxdv.rmii1_rxdv */
 151                                 AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txd1.rmii1_txd1 */
 152                                 AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txd0.rmii1_txd0 */
 153                                 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_rxd1.rmii1_rxd1 */
 154                                 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_rxd0.rmii1_rxd0 */
 155                                 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* rmii1_refclk.rmii1_refclk */
 156                         >;
 157                 };
 158
 159                 cpsw_sleep: cpsw_sleep {
 160                         pinctrl-single,pins = <
 161                                 /* Slave 1 reset value */
 162                                 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 163                                 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
 164                                 AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
 165                                 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
 166                                 AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
 167                                 AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
 168                                 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 169                                 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
 170                                 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
 171                         >;
 172                 };
 173
 174                 davinci_mdio_default: davinci_mdio_default {
 175                         pinctrl-single,pins = <
 176                                 /* MDIO */
 177                                 AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
 178                                 AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
 179                         >;
 180                 };
 181
 182                 davinci_mdio_sleep: davinci_mdio_sleep {
 183                         pinctrl-single,pins = <
 184                                 /* MDIO reset value */
 185                                 AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
 186                                 AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 187                         >;
 188                 };
 189
 190                 i2c0_pins: pinmux_i2c0_pins {
 191                         pinctrl-single,pins = <
 192                                 AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
 193                                 AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
 194                         >;
 195                 };
 196
 197                 nand_flash_x8: nand_flash_x8 {
 198                         pinctrl-single,pins = <
 199                                 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gpmc_a0.SELQSPIorNAND/GPIO */
 200                                 AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad0.gpmc_ad0 */
 201                                 AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad1.gpmc_ad1 */
 202                                 AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad2.gpmc_ad2 */
 203                                 AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad3.gpmc_ad3 */
 204                                 AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
 205                                 AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
 206                                 AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
 207                                 AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
 208                                 AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
 209                                 AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_wpn.gpmc_wpn */
 210                                 AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn0.gpmc_csn0  */
 211                                 AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)             /* gpmc_advn_ale.gpmc_advn_ale */
 212                                 AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)             /* gpmc_oen_ren.gpmc_oen_ren */
 213                                 AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)             /* gpmc_wen.gpmc_wen */
 214                                 AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_be0n_cle.gpmc_be0n_cle */
 215                         >;
 216                 };
 217
 218                 ecap0_pins: backlight_pins {
 219                         pinctrl-single,pins = <
 220                                 AM4372_IOPAD(0x964, MUX_MODE0)         /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 221                         >;
 222                 };
 223
 224                 i2c2_pins: pinmux_i2c2_pins {
 225                         pinctrl-single,pins = <
 226                                 AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_sda.i2c2_sda */
 227                                 AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_scl.i2c2_scl */
 228                         >;
 229                 };
 230
 231                 spi0_pins: pinmux_spi0_pins {
 232                         pinctrl-single,pins = <
 233                                 AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0)           /* spi0_clk.spi0_clk */
 234                                 AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0)           /* spi0_d0.spi0_d0 */
 235                                 AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0)           /* spi0_d1.spi0_d1 */
 236                                 AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0)          /* spi0_cs0.spi0_cs0 */
 237                         >;
 238                 };
 239
 240                 spi1_pins: pinmux_spi1_pins {
 241                         pinctrl-single,pins = <
 242                                 AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3)           /* mcasp0_aclkx.spi1_clk */
 243                                 AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3)           /* mcasp0_fsx.spi1_d0 */
 244                                 AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3)           /* mcasp0_axr0.spi1_d1 */
 245                                 AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3)          /* mcasp0_ahclkr.spi1_cs0 */
 246                         >;
 247                 };
 248
 249                 mmc1_pins: pinmux_mmc1_pins {
 250                         pinctrl-single,pins = <
 251                                 AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 252                         >;
 253                 };
 254
 255                 qspi1_default: qspi1_default {
 256                         pinctrl-single,pins = <
 257                                 AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3)
 258                                 AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2)
 259                                 AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3)
 260                                 AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3)
 261                                 AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3)
 262                                 AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3)
 263                         >;
 264                 };
 265
 266                 pixcir_ts_pins: pixcir_ts_pins {
 267                         pinctrl-single,pins = <
 268                                 AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7)       /* gpmc_a1.gpio1_17 */
 269                         >;
 270                 };
 271
 272                 hdq_pins: pinmux_hdq_pins {
 273                         pinctrl-single,pins = <
 274                                 AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1)    /* cam1_wen.hdq_gpio */
 275                         >;
 276                 };
 277
 278                 dss_pins: dss_pins {
 279                         pinctrl-single,pins = <
 280                                 AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
 281                                 AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
 282                                 AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
 283                                 AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
 284                                 AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
 285                                 AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
 286                                 AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
 287                                 AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
 288                                 AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
 289                                 AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 290                                 AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 291                                 AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
 292                                 AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
 293                                 AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 294                                 AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 295                                 AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
 296                                 AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
 297                                 AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 298                                 AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 299                                 AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
 300                                 AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
 301                                 AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 302                                 AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 303                                 AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
 304                                 AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
 305                                 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
 306                                 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
 307                                 AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
 308                         >;
 309                 };
 310
 311                 display_mux_pins: display_mux_pins {
 312                         pinctrl-single,pins = <
 313                                 /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
 314                                 AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7)
 315                         >;
 316                 };
 317
 318                 vpfe1_pins_default: vpfe1_pins_default {
 319                         pinctrl-single,pins = <
 320                                 AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0 */
 321                                 AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0 */
 322                                 AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0 */
 323                                 AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0 */
 324                                 AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0 */
 325                                 AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0 */
 326                                 AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0 */
 327                                 AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0 */
 328                                 AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0 */
 329                                 AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0 */
 330                                 AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0 */
 331                                 AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0 */
 332                                 AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0 */
 333                         >;
 334                 };
 335
 336                 vpfe1_pins_sleep: vpfe1_pins_sleep {
 337                         pinctrl-single,pins = <
 338                                 AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 339                                 AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 340                                 AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 341                                 AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 342                                 AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 343                                 AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 344                                 AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 345                                 AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 346                                 AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 347                                 AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 348                                 AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 349                                 AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 350                                 AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 351                         >;
 352                 };
 353
 354                 mcasp1_pins: mcasp1_pins {
 355                         pinctrl-single,pins = <
 356                                 AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */
 357                                 AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */
 358                                 AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */
 359                                 AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */
 360                         >;
 361                 };
 362
 363                 mcasp1_sleep_pins: mcasp1_sleep_pins {
 364                         pinctrl-single,pins = <
 365                                 AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
 366                                 AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7)
 367                                 AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
 368                                 AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7)
 369                         >;
 370                 };
 371 };
 372
 373 &mmc1 {
 374         status = "okay";
 375         vmmc-supply = <&vmmcsd_fixed>;
 376         bus-width = <4>;
 377         pinctrl-names = "default";
 378         pinctrl-0 = <&mmc1_pins>;
 379         cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 380 };
 381
 382 &mac {
 383         pinctrl-names = "default", "sleep";
 384         pinctrl-0 = <&cpsw_default>;
 385         pinctrl-1 = <&cpsw_sleep>;
 386         status = "okay";
 387 };
 388
 389 &davinci_mdio {
 390         pinctrl-names = "default", "sleep";
 391         pinctrl-0 = <&davinci_mdio_default>;
 392         pinctrl-1 = <&davinci_mdio_sleep>;
 393         status = "okay";
 394 };
 395
 396 &cpsw_emac0 {
 397         phy_id = <&davinci_mdio>, <16>;
 398         phy-mode = "rmii";
 399 };
 400
 401 &cpsw_emac1 {
 402         phy_id = <&davinci_mdio>, <1>;
 403         phy-mode = "rmii";
 404 };
 405
 406 &phy_sel {
 407         rmii-clock-ext;
 408 };
 409
 410 &i2c0 {
 411         status = "okay";
 412         pinctrl-names = "default";
 413         pinctrl-0 = <&i2c0_pins>;
 414         clock-frequency = <400000>;
 415
 416         tps65218: tps65218@24 {
 417                 reg = <0x24>;
 418                 compatible = "ti,tps65218";
 419                 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
 420                 interrupt-controller;
 421                 #interrupt-cells = <2>;
 422
 423                 dcdc1: regulator-dcdc1 {
 424                         regulator-name = "vdd_core";
 425                         regulator-min-microvolt = <912000>;
 426                         regulator-max-microvolt = <1144000>;
 427                         regulator-boot-on;
 428                         regulator-always-on;
 429                 };
 430
 431                 dcdc2: regulator-dcdc2 {
 432                         regulator-name = "vdd_mpu";
 433                         regulator-min-microvolt = <912000>;
 434                         regulator-max-microvolt = <1378000>;
 435                         regulator-boot-on;
 436                         regulator-always-on;
 437                 };
 438
 439                 dcdc3: regulator-dcdc3 {
 440                         regulator-name = "vdcdc3";
 441                         regulator-min-microvolt = <1500000>;
 442                         regulator-max-microvolt = <1500000>;
 443                         regulator-boot-on;
 444                         regulator-always-on;
 445                 };
 446
 447                 dcdc4: regulator-dcdc4 {
 448                         regulator-name = "vdcdc4";
 449                         regulator-min-microvolt = <3300000>;
 450                         regulator-max-microvolt = <3300000>;
 451                         regulator-boot-on;
 452                         regulator-always-on;
 453                 };
 454
 455                 dcdc5: regulator-dcdc5 {
 456                         regulator-name = "v1_0bat";
 457                         regulator-min-microvolt = <1000000>;
 458                         regulator-max-microvolt = <1000000>;
 459                 };
 460
 461                 dcdc6: regulator-dcdc6 {
 462                         regulator-name = "v1_8bat";
 463                         regulator-min-microvolt = <1800000>;
 464                         regulator-max-microvolt = <1800000>;
 465                 };
 466
 467                 ldo1: regulator-ldo1 {
 468                         regulator-min-microvolt = <1800000>;
 469                         regulator-max-microvolt = <1800000>;
 470                         regulator-boot-on;
 471                         regulator-always-on;
 472                 };
 473         };
 474
 475         at24@50 {
 476                 compatible = "at24,24c256";
 477                 pagesize = <64>;
 478                 reg = <0x50>;
 479         };
 480
 481         pixcir_ts@5c {
 482                 compatible = "pixcir,pixcir_tangoc";
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&pixcir_ts_pins>;
 485                 reg = <0x5c>;
 486                 interrupt-parent = <&gpio1>;
 487                 interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
 488
 489                 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
 490
 491                 touchscreen-size-x = <1024>;
 492                 touchscreen-size-y = <600>;
 493         };
 494
 495         tlv320aic3111: tlv320aic3111@18 {
 496                 #sound-dai-cells = <0>;
 497                 compatible = "ti,tlv320aic3111";
 498                 reg = <0x18>;
 499                 status = "okay";
 500
 501                 ai31xx-micbias-vg = <MICBIAS_2_0V>;
 502
 503                 /* Regulators */
 504                 HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
 505                 SPRVDD-supply = <&vbat>; /* vbat */
 506                 SPLVDD-supply = <&vbat>; /* vbat */
 507                 AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
 508                 IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
 509                 DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
 510         };
 511 };
 512
 513 &i2c2 {
 514         pinctrl-names = "default";
 515         pinctrl-0 = <&i2c2_pins>;
 516         status = "okay";
 517 };
 518
 519 &gpio0 {
 520         status = "okay";
 521 };
 522
 523 &gpio1 {
 524         status = "okay";
 525 };
 526
 527 &gpio2 {
 528         pinctrl-names = "default";
 529         pinctrl-0 = <&display_mux_pins>;
 530         status = "okay";
 531
 532         p1 {
 533                 /*
 534                  * SelLCDorHDMI selects between display and audio paths:
 535                  * Low: HDMI display with audio via HDMI
 536                  * High: LCD display with analog audio via aic3111 codec
 537                  */
 538                 gpio-hog;
 539                 gpios = <1 GPIO_ACTIVE_HIGH>;
 540                 output-high;
 541                 line-name = "SelLCDorHDMI";
 542         };
 543 };
 544
 545 &gpio3 {
 546         status = "okay";
 547 };
 548
 549 &elm {
 550         status = "okay";
 551 };
 552
 553 &gpmc {
 554         status = "okay";        /* Disable QSPI when enabling GPMC (NAND) */
 555         pinctrl-names = "default";
 556         pinctrl-0 = <&nand_flash_x8>;
 557         ranges = <0 0 0x08000000 0x01000000>;   /* CS0 space. Min partition = 16MB */
 558         nand@0,0 {
 559                 compatible = "ti,omap2-nand";
 560                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 561                 interrupt-parent = <&gpmc>;
 562                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 563                              <1 IRQ_TYPE_NONE>; /* termcount */
 564                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;  /* gpmc_wait0 */
 565                 ti,nand-ecc-opt = "bch16";
 566                 ti,elm-id = <&elm>;
 567                 nand-bus-width = <8>;
 568                 gpmc,device-width = <1>;
 569                 gpmc,sync-clk-ps = <0>;
 570                 gpmc,cs-on-ns = <0>;
 571                 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
 572                 gpmc,cs-wr-off-ns = <40>;
 573                 gpmc,adv-on-ns = <0>;  /* cs-on-ns */
 574                 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
 575                 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
 576                 gpmc,we-on-ns = <0>;   /* cs-on-ns */
 577                 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
 578                 gpmc,oe-on-ns = <3>;  /* cs-on-ns + tRR + 2 */
 579                 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
 580                 gpmc,access-ns = <30>; /* tCEA + 4*/
 581                 gpmc,rd-cycle-ns = <40>;
 582                 gpmc,wr-cycle-ns = <40>;
 583                 gpmc,bus-turnaround-ns = <0>;
 584                 gpmc,cycle2cycle-delay-ns = <0>;
 585                 gpmc,clk-activation-ns = <0>;
 586                 gpmc,wr-access-ns = <40>;
 587                 gpmc,wr-data-mux-bus-ns = <0>;
 588                 /* MTD partition table */
 589                 /* All SPL-* partitions are sized to minimal length
 590                  * which can be independently programmable. For
 591                  * NAND flash this is equal to size of erase-block */
 592                 #address-cells = <1>;
 593                 #size-cells = <1>;
 594                 partition@0 {
 595                         label = "NAND.SPL";
 596                         reg = <0x00000000 0x00040000>;
 597                 };
 598                 partition@1 {
 599                         label = "NAND.SPL.backup1";
 600                         reg = <0x00040000 0x00040000>;
 601                 };
 602                 partition@2 {
 603                         label = "NAND.SPL.backup2";
 604                         reg = <0x00080000 0x00040000>;
 605                 };
 606                 partition@3 {
 607                         label = "NAND.SPL.backup3";
 608                         reg = <0x000C0000 0x00040000>;
 609                 };
 610                 partition@4 {
 611                         label = "NAND.u-boot-spl-os";
 612                         reg = <0x00100000 0x00080000>;
 613                 };
 614                 partition@5 {
 615                         label = "NAND.u-boot";
 616                         reg = <0x00180000 0x00100000>;
 617                 };
 618                 partition@6 {
 619                         label = "NAND.u-boot-env";
 620                         reg = <0x00280000 0x00040000>;
 621                 };
 622                 partition@7 {
 623                         label = "NAND.u-boot-env.backup1";
 624                         reg = <0x002C0000 0x00040000>;
 625                 };
 626                 partition@8 {
 627                         label = "NAND.kernel";
 628                         reg = <0x00300000 0x00700000>;
 629                 };
 630                 partition@9 {
 631                         label = "NAND.file-system";
 632                         reg = <0x00a00000 0x1f600000>;
 633                 };
 634         };
 635 };
 636
 637 &epwmss0 {
 638         status = "okay";
 639 };
 640
 641 &tscadc {
 642         status = "okay";
 643
 644         adc {
 645                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 646         };
 647 };
 648
 649 &ecap0 {
 650                 status = "okay";
 651                 pinctrl-names = "default";
 652                 pinctrl-0 = <&ecap0_pins>;
 653 };
 654
 655 &spi0 {
 656         pinctrl-names = "default";
 657         pinctrl-0 = <&spi0_pins>;
 658         status = "okay";
 659 };
 660
 661 &spi1 {
 662         pinctrl-names = "default";
 663         pinctrl-0 = <&spi1_pins>;
 664         status = "okay";
 665 };
 666
 667 &usb2_phy1 {
 668         status = "okay";
 669 };
 670
 671 &usb1 {
 672         dr_mode = "peripheral";
 673         status = "okay";
 674 };
 675
 676 &usb2_phy2 {
 677         status = "okay";
 678 };
 679
 680 &usb2 {
 681         dr_mode = "host";
 682         status = "okay";
 683 };
 684
 685 &qspi {
 686         status = "disabled";    /* Disable GPMC (NAND) when enabling QSPI */
 687         pinctrl-names = "default";
 688         pinctrl-0 = <&qspi1_default>;
 689
 690         spi-max-frequency = <48000000>;
 691         m25p80@0 {
 692                 compatible = "mx66l51235l";
 693                 spi-max-frequency = <48000000>;
 694                 reg = <0>;
 695                 spi-cpol;
 696                 spi-cpha;
 697                 spi-tx-bus-width = <1>;
 698                 spi-rx-bus-width = <4>;
 699                 #address-cells = <1>;
 700                 #size-cells = <1>;
 701
 702                 /* MTD partition table.
 703                  * The ROM checks the first 512KiB
 704                  * for a valid file to boot(XIP).
 705                  */
 706                 partition@0 {
 707                         label = "QSPI.U_BOOT";
 708                         reg = <0x00000000 0x000080000>;
 709                 };
 710                 partition@1 {
 711                         label = "QSPI.U_BOOT.backup";
 712                         reg = <0x00080000 0x00080000>;
 713                 };
 714                 partition@2 {
 715                         label = "QSPI.U-BOOT-SPL_OS";
 716                         reg = <0x00100000 0x00010000>;
 717                 };
 718                 partition@3 {
 719                         label = "QSPI.U_BOOT_ENV";
 720                         reg = <0x00110000 0x00010000>;
 721                 };
 722                 partition@4 {
 723                         label = "QSPI.U-BOOT-ENV.backup";
 724                         reg = <0x00120000 0x00010000>;
 725                 };
 726                 partition@5 {
 727                         label = "QSPI.KERNEL";
 728                         reg = <0x00130000 0x0800000>;
 729                 };
 730                 partition@6 {
 731                         label = "QSPI.FILESYSTEM";
 732                         reg = <0x00930000 0x36D0000>;
 733                 };
 734         };
 735 };
 736
 737 &hdq {
 738         status = "okay";
 739         pinctrl-names = "default";
 740         pinctrl-0 = <&hdq_pins>;
 741 };
 742
 743 &dss {
 744         status = "ok";
 745
 746         pinctrl-names = "default";
 747         pinctrl-0 = <&dss_pins>;
 748
 749         port {
 750                 dpi_out: endpoint {
 751                         remote-endpoint = <&lcd_in>;
 752                         data-lines = <24>;
 753                 };
 754         };
 755 };
 756
 757 &vpfe1 {
 758         status = "okay";
 759         pinctrl-names = "default", "sleep";
 760         pinctrl-0 = <&vpfe1_pins_default>;
 761         pinctrl-1 = <&vpfe1_pins_sleep>;
 762
 763         port {
 764                 vpfe1_ep: endpoint {
 765                         /* remote-endpoint = <&sensor>; add once we have it */
 766                         ti,am437x-vpfe-interface = <0>;
 767                         bus-width = <8>;
 768                         hsync-active = <0>;
 769                         vsync-active = <0>;
 770                 };
 771         };
 772 };
 773
 774 &mcasp1 {
 775         #sound-dai-cells = <0>;
 776         pinctrl-names = "default", "sleep";
 777         pinctrl-0 = <&mcasp1_pins>;
 778         pinctrl-1 = <&mcasp1_sleep_pins>;
 779
 780         status = "okay";
 781
 782         op-mode = <0>;          /* MCASP_IIS_MODE */
 783         tdm-slots = <2>;
 784         /* 4 serializer */
 785         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 786                 1 2 0 0
 787         >;
 788         tx-num-evt = <32>;
 789         rx-num-evt = <32>;
 790 };
 791
 792 &synctimer_32kclk {
 793         assigned-clocks = <&mux_synctimer32k_ck>;
 794         assigned-clock-parents = <&clkdiv32k_ick>;
 795 };