arch/arm/boot/dts/armada-375.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 375 family SoC
   3  *
   4  * Copyright (C) 2014 Marvell
   5  *
   6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   7  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2.  This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include "skeleton.dtsi"
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/phy/phy.h>
  18
  19 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  20
  21 / {
  22         model = "Marvell Armada 375 family SoC";
  23         compatible = "marvell,armada375";
  24
  25         aliases {
  26                 gpio0 = &gpio0;
  27                 gpio1 = &gpio1;
  28                 gpio2 = &gpio2;
  29                 ethernet0 = &eth0;
  30                 ethernet1 = &eth1;
  31         };
  32
  33         clocks {
  34                 /* 2 GHz fixed main PLL */
  35                 mainpll: mainpll {
  36                         compatible = "fixed-clock";
  37                         #clock-cells = <0>;
  38                         clock-frequency = <2000000000>;
  39                 };
  40                 /* 25 MHz reference crystal */
  41                 refclk: oscillator {
  42                         compatible = "fixed-clock";
  43                         #clock-cells = <0>;
  44                         clock-frequency = <25000000>;
  45                 };
  46         };
  47
  48         cpus {
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51                 enable-method = "marvell,armada-375-smp";
  52
  53                 cpu@0 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a9";
  56                         reg = <0>;
  57                 };
  58                 cpu@1 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a9";
  61                         reg = <1>;
  62                 };
  63         };
  64
  65         soc {
  66                 compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
  67                 #address-cells = <2>;
  68                 #size-cells = <1>;
  69                 controller = <&mbusc>;
  70                 interrupt-parent = <&gic>;
  71                 pcie-mem-aperture = <0xe0000000 0x8000000>;
  72                 pcie-io-aperture  = <0xe8000000 0x100000>;
  73
  74                 bootrom {
  75                         compatible = "marvell,bootrom";
  76                         reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
  77                 };
  78
  79                 devbus-bootcs {
  80                         compatible = "marvell,mvebu-devbus";
  81                         reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
  82                         ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
  83                         #address-cells = <1>;
  84                         #size-cells = <1>;
  85                         clocks = <&coreclk 0>;
  86                         status = "disabled";
  87                 };
  88
  89                 devbus-cs0 {
  90                         compatible = "marvell,mvebu-devbus";
  91                         reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
  92                         ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
  93                         #address-cells = <1>;
  94                         #size-cells = <1>;
  95                         clocks = <&coreclk 0>;
  96                         status = "disabled";
  97                 };
  98
  99                 devbus-cs1 {
 100                         compatible = "marvell,mvebu-devbus";
 101                         reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
 102                         ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105                         clocks = <&coreclk 0>;
 106                         status = "disabled";
 107                 };
 108
 109                 devbus-cs2 {
 110                         compatible = "marvell,mvebu-devbus";
 111                         reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
 112                         ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
 113                         #address-cells = <1>;
 114                         #size-cells = <1>;
 115                         clocks = <&coreclk 0>;
 116                         status = "disabled";
 117                 };
 118
 119                 devbus-cs3 {
 120                         compatible = "marvell,mvebu-devbus";
 121                         reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
 122                         ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
 123                         #address-cells = <1>;
 124                         #size-cells = <1>;
 125                         clocks = <&coreclk 0>;
 126                         status = "disabled";
 127                 };
 128
 129                 internal-regs {
 130                         compatible = "simple-bus";
 131                         #address-cells = <1>;
 132                         #size-cells = <1>;
 133                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 134
 135                         L2: cache-controller@8000 {
 136                                 compatible = "arm,pl310-cache";
 137                                 reg = <0x8000 0x1000>;
 138                                 cache-unified;
 139                                 cache-level = <2>;
 140                         };
 141
 142                         scu@c000 {
 143                                 compatible = "arm,cortex-a9-scu";
 144                                 reg = <0xc000 0x58>;
 145                         };
 146
 147                         timer@c600 {
 148                                 compatible = "arm,cortex-a9-twd-timer";
 149                                 reg = <0xc600 0x20>;
 150                                 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
 151                                 clocks = <&coreclk 2>;
 152                         };
 153
 154                         gic: interrupt-controller@d000 {
 155                                 compatible = "arm,cortex-a9-gic";
 156                                 #interrupt-cells = <3>;
 157                                 #size-cells = <0>;
 158                                 interrupt-controller;
 159                                 reg = <0xd000 0x1000>,
 160                                       <0xc100 0x100>;
 161                         };
 162
 163                         mdio {
 164                                 #address-cells = <1>;
 165                                 #size-cells = <0>;
 166                                 compatible = "marvell,orion-mdio";
 167                                 reg = <0xc0054 0x4>;
 168                                 clocks = <&gateclk 19>;
 169                         };
 170
 171                         /* Network controller */
 172                         ethernet@f0000 {
 173                                 compatible = "marvell,armada-375-pp2";
 174                                 reg = <0xf0000 0xa000>, /* Packet Processor regs */
 175                                       <0xc0000 0x3060>, /* LMS regs */
 176                                       <0xc4000 0x100>,  /* eth0 regs */
 177                                       <0xc5000 0x100>;  /* eth1 regs */
 178                                 clocks = <&gateclk 3>, <&gateclk 19>;
 179                                 clock-names = "pp_clk", "gop_clk";
 180                                 status = "disabled";
 181
 182                                 eth0: eth0@c4000 {
 183                                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 184                                         port-id = <0>;
 185                                         status = "disabled";
 186                                 };
 187
 188                                 eth1: eth1@c5000 {
 189                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 190                                         port-id = <1>;
 191                                         status = "disabled";
 192                                 };
 193                         };
 194
 195                         rtc@10300 {
 196                                 compatible = "marvell,orion-rtc";
 197                                 reg = <0x10300 0x20>;
 198                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 199                         };
 200
 201                         spi0: spi@10600 {
 202                                 compatible = "marvell,orion-spi";
 203                                 reg = <0x10600 0x50>;
 204                                 #address-cells = <1>;
 205                                 #size-cells = <0>;
 206                                 cell-index = <0>;
 207                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 208                                 clocks = <&coreclk 0>;
 209                                 status = "disabled";
 210                         };
 211
 212                         spi1: spi@10680 {
 213                                 compatible = "marvell,orion-spi";
 214                                 reg = <0x10680 0x50>;
 215                                 #address-cells = <1>;
 216                                 #size-cells = <0>;
 217                                 cell-index = <1>;
 218                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 219                                 clocks = <&coreclk 0>;
 220                                 status = "disabled";
 221                         };
 222
 223                         i2c0: i2c@11000 {
 224                                 compatible = "marvell,mv64xxx-i2c";
 225                                 reg = <0x11000 0x20>;
 226                                 #address-cells = <1>;
 227                                 #size-cells = <0>;
 228                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 229                                 timeout-ms = <1000>;
 230                                 clocks = <&coreclk 0>;
 231                                 status = "disabled";
 232                         };
 233
 234                         i2c1: i2c@11100 {
 235                                 compatible = "marvell,mv64xxx-i2c";
 236                                 reg = <0x11100 0x20>;
 237                                 #address-cells = <1>;
 238                                 #size-cells = <0>;
 239                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 240                                 timeout-ms = <1000>;
 241                                 clocks = <&coreclk 0>;
 242                                 status = "disabled";
 243                         };
 244
 245                         serial@12000 {
 246                                 compatible = "snps,dw-apb-uart";
 247                                 reg = <0x12000 0x100>;
 248                                 reg-shift = <2>;
 249                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 250                                 reg-io-width = <1>;
 251                                 clocks = <&coreclk 0>;
 252                                 status = "disabled";
 253                         };
 254
 255                         serial@12100 {
 256                                 compatible = "snps,dw-apb-uart";
 257                                 reg = <0x12100 0x100>;
 258                                 reg-shift = <2>;
 259                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 260                                 reg-io-width = <1>;
 261                                 clocks = <&coreclk 0>;
 262                                 status = "disabled";
 263                         };
 264
 265                         pinctrl {
 266                                 compatible = "marvell,mv88f6720-pinctrl";
 267                                 reg = <0x18000 0x24>;
 268
 269                                 i2c0_pins: i2c0-pins {
 270                                         marvell,pins = "mpp14",  "mpp15";
 271                                         marvell,function = "i2c0";
 272                                 };
 273
 274                                 i2c1_pins: i2c1-pins {
 275                                         marvell,pins = "mpp61",  "mpp62";
 276                                         marvell,function = "i2c1";
 277                                 };
 278
 279                                 nand_pins: nand-pins {
 280                                         marvell,pins = "mpp0", "mpp1", "mpp2",
 281                                                 "mpp3", "mpp4", "mpp5",
 282                                                 "mpp6", "mpp7", "mpp8",
 283                                                 "mpp9", "mpp10", "mpp11",
 284                                                 "mpp12", "mpp13";
 285                                         marvell,function = "nand";
 286                                 };
 287
 288                                 sdio_pins: sdio-pins {
 289                                         marvell,pins = "mpp24",  "mpp25", "mpp26",
 290                                                      "mpp27", "mpp28", "mpp29";
 291                                         marvell,function = "sd";
 292                                 };
 293
 294                                 spi0_pins: spi0-pins {
 295                                         marvell,pins = "mpp0",  "mpp1", "mpp4",
 296                                                      "mpp5", "mpp8", "mpp9";
 297                                         marvell,function = "spi0";
 298                                 };
 299                         };
 300
 301                         gpio0: gpio@18100 {
 302                                 compatible = "marvell,orion-gpio";
 303                                 reg = <0x18100 0x40>;
 304                                 ngpios = <32>;
 305                                 gpio-controller;
 306                                 #gpio-cells = <2>;
 307                                 interrupt-controller;
 308                                 #interrupt-cells = <2>;
 309                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 310                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 311                                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 312                                              <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 313                         };
 314
 315                         gpio1: gpio@18140 {
 316                                 compatible = "marvell,orion-gpio";
 317                                 reg = <0x18140 0x40>;
 318                                 ngpios = <32>;
 319                                 gpio-controller;
 320                                 #gpio-cells = <2>;
 321                                 interrupt-controller;
 322                                 #interrupt-cells = <2>;
 323                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 324                                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 325                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 326                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 327                         };
 328
 329                         gpio2: gpio@18180 {
 330                                 compatible = "marvell,orion-gpio";
 331                                 reg = <0x18180 0x40>;
 332                                 ngpios = <3>;
 333                                 gpio-controller;
 334                                 #gpio-cells = <2>;
 335                                 interrupt-controller;
 336                                 #interrupt-cells = <2>;
 337                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 338                         };
 339
 340                         system-controller@18200 {
 341                                 compatible = "marvell,armada-375-system-controller";
 342                                 reg = <0x18200 0x100>;
 343                         };
 344
 345                         gateclk: clock-gating-control@18220 {
 346                                 compatible = "marvell,armada-375-gating-clock";
 347                                 reg = <0x18220 0x4>;
 348                                 clocks = <&coreclk 0>;
 349                                 #clock-cells = <1>;
 350                         };
 351
 352                         usbcluster: usb-cluster@18400 {
 353                                 compatible = "marvell,armada-375-usb-cluster";
 354                                 reg = <0x18400 0x4>;
 355                                 #phy-cells = <1>;
 356                         };
 357
 358                         mbusc: mbus-controller@20000 {
 359                                 compatible = "marvell,mbus-controller";
 360                                 reg = <0x20000 0x100>, <0x20180 0x20>;
 361                         };
 362
 363                         mpic: interrupt-controller@20000 {
 364                                 compatible = "marvell,mpic";
 365                                 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 366                                 #interrupt-cells = <1>;
 367                                 #size-cells = <1>;
 368                                 interrupt-controller;
 369                                 msi-controller;
 370                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 371                         };
 372
 373                         timer@20300 {
 374                                 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
 375                                 reg = <0x20300 0x30>, <0x21040 0x30>;
 376                                 interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
 377                                                       <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
 378                                                       <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 379                                                       <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 380                                                       <&mpic 5>,
 381                                                       <&mpic 6>;
 382                                 clocks = <&coreclk 0>, <&refclk>;
 383                                 clock-names = "nbclk", "fixed";
 384                         };
 385
 386                         watchdog@20300 {
 387                                 compatible = "marvell,armada-375-wdt";
 388                                 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
 389                                 clocks = <&coreclk 0>, <&refclk>;
 390                                 clock-names = "nbclk", "fixed";
 391                         };
 392
 393                         cpurst@20800 {
 394                                 compatible = "marvell,armada-370-cpu-reset";
 395                                 reg = <0x20800 0x10>;
 396                         };
 397
 398                         coherency-fabric@21010 {
 399                                 compatible = "marvell,armada-375-coherency-fabric";
 400                                 reg = <0x21010 0x1c>;
 401                         };
 402
 403                         usb@50000 {
 404                                 compatible = "marvell,orion-ehci";
 405                                 reg = <0x50000 0x500>;
 406                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 407                                 clocks = <&gateclk 18>;
 408                                 phys = <&usbcluster PHY_TYPE_USB2>;
 409                                 phy-names = "usb";
 410                                 status = "disabled";
 411                         };
 412
 413                         usb@54000 {
 414                                 compatible = "marvell,orion-ehci";
 415                                 reg = <0x54000 0x500>;
 416                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 417                                 clocks = <&gateclk 26>;
 418                                 status = "disabled";
 419                         };
 420
 421                         usb3@58000 {
 422                                 compatible = "marvell,armada-375-xhci";
 423                                 reg = <0x58000 0x20000>,<0x5b880 0x80>;
 424                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 425                                 clocks = <&gateclk 16>;
 426                                 phys = <&usbcluster PHY_TYPE_USB3>;
 427                                 phy-names = "usb";
 428                                 status = "disabled";
 429                         };
 430
 431                         xor@60800 {
 432                                 compatible = "marvell,orion-xor";
 433                                 reg = <0x60800 0x100
 434                                        0x60A00 0x100>;
 435                                 clocks = <&gateclk 22>;
 436                                 status = "okay";
 437
 438                                 xor00 {
 439                                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 440                                         dmacap,memcpy;
 441                                         dmacap,xor;
 442                                 };
 443                                 xor01 {
 444                                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 445                                         dmacap,memcpy;
 446                                         dmacap,xor;
 447                                         dmacap,memset;
 448                                 };
 449                         };
 450
 451                         xor@60900 {
 452                                 compatible = "marvell,orion-xor";
 453                                 reg = <0x60900 0x100
 454                                        0x60b00 0x100>;
 455                                 clocks = <&gateclk 23>;
 456                                 status = "okay";
 457
 458                                 xor10 {
 459                                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 460                                         dmacap,memcpy;
 461                                         dmacap,xor;
 462                                 };
 463                                 xor11 {
 464                                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 465                                         dmacap,memcpy;
 466                                         dmacap,xor;
 467                                         dmacap,memset;
 468                                 };
 469                         };
 470
 471                         sata@a0000 {
 472                                 compatible = "marvell,orion-sata";
 473                                 reg = <0xa0000 0x5000>;
 474                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 475                                 clocks = <&gateclk 14>, <&gateclk 20>;
 476                                 clock-names = "0", "1";
 477                                 status = "disabled";
 478                         };
 479
 480                         nand@d0000 {
 481                                 compatible = "marvell,armada370-nand";
 482                                 reg = <0xd0000 0x54>;
 483                                 #address-cells = <1>;
 484                                 #size-cells = <1>;
 485                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 486                                 clocks = <&gateclk 11>;
 487                                 status = "disabled";
 488                         };
 489
 490                         mvsdio@d4000 {
 491                                 compatible = "marvell,orion-sdio";
 492                                 reg = <0xd4000 0x200>;
 493                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 494                                 clocks = <&gateclk 17>;
 495                                 bus-width = <4>;
 496                                 cap-sdio-irq;
 497                                 cap-sd-highspeed;
 498                                 cap-mmc-highspeed;
 499                                 status = "disabled";
 500                         };
 501
 502                         thermal@e8078 {
 503                                 compatible = "marvell,armada375-thermal";
 504                                 reg = <0xe8078 0x4>, <0xe807c 0x8>;
 505                                 status = "okay";
 506                         };
 507
 508                         coreclk: mvebu-sar@e8204 {
 509                                 compatible = "marvell,armada-375-core-clock";
 510                                 reg = <0xe8204 0x04>;
 511                                 #clock-cells = <1>;
 512                         };
 513
 514                         coredivclk: corediv-clock@e8250 {
 515                                 compatible = "marvell,armada-375-corediv-clock";
 516                                 reg = <0xe8250 0xc>;
 517                                 #clock-cells = <1>;
 518                                 clocks = <&mainpll>;
 519                                 clock-output-names = "nand";
 520                         };
 521                 };
 522
 523                 pcie-controller {
 524                         compatible = "marvell,armada-370-pcie";
 525                         status = "disabled";
 526                         device_type = "pci";
 527
 528                         #address-cells = <3>;
 529                         #size-cells = <2>;
 530
 531                         msi-parent = <&mpic>;
 532                         bus-range = <0x00 0xff>;
 533
 534                         ranges =
 535                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
 536                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
 537                                 0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
 538                                 0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
 539                                 0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
 540                                 0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;
 541
 542                         pcie@1,0 {
 543                                 device_type = "pci";
 544                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 545                                 reg = <0x0800 0 0 0 0>;
 546                                 #address-cells = <3>;
 547                                 #size-cells = <2>;
 548                                 #interrupt-cells = <1>;
 549                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 550                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 551                                 interrupt-map-mask = <0 0 0 0>;
 552                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 553                                 marvell,pcie-port = <0>;
 554                                 marvell,pcie-lane = <0>;
 555                                 clocks = <&gateclk 5>;
 556                                 status = "disabled";
 557                         };
 558
 559                         pcie@2,0 {
 560                                 device_type = "pci";
 561                                 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 562                                 reg = <0x1000 0 0 0 0>;
 563                                 #address-cells = <3>;
 564                                 #size-cells = <2>;
 565                                 #interrupt-cells = <1>;
 566                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 567                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 568                                 interrupt-map-mask = <0 0 0 0>;
 569                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 570                                 marvell,pcie-port = <0>;
 571                                 marvell,pcie-lane = <1>;
 572                                 clocks = <&gateclk 6>;
 573                                 status = "disabled";
 574                         };
 575
 576                 };
 577         };
 578 };