2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #define MAX_SOURCES 400
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&crossbar_mpu>;
38 ethernet0 = &cpsw_emac0;
39 ethernet1 = &cpsw_emac1;
46 compatible = "arm,armv7-timer";
47 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
48 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
51 interrupt-parent = <&gic>;
54 gic: interrupt-controller@48211000 {
55 compatible = "arm,cortex-a15-gic";
57 #interrupt-cells = <3>;
58 reg = <0x0 0x48211000 0x0 0x1000>,
59 <0x0 0x48212000 0x0 0x1000>,
60 <0x0 0x48214000 0x0 0x2000>,
61 <0x0 0x48216000 0x0 0x2000>;
62 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
63 interrupt-parent = <&gic>;
66 wakeupgen: interrupt-controller@48281000 {
67 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
69 #interrupt-cells = <3>;
70 reg = <0x0 0x48281000 0x0 0x1000>;
71 interrupt-parent = <&gic>;
80 compatible = "arm,cortex-a15";
89 clocks = <&dpll_mpu_ck>;
92 clock-latency = <300000>; /* From omap-cpufreq driver */
95 cooling-min-level = <0>;
96 cooling-max-level = <2>;
97 #cooling-cells = <2>; /* min followed by max */
102 * The soc node represents the soc top level view. It is used for IPs
103 * that are not memory mapped in the MPU view or for the MPU itself.
106 compatible = "ti,omap-infra";
108 compatible = "ti,omap5-mpu";
114 * XXX: Use a flat representation of the SOC interconnect.
115 * The real OMAP interconnect network is quite complex.
116 * Since it will not bring real advantage to represent that in DT for
117 * the moment, just use a fake OCP bus entry to represent the whole bus
121 compatible = "ti,dra7-l3-noc", "simple-bus";
122 #address-cells = <1>;
124 ranges = <0x0 0x0 0x0 0xc0000000>;
125 ti,hwmods = "l3_main_1", "l3_main_2";
126 reg = <0x0 0x44000000 0x0 0x1000000>,
127 <0x0 0x45000000 0x0 0x1000>;
128 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
129 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
131 l4_cfg: l4@4a000000 {
132 compatible = "ti,dra7-l4-cfg", "simple-bus";
133 #address-cells = <1>;
135 ranges = <0 0x4a000000 0x22c000>;
138 compatible = "ti,dra7-scm-core", "simple-bus";
139 reg = <0x2000 0x2000>;
140 #address-cells = <1>;
142 ranges = <0 0x2000 0x2000>;
144 scm_conf: scm_conf@0 {
145 compatible = "syscon", "simple-bus";
147 #address-cells = <1>;
149 ranges = <0 0x0 0x1400>;
151 pbias_regulator: pbias_regulator@e00 {
152 compatible = "ti,pbias-dra7", "ti,pbias-omap";
154 syscon = <&scm_conf>;
155 pbias_mmc_reg: pbias_mmc_omap5 {
156 regulator-name = "pbias_mmc_omap5";
157 regulator-min-microvolt = <1800000>;
158 regulator-max-microvolt = <3000000>;
162 scm_conf_clocks: clocks {
163 #address-cells = <1>;
168 dra7_pmx_core: pinmux@1400 {
169 compatible = "ti,dra7-padconf",
171 reg = <0x1400 0x0468>;
172 #address-cells = <1>;
174 #interrupt-cells = <1>;
175 interrupt-controller;
176 pinctrl-single,register-width = <32>;
177 pinctrl-single,function-mask = <0x3fffffff>;
180 scm_conf1: scm_conf@1c04 {
181 compatible = "syscon";
182 reg = <0x1c04 0x0020>;
185 scm_conf_pcie: scm_conf@1c24 {
186 compatible = "syscon";
187 reg = <0x1c24 0x0024>;
190 sdma_xbar: dma-router@b78 {
191 compatible = "ti,dra7-dma-crossbar";
194 dma-requests = <205>;
195 ti,dma-safe-map = <0>;
196 dma-masters = <&sdma>;
199 edma_xbar: dma-router@c78 {
200 compatible = "ti,dra7-dma-crossbar";
203 dma-requests = <204>;
204 ti,dma-safe-map = <0>;
205 dma-masters = <&edma>;
209 cm_core_aon: cm_core_aon@5000 {
210 compatible = "ti,dra7-cm-core-aon";
211 reg = <0x5000 0x2000>;
213 cm_core_aon_clocks: clocks {
214 #address-cells = <1>;
218 cm_core_aon_clockdomains: clockdomains {
222 cm_core: cm_core@8000 {
223 compatible = "ti,dra7-cm-core";
224 reg = <0x8000 0x3000>;
226 cm_core_clocks: clocks {
227 #address-cells = <1>;
231 cm_core_clockdomains: clockdomains {
236 l4_wkup: l4@4ae00000 {
237 compatible = "ti,dra7-l4-wkup", "simple-bus";
238 #address-cells = <1>;
240 ranges = <0 0x4ae00000 0x3f000>;
242 counter32k: counter@4000 {
243 compatible = "ti,omap-counter32k";
245 ti,hwmods = "counter_32k";
249 compatible = "ti,dra7-prm";
250 reg = <0x6000 0x3000>;
251 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
254 #address-cells = <1>;
258 prm_clockdomains: clockdomains {
262 scm_wkup: scm_conf@c000 {
263 compatible = "syscon";
264 reg = <0xc000 0x1000>;
269 compatible = "simple-bus";
271 #address-cells = <1>;
272 ranges = <0x51000000 0x51000000 0x3000
273 0x0 0x20000000 0x10000000>;
274 pcie1: pcie@51000000 {
275 compatible = "ti,dra7-pcie";
276 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
277 reg-names = "rc_dbics", "ti_conf", "config";
278 interrupts = <0 232 0x4>, <0 233 0x4>;
279 #address-cells = <3>;
282 ranges = <0x81000000 0 0 0x03000 0 0x00010000
283 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
284 #interrupt-cells = <1>;
286 linux,pci-domain = <0>;
289 phy-names = "pcie-phy0";
290 interrupt-map-mask = <0 0 0 7>;
291 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
292 <0 0 0 2 &pcie1_intc 2>,
293 <0 0 0 3 &pcie1_intc 3>,
294 <0 0 0 4 &pcie1_intc 4>;
295 pcie1_intc: interrupt-controller {
296 interrupt-controller;
297 #address-cells = <0>;
298 #interrupt-cells = <1>;
304 compatible = "simple-bus";
306 #address-cells = <1>;
307 ranges = <0x51800000 0x51800000 0x3000
308 0x0 0x30000000 0x10000000>;
311 compatible = "ti,dra7-pcie";
312 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
313 reg-names = "rc_dbics", "ti_conf", "config";
314 interrupts = <0 355 0x4>, <0 356 0x4>;
315 #address-cells = <3>;
318 ranges = <0x81000000 0 0 0x03000 0 0x00010000
319 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
320 #interrupt-cells = <1>;
322 linux,pci-domain = <1>;
325 phy-names = "pcie-phy0";
326 interrupt-map-mask = <0 0 0 7>;
327 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
328 <0 0 0 2 &pcie2_intc 2>,
329 <0 0 0 3 &pcie2_intc 3>,
330 <0 0 0 4 &pcie2_intc 4>;
331 pcie2_intc: interrupt-controller {
332 interrupt-controller;
333 #address-cells = <0>;
334 #interrupt-cells = <1>;
339 ocmcram1: ocmcram@40300000 {
340 compatible = "mmio-sram";
341 reg = <0x40300000 0x80000>;
342 ranges = <0x0 0x40300000 0x80000>;
343 #address-cells = <1>;
346 * This is a placeholder for an optional reserved
347 * region for use by secure software. The size
348 * of this region is not known until runtime so it
349 * is set as zero to either be updated to reserve
350 * space or left unchanged to leave all SRAM for use.
351 * On HS parts that that require the reserved region
352 * either the bootloader can update the size to
353 * the required amount or the node can be overridden
354 * from the board dts file for the secure platform.
357 compatible = "ti,secure-ram";
363 * NOTE: ocmcram2 and ocmcram3 are not available on all
364 * DRA7xx and AM57xx variants. Confirm availability in
365 * the data manual for the exact part number in use
366 * before enabling these nodes in the board dts file.
368 ocmcram2: ocmcram@40400000 {
370 compatible = "mmio-sram";
371 reg = <0x40400000 0x100000>;
372 ranges = <0x0 0x40400000 0x100000>;
373 #address-cells = <1>;
377 ocmcram3: ocmcram@40500000 {
379 compatible = "mmio-sram";
380 reg = <0x40500000 0x100000>;
381 ranges = <0x0 0x40500000 0x100000>;
382 #address-cells = <1>;
386 bandgap: bandgap@4a0021e0 {
387 reg = <0x4a0021e0 0xc
393 compatible = "ti,dra752-bandgap";
394 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
395 #thermal-sensor-cells = <1>;
398 dsp1_system: dsp_system@40d00000 {
399 compatible = "syscon";
400 reg = <0x40d00000 0x100>;
403 sdma: dma-controller@4a056000 {
404 compatible = "ti,omap4430-sdma";
405 reg = <0x4a056000 0x1000>;
406 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
412 dma-requests = <127>;
415 edma: edma@43300000 {
416 compatible = "ti,edma3-tpcc";
418 reg = <0x43300000 0x100000>;
419 reg-names = "edma3_cc";
420 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
423 interrupt-names = "edma3_ccint", "edma3_mperr",
428 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
431 * memcpy is disabled, can be enabled with:
432 * ti,edma-memcpy-channels = <20 21>;
433 * for example. Note that these channels need to be
434 * masked in the xbar as well.
438 edma_tptc0: tptc@43400000 {
439 compatible = "ti,edma3-tptc";
441 reg = <0x43400000 0x100000>;
442 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-names = "edma3_tcerrint";
446 edma_tptc1: tptc@43500000 {
447 compatible = "ti,edma3-tptc";
449 reg = <0x43500000 0x100000>;
450 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
451 interrupt-names = "edma3_tcerrint";
454 gpio1: gpio@4ae10000 {
455 compatible = "ti,omap4-gpio";
456 reg = <0x4ae10000 0x200>;
457 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
465 gpio2: gpio@48055000 {
466 compatible = "ti,omap4-gpio";
467 reg = <0x48055000 0x200>;
468 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
476 gpio3: gpio@48057000 {
477 compatible = "ti,omap4-gpio";
478 reg = <0x48057000 0x200>;
479 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
483 interrupt-controller;
484 #interrupt-cells = <2>;
487 gpio4: gpio@48059000 {
488 compatible = "ti,omap4-gpio";
489 reg = <0x48059000 0x200>;
490 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
494 interrupt-controller;
495 #interrupt-cells = <2>;
498 gpio5: gpio@4805b000 {
499 compatible = "ti,omap4-gpio";
500 reg = <0x4805b000 0x200>;
501 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
505 interrupt-controller;
506 #interrupt-cells = <2>;
509 gpio6: gpio@4805d000 {
510 compatible = "ti,omap4-gpio";
511 reg = <0x4805d000 0x200>;
512 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
520 gpio7: gpio@48051000 {
521 compatible = "ti,omap4-gpio";
522 reg = <0x48051000 0x200>;
523 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
527 interrupt-controller;
528 #interrupt-cells = <2>;
531 gpio8: gpio@48053000 {
532 compatible = "ti,omap4-gpio";
533 reg = <0x48053000 0x200>;
534 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
538 interrupt-controller;
539 #interrupt-cells = <2>;
542 uart1: serial@4806a000 {
543 compatible = "ti,dra742-uart", "ti,omap4-uart";
544 reg = <0x4806a000 0x100>;
545 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
547 clock-frequency = <48000000>;
549 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
550 dma-names = "tx", "rx";
553 uart2: serial@4806c000 {
554 compatible = "ti,dra742-uart", "ti,omap4-uart";
555 reg = <0x4806c000 0x100>;
556 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
558 clock-frequency = <48000000>;
560 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
561 dma-names = "tx", "rx";
564 uart3: serial@48020000 {
565 compatible = "ti,dra742-uart", "ti,omap4-uart";
566 reg = <0x48020000 0x100>;
567 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
569 clock-frequency = <48000000>;
571 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
572 dma-names = "tx", "rx";
575 uart4: serial@4806e000 {
576 compatible = "ti,dra742-uart", "ti,omap4-uart";
577 reg = <0x4806e000 0x100>;
578 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
580 clock-frequency = <48000000>;
582 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
583 dma-names = "tx", "rx";
586 uart5: serial@48066000 {
587 compatible = "ti,dra742-uart", "ti,omap4-uart";
588 reg = <0x48066000 0x100>;
589 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
591 clock-frequency = <48000000>;
593 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
594 dma-names = "tx", "rx";
597 uart6: serial@48068000 {
598 compatible = "ti,dra742-uart", "ti,omap4-uart";
599 reg = <0x48068000 0x100>;
600 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
602 clock-frequency = <48000000>;
604 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
605 dma-names = "tx", "rx";
608 uart7: serial@48420000 {
609 compatible = "ti,dra742-uart", "ti,omap4-uart";
610 reg = <0x48420000 0x100>;
611 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
613 clock-frequency = <48000000>;
617 uart8: serial@48422000 {
618 compatible = "ti,dra742-uart", "ti,omap4-uart";
619 reg = <0x48422000 0x100>;
620 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
622 clock-frequency = <48000000>;
626 uart9: serial@48424000 {
627 compatible = "ti,dra742-uart", "ti,omap4-uart";
628 reg = <0x48424000 0x100>;
629 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
631 clock-frequency = <48000000>;
635 uart10: serial@4ae2b000 {
636 compatible = "ti,dra742-uart", "ti,omap4-uart";
637 reg = <0x4ae2b000 0x100>;
638 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
639 ti,hwmods = "uart10";
640 clock-frequency = <48000000>;
644 mailbox1: mailbox@4a0f4000 {
645 compatible = "ti,omap4-mailbox";
646 reg = <0x4a0f4000 0x200>;
647 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
650 ti,hwmods = "mailbox1";
652 ti,mbox-num-users = <3>;
653 ti,mbox-num-fifos = <8>;
657 mailbox2: mailbox@4883a000 {
658 compatible = "ti,omap4-mailbox";
659 reg = <0x4883a000 0x200>;
660 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
664 ti,hwmods = "mailbox2";
666 ti,mbox-num-users = <4>;
667 ti,mbox-num-fifos = <12>;
671 mailbox3: mailbox@4883c000 {
672 compatible = "ti,omap4-mailbox";
673 reg = <0x4883c000 0x200>;
674 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
678 ti,hwmods = "mailbox3";
680 ti,mbox-num-users = <4>;
681 ti,mbox-num-fifos = <12>;
685 mailbox4: mailbox@4883e000 {
686 compatible = "ti,omap4-mailbox";
687 reg = <0x4883e000 0x200>;
688 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
692 ti,hwmods = "mailbox4";
694 ti,mbox-num-users = <4>;
695 ti,mbox-num-fifos = <12>;
699 mailbox5: mailbox@48840000 {
700 compatible = "ti,omap4-mailbox";
701 reg = <0x48840000 0x200>;
702 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
706 ti,hwmods = "mailbox5";
708 ti,mbox-num-users = <4>;
709 ti,mbox-num-fifos = <12>;
713 mailbox6: mailbox@48842000 {
714 compatible = "ti,omap4-mailbox";
715 reg = <0x48842000 0x200>;
716 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
720 ti,hwmods = "mailbox6";
722 ti,mbox-num-users = <4>;
723 ti,mbox-num-fifos = <12>;
727 mailbox7: mailbox@48844000 {
728 compatible = "ti,omap4-mailbox";
729 reg = <0x48844000 0x200>;
730 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
734 ti,hwmods = "mailbox7";
736 ti,mbox-num-users = <4>;
737 ti,mbox-num-fifos = <12>;
741 mailbox8: mailbox@48846000 {
742 compatible = "ti,omap4-mailbox";
743 reg = <0x48846000 0x200>;
744 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
748 ti,hwmods = "mailbox8";
750 ti,mbox-num-users = <4>;
751 ti,mbox-num-fifos = <12>;
755 mailbox9: mailbox@4885e000 {
756 compatible = "ti,omap4-mailbox";
757 reg = <0x4885e000 0x200>;
758 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
762 ti,hwmods = "mailbox9";
764 ti,mbox-num-users = <4>;
765 ti,mbox-num-fifos = <12>;
769 mailbox10: mailbox@48860000 {
770 compatible = "ti,omap4-mailbox";
771 reg = <0x48860000 0x200>;
772 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
776 ti,hwmods = "mailbox10";
778 ti,mbox-num-users = <4>;
779 ti,mbox-num-fifos = <12>;
783 mailbox11: mailbox@48862000 {
784 compatible = "ti,omap4-mailbox";
785 reg = <0x48862000 0x200>;
786 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
790 ti,hwmods = "mailbox11";
792 ti,mbox-num-users = <4>;
793 ti,mbox-num-fifos = <12>;
797 mailbox12: mailbox@48864000 {
798 compatible = "ti,omap4-mailbox";
799 reg = <0x48864000 0x200>;
800 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
801 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
804 ti,hwmods = "mailbox12";
806 ti,mbox-num-users = <4>;
807 ti,mbox-num-fifos = <12>;
811 mailbox13: mailbox@48802000 {
812 compatible = "ti,omap4-mailbox";
813 reg = <0x48802000 0x200>;
814 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
816 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
818 ti,hwmods = "mailbox13";
820 ti,mbox-num-users = <4>;
821 ti,mbox-num-fifos = <12>;
825 timer1: timer@4ae18000 {
826 compatible = "ti,omap5430-timer";
827 reg = <0x4ae18000 0x80>;
828 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
829 ti,hwmods = "timer1";
833 timer2: timer@48032000 {
834 compatible = "ti,omap5430-timer";
835 reg = <0x48032000 0x80>;
836 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
837 ti,hwmods = "timer2";
840 timer3: timer@48034000 {
841 compatible = "ti,omap5430-timer";
842 reg = <0x48034000 0x80>;
843 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
844 ti,hwmods = "timer3";
847 timer4: timer@48036000 {
848 compatible = "ti,omap5430-timer";
849 reg = <0x48036000 0x80>;
850 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
851 ti,hwmods = "timer4";
854 timer5: timer@48820000 {
855 compatible = "ti,omap5430-timer";
856 reg = <0x48820000 0x80>;
857 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
858 ti,hwmods = "timer5";
861 timer6: timer@48822000 {
862 compatible = "ti,omap5430-timer";
863 reg = <0x48822000 0x80>;
864 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
865 ti,hwmods = "timer6";
868 timer7: timer@48824000 {
869 compatible = "ti,omap5430-timer";
870 reg = <0x48824000 0x80>;
871 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
872 ti,hwmods = "timer7";
875 timer8: timer@48826000 {
876 compatible = "ti,omap5430-timer";
877 reg = <0x48826000 0x80>;
878 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
879 ti,hwmods = "timer8";
882 timer9: timer@4803e000 {
883 compatible = "ti,omap5430-timer";
884 reg = <0x4803e000 0x80>;
885 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
886 ti,hwmods = "timer9";
889 timer10: timer@48086000 {
890 compatible = "ti,omap5430-timer";
891 reg = <0x48086000 0x80>;
892 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
893 ti,hwmods = "timer10";
896 timer11: timer@48088000 {
897 compatible = "ti,omap5430-timer";
898 reg = <0x48088000 0x80>;
899 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
900 ti,hwmods = "timer11";
903 timer12: timer@4ae20000 {
904 compatible = "ti,omap5430-timer";
905 reg = <0x4ae20000 0x80>;
906 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
907 ti,hwmods = "timer12";
912 timer13: timer@48828000 {
913 compatible = "ti,omap5430-timer";
914 reg = <0x48828000 0x80>;
915 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
916 ti,hwmods = "timer13";
919 timer14: timer@4882a000 {
920 compatible = "ti,omap5430-timer";
921 reg = <0x4882a000 0x80>;
922 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
923 ti,hwmods = "timer14";
926 timer15: timer@4882c000 {
927 compatible = "ti,omap5430-timer";
928 reg = <0x4882c000 0x80>;
929 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
930 ti,hwmods = "timer15";
933 timer16: timer@4882e000 {
934 compatible = "ti,omap5430-timer";
935 reg = <0x4882e000 0x80>;
936 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
937 ti,hwmods = "timer16";
941 compatible = "ti,omap3-wdt";
942 reg = <0x4ae14000 0x80>;
943 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
944 ti,hwmods = "wd_timer2";
947 hwspinlock: spinlock@4a0f6000 {
948 compatible = "ti,omap4-hwspinlock";
949 reg = <0x4a0f6000 0x1000>;
950 ti,hwmods = "spinlock";
955 compatible = "ti,omap5-dmm";
956 reg = <0x4e000000 0x800>;
957 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
962 compatible = "ti,omap4-i2c";
963 reg = <0x48070000 0x100>;
964 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
965 #address-cells = <1>;
972 compatible = "ti,omap4-i2c";
973 reg = <0x48072000 0x100>;
974 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
975 #address-cells = <1>;
982 compatible = "ti,omap4-i2c";
983 reg = <0x48060000 0x100>;
984 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
985 #address-cells = <1>;
992 compatible = "ti,omap4-i2c";
993 reg = <0x4807a000 0x100>;
994 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
995 #address-cells = <1>;
1001 i2c5: i2c@4807c000 {
1002 compatible = "ti,omap4-i2c";
1003 reg = <0x4807c000 0x100>;
1004 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1005 #address-cells = <1>;
1008 status = "disabled";
1011 mmc1: mmc@4809c000 {
1012 compatible = "ti,omap4-hsmmc";
1013 reg = <0x4809c000 0x400>;
1014 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1017 ti,needs-special-reset;
1018 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
1019 dma-names = "tx", "rx";
1020 status = "disabled";
1021 pbias-supply = <&pbias_mmc_reg>;
1024 mmc2: mmc@480b4000 {
1025 compatible = "ti,omap4-hsmmc";
1026 reg = <0x480b4000 0x400>;
1027 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1029 ti,needs-special-reset;
1030 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
1031 dma-names = "tx", "rx";
1032 status = "disabled";
1035 mmc3: mmc@480ad000 {
1036 compatible = "ti,omap4-hsmmc";
1037 reg = <0x480ad000 0x400>;
1038 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1040 ti,needs-special-reset;
1041 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
1042 dma-names = "tx", "rx";
1043 status = "disabled";
1046 mmc4: mmc@480d1000 {
1047 compatible = "ti,omap4-hsmmc";
1048 reg = <0x480d1000 0x400>;
1049 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1051 ti,needs-special-reset;
1052 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
1053 dma-names = "tx", "rx";
1054 status = "disabled";
1057 mmu0_dsp1: mmu@40d01000 {
1058 compatible = "ti,dra7-dsp-iommu";
1059 reg = <0x40d01000 0x100>;
1060 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1061 ti,hwmods = "mmu0_dsp1";
1063 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1064 status = "disabled";
1067 mmu1_dsp1: mmu@40d02000 {
1068 compatible = "ti,dra7-dsp-iommu";
1069 reg = <0x40d02000 0x100>;
1070 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1071 ti,hwmods = "mmu1_dsp1";
1073 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1074 status = "disabled";
1077 mmu_ipu1: mmu@58882000 {
1078 compatible = "ti,dra7-iommu";
1079 reg = <0x58882000 0x100>;
1080 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1081 ti,hwmods = "mmu_ipu1";
1083 ti,iommu-bus-err-back;
1084 status = "disabled";
1087 mmu_ipu2: mmu@55082000 {
1088 compatible = "ti,dra7-iommu";
1089 reg = <0x55082000 0x100>;
1090 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1091 ti,hwmods = "mmu_ipu2";
1093 ti,iommu-bus-err-back;
1094 status = "disabled";
1097 abb_mpu: regulator-abb-mpu {
1098 compatible = "ti,abb-v3";
1099 regulator-name = "abb_mpu";
1100 #address-cells = <0>;
1102 clocks = <&sys_clkin1>;
1103 ti,settling-time = <50>;
1104 ti,clock-cycles = <16>;
1106 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1107 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1109 reg-names = "setup-address", "control-address",
1110 "int-address", "efuse-address",
1112 ti,tranxdone-status-mask = <0x80>;
1113 /* LDOVBBMPU_FBB_MUX_CTRL */
1114 ti,ldovbb-override-mask = <0x400>;
1115 /* LDOVBBMPU_FBB_VSET_OUT */
1116 ti,ldovbb-vset-mask = <0x1F>;
1119 * NOTE: only FBB mode used but actual vset will
1120 * determine final biasing
1123 /*uV ABB efuse rbb_m fbb_m vset_m*/
1124 1060000 0 0x0 0 0x02000000 0x01F00000
1125 1160000 0 0x4 0 0x02000000 0x01F00000
1126 1210000 0 0x8 0 0x02000000 0x01F00000
1130 abb_ivahd: regulator-abb-ivahd {
1131 compatible = "ti,abb-v3";
1132 regulator-name = "abb_ivahd";
1133 #address-cells = <0>;
1135 clocks = <&sys_clkin1>;
1136 ti,settling-time = <50>;
1137 ti,clock-cycles = <16>;
1139 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1140 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1142 reg-names = "setup-address", "control-address",
1143 "int-address", "efuse-address",
1145 ti,tranxdone-status-mask = <0x40000000>;
1146 /* LDOVBBIVA_FBB_MUX_CTRL */
1147 ti,ldovbb-override-mask = <0x400>;
1148 /* LDOVBBIVA_FBB_VSET_OUT */
1149 ti,ldovbb-vset-mask = <0x1F>;
1152 * NOTE: only FBB mode used but actual vset will
1153 * determine final biasing
1156 /*uV ABB efuse rbb_m fbb_m vset_m*/
1157 1055000 0 0x0 0 0x02000000 0x01F00000
1158 1150000 0 0x4 0 0x02000000 0x01F00000
1159 1250000 0 0x8 0 0x02000000 0x01F00000
1163 abb_dspeve: regulator-abb-dspeve {
1164 compatible = "ti,abb-v3";
1165 regulator-name = "abb_dspeve";
1166 #address-cells = <0>;
1168 clocks = <&sys_clkin1>;
1169 ti,settling-time = <50>;
1170 ti,clock-cycles = <16>;
1172 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1173 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1175 reg-names = "setup-address", "control-address",
1176 "int-address", "efuse-address",
1178 ti,tranxdone-status-mask = <0x20000000>;
1179 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1180 ti,ldovbb-override-mask = <0x400>;
1181 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1182 ti,ldovbb-vset-mask = <0x1F>;
1185 * NOTE: only FBB mode used but actual vset will
1186 * determine final biasing
1189 /*uV ABB efuse rbb_m fbb_m vset_m*/
1190 1055000 0 0x0 0 0x02000000 0x01F00000
1191 1150000 0 0x4 0 0x02000000 0x01F00000
1192 1250000 0 0x8 0 0x02000000 0x01F00000
1196 abb_gpu: regulator-abb-gpu {
1197 compatible = "ti,abb-v3";
1198 regulator-name = "abb_gpu";
1199 #address-cells = <0>;
1201 clocks = <&sys_clkin1>;
1202 ti,settling-time = <50>;
1203 ti,clock-cycles = <16>;
1205 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1206 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1208 reg-names = "setup-address", "control-address",
1209 "int-address", "efuse-address",
1211 ti,tranxdone-status-mask = <0x10000000>;
1212 /* LDOVBBGPU_FBB_MUX_CTRL */
1213 ti,ldovbb-override-mask = <0x400>;
1214 /* LDOVBBGPU_FBB_VSET_OUT */
1215 ti,ldovbb-vset-mask = <0x1F>;
1218 * NOTE: only FBB mode used but actual vset will
1219 * determine final biasing
1222 /*uV ABB efuse rbb_m fbb_m vset_m*/
1223 1090000 0 0x0 0 0x02000000 0x01F00000
1224 1210000 0 0x4 0 0x02000000 0x01F00000
1225 1280000 0 0x8 0 0x02000000 0x01F00000
1229 mcspi1: spi@48098000 {
1230 compatible = "ti,omap4-mcspi";
1231 reg = <0x48098000 0x200>;
1232 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1233 #address-cells = <1>;
1235 ti,hwmods = "mcspi1";
1236 ti,spi-num-cs = <4>;
1237 dmas = <&sdma_xbar 35>,
1245 dma-names = "tx0", "rx0", "tx1", "rx1",
1246 "tx2", "rx2", "tx3", "rx3";
1247 status = "disabled";
1250 mcspi2: spi@4809a000 {
1251 compatible = "ti,omap4-mcspi";
1252 reg = <0x4809a000 0x200>;
1253 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1254 #address-cells = <1>;
1256 ti,hwmods = "mcspi2";
1257 ti,spi-num-cs = <2>;
1258 dmas = <&sdma_xbar 43>,
1262 dma-names = "tx0", "rx0", "tx1", "rx1";
1263 status = "disabled";
1266 mcspi3: spi@480b8000 {
1267 compatible = "ti,omap4-mcspi";
1268 reg = <0x480b8000 0x200>;
1269 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1270 #address-cells = <1>;
1272 ti,hwmods = "mcspi3";
1273 ti,spi-num-cs = <2>;
1274 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1275 dma-names = "tx0", "rx0";
1276 status = "disabled";
1279 mcspi4: spi@480ba000 {
1280 compatible = "ti,omap4-mcspi";
1281 reg = <0x480ba000 0x200>;
1282 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1283 #address-cells = <1>;
1285 ti,hwmods = "mcspi4";
1286 ti,spi-num-cs = <1>;
1287 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1288 dma-names = "tx0", "rx0";
1289 status = "disabled";
1292 qspi: qspi@4b300000 {
1293 compatible = "ti,dra7xxx-qspi";
1294 reg = <0x4b300000 0x100>,
1295 <0x5c000000 0x4000000>;
1296 reg-names = "qspi_base", "qspi_mmap";
1297 syscon-chipselects = <&scm_conf 0x558>;
1298 #address-cells = <1>;
1301 clocks = <&qspi_gfclk_div>;
1302 clock-names = "fck";
1304 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1305 status = "disabled";
1310 compatible = "ti,omap-ocp2scp";
1311 #address-cells = <1>;
1314 reg = <0x4a090000 0x20>;
1315 ti,hwmods = "ocp2scp3";
1316 sata_phy: phy@4A096000 {
1317 compatible = "ti,phy-pipe3-sata";
1318 reg = <0x4A096000 0x80>, /* phy_rx */
1319 <0x4A096400 0x64>, /* phy_tx */
1320 <0x4A096800 0x40>; /* pll_ctrl */
1321 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1322 syscon-phy-power = <&scm_conf 0x374>;
1323 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1324 clock-names = "sysclk", "refclk";
1325 syscon-pllreset = <&scm_conf 0x3fc>;
1329 pcie1_phy: pciephy@4a094000 {
1330 compatible = "ti,phy-pipe3-pcie";
1331 reg = <0x4a094000 0x80>, /* phy_rx */
1332 <0x4a094400 0x64>; /* phy_tx */
1333 reg-names = "phy_rx", "phy_tx";
1334 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1335 syscon-pcs = <&scm_conf_pcie 0x10>;
1336 clocks = <&dpll_pcie_ref_ck>,
1337 <&dpll_pcie_ref_m2ldo_ck>,
1338 <&optfclk_pciephy1_32khz>,
1339 <&optfclk_pciephy1_clk>,
1340 <&optfclk_pciephy1_div_clk>,
1341 <&optfclk_pciephy_div>,
1343 clock-names = "dpll_ref", "dpll_ref_m2",
1344 "wkupclk", "refclk",
1345 "div-clk", "phy-div", "sysclk";
1349 pcie2_phy: pciephy@4a095000 {
1350 compatible = "ti,phy-pipe3-pcie";
1351 reg = <0x4a095000 0x80>, /* phy_rx */
1352 <0x4a095400 0x64>; /* phy_tx */
1353 reg-names = "phy_rx", "phy_tx";
1354 syscon-phy-power = <&scm_conf_pcie 0x20>;
1355 syscon-pcs = <&scm_conf_pcie 0x10>;
1356 clocks = <&dpll_pcie_ref_ck>,
1357 <&dpll_pcie_ref_m2ldo_ck>,
1358 <&optfclk_pciephy2_32khz>,
1359 <&optfclk_pciephy2_clk>,
1360 <&optfclk_pciephy2_div_clk>,
1361 <&optfclk_pciephy_div>,
1363 clock-names = "dpll_ref", "dpll_ref_m2",
1364 "wkupclk", "refclk",
1365 "div-clk", "phy-div", "sysclk";
1367 status = "disabled";
1371 sata: sata@4a141100 {
1372 compatible = "snps,dwc-ahci";
1373 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1374 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1376 phy-names = "sata-phy";
1377 clocks = <&sata_ref_clk>;
1382 compatible = "ti,am3352-rtc";
1383 reg = <0x48838000 0x100>;
1384 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1386 ti,hwmods = "rtcss";
1387 clocks = <&sys_32k_ck>;
1392 compatible = "ti,omap-ocp2scp";
1393 #address-cells = <1>;
1396 reg = <0x4a080000 0x20>;
1397 ti,hwmods = "ocp2scp1";
1399 usb2_phy1: phy@4a084000 {
1400 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1401 reg = <0x4a084000 0x400>;
1402 syscon-phy-power = <&scm_conf 0x300>;
1403 clocks = <&usb_phy1_always_on_clk32k>,
1404 <&usb_otg_ss1_refclk960m>;
1405 clock-names = "wkupclk",
1410 usb2_phy2: phy@4a085000 {
1411 compatible = "ti,dra7x-usb2-phy2",
1413 reg = <0x4a085000 0x400>;
1414 syscon-phy-power = <&scm_conf 0xe74>;
1415 clocks = <&usb_phy2_always_on_clk32k>,
1416 <&usb_otg_ss2_refclk960m>;
1417 clock-names = "wkupclk",
1422 usb3_phy1: phy@4a084400 {
1423 compatible = "ti,omap-usb3";
1424 reg = <0x4a084400 0x80>,
1427 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1428 syscon-phy-power = <&scm_conf 0x370>;
1429 clocks = <&usb_phy3_always_on_clk32k>,
1431 <&usb_otg_ss1_refclk960m>;
1432 clock-names = "wkupclk",
1439 omap_dwc3_1: omap_dwc3_1@48880000 {
1440 compatible = "ti,dwc3";
1441 ti,hwmods = "usb_otg_ss1";
1442 reg = <0x48880000 0x10000>;
1443 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1444 #address-cells = <1>;
1448 usb1: usb@48890000 {
1449 compatible = "snps,dwc3";
1450 reg = <0x48890000 0x17000>;
1451 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1454 interrupt-names = "peripheral",
1457 phys = <&usb2_phy1>, <&usb3_phy1>;
1458 phy-names = "usb2-phy", "usb3-phy";
1459 maximum-speed = "super-speed";
1461 snps,dis_u3_susphy_quirk;
1462 snps,dis_u2_susphy_quirk;
1466 omap_dwc3_2: omap_dwc3_2@488c0000 {
1467 compatible = "ti,dwc3";
1468 ti,hwmods = "usb_otg_ss2";
1469 reg = <0x488c0000 0x10000>;
1470 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1471 #address-cells = <1>;
1475 usb2: usb@488d0000 {
1476 compatible = "snps,dwc3";
1477 reg = <0x488d0000 0x17000>;
1478 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1480 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1481 interrupt-names = "peripheral",
1484 phys = <&usb2_phy2>;
1485 phy-names = "usb2-phy";
1486 maximum-speed = "high-speed";
1488 snps,dis_u3_susphy_quirk;
1489 snps,dis_u2_susphy_quirk;
1493 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1494 omap_dwc3_3: omap_dwc3_3@48900000 {
1495 compatible = "ti,dwc3";
1496 ti,hwmods = "usb_otg_ss3";
1497 reg = <0x48900000 0x10000>;
1498 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1499 #address-cells = <1>;
1503 status = "disabled";
1504 usb3: usb@48910000 {
1505 compatible = "snps,dwc3";
1506 reg = <0x48910000 0x17000>;
1507 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1508 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1509 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1510 interrupt-names = "peripheral",
1513 maximum-speed = "high-speed";
1515 snps,dis_u3_susphy_quirk;
1516 snps,dis_u2_susphy_quirk;
1521 compatible = "ti,am3352-elm";
1522 reg = <0x48078000 0xfc0>; /* device IO registers */
1523 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1525 status = "disabled";
1528 gpmc: gpmc@50000000 {
1529 compatible = "ti,am3352-gpmc";
1531 reg = <0x50000000 0x37c>; /* device IO registers */
1532 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1533 dmas = <&edma_xbar 4 0>;
1536 gpmc,num-waitpins = <2>;
1537 #address-cells = <2>;
1539 interrupt-controller;
1540 #interrupt-cells = <2>;
1543 status = "disabled";
1547 compatible = "ti,dra7-atl";
1548 reg = <0x4843c000 0x3ff>;
1550 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1551 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1552 clocks = <&atl_gfclk_mux>;
1553 clock-names = "fck";
1554 status = "disabled";
1557 mcasp1: mcasp@48460000 {
1558 compatible = "ti,dra7-mcasp-audio";
1559 ti,hwmods = "mcasp1";
1560 reg = <0x48460000 0x2000>,
1561 <0x45800000 0x1000>;
1562 reg-names = "mpu","dat";
1563 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1565 interrupt-names = "tx", "rx";
1566 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1567 dma-names = "tx", "rx";
1568 clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
1569 <&mcasp1_ahclkr_mux>;
1570 clock-names = "fck", "ahclkx", "ahclkr";
1571 status = "disabled";
1574 mcasp2: mcasp@48464000 {
1575 compatible = "ti,dra7-mcasp-audio";
1576 ti,hwmods = "mcasp2";
1577 reg = <0x48464000 0x2000>,
1578 <0x45c00000 0x1000>;
1579 reg-names = "mpu","dat";
1580 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1581 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1582 interrupt-names = "tx", "rx";
1583 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1584 dma-names = "tx", "rx";
1585 clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
1586 <&mcasp2_ahclkr_mux>;
1587 clock-names = "fck", "ahclkx", "ahclkr";
1588 status = "disabled";
1591 mcasp3: mcasp@48468000 {
1592 compatible = "ti,dra7-mcasp-audio";
1593 ti,hwmods = "mcasp3";
1594 reg = <0x48468000 0x2000>,
1595 <0x46000000 0x1000>;
1596 reg-names = "mpu","dat";
1597 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1598 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1599 interrupt-names = "tx", "rx";
1600 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1601 dma-names = "tx", "rx";
1602 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1603 clock-names = "fck", "ahclkx";
1604 status = "disabled";
1607 mcasp4: mcasp@4846c000 {
1608 compatible = "ti,dra7-mcasp-audio";
1609 ti,hwmods = "mcasp4";
1610 reg = <0x4846c000 0x2000>,
1611 <0x48436000 0x1000>;
1612 reg-names = "mpu","dat";
1613 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1614 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1615 interrupt-names = "tx", "rx";
1616 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1617 dma-names = "tx", "rx";
1618 clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
1619 clock-names = "fck", "ahclkx";
1620 status = "disabled";
1623 mcasp5: mcasp@48470000 {
1624 compatible = "ti,dra7-mcasp-audio";
1625 ti,hwmods = "mcasp5";
1626 reg = <0x48470000 0x2000>,
1627 <0x4843a000 0x1000>;
1628 reg-names = "mpu","dat";
1629 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1630 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1631 interrupt-names = "tx", "rx";
1632 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1633 dma-names = "tx", "rx";
1634 clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
1635 clock-names = "fck", "ahclkx";
1636 status = "disabled";
1639 mcasp6: mcasp@48474000 {
1640 compatible = "ti,dra7-mcasp-audio";
1641 ti,hwmods = "mcasp6";
1642 reg = <0x48474000 0x2000>,
1643 <0x4844c000 0x1000>;
1644 reg-names = "mpu","dat";
1645 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1646 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1647 interrupt-names = "tx", "rx";
1648 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1649 dma-names = "tx", "rx";
1650 clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
1651 clock-names = "fck", "ahclkx";
1652 status = "disabled";
1655 mcasp7: mcasp@48478000 {
1656 compatible = "ti,dra7-mcasp-audio";
1657 ti,hwmods = "mcasp7";
1658 reg = <0x48478000 0x2000>,
1659 <0x48450000 0x1000>;
1660 reg-names = "mpu","dat";
1661 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1662 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1663 interrupt-names = "tx", "rx";
1664 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1665 dma-names = "tx", "rx";
1666 clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
1667 clock-names = "fck", "ahclkx";
1668 status = "disabled";
1671 mcasp8: mcasp@4847c000 {
1672 compatible = "ti,dra7-mcasp-audio";
1673 ti,hwmods = "mcasp8";
1674 reg = <0x4847c000 0x2000>,
1675 <0x48454000 0x1000>;
1676 reg-names = "mpu","dat";
1677 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1678 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1679 interrupt-names = "tx", "rx";
1680 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1681 dma-names = "tx", "rx";
1682 clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
1683 clock-names = "fck", "ahclkx";
1684 status = "disabled";
1687 crossbar_mpu: crossbar@4a002a48 {
1688 compatible = "ti,irq-crossbar";
1689 reg = <0x4a002a48 0x130>;
1690 interrupt-controller;
1691 interrupt-parent = <&wakeupgen>;
1692 #interrupt-cells = <3>;
1693 ti,max-irqs = <160>;
1694 ti,max-crossbar-sources = <MAX_SOURCES>;
1696 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1697 ti,irqs-skip = <10 133 139 140>;
1698 ti,irqs-safe-map = <0>;
1701 mac: ethernet@48484000 {
1702 compatible = "ti,dra7-cpsw","ti,cpsw";
1704 clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
1705 clock-names = "fck", "cpts";
1706 cpdma_channels = <8>;
1707 ale_entries = <1024>;
1708 bd_ram_size = <0x2000>;
1710 mac_control = <0x20>;
1713 cpts_clock_mult = <0x784CFE14>;
1714 cpts_clock_shift = <29>;
1715 reg = <0x48484000 0x1000
1717 #address-cells = <1>;
1721 * Do not allow gating of cpsw clock as workaround
1722 * for errata i877. Keeping internal clock disabled
1723 * causes the device switching characteristics
1724 * to degrade over time and eventually fail to meet
1725 * the data manual delay time/skew specs.
1735 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1740 syscon = <&scm_conf>;
1741 status = "disabled";
1743 davinci_mdio: mdio@48485000 {
1744 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1745 #address-cells = <1>;
1747 ti,hwmods = "davinci_mdio";
1748 bus_freq = <1000000>;
1749 reg = <0x48485000 0x100>;
1752 cpsw_emac0: slave@48480200 {
1753 /* Filled in by U-Boot */
1754 mac-address = [ 00 00 00 00 00 00 ];
1757 cpsw_emac1: slave@48480300 {
1758 /* Filled in by U-Boot */
1759 mac-address = [ 00 00 00 00 00 00 ];
1762 phy_sel: cpsw-phy-sel@4a002554 {
1763 compatible = "ti,dra7xx-cpsw-phy-sel";
1764 reg= <0x4a002554 0x4>;
1765 reg-names = "gmii-sel";
1769 dcan1: can@481cc000 {
1770 compatible = "ti,dra7-d_can";
1771 ti,hwmods = "dcan1";
1772 reg = <0x4ae3c000 0x2000>;
1773 syscon-raminit = <&scm_conf 0x558 0>;
1774 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1775 clocks = <&dcan1_sys_clk_mux>;
1776 status = "disabled";
1779 dcan2: can@481d0000 {
1780 compatible = "ti,dra7-d_can";
1781 ti,hwmods = "dcan2";
1782 reg = <0x48480000 0x2000>;
1783 syscon-raminit = <&scm_conf 0x558 1>;
1784 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1785 clocks = <&sys_clkin1>;
1786 status = "disabled";
1790 compatible = "ti,dra7-dss";
1791 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1792 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1793 status = "disabled";
1794 ti,hwmods = "dss_core";
1795 /* CTRL_CORE_DSS_PLL_CONTROL */
1796 syscon-pll-ctrl = <&scm_conf 0x538>;
1797 #address-cells = <1>;
1802 compatible = "ti,dra7-dispc";
1803 reg = <0x58001000 0x1000>;
1804 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1805 ti,hwmods = "dss_dispc";
1806 clocks = <&dss_dss_clk>;
1807 clock-names = "fck";
1808 /* CTRL_CORE_SMA_SW_1 */
1809 syscon-pol = <&scm_conf 0x534>;
1812 hdmi: encoder@58060000 {
1813 compatible = "ti,dra7-hdmi";
1814 reg = <0x58040000 0x200>,
1817 <0x58060000 0x19000>;
1818 reg-names = "wp", "pll", "phy", "core";
1819 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1820 status = "disabled";
1821 ti,hwmods = "dss_hdmi";
1822 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1823 clock-names = "fck", "sys_clk";
1827 epwmss0: epwmss@4843e000 {
1828 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1829 reg = <0x4843e000 0x30>;
1830 ti,hwmods = "epwmss0";
1831 #address-cells = <1>;
1833 status = "disabled";
1836 ehrpwm0: pwm@4843e200 {
1837 compatible = "ti,dra746-ehrpwm",
1840 reg = <0x4843e200 0x80>;
1841 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1842 clock-names = "tbclk", "fck";
1843 status = "disabled";
1846 ecap0: ecap@4843e100 {
1847 compatible = "ti,dra746-ecap",
1850 reg = <0x4843e100 0x80>;
1851 clocks = <&l4_root_clk_div>;
1852 clock-names = "fck";
1853 status = "disabled";
1857 epwmss1: epwmss@48440000 {
1858 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1859 reg = <0x48440000 0x30>;
1860 ti,hwmods = "epwmss1";
1861 #address-cells = <1>;
1863 status = "disabled";
1866 ehrpwm1: pwm@48440200 {
1867 compatible = "ti,dra746-ehrpwm",
1870 reg = <0x48440200 0x80>;
1871 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
1872 clock-names = "tbclk", "fck";
1873 status = "disabled";
1876 ecap1: ecap@48440100 {
1877 compatible = "ti,dra746-ecap",
1880 reg = <0x48440100 0x80>;
1881 clocks = <&l4_root_clk_div>;
1882 clock-names = "fck";
1883 status = "disabled";
1887 epwmss2: epwmss@48442000 {
1888 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1889 reg = <0x48442000 0x30>;
1890 ti,hwmods = "epwmss2";
1891 #address-cells = <1>;
1893 status = "disabled";
1896 ehrpwm2: pwm@48442200 {
1897 compatible = "ti,dra746-ehrpwm",
1900 reg = <0x48442200 0x80>;
1901 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
1902 clock-names = "tbclk", "fck";
1903 status = "disabled";
1906 ecap2: ecap@48442100 {
1907 compatible = "ti,dra746-ecap",
1910 reg = <0x48442100 0x80>;
1911 clocks = <&l4_root_clk_div>;
1912 clock-names = "fck";
1913 status = "disabled";
1917 aes1: aes@4b500000 {
1918 compatible = "ti,omap4-aes";
1920 reg = <0x4b500000 0xa0>;
1921 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1922 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1923 dma-names = "tx", "rx";
1924 clocks = <&l3_iclk_div>;
1925 clock-names = "fck";
1928 aes2: aes@4b700000 {
1929 compatible = "ti,omap4-aes";
1931 reg = <0x4b700000 0xa0>;
1932 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1933 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1934 dma-names = "tx", "rx";
1935 clocks = <&l3_iclk_div>;
1936 clock-names = "fck";
1940 compatible = "ti,omap4-des";
1942 reg = <0x480a5000 0xa0>;
1943 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1944 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
1945 dma-names = "tx", "rx";
1946 clocks = <&l3_iclk_div>;
1947 clock-names = "fck";
1950 sham: sham@53100000 {
1951 compatible = "ti,omap5-sham";
1953 reg = <0x4b101000 0x300>;
1954 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1955 dmas = <&edma_xbar 119 0>;
1957 clocks = <&l3_iclk_div>;
1958 clock-names = "fck";
1962 compatible = "ti,omap4-rng";
1964 reg = <0x48090000 0x2000>;
1965 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1966 clocks = <&l3_iclk_div>;
1967 clock-names = "fck";
1971 thermal_zones: thermal-zones {
1972 #include "omap4-cpu-thermal.dtsi"
1973 #include "omap5-gpu-thermal.dtsi"
1974 #include "omap5-core-thermal.dtsi"
1975 #include "dra7-dspeve-thermal.dtsi"
1976 #include "dra7-iva-thermal.dtsi"
1982 polling-delay = <500>; /* milliseconds */
1985 /include/ "dra7xx-clocks.dtsi"