arch/arm/boot/dts/dra72-evm.dts

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra72x.dtsi"
  11
  12 / {
  13         model = "TI DRA722";
  14         compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
  15
  16         memory {
  17                 device_type = "memory";
  18                 reg = <0x80000000 0x40000000>; /* 1024 MB */
  19         };
  20
  21         evm_3v3: fixedregulator-evm_3v3 {
  22                 compatible = "regulator-fixed";
  23                 regulator-name = "evm_3v3";
  24                 regulator-min-microvolt = <3300000>;
  25                 regulator-max-microvolt = <3300000>;
  26         };
  27 };
  28
  29 &dra7_pmx_core {
  30         i2c1_pins: pinmux_i2c1_pins {
  31                 pinctrl-single,pins = <
  32                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
  33                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
  34                 >;
  35         };
  36
  37         nand_default: nand_default {
  38                 pinctrl-single,pins = <
  39                         0x0     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
  40                         0x4     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
  41                         0x8     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
  42                         0xc     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
  43                         0x10    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
  44                         0x14    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
  45                         0x18    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
  46                         0x1c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
  47                         0x20    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
  48                         0x24    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
  49                         0x28    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
  50                         0x2c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
  51                         0x30    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
  52                         0x34    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
  53                         0x38    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
  54                         0x3c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
  55                         0xb4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
  56                         0xc4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
  57                         0xcc    (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
  58                         0xc8    (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
  59                         0xd0    (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
  60                         0xd8    (PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
  61                 >;
  62         };
  63
  64         usb1_pins: pinmux_usb1_pins {
  65                 pinctrl-single,pins = <
  66                         0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
  67                 >;
  68         };
  69
  70         usb2_pins: pinmux_usb2_pins {
  71                 pinctrl-single,pins = <
  72                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
  73                 >;
  74         };
  75
  76         tps65917_pins_default: tps65917_pins_default {
  77                 pinctrl-single,pins = <
  78                         0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
  79                 >;
  80         };
  81
  82         mmc1_pins_default: mmc1_pins_default {
  83                 pinctrl-single,pins = <
  84                         0x36c (PIN_INPUT | MUX_MODE14)  /* mmc1sdcd.gpio219 */
  85                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  86                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  87                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  88                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  89                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  90                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  91                 >;
  92         };
  93
  94         mmc2_pins_default: mmc2_pins_default {
  95                 pinctrl-single,pins = <
  96                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
  97                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
  98                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
  99                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 100                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 101                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 102                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 103                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 104                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 105                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 106                 >;
 107         };
 108
 109         dcan1_pins_default: dcan1_pins_default {
 110                 pinctrl-single,pins = <
 111                         0x3d0   (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
 112                         0x3d4   (MUX_MODE15)            /* dcan1_rx.off */
 113                         0x418   (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
 114                 >;
 115         };
 116
 117         dcan1_pins_sleep: dcan1_pins_sleep {
 118                 pinctrl-single,pins = <
 119                         0x3d0   (MUX_MODE15)    /* dcan1_tx.off */
 120                         0x3d4   (MUX_MODE15)    /* dcan1_rx.off */
 121                         0x418   (MUX_MODE15)    /* wakeup0.off */
 122                 >;
 123         };
 124 };
 125
 126 &i2c1 {
 127         status = "okay";
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&i2c1_pins>;
 130         clock-frequency = <400000>;
 131
 132         tps65917: tps65917@58 {
 133                 compatible = "ti,tps65917";
 134                 reg = <0x58>;
 135
 136                 pinctrl-names = "default";
 137                 pinctrl-0 = <&tps65917_pins_default>;
 138
 139                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
 140                 interrupt-parent = <&gic>;
 141                 interrupt-controller;
 142                 #interrupt-cells = <2>;
 143
 144                 ti,system-power-controller;
 145
 146                 tps65917_pmic {
 147                         compatible = "ti,tps65917-pmic";
 148
 149                         regulators {
 150                                 smps1_reg: smps1 {
 151                                         /* VDD_MPU */
 152                                         regulator-name = "smps1";
 153                                         regulator-min-microvolt = <850000>;
 154                                         regulator-max-microvolt = <1250000>;
 155                                         regulator-always-on;
 156                                         regulator-boot-on;
 157                                 };
 158
 159                                 smps2_reg: smps2 {
 160                                         /* VDD_CORE */
 161                                         regulator-name = "smps2";
 162                                         regulator-min-microvolt = <850000>;
 163                                         regulator-max-microvolt = <1060000>;
 164                                         regulator-boot-on;
 165                                         regulator-always-on;
 166                                 };
 167
 168                                 smps3_reg: smps3 {
 169                                         /* VDD_GPU IVA DSPEVE */
 170                                         regulator-name = "smps3";
 171                                         regulator-min-microvolt = <850000>;
 172                                         regulator-max-microvolt = <1250000>;
 173                                         regulator-boot-on;
 174                                         regulator-always-on;
 175                                 };
 176
 177                                 smps4_reg: smps4 {
 178                                         /* VDDS1V8 */
 179                                         regulator-name = "smps4";
 180                                         regulator-min-microvolt = <1800000>;
 181                                         regulator-max-microvolt = <1800000>;
 182                                         regulator-always-on;
 183                                         regulator-boot-on;
 184                                 };
 185
 186                                 smps5_reg: smps5 {
 187                                         /* VDD_DDR */
 188                                         regulator-name = "smps5";
 189                                         regulator-min-microvolt = <1350000>;
 190                                         regulator-max-microvolt = <1350000>;
 191                                         regulator-boot-on;
 192                                         regulator-always-on;
 193                                 };
 194
 195                                 ldo1_reg: ldo1 {
 196                                         /* LDO1_OUT --> SDIO  */
 197                                         regulator-name = "ldo1";
 198                                         regulator-min-microvolt = <1800000>;
 199                                         regulator-max-microvolt = <3300000>;
 200                                         regulator-boot-on;
 201                                 };
 202
 203                                 ldo2_reg: ldo2 {
 204                                         /* LDO2_OUT --> TP1017 (UNUSED)  */
 205                                         regulator-name = "ldo2";
 206                                         regulator-min-microvolt = <1800000>;
 207                                         regulator-max-microvolt = <3300000>;
 208                                 };
 209
 210                                 ldo3_reg: ldo3 {
 211                                         /* VDDA_1V8_PHY */
 212                                         regulator-name = "ldo3";
 213                                         regulator-min-microvolt = <1800000>;
 214                                         regulator-max-microvolt = <1800000>;
 215                                         regulator-boot-on;
 216                                         regulator-always-on;
 217                                 };
 218
 219                                 ldo5_reg: ldo5 {
 220                                         /* VDDA_1V8_PLL */
 221                                         regulator-name = "ldo5";
 222                                         regulator-min-microvolt = <1800000>;
 223                                         regulator-max-microvolt = <1800000>;
 224                                         regulator-always-on;
 225                                         regulator-boot-on;
 226                                 };
 227
 228                                 ldo4_reg: ldo4 {
 229                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 230                                         regulator-name = "ldo4";
 231                                         regulator-min-microvolt = <3300000>;
 232                                         regulator-max-microvolt = <3300000>;
 233                                         regulator-boot-on;
 234                                 };
 235                         };
 236                 };
 237
 238                 tps65917_power_button {
 239                         compatible = "ti,palmas-pwrbutton";
 240                         interrupt-parent = <&tps65917>;
 241                         interrupts = <1 IRQ_TYPE_NONE>;
 242                         wakeup-source;
 243                         ti,palmas-long-press-seconds = <6>;
 244                 };
 245         };
 246 };
 247
 248 &uart1 {
 249         status = "okay";
 250 };
 251
 252 &elm {
 253         status = "okay";
 254 };
 255
 256 &gpmc {
 257         status = "okay";
 258         pinctrl-names = "default";
 259         pinctrl-0 = <&nand_default>;
 260         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 261         nand@0,0 {
 262                 /* To use NAND, DIP switch SW5 must be set like so:
 263                  * SW5.1 (NAND_SELn) = ON (LOW)
 264                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 265                  */
 266                 reg = <0 0 4>;          /* device IO registers */
 267                 ti,nand-ecc-opt = "bch8";
 268                 ti,elm-id = <&elm>;
 269                 nand-bus-width = <16>;
 270                 gpmc,device-width = <2>;
 271                 gpmc,sync-clk-ps = <0>;
 272                 gpmc,cs-on-ns = <0>;
 273                 gpmc,cs-rd-off-ns = <80>;
 274                 gpmc,cs-wr-off-ns = <80>;
 275                 gpmc,adv-on-ns = <0>;
 276                 gpmc,adv-rd-off-ns = <60>;
 277                 gpmc,adv-wr-off-ns = <60>;
 278                 gpmc,we-on-ns = <10>;
 279                 gpmc,we-off-ns = <50>;
 280                 gpmc,oe-on-ns = <4>;
 281                 gpmc,oe-off-ns = <40>;
 282                 gpmc,access-ns = <40>;
 283                 gpmc,wr-access-ns = <80>;
 284                 gpmc,rd-cycle-ns = <80>;
 285                 gpmc,wr-cycle-ns = <80>;
 286                 gpmc,bus-turnaround-ns = <0>;
 287                 gpmc,cycle2cycle-delay-ns = <0>;
 288                 gpmc,clk-activation-ns = <0>;
 289                 gpmc,wait-monitoring-ns = <0>;
 290                 gpmc,wr-data-mux-bus-ns = <0>;
 291                 /* MTD partition table */
 292                 /* All SPL-* partitions are sized to minimal length
 293                  * which can be independently programmable. For
 294                  * NAND flash this is equal to size of erase-block */
 295                 #address-cells = <1>;
 296                 #size-cells = <1>;
 297                 partition@0 {
 298                         label = "NAND.SPL";
 299                         reg = <0x00000000 0x000020000>;
 300                 };
 301                 partition@1 {
 302                         label = "NAND.SPL.backup1";
 303                         reg = <0x00020000 0x00020000>;
 304                 };
 305                 partition@2 {
 306                         label = "NAND.SPL.backup2";
 307                         reg = <0x00040000 0x00020000>;
 308                 };
 309                 partition@3 {
 310                         label = "NAND.SPL.backup3";
 311                         reg = <0x00060000 0x00020000>;
 312                 };
 313                 partition@4 {
 314                         label = "NAND.u-boot-spl-os";
 315                         reg = <0x00080000 0x00040000>;
 316                 };
 317                 partition@5 {
 318                         label = "NAND.u-boot";
 319                         reg = <0x000c0000 0x00100000>;
 320                 };
 321                 partition@6 {
 322                         label = "NAND.u-boot-env";
 323                         reg = <0x001c0000 0x00020000>;
 324                 };
 325                 partition@7 {
 326                         label = "NAND.u-boot-env.backup1";
 327                         reg = <0x001e0000 0x00020000>;
 328                 };
 329                 partition@8 {
 330                         label = "NAND.kernel";
 331                         reg = <0x00200000 0x00800000>;
 332                 };
 333                 partition@9 {
 334                         label = "NAND.file-system";
 335                         reg = <0x00a00000 0x0f600000>;
 336                 };
 337         };
 338 };
 339
 340 &usb2_phy1 {
 341         phy-supply = <&ldo4_reg>;
 342 };
 343
 344 &usb2_phy2 {
 345         phy-supply = <&ldo4_reg>;
 346 };
 347
 348 &usb1 {
 349         dr_mode = "peripheral";
 350         pinctrl-names = "default";
 351         pinctrl-0 = <&usb1_pins>;
 352 };
 353
 354 &usb2 {
 355         dr_mode = "host";
 356         pinctrl-names = "default";
 357         pinctrl-0 = <&usb2_pins>;
 358 };
 359
 360 &mmc1 {
 361         status = "okay";
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&mmc1_pins_default>;
 364
 365         vmmc-supply = <&ldo1_reg>;
 366         bus-width = <4>;
 367         /*
 368          * SDCD signal is not being used here - using the fact that GPIO mode
 369          * is a viable alternative
 370          */
 371         cd-gpios = <&gpio6 27 0>;
 372 };
 373
 374 &mmc2 {
 375         /* SW5-3 in ON position */
 376         status = "okay";
 377         pinctrl-names = "default";
 378         pinctrl-0 = <&mmc2_pins_default>;
 379
 380         vmmc-supply = <&evm_3v3>;
 381         bus-width = <8>;
 382         ti,non-removable;
 383 };
 384
 385 &dra7_pmx_core {
 386         cpsw_default: cpsw_default {
 387                 pinctrl-single,pins = <
 388                         /* Slave 2 */
 389                         0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
 390                         0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
 391                         0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
 392                         0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
 393                         0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
 394                         0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
 395                         0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
 396                         0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
 397                         0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
 398                         0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
 399                         0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
 400                         0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
 401                 >;
 402
 403         };
 404
 405         cpsw_sleep: cpsw_sleep {
 406                 pinctrl-single,pins = <
 407                         /* Slave 2 */
 408                         0x198 (MUX_MODE15)
 409                         0x19c (MUX_MODE15)
 410                         0x1a0 (MUX_MODE15)
 411                         0x1a4 (MUX_MODE15)
 412                         0x1a8 (MUX_MODE15)
 413                         0x1ac (MUX_MODE15)
 414                         0x1b0 (MUX_MODE15)
 415                         0x1b4 (MUX_MODE15)
 416                         0x1b8 (MUX_MODE15)
 417                         0x1bc (MUX_MODE15)
 418                         0x1c0 (MUX_MODE15)
 419                         0x1c4 (MUX_MODE15)
 420                 >;
 421         };
 422
 423         davinci_mdio_default: davinci_mdio_default {
 424                 pinctrl-single,pins = <
 425                         /* MDIO */
 426                         0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
 427                         0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
 428                 >;
 429         };
 430
 431         davinci_mdio_sleep: davinci_mdio_sleep {
 432                 pinctrl-single,pins = <
 433                         0x23c (MUX_MODE15)
 434                         0x240 (MUX_MODE15)
 435                 >;
 436         };
 437 };
 438
 439 &mac {
 440         status = "okay";
 441         pinctrl-names = "default", "sleep";
 442         pinctrl-0 = <&cpsw_default>;
 443         pinctrl-1 = <&cpsw_sleep>;
 444 };
 445
 446 &cpsw_emac1 {
 447         phy_id = <&davinci_mdio>, <3>;
 448         phy-mode = "rgmii";
 449 };
 450
 451 &davinci_mdio {
 452         pinctrl-names = "default", "sleep";
 453         pinctrl-0 = <&davinci_mdio_default>;
 454         pinctrl-1 = <&davinci_mdio_sleep>;
 455         active_slave = <1>;
 456 };
 457
 458 &dcan1 {
 459         status = "ok";
 460         pinctrl-names = "default", "sleep";
 461         pinctrl-0 = <&dcan1_pins_default>;
 462         pinctrl-1 = <&dcan1_pins_sleep>;
 463 };