arch/arm/boot/dts/dra74x.dtsi

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include "dra7.dtsi"
  11
  12 / {
  13         compatible = "ti,dra742", "ti,dra74", "ti,dra7";
  14
  15         cpus {
  16                 cpu@1 {
  17                         device_type = "cpu";
  18                         compatible = "arm,cortex-a15";
  19                         reg = <1>;
  20                 };
  21         };
  22
  23         pmu {
  24                 compatible = "arm,cortex-a15-pmu";
  25                 interrupt-parent = <&wakeupgen>;
  26                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  27                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  28         };
  29
  30         ocp {
  31                 dsp2_system: dsp_system@41500000 {
  32                         compatible = "syscon";
  33                         reg = <0x41500000 0x100>;
  34                 };
  35
  36                 omap_dwc3_4: omap_dwc3_4@48940000 {
  37                         compatible = "ti,dwc3";
  38                         ti,hwmods = "usb_otg_ss4";
  39                         reg = <0x48940000 0x10000>;
  40                         interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
  41                         #address-cells = <1>;
  42                         #size-cells = <1>;
  43                         utmi-mode = <2>;
  44                         ranges;
  45                         status = "disabled";
  46                         usb4: usb@48950000 {
  47                                 compatible = "snps,dwc3";
  48                                 reg = <0x48950000 0x17000>;
  49                                 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
  50                                              <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
  51                                              <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
  52                                 interrupt-names = "peripheral",
  53                                                   "host",
  54                                                   "otg";
  55                                 maximum-speed = "high-speed";
  56                                 dr_mode = "otg";
  57                         };
  58                 };
  59
  60                 mmu0_dsp2: mmu@41501000 {
  61                         compatible = "ti,dra7-dsp-iommu";
  62                         reg = <0x41501000 0x100>;
  63                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
  64                         ti,hwmods = "mmu0_dsp2";
  65                         #iommu-cells = <0>;
  66                         ti,syscon-mmuconfig = <&dsp2_system 0x0>;
  67                         status = "disabled";
  68                 };
  69
  70                 mmu1_dsp2: mmu@41502000 {
  71                         compatible = "ti,dra7-dsp-iommu";
  72                         reg = <0x41502000 0x100>;
  73                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
  74                         ti,hwmods = "mmu1_dsp2";
  75                         #iommu-cells = <0>;
  76                         ti,syscon-mmuconfig = <&dsp2_system 0x1>;
  77                         status = "disabled";
  78                 };
  79         };
  80 };
  81
  82 &dss {
  83         reg = <0x58000000 0x80>,
  84               <0x58004054 0x4>,
  85               <0x58004300 0x20>,
  86               <0x58009054 0x4>,
  87               <0x58009300 0x20>;
  88         reg-names = "dss", "pll1_clkctrl", "pll1",
  89                     "pll2_clkctrl", "pll2";
  90
  91         clocks = <&dss_dss_clk>,
  92                  <&dss_video1_clk>,
  93                  <&dss_video2_clk>;
  94         clock-names = "fck", "video1_clk", "video2_clk";
  95 };
  96
  97 &mailbox5 {
  98         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
  99                 ti,mbox-tx = <6 2 2>;
 100                 ti,mbox-rx = <4 2 2>;
 101                 status = "disabled";
 102         };
 103         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 104                 ti,mbox-tx = <5 2 2>;
 105                 ti,mbox-rx = <1 2 2>;
 106                 status = "disabled";
 107         };
 108 };
 109
 110 &mailbox6 {
 111         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 112                 ti,mbox-tx = <6 2 2>;
 113                 ti,mbox-rx = <4 2 2>;
 114                 status = "disabled";
 115         };
 116         mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
 117                 ti,mbox-tx = <5 2 2>;
 118                 ti,mbox-rx = <1 2 2>;
 119                 status = "disabled";
 120         };
 121 };