arch/arm/boot/dts/dra7xx-clocks.dtsi

   1 /*
   2  * Device Tree Source for DRA7xx clock data
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 &cm_core_aon_clocks {
  11         atl_clkin0_ck: atl_clkin0_ck {
  12                 #clock-cells = <0>;
  13                 compatible = "ti,dra7-atl-clock";
  14                 clocks = <&atl_gfclk_mux>;
  15         };
  16
  17         atl_clkin1_ck: atl_clkin1_ck {
  18                 #clock-cells = <0>;
  19                 compatible = "ti,dra7-atl-clock";
  20                 clocks = <&atl_gfclk_mux>;
  21         };
  22
  23         atl_clkin2_ck: atl_clkin2_ck {
  24                 #clock-cells = <0>;
  25                 compatible = "ti,dra7-atl-clock";
  26                 clocks = <&atl_gfclk_mux>;
  27         };
  28
  29         atl_clkin3_ck: atl_clkin3_ck {
  30                 #clock-cells = <0>;
  31                 compatible = "ti,dra7-atl-clock";
  32                 clocks = <&atl_gfclk_mux>;
  33         };
  34
  35         hdmi_clkin_ck: hdmi_clkin_ck {
  36                 #clock-cells = <0>;
  37                 compatible = "fixed-clock";
  38                 clock-frequency = <0>;
  39         };
  40
  41         mlb_clkin_ck: mlb_clkin_ck {
  42                 #clock-cells = <0>;
  43                 compatible = "fixed-clock";
  44                 clock-frequency = <0>;
  45         };
  46
  47         mlbp_clkin_ck: mlbp_clkin_ck {
  48                 #clock-cells = <0>;
  49                 compatible = "fixed-clock";
  50                 clock-frequency = <0>;
  51         };
  52
  53         pciesref_acs_clk_ck: pciesref_acs_clk_ck {
  54                 #clock-cells = <0>;
  55                 compatible = "fixed-clock";
  56                 clock-frequency = <100000000>;
  57         };
  58
  59         ref_clkin0_ck: ref_clkin0_ck {
  60                 #clock-cells = <0>;
  61                 compatible = "fixed-clock";
  62                 clock-frequency = <0>;
  63         };
  64
  65         ref_clkin1_ck: ref_clkin1_ck {
  66                 #clock-cells = <0>;
  67                 compatible = "fixed-clock";
  68                 clock-frequency = <0>;
  69         };
  70
  71         ref_clkin2_ck: ref_clkin2_ck {
  72                 #clock-cells = <0>;
  73                 compatible = "fixed-clock";
  74                 clock-frequency = <0>;
  75         };
  76
  77         ref_clkin3_ck: ref_clkin3_ck {
  78                 #clock-cells = <0>;
  79                 compatible = "fixed-clock";
  80                 clock-frequency = <0>;
  81         };
  82
  83         rmii_clk_ck: rmii_clk_ck {
  84                 #clock-cells = <0>;
  85                 compatible = "fixed-clock";
  86                 clock-frequency = <0>;
  87         };
  88
  89         sdvenc_clkin_ck: sdvenc_clkin_ck {
  90                 #clock-cells = <0>;
  91                 compatible = "fixed-clock";
  92                 clock-frequency = <0>;
  93         };
  94
  95         secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  96                 #clock-cells = <0>;
  97                 compatible = "fixed-clock";
  98                 clock-frequency = <32768>;
  99         };
 100
 101         sys_32k_ck: sys_32k_ck {
 102                 #clock-cells = <0>;
 103                 compatible = "fixed-clock";
 104                 clock-frequency = <32768>;
 105         };
 106
 107         virt_12000000_ck: virt_12000000_ck {
 108                 #clock-cells = <0>;
 109                 compatible = "fixed-clock";
 110                 clock-frequency = <12000000>;
 111         };
 112
 113         virt_13000000_ck: virt_13000000_ck {
 114                 #clock-cells = <0>;
 115                 compatible = "fixed-clock";
 116                 clock-frequency = <13000000>;
 117         };
 118
 119         virt_16800000_ck: virt_16800000_ck {
 120                 #clock-cells = <0>;
 121                 compatible = "fixed-clock";
 122                 clock-frequency = <16800000>;
 123         };
 124
 125         virt_19200000_ck: virt_19200000_ck {
 126                 #clock-cells = <0>;
 127                 compatible = "fixed-clock";
 128                 clock-frequency = <19200000>;
 129         };
 130
 131         virt_20000000_ck: virt_20000000_ck {
 132                 #clock-cells = <0>;
 133                 compatible = "fixed-clock";
 134                 clock-frequency = <20000000>;
 135         };
 136
 137         virt_26000000_ck: virt_26000000_ck {
 138                 #clock-cells = <0>;
 139                 compatible = "fixed-clock";
 140                 clock-frequency = <26000000>;
 141         };
 142
 143         virt_27000000_ck: virt_27000000_ck {
 144                 #clock-cells = <0>;
 145                 compatible = "fixed-clock";
 146                 clock-frequency = <27000000>;
 147         };
 148
 149         virt_38400000_ck: virt_38400000_ck {
 150                 #clock-cells = <0>;
 151                 compatible = "fixed-clock";
 152                 clock-frequency = <38400000>;
 153         };
 154
 155         sys_clkin2: sys_clkin2 {
 156                 #clock-cells = <0>;
 157                 compatible = "fixed-clock";
 158                 clock-frequency = <22579200>;
 159         };
 160
 161         usb_otg_clkin_ck: usb_otg_clkin_ck {
 162                 #clock-cells = <0>;
 163                 compatible = "fixed-clock";
 164                 clock-frequency = <0>;
 165         };
 166
 167         video1_clkin_ck: video1_clkin_ck {
 168                 #clock-cells = <0>;
 169                 compatible = "fixed-clock";
 170                 clock-frequency = <0>;
 171         };
 172
 173         video1_m2_clkin_ck: video1_m2_clkin_ck {
 174                 #clock-cells = <0>;
 175                 compatible = "fixed-clock";
 176                 clock-frequency = <0>;
 177         };
 178
 179         video2_clkin_ck: video2_clkin_ck {
 180                 #clock-cells = <0>;
 181                 compatible = "fixed-clock";
 182                 clock-frequency = <0>;
 183         };
 184
 185         video2_m2_clkin_ck: video2_m2_clkin_ck {
 186                 #clock-cells = <0>;
 187                 compatible = "fixed-clock";
 188                 clock-frequency = <0>;
 189         };
 190
 191         dpll_abe_ck: dpll_abe_ck {
 192                 #clock-cells = <0>;
 193                 compatible = "ti,omap4-dpll-m4xen-clock";
 194                 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
 195                 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 196         };
 197
 198         dpll_abe_x2_ck: dpll_abe_x2_ck {
 199                 #clock-cells = <0>;
 200                 compatible = "ti,omap4-dpll-x2-clock";
 201                 clocks = <&dpll_abe_ck>;
 202         };
 203
 204         dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
 205                 #clock-cells = <0>;
 206                 compatible = "ti,divider-clock";
 207                 clocks = <&dpll_abe_x2_ck>;
 208                 ti,max-div = <31>;
 209                 ti,autoidle-shift = <8>;
 210                 reg = <0x01f0>;
 211                 ti,index-starts-at-one;
 212                 ti,invert-autoidle-bit;
 213         };
 214
 215         abe_clk: abe_clk {
 216                 #clock-cells = <0>;
 217                 compatible = "ti,divider-clock";
 218                 clocks = <&dpll_abe_m2x2_ck>;
 219                 ti,max-div = <4>;
 220                 reg = <0x0108>;
 221                 ti,index-power-of-two;
 222         };
 223
 224         dpll_abe_m2_ck: dpll_abe_m2_ck {
 225                 #clock-cells = <0>;
 226                 compatible = "ti,divider-clock";
 227                 clocks = <&dpll_abe_ck>;
 228                 ti,max-div = <31>;
 229                 ti,autoidle-shift = <8>;
 230                 reg = <0x01f0>;
 231                 ti,index-starts-at-one;
 232                 ti,invert-autoidle-bit;
 233         };
 234
 235         dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
 236                 #clock-cells = <0>;
 237                 compatible = "ti,divider-clock";
 238                 clocks = <&dpll_abe_x2_ck>;
 239                 ti,max-div = <31>;
 240                 ti,autoidle-shift = <8>;
 241                 reg = <0x01f4>;
 242                 ti,index-starts-at-one;
 243                 ti,invert-autoidle-bit;
 244         };
 245
 246         dpll_core_ck: dpll_core_ck {
 247                 #clock-cells = <0>;
 248                 compatible = "ti,omap4-dpll-core-clock";
 249                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 250                 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 251         };
 252
 253         dpll_core_x2_ck: dpll_core_x2_ck {
 254                 #clock-cells = <0>;
 255                 compatible = "ti,omap4-dpll-x2-clock";
 256                 clocks = <&dpll_core_ck>;
 257         };
 258
 259         dpll_core_h12x2_ck: dpll_core_h12x2_ck {
 260                 #clock-cells = <0>;
 261                 compatible = "ti,divider-clock";
 262                 clocks = <&dpll_core_x2_ck>;
 263                 ti,max-div = <63>;
 264                 ti,autoidle-shift = <8>;
 265                 reg = <0x013c>;
 266                 ti,index-starts-at-one;
 267                 ti,invert-autoidle-bit;
 268         };
 269
 270         mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
 271                 #clock-cells = <0>;
 272                 compatible = "fixed-factor-clock";
 273                 clocks = <&dpll_core_h12x2_ck>;
 274                 clock-mult = <1>;
 275                 clock-div = <1>;
 276         };
 277
 278         dpll_mpu_ck: dpll_mpu_ck {
 279                 #clock-cells = <0>;
 280                 compatible = "ti,omap5-mpu-dpll-clock";
 281                 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
 282                 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 283         };
 284
 285         dpll_mpu_m2_ck: dpll_mpu_m2_ck {
 286                 #clock-cells = <0>;
 287                 compatible = "ti,divider-clock";
 288                 clocks = <&dpll_mpu_ck>;
 289                 ti,max-div = <31>;
 290                 ti,autoidle-shift = <8>;
 291                 reg = <0x0170>;
 292                 ti,index-starts-at-one;
 293                 ti,invert-autoidle-bit;
 294         };
 295
 296         mpu_dclk_div: mpu_dclk_div {
 297                 #clock-cells = <0>;
 298                 compatible = "fixed-factor-clock";
 299                 clocks = <&dpll_mpu_m2_ck>;
 300                 clock-mult = <1>;
 301                 clock-div = <1>;
 302         };
 303
 304         dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
 305                 #clock-cells = <0>;
 306                 compatible = "fixed-factor-clock";
 307                 clocks = <&dpll_core_h12x2_ck>;
 308                 clock-mult = <1>;
 309                 clock-div = <1>;
 310         };
 311
 312         dpll_dsp_ck: dpll_dsp_ck {
 313                 #clock-cells = <0>;
 314                 compatible = "ti,omap4-dpll-clock";
 315                 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
 316                 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
 317         };
 318
 319         dpll_dsp_m2_ck: dpll_dsp_m2_ck {
 320                 #clock-cells = <0>;
 321                 compatible = "ti,divider-clock";
 322                 clocks = <&dpll_dsp_ck>;
 323                 ti,max-div = <31>;
 324                 ti,autoidle-shift = <8>;
 325                 reg = <0x0244>;
 326                 ti,index-starts-at-one;
 327                 ti,invert-autoidle-bit;
 328         };
 329
 330         iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
 331                 #clock-cells = <0>;
 332                 compatible = "fixed-factor-clock";
 333                 clocks = <&dpll_core_h12x2_ck>;
 334                 clock-mult = <1>;
 335                 clock-div = <1>;
 336         };
 337
 338         dpll_iva_ck: dpll_iva_ck {
 339                 #clock-cells = <0>;
 340                 compatible = "ti,omap4-dpll-clock";
 341                 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
 342                 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 343         };
 344
 345         dpll_iva_m2_ck: dpll_iva_m2_ck {
 346                 #clock-cells = <0>;
 347                 compatible = "ti,divider-clock";
 348                 clocks = <&dpll_iva_ck>;
 349                 ti,max-div = <31>;
 350                 ti,autoidle-shift = <8>;
 351                 reg = <0x01b0>;
 352                 ti,index-starts-at-one;
 353                 ti,invert-autoidle-bit;
 354         };
 355
 356         iva_dclk: iva_dclk {
 357                 #clock-cells = <0>;
 358                 compatible = "fixed-factor-clock";
 359                 clocks = <&dpll_iva_m2_ck>;
 360                 clock-mult = <1>;
 361                 clock-div = <1>;
 362         };
 363
 364         dpll_gpu_ck: dpll_gpu_ck {
 365                 #clock-cells = <0>;
 366                 compatible = "ti,omap4-dpll-clock";
 367                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 368                 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
 369         };
 370
 371         dpll_gpu_m2_ck: dpll_gpu_m2_ck {
 372                 #clock-cells = <0>;
 373                 compatible = "ti,divider-clock";
 374                 clocks = <&dpll_gpu_ck>;
 375                 ti,max-div = <31>;
 376                 ti,autoidle-shift = <8>;
 377                 reg = <0x02e8>;
 378                 ti,index-starts-at-one;
 379                 ti,invert-autoidle-bit;
 380         };
 381
 382         dpll_core_m2_ck: dpll_core_m2_ck {
 383                 #clock-cells = <0>;
 384                 compatible = "ti,divider-clock";
 385                 clocks = <&dpll_core_ck>;
 386                 ti,max-div = <31>;
 387                 ti,autoidle-shift = <8>;
 388                 reg = <0x0130>;
 389                 ti,index-starts-at-one;
 390                 ti,invert-autoidle-bit;
 391         };
 392
 393         core_dpll_out_dclk_div: core_dpll_out_dclk_div {
 394                 #clock-cells = <0>;
 395                 compatible = "fixed-factor-clock";
 396                 clocks = <&dpll_core_m2_ck>;
 397                 clock-mult = <1>;
 398                 clock-div = <1>;
 399         };
 400
 401         dpll_ddr_ck: dpll_ddr_ck {
 402                 #clock-cells = <0>;
 403                 compatible = "ti,omap4-dpll-clock";
 404                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 405                 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
 406         };
 407
 408         dpll_ddr_m2_ck: dpll_ddr_m2_ck {
 409                 #clock-cells = <0>;
 410                 compatible = "ti,divider-clock";
 411                 clocks = <&dpll_ddr_ck>;
 412                 ti,max-div = <31>;
 413                 ti,autoidle-shift = <8>;
 414                 reg = <0x0220>;
 415                 ti,index-starts-at-one;
 416                 ti,invert-autoidle-bit;
 417         };
 418
 419         dpll_gmac_ck: dpll_gmac_ck {
 420                 #clock-cells = <0>;
 421                 compatible = "ti,omap4-dpll-clock";
 422                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 423                 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
 424         };
 425
 426         dpll_gmac_m2_ck: dpll_gmac_m2_ck {
 427                 #clock-cells = <0>;
 428                 compatible = "ti,divider-clock";
 429                 clocks = <&dpll_gmac_ck>;
 430                 ti,max-div = <31>;
 431                 ti,autoidle-shift = <8>;
 432                 reg = <0x02b8>;
 433                 ti,index-starts-at-one;
 434                 ti,invert-autoidle-bit;
 435         };
 436
 437         video2_dclk_div: video2_dclk_div {
 438                 #clock-cells = <0>;
 439                 compatible = "fixed-factor-clock";
 440                 clocks = <&video2_m2_clkin_ck>;
 441                 clock-mult = <1>;
 442                 clock-div = <1>;
 443         };
 444
 445         video1_dclk_div: video1_dclk_div {
 446                 #clock-cells = <0>;
 447                 compatible = "fixed-factor-clock";
 448                 clocks = <&video1_m2_clkin_ck>;
 449                 clock-mult = <1>;
 450                 clock-div = <1>;
 451         };
 452
 453         hdmi_dclk_div: hdmi_dclk_div {
 454                 #clock-cells = <0>;
 455                 compatible = "fixed-factor-clock";
 456                 clocks = <&hdmi_clkin_ck>;
 457                 clock-mult = <1>;
 458                 clock-div = <1>;
 459         };
 460
 461         per_dpll_hs_clk_div: per_dpll_hs_clk_div {
 462                 #clock-cells = <0>;
 463                 compatible = "fixed-factor-clock";
 464                 clocks = <&dpll_abe_m3x2_ck>;
 465                 clock-mult = <1>;
 466                 clock-div = <2>;
 467         };
 468
 469         usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
 470                 #clock-cells = <0>;
 471                 compatible = "fixed-factor-clock";
 472                 clocks = <&dpll_abe_m3x2_ck>;
 473                 clock-mult = <1>;
 474                 clock-div = <3>;
 475         };
 476
 477         eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
 478                 #clock-cells = <0>;
 479                 compatible = "fixed-factor-clock";
 480                 clocks = <&dpll_core_h12x2_ck>;
 481                 clock-mult = <1>;
 482                 clock-div = <1>;
 483         };
 484
 485         dpll_eve_ck: dpll_eve_ck {
 486                 #clock-cells = <0>;
 487                 compatible = "ti,omap4-dpll-clock";
 488                 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
 489                 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
 490         };
 491
 492         dpll_eve_m2_ck: dpll_eve_m2_ck {
 493                 #clock-cells = <0>;
 494                 compatible = "ti,divider-clock";
 495                 clocks = <&dpll_eve_ck>;
 496                 ti,max-div = <31>;
 497                 ti,autoidle-shift = <8>;
 498                 reg = <0x0294>;
 499                 ti,index-starts-at-one;
 500                 ti,invert-autoidle-bit;
 501         };
 502
 503         eve_dclk_div: eve_dclk_div {
 504                 #clock-cells = <0>;
 505                 compatible = "fixed-factor-clock";
 506                 clocks = <&dpll_eve_m2_ck>;
 507                 clock-mult = <1>;
 508                 clock-div = <1>;
 509         };
 510
 511         dpll_core_h13x2_ck: dpll_core_h13x2_ck {
 512                 #clock-cells = <0>;
 513                 compatible = "ti,divider-clock";
 514                 clocks = <&dpll_core_x2_ck>;
 515                 ti,max-div = <63>;
 516                 ti,autoidle-shift = <8>;
 517                 reg = <0x0140>;
 518                 ti,index-starts-at-one;
 519                 ti,invert-autoidle-bit;
 520         };
 521
 522         dpll_core_h14x2_ck: dpll_core_h14x2_ck {
 523                 #clock-cells = <0>;
 524                 compatible = "ti,divider-clock";
 525                 clocks = <&dpll_core_x2_ck>;
 526                 ti,max-div = <63>;
 527                 ti,autoidle-shift = <8>;
 528                 reg = <0x0144>;
 529                 ti,index-starts-at-one;
 530                 ti,invert-autoidle-bit;
 531         };
 532
 533         dpll_core_h22x2_ck: dpll_core_h22x2_ck {
 534                 #clock-cells = <0>;
 535                 compatible = "ti,divider-clock";
 536                 clocks = <&dpll_core_x2_ck>;
 537                 ti,max-div = <63>;
 538                 ti,autoidle-shift = <8>;
 539                 reg = <0x0154>;
 540                 ti,index-starts-at-one;
 541                 ti,invert-autoidle-bit;
 542         };
 543
 544         dpll_core_h23x2_ck: dpll_core_h23x2_ck {
 545                 #clock-cells = <0>;
 546                 compatible = "ti,divider-clock";
 547                 clocks = <&dpll_core_x2_ck>;
 548                 ti,max-div = <63>;
 549                 ti,autoidle-shift = <8>;
 550                 reg = <0x0158>;
 551                 ti,index-starts-at-one;
 552                 ti,invert-autoidle-bit;
 553         };
 554
 555         dpll_core_h24x2_ck: dpll_core_h24x2_ck {
 556                 #clock-cells = <0>;
 557                 compatible = "ti,divider-clock";
 558                 clocks = <&dpll_core_x2_ck>;
 559                 ti,max-div = <63>;
 560                 ti,autoidle-shift = <8>;
 561                 reg = <0x015c>;
 562                 ti,index-starts-at-one;
 563                 ti,invert-autoidle-bit;
 564         };
 565
 566         dpll_ddr_x2_ck: dpll_ddr_x2_ck {
 567                 #clock-cells = <0>;
 568                 compatible = "ti,omap4-dpll-x2-clock";
 569                 clocks = <&dpll_ddr_ck>;
 570         };
 571
 572         dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
 573                 #clock-cells = <0>;
 574                 compatible = "ti,divider-clock";
 575                 clocks = <&dpll_ddr_x2_ck>;
 576                 ti,max-div = <63>;
 577                 ti,autoidle-shift = <8>;
 578                 reg = <0x0228>;
 579                 ti,index-starts-at-one;
 580                 ti,invert-autoidle-bit;
 581         };
 582
 583         dpll_dsp_x2_ck: dpll_dsp_x2_ck {
 584                 #clock-cells = <0>;
 585                 compatible = "ti,omap4-dpll-x2-clock";
 586                 clocks = <&dpll_dsp_ck>;
 587         };
 588
 589         dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
 590                 #clock-cells = <0>;
 591                 compatible = "ti,divider-clock";
 592                 clocks = <&dpll_dsp_x2_ck>;
 593                 ti,max-div = <31>;
 594                 ti,autoidle-shift = <8>;
 595                 reg = <0x0248>;
 596                 ti,index-starts-at-one;
 597                 ti,invert-autoidle-bit;
 598         };
 599
 600         dpll_gmac_x2_ck: dpll_gmac_x2_ck {
 601                 #clock-cells = <0>;
 602                 compatible = "ti,omap4-dpll-x2-clock";
 603                 clocks = <&dpll_gmac_ck>;
 604         };
 605
 606         dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
 607                 #clock-cells = <0>;
 608                 compatible = "ti,divider-clock";
 609                 clocks = <&dpll_gmac_x2_ck>;
 610                 ti,max-div = <63>;
 611                 ti,autoidle-shift = <8>;
 612                 reg = <0x02c0>;
 613                 ti,index-starts-at-one;
 614                 ti,invert-autoidle-bit;
 615         };
 616
 617         dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
 618                 #clock-cells = <0>;
 619                 compatible = "ti,divider-clock";
 620                 clocks = <&dpll_gmac_x2_ck>;
 621                 ti,max-div = <63>;
 622                 ti,autoidle-shift = <8>;
 623                 reg = <0x02c4>;
 624                 ti,index-starts-at-one;
 625                 ti,invert-autoidle-bit;
 626         };
 627
 628         dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
 629                 #clock-cells = <0>;
 630                 compatible = "ti,divider-clock";
 631                 clocks = <&dpll_gmac_x2_ck>;
 632                 ti,max-div = <63>;
 633                 ti,autoidle-shift = <8>;
 634                 reg = <0x02c8>;
 635                 ti,index-starts-at-one;
 636                 ti,invert-autoidle-bit;
 637         };
 638
 639         dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
 640                 #clock-cells = <0>;
 641                 compatible = "ti,divider-clock";
 642                 clocks = <&dpll_gmac_x2_ck>;
 643                 ti,max-div = <31>;
 644                 ti,autoidle-shift = <8>;
 645                 reg = <0x02bc>;
 646                 ti,index-starts-at-one;
 647                 ti,invert-autoidle-bit;
 648         };
 649
 650         gmii_m_clk_div: gmii_m_clk_div {
 651                 #clock-cells = <0>;
 652                 compatible = "fixed-factor-clock";
 653                 clocks = <&dpll_gmac_h11x2_ck>;
 654                 clock-mult = <1>;
 655                 clock-div = <2>;
 656         };
 657
 658         hdmi_clk2_div: hdmi_clk2_div {
 659                 #clock-cells = <0>;
 660                 compatible = "fixed-factor-clock";
 661                 clocks = <&hdmi_clkin_ck>;
 662                 clock-mult = <1>;
 663                 clock-div = <1>;
 664         };
 665
 666         hdmi_div_clk: hdmi_div_clk {
 667                 #clock-cells = <0>;
 668                 compatible = "fixed-factor-clock";
 669                 clocks = <&hdmi_clkin_ck>;
 670                 clock-mult = <1>;
 671                 clock-div = <1>;
 672         };
 673
 674         l3_iclk_div: l3_iclk_div {
 675                 #clock-cells = <0>;
 676                 compatible = "ti,divider-clock";
 677                 ti,max-div = <2>;
 678                 ti,bit-shift = <4>;
 679                 reg = <0x0100>;
 680                 clocks = <&dpll_core_h12x2_ck>;
 681                 ti,index-power-of-two;
 682         };
 683
 684         l4_root_clk_div: l4_root_clk_div {
 685                 #clock-cells = <0>;
 686                 compatible = "fixed-factor-clock";
 687                 clocks = <&l3_iclk_div>;
 688                 clock-mult = <1>;
 689                 clock-div = <2>;
 690         };
 691
 692         video1_clk2_div: video1_clk2_div {
 693                 #clock-cells = <0>;
 694                 compatible = "fixed-factor-clock";
 695                 clocks = <&video1_clkin_ck>;
 696                 clock-mult = <1>;
 697                 clock-div = <1>;
 698         };
 699
 700         video1_div_clk: video1_div_clk {
 701                 #clock-cells = <0>;
 702                 compatible = "fixed-factor-clock";
 703                 clocks = <&video1_clkin_ck>;
 704                 clock-mult = <1>;
 705                 clock-div = <1>;
 706         };
 707
 708         video2_clk2_div: video2_clk2_div {
 709                 #clock-cells = <0>;
 710                 compatible = "fixed-factor-clock";
 711                 clocks = <&video2_clkin_ck>;
 712                 clock-mult = <1>;
 713                 clock-div = <1>;
 714         };
 715
 716         video2_div_clk: video2_div_clk {
 717                 #clock-cells = <0>;
 718                 compatible = "fixed-factor-clock";
 719                 clocks = <&video2_clkin_ck>;
 720                 clock-mult = <1>;
 721                 clock-div = <1>;
 722         };
 723
 724         ipu1_gfclk_mux: ipu1_gfclk_mux {
 725                 #clock-cells = <0>;
 726                 compatible = "ti,mux-clock";
 727                 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
 728                 ti,bit-shift = <24>;
 729                 reg = <0x0520>;
 730         };
 731
 732         mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
 733                 #clock-cells = <0>;
 734                 compatible = "ti,mux-clock";
 735                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
 736                 ti,bit-shift = <28>;
 737                 reg = <0x0550>;
 738         };
 739
 740         mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
 741                 #clock-cells = <0>;
 742                 compatible = "ti,mux-clock";
 743                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
 744                 ti,bit-shift = <24>;
 745                 reg = <0x0550>;
 746         };
 747
 748         mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
 749                 #clock-cells = <0>;
 750                 compatible = "ti,mux-clock";
 751                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
 752                 ti,bit-shift = <22>;
 753                 reg = <0x0550>;
 754         };
 755
 756         timer5_gfclk_mux: timer5_gfclk_mux {
 757                 #clock-cells = <0>;
 758                 compatible = "ti,mux-clock";
 759                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 760                 ti,bit-shift = <24>;
 761                 reg = <0x0558>;
 762         };
 763
 764         timer6_gfclk_mux: timer6_gfclk_mux {
 765                 #clock-cells = <0>;
 766                 compatible = "ti,mux-clock";
 767                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 768                 ti,bit-shift = <24>;
 769                 reg = <0x0560>;
 770         };
 771
 772         timer7_gfclk_mux: timer7_gfclk_mux {
 773                 #clock-cells = <0>;
 774                 compatible = "ti,mux-clock";
 775                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 776                 ti,bit-shift = <24>;
 777                 reg = <0x0568>;
 778         };
 779
 780         timer8_gfclk_mux: timer8_gfclk_mux {
 781                 #clock-cells = <0>;
 782                 compatible = "ti,mux-clock";
 783                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 784                 ti,bit-shift = <24>;
 785                 reg = <0x0570>;
 786         };
 787
 788         uart6_gfclk_mux: uart6_gfclk_mux {
 789                 #clock-cells = <0>;
 790                 compatible = "ti,mux-clock";
 791                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
 792                 ti,bit-shift = <24>;
 793                 reg = <0x0580>;
 794         };
 795
 796         dummy_ck: dummy_ck {
 797                 #clock-cells = <0>;
 798                 compatible = "fixed-clock";
 799                 clock-frequency = <0>;
 800         };
 801 };
 802 &prm_clocks {
 803         sys_clkin1: sys_clkin1 {
 804                 #clock-cells = <0>;
 805                 compatible = "ti,mux-clock";
 806                 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
 807                 reg = <0x0110>;
 808                 ti,index-starts-at-one;
 809         };
 810
 811         abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
 812                 #clock-cells = <0>;
 813                 compatible = "ti,mux-clock";
 814                 clocks = <&sys_clkin1>, <&sys_clkin2>;
 815                 reg = <0x0118>;
 816         };
 817
 818         abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
 819                 #clock-cells = <0>;
 820                 compatible = "ti,mux-clock";
 821                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 822                 reg = <0x0114>;
 823         };
 824
 825         abe_dpll_clk_mux: abe_dpll_clk_mux {
 826                 #clock-cells = <0>;
 827                 compatible = "ti,mux-clock";
 828                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 829                 reg = <0x010c>;
 830         };
 831
 832         abe_24m_fclk: abe_24m_fclk {
 833                 #clock-cells = <0>;
 834                 compatible = "ti,divider-clock";
 835                 clocks = <&dpll_abe_m2x2_ck>;
 836                 reg = <0x011c>;
 837                 ti,dividers = <8>, <16>;
 838         };
 839
 840         aess_fclk: aess_fclk {
 841                 #clock-cells = <0>;
 842                 compatible = "ti,divider-clock";
 843                 clocks = <&abe_clk>;
 844                 reg = <0x0178>;
 845                 ti,max-div = <2>;
 846         };
 847
 848         abe_giclk_div: abe_giclk_div {
 849                 #clock-cells = <0>;
 850                 compatible = "ti,divider-clock";
 851                 clocks = <&aess_fclk>;
 852                 reg = <0x0174>;
 853                 ti,max-div = <2>;
 854         };
 855
 856         abe_lp_clk_div: abe_lp_clk_div {
 857                 #clock-cells = <0>;
 858                 compatible = "ti,divider-clock";
 859                 clocks = <&dpll_abe_m2x2_ck>;
 860                 reg = <0x01d8>;
 861                 ti,dividers = <16>, <32>;
 862         };
 863
 864         abe_sys_clk_div: abe_sys_clk_div {
 865                 #clock-cells = <0>;
 866                 compatible = "ti,divider-clock";
 867                 clocks = <&sys_clkin1>;
 868                 reg = <0x0120>;
 869                 ti,max-div = <2>;
 870         };
 871
 872         adc_gfclk_mux: adc_gfclk_mux {
 873                 #clock-cells = <0>;
 874                 compatible = "ti,mux-clock";
 875                 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
 876                 reg = <0x01dc>;
 877         };
 878
 879         sys_clk1_dclk_div: sys_clk1_dclk_div {
 880                 #clock-cells = <0>;
 881                 compatible = "ti,divider-clock";
 882                 clocks = <&sys_clkin1>;
 883                 ti,max-div = <64>;
 884                 reg = <0x01c8>;
 885                 ti,index-power-of-two;
 886         };
 887
 888         sys_clk2_dclk_div: sys_clk2_dclk_div {
 889                 #clock-cells = <0>;
 890                 compatible = "ti,divider-clock";
 891                 clocks = <&sys_clkin2>;
 892                 ti,max-div = <64>;
 893                 reg = <0x01cc>;
 894                 ti,index-power-of-two;
 895         };
 896
 897         per_abe_x1_dclk_div: per_abe_x1_dclk_div {
 898                 #clock-cells = <0>;
 899                 compatible = "ti,divider-clock";
 900                 clocks = <&dpll_abe_m2_ck>;
 901                 ti,max-div = <64>;
 902                 reg = <0x01bc>;
 903                 ti,index-power-of-two;
 904         };
 905
 906         dsp_gclk_div: dsp_gclk_div {
 907                 #clock-cells = <0>;
 908                 compatible = "ti,divider-clock";
 909                 clocks = <&dpll_dsp_m2_ck>;
 910                 ti,max-div = <64>;
 911                 reg = <0x018c>;
 912                 ti,index-power-of-two;
 913         };
 914
 915         gpu_dclk: gpu_dclk {
 916                 #clock-cells = <0>;
 917                 compatible = "ti,divider-clock";
 918                 clocks = <&dpll_gpu_m2_ck>;
 919                 ti,max-div = <64>;
 920                 reg = <0x01a0>;
 921                 ti,index-power-of-two;
 922         };
 923
 924         emif_phy_dclk_div: emif_phy_dclk_div {
 925                 #clock-cells = <0>;
 926                 compatible = "ti,divider-clock";
 927                 clocks = <&dpll_ddr_m2_ck>;
 928                 ti,max-div = <64>;
 929                 reg = <0x0190>;
 930                 ti,index-power-of-two;
 931         };
 932
 933         gmac_250m_dclk_div: gmac_250m_dclk_div {
 934                 #clock-cells = <0>;
 935                 compatible = "ti,divider-clock";
 936                 clocks = <&dpll_gmac_m2_ck>;
 937                 ti,max-div = <64>;
 938                 reg = <0x019c>;
 939                 ti,index-power-of-two;
 940         };
 941
 942         l3init_480m_dclk_div: l3init_480m_dclk_div {
 943                 #clock-cells = <0>;
 944                 compatible = "ti,divider-clock";
 945                 clocks = <&dpll_usb_m2_ck>;
 946                 ti,max-div = <64>;
 947                 reg = <0x01ac>;
 948                 ti,index-power-of-two;
 949         };
 950
 951         usb_otg_dclk_div: usb_otg_dclk_div {
 952                 #clock-cells = <0>;
 953                 compatible = "ti,divider-clock";
 954                 clocks = <&usb_otg_clkin_ck>;
 955                 ti,max-div = <64>;
 956                 reg = <0x0184>;
 957                 ti,index-power-of-two;
 958         };
 959
 960         sata_dclk_div: sata_dclk_div {
 961                 #clock-cells = <0>;
 962                 compatible = "ti,divider-clock";
 963                 clocks = <&sys_clkin1>;
 964                 ti,max-div = <64>;
 965                 reg = <0x01c0>;
 966                 ti,index-power-of-two;
 967         };
 968
 969         pcie2_dclk_div: pcie2_dclk_div {
 970                 #clock-cells = <0>;
 971                 compatible = "ti,divider-clock";
 972                 clocks = <&dpll_pcie_ref_m2_ck>;
 973                 ti,max-div = <64>;
 974                 reg = <0x01b8>;
 975                 ti,index-power-of-two;
 976         };
 977
 978         pcie_dclk_div: pcie_dclk_div {
 979                 #clock-cells = <0>;
 980                 compatible = "ti,divider-clock";
 981                 clocks = <&apll_pcie_m2_ck>;
 982                 ti,max-div = <64>;
 983                 reg = <0x01b4>;
 984                 ti,index-power-of-two;
 985         };
 986
 987         emu_dclk_div: emu_dclk_div {
 988                 #clock-cells = <0>;
 989                 compatible = "ti,divider-clock";
 990                 clocks = <&sys_clkin1>;
 991                 ti,max-div = <64>;
 992                 reg = <0x0194>;
 993                 ti,index-power-of-two;
 994         };
 995
 996         secure_32k_dclk_div: secure_32k_dclk_div {
 997                 #clock-cells = <0>;
 998                 compatible = "ti,divider-clock";
 999                 clocks = <&secure_32k_clk_src_ck>;
1000                 ti,max-div = <64>;
1001                 reg = <0x01c4>;
1002                 ti,index-power-of-two;
1003         };
1004
1005         clkoutmux0_clk_mux: clkoutmux0_clk_mux {
1006                 #clock-cells = <0>;
1007                 compatible = "ti,mux-clock";
1008                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1009                 reg = <0x0158>;
1010         };
1011
1012         clkoutmux1_clk_mux: clkoutmux1_clk_mux {
1013                 #clock-cells = <0>;
1014                 compatible = "ti,mux-clock";
1015                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1016                 reg = <0x015c>;
1017         };
1018
1019         clkoutmux2_clk_mux: clkoutmux2_clk_mux {
1020                 #clock-cells = <0>;
1021                 compatible = "ti,mux-clock";
1022                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1023                 reg = <0x0160>;
1024         };
1025
1026         custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1027                 #clock-cells = <0>;
1028                 compatible = "fixed-factor-clock";
1029                 clocks = <&sys_clkin1>;
1030                 clock-mult = <1>;
1031                 clock-div = <2>;
1032         };
1033
1034         eve_clk: eve_clk {
1035                 #clock-cells = <0>;
1036                 compatible = "ti,mux-clock";
1037                 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1038                 reg = <0x0180>;
1039         };
1040
1041         hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
1042                 #clock-cells = <0>;
1043                 compatible = "ti,mux-clock";
1044                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1045                 reg = <0x0164>;
1046         };
1047
1048         mlb_clk: mlb_clk {
1049                 #clock-cells = <0>;
1050                 compatible = "ti,divider-clock";
1051                 clocks = <&mlb_clkin_ck>;
1052                 ti,max-div = <64>;
1053                 reg = <0x0134>;
1054                 ti,index-power-of-two;
1055         };
1056
1057         mlbp_clk: mlbp_clk {
1058                 #clock-cells = <0>;
1059                 compatible = "ti,divider-clock";
1060                 clocks = <&mlbp_clkin_ck>;
1061                 ti,max-div = <64>;
1062                 reg = <0x0130>;
1063                 ti,index-power-of-two;
1064         };
1065
1066         per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
1067                 #clock-cells = <0>;
1068                 compatible = "ti,divider-clock";
1069                 clocks = <&dpll_abe_m2_ck>;
1070                 ti,max-div = <64>;
1071                 reg = <0x0138>;
1072                 ti,index-power-of-two;
1073         };
1074
1075         timer_sys_clk_div: timer_sys_clk_div {
1076                 #clock-cells = <0>;
1077                 compatible = "ti,divider-clock";
1078                 clocks = <&sys_clkin1>;
1079                 reg = <0x0144>;
1080                 ti,max-div = <2>;
1081         };
1082
1083         video1_dpll_clk_mux: video1_dpll_clk_mux {
1084                 #clock-cells = <0>;
1085                 compatible = "ti,mux-clock";
1086                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1087                 reg = <0x0168>;
1088         };
1089
1090         video2_dpll_clk_mux: video2_dpll_clk_mux {
1091                 #clock-cells = <0>;
1092                 compatible = "ti,mux-clock";
1093                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1094                 reg = <0x016c>;
1095         };
1096
1097         wkupaon_iclk_mux: wkupaon_iclk_mux {
1098                 #clock-cells = <0>;
1099                 compatible = "ti,mux-clock";
1100                 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1101                 reg = <0x0108>;
1102         };
1103
1104         gpio1_dbclk: gpio1_dbclk {
1105                 #clock-cells = <0>;
1106                 compatible = "ti,gate-clock";
1107                 clocks = <&sys_32k_ck>;
1108                 ti,bit-shift = <8>;
1109                 reg = <0x1838>;
1110         };
1111
1112         dcan1_sys_clk_mux: dcan1_sys_clk_mux {
1113                 #clock-cells = <0>;
1114                 compatible = "ti,mux-clock";
1115                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1116                 ti,bit-shift = <24>;
1117                 reg = <0x1888>;
1118         };
1119
1120         timer1_gfclk_mux: timer1_gfclk_mux {
1121                 #clock-cells = <0>;
1122                 compatible = "ti,mux-clock";
1123                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1124                 ti,bit-shift = <24>;
1125                 reg = <0x1840>;
1126         };
1127
1128         uart10_gfclk_mux: uart10_gfclk_mux {
1129                 #clock-cells = <0>;
1130                 compatible = "ti,mux-clock";
1131                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1132                 ti,bit-shift = <24>;
1133                 reg = <0x1880>;
1134         };
1135 };
1136 &cm_core_clocks {
1137         dpll_pcie_ref_ck: dpll_pcie_ref_ck {
1138                 #clock-cells = <0>;
1139                 compatible = "ti,omap4-dpll-clock";
1140                 clocks = <&sys_clkin1>, <&sys_clkin1>;
1141                 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1142         };
1143
1144         dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
1145                 #clock-cells = <0>;
1146                 compatible = "ti,divider-clock";
1147                 clocks = <&dpll_pcie_ref_ck>;
1148                 ti,max-div = <31>;
1149                 ti,autoidle-shift = <8>;
1150                 reg = <0x0210>;
1151                 ti,index-starts-at-one;
1152                 ti,invert-autoidle-bit;
1153         };
1154
1155         apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1156                 compatible = "ti,mux-clock";
1157                 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1158                 #clock-cells = <0>;
1159                 reg = <0x021c 0x4>;
1160                 ti,bit-shift = <7>;
1161         };
1162
1163         apll_pcie_ck: apll_pcie_ck {
1164                 #clock-cells = <0>;
1165                 compatible = "ti,dra7-apll-clock";
1166                 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1167                 reg = <0x021c>, <0x0220>;
1168         };
1169
1170         optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
1171                 compatible = "ti,gate-clock";
1172                 clocks = <&sys_32k_ck>;
1173                 #clock-cells = <0>;
1174                 reg = <0x13b0>;
1175                 ti,bit-shift = <8>;
1176         };
1177
1178         optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
1179                 compatible = "ti,gate-clock";
1180                 clocks = <&sys_32k_ck>;
1181                 #clock-cells = <0>;
1182                 reg = <0x13b8>;
1183                 ti,bit-shift = <8>;
1184         };
1185
1186         optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1187                 compatible = "ti,divider-clock";
1188                 clocks = <&apll_pcie_ck>;
1189                 #clock-cells = <0>;
1190                 reg = <0x021c>;
1191                 ti,dividers = <2>, <1>;
1192                 ti,bit-shift = <8>;
1193                 ti,max-div = <2>;
1194         };
1195
1196         optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
1197                 compatible = "ti,gate-clock";
1198                 clocks = <&apll_pcie_ck>;
1199                 #clock-cells = <0>;
1200                 reg = <0x13b0>;
1201                 ti,bit-shift = <9>;
1202         };
1203
1204         optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
1205                 compatible = "ti,gate-clock";
1206                 clocks = <&apll_pcie_ck>;
1207                 #clock-cells = <0>;
1208                 reg = <0x13b8>;
1209                 ti,bit-shift = <9>;
1210         };
1211
1212         optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
1213                 compatible = "ti,gate-clock";
1214                 clocks = <&optfclk_pciephy_div>;
1215                 #clock-cells = <0>;
1216                 reg = <0x13b0>;
1217                 ti,bit-shift = <10>;
1218         };
1219
1220         optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
1221                 compatible = "ti,gate-clock";
1222                 clocks = <&optfclk_pciephy_div>;
1223                 #clock-cells = <0>;
1224                 reg = <0x13b8>;
1225                 ti,bit-shift = <10>;
1226         };
1227
1228         apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1229                 #clock-cells = <0>;
1230                 compatible = "fixed-factor-clock";
1231                 clocks = <&apll_pcie_ck>;
1232                 clock-mult = <1>;
1233                 clock-div = <1>;
1234         };
1235
1236         apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1237                 #clock-cells = <0>;
1238                 compatible = "fixed-factor-clock";
1239                 clocks = <&apll_pcie_ck>;
1240                 clock-mult = <1>;
1241                 clock-div = <1>;
1242         };
1243
1244         apll_pcie_m2_ck: apll_pcie_m2_ck {
1245                 #clock-cells = <0>;
1246                 compatible = "fixed-factor-clock";
1247                 clocks = <&apll_pcie_ck>;
1248                 clock-mult = <1>;
1249                 clock-div = <1>;
1250         };
1251
1252         dpll_per_ck: dpll_per_ck {
1253                 #clock-cells = <0>;
1254                 compatible = "ti,omap4-dpll-clock";
1255                 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1256                 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1257         };
1258
1259         dpll_per_m2_ck: dpll_per_m2_ck {
1260                 #clock-cells = <0>;
1261                 compatible = "ti,divider-clock";
1262                 clocks = <&dpll_per_ck>;
1263                 ti,max-div = <31>;
1264                 ti,autoidle-shift = <8>;
1265                 reg = <0x0150>;
1266                 ti,index-starts-at-one;
1267                 ti,invert-autoidle-bit;
1268         };
1269
1270         func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1271                 #clock-cells = <0>;
1272                 compatible = "fixed-factor-clock";
1273                 clocks = <&dpll_per_m2_ck>;
1274                 clock-mult = <1>;
1275                 clock-div = <1>;
1276         };
1277
1278         dpll_usb_ck: dpll_usb_ck {
1279                 #clock-cells = <0>;
1280                 compatible = "ti,omap4-dpll-j-type-clock";
1281                 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1282                 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1283         };
1284
1285         dpll_usb_m2_ck: dpll_usb_m2_ck {
1286                 #clock-cells = <0>;
1287                 compatible = "ti,divider-clock";
1288                 clocks = <&dpll_usb_ck>;
1289                 ti,max-div = <127>;
1290                 ti,autoidle-shift = <8>;
1291                 reg = <0x0190>;
1292                 ti,index-starts-at-one;
1293                 ti,invert-autoidle-bit;
1294         };
1295
1296         dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
1297                 #clock-cells = <0>;
1298                 compatible = "ti,divider-clock";
1299                 clocks = <&dpll_pcie_ref_ck>;
1300                 ti,max-div = <127>;
1301                 ti,autoidle-shift = <8>;
1302                 reg = <0x0210>;
1303                 ti,index-starts-at-one;
1304                 ti,invert-autoidle-bit;
1305         };
1306
1307         dpll_per_x2_ck: dpll_per_x2_ck {
1308                 #clock-cells = <0>;
1309                 compatible = "ti,omap4-dpll-x2-clock";
1310                 clocks = <&dpll_per_ck>;
1311         };
1312
1313         dpll_per_h11x2_ck: dpll_per_h11x2_ck {
1314                 #clock-cells = <0>;
1315                 compatible = "ti,divider-clock";
1316                 clocks = <&dpll_per_x2_ck>;
1317                 ti,max-div = <63>;
1318                 ti,autoidle-shift = <8>;
1319                 reg = <0x0158>;
1320                 ti,index-starts-at-one;
1321                 ti,invert-autoidle-bit;
1322         };
1323
1324         dpll_per_h12x2_ck: dpll_per_h12x2_ck {
1325                 #clock-cells = <0>;
1326                 compatible = "ti,divider-clock";
1327                 clocks = <&dpll_per_x2_ck>;
1328                 ti,max-div = <63>;
1329                 ti,autoidle-shift = <8>;
1330                 reg = <0x015c>;
1331                 ti,index-starts-at-one;
1332                 ti,invert-autoidle-bit;
1333         };
1334
1335         dpll_per_h13x2_ck: dpll_per_h13x2_ck {
1336                 #clock-cells = <0>;
1337                 compatible = "ti,divider-clock";
1338                 clocks = <&dpll_per_x2_ck>;
1339                 ti,max-div = <63>;
1340                 ti,autoidle-shift = <8>;
1341                 reg = <0x0160>;
1342                 ti,index-starts-at-one;
1343                 ti,invert-autoidle-bit;
1344         };
1345
1346         dpll_per_h14x2_ck: dpll_per_h14x2_ck {
1347                 #clock-cells = <0>;
1348                 compatible = "ti,divider-clock";
1349                 clocks = <&dpll_per_x2_ck>;
1350                 ti,max-div = <63>;
1351                 ti,autoidle-shift = <8>;
1352                 reg = <0x0164>;
1353                 ti,index-starts-at-one;
1354                 ti,invert-autoidle-bit;
1355         };
1356
1357         dpll_per_m2x2_ck: dpll_per_m2x2_ck {
1358                 #clock-cells = <0>;
1359                 compatible = "ti,divider-clock";
1360                 clocks = <&dpll_per_x2_ck>;
1361                 ti,max-div = <31>;
1362                 ti,autoidle-shift = <8>;
1363                 reg = <0x0150>;
1364                 ti,index-starts-at-one;
1365                 ti,invert-autoidle-bit;
1366         };
1367
1368         dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1369                 #clock-cells = <0>;
1370                 compatible = "fixed-factor-clock";
1371                 clocks = <&dpll_usb_ck>;
1372                 clock-mult = <1>;
1373                 clock-div = <1>;
1374         };
1375
1376         func_128m_clk: func_128m_clk {
1377                 #clock-cells = <0>;
1378                 compatible = "fixed-factor-clock";
1379                 clocks = <&dpll_per_h11x2_ck>;
1380                 clock-mult = <1>;
1381                 clock-div = <2>;
1382         };
1383
1384         func_12m_fclk: func_12m_fclk {
1385                 #clock-cells = <0>;
1386                 compatible = "fixed-factor-clock";
1387                 clocks = <&dpll_per_m2x2_ck>;
1388                 clock-mult = <1>;
1389                 clock-div = <16>;
1390         };
1391
1392         func_24m_clk: func_24m_clk {
1393                 #clock-cells = <0>;
1394                 compatible = "fixed-factor-clock";
1395                 clocks = <&dpll_per_m2_ck>;
1396                 clock-mult = <1>;
1397                 clock-div = <4>;
1398         };
1399
1400         func_48m_fclk: func_48m_fclk {
1401                 #clock-cells = <0>;
1402                 compatible = "fixed-factor-clock";
1403                 clocks = <&dpll_per_m2x2_ck>;
1404                 clock-mult = <1>;
1405                 clock-div = <4>;
1406         };
1407
1408         func_96m_fclk: func_96m_fclk {
1409                 #clock-cells = <0>;
1410                 compatible = "fixed-factor-clock";
1411                 clocks = <&dpll_per_m2x2_ck>;
1412                 clock-mult = <1>;
1413                 clock-div = <2>;
1414         };
1415
1416         l3init_60m_fclk: l3init_60m_fclk {
1417                 #clock-cells = <0>;
1418                 compatible = "ti,divider-clock";
1419                 clocks = <&dpll_usb_m2_ck>;
1420                 reg = <0x0104>;
1421                 ti,dividers = <1>, <8>;
1422         };
1423
1424         l3init_960m_gfclk: l3init_960m_gfclk {
1425                 #clock-cells = <0>;
1426                 compatible = "ti,gate-clock";
1427                 clocks = <&dpll_usb_clkdcoldo>;
1428                 ti,bit-shift = <8>;
1429                 reg = <0x06c0>;
1430         };
1431
1432         dss_32khz_clk: dss_32khz_clk {
1433                 #clock-cells = <0>;
1434                 compatible = "ti,gate-clock";
1435                 clocks = <&sys_32k_ck>;
1436                 ti,bit-shift = <11>;
1437                 reg = <0x1120>;
1438         };
1439
1440         dss_48mhz_clk: dss_48mhz_clk {
1441                 #clock-cells = <0>;
1442                 compatible = "ti,gate-clock";
1443                 clocks = <&func_48m_fclk>;
1444                 ti,bit-shift = <9>;
1445                 reg = <0x1120>;
1446         };
1447
1448         dss_dss_clk: dss_dss_clk {
1449                 #clock-cells = <0>;
1450                 compatible = "ti,gate-clock";
1451                 clocks = <&dpll_per_h12x2_ck>;
1452                 ti,bit-shift = <8>;
1453                 reg = <0x1120>;
1454         };
1455
1456         dss_hdmi_clk: dss_hdmi_clk {
1457                 #clock-cells = <0>;
1458                 compatible = "ti,gate-clock";
1459                 clocks = <&hdmi_dpll_clk_mux>;
1460                 ti,bit-shift = <10>;
1461                 reg = <0x1120>;
1462         };
1463
1464         dss_video1_clk: dss_video1_clk {
1465                 #clock-cells = <0>;
1466                 compatible = "ti,gate-clock";
1467                 clocks = <&video1_dpll_clk_mux>;
1468                 ti,bit-shift = <12>;
1469                 reg = <0x1120>;
1470         };
1471
1472         dss_video2_clk: dss_video2_clk {
1473                 #clock-cells = <0>;
1474                 compatible = "ti,gate-clock";
1475                 clocks = <&video2_dpll_clk_mux>;
1476                 ti,bit-shift = <13>;
1477                 reg = <0x1120>;
1478         };
1479
1480         gpio2_dbclk: gpio2_dbclk {
1481                 #clock-cells = <0>;
1482                 compatible = "ti,gate-clock";
1483                 clocks = <&sys_32k_ck>;
1484                 ti,bit-shift = <8>;
1485                 reg = <0x1760>;
1486         };
1487
1488         gpio3_dbclk: gpio3_dbclk {
1489                 #clock-cells = <0>;
1490                 compatible = "ti,gate-clock";
1491                 clocks = <&sys_32k_ck>;
1492                 ti,bit-shift = <8>;
1493                 reg = <0x1768>;
1494         };
1495
1496         gpio4_dbclk: gpio4_dbclk {
1497                 #clock-cells = <0>;
1498                 compatible = "ti,gate-clock";
1499                 clocks = <&sys_32k_ck>;
1500                 ti,bit-shift = <8>;
1501                 reg = <0x1770>;
1502         };
1503
1504         gpio5_dbclk: gpio5_dbclk {
1505                 #clock-cells = <0>;
1506                 compatible = "ti,gate-clock";
1507                 clocks = <&sys_32k_ck>;
1508                 ti,bit-shift = <8>;
1509                 reg = <0x1778>;
1510         };
1511
1512         gpio6_dbclk: gpio6_dbclk {
1513                 #clock-cells = <0>;
1514                 compatible = "ti,gate-clock";
1515                 clocks = <&sys_32k_ck>;
1516                 ti,bit-shift = <8>;
1517                 reg = <0x1780>;
1518         };
1519
1520         gpio7_dbclk: gpio7_dbclk {
1521                 #clock-cells = <0>;
1522                 compatible = "ti,gate-clock";
1523                 clocks = <&sys_32k_ck>;
1524                 ti,bit-shift = <8>;
1525                 reg = <0x1810>;
1526         };
1527
1528         gpio8_dbclk: gpio8_dbclk {
1529                 #clock-cells = <0>;
1530                 compatible = "ti,gate-clock";
1531                 clocks = <&sys_32k_ck>;
1532                 ti,bit-shift = <8>;
1533                 reg = <0x1818>;
1534         };
1535
1536         mmc1_clk32k: mmc1_clk32k {
1537                 #clock-cells = <0>;
1538                 compatible = "ti,gate-clock";
1539                 clocks = <&sys_32k_ck>;
1540                 ti,bit-shift = <8>;
1541                 reg = <0x1328>;
1542         };
1543
1544         mmc2_clk32k: mmc2_clk32k {
1545                 #clock-cells = <0>;
1546                 compatible = "ti,gate-clock";
1547                 clocks = <&sys_32k_ck>;
1548                 ti,bit-shift = <8>;
1549                 reg = <0x1330>;
1550         };
1551
1552         mmc3_clk32k: mmc3_clk32k {
1553                 #clock-cells = <0>;
1554                 compatible = "ti,gate-clock";
1555                 clocks = <&sys_32k_ck>;
1556                 ti,bit-shift = <8>;
1557                 reg = <0x1820>;
1558         };
1559
1560         mmc4_clk32k: mmc4_clk32k {
1561                 #clock-cells = <0>;
1562                 compatible = "ti,gate-clock";
1563                 clocks = <&sys_32k_ck>;
1564                 ti,bit-shift = <8>;
1565                 reg = <0x1828>;
1566         };
1567
1568         sata_ref_clk: sata_ref_clk {
1569                 #clock-cells = <0>;
1570                 compatible = "ti,gate-clock";
1571                 clocks = <&sys_clkin1>;
1572                 ti,bit-shift = <8>;
1573                 reg = <0x1388>;
1574         };
1575
1576         usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
1577                 #clock-cells = <0>;
1578                 compatible = "ti,gate-clock";
1579                 clocks = <&l3init_960m_gfclk>;
1580                 ti,bit-shift = <8>;
1581                 reg = <0x13f0>;
1582         };
1583
1584         usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
1585                 #clock-cells = <0>;
1586                 compatible = "ti,gate-clock";
1587                 clocks = <&l3init_960m_gfclk>;
1588                 ti,bit-shift = <8>;
1589                 reg = <0x1340>;
1590         };
1591
1592         usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
1593                 #clock-cells = <0>;
1594                 compatible = "ti,gate-clock";
1595                 clocks = <&sys_32k_ck>;
1596                 ti,bit-shift = <8>;
1597                 reg = <0x0640>;
1598         };
1599
1600         usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
1601                 #clock-cells = <0>;
1602                 compatible = "ti,gate-clock";
1603                 clocks = <&sys_32k_ck>;
1604                 ti,bit-shift = <8>;
1605                 reg = <0x0688>;
1606         };
1607
1608         usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
1609                 #clock-cells = <0>;
1610                 compatible = "ti,gate-clock";
1611                 clocks = <&sys_32k_ck>;
1612                 ti,bit-shift = <8>;
1613                 reg = <0x0698>;
1614         };
1615
1616         atl_dpll_clk_mux: atl_dpll_clk_mux {
1617                 #clock-cells = <0>;
1618                 compatible = "ti,mux-clock";
1619                 clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
1620                 ti,bit-shift = <24>;
1621                 reg = <0x0c00>;
1622         };
1623
1624         atl_gfclk_mux: atl_gfclk_mux {
1625                 #clock-cells = <0>;
1626                 compatible = "ti,mux-clock";
1627                 clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
1628                 ti,bit-shift = <26>;
1629                 reg = <0x0c00>;
1630         };
1631
1632         gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
1633                 #clock-cells = <0>;
1634                 compatible = "ti,divider-clock";
1635                 clocks = <&dpll_gmac_m2_ck>;
1636                 ti,bit-shift = <24>;
1637                 reg = <0x13d0>;
1638                 ti,dividers = <2>;
1639         };
1640
1641         gmac_rft_clk_mux: gmac_rft_clk_mux {
1642                 #clock-cells = <0>;
1643                 compatible = "ti,mux-clock";
1644                 clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
1645                 ti,bit-shift = <25>;
1646                 reg = <0x13d0>;
1647         };
1648
1649         gpu_core_gclk_mux: gpu_core_gclk_mux {
1650                 #clock-cells = <0>;
1651                 compatible = "ti,mux-clock";
1652                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1653                 ti,bit-shift = <24>;
1654                 reg = <0x1220>;
1655         };
1656
1657         gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
1658                 #clock-cells = <0>;
1659                 compatible = "ti,mux-clock";
1660                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1661                 ti,bit-shift = <26>;
1662                 reg = <0x1220>;
1663         };
1664
1665         l3instr_ts_gclk_div: l3instr_ts_gclk_div {
1666                 #clock-cells = <0>;
1667                 compatible = "ti,divider-clock";
1668                 clocks = <&wkupaon_iclk_mux>;
1669                 ti,bit-shift = <24>;
1670                 reg = <0x0e50>;
1671                 ti,dividers = <8>, <16>, <32>;
1672         };
1673
1674         mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
1675                 #clock-cells = <0>;
1676                 compatible = "ti,mux-clock";
1677                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1678                 ti,bit-shift = <28>;
1679                 reg = <0x1860>;
1680         };
1681
1682         mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
1683                 #clock-cells = <0>;
1684                 compatible = "ti,mux-clock";
1685                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1686                 ti,bit-shift = <24>;
1687                 reg = <0x1860>;
1688         };
1689
1690         mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
1691                 #clock-cells = <0>;
1692                 compatible = "ti,mux-clock";
1693                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1694                 ti,bit-shift = <22>;
1695                 reg = <0x1860>;
1696         };
1697
1698         mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
1699                 #clock-cells = <0>;
1700                 compatible = "ti,mux-clock";
1701                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1702                 ti,bit-shift = <24>;
1703                 reg = <0x1868>;
1704         };
1705
1706         mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
1707                 #clock-cells = <0>;
1708                 compatible = "ti,mux-clock";
1709                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1710                 ti,bit-shift = <22>;
1711                 reg = <0x1868>;
1712         };
1713
1714         mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
1715                 #clock-cells = <0>;
1716                 compatible = "ti,mux-clock";
1717                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1718                 ti,bit-shift = <24>;
1719                 reg = <0x1898>;
1720         };
1721
1722         mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
1723                 #clock-cells = <0>;
1724                 compatible = "ti,mux-clock";
1725                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1726                 ti,bit-shift = <22>;
1727                 reg = <0x1898>;
1728         };
1729
1730         mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
1731                 #clock-cells = <0>;
1732                 compatible = "ti,mux-clock";
1733                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1734                 ti,bit-shift = <24>;
1735                 reg = <0x1878>;
1736         };
1737
1738         mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
1739                 #clock-cells = <0>;
1740                 compatible = "ti,mux-clock";
1741                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1742                 ti,bit-shift = <22>;
1743                 reg = <0x1878>;
1744         };
1745
1746         mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
1747                 #clock-cells = <0>;
1748                 compatible = "ti,mux-clock";
1749                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1750                 ti,bit-shift = <24>;
1751                 reg = <0x1904>;
1752         };
1753
1754         mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
1755                 #clock-cells = <0>;
1756                 compatible = "ti,mux-clock";
1757                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1758                 ti,bit-shift = <22>;
1759                 reg = <0x1904>;
1760         };
1761
1762         mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
1763                 #clock-cells = <0>;
1764                 compatible = "ti,mux-clock";
1765                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1766                 ti,bit-shift = <24>;
1767                 reg = <0x1908>;
1768         };
1769
1770         mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
1771                 #clock-cells = <0>;
1772                 compatible = "ti,mux-clock";
1773                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1774                 ti,bit-shift = <22>;
1775                 reg = <0x1908>;
1776         };
1777
1778         mcasp8_ahclk_mux: mcasp8_ahclk_mux {
1779                 #clock-cells = <0>;
1780                 compatible = "ti,mux-clock";
1781                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1782                 ti,bit-shift = <22>;
1783                 reg = <0x1890>;
1784         };
1785
1786         mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
1787                 #clock-cells = <0>;
1788                 compatible = "ti,mux-clock";
1789                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1790                 ti,bit-shift = <24>;
1791                 reg = <0x1890>;
1792         };
1793
1794         mmc1_fclk_mux: mmc1_fclk_mux {
1795                 #clock-cells = <0>;
1796                 compatible = "ti,mux-clock";
1797                 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1798                 ti,bit-shift = <24>;
1799                 reg = <0x1328>;
1800         };
1801
1802         mmc1_fclk_div: mmc1_fclk_div {
1803                 #clock-cells = <0>;
1804                 compatible = "ti,divider-clock";
1805                 clocks = <&mmc1_fclk_mux>;
1806                 ti,bit-shift = <25>;
1807                 ti,max-div = <4>;
1808                 reg = <0x1328>;
1809                 ti,index-power-of-two;
1810         };
1811
1812         mmc2_fclk_mux: mmc2_fclk_mux {
1813                 #clock-cells = <0>;
1814                 compatible = "ti,mux-clock";
1815                 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1816                 ti,bit-shift = <24>;
1817                 reg = <0x1330>;
1818         };
1819
1820         mmc2_fclk_div: mmc2_fclk_div {
1821                 #clock-cells = <0>;
1822                 compatible = "ti,divider-clock";
1823                 clocks = <&mmc2_fclk_mux>;
1824                 ti,bit-shift = <25>;
1825                 ti,max-div = <4>;
1826                 reg = <0x1330>;
1827                 ti,index-power-of-two;
1828         };
1829
1830         mmc3_gfclk_mux: mmc3_gfclk_mux {
1831                 #clock-cells = <0>;
1832                 compatible = "ti,mux-clock";
1833                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1834                 ti,bit-shift = <24>;
1835                 reg = <0x1820>;
1836         };
1837
1838         mmc3_gfclk_div: mmc3_gfclk_div {
1839                 #clock-cells = <0>;
1840                 compatible = "ti,divider-clock";
1841                 clocks = <&mmc3_gfclk_mux>;
1842                 ti,bit-shift = <25>;
1843                 ti,max-div = <4>;
1844                 reg = <0x1820>;
1845                 ti,index-power-of-two;
1846         };
1847
1848         mmc4_gfclk_mux: mmc4_gfclk_mux {
1849                 #clock-cells = <0>;
1850                 compatible = "ti,mux-clock";
1851                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1852                 ti,bit-shift = <24>;
1853                 reg = <0x1828>;
1854         };
1855
1856         mmc4_gfclk_div: mmc4_gfclk_div {
1857                 #clock-cells = <0>;
1858                 compatible = "ti,divider-clock";
1859                 clocks = <&mmc4_gfclk_mux>;
1860                 ti,bit-shift = <25>;
1861                 ti,max-div = <4>;
1862                 reg = <0x1828>;
1863                 ti,index-power-of-two;
1864         };
1865
1866         qspi_gfclk_mux: qspi_gfclk_mux {
1867                 #clock-cells = <0>;
1868                 compatible = "ti,mux-clock";
1869                 clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
1870                 ti,bit-shift = <24>;
1871                 reg = <0x1838>;
1872         };
1873
1874         qspi_gfclk_div: qspi_gfclk_div {
1875                 #clock-cells = <0>;
1876                 compatible = "ti,divider-clock";
1877                 clocks = <&qspi_gfclk_mux>;
1878                 ti,bit-shift = <25>;
1879                 ti,max-div = <4>;
1880                 reg = <0x1838>;
1881                 ti,index-power-of-two;
1882         };
1883
1884         timer10_gfclk_mux: timer10_gfclk_mux {
1885                 #clock-cells = <0>;
1886                 compatible = "ti,mux-clock";
1887                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1888                 ti,bit-shift = <24>;
1889                 reg = <0x1728>;
1890         };
1891
1892         timer11_gfclk_mux: timer11_gfclk_mux {
1893                 #clock-cells = <0>;
1894                 compatible = "ti,mux-clock";
1895                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1896                 ti,bit-shift = <24>;
1897                 reg = <0x1730>;
1898         };
1899
1900         timer13_gfclk_mux: timer13_gfclk_mux {
1901                 #clock-cells = <0>;
1902                 compatible = "ti,mux-clock";
1903                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1904                 ti,bit-shift = <24>;
1905                 reg = <0x17c8>;
1906         };
1907
1908         timer14_gfclk_mux: timer14_gfclk_mux {
1909                 #clock-cells = <0>;
1910                 compatible = "ti,mux-clock";
1911                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1912                 ti,bit-shift = <24>;
1913                 reg = <0x17d0>;
1914         };
1915
1916         timer15_gfclk_mux: timer15_gfclk_mux {
1917                 #clock-cells = <0>;
1918                 compatible = "ti,mux-clock";
1919                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1920                 ti,bit-shift = <24>;
1921                 reg = <0x17d8>;
1922         };
1923
1924         timer16_gfclk_mux: timer16_gfclk_mux {
1925                 #clock-cells = <0>;
1926                 compatible = "ti,mux-clock";
1927                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1928                 ti,bit-shift = <24>;
1929                 reg = <0x1830>;
1930         };
1931
1932         timer2_gfclk_mux: timer2_gfclk_mux {
1933                 #clock-cells = <0>;
1934                 compatible = "ti,mux-clock";
1935                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1936                 ti,bit-shift = <24>;
1937                 reg = <0x1738>;
1938         };
1939
1940         timer3_gfclk_mux: timer3_gfclk_mux {
1941                 #clock-cells = <0>;
1942                 compatible = "ti,mux-clock";
1943                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1944                 ti,bit-shift = <24>;
1945                 reg = <0x1740>;
1946         };
1947
1948         timer4_gfclk_mux: timer4_gfclk_mux {
1949                 #clock-cells = <0>;
1950                 compatible = "ti,mux-clock";
1951                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1952                 ti,bit-shift = <24>;
1953                 reg = <0x1748>;
1954         };
1955
1956         timer9_gfclk_mux: timer9_gfclk_mux {
1957                 #clock-cells = <0>;
1958                 compatible = "ti,mux-clock";
1959                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1960                 ti,bit-shift = <24>;
1961                 reg = <0x1750>;
1962         };
1963
1964         uart1_gfclk_mux: uart1_gfclk_mux {
1965                 #clock-cells = <0>;
1966                 compatible = "ti,mux-clock";
1967                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1968                 ti,bit-shift = <24>;
1969                 reg = <0x1840>;
1970         };
1971
1972         uart2_gfclk_mux: uart2_gfclk_mux {
1973                 #clock-cells = <0>;
1974                 compatible = "ti,mux-clock";
1975                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1976                 ti,bit-shift = <24>;
1977                 reg = <0x1848>;
1978         };
1979
1980         uart3_gfclk_mux: uart3_gfclk_mux {
1981                 #clock-cells = <0>;
1982                 compatible = "ti,mux-clock";
1983                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1984                 ti,bit-shift = <24>;
1985                 reg = <0x1850>;
1986         };
1987
1988         uart4_gfclk_mux: uart4_gfclk_mux {
1989                 #clock-cells = <0>;
1990                 compatible = "ti,mux-clock";
1991                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1992                 ti,bit-shift = <24>;
1993                 reg = <0x1858>;
1994         };
1995
1996         uart5_gfclk_mux: uart5_gfclk_mux {
1997                 #clock-cells = <0>;
1998                 compatible = "ti,mux-clock";
1999                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2000                 ti,bit-shift = <24>;
2001                 reg = <0x1870>;
2002         };
2003
2004         uart7_gfclk_mux: uart7_gfclk_mux {
2005                 #clock-cells = <0>;
2006                 compatible = "ti,mux-clock";
2007                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2008                 ti,bit-shift = <24>;
2009                 reg = <0x18d0>;
2010         };
2011
2012         uart8_gfclk_mux: uart8_gfclk_mux {
2013                 #clock-cells = <0>;
2014                 compatible = "ti,mux-clock";
2015                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2016                 ti,bit-shift = <24>;
2017                 reg = <0x18e0>;
2018         };
2019
2020         uart9_gfclk_mux: uart9_gfclk_mux {
2021                 #clock-cells = <0>;
2022                 compatible = "ti,mux-clock";
2023                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2024                 ti,bit-shift = <24>;
2025                 reg = <0x18e8>;
2026         };
2027
2028         vip1_gclk_mux: vip1_gclk_mux {
2029                 #clock-cells = <0>;
2030                 compatible = "ti,mux-clock";
2031                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2032                 ti,bit-shift = <24>;
2033                 reg = <0x1020>;
2034         };
2035
2036         vip2_gclk_mux: vip2_gclk_mux {
2037                 #clock-cells = <0>;
2038                 compatible = "ti,mux-clock";
2039                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2040                 ti,bit-shift = <24>;
2041                 reg = <0x1028>;
2042         };
2043
2044         vip3_gclk_mux: vip3_gclk_mux {
2045                 #clock-cells = <0>;
2046                 compatible = "ti,mux-clock";
2047                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2048                 ti,bit-shift = <24>;
2049                 reg = <0x1030>;
2050         };
2051 };
2052
2053 &cm_core_clockdomains {
2054         coreaon_clkdm: coreaon_clkdm {
2055                 compatible = "ti,clockdomain";
2056                 clocks = <&dpll_usb_ck>;
2057         };
2058 };