arch/arm/boot/dts/exynos3250.dtsi

   1 /*
   2  * Samsung's Exynos3250 SoC device tree source
   3  *
   4  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include "skeleton.dtsi"
  21 #include <dt-bindings/clock/exynos3250.h>
  22
  23 / {
  24         compatible = "samsung,exynos3250";
  25         interrupt-parent = <&gic>;
  26
  27         aliases {
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 mshc0 = &mshc_0;
  31                 mshc1 = &mshc_1;
  32                 spi0 = &spi_0;
  33                 spi1 = &spi_1;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &i2c_4;
  39                 i2c5 = &i2c_5;
  40                 i2c6 = &i2c_6;
  41                 i2c7 = &i2c_7;
  42                 serial0 = &serial_0;
  43                 serial1 = &serial_1;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu0: cpu@0 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <0>;
  54                         clock-frequency = <1000000000>;
  55                 };
  56
  57                 cpu1: cpu@1 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a7";
  60                         reg = <1>;
  61                         clock-frequency = <1000000000>;
  62                 };
  63         };
  64
  65         soc: soc {
  66                 compatible = "simple-bus";
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 fixed-rate-clocks {
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74
  75                         xusbxti: clock@0 {
  76                                 compatible = "fixed-clock";
  77                                 #address-cells = <1>;
  78                                 #size-cells = <0>;
  79                                 reg = <0>;
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                                 clock-output-names = "xusbxti";
  83                         };
  84
  85                         xxti: clock@1 {
  86                                 compatible = "fixed-clock";
  87                                 reg = <1>;
  88                                 clock-frequency = <0>;
  89                                 #clock-cells = <0>;
  90                                 clock-output-names = "xxti";
  91                         };
  92
  93                         xtcxo: clock@2 {
  94                                 compatible = "fixed-clock";
  95                                 reg = <2>;
  96                                 clock-frequency = <0>;
  97                                 #clock-cells = <0>;
  98                                 clock-output-names = "xtcxo";
  99                         };
 100                 };
 101
 102                 sysram@02020000 {
 103                         compatible = "mmio-sram";
 104                         reg = <0x02020000 0x40000>;
 105                         #address-cells = <1>;
 106                         #size-cells = <1>;
 107                         ranges = <0 0x02020000 0x40000>;
 108
 109                         smp-sysram@0 {
 110                                 compatible = "samsung,exynos4210-sysram";
 111                                 reg = <0x0 0x1000>;
 112                         };
 113
 114                         smp-sysram@3f000 {
 115                                 compatible = "samsung,exynos4210-sysram-ns";
 116                                 reg = <0x3f000 0x1000>;
 117                         };
 118                 };
 119
 120                 chipid@10000000 {
 121                         compatible = "samsung,exynos4210-chipid";
 122                         reg = <0x10000000 0x100>;
 123                 };
 124
 125                 sys_reg: syscon@10010000 {
 126                         compatible = "samsung,exynos3-sysreg", "syscon";
 127                         reg = <0x10010000 0x400>;
 128                 };
 129
 130                 pmu_system_controller: system-controller@10020000 {
 131                         compatible = "samsung,exynos3250-pmu", "syscon";
 132                         reg = <0x10020000 0x4000>;
 133                 };
 134
 135                 mipi_phy: video-phy@10020710 {
 136                         compatible = "samsung,s5pv210-mipi-video-phy";
 137                         reg = <0x10020710 8>;
 138                         #phy-cells = <1>;
 139                 };
 140
 141                 pd_cam: cam-power-domain@10023C00 {
 142                         compatible = "samsung,exynos4210-pd";
 143                         reg = <0x10023C00 0x20>;
 144                 };
 145
 146                 pd_mfc: mfc-power-domain@10023C40 {
 147                         compatible = "samsung,exynos4210-pd";
 148                         reg = <0x10023C40 0x20>;
 149                 };
 150
 151                 pd_g3d: g3d-power-domain@10023C60 {
 152                         compatible = "samsung,exynos4210-pd";
 153                         reg = <0x10023C60 0x20>;
 154                 };
 155
 156                 pd_lcd0: lcd0-power-domain@10023C80 {
 157                         compatible = "samsung,exynos4210-pd";
 158                         reg = <0x10023C80 0x20>;
 159                 };
 160
 161                 pd_isp: isp-power-domain@10023CA0 {
 162                         compatible = "samsung,exynos4210-pd";
 163                         reg = <0x10023CA0 0x20>;
 164                 };
 165
 166                 cmu: clock-controller@10030000 {
 167                         compatible = "samsung,exynos3250-cmu";
 168                         reg = <0x10030000 0x20000>;
 169                         #clock-cells = <1>;
 170                 };
 171
 172                 cmu_dmc: clock-controller@105C0000 {
 173                         compatible = "samsung,exynos3250-cmu-dmc";
 174                         reg = <0x105C0000 0x2000>;
 175                         #clock-cells = <1>;
 176                 };
 177
 178                 rtc: rtc@10070000 {
 179                         compatible = "samsung,exynos3250-rtc";
 180                         reg = <0x10070000 0x100>;
 181                         interrupts = <0 73 0>, <0 74 0>;
 182                         status = "disabled";
 183                 };
 184
 185                 tmu: tmu@100C0000 {
 186                         compatible = "samsung,exynos3250-tmu";
 187                         reg = <0x100C0000 0x100>;
 188                         interrupts = <0 216 0>;
 189                         clocks = <&cmu CLK_TMU_APBIF>;
 190                         clock-names = "tmu_apbif";
 191                         status = "disabled";
 192                 };
 193
 194                 gic: interrupt-controller@10481000 {
 195                         compatible = "arm,cortex-a15-gic";
 196                         #interrupt-cells = <3>;
 197                         interrupt-controller;
 198                         reg = <0x10481000 0x1000>,
 199                               <0x10482000 0x1000>,
 200                               <0x10484000 0x2000>,
 201                               <0x10486000 0x2000>;
 202                         interrupts = <1 9 0xf04>;
 203                 };
 204
 205                 mct@10050000 {
 206                         compatible = "samsung,exynos4210-mct";
 207                         reg = <0x10050000 0x800>;
 208                         interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
 209                                      <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
 210                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 211                         clock-names = "fin_pll", "mct";
 212                 };
 213
 214                 pinctrl_1: pinctrl@11000000 {
 215                         compatible = "samsung,exynos3250-pinctrl";
 216                         reg = <0x11000000 0x1000>;
 217                         interrupts = <0 225 0>;
 218
 219                         wakeup-interrupt-controller {
 220                                 compatible = "samsung,exynos4210-wakeup-eint";
 221                                 interrupts = <0 48 0>;
 222                         };
 223                 };
 224
 225                 pinctrl_0: pinctrl@11400000 {
 226                         compatible = "samsung,exynos3250-pinctrl";
 227                         reg = <0x11400000 0x1000>;
 228                         interrupts = <0 240 0>;
 229                 };
 230
 231                 fimd: fimd@11c00000 {
 232                         compatible = "samsung,exynos3250-fimd";
 233                         reg = <0x11c00000 0x30000>;
 234                         interrupt-names = "fifo", "vsync", "lcd_sys";
 235                         interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
 236                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
 237                         clock-names = "sclk_fimd", "fimd";
 238                         samsung,power-domain = <&pd_lcd0>;
 239                         samsung,sysreg = <&sys_reg>;
 240                         status = "disabled";
 241                 };
 242
 243                 dsi_0: dsi@11C80000 {
 244                         compatible = "samsung,exynos3250-mipi-dsi";
 245                         reg = <0x11C80000 0x10000>;
 246                         interrupts = <0 83 0>;
 247                         samsung,phy-type = <0>;
 248                         samsung,power-domain = <&pd_lcd0>;
 249                         phys = <&mipi_phy 1>;
 250                         phy-names = "dsim";
 251                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
 252                         clock-names = "bus_clk", "pll_clk";
 253                         #address-cells = <1>;
 254                         #size-cells = <0>;
 255                         status = "disabled";
 256                 };
 257
 258                 mshc_0: mshc@12510000 {
 259                         compatible = "samsung,exynos5250-dw-mshc";
 260                         reg = <0x12510000 0x1000>;
 261                         interrupts = <0 142 0>;
 262                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 263                         clock-names = "biu", "ciu";
 264                         fifo-depth = <0x80>;
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267                         status = "disabled";
 268                 };
 269
 270                 mshc_1: mshc@12520000 {
 271                         compatible = "samsung,exynos5250-dw-mshc";
 272                         reg = <0x12520000 0x1000>;
 273                         interrupts = <0 143 0>;
 274                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 275                         clock-names = "biu", "ciu";
 276                         fifo-depth = <0x80>;
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                         status = "disabled";
 280                 };
 281
 282                 amba {
 283                         compatible = "arm,amba-bus";
 284                         #address-cells = <1>;
 285                         #size-cells = <1>;
 286                         ranges;
 287
 288                         pdma0: pdma@12680000 {
 289                                 compatible = "arm,pl330", "arm,primecell";
 290                                 reg = <0x12680000 0x1000>;
 291                                 interrupts = <0 138 0>;
 292                                 clocks = <&cmu CLK_PDMA0>;
 293                                 clock-names = "apb_pclk";
 294                                 #dma-cells = <1>;
 295                                 #dma-channels = <8>;
 296                                 #dma-requests = <32>;
 297                         };
 298
 299                         pdma1: pdma@12690000 {
 300                                 compatible = "arm,pl330", "arm,primecell";
 301                                 reg = <0x12690000 0x1000>;
 302                                 interrupts = <0 139 0>;
 303                                 clocks = <&cmu CLK_PDMA1>;
 304                                 clock-names = "apb_pclk";
 305                                 #dma-cells = <1>;
 306                                 #dma-channels = <8>;
 307                                 #dma-requests = <32>;
 308                         };
 309                 };
 310
 311                 adc: adc@126C0000 {
 312                         compatible = "samsung,exynos3250-adc",
 313                                      "samsung,exynos-adc-v2";
 314                         reg = <0x126C0000 0x100>;
 315                         interrupts = <0 137 0>;
 316                         clock-names = "adc", "sclk";
 317                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 318                         #io-channel-cells = <1>;
 319                         io-channel-ranges;
 320                         samsung,syscon-phandle = <&pmu_system_controller>;
 321                         status = "disabled";
 322                 };
 323
 324                 mfc: codec@13400000 {
 325                         compatible = "samsung,mfc-v7";
 326                         reg = <0x13400000 0x10000>;
 327                         interrupts = <0 102 0>;
 328                         clock-names = "mfc", "sclk_mfc";
 329                         clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
 330                         samsung,power-domain = <&pd_mfc>;
 331                         status = "disabled";
 332                 };
 333
 334                 serial_0: serial@13800000 {
 335                         compatible = "samsung,exynos4210-uart";
 336                         reg = <0x13800000 0x100>;
 337                         interrupts = <0 109 0>;
 338                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 339                         clock-names = "uart", "clk_uart_baud0";
 340                         pinctrl-names = "default";
 341                         pinctrl-0 = <&uart0_data &uart0_fctl>;
 342                         status = "disabled";
 343                 };
 344
 345                 serial_1: serial@13810000 {
 346                         compatible = "samsung,exynos4210-uart";
 347                         reg = <0x13810000 0x100>;
 348                         interrupts = <0 110 0>;
 349                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 350                         clock-names = "uart", "clk_uart_baud0";
 351                         pinctrl-names = "default";
 352                         pinctrl-0 = <&uart1_data>;
 353                         status = "disabled";
 354                 };
 355
 356                 i2c_0: i2c@13860000 {
 357                         #address-cells = <1>;
 358                         #size-cells = <0>;
 359                         compatible = "samsung,s3c2440-i2c";
 360                         reg = <0x13860000 0x100>;
 361                         interrupts = <0 113 0>;
 362                         clocks = <&cmu CLK_I2C0>;
 363                         clock-names = "i2c";
 364                         pinctrl-names = "default";
 365                         pinctrl-0 = <&i2c0_bus>;
 366                         status = "disabled";
 367                 };
 368
 369                 i2c_1: i2c@13870000 {
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         compatible = "samsung,s3c2440-i2c";
 373                         reg = <0x13870000 0x100>;
 374                         interrupts = <0 114 0>;
 375                         clocks = <&cmu CLK_I2C1>;
 376                         clock-names = "i2c";
 377                         pinctrl-names = "default";
 378                         pinctrl-0 = <&i2c1_bus>;
 379                         status = "disabled";
 380                 };
 381
 382                 i2c_2: i2c@13880000 {
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         compatible = "samsung,s3c2440-i2c";
 386                         reg = <0x13880000 0x100>;
 387                         interrupts = <0 115 0>;
 388                         clocks = <&cmu CLK_I2C2>;
 389                         clock-names = "i2c";
 390                         pinctrl-names = "default";
 391                         pinctrl-0 = <&i2c2_bus>;
 392                         status = "disabled";
 393                 };
 394
 395                 i2c_3: i2c@13890000 {
 396                         #address-cells = <1>;
 397                         #size-cells = <0>;
 398                         compatible = "samsung,s3c2440-i2c";
 399                         reg = <0x13890000 0x100>;
 400                         interrupts = <0 116 0>;
 401                         clocks = <&cmu CLK_I2C3>;
 402                         clock-names = "i2c";
 403                         pinctrl-names = "default";
 404                         pinctrl-0 = <&i2c3_bus>;
 405                         status = "disabled";
 406                 };
 407
 408                 i2c_4: i2c@138A0000 {
 409                         #address-cells = <1>;
 410                         #size-cells = <0>;
 411                         compatible = "samsung,s3c2440-i2c";
 412                         reg = <0x138A0000 0x100>;
 413                         interrupts = <0 117 0>;
 414                         clocks = <&cmu CLK_I2C4>;
 415                         clock-names = "i2c";
 416                         pinctrl-names = "default";
 417                         pinctrl-0 = <&i2c4_bus>;
 418                         status = "disabled";
 419                 };
 420
 421                 i2c_5: i2c@138B0000 {
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         compatible = "samsung,s3c2440-i2c";
 425                         reg = <0x138B0000 0x100>;
 426                         interrupts = <0 118 0>;
 427                         clocks = <&cmu CLK_I2C5>;
 428                         clock-names = "i2c";
 429                         pinctrl-names = "default";
 430                         pinctrl-0 = <&i2c5_bus>;
 431                         status = "disabled";
 432                 };
 433
 434                 i2c_6: i2c@138C0000 {
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         compatible = "samsung,s3c2440-i2c";
 438                         reg = <0x138C0000 0x100>;
 439                         interrupts = <0 119 0>;
 440                         clocks = <&cmu CLK_I2C6>;
 441                         clock-names = "i2c";
 442                         pinctrl-names = "default";
 443                         pinctrl-0 = <&i2c6_bus>;
 444                         status = "disabled";
 445                 };
 446
 447                 i2c_7: i2c@138D0000 {
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         compatible = "samsung,s3c2440-i2c";
 451                         reg = <0x138D0000 0x100>;
 452                         interrupts = <0 120 0>;
 453                         clocks = <&cmu CLK_I2C7>;
 454                         clock-names = "i2c";
 455                         pinctrl-names = "default";
 456                         pinctrl-0 = <&i2c7_bus>;
 457                         status = "disabled";
 458                 };
 459
 460                 spi_0: spi@13920000 {
 461                         compatible = "samsung,exynos4210-spi";
 462                         reg = <0x13920000 0x100>;
 463                         interrupts = <0 121 0>;
 464                         dmas = <&pdma0 7>, <&pdma0 6>;
 465                         dma-names = "tx", "rx";
 466                         #address-cells = <1>;
 467                         #size-cells = <0>;
 468                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 469                         clock-names = "spi", "spi_busclk0";
 470                         samsung,spi-src-clk = <0>;
 471                         pinctrl-names = "default";
 472                         pinctrl-0 = <&spi0_bus>;
 473                         status = "disabled";
 474                 };
 475
 476                 spi_1: spi@13930000 {
 477                         compatible = "samsung,exynos4210-spi";
 478                         reg = <0x13930000 0x100>;
 479                         interrupts = <0 122 0>;
 480                         dmas = <&pdma1 7>, <&pdma1 6>;
 481                         dma-names = "tx", "rx";
 482                         #address-cells = <1>;
 483                         #size-cells = <0>;
 484                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 485                         clock-names = "spi", "spi_busclk0";
 486                         samsung,spi-src-clk = <0>;
 487                         pinctrl-names = "default";
 488                         pinctrl-0 = <&spi1_bus>;
 489                         status = "disabled";
 490                 };
 491
 492                 i2s2: i2s@13970000 {
 493                         compatible = "samsung,s3c6410-i2s";
 494                         reg = <0x13970000 0x100>;
 495                         interrupts = <0 126 0>;
 496                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
 497                         clock-names = "iis", "i2s_opclk0";
 498                         dmas = <&pdma0 14>, <&pdma0 13>;
 499                         dma-names = "tx", "rx";
 500                         pinctrl-0 = <&i2s2_bus>;
 501                         pinctrl-names = "default";
 502                         status = "disabled";
 503                 };
 504
 505                 pwm: pwm@139D0000 {
 506                         compatible = "samsung,exynos4210-pwm";
 507                         reg = <0x139D0000 0x1000>;
 508                         interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
 509                                      <0 107 0>, <0 108 0>;
 510                         #pwm-cells = <3>;
 511                         status = "disabled";
 512                 };
 513
 514                 pmu {
 515                         compatible = "arm,cortex-a7-pmu";
 516                         interrupts = <0 18 0>, <0 19 0>;
 517                 };
 518         };
 519 };
 520
 521 #include "exynos3250-pinctrl.dtsi"