arch/arm/boot/dts/exynos5250.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5250 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
   8  * EXYNOS5250 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  13  * additional nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include <dt-bindings/clock/exynos5250.h>
  21 #include "exynos5.dtsi"
  22 #include "exynos5250-pinctrl.dtsi"
  23
  24 #include <dt-bindings/clock/exynos-audss-clk.h>
  25
  26 / {
  27         compatible = "samsung,exynos5250", "samsung,exynos5";
  28
  29         aliases {
  30                 spi0 = &spi_0;
  31                 spi1 = &spi_1;
  32                 spi2 = &spi_2;
  33                 gsc0 = &gsc_0;
  34                 gsc1 = &gsc_1;
  35                 gsc2 = &gsc_2;
  36                 gsc3 = &gsc_3;
  37                 mshc0 = &mmc_0;
  38                 mshc1 = &mmc_1;
  39                 mshc2 = &mmc_2;
  40                 mshc3 = &mmc_3;
  41                 i2c0 = &i2c_0;
  42                 i2c1 = &i2c_1;
  43                 i2c2 = &i2c_2;
  44                 i2c3 = &i2c_3;
  45                 i2c4 = &i2c_4;
  46                 i2c5 = &i2c_5;
  47                 i2c6 = &i2c_6;
  48                 i2c7 = &i2c_7;
  49                 i2c8 = &i2c_8;
  50                 i2c9 = &i2c_9;
  51                 pinctrl0 = &pinctrl_0;
  52                 pinctrl1 = &pinctrl_1;
  53                 pinctrl2 = &pinctrl_2;
  54                 pinctrl3 = &pinctrl_3;
  55         };
  56
  57         cpus {
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 cpu@0 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a15";
  64                         reg = <0>;
  65                         clock-frequency = <1700000000>;
  66                 };
  67                 cpu@1 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a15";
  70                         reg = <1>;
  71                         clock-frequency = <1700000000>;
  72                 };
  73         };
  74
  75         sysram@02020000 {
  76                 compatible = "mmio-sram";
  77                 reg = <0x02020000 0x30000>;
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 ranges = <0 0x02020000 0x30000>;
  81
  82                 smp-sysram@0 {
  83                         compatible = "samsung,exynos4210-sysram";
  84                         reg = <0x0 0x1000>;
  85                 };
  86
  87                 smp-sysram@2f000 {
  88                         compatible = "samsung,exynos4210-sysram-ns";
  89                         reg = <0x2f000 0x1000>;
  90                 };
  91         };
  92
  93         pd_gsc: gsc-power-domain@10044000 {
  94                 compatible = "samsung,exynos4210-pd";
  95                 reg = <0x10044000 0x20>;
  96         };
  97
  98         pd_mfc: mfc-power-domain@10044040 {
  99                 compatible = "samsung,exynos4210-pd";
 100                 reg = <0x10044040 0x20>;
 101         };
 102
 103         clock: clock-controller@10010000 {
 104                 compatible = "samsung,exynos5250-clock";
 105                 reg = <0x10010000 0x30000>;
 106                 #clock-cells = <1>;
 107         };
 108
 109         clock_audss: audss-clock-controller@3810000 {
 110                 compatible = "samsung,exynos5250-audss-clock";
 111                 reg = <0x03810000 0x0C>;
 112                 #clock-cells = <1>;
 113                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 114                          <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
 115                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 116         };
 117
 118         timer {
 119                 compatible = "arm,armv7-timer";
 120                 interrupts = <1 13 0xf08>,
 121                              <1 14 0xf08>,
 122                              <1 11 0xf08>,
 123                              <1 10 0xf08>;
 124                 /* Unfortunately we need this since some versions of U-Boot
 125                  * on Exynos don't set the CNTFRQ register, so we need the
 126                  * value from DT.
 127                  */
 128                 clock-frequency = <24000000>;
 129         };
 130
 131         mct@101C0000 {
 132                 compatible = "samsung,exynos4210-mct";
 133                 reg = <0x101C0000 0x800>;
 134                 interrupt-controller;
 135                 #interrups-cells = <2>;
 136                 interrupt-parent = <&mct_map>;
 137                 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 138                              <4 0>, <5 0>;
 139                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 140                 clock-names = "fin_pll", "mct";
 141
 142                 mct_map: mct-map {
 143                         #interrupt-cells = <2>;
 144                         #address-cells = <0>;
 145                         #size-cells = <0>;
 146                         interrupt-map = <0x0 0 &combiner 23 3>,
 147                                         <0x1 0 &combiner 23 4>,
 148                                         <0x2 0 &combiner 25 2>,
 149                                         <0x3 0 &combiner 25 3>,
 150                                         <0x4 0 &gic 0 120 0>,
 151                                         <0x5 0 &gic 0 121 0>;
 152                 };
 153         };
 154
 155         pmu {
 156                 compatible = "arm,cortex-a15-pmu";
 157                 interrupt-parent = <&combiner>;
 158                 interrupts = <1 2>, <22 4>;
 159         };
 160
 161         pinctrl_0: pinctrl@11400000 {
 162                 compatible = "samsung,exynos5250-pinctrl";
 163                 reg = <0x11400000 0x1000>;
 164                 interrupts = <0 46 0>;
 165
 166                 wakup_eint: wakeup-interrupt-controller {
 167                         compatible = "samsung,exynos4210-wakeup-eint";
 168                         interrupt-parent = <&gic>;
 169                         interrupts = <0 32 0>;
 170                 };
 171         };
 172
 173         pinctrl_1: pinctrl@13400000 {
 174                 compatible = "samsung,exynos5250-pinctrl";
 175                 reg = <0x13400000 0x1000>;
 176                 interrupts = <0 45 0>;
 177         };
 178
 179         pinctrl_2: pinctrl@10d10000 {
 180                 compatible = "samsung,exynos5250-pinctrl";
 181                 reg = <0x10d10000 0x1000>;
 182                 interrupts = <0 50 0>;
 183         };
 184
 185         pinctrl_3: pinctrl@03860000 {
 186                 compatible = "samsung,exynos5250-pinctrl";
 187                 reg = <0x03860000 0x1000>;
 188                 interrupts = <0 47 0>;
 189         };
 190
 191         pmu_system_controller: system-controller@10040000 {
 192                 compatible = "samsung,exynos5250-pmu", "syscon";
 193                 reg = <0x10040000 0x5000>;
 194                 clock-names = "clkout16";
 195                 clocks = <&clock CLK_FIN_PLL>;
 196                 #clock-cells = <1>;
 197         };
 198
 199         sysreg_system_controller: syscon@10050000 {
 200                 compatible = "samsung,exynos5-sysreg", "syscon";
 201                 reg = <0x10050000 0x5000>;
 202         };
 203
 204         watchdog@101D0000 {
 205                 compatible = "samsung,exynos5250-wdt";
 206                 reg = <0x101D0000 0x100>;
 207                 interrupts = <0 42 0>;
 208                 clocks = <&clock CLK_WDT>;
 209                 clock-names = "watchdog";
 210                 samsung,syscon-phandle = <&pmu_system_controller>;
 211         };
 212
 213         g2d@10850000 {
 214                 compatible = "samsung,exynos5250-g2d";
 215                 reg = <0x10850000 0x1000>;
 216                 interrupts = <0 91 0>;
 217                 clocks = <&clock CLK_G2D>;
 218                 clock-names = "fimg2d";
 219         };
 220
 221         mfc: codec@11000000 {
 222                 compatible = "samsung,mfc-v6";
 223                 reg = <0x11000000 0x10000>;
 224                 interrupts = <0 96 0>;
 225                 samsung,power-domain = <&pd_mfc>;
 226                 clocks = <&clock CLK_MFC>;
 227                 clock-names = "mfc";
 228         };
 229
 230         rtc: rtc@101E0000 {
 231                 clocks = <&clock CLK_RTC>;
 232                 clock-names = "rtc";
 233                 status = "disabled";
 234         };
 235
 236         tmu@10060000 {
 237                 compatible = "samsung,exynos5250-tmu";
 238                 reg = <0x10060000 0x100>;
 239                 interrupts = <0 65 0>;
 240                 clocks = <&clock CLK_TMU>;
 241                 clock-names = "tmu_apbif";
 242         };
 243
 244         serial@12C00000 {
 245                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 246                 clock-names = "uart", "clk_uart_baud0";
 247         };
 248
 249         serial@12C10000 {
 250                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 251                 clock-names = "uart", "clk_uart_baud0";
 252         };
 253
 254         serial@12C20000 {
 255                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 256                 clock-names = "uart", "clk_uart_baud0";
 257         };
 258
 259         serial@12C30000 {
 260                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 261                 clock-names = "uart", "clk_uart_baud0";
 262         };
 263
 264         sata: sata@122F0000 {
 265                 compatible = "snps,dwc-ahci";
 266                 samsung,sata-freq = <66>;
 267                 reg = <0x122F0000 0x1ff>;
 268                 interrupts = <0 115 0>;
 269                 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
 270                 clock-names = "sata", "sclk_sata";
 271                 phys = <&sata_phy>;
 272                 phy-names = "sata-phy";
 273                 status = "disabled";
 274         };
 275
 276         sata_phy: sata-phy@12170000 {
 277                 compatible = "samsung,exynos5250-sata-phy";
 278                 reg = <0x12170000 0x1ff>;
 279                 clocks = <&clock CLK_SATA_PHYCTRL>;
 280                 clock-names = "sata_phyctrl";
 281                 #phy-cells = <0>;
 282                 samsung,syscon-phandle = <&pmu_system_controller>;
 283                 status = "disabled";
 284         };
 285
 286         i2c_0: i2c@12C60000 {
 287                 compatible = "samsung,s3c2440-i2c";
 288                 reg = <0x12C60000 0x100>;
 289                 interrupts = <0 56 0>;
 290                 #address-cells = <1>;
 291                 #size-cells = <0>;
 292                 clocks = <&clock CLK_I2C0>;
 293                 clock-names = "i2c";
 294                 pinctrl-names = "default";
 295                 pinctrl-0 = <&i2c0_bus>;
 296                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 297                 status = "disabled";
 298         };
 299
 300         i2c_1: i2c@12C70000 {
 301                 compatible = "samsung,s3c2440-i2c";
 302                 reg = <0x12C70000 0x100>;
 303                 interrupts = <0 57 0>;
 304                 #address-cells = <1>;
 305                 #size-cells = <0>;
 306                 clocks = <&clock CLK_I2C1>;
 307                 clock-names = "i2c";
 308                 pinctrl-names = "default";
 309                 pinctrl-0 = <&i2c1_bus>;
 310                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 311                 status = "disabled";
 312         };
 313
 314         i2c_2: i2c@12C80000 {
 315                 compatible = "samsung,s3c2440-i2c";
 316                 reg = <0x12C80000 0x100>;
 317                 interrupts = <0 58 0>;
 318                 #address-cells = <1>;
 319                 #size-cells = <0>;
 320                 clocks = <&clock CLK_I2C2>;
 321                 clock-names = "i2c";
 322                 pinctrl-names = "default";
 323                 pinctrl-0 = <&i2c2_bus>;
 324                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 325                 status = "disabled";
 326         };
 327
 328         i2c_3: i2c@12C90000 {
 329                 compatible = "samsung,s3c2440-i2c";
 330                 reg = <0x12C90000 0x100>;
 331                 interrupts = <0 59 0>;
 332                 #address-cells = <1>;
 333                 #size-cells = <0>;
 334                 clocks = <&clock CLK_I2C3>;
 335                 clock-names = "i2c";
 336                 pinctrl-names = "default";
 337                 pinctrl-0 = <&i2c3_bus>;
 338                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 339                 status = "disabled";
 340         };
 341
 342         i2c_4: i2c@12CA0000 {
 343                 compatible = "samsung,s3c2440-i2c";
 344                 reg = <0x12CA0000 0x100>;
 345                 interrupts = <0 60 0>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 clocks = <&clock CLK_I2C4>;
 349                 clock-names = "i2c";
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&i2c4_bus>;
 352                 status = "disabled";
 353         };
 354
 355         i2c_5: i2c@12CB0000 {
 356                 compatible = "samsung,s3c2440-i2c";
 357                 reg = <0x12CB0000 0x100>;
 358                 interrupts = <0 61 0>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clocks = <&clock CLK_I2C5>;
 362                 clock-names = "i2c";
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&i2c5_bus>;
 365                 status = "disabled";
 366         };
 367
 368         i2c_6: i2c@12CC0000 {
 369                 compatible = "samsung,s3c2440-i2c";
 370                 reg = <0x12CC0000 0x100>;
 371                 interrupts = <0 62 0>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 clocks = <&clock CLK_I2C6>;
 375                 clock-names = "i2c";
 376                 pinctrl-names = "default";
 377                 pinctrl-0 = <&i2c6_bus>;
 378                 status = "disabled";
 379         };
 380
 381         i2c_7: i2c@12CD0000 {
 382                 compatible = "samsung,s3c2440-i2c";
 383                 reg = <0x12CD0000 0x100>;
 384                 interrupts = <0 63 0>;
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 clocks = <&clock CLK_I2C7>;
 388                 clock-names = "i2c";
 389                 pinctrl-names = "default";
 390                 pinctrl-0 = <&i2c7_bus>;
 391                 status = "disabled";
 392         };
 393
 394         i2c_8: i2c@12CE0000 {
 395                 compatible = "samsung,s3c2440-hdmiphy-i2c";
 396                 reg = <0x12CE0000 0x1000>;
 397                 interrupts = <0 64 0>;
 398                 #address-cells = <1>;
 399                 #size-cells = <0>;
 400                 clocks = <&clock CLK_I2C_HDMI>;
 401                 clock-names = "i2c";
 402                 status = "disabled";
 403         };
 404
 405         i2c_9: i2c@121D0000 {
 406                 compatible = "samsung,exynos5-sata-phy-i2c";
 407                 reg = <0x121D0000 0x100>;
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 clocks = <&clock CLK_SATA_PHYI2C>;
 411                 clock-names = "i2c";
 412                 status = "disabled";
 413         };
 414
 415         spi_0: spi@12d20000 {
 416                 compatible = "samsung,exynos4210-spi";
 417                 status = "disabled";
 418                 reg = <0x12d20000 0x100>;
 419                 interrupts = <0 66 0>;
 420                 dmas = <&pdma0 5
 421                         &pdma0 4>;
 422                 dma-names = "tx", "rx";
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 426                 clock-names = "spi", "spi_busclk0";
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&spi0_bus>;
 429         };
 430
 431         spi_1: spi@12d30000 {
 432                 compatible = "samsung,exynos4210-spi";
 433                 status = "disabled";
 434                 reg = <0x12d30000 0x100>;
 435                 interrupts = <0 67 0>;
 436                 dmas = <&pdma1 5
 437                         &pdma1 4>;
 438                 dma-names = "tx", "rx";
 439                 #address-cells = <1>;
 440                 #size-cells = <0>;
 441                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 442                 clock-names = "spi", "spi_busclk0";
 443                 pinctrl-names = "default";
 444                 pinctrl-0 = <&spi1_bus>;
 445         };
 446
 447         spi_2: spi@12d40000 {
 448                 compatible = "samsung,exynos4210-spi";
 449                 status = "disabled";
 450                 reg = <0x12d40000 0x100>;
 451                 interrupts = <0 68 0>;
 452                 dmas = <&pdma0 7
 453                         &pdma0 6>;
 454                 dma-names = "tx", "rx";
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 458                 clock-names = "spi", "spi_busclk0";
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&spi2_bus>;
 461         };
 462
 463         mmc_0: mmc@12200000 {
 464                 compatible = "samsung,exynos5250-dw-mshc";
 465                 interrupts = <0 75 0>;
 466                 #address-cells = <1>;
 467                 #size-cells = <0>;
 468                 reg = <0x12200000 0x1000>;
 469                 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 470                 clock-names = "biu", "ciu";
 471                 fifo-depth = <0x80>;
 472                 status = "disabled";
 473         };
 474
 475         mmc_1: mmc@12210000 {
 476                 compatible = "samsung,exynos5250-dw-mshc";
 477                 interrupts = <0 76 0>;
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 reg = <0x12210000 0x1000>;
 481                 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 482                 clock-names = "biu", "ciu";
 483                 fifo-depth = <0x80>;
 484                 status = "disabled";
 485         };
 486
 487         mmc_2: mmc@12220000 {
 488                 compatible = "samsung,exynos5250-dw-mshc";
 489                 interrupts = <0 77 0>;
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 reg = <0x12220000 0x1000>;
 493                 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 494                 clock-names = "biu", "ciu";
 495                 fifo-depth = <0x80>;
 496                 status = "disabled";
 497         };
 498
 499         mmc_3: mmc@12230000 {
 500                 compatible = "samsung,exynos5250-dw-mshc";
 501                 reg = <0x12230000 0x1000>;
 502                 interrupts = <0 78 0>;
 503                 #address-cells = <1>;
 504                 #size-cells = <0>;
 505                 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 506                 clock-names = "biu", "ciu";
 507                 fifo-depth = <0x80>;
 508                 status = "disabled";
 509         };
 510
 511         i2s0: i2s@03830000 {
 512                 compatible = "samsung,s5pv210-i2s";
 513                 status = "disabled";
 514                 reg = <0x03830000 0x100>;
 515                 dmas = <&pdma0 10
 516                         &pdma0 9
 517                         &pdma0 8>;
 518                 dma-names = "tx", "rx", "tx-sec";
 519                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 520                         <&clock_audss EXYNOS_I2S_BUS>,
 521                         <&clock_audss EXYNOS_SCLK_I2S>;
 522                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 523                 samsung,idma-addr = <0x03000000>;
 524                 pinctrl-names = "default";
 525                 pinctrl-0 = <&i2s0_bus>;
 526         };
 527
 528         i2s1: i2s@12D60000 {
 529                 compatible = "samsung,s3c6410-i2s";
 530                 status = "disabled";
 531                 reg = <0x12D60000 0x100>;
 532                 dmas = <&pdma1 12
 533                         &pdma1 11>;
 534                 dma-names = "tx", "rx";
 535                 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
 536                 clock-names = "iis", "i2s_opclk0";
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&i2s1_bus>;
 539         };
 540
 541         i2s2: i2s@12D70000 {
 542                 compatible = "samsung,s3c6410-i2s";
 543                 status = "disabled";
 544                 reg = <0x12D70000 0x100>;
 545                 dmas = <&pdma0 12
 546                         &pdma0 11>;
 547                 dma-names = "tx", "rx";
 548                 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
 549                 clock-names = "iis", "i2s_opclk0";
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2s2_bus>;
 552         };
 553
 554         usb@12000000 {
 555                 compatible = "samsung,exynos5250-dwusb3";
 556                 clocks = <&clock CLK_USB3>;
 557                 clock-names = "usbdrd30";
 558                 #address-cells = <1>;
 559                 #size-cells = <1>;
 560                 ranges;
 561
 562                 usbdrd_dwc3: dwc3 {
 563                         compatible = "synopsys,dwc3";
 564                         reg = <0x12000000 0x10000>;
 565                         interrupts = <0 72 0>;
 566                         phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 567                         phy-names = "usb2-phy", "usb3-phy";
 568                 };
 569         };
 570
 571         usbdrd_phy: phy@12100000 {
 572                 compatible = "samsung,exynos5250-usbdrd-phy";
 573                 reg = <0x12100000 0x100>;
 574                 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
 575                 clock-names = "phy", "ref";
 576                 samsung,pmu-syscon = <&pmu_system_controller>;
 577                 #phy-cells = <1>;
 578         };
 579
 580         ehci: usb@12110000 {
 581                 compatible = "samsung,exynos4210-ehci";
 582                 reg = <0x12110000 0x100>;
 583                 interrupts = <0 71 0>;
 584
 585                 clocks = <&clock CLK_USB2>;
 586                 clock-names = "usbhost";
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 port@0 {
 590                         reg = <0>;
 591                         phys = <&usb2_phy_gen 1>;
 592                 };
 593         };
 594
 595         ohci: usb@12120000 {
 596                 compatible = "samsung,exynos4210-ohci";
 597                 reg = <0x12120000 0x100>;
 598                 interrupts = <0 71 0>;
 599
 600                 clocks = <&clock CLK_USB2>;
 601                 clock-names = "usbhost";
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 port@0 {
 605                         reg = <0>;
 606                         phys = <&usb2_phy_gen 1>;
 607                 };
 608         };
 609
 610         usb2_phy_gen: phy@12130000 {
 611                 compatible = "samsung,exynos5250-usb2-phy";
 612                 reg = <0x12130000 0x100>;
 613                 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
 614                 clock-names = "phy", "ref";
 615                 #phy-cells = <1>;
 616                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 617                 samsung,pmureg-phandle = <&pmu_system_controller>;
 618         };
 619
 620         pwm: pwm@12dd0000 {
 621                 compatible = "samsung,exynos4210-pwm";
 622                 reg = <0x12dd0000 0x100>;
 623                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 624                 #pwm-cells = <3>;
 625                 clocks = <&clock CLK_PWM>;
 626                 clock-names = "timers";
 627         };
 628
 629         amba {
 630                 #address-cells = <1>;
 631                 #size-cells = <1>;
 632                 compatible = "arm,amba-bus";
 633                 interrupt-parent = <&gic>;
 634                 ranges;
 635
 636                 pdma0: pdma@121A0000 {
 637                         compatible = "arm,pl330", "arm,primecell";
 638                         reg = <0x121A0000 0x1000>;
 639                         interrupts = <0 34 0>;
 640                         clocks = <&clock CLK_PDMA0>;
 641                         clock-names = "apb_pclk";
 642                         #dma-cells = <1>;
 643                         #dma-channels = <8>;
 644                         #dma-requests = <32>;
 645                 };
 646
 647                 pdma1: pdma@121B0000 {
 648                         compatible = "arm,pl330", "arm,primecell";
 649                         reg = <0x121B0000 0x1000>;
 650                         interrupts = <0 35 0>;
 651                         clocks = <&clock CLK_PDMA1>;
 652                         clock-names = "apb_pclk";
 653                         #dma-cells = <1>;
 654                         #dma-channels = <8>;
 655                         #dma-requests = <32>;
 656                 };
 657
 658                 mdma0: mdma@10800000 {
 659                         compatible = "arm,pl330", "arm,primecell";
 660                         reg = <0x10800000 0x1000>;
 661                         interrupts = <0 33 0>;
 662                         clocks = <&clock CLK_MDMA0>;
 663                         clock-names = "apb_pclk";
 664                         #dma-cells = <1>;
 665                         #dma-channels = <8>;
 666                         #dma-requests = <1>;
 667                 };
 668
 669                 mdma1: mdma@11C10000 {
 670                         compatible = "arm,pl330", "arm,primecell";
 671                         reg = <0x11C10000 0x1000>;
 672                         interrupts = <0 124 0>;
 673                         clocks = <&clock CLK_MDMA1>;
 674                         clock-names = "apb_pclk";
 675                         #dma-cells = <1>;
 676                         #dma-channels = <8>;
 677                         #dma-requests = <1>;
 678                 };
 679         };
 680
 681         gsc_0:  gsc@13e00000 {
 682                 compatible = "samsung,exynos5-gsc";
 683                 reg = <0x13e00000 0x1000>;
 684                 interrupts = <0 85 0>;
 685                 samsung,power-domain = <&pd_gsc>;
 686                 clocks = <&clock CLK_GSCL0>;
 687                 clock-names = "gscl";
 688         };
 689
 690         gsc_1:  gsc@13e10000 {
 691                 compatible = "samsung,exynos5-gsc";
 692                 reg = <0x13e10000 0x1000>;
 693                 interrupts = <0 86 0>;
 694                 samsung,power-domain = <&pd_gsc>;
 695                 clocks = <&clock CLK_GSCL1>;
 696                 clock-names = "gscl";
 697         };
 698
 699         gsc_2:  gsc@13e20000 {
 700                 compatible = "samsung,exynos5-gsc";
 701                 reg = <0x13e20000 0x1000>;
 702                 interrupts = <0 87 0>;
 703                 samsung,power-domain = <&pd_gsc>;
 704                 clocks = <&clock CLK_GSCL2>;
 705                 clock-names = "gscl";
 706         };
 707
 708         gsc_3:  gsc@13e30000 {
 709                 compatible = "samsung,exynos5-gsc";
 710                 reg = <0x13e30000 0x1000>;
 711                 interrupts = <0 88 0>;
 712                 samsung,power-domain = <&pd_gsc>;
 713                 clocks = <&clock CLK_GSCL3>;
 714                 clock-names = "gscl";
 715         };
 716
 717         hdmi: hdmi {
 718                 compatible = "samsung,exynos4212-hdmi";
 719                 reg = <0x14530000 0x70000>;
 720                 interrupts = <0 95 0>;
 721                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 722                          <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 723                          <&clock CLK_MOUT_HDMI>;
 724                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 725                                 "sclk_hdmiphy", "mout_hdmi";
 726                 samsung,syscon-phandle = <&pmu_system_controller>;
 727         };
 728
 729         mixer {
 730                 compatible = "samsung,exynos5250-mixer";
 731                 reg = <0x14450000 0x10000>;
 732                 interrupts = <0 94 0>;
 733                 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
 734                 clock-names = "mixer", "sclk_hdmi";
 735         };
 736
 737         dp_phy: video-phy@10040720 {
 738                 compatible = "samsung,exynos5250-dp-video-phy";
 739                 reg = <0x10040720 4>;
 740                 #phy-cells = <0>;
 741         };
 742
 743         dp: dp-controller@145B0000 {
 744                 clocks = <&clock CLK_DP>;
 745                 clock-names = "dp";
 746                 phys = <&dp_phy>;
 747                 phy-names = "dp";
 748         };
 749
 750         fimd: fimd@14400000 {
 751                 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
 752                 clock-names = "sclk_fimd", "fimd";
 753         };
 754
 755         adc: adc@12D10000 {
 756                 compatible = "samsung,exynos-adc-v1";
 757                 reg = <0x12D10000 0x100>;
 758                 interrupts = <0 106 0>;
 759                 clocks = <&clock CLK_ADC>;
 760                 clock-names = "adc";
 761                 #io-channel-cells = <1>;
 762                 io-channel-ranges;
 763                 samsung,syscon-phandle = <&pmu_system_controller>;
 764                 status = "disabled";
 765         };
 766
 767         sss@10830000 {
 768                 compatible = "samsung,exynos4210-secss";
 769                 reg = <0x10830000 0x10000>;
 770                 interrupts = <0 112 0>;
 771                 clocks = <&clock CLK_SSS>;
 772                 clock-names = "secss";
 773         };
 774 };