arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5420.h>
  17 #include "exynos5.dtsi"
  18 #include "exynos5420-pinctrl.dtsi"
  19
  20 #include <dt-bindings/clock/exynos-audss-clk.h>
  21
  22 / {
  23         compatible = "samsung,exynos5420", "samsung,exynos5";
  24
  25         aliases {
  26                 mshc0 = &mmc_0;
  27                 mshc1 = &mmc_1;
  28                 mshc2 = &mmc_2;
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 pinctrl2 = &pinctrl_2;
  32                 pinctrl3 = &pinctrl_3;
  33                 pinctrl4 = &pinctrl_4;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &hsi2c_4;
  39                 i2c5 = &hsi2c_5;
  40                 i2c6 = &hsi2c_6;
  41                 i2c7 = &hsi2c_7;
  42                 i2c8 = &hsi2c_8;
  43                 i2c9 = &hsi2c_9;
  44                 i2c10 = &hsi2c_10;
  45                 gsc0 = &gsc_0;
  46                 gsc1 = &gsc_1;
  47                 spi0 = &spi_0;
  48                 spi1 = &spi_1;
  49                 spi2 = &spi_2;
  50                 usbdrdphy0 = &usbdrd_phy0;
  51                 usbdrdphy1 = &usbdrd_phy1;
  52         };
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@0 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a15";
  61                         reg = <0x0>;
  62                         clock-frequency = <1800000000>;
  63                         cci-control-port = <&cci_control1>;
  64                 };
  65
  66                 cpu1: cpu@1 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a15";
  69                         reg = <0x1>;
  70                         clock-frequency = <1800000000>;
  71                         cci-control-port = <&cci_control1>;
  72                 };
  73
  74                 cpu2: cpu@2 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a15";
  77                         reg = <0x2>;
  78                         clock-frequency = <1800000000>;
  79                         cci-control-port = <&cci_control1>;
  80                 };
  81
  82                 cpu3: cpu@3 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a15";
  85                         reg = <0x3>;
  86                         clock-frequency = <1800000000>;
  87                         cci-control-port = <&cci_control1>;
  88                 };
  89
  90                 cpu4: cpu@100 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0x100>;
  94                         clock-frequency = <1000000000>;
  95                         cci-control-port = <&cci_control0>;
  96                 };
  97
  98                 cpu5: cpu@101 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a7";
 101                         reg = <0x101>;
 102                         clock-frequency = <1000000000>;
 103                         cci-control-port = <&cci_control0>;
 104                 };
 105
 106                 cpu6: cpu@102 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a7";
 109                         reg = <0x102>;
 110                         clock-frequency = <1000000000>;
 111                         cci-control-port = <&cci_control0>;
 112                 };
 113
 114                 cpu7: cpu@103 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a7";
 117                         reg = <0x103>;
 118                         clock-frequency = <1000000000>;
 119                         cci-control-port = <&cci_control0>;
 120                 };
 121         };
 122
 123         cci: cci@10d20000 {
 124                 compatible = "arm,cci-400";
 125                 #address-cells = <1>;
 126                 #size-cells = <1>;
 127                 reg = <0x10d20000 0x1000>;
 128                 ranges = <0x0 0x10d20000 0x6000>;
 129
 130                 cci_control0: slave-if@4000 {
 131                         compatible = "arm,cci-400-ctrl-if";
 132                         interface-type = "ace";
 133                         reg = <0x4000 0x1000>;
 134                 };
 135                 cci_control1: slave-if@5000 {
 136                         compatible = "arm,cci-400-ctrl-if";
 137                         interface-type = "ace";
 138                         reg = <0x5000 0x1000>;
 139                 };
 140         };
 141
 142         sysram@02020000 {
 143                 compatible = "mmio-sram";
 144                 reg = <0x02020000 0x54000>;
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 ranges = <0 0x02020000 0x54000>;
 148
 149                 smp-sysram@0 {
 150                         compatible = "samsung,exynos4210-sysram";
 151                         reg = <0x0 0x1000>;
 152                 };
 153
 154                 smp-sysram@53000 {
 155                         compatible = "samsung,exynos4210-sysram-ns";
 156                         reg = <0x53000 0x1000>;
 157                 };
 158         };
 159
 160         clock: clock-controller@10010000 {
 161                 compatible = "samsung,exynos5420-clock";
 162                 reg = <0x10010000 0x30000>;
 163                 #clock-cells = <1>;
 164         };
 165
 166         clock_audss: audss-clock-controller@3810000 {
 167                 compatible = "samsung,exynos5420-audss-clock";
 168                 reg = <0x03810000 0x0C>;
 169                 #clock-cells = <1>;
 170                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 171                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 172                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 173         };
 174
 175         mfc: codec@11000000 {
 176                 compatible = "samsung,mfc-v7";
 177                 reg = <0x11000000 0x10000>;
 178                 interrupts = <0 96 0>;
 179                 clocks = <&clock CLK_MFC>;
 180                 clock-names = "mfc";
 181                 samsung,power-domain = <&mfc_pd>;
 182         };
 183
 184         mmc_0: mmc@12200000 {
 185                 compatible = "samsung,exynos5420-dw-mshc-smu";
 186                 interrupts = <0 75 0>;
 187                 #address-cells = <1>;
 188                 #size-cells = <0>;
 189                 reg = <0x12200000 0x2000>;
 190                 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 191                 clock-names = "biu", "ciu";
 192                 fifo-depth = <0x40>;
 193                 status = "disabled";
 194         };
 195
 196         mmc_1: mmc@12210000 {
 197                 compatible = "samsung,exynos5420-dw-mshc-smu";
 198                 interrupts = <0 76 0>;
 199                 #address-cells = <1>;
 200                 #size-cells = <0>;
 201                 reg = <0x12210000 0x2000>;
 202                 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 203                 clock-names = "biu", "ciu";
 204                 fifo-depth = <0x40>;
 205                 status = "disabled";
 206         };
 207
 208         mmc_2: mmc@12220000 {
 209                 compatible = "samsung,exynos5420-dw-mshc";
 210                 interrupts = <0 77 0>;
 211                 #address-cells = <1>;
 212                 #size-cells = <0>;
 213                 reg = <0x12220000 0x1000>;
 214                 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 215                 clock-names = "biu", "ciu";
 216                 fifo-depth = <0x40>;
 217                 status = "disabled";
 218         };
 219
 220         mct: mct@101C0000 {
 221                 compatible = "samsung,exynos4210-mct";
 222                 reg = <0x101C0000 0x800>;
 223                 interrupt-controller;
 224                 #interrups-cells = <1>;
 225                 interrupt-parent = <&mct_map>;
 226                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 227                                 <8>, <9>, <10>, <11>;
 228                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 229                 clock-names = "fin_pll", "mct";
 230
 231                 mct_map: mct-map {
 232                         #interrupt-cells = <1>;
 233                         #address-cells = <0>;
 234                         #size-cells = <0>;
 235                         interrupt-map = <0 &combiner 23 3>,
 236                                         <1 &combiner 23 4>,
 237                                         <2 &combiner 25 2>,
 238                                         <3 &combiner 25 3>,
 239                                         <4 &gic 0 120 0>,
 240                                         <5 &gic 0 121 0>,
 241                                         <6 &gic 0 122 0>,
 242                                         <7 &gic 0 123 0>,
 243                                         <8 &gic 0 128 0>,
 244                                         <9 &gic 0 129 0>,
 245                                         <10 &gic 0 130 0>,
 246                                         <11 &gic 0 131 0>;
 247                 };
 248         };
 249
 250         gsc_pd: power-domain@10044000 {
 251                 compatible = "samsung,exynos4210-pd";
 252                 reg = <0x10044000 0x20>;
 253         };
 254
 255         isp_pd: power-domain@10044020 {
 256                 compatible = "samsung,exynos4210-pd";
 257                 reg = <0x10044020 0x20>;
 258         };
 259
 260         mfc_pd: power-domain@10044060 {
 261                 compatible = "samsung,exynos4210-pd";
 262                 reg = <0x10044060 0x20>;
 263                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
 264                         <&clock CLK_MOUT_USER_ACLK333>;
 265                 clock-names = "oscclk", "pclk0", "clk0";
 266         };
 267
 268         msc_pd: power-domain@10044120 {
 269                 compatible = "samsung,exynos4210-pd";
 270                 reg = <0x10044120 0x20>;
 271         };
 272
 273         pinctrl_0: pinctrl@13400000 {
 274                 compatible = "samsung,exynos5420-pinctrl";
 275                 reg = <0x13400000 0x1000>;
 276                 interrupts = <0 45 0>;
 277
 278                 wakeup-interrupt-controller {
 279                         compatible = "samsung,exynos4210-wakeup-eint";
 280                         interrupt-parent = <&gic>;
 281                         interrupts = <0 32 0>;
 282                 };
 283         };
 284
 285         pinctrl_1: pinctrl@13410000 {
 286                 compatible = "samsung,exynos5420-pinctrl";
 287                 reg = <0x13410000 0x1000>;
 288                 interrupts = <0 78 0>;
 289         };
 290
 291         pinctrl_2: pinctrl@14000000 {
 292                 compatible = "samsung,exynos5420-pinctrl";
 293                 reg = <0x14000000 0x1000>;
 294                 interrupts = <0 46 0>;
 295         };
 296
 297         pinctrl_3: pinctrl@14010000 {
 298                 compatible = "samsung,exynos5420-pinctrl";
 299                 reg = <0x14010000 0x1000>;
 300                 interrupts = <0 50 0>;
 301         };
 302
 303         pinctrl_4: pinctrl@03860000 {
 304                 compatible = "samsung,exynos5420-pinctrl";
 305                 reg = <0x03860000 0x1000>;
 306                 interrupts = <0 47 0>;
 307         };
 308
 309         rtc: rtc@101E0000 {
 310                 clocks = <&clock CLK_RTC>;
 311                 clock-names = "rtc";
 312                 status = "disabled";
 313         };
 314
 315         amba {
 316                 #address-cells = <1>;
 317                 #size-cells = <1>;
 318                 compatible = "arm,amba-bus";
 319                 interrupt-parent = <&gic>;
 320                 ranges;
 321
 322                 adma: adma@03880000 {
 323                         compatible = "arm,pl330", "arm,primecell";
 324                         reg = <0x03880000 0x1000>;
 325                         interrupts = <0 110 0>;
 326                         clocks = <&clock_audss EXYNOS_ADMA>;
 327                         clock-names = "apb_pclk";
 328                         #dma-cells = <1>;
 329                         #dma-channels = <6>;
 330                         #dma-requests = <16>;
 331                 };
 332
 333                 pdma0: pdma@121A0000 {
 334                         compatible = "arm,pl330", "arm,primecell";
 335                         reg = <0x121A0000 0x1000>;
 336                         interrupts = <0 34 0>;
 337                         clocks = <&clock CLK_PDMA0>;
 338                         clock-names = "apb_pclk";
 339                         #dma-cells = <1>;
 340                         #dma-channels = <8>;
 341                         #dma-requests = <32>;
 342                 };
 343
 344                 pdma1: pdma@121B0000 {
 345                         compatible = "arm,pl330", "arm,primecell";
 346                         reg = <0x121B0000 0x1000>;
 347                         interrupts = <0 35 0>;
 348                         clocks = <&clock CLK_PDMA1>;
 349                         clock-names = "apb_pclk";
 350                         #dma-cells = <1>;
 351                         #dma-channels = <8>;
 352                         #dma-requests = <32>;
 353                 };
 354
 355                 mdma0: mdma@10800000 {
 356                         compatible = "arm,pl330", "arm,primecell";
 357                         reg = <0x10800000 0x1000>;
 358                         interrupts = <0 33 0>;
 359                         clocks = <&clock CLK_MDMA0>;
 360                         clock-names = "apb_pclk";
 361                         #dma-cells = <1>;
 362                         #dma-channels = <8>;
 363                         #dma-requests = <1>;
 364                 };
 365
 366                 mdma1: mdma@11C10000 {
 367                         compatible = "arm,pl330", "arm,primecell";
 368                         reg = <0x11C10000 0x1000>;
 369                         interrupts = <0 124 0>;
 370                         clocks = <&clock CLK_MDMA1>;
 371                         clock-names = "apb_pclk";
 372                         #dma-cells = <1>;
 373                         #dma-channels = <8>;
 374                         #dma-requests = <1>;
 375                         /*
 376                          * MDMA1 can support both secure and non-secure
 377                          * AXI transactions. When this is enabled in the kernel
 378                          * for boards that run in secure mode, we are getting
 379                          * imprecise external aborts causing the kernel to oops.
 380                          */
 381                         status = "disabled";
 382                 };
 383         };
 384
 385         i2s0: i2s@03830000 {
 386                 compatible = "samsung,exynos5420-i2s";
 387                 reg = <0x03830000 0x100>;
 388                 dmas = <&adma 0
 389                         &adma 2
 390                         &adma 1>;
 391                 dma-names = "tx", "rx", "tx-sec";
 392                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 393                         <&clock_audss EXYNOS_I2S_BUS>,
 394                         <&clock_audss EXYNOS_SCLK_I2S>;
 395                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 396                 samsung,idma-addr = <0x03000000>;
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&i2s0_bus>;
 399                 status = "disabled";
 400         };
 401
 402         i2s1: i2s@12D60000 {
 403                 compatible = "samsung,exynos5420-i2s";
 404                 reg = <0x12D60000 0x100>;
 405                 dmas = <&pdma1 12
 406                         &pdma1 11>;
 407                 dma-names = "tx", "rx";
 408                 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 409                 clock-names = "iis", "i2s_opclk0";
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&i2s1_bus>;
 412                 status = "disabled";
 413         };
 414
 415         i2s2: i2s@12D70000 {
 416                 compatible = "samsung,exynos5420-i2s";
 417                 reg = <0x12D70000 0x100>;
 418                 dmas = <&pdma0 12
 419                         &pdma0 11>;
 420                 dma-names = "tx", "rx";
 421                 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 422                 clock-names = "iis", "i2s_opclk0";
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&i2s2_bus>;
 425                 status = "disabled";
 426         };
 427
 428         spi_0: spi@12d20000 {
 429                 compatible = "samsung,exynos4210-spi";
 430                 reg = <0x12d20000 0x100>;
 431                 interrupts = <0 68 0>;
 432                 dmas = <&pdma0 5
 433                         &pdma0 4>;
 434                 dma-names = "tx", "rx";
 435                 #address-cells = <1>;
 436                 #size-cells = <0>;
 437                 pinctrl-names = "default";
 438                 pinctrl-0 = <&spi0_bus>;
 439                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 440                 clock-names = "spi", "spi_busclk0";
 441                 status = "disabled";
 442         };
 443
 444         spi_1: spi@12d30000 {
 445                 compatible = "samsung,exynos4210-spi";
 446                 reg = <0x12d30000 0x100>;
 447                 interrupts = <0 69 0>;
 448                 dmas = <&pdma1 5
 449                         &pdma1 4>;
 450                 dma-names = "tx", "rx";
 451                 #address-cells = <1>;
 452                 #size-cells = <0>;
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&spi1_bus>;
 455                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 456                 clock-names = "spi", "spi_busclk0";
 457                 status = "disabled";
 458         };
 459
 460         spi_2: spi@12d40000 {
 461                 compatible = "samsung,exynos4210-spi";
 462                 reg = <0x12d40000 0x100>;
 463                 interrupts = <0 70 0>;
 464                 dmas = <&pdma0 7
 465                         &pdma0 6>;
 466                 dma-names = "tx", "rx";
 467                 #address-cells = <1>;
 468                 #size-cells = <0>;
 469                 pinctrl-names = "default";
 470                 pinctrl-0 = <&spi2_bus>;
 471                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 472                 clock-names = "spi", "spi_busclk0";
 473                 status = "disabled";
 474         };
 475
 476         uart_0: serial@12C00000 {
 477                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 478                 clock-names = "uart", "clk_uart_baud0";
 479         };
 480
 481         uart_1: serial@12C10000 {
 482                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 483                 clock-names = "uart", "clk_uart_baud0";
 484         };
 485
 486         uart_2: serial@12C20000 {
 487                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 488                 clock-names = "uart", "clk_uart_baud0";
 489         };
 490
 491         uart_3: serial@12C30000 {
 492                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 493                 clock-names = "uart", "clk_uart_baud0";
 494         };
 495
 496         pwm: pwm@12dd0000 {
 497                 compatible = "samsung,exynos4210-pwm";
 498                 reg = <0x12dd0000 0x100>;
 499                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 500                 #pwm-cells = <3>;
 501                 clocks = <&clock CLK_PWM>;
 502                 clock-names = "timers";
 503         };
 504
 505         dp_phy: video-phy@10040728 {
 506                 compatible = "samsung,exynos5250-dp-video-phy";
 507                 reg = <0x10040728 4>;
 508                 #phy-cells = <0>;
 509         };
 510
 511         dp: dp-controller@145B0000 {
 512                 clocks = <&clock CLK_DP1>;
 513                 clock-names = "dp";
 514                 phys = <&dp_phy>;
 515                 phy-names = "dp";
 516         };
 517
 518         mipi_phy: video-phy@10040714 {
 519                 compatible = "samsung,s5pv210-mipi-video-phy";
 520                 reg = <0x10040714 12>;
 521                 #phy-cells = <1>;
 522         };
 523
 524         dsi@14500000 {
 525                 compatible = "samsung,exynos5410-mipi-dsi";
 526                 reg = <0x14500000 0x10000>;
 527                 interrupts = <0 82 0>;
 528                 phys = <&mipi_phy 1>;
 529                 phy-names = "dsim";
 530                 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
 531                 clock-names = "bus_clk", "pll_clk";
 532                 #address-cells = <1>;
 533                 #size-cells = <0>;
 534                 status = "disabled";
 535         };
 536
 537         fimd: fimd@14400000 {
 538                 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
 539                 clock-names = "sclk_fimd", "fimd";
 540         };
 541
 542         adc: adc@12D10000 {
 543                 compatible = "samsung,exynos-adc-v2";
 544                 reg = <0x12D10000 0x100>;
 545                 interrupts = <0 106 0>;
 546                 clocks = <&clock CLK_TSADC>;
 547                 clock-names = "adc";
 548                 #io-channel-cells = <1>;
 549                 io-channel-ranges;
 550                 samsung,syscon-phandle = <&pmu_system_controller>;
 551                 status = "disabled";
 552         };
 553
 554         i2c_0: i2c@12C60000 {
 555                 compatible = "samsung,s3c2440-i2c";
 556                 reg = <0x12C60000 0x100>;
 557                 interrupts = <0 56 0>;
 558                 #address-cells = <1>;
 559                 #size-cells = <0>;
 560                 clocks = <&clock CLK_I2C0>;
 561                 clock-names = "i2c";
 562                 pinctrl-names = "default";
 563                 pinctrl-0 = <&i2c0_bus>;
 564                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 565                 status = "disabled";
 566         };
 567
 568         i2c_1: i2c@12C70000 {
 569                 compatible = "samsung,s3c2440-i2c";
 570                 reg = <0x12C70000 0x100>;
 571                 interrupts = <0 57 0>;
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 clocks = <&clock CLK_I2C1>;
 575                 clock-names = "i2c";
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&i2c1_bus>;
 578                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 579                 status = "disabled";
 580         };
 581
 582         i2c_2: i2c@12C80000 {
 583                 compatible = "samsung,s3c2440-i2c";
 584                 reg = <0x12C80000 0x100>;
 585                 interrupts = <0 58 0>;
 586                 #address-cells = <1>;
 587                 #size-cells = <0>;
 588                 clocks = <&clock CLK_I2C2>;
 589                 clock-names = "i2c";
 590                 pinctrl-names = "default";
 591                 pinctrl-0 = <&i2c2_bus>;
 592                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 593                 status = "disabled";
 594         };
 595
 596         i2c_3: i2c@12C90000 {
 597                 compatible = "samsung,s3c2440-i2c";
 598                 reg = <0x12C90000 0x100>;
 599                 interrupts = <0 59 0>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 clocks = <&clock CLK_I2C3>;
 603                 clock-names = "i2c";
 604                 pinctrl-names = "default";
 605                 pinctrl-0 = <&i2c3_bus>;
 606                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 607                 status = "disabled";
 608         };
 609
 610         hsi2c_4: i2c@12CA0000 {
 611                 compatible = "samsung,exynos5-hsi2c";
 612                 reg = <0x12CA0000 0x1000>;
 613                 interrupts = <0 60 0>;
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616                 pinctrl-names = "default";
 617                 pinctrl-0 = <&i2c4_hs_bus>;
 618                 clocks = <&clock CLK_USI0>;
 619                 clock-names = "hsi2c";
 620                 status = "disabled";
 621         };
 622
 623         hsi2c_5: i2c@12CB0000 {
 624                 compatible = "samsung,exynos5-hsi2c";
 625                 reg = <0x12CB0000 0x1000>;
 626                 interrupts = <0 61 0>;
 627                 #address-cells = <1>;
 628                 #size-cells = <0>;
 629                 pinctrl-names = "default";
 630                 pinctrl-0 = <&i2c5_hs_bus>;
 631                 clocks = <&clock CLK_USI1>;
 632                 clock-names = "hsi2c";
 633                 status = "disabled";
 634         };
 635
 636         hsi2c_6: i2c@12CC0000 {
 637                 compatible = "samsung,exynos5-hsi2c";
 638                 reg = <0x12CC0000 0x1000>;
 639                 interrupts = <0 62 0>;
 640                 #address-cells = <1>;
 641                 #size-cells = <0>;
 642                 pinctrl-names = "default";
 643                 pinctrl-0 = <&i2c6_hs_bus>;
 644                 clocks = <&clock CLK_USI2>;
 645                 clock-names = "hsi2c";
 646                 status = "disabled";
 647         };
 648
 649         hsi2c_7: i2c@12CD0000 {
 650                 compatible = "samsung,exynos5-hsi2c";
 651                 reg = <0x12CD0000 0x1000>;
 652                 interrupts = <0 63 0>;
 653                 #address-cells = <1>;
 654                 #size-cells = <0>;
 655                 pinctrl-names = "default";
 656                 pinctrl-0 = <&i2c7_hs_bus>;
 657                 clocks = <&clock CLK_USI3>;
 658                 clock-names = "hsi2c";
 659                 status = "disabled";
 660         };
 661
 662         hsi2c_8: i2c@12E00000 {
 663                 compatible = "samsung,exynos5-hsi2c";
 664                 reg = <0x12E00000 0x1000>;
 665                 interrupts = <0 87 0>;
 666                 #address-cells = <1>;
 667                 #size-cells = <0>;
 668                 pinctrl-names = "default";
 669                 pinctrl-0 = <&i2c8_hs_bus>;
 670                 clocks = <&clock CLK_USI4>;
 671                 clock-names = "hsi2c";
 672                 status = "disabled";
 673         };
 674
 675         hsi2c_9: i2c@12E10000 {
 676                 compatible = "samsung,exynos5-hsi2c";
 677                 reg = <0x12E10000 0x1000>;
 678                 interrupts = <0 88 0>;
 679                 #address-cells = <1>;
 680                 #size-cells = <0>;
 681                 pinctrl-names = "default";
 682                 pinctrl-0 = <&i2c9_hs_bus>;
 683                 clocks = <&clock CLK_USI5>;
 684                 clock-names = "hsi2c";
 685                 status = "disabled";
 686         };
 687
 688         hsi2c_10: i2c@12E20000 {
 689                 compatible = "samsung,exynos5-hsi2c";
 690                 reg = <0x12E20000 0x1000>;
 691                 interrupts = <0 203 0>;
 692                 #address-cells = <1>;
 693                 #size-cells = <0>;
 694                 pinctrl-names = "default";
 695                 pinctrl-0 = <&i2c10_hs_bus>;
 696                 clocks = <&clock CLK_USI6>;
 697                 clock-names = "hsi2c";
 698                 status = "disabled";
 699         };
 700
 701         hdmi: hdmi@14530000 {
 702                 compatible = "samsung,exynos5420-hdmi";
 703                 reg = <0x14530000 0x70000>;
 704                 interrupts = <0 95 0>;
 705                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 706                          <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 707                          <&clock CLK_MOUT_HDMI>;
 708                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 709                         "sclk_hdmiphy", "mout_hdmi";
 710                 phy = <&hdmiphy>;
 711                 samsung,syscon-phandle = <&pmu_system_controller>;
 712                 status = "disabled";
 713         };
 714
 715         hdmiphy: hdmiphy@145D0000 {
 716                 reg = <0x145D0000 0x20>;
 717         };
 718
 719         mixer: mixer@14450000 {
 720                 compatible = "samsung,exynos5420-mixer";
 721                 reg = <0x14450000 0x10000>;
 722                 interrupts = <0 94 0>;
 723                 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
 724                 clock-names = "mixer", "sclk_hdmi";
 725         };
 726
 727         gsc_0: video-scaler@13e00000 {
 728                 compatible = "samsung,exynos5-gsc";
 729                 reg = <0x13e00000 0x1000>;
 730                 interrupts = <0 85 0>;
 731                 clocks = <&clock CLK_GSCL0>;
 732                 clock-names = "gscl";
 733                 samsung,power-domain = <&gsc_pd>;
 734         };
 735
 736         gsc_1: video-scaler@13e10000 {
 737                 compatible = "samsung,exynos5-gsc";
 738                 reg = <0x13e10000 0x1000>;
 739                 interrupts = <0 86 0>;
 740                 clocks = <&clock CLK_GSCL1>;
 741                 clock-names = "gscl";
 742                 samsung,power-domain = <&gsc_pd>;
 743         };
 744
 745         pmu_system_controller: system-controller@10040000 {
 746                 compatible = "samsung,exynos5420-pmu", "syscon";
 747                 reg = <0x10040000 0x5000>;
 748                 clock-names = "clkout16";
 749                 clocks = <&clock CLK_FIN_PLL>;
 750                 #clock-cells = <1>;
 751         };
 752
 753         sysreg_system_controller: syscon@10050000 {
 754                 compatible = "samsung,exynos5-sysreg", "syscon";
 755                 reg = <0x10050000 0x5000>;
 756         };
 757
 758         tmu_cpu0: tmu@10060000 {
 759                 compatible = "samsung,exynos5420-tmu";
 760                 reg = <0x10060000 0x100>;
 761                 interrupts = <0 65 0>;
 762                 clocks = <&clock CLK_TMU>;
 763                 clock-names = "tmu_apbif";
 764         };
 765
 766         tmu_cpu1: tmu@10064000 {
 767                 compatible = "samsung,exynos5420-tmu";
 768                 reg = <0x10064000 0x100>;
 769                 interrupts = <0 183 0>;
 770                 clocks = <&clock CLK_TMU>;
 771                 clock-names = "tmu_apbif";
 772         };
 773
 774         tmu_cpu2: tmu@10068000 {
 775                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 776                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 777                 interrupts = <0 184 0>;
 778                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 779                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 780         };
 781
 782         tmu_cpu3: tmu@1006c000 {
 783                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 784                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 785                 interrupts = <0 185 0>;
 786                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 787                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 788         };
 789
 790         tmu_gpu: tmu@100a0000 {
 791                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 792                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 793                 interrupts = <0 215 0>;
 794                 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 795                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 796         };
 797
 798         watchdog: watchdog@101D0000 {
 799                 compatible = "samsung,exynos5420-wdt";
 800                 reg = <0x101D0000 0x100>;
 801                 interrupts = <0 42 0>;
 802                 clocks = <&clock CLK_WDT>;
 803                 clock-names = "watchdog";
 804                 samsung,syscon-phandle = <&pmu_system_controller>;
 805         };
 806
 807         sss: sss@10830000 {
 808                 compatible = "samsung,exynos4210-secss";
 809                 reg = <0x10830000 0x10000>;
 810                 interrupts = <0 112 0>;
 811                 clocks = <&clock CLK_SSS>;
 812                 clock-names = "secss";
 813         };
 814
 815         usbdrd3_0: usb@12000000 {
 816                 compatible = "samsung,exynos5250-dwusb3";
 817                 clocks = <&clock CLK_USBD300>;
 818                 clock-names = "usbdrd30";
 819                 #address-cells = <1>;
 820                 #size-cells = <1>;
 821                 ranges;
 822
 823                 usbdrd_dwc3_0: dwc3 {
 824                         compatible = "snps,dwc3";
 825                         reg = <0x12000000 0x10000>;
 826                         interrupts = <0 72 0>;
 827                         phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
 828                         phy-names = "usb2-phy", "usb3-phy";
 829                 };
 830         };
 831
 832         usbdrd_phy0: phy@12100000 {
 833                 compatible = "samsung,exynos5420-usbdrd-phy";
 834                 reg = <0x12100000 0x100>;
 835                 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 836                 clock-names = "phy", "ref";
 837                 samsung,pmu-syscon = <&pmu_system_controller>;
 838                 #phy-cells = <1>;
 839         };
 840
 841         usbdrd3_1: usb@12400000 {
 842                 compatible = "samsung,exynos5250-dwusb3";
 843                 clocks = <&clock CLK_USBD301>;
 844                 clock-names = "usbdrd30";
 845                 #address-cells = <1>;
 846                 #size-cells = <1>;
 847                 ranges;
 848
 849                 usbdrd_dwc3_1: dwc3 {
 850                         compatible = "snps,dwc3";
 851                         reg = <0x12400000 0x10000>;
 852                         interrupts = <0 73 0>;
 853                         phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
 854                         phy-names = "usb2-phy", "usb3-phy";
 855                 };
 856         };
 857
 858         usbdrd_phy1: phy@12500000 {
 859                 compatible = "samsung,exynos5420-usbdrd-phy";
 860                 reg = <0x12500000 0x100>;
 861                 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 862                 clock-names = "phy", "ref";
 863                 samsung,pmu-syscon = <&pmu_system_controller>;
 864                 #phy-cells = <1>;
 865         };
 866
 867         usbhost2: usb@12110000 {
 868                 compatible = "samsung,exynos4210-ehci";
 869                 reg = <0x12110000 0x100>;
 870                 interrupts = <0 71 0>;
 871
 872                 clocks = <&clock CLK_USBH20>;
 873                 clock-names = "usbhost";
 874                 #address-cells = <1>;
 875                 #size-cells = <0>;
 876                 port@0 {
 877                         reg = <0>;
 878                         phys = <&usb2_phy 1>;
 879                 };
 880         };
 881
 882         usbhost1: usb@12120000 {
 883                 compatible = "samsung,exynos4210-ohci";
 884                 reg = <0x12120000 0x100>;
 885                 interrupts = <0 71 0>;
 886
 887                 clocks = <&clock CLK_USBH20>;
 888                 clock-names = "usbhost";
 889                 #address-cells = <1>;
 890                 #size-cells = <0>;
 891                 port@0 {
 892                         reg = <0>;
 893                         phys = <&usb2_phy 1>;
 894                 };
 895         };
 896
 897         usb2_phy: phy@12130000 {
 898                 compatible = "samsung,exynos5250-usb2-phy";
 899                 reg = <0x12130000 0x100>;
 900                 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
 901                 clock-names = "phy", "ref";
 902                 #phy-cells = <1>;
 903                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 904                 samsung,pmureg-phandle = <&pmu_system_controller>;
 905         };
 906 };