arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx53-pinfunc.h"
  15 #include <dt-bindings/clock/imx5-clock.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/input/input.h>
  18 #include <dt-bindings/interrupt-controller/irq.h>
  19
  20 / {
  21         aliases {
  22                 ethernet0 = &fec;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 gpio5 = &gpio6;
  29                 gpio6 = &gpio7;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 i2c2 = &i2c3;
  33                 mmc0 = &esdhc1;
  34                 mmc1 = &esdhc2;
  35                 mmc2 = &esdhc3;
  36                 mmc3 = &esdhc4;
  37                 serial0 = &uart1;
  38                 serial1 = &uart2;
  39                 serial2 = &uart3;
  40                 serial3 = &uart4;
  41                 serial4 = &uart5;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &cspi;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 cpu0: cpu@0 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a8";
  53                         reg = <0x0>;
  54                         clocks = <&clks IMX5_CLK_ARM>;
  55                         clock-latency = <61036>;
  56                         voltage-tolerance = <5>;
  57                         operating-points = <
  58                                 /* kHz */
  59                                  166666  850000
  60                                  400000  900000
  61                                  800000 1050000
  62                                 1000000 1200000
  63                                 1200000 1300000
  64                         >;
  65                 };
  66         };
  67
  68         display-subsystem {
  69                 compatible = "fsl,imx-display-subsystem";
  70                 ports = <&ipu_di0>, <&ipu_di1>;
  71         };
  72
  73         tzic: tz-interrupt-controller@0fffc000 {
  74                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  75                 interrupt-controller;
  76                 #interrupt-cells = <1>;
  77                 reg = <0x0fffc000 0x4000>;
  78         };
  79
  80         clocks {
  81                 #address-cells = <1>;
  82                 #size-cells = <0>;
  83
  84                 ckil {
  85                         compatible = "fsl,imx-ckil", "fixed-clock";
  86                         #clock-cells = <0>;
  87                         clock-frequency = <32768>;
  88                 };
  89
  90                 ckih1 {
  91                         compatible = "fsl,imx-ckih1", "fixed-clock";
  92                         #clock-cells = <0>;
  93                         clock-frequency = <22579200>;
  94                 };
  95
  96                 ckih2 {
  97                         compatible = "fsl,imx-ckih2", "fixed-clock";
  98                         #clock-cells = <0>;
  99                         clock-frequency = <0>;
 100                 };
 101
 102                 osc {
 103                         compatible = "fsl,imx-osc", "fixed-clock";
 104                         #clock-cells = <0>;
 105                         clock-frequency = <24000000>;
 106                 };
 107         };
 108
 109         soc {
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 compatible = "simple-bus";
 113                 interrupt-parent = <&tzic>;
 114                 ranges;
 115
 116                 sata: sata@10000000 {
 117                         compatible = "fsl,imx53-ahci";
 118                         reg = <0x10000000 0x1000>;
 119                         interrupts = <28>;
 120                         clocks = <&clks IMX5_CLK_SATA_GATE>,
 121                                  <&clks IMX5_CLK_SATA_REF>,
 122                                  <&clks IMX5_CLK_AHB>;
 123                         clock-names = "sata", "sata_ref", "ahb";
 124                         status = "disabled";
 125                 };
 126
 127                 ipu: ipu@18000000 {
 128                         #address-cells = <1>;
 129                         #size-cells = <0>;
 130                         compatible = "fsl,imx53-ipu";
 131                         reg = <0x18000000 0x08000000>;
 132                         interrupts = <11 10>;
 133                         clocks = <&clks IMX5_CLK_IPU_GATE>,
 134                                  <&clks IMX5_CLK_IPU_DI0_GATE>,
 135                                  <&clks IMX5_CLK_IPU_DI1_GATE>;
 136                         clock-names = "bus", "di0", "di1";
 137                         resets = <&src 2>;
 138
 139                         ipu_csi0: port@0 {
 140                                 reg = <0>;
 141                         };
 142
 143                         ipu_csi1: port@1 {
 144                                 reg = <1>;
 145                         };
 146
 147                         ipu_di0: port@2 {
 148                                 #address-cells = <1>;
 149                                 #size-cells = <0>;
 150                                 reg = <2>;
 151
 152                                 ipu_di0_disp0: endpoint@0 {
 153                                         reg = <0>;
 154                                 };
 155
 156                                 ipu_di0_lvds0: endpoint@1 {
 157                                         reg = <1>;
 158                                         remote-endpoint = <&lvds0_in>;
 159                                 };
 160                         };
 161
 162                         ipu_di1: port@3 {
 163                                 #address-cells = <1>;
 164                                 #size-cells = <0>;
 165                                 reg = <3>;
 166
 167                                 ipu_di1_disp1: endpoint@0 {
 168                                         reg = <0>;
 169                                 };
 170
 171                                 ipu_di1_lvds1: endpoint@1 {
 172                                         reg = <1>;
 173                                         remote-endpoint = <&lvds1_in>;
 174                                 };
 175
 176                                 ipu_di1_tve: endpoint@2 {
 177                                         reg = <2>;
 178                                         remote-endpoint = <&tve_in>;
 179                                 };
 180                         };
 181                 };
 182
 183                 aips@50000000 { /* AIPS1 */
 184                         compatible = "fsl,aips-bus", "simple-bus";
 185                         #address-cells = <1>;
 186                         #size-cells = <1>;
 187                         reg = <0x50000000 0x10000000>;
 188                         ranges;
 189
 190                         spba@50000000 {
 191                                 compatible = "fsl,spba-bus", "simple-bus";
 192                                 #address-cells = <1>;
 193                                 #size-cells = <1>;
 194                                 reg = <0x50000000 0x40000>;
 195                                 ranges;
 196
 197                                 esdhc1: esdhc@50004000 {
 198                                         compatible = "fsl,imx53-esdhc";
 199                                         reg = <0x50004000 0x4000>;
 200                                         interrupts = <1>;
 201                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
 202                                                  <&clks IMX5_CLK_DUMMY>,
 203                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
 204                                         clock-names = "ipg", "ahb", "per";
 205                                         bus-width = <4>;
 206                                         status = "disabled";
 207                                 };
 208
 209                                 esdhc2: esdhc@50008000 {
 210                                         compatible = "fsl,imx53-esdhc";
 211                                         reg = <0x50008000 0x4000>;
 212                                         interrupts = <2>;
 213                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
 214                                                  <&clks IMX5_CLK_DUMMY>,
 215                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
 216                                         clock-names = "ipg", "ahb", "per";
 217                                         bus-width = <4>;
 218                                         status = "disabled";
 219                                 };
 220
 221                                 uart3: serial@5000c000 {
 222                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 223                                         reg = <0x5000c000 0x4000>;
 224                                         interrupts = <33>;
 225                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
 226                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
 227                                         clock-names = "ipg", "per";
 228                                         dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
 229                                         dma-names = "rx", "tx";
 230                                         status = "disabled";
 231                                 };
 232
 233                                 ecspi1: ecspi@50010000 {
 234                                         #address-cells = <1>;
 235                                         #size-cells = <0>;
 236                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 237                                         reg = <0x50010000 0x4000>;
 238                                         interrupts = <36>;
 239                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
 240                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
 241                                         clock-names = "ipg", "per";
 242                                         status = "disabled";
 243                                 };
 244
 245                                 ssi2: ssi@50014000 {
 246                                         #sound-dai-cells = <0>;
 247                                         compatible = "fsl,imx53-ssi",
 248                                                         "fsl,imx51-ssi",
 249                                                         "fsl,imx21-ssi";
 250                                         reg = <0x50014000 0x4000>;
 251                                         interrupts = <30>;
 252                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
 253                                                  <&clks IMX5_CLK_SSI2_ROOT_GATE>;
 254                                         clock-names = "ipg", "baud";
 255                                         dmas = <&sdma 24 1 0>,
 256                                                <&sdma 25 1 0>;
 257                                         dma-names = "rx", "tx";
 258                                         fsl,fifo-depth = <15>;
 259                                         status = "disabled";
 260                                 };
 261
 262                                 esdhc3: esdhc@50020000 {
 263                                         compatible = "fsl,imx53-esdhc";
 264                                         reg = <0x50020000 0x4000>;
 265                                         interrupts = <3>;
 266                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 267                                                  <&clks IMX5_CLK_DUMMY>,
 268                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 269                                         clock-names = "ipg", "ahb", "per";
 270                                         bus-width = <4>;
 271                                         status = "disabled";
 272                                 };
 273
 274                                 esdhc4: esdhc@50024000 {
 275                                         compatible = "fsl,imx53-esdhc";
 276                                         reg = <0x50024000 0x4000>;
 277                                         interrupts = <4>;
 278                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 279                                                  <&clks IMX5_CLK_DUMMY>,
 280                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 281                                         clock-names = "ipg", "ahb", "per";
 282                                         bus-width = <4>;
 283                                         status = "disabled";
 284                                 };
 285                         };
 286
 287                         aipstz1: bridge@53f00000 {
 288                                 compatible = "fsl,imx53-aipstz";
 289                                 reg = <0x53f00000 0x60>;
 290                         };
 291
 292                         usbphy0: usbphy@0 {
 293                                 compatible = "usb-nop-xceiv";
 294                                 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
 295                                 clock-names = "main_clk";
 296                                 status = "okay";
 297                         };
 298
 299                         usbphy1: usbphy@1 {
 300                                 compatible = "usb-nop-xceiv";
 301                                 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
 302                                 clock-names = "main_clk";
 303                                 status = "okay";
 304                         };
 305
 306                         usbotg: usb@53f80000 {
 307                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 308                                 reg = <0x53f80000 0x0200>;
 309                                 interrupts = <18>;
 310                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 311                                 fsl,usbmisc = <&usbmisc 0>;
 312                                 fsl,usbphy = <&usbphy0>;
 313                                 status = "disabled";
 314                         };
 315
 316                         usbh1: usb@53f80200 {
 317                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 318                                 reg = <0x53f80200 0x0200>;
 319                                 interrupts = <14>;
 320                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 321                                 fsl,usbmisc = <&usbmisc 1>;
 322                                 fsl,usbphy = <&usbphy1>;
 323                                 dr_mode = "host";
 324                                 status = "disabled";
 325                         };
 326
 327                         usbh2: usb@53f80400 {
 328                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 329                                 reg = <0x53f80400 0x0200>;
 330                                 interrupts = <16>;
 331                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 332                                 fsl,usbmisc = <&usbmisc 2>;
 333                                 dr_mode = "host";
 334                                 status = "disabled";
 335                         };
 336
 337                         usbh3: usb@53f80600 {
 338                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 339                                 reg = <0x53f80600 0x0200>;
 340                                 interrupts = <17>;
 341                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 342                                 fsl,usbmisc = <&usbmisc 3>;
 343                                 dr_mode = "host";
 344                                 status = "disabled";
 345                         };
 346
 347                         usbmisc: usbmisc@53f80800 {
 348                                 #index-cells = <1>;
 349                                 compatible = "fsl,imx53-usbmisc";
 350                                 reg = <0x53f80800 0x200>;
 351                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 352                         };
 353
 354                         gpio1: gpio@53f84000 {
 355                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 356                                 reg = <0x53f84000 0x4000>;
 357                                 interrupts = <50 51>;
 358                                 gpio-controller;
 359                                 #gpio-cells = <2>;
 360                                 interrupt-controller;
 361                                 #interrupt-cells = <2>;
 362                         };
 363
 364                         gpio2: gpio@53f88000 {
 365                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 366                                 reg = <0x53f88000 0x4000>;
 367                                 interrupts = <52 53>;
 368                                 gpio-controller;
 369                                 #gpio-cells = <2>;
 370                                 interrupt-controller;
 371                                 #interrupt-cells = <2>;
 372                         };
 373
 374                         gpio3: gpio@53f8c000 {
 375                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 376                                 reg = <0x53f8c000 0x4000>;
 377                                 interrupts = <54 55>;
 378                                 gpio-controller;
 379                                 #gpio-cells = <2>;
 380                                 interrupt-controller;
 381                                 #interrupt-cells = <2>;
 382                         };
 383
 384                         gpio4: gpio@53f90000 {
 385                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 386                                 reg = <0x53f90000 0x4000>;
 387                                 interrupts = <56 57>;
 388                                 gpio-controller;
 389                                 #gpio-cells = <2>;
 390                                 interrupt-controller;
 391                                 #interrupt-cells = <2>;
 392                         };
 393
 394                         kpp: kpp@53f94000 {
 395                                 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
 396                                 reg = <0x53f94000 0x4000>;
 397                                 interrupts = <60>;
 398                                 clocks = <&clks IMX5_CLK_DUMMY>;
 399                                 status = "disabled";
 400                         };
 401
 402                         wdog1: wdog@53f98000 {
 403                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 404                                 reg = <0x53f98000 0x4000>;
 405                                 interrupts = <58>;
 406                                 clocks = <&clks IMX5_CLK_DUMMY>;
 407                         };
 408
 409                         wdog2: wdog@53f9c000 {
 410                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 411                                 reg = <0x53f9c000 0x4000>;
 412                                 interrupts = <59>;
 413                                 clocks = <&clks IMX5_CLK_DUMMY>;
 414                                 status = "disabled";
 415                         };
 416
 417                         gpt: timer@53fa0000 {
 418                                 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
 419                                 reg = <0x53fa0000 0x4000>;
 420                                 interrupts = <39>;
 421                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
 422                                          <&clks IMX5_CLK_GPT_HF_GATE>;
 423                                 clock-names = "ipg", "per";
 424                         };
 425
 426                         iomuxc: iomuxc@53fa8000 {
 427                                 compatible = "fsl,imx53-iomuxc";
 428                                 reg = <0x53fa8000 0x4000>;
 429                         };
 430
 431                         gpr: iomuxc-gpr@53fa8000 {
 432                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 433                                 reg = <0x53fa8000 0xc>;
 434                         };
 435
 436                         ldb: ldb@53fa8008 {
 437                                 #address-cells = <1>;
 438                                 #size-cells = <0>;
 439                                 compatible = "fsl,imx53-ldb";
 440                                 reg = <0x53fa8008 0x4>;
 441                                 gpr = <&gpr>;
 442                                 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
 443                                          <&clks IMX5_CLK_LDB_DI1_SEL>,
 444                                          <&clks IMX5_CLK_IPU_DI0_SEL>,
 445                                          <&clks IMX5_CLK_IPU_DI1_SEL>,
 446                                          <&clks IMX5_CLK_LDB_DI0_GATE>,
 447                                          <&clks IMX5_CLK_LDB_DI1_GATE>;
 448                                 clock-names = "di0_pll", "di1_pll",
 449                                               "di0_sel", "di1_sel",
 450                                               "di0", "di1";
 451                                 status = "disabled";
 452
 453                                 lvds-channel@0 {
 454                                         #address-cells = <1>;
 455                                         #size-cells = <0>;
 456                                         reg = <0>;
 457                                         status = "disabled";
 458
 459                                         port@0 {
 460                                                 reg = <0>;
 461
 462                                                 lvds0_in: endpoint {
 463                                                         remote-endpoint = <&ipu_di0_lvds0>;
 464                                                 };
 465                                         };
 466                                 };
 467
 468                                 lvds-channel@1 {
 469                                         #address-cells = <1>;
 470                                         #size-cells = <0>;
 471                                         reg = <1>;
 472                                         status = "disabled";
 473
 474                                         port@1 {
 475                                                 reg = <1>;
 476
 477                                                 lvds1_in: endpoint {
 478                                                         remote-endpoint = <&ipu_di1_lvds1>;
 479                                                 };
 480                                         };
 481                                 };
 482                         };
 483
 484                         pwm1: pwm@53fb4000 {
 485                                 #pwm-cells = <2>;
 486                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 487                                 reg = <0x53fb4000 0x4000>;
 488                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
 489                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
 490                                 clock-names = "ipg", "per";
 491                                 interrupts = <61>;
 492                         };
 493
 494                         pwm2: pwm@53fb8000 {
 495                                 #pwm-cells = <2>;
 496                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 497                                 reg = <0x53fb8000 0x4000>;
 498                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
 499                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
 500                                 clock-names = "ipg", "per";
 501                                 interrupts = <94>;
 502                         };
 503
 504                         uart1: serial@53fbc000 {
 505                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 506                                 reg = <0x53fbc000 0x4000>;
 507                                 interrupts = <31>;
 508                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
 509                                          <&clks IMX5_CLK_UART1_PER_GATE>;
 510                                 clock-names = "ipg", "per";
 511                                 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
 512                                 dma-names = "rx", "tx";
 513                                 status = "disabled";
 514                         };
 515
 516                         uart2: serial@53fc0000 {
 517                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 518                                 reg = <0x53fc0000 0x4000>;
 519                                 interrupts = <32>;
 520                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 521                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 522                                 clock-names = "ipg", "per";
 523                                 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
 524                                 dma-names = "rx", "tx";
 525                                 status = "disabled";
 526                         };
 527
 528                         can1: can@53fc8000 {
 529                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 530                                 reg = <0x53fc8000 0x4000>;
 531                                 interrupts = <82>;
 532                                 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
 533                                          <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
 534                                 clock-names = "ipg", "per";
 535                                 status = "disabled";
 536                         };
 537
 538                         can2: can@53fcc000 {
 539                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 540                                 reg = <0x53fcc000 0x4000>;
 541                                 interrupts = <83>;
 542                                 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
 543                                          <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
 544                                 clock-names = "ipg", "per";
 545                                 status = "disabled";
 546                         };
 547
 548                         src: src@53fd0000 {
 549                                 compatible = "fsl,imx53-src", "fsl,imx51-src";
 550                                 reg = <0x53fd0000 0x4000>;
 551                                 #reset-cells = <1>;
 552                         };
 553
 554                         clks: ccm@53fd4000{
 555                                 compatible = "fsl,imx53-ccm";
 556                                 reg = <0x53fd4000 0x4000>;
 557                                 interrupts = <0 71 0x04 0 72 0x04>;
 558                                 #clock-cells = <1>;
 559                         };
 560
 561                         gpio5: gpio@53fdc000 {
 562                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 563                                 reg = <0x53fdc000 0x4000>;
 564                                 interrupts = <103 104>;
 565                                 gpio-controller;
 566                                 #gpio-cells = <2>;
 567                                 interrupt-controller;
 568                                 #interrupt-cells = <2>;
 569                         };
 570
 571                         gpio6: gpio@53fe0000 {
 572                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 573                                 reg = <0x53fe0000 0x4000>;
 574                                 interrupts = <105 106>;
 575                                 gpio-controller;
 576                                 #gpio-cells = <2>;
 577                                 interrupt-controller;
 578                                 #interrupt-cells = <2>;
 579                         };
 580
 581                         gpio7: gpio@53fe4000 {
 582                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 583                                 reg = <0x53fe4000 0x4000>;
 584                                 interrupts = <107 108>;
 585                                 gpio-controller;
 586                                 #gpio-cells = <2>;
 587                                 interrupt-controller;
 588                                 #interrupt-cells = <2>;
 589                         };
 590
 591                         i2c3: i2c@53fec000 {
 592                                 #address-cells = <1>;
 593                                 #size-cells = <0>;
 594                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 595                                 reg = <0x53fec000 0x4000>;
 596                                 interrupts = <64>;
 597                                 clocks = <&clks IMX5_CLK_I2C3_GATE>;
 598                                 status = "disabled";
 599                         };
 600
 601                         uart4: serial@53ff0000 {
 602                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 603                                 reg = <0x53ff0000 0x4000>;
 604                                 interrupts = <13>;
 605                                 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
 606                                          <&clks IMX5_CLK_UART4_PER_GATE>;
 607                                 clock-names = "ipg", "per";
 608                                 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
 609                                 dma-names = "rx", "tx";
 610                                 status = "disabled";
 611                         };
 612                 };
 613
 614                 aips@60000000 { /* AIPS2 */
 615                         compatible = "fsl,aips-bus", "simple-bus";
 616                         #address-cells = <1>;
 617                         #size-cells = <1>;
 618                         reg = <0x60000000 0x10000000>;
 619                         ranges;
 620
 621                         aipstz2: bridge@63f00000 {
 622                                 compatible = "fsl,imx53-aipstz";
 623                                 reg = <0x63f00000 0x60>;
 624                         };
 625
 626                         iim: iim@63f98000 {
 627                                 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
 628                                 reg = <0x63f98000 0x4000>;
 629                                 interrupts = <69>;
 630                                 clocks = <&clks IMX5_CLK_IIM_GATE>;
 631                         };
 632
 633                         uart5: serial@63f90000 {
 634                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 635                                 reg = <0x63f90000 0x4000>;
 636                                 interrupts = <86>;
 637                                 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
 638                                          <&clks IMX5_CLK_UART5_PER_GATE>;
 639                                 clock-names = "ipg", "per";
 640                                 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
 641                                 dma-names = "rx", "tx";
 642                                 status = "disabled";
 643                         };
 644
 645                         owire: owire@63fa4000 {
 646                                 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
 647                                 reg = <0x63fa4000 0x4000>;
 648                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
 649                                 status = "disabled";
 650                         };
 651
 652                         ecspi2: ecspi@63fac000 {
 653                                 #address-cells = <1>;
 654                                 #size-cells = <0>;
 655                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 656                                 reg = <0x63fac000 0x4000>;
 657                                 interrupts = <37>;
 658                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
 659                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
 660                                 clock-names = "ipg", "per";
 661                                 status = "disabled";
 662                         };
 663
 664                         sdma: sdma@63fb0000 {
 665                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 666                                 reg = <0x63fb0000 0x4000>;
 667                                 interrupts = <6>;
 668                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 669                                          <&clks IMX5_CLK_SDMA_GATE>;
 670                                 clock-names = "ipg", "ahb";
 671                                 #dma-cells = <3>;
 672                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 673                         };
 674
 675                         cspi: cspi@63fc0000 {
 676                                 #address-cells = <1>;
 677                                 #size-cells = <0>;
 678                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 679                                 reg = <0x63fc0000 0x4000>;
 680                                 interrupts = <38>;
 681                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
 682                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
 683                                 clock-names = "ipg", "per";
 684                                 status = "disabled";
 685                         };
 686
 687                         i2c2: i2c@63fc4000 {
 688                                 #address-cells = <1>;
 689                                 #size-cells = <0>;
 690                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 691                                 reg = <0x63fc4000 0x4000>;
 692                                 interrupts = <63>;
 693                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 694                                 status = "disabled";
 695                         };
 696
 697                         i2c1: i2c@63fc8000 {
 698                                 #address-cells = <1>;
 699                                 #size-cells = <0>;
 700                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 701                                 reg = <0x63fc8000 0x4000>;
 702                                 interrupts = <62>;
 703                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 704                                 status = "disabled";
 705                         };
 706
 707                         ssi1: ssi@63fcc000 {
 708                                 #sound-dai-cells = <0>;
 709                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
 710                                                 "fsl,imx21-ssi";
 711                                 reg = <0x63fcc000 0x4000>;
 712                                 interrupts = <29>;
 713                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
 714                                          <&clks IMX5_CLK_SSI1_ROOT_GATE>;
 715                                 clock-names = "ipg", "baud";
 716                                 dmas = <&sdma 28 0 0>,
 717                                        <&sdma 29 0 0>;
 718                                 dma-names = "rx", "tx";
 719                                 fsl,fifo-depth = <15>;
 720                                 status = "disabled";
 721                         };
 722
 723                         audmux: audmux@63fd0000 {
 724                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
 725                                 reg = <0x63fd0000 0x4000>;
 726                                 status = "disabled";
 727                         };
 728
 729                         nfc: nand@63fdb000 {
 730                                 compatible = "fsl,imx53-nand";
 731                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
 732                                 interrupts = <8>;
 733                                 clocks = <&clks IMX5_CLK_NFC_GATE>;
 734                                 status = "disabled";
 735                         };
 736
 737                         ssi3: ssi@63fe8000 {
 738                                 #sound-dai-cells = <0>;
 739                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
 740                                                 "fsl,imx21-ssi";
 741                                 reg = <0x63fe8000 0x4000>;
 742                                 interrupts = <96>;
 743                                 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
 744                                          <&clks IMX5_CLK_SSI3_ROOT_GATE>;
 745                                 clock-names = "ipg", "baud";
 746                                 dmas = <&sdma 46 0 0>,
 747                                        <&sdma 47 0 0>;
 748                                 dma-names = "rx", "tx";
 749                                 fsl,fifo-depth = <15>;
 750                                 status = "disabled";
 751                         };
 752
 753                         fec: ethernet@63fec000 {
 754                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 755                                 reg = <0x63fec000 0x4000>;
 756                                 interrupts = <87>;
 757                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 758                                          <&clks IMX5_CLK_FEC_GATE>,
 759                                          <&clks IMX5_CLK_FEC_GATE>;
 760                                 clock-names = "ipg", "ahb", "ptp";
 761                                 status = "disabled";
 762                         };
 763
 764                         tve: tve@63ff0000 {
 765                                 compatible = "fsl,imx53-tve";
 766                                 reg = <0x63ff0000 0x1000>;
 767                                 interrupts = <92>;
 768                                 clocks = <&clks IMX5_CLK_TVE_GATE>,
 769                                          <&clks IMX5_CLK_IPU_DI1_SEL>;
 770                                 clock-names = "tve", "di_sel";
 771                                 status = "disabled";
 772
 773                                 port {
 774                                         tve_in: endpoint {
 775                                                 remote-endpoint = <&ipu_di1_tve>;
 776                                         };
 777                                 };
 778                         };
 779
 780                         vpu: vpu@63ff4000 {
 781                                 compatible = "fsl,imx53-vpu", "cnm,coda7541";
 782                                 reg = <0x63ff4000 0x1000>;
 783                                 interrupts = <9>;
 784                                 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
 785                                          <&clks IMX5_CLK_VPU_GATE>;
 786                                 clock-names = "per", "ahb";
 787                                 resets = <&src 1>;
 788                                 iram = <&ocram>;
 789                         };
 790
 791                         sahara: crypto@63ff8000 {
 792                                 compatible = "fsl,imx53-sahara";
 793                                 reg = <0x63ff8000 0x4000>;
 794                                 interrupts = <19 20>;
 795                                 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
 796                                          <&clks IMX5_CLK_SAHARA_IPG_GATE>;
 797                                 clock-names = "ipg", "ahb";
 798                         };
 799                 };
 800
 801                 ocram: sram@f8000000 {
 802                         compatible = "mmio-sram";
 803                         reg = <0xf8000000 0x20000>;
 804                         clocks = <&clks IMX5_CLK_OCRAM>;
 805                 };
 806
 807                 pmu {
 808                         compatible = "arm,cortex-a8-pmu";
 809                         interrupts = <77>;
 810                 };
 811         };
 812 };