arch/arm/boot/dts/imx6q-cm-fx6.dts

   1 /*
   2  * Copyright 2013 CompuLab Ltd.
   3  *
   4  * Author: Valentin Raevsky <valentin@compulab.co.il>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License
  13  *     version 2 as published by the Free Software Foundation.
  14  *
  15  *     This file is distributed in the hope that it will be useful
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 /dts-v1/;
  45 #include <dt-bindings/gpio/gpio.h>
  46 #include "imx6q.dtsi"
  47
  48 / {
  49         model = "CompuLab CM-FX6";
  50         compatible = "compulab,cm-fx6", "fsl,imx6q";
  51
  52         memory {
  53                 reg = <0x10000000 0x80000000>;
  54         };
  55
  56         leds {
  57                 compatible = "gpio-leds";
  58
  59                 heartbeat-led {
  60                         label = "Heartbeat";
  61                         gpios = <&gpio2 31 0>;
  62                         linux,default-trigger = "heartbeat";
  63                 };
  64         };
  65
  66         reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio {
  67                 compatible = "regulator-fixed";
  68                 regulator-name = "regulator-pcie-power-on-gpio";
  69                 regulator-min-microvolt = <3300000>;
  70                 regulator-max-microvolt = <3300000>;
  71                 gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
  72                 enable-active-high;
  73         };
  74
  75         reg_usb_h1_vbus: usb_h1_vbus {
  76                 compatible = "regulator-fixed";
  77                 regulator-name = "usb_h1_vbus";
  78                 regulator-min-microvolt = <5000000>;
  79                 regulator-max-microvolt = <5000000>;
  80                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
  81                 enable-active-high;
  82         };
  83
  84         reg_usb_otg_vbus: usb_otg_vbus {
  85                 compatible = "regulator-fixed";
  86                 regulator-name = "usb_otg_vbus";
  87                 regulator-min-microvolt = <5000000>;
  88                 regulator-max-microvolt = <5000000>;
  89                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  90                 enable-active-high;
  91         };
  92 };
  93
  94 &cpu0 {
  95         /*
  96          * Although the imx6q fuse indicates that 1.2GHz operation is possible,
  97          * the module behaves unstable at this frequency. Hence, remove the
  98          * 1.2GHz operation point here.
  99          */
 100         operating-points = <
 101                 /* kHz  uV */
 102                 996000  1250000
 103                 852000  1250000
 104                 792000  1175000
 105                 396000  975000
 106         >;
 107         fsl,soc-operating-points = <
 108                 /* ARM kHz      SOC-PU uV */
 109                 996000          1250000
 110                 852000          1250000
 111                 792000          1175000
 112                 396000          1175000
 113         >;
 114 };
 115
 116 &ecspi1 {
 117         fsl,spi-num-chipselects = <2>;
 118         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&pinctrl_ecspi1>;
 121         status = "okay";
 122
 123         m25p80@0 {
 124                 #address-cells = <1>;
 125                 #size-cells = <1>;
 126                 compatible = "st,m25p", "jedec,spi-nor";
 127                 spi-max-frequency = <20000000>;
 128                 reg = <0>;
 129         };
 130 };
 131
 132 &fec {
 133         pinctrl-names = "default";
 134         pinctrl-0 = <&pinctrl_enet>;
 135         phy-mode = "rgmii";
 136         status = "okay";
 137 };
 138
 139 &gpmi {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_gpmi_nand>;
 142         status = "okay";
 143 };
 144
 145 &i2c3 {
 146         pinctrl-names = "default";
 147         pinctrl-0 = <&pinctrl_i2c3>;
 148         status = "okay";
 149         clock-frequency = <100000>;
 150
 151         eeprom@50 {
 152                 compatible = "at24,24c02";
 153                 reg = <0x50>;
 154                 pagesize = <16>;
 155         };
 156 };
 157
 158 &iomuxc {
 159         pinctrl_ecspi1: ecspi1grp {
 160                 fsl,pins = <
 161                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
 162                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
 163                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
 164                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30  0x100b1
 165                         MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x100b1
 166                 >;
 167         };
 168
 169         pinctrl_enet: enetgrp {
 170                 fsl,pins = <
 171                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 172                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 173                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 174                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 175                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 176                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 177                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 178                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 179                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 180                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 181                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 182                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 183                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 184                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 185                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 186                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 187                 >;
 188         };
 189
 190         pinctrl_gpmi_nand: gpminandgrp {
 191                 fsl,pins = <
 192                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 193                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 194                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 195                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 196                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 197                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 198                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 199                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 200                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 201                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 202                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 203                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 204                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 205                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 206                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 207                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 208                         MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 209                 >;
 210         };
 211
 212         pinctrl_i2c3: i2c3grp {
 213                 fsl,pins = <
 214                         MX6QDL_PAD_GPIO_3__I2C3_SCL     0x4001b8b1
 215                         MX6QDL_PAD_GPIO_6__I2C3_SDA     0x4001b8b1
 216                 >;
 217         };
 218
 219         pinctrl_pcie: pciegrp {
 220                 fsl,pins = <
 221                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 222                         MX6QDL_PAD_EIM_CS1__GPIO2_IO24  0x1b0b1
 223                 >;
 224         };
 225
 226         pinctrl_uart4: uart4grp {
 227                 fsl,pins = <
 228                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 229                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 230                 >;
 231         };
 232
 233         pinctrl_usbh1: usbh1grp {
 234                 fsl,pins = <
 235                         MX6QDL_PAD_SD3_RST__GPIO7_IO08  0x1b0b1
 236                 >;
 237         };
 238
 239         pinctrl_usbotg: usbotggrp {
 240                 fsl,pins = <
 241                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 242                         MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x130b0
 243                 >;
 244         };
 245 };
 246
 247 &pcie {
 248         pinctrl-names = "default";
 249         pinctrl-0 = <&pinctrl_pcie>;
 250         reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
 251         vdd-supply = <&reg_pcie_power_on_gpio>;
 252         status = "okay";
 253 };
 254
 255 &sata {
 256         status = "okay";
 257 };
 258
 259 &snvs_poweroff {
 260         status = "okay";
 261 };
 262
 263 &uart4 {
 264         pinctrl-names = "default";
 265         pinctrl-0 = <&pinctrl_uart4>;
 266         status = "okay";
 267 };
 268
 269 &usbh1 {
 270         vbus-supply = <&reg_usb_h1_vbus>;
 271         pinctrl-names = "default";
 272         pinctrl-0 = <&pinctrl_usbh1>;
 273         status = "okay";
 274 };
 275
 276 &usbotg {
 277         vbus-supply = <&reg_usb_otg_vbus>;
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_usbotg>;
 280         dr_mode = "otg";
 281         status = "okay";
 282 };